* [PATCH] wext: let get_wireless_stats() sleep
From: Johannes Berg @ 2009-10-05 9:15 UTC (permalink / raw)
To: John Linville; +Cc: Miles Lane, linux-wireless, netdev
A number of drivers (recently including cfg80211-based ones)
assume that all wireless handlers, including statistics, can
sleep and they often also implicitly assume that the rtnl is
held around their invocation. This is almost always true now
except when reading from sysfs:
BUG: sleeping function called from invalid context at kernel/mutex.c:280
in_atomic(): 1, irqs_disabled(): 0, pid: 10450, name: head
2 locks held by head/10450:
#0: (&buffer->mutex){+.+.+.}, at: [<c10ceb99>] sysfs_read_file+0x24/0xf4
#1: (dev_base_lock){++.?..}, at: [<c12844ee>] wireless_show+0x1a/0x4c
Pid: 10450, comm: head Not tainted 2.6.32-rc3 #1
Call Trace:
[<c102301c>] __might_sleep+0xf0/0xf7
[<c1324355>] mutex_lock_nested+0x1a/0x33
[<f8cea53b>] wdev_lock+0xd/0xf [cfg80211]
[<f8cea58f>] cfg80211_wireless_stats+0x45/0x12d [cfg80211]
[<c13118d6>] get_wireless_stats+0x16/0x1c
[<c12844fe>] wireless_show+0x2a/0x4c
Fix this by using the rtnl instead of dev_base_lock.
Reported-by: Miles Lane <miles.lane-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Johannes Berg <johannes-cdvu00un1VgdHxzADdlk8Q@public.gmane.org>
---
net/core/net-sysfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- wireless-testing.orig/net/core/net-sysfs.c 2009-10-05 11:09:56.000000000 +0200
+++ wireless-testing/net/core/net-sysfs.c 2009-10-05 11:10:52.000000000 +0200
@@ -366,13 +366,13 @@ static ssize_t wireless_show(struct devi
const struct iw_statistics *iw;
ssize_t ret = -EINVAL;
- read_lock(&dev_base_lock);
+ rtnl_lock();
if (dev_isalive(dev)) {
iw = get_wireless_stats(dev);
if (iw)
ret = (*format)(iw, buf);
}
- read_unlock(&dev_base_lock);
+ rtnl_unlock();
return ret;
}
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^ permalink raw reply
* [net-next-2.6 PATCH 9/9] vxge: Version update
From: Sreenivasa Honnur @ 2009-10-05 9:15 UTC (permalink / raw)
To: davem; +Cc: netdev, support
- Version Update.
Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
---
diff -urpN orig//drivers/net/vxge/vxge-version.h patch-9//drivers/net/vxge/vxge-version.h
--- orig//drivers/net/vxge/vxge-version.h 2009-10-04 22:43:59.000000000 -0700
+++ patch-9//drivers/net/vxge/vxge-version.h 2009-10-04 22:43:08.000000000 -0700
@@ -17,7 +17,7 @@
#define VXGE_VERSION_MAJOR "2"
#define VXGE_VERSION_MINOR "0"
-#define VXGE_VERSION_FIX "5"
-#define VXGE_VERSION_BUILD "18053"
+#define VXGE_VERSION_FIX "6"
+#define VXGE_VERSION_BUILD "18707"
#define VXGE_VERSION_FOR "k"
#endif
^ permalink raw reply
* Re: [net-next-2.6 PATCH 1/9] vxge: Modify __vxge_hw_device_is_privilaged() to not assume function-0 as privilaged function.
From: David Miller @ 2009-10-05 9:20 UTC (permalink / raw)
To: Sreenivasa.Honnur; +Cc: netdev, support
In-Reply-To: <Pine.GSO.4.10.10910050503530.2346-100000@guinness>
From: Sreenivasa Honnur <Sreenivasa.Honnur@neterion.com>
Date: Mon, 5 Oct 2009 05:06:06 -0400 (EDT)
> - vxge driver was assuming function-0 is always the privilaged function. Now that
> restriction has been removed any function can act as a privilaged function.
>
> - This patch modifies the __vxge_hw_device_is_privilaged routine to not assume
> function-0 as the privileged function.
>
> Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
> ---
> diff -urpN orig//drivers/net/vxge/vxge-config.c patch1//drivers/net/vxge/vxge-config.c
> --- orig//drivers/net/vxge/vxge-config.c 2009-09-03 22:39:48.000000000 -0700
> +++ patch1//drivers/net/vxge/vxge-config.c 2009-09-03 23:11:24.000000000 -0700
You can't have the double slash there in your paths, this
gets interpreted as "/drivers/net/vxge/vxge-config.c" by
all the patch applying tools.
Please "-p1" root your patches properly as described in
linux/Documentation/SubmittingPatches
You'll need to resubmit your entire patch set with this
fixed up.
Thanks.
^ permalink raw reply
* Re: [PATCH] wext: let get_wireless_stats() sleep
From: David Miller @ 2009-10-05 9:22 UTC (permalink / raw)
To: johannes-cdvu00un1VgdHxzADdlk8Q
Cc: linville-2XuSBdqkA4R54TAoqtyWWQ,
miles.lane-Re5JQEeQqe8AvxtiuMwx3w,
linux-wireless-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1254734159.22426.6.camel-YfaajirXv2244ywRPIzf9A@public.gmane.org>
From: Johannes Berg <johannes-cdvu00un1VgdHxzADdlk8Q@public.gmane.org>
Date: Mon, 05 Oct 2009 11:15:59 +0200
> A number of drivers (recently including cfg80211-based ones)
> assume that all wireless handlers, including statistics, can
> sleep and they often also implicitly assume that the rtnl is
> held around their invocation. This is almost always true now
> except when reading from sysfs:
...
> Fix this by using the rtnl instead of dev_base_lock.
>
> Reported-by: Miles Lane <miles.lane-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Johannes Berg <johannes-cdvu00un1VgdHxzADdlk8Q@public.gmane.org>
Fair enough, applied, thanks!
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^ permalink raw reply
* Re: [PATCH] TCPCT+1: initial SYN exchange with SYNACK data
From: Eric Dumazet @ 2009-10-05 9:22 UTC (permalink / raw)
To: William Allen Simpson; +Cc: David Miller, netdev
In-Reply-To: <4AC9AD14.2060500@gmail.com>
William Allen Simpson a écrit :
> This will be widely deployed. Deployment in DNS root servers is
> expected by December. It will be hammered with 600,000+ queries per
> minute. Does that impact your design expectations?
>
10.000 queries per second are challenging, definitly worth to study.
I could not find exact RFC number for this new feature.
Could you give us the up2date info ?
http://ietfreport.isoc.org/all-ids/draft-agl-tcpm-sadata-00.txt is expired.
^ permalink raw reply
* vxge: Update driver_config->vpath_per_dev for each function in probe.
From: Sreenivasa Honnur @ 2009-10-05 9:06 UTC (permalink / raw)
To: davem; +Cc: netdev, support
- Update driver_config->vpath_per_dev for each function in probe.
- vpath_per_device specifies number of vpaths supported for each function/device. The
current code was updating vpath_per_device only for physical device, however this has
to be updated for each function also in case of a MF(Multi function) device.
Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
---
diff -urpN patch1/drivers/net/vxge/vxge-main.c patch2/drivers/net/vxge/vxge-main.c
--- patch1/drivers/net/vxge/vxge-main.c 2009-09-03 22:40:14.000000000 -0700
+++ patch2/drivers/net/vxge/vxge-main.c 2009-09-04 01:18:13.000000000 -0700
@@ -4088,9 +4088,10 @@ vxge_probe(struct pci_dev *pdev, const s
driver_config->config_dev_cnt = 0;
driver_config->total_dev_cnt = 0;
driver_config->g_no_cpus = 0;
- driver_config->vpath_per_dev = max_config_vpath;
}
+ driver_config->vpath_per_dev = max_config_vpath;
+
driver_config->total_dev_cnt++;
if (++driver_config->config_dev_cnt > max_config_dev) {
ret = 0;
^ permalink raw reply
* [net-next-2.6 PATCH 4/9] vxge: Fixed crash in PAE system due to wrong typecasting.
From: Sreenivasa Honnur @ 2009-10-05 9:09 UTC (permalink / raw)
To: davem; +Cc: netdev, support
- Fix a crash in PAE system due to wrong typecasting.
- On PAE system size_t is unsigned int which is 32bit. Avoid casting
64 bit address to 32 bit
Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
---
diff -urpN patch3/drivers/net/vxge/vxge-traffic.c patch4/drivers/net/vxge/vxge-traffic.c
--- patch3/drivers/net/vxge/vxge-traffic.c 2009-09-04 01:19:23.000000000 -0700
+++ patch4/drivers/net/vxge/vxge-traffic.c 2009-09-04 01:22:35.000000000 -0700
@@ -1232,7 +1232,7 @@ void vxge_hw_fifo_txdl_post(struct __vxg
vxge_hw_channel_dtr_post(&fifo->channel, txdlh);
__vxge_hw_non_offload_db_post(fifo,
- (u64)(size_t)txdl_priv->dma_addr,
+ (u64)txdl_priv->dma_addr,
txdl_priv->frags - 1,
fifo->no_snoop_bits);
^ permalink raw reply
* [net-next-2.6 PATCH 5/9] vxge: Removed unused functions.
From: Sreenivasa Honnur @ 2009-10-05 9:10 UTC (permalink / raw)
To: davem; +Cc: netdev, support
- Removed the wrr_rebalance function
- This feature is not supported by the ASIC, hence removing the related code.
Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
---
diff -urpN patch4/drivers/net/vxge/vxge-config.c patch5/drivers/net/vxge/vxge-config.c
--- patch4/drivers/net/vxge/vxge-config.c 2009-09-04 01:21:52.000000000 -0700
+++ patch5/drivers/net/vxge/vxge-config.c 2009-09-04 01:24:25.000000000 -0700
@@ -461,209 +461,6 @@ __vxge_hw_verify_pci_e_info(struct __vxg
}
/*
- * vxge_hw_wrr_rebalance - Rebalance the RX_WRR and KDFC_WRR calandars.
- * Rebalance the RX_WRR and KDFC_WRR calandars.
- */
-static enum
-vxge_hw_status vxge_hw_wrr_rebalance(struct __vxge_hw_device *hldev)
-{
- u64 val64;
- u32 wrr_states[VXGE_HW_WEIGHTED_RR_SERVICE_STATES];
- u32 i, j, how_often = 1;
- enum vxge_hw_status status = VXGE_HW_OK;
-
- status = __vxge_hw_device_is_privilaged(hldev->host_type,
- hldev->func_id);
- if (status != VXGE_HW_OK)
- goto exit;
-
- /* Reset the priorities assigned to the WRR arbitration
- phases for the receive traffic */
- for (i = 0; i < VXGE_HW_WRR_RING_COUNT; i++)
- writeq(0, ((&hldev->mrpcim_reg->rx_w_round_robin_0) + i));
-
- /* Reset the transmit FIFO servicing calendar for FIFOs */
- for (i = 0; i < VXGE_HW_WRR_FIFO_COUNT; i++) {
- writeq(0, ((&hldev->mrpcim_reg->kdfc_w_round_robin_0) + i));
- writeq(0, ((&hldev->mrpcim_reg->kdfc_w_round_robin_20) + i));
- }
-
- /* Assign WRR priority 0 for all FIFOs */
- for (i = 1; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
- writeq(VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(0),
- ((&hldev->mrpcim_reg->kdfc_fifo_0_ctrl) + i));
-
- writeq(VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(0),
- ((&hldev->mrpcim_reg->kdfc_fifo_17_ctrl) + i));
- }
-
- /* Reset to service non-offload doorbells */
- writeq(0, &hldev->mrpcim_reg->kdfc_entry_type_sel_0);
- writeq(0, &hldev->mrpcim_reg->kdfc_entry_type_sel_1);
-
- /* Set priority 0 to all receive queues */
- writeq(0, &hldev->mrpcim_reg->rx_queue_priority_0);
- writeq(0, &hldev->mrpcim_reg->rx_queue_priority_1);
- writeq(0, &hldev->mrpcim_reg->rx_queue_priority_2);
-
- /* Initialize all the slots as unused */
- for (i = 0; i < VXGE_HW_WEIGHTED_RR_SERVICE_STATES; i++)
- wrr_states[i] = -1;
-
- /* Prepare the Fifo service states */
- for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
-
- if (!hldev->config.vp_config[i].min_bandwidth)
- continue;
-
- how_often = VXGE_HW_VPATH_BANDWIDTH_MAX /
- hldev->config.vp_config[i].min_bandwidth;
- if (how_often) {
-
- for (j = 0; j < VXGE_HW_WRR_FIFO_SERVICE_STATES;) {
- if (wrr_states[j] == -1) {
- wrr_states[j] = i;
- /* Make sure each fifo is serviced
- * atleast once */
- if (i == j)
- j += VXGE_HW_MAX_VIRTUAL_PATHS;
- else
- j += how_often;
- } else
- j++;
- }
- }
- }
-
- /* Fill the unused slots with 0 */
- for (j = 0; j < VXGE_HW_WEIGHTED_RR_SERVICE_STATES; j++) {
- if (wrr_states[j] == -1)
- wrr_states[j] = 0;
- }
-
- /* Assign WRR priority number for FIFOs */
- for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
- writeq(VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(i),
- ((&hldev->mrpcim_reg->kdfc_fifo_0_ctrl) + i));
-
- writeq(VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(i),
- ((&hldev->mrpcim_reg->kdfc_fifo_17_ctrl) + i));
- }
-
- /* Modify the servicing algorithm applied to the 3 types of doorbells.
- i.e, none-offload, message and offload */
- writeq(VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(0) |
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(0) |
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(0) |
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(0) |
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(1) |
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(0) |
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(0) |
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(0),
- &hldev->mrpcim_reg->kdfc_entry_type_sel_0);
-
- writeq(VXGE_HW_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(1),
- &hldev->mrpcim_reg->kdfc_entry_type_sel_1);
-
- for (i = 0, j = 0; i < VXGE_HW_WRR_FIFO_COUNT; i++) {
-
- val64 = VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_0(wrr_states[j++]);
- val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1(wrr_states[j++]);
- val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_2(wrr_states[j++]);
- val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_3(wrr_states[j++]);
- val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_4(wrr_states[j++]);
- val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_5(wrr_states[j++]);
- val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_6(wrr_states[j++]);
- val64 |= VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_7(wrr_states[j++]);
-
- writeq(val64, (&hldev->mrpcim_reg->kdfc_w_round_robin_0 + i));
- writeq(val64, (&hldev->mrpcim_reg->kdfc_w_round_robin_20 + i));
- }
-
- /* Set up the priorities assigned to receive queues */
- writeq(VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(0) |
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(1) |
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(2) |
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(3) |
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(4) |
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(5) |
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(6) |
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(7),
- &hldev->mrpcim_reg->rx_queue_priority_0);
-
- writeq(VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(8) |
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(9) |
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(10) |
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(11) |
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(12) |
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(13) |
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(14) |
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(15),
- &hldev->mrpcim_reg->rx_queue_priority_1);
-
- writeq(VXGE_HW_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(16),
- &hldev->mrpcim_reg->rx_queue_priority_2);
-
- /* Initialize all the slots as unused */
- for (i = 0; i < VXGE_HW_WEIGHTED_RR_SERVICE_STATES; i++)
- wrr_states[i] = -1;
-
- /* Prepare the Ring service states */
- for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
-
- if (!hldev->config.vp_config[i].min_bandwidth)
- continue;
-
- how_often = VXGE_HW_VPATH_BANDWIDTH_MAX /
- hldev->config.vp_config[i].min_bandwidth;
-
- if (how_often) {
- for (j = 0; j < VXGE_HW_WRR_RING_SERVICE_STATES;) {
- if (wrr_states[j] == -1) {
- wrr_states[j] = i;
- /* Make sure each ring is
- * serviced atleast once */
- if (i == j)
- j += VXGE_HW_MAX_VIRTUAL_PATHS;
- else
- j += how_often;
- } else
- j++;
- }
- }
- }
-
- /* Fill the unused slots with 0 */
- for (j = 0; j < VXGE_HW_WEIGHTED_RR_SERVICE_STATES; j++) {
- if (wrr_states[j] == -1)
- wrr_states[j] = 0;
- }
-
- for (i = 0, j = 0; i < VXGE_HW_WRR_RING_COUNT; i++) {
- val64 = VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(
- wrr_states[j++]);
- val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(
- wrr_states[j++]);
- val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(
- wrr_states[j++]);
- val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(
- wrr_states[j++]);
- val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(
- wrr_states[j++]);
- val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(
- wrr_states[j++]);
- val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(
- wrr_states[j++]);
- val64 |= VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(
- wrr_states[j++]);
-
- writeq(val64, ((&hldev->mrpcim_reg->rx_w_round_robin_0) + i));
- }
-exit:
- return status;
-}
-
-/*
* __vxge_hw_device_initialize
* Initialize Titan-V hardware.
*/
@@ -679,7 +476,6 @@ enum vxge_hw_status __vxge_hw_device_ini
goto exit;
}
- vxge_hw_wrr_rebalance(hldev);
exit:
return status;
}
^ permalink raw reply
* [net-next-2.6 PATCH 1/9] vxge: Modify __vxge_hw_device_is_privilaged() to not assume function-0 as privilaged function.
From: Sreenivasa Honnur @ 2009-10-05 9:06 UTC (permalink / raw)
To: davem; +Cc: netdev, support
- vxge driver was assuming function-0 is always the privilaged function. Now that
restriction has been removed any function can act as a privilaged function.
- This patch modifies the __vxge_hw_device_is_privilaged routine to not assume
function-0 as the privileged function.
Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
---
diff -urpN orig//drivers/net/vxge/vxge-config.c patch1//drivers/net/vxge/vxge-config.c
--- orig//drivers/net/vxge/vxge-config.c 2009-09-03 22:39:48.000000000 -0700
+++ patch1//drivers/net/vxge/vxge-config.c 2009-09-03 23:11:24.000000000 -0700
@@ -356,10 +356,8 @@ __vxge_hw_device_access_rights_get(u32 h
switch (host_type) {
case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
- if (func_id == 0) {
- access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
- VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
- }
+ access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
+ VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
break;
case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
@@ -382,6 +380,22 @@ __vxge_hw_device_access_rights_get(u32 h
return access_rights;
}
/*
+ * __vxge_hw_device_is_privilaged
+ * This routine checks if the device function is privilaged or not
+ */
+
+enum vxge_hw_status
+__vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
+{
+ if (__vxge_hw_device_access_rights_get(host_type,
+ func_id) &
+ VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
+ return VXGE_HW_OK;
+ else
+ return VXGE_HW_ERR_PRIVILAGED_OPEARATION;
+}
+
+/*
* __vxge_hw_device_host_info_get
* This routine returns the host type assignments
*/
@@ -446,18 +460,6 @@ __vxge_hw_verify_pci_e_info(struct __vxg
return VXGE_HW_OK;
}
-enum vxge_hw_status
-__vxge_hw_device_is_privilaged(struct __vxge_hw_device *hldev)
-{
- if ((hldev->host_type == VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION ||
- hldev->host_type == VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION ||
- hldev->host_type == VXGE_HW_NO_MR_SR_VH0_FUNCTION0) &&
- (hldev->func_id == 0))
- return VXGE_HW_OK;
- else
- return VXGE_HW_ERR_PRIVILAGED_OPEARATION;
-}
-
/*
* vxge_hw_wrr_rebalance - Rebalance the RX_WRR and KDFC_WRR calandars.
* Rebalance the RX_WRR and KDFC_WRR calandars.
@@ -470,7 +472,8 @@ vxge_hw_status vxge_hw_wrr_rebalance(str
u32 i, j, how_often = 1;
enum vxge_hw_status status = VXGE_HW_OK;
- status = __vxge_hw_device_is_privilaged(hldev);
+ status = __vxge_hw_device_is_privilaged(hldev->host_type,
+ hldev->func_id);
if (status != VXGE_HW_OK)
goto exit;
@@ -668,7 +671,8 @@ enum vxge_hw_status __vxge_hw_device_ini
{
enum vxge_hw_status status = VXGE_HW_OK;
- if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev)) {
+ if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
+ hldev->func_id)) {
/* Validate the pci-e link width and speed */
status = __vxge_hw_verify_pci_e_info(hldev);
if (status != VXGE_HW_OK)
@@ -953,7 +957,8 @@ vxge_hw_mrpcim_stats_access(struct __vxg
u64 val64;
enum vxge_hw_status status = VXGE_HW_OK;
- status = __vxge_hw_device_is_privilaged(hldev);
+ status = __vxge_hw_device_is_privilaged(hldev->host_type,
+ hldev->func_id);
if (status != VXGE_HW_OK)
goto exit;
@@ -990,7 +995,8 @@ vxge_hw_device_xmac_aggr_stats_get(struc
val64 = (u64 *)aggr_stats;
- status = __vxge_hw_device_is_privilaged(hldev);
+ status = __vxge_hw_device_is_privilaged(hldev->host_type,
+ hldev->func_id);
if (status != VXGE_HW_OK)
goto exit;
@@ -1023,7 +1029,8 @@ vxge_hw_device_xmac_port_stats_get(struc
u32 offset = 0x0;
val64 = (u64 *) port_stats;
- status = __vxge_hw_device_is_privilaged(hldev);
+ status = __vxge_hw_device_is_privilaged(hldev->host_type,
+ hldev->func_id);
if (status != VXGE_HW_OK)
goto exit;
@@ -1221,7 +1228,8 @@ enum vxge_hw_status vxge_hw_device_setpa
goto exit;
}
- status = __vxge_hw_device_is_privilaged(hldev);
+ status = __vxge_hw_device_is_privilaged(hldev->host_type,
+ hldev->func_id);
if (status != VXGE_HW_OK)
goto exit;
^ permalink raw reply
* [net-next-2.6 PATCH 2/9] vxge: Update driver_config->vpath_per_dev for each function in probe
From: Sreenivasa Honnur @ 2009-10-05 9:08 UTC (permalink / raw)
To: davem; +Cc: netdev, support
- Update driver_config->vpath_per_dev for each function in probe.
- vpath_per_device specifies number of vpaths supported for each function/device. The
current code was updating vpath_per_device only for physical device, however this has
to be updated for each function also in case of a MF(Multi function) device.
Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
---
diff -urpN patch1/drivers/net/vxge/vxge-main.c patch2/drivers/net/vxge/vxge-main.c
--- patch1/drivers/net/vxge/vxge-main.c 2009-09-03 22:40:14.000000000 -0700
+++ patch2/drivers/net/vxge/vxge-main.c 2009-09-04 01:18:13.000000000 -0700
@@ -4088,9 +4088,10 @@ vxge_probe(struct pci_dev *pdev, const s
driver_config->config_dev_cnt = 0;
driver_config->total_dev_cnt = 0;
driver_config->g_no_cpus = 0;
- driver_config->vpath_per_dev = max_config_vpath;
}
+ driver_config->vpath_per_dev = max_config_vpath;
+
driver_config->total_dev_cnt++;
if (++driver_config->config_dev_cnt > max_config_dev) {
ret = 0;
^ permalink raw reply
* [net-next-2.6 PATCH 3/9] vxge: Removed accessing non-supported registers.
From: Sreenivasa Honnur @ 2009-10-05 9:08 UTC (permalink / raw)
To: davem; +Cc: netdev, support
- Removed accessing GENDMA_INT register
- This allowed the firmware to perform a generic DMA write to host memory.
This feature is not supported by the ASIC, this patch removes access to
GENDMA_INT register.
Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
---
diff -urpN patch2/drivers/net/vxge/vxge-config.c patch3/drivers/net/vxge/vxge-config.c
--- patch2/drivers/net/vxge/vxge-config.c 2009-09-04 01:17:22.000000000 -0700
+++ patch3/drivers/net/vxge/vxge-config.c 2009-09-04 01:19:53.000000000 -0700
@@ -4106,8 +4106,6 @@ __vxge_hw_vpath_initialize(struct __vxge
if (status != VXGE_HW_OK)
goto exit;
- writeq(0, &vp_reg->gendma_int);
-
val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
/* Get MRRS value from device control */
diff -urpN patch2/drivers/net/vxge/vxge-reg.h patch3/drivers/net/vxge/vxge-reg.h
--- patch2/drivers/net/vxge/vxge-reg.h 2009-09-04 01:17:22.000000000 -0700
+++ patch3/drivers/net/vxge/vxge-reg.h 2009-09-04 01:20:26.000000000 -0700
@@ -4326,10 +4326,6 @@ struct vxge_hw_vpath_reg {
/*0x011e0*/ u64 umq_bwr_init_byte;
#define VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32)
/*0x011e8*/ u64 gendma_int;
-#define VXGE_HW_GENDMA_INT_IMMED_ENABLE vxge_mBIT(6)
-#define VXGE_HW_GENDMA_INT_EVENT_ENABLE vxge_mBIT(7)
-#define VXGE_HW_GENDMA_INT_NUMBER(val) vxge_vBIT(val, 9, 7)
-#define VXGE_HW_GENDMA_INT_BITMAP(val) vxge_vBIT(val, 16, 16)
/*0x011f0*/ u64 umqdmq_ir_init_notify;
#define VXGE_HW_UMQDMQ_IR_INIT_NOTIFY_PULSE vxge_mBIT(3)
/*0x011f8*/ u64 dmq_init_notify;
^ permalink raw reply
* Re: vxge: Update driver_config->vpath_per_dev for each function in probe.
From: David Miller @ 2009-10-05 9:32 UTC (permalink / raw)
To: Sreenivasa.Honnur; +Cc: netdev, support
In-Reply-To: <Pine.GSO.4.10.10910050506150.2346-100000@guinness>
From: Sreenivasa Honnur <Sreenivasa.Honnur@neterion.com>
Date: Mon, 5 Oct 2009 05:06:56 -0400 (EDT)
> - Update driver_config->vpath_per_dev for each function in probe.
>
> - vpath_per_device specifies number of vpaths supported for each function/device. The
> current code was updating vpath_per_device only for physical device, however this has
> to be updated for each function also in case of a MF(Multi function) device.
>
> Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
You keep posting this patch twice.
Once without the proper "[PATCH 2/9]" indication in the subject
heading, and once with it there.
Please sort out your patch set, there is something wrong with
what you're submitting for this.
^ permalink raw reply
* RE: vxge: Update driver_config->vpath_per_dev for each function in probe.
From: Sreenivasa Honnur @ 2009-10-05 9:36 UTC (permalink / raw)
To: David Miller; +Cc: netdev, support
In-Reply-To: <20091005.023219.45309053.davem@davemloft.net>
Please ignore this patch.
I submitted this patch without patch number. I again resubmitted it with
patch number.
-----Original Message-----
From: David Miller [mailto:davem@davemloft.net]
Sent: Monday, October 05, 2009 3:02 PM
To: Sreenivasa Honnur
Cc: netdev@vger.kernel.org; support
Subject: Re: vxge: Update driver_config->vpath_per_dev for each function
in probe.
From: Sreenivasa Honnur <Sreenivasa.Honnur@neterion.com>
Date: Mon, 5 Oct 2009 05:06:56 -0400 (EDT)
> - Update driver_config->vpath_per_dev for each function in probe.
>
> - vpath_per_device specifies number of vpaths supported for each
function/device. The
> current code was updating vpath_per_device only for physical device,
however this has
> to be updated for each function also in case of a MF(Multi function)
device.
>
> Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
You keep posting this patch twice.
Once without the proper "[PATCH 2/9]" indication in the subject heading,
and once with it there.
Please sort out your patch set, there is something wrong with what
you're submitting for this.
^ permalink raw reply
* Re: vxge: Update driver_config->vpath_per_dev for each function in probe.
From: David Miller @ 2009-10-05 9:38 UTC (permalink / raw)
To: Sreenivasa.Honnur; +Cc: netdev, support
In-Reply-To: <78C9135A3D2ECE4B8162EBDCE82CAD7705C1618E@nekter>
From: "Sreenivasa Honnur" <Sreenivasa.Honnur@neterion.com>
Date: Mon, 5 Oct 2009 05:36:19 -0400
> Please ignore this patch.
>
> I submitted this patch without patch number. I again resubmitted it with
> patch number.
Ok.
^ permalink raw reply
* RE: [net-next-2.6 PATCH 1/9] vxge: Modify __vxge_hw_device_is_privilaged() to not assume function-0 as privilaged function.
From: Sreenivasa Honnur @ 2009-10-05 9:40 UTC (permalink / raw)
To: David Miller; +Cc: netdev, support
In-Reply-To: <20091005.022017.252887922.davem@davemloft.net>
I could apply these patches with "patch -p1 patch_file" command.
-----Original Message-----
From: David Miller [mailto:davem@davemloft.net]
Sent: Monday, October 05, 2009 2:50 PM
To: Sreenivasa Honnur
Cc: netdev@vger.kernel.org; support
Subject: Re: [net-next-2.6 PATCH 1/9] vxge: Modify
__vxge_hw_device_is_privilaged() to not assume function-0 as privilaged
function.
From: Sreenivasa Honnur <Sreenivasa.Honnur@neterion.com>
Date: Mon, 5 Oct 2009 05:06:06 -0400 (EDT)
> - vxge driver was assuming function-0 is always the privilaged
function. Now that
> restriction has been removed any function can act as a privilaged
function.
>
> - This patch modifies the __vxge_hw_device_is_privilaged routine to
not assume
> function-0 as the privileged function.
>
> Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
> ---
> diff -urpN orig//drivers/net/vxge/vxge-config.c
patch1//drivers/net/vxge/vxge-config.c
> --- orig//drivers/net/vxge/vxge-config.c 2009-09-03
22:39:48.000000000 -0700
> +++ patch1//drivers/net/vxge/vxge-config.c 2009-09-03
23:11:24.000000000 -0700
You can't have the double slash there in your paths, this gets
interpreted as "/drivers/net/vxge/vxge-config.c" by all the patch
applying tools.
Please "-p1" root your patches properly as described in
linux/Documentation/SubmittingPatches
You'll need to resubmit your entire patch set with this fixed up.
Thanks.
^ permalink raw reply
* RE: [net-next-2.6 PATCH 1/9] vxge: Modify __vxge_hw_device_is_privilaged() to not assume function-0 as privilaged function.
From: Sreenivasa Honnur @ 2009-10-05 9:43 UTC (permalink / raw)
To: Sreenivasa Honnur, David Miller; +Cc: netdev, support
In-Reply-To: <78C9135A3D2ECE4B8162EBDCE82CAD7705C1618F@nekter>
I could apply these patches with "patch -p1 < patch_file" command.
i.e /usr/src/davem-net-2.6 # patch -p1 < patch_2-0-6-1
-----Original Message-----
From: Sreenivasa Honnur
Sent: Monday, October 05, 2009 3:10 PM
To: David Miller
Cc: netdev@vger.kernel.org; support
Subject: RE: [net-next-2.6 PATCH 1/9] vxge: Modify
__vxge_hw_device_is_privilaged() to not assume function-0 as privilaged
function.
I could apply these patches with "patch -p1 patch_file" command.
-----Original Message-----
From: David Miller [mailto:davem@davemloft.net]
Sent: Monday, October 05, 2009 2:50 PM
To: Sreenivasa Honnur
Cc: netdev@vger.kernel.org; support
Subject: Re: [net-next-2.6 PATCH 1/9] vxge: Modify
__vxge_hw_device_is_privilaged() to not assume function-0 as privilaged
function.
From: Sreenivasa Honnur <Sreenivasa.Honnur@neterion.com>
Date: Mon, 5 Oct 2009 05:06:06 -0400 (EDT)
> - vxge driver was assuming function-0 is always the privilaged
function. Now that
> restriction has been removed any function can act as a privilaged
function.
>
> - This patch modifies the __vxge_hw_device_is_privilaged routine to
not assume
> function-0 as the privileged function.
>
> Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
> ---
> diff -urpN orig//drivers/net/vxge/vxge-config.c
patch1//drivers/net/vxge/vxge-config.c
> --- orig//drivers/net/vxge/vxge-config.c 2009-09-03
22:39:48.000000000 -0700
> +++ patch1//drivers/net/vxge/vxge-config.c 2009-09-03
23:11:24.000000000 -0700
You can't have the double slash there in your paths, this gets
interpreted as "/drivers/net/vxge/vxge-config.c" by all the patch
applying tools.
Please "-p1" root your patches properly as described in
linux/Documentation/SubmittingPatches
You'll need to resubmit your entire patch set with this fixed up.
Thanks.
^ permalink raw reply
* Re: r8169 chips on some Intel D945GSEJT boards fail to work after PXE boot
From: Simon Farnsworth @ 2009-10-05 9:47 UTC (permalink / raw)
To: Francois Romieu; +Cc: netdev
In-Reply-To: <20090930220702.GA15415@electric-eye.fr.zoreil.com>
Francois Romieu wrote:
> Simon Farnsworth <simon.farnsworth@onelan.com> :
[...]
>> Is my assumption wrong? If not, is there anything else I can do that
>> would help you diagnose this?
>
> Try this against 2.6.31 or latest -rc.
This worked for my boards.
Thanks for your help,
Tested-By: Simon Farnsworth <simon.farnsworth@onelan.com>
>
>
> diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
> index 50c6a3c..74488a6 100644
> --- a/drivers/net/r8169.c
> +++ b/drivers/net/r8169.c
> @@ -115,7 +115,9 @@ enum mac_version {
> RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
> RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
> RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
> - RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
> + RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
> + RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
> + RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
> };
>
> #define _R(NAME,MAC,MASK) \
> @@ -150,7 +152,9 @@ static const struct {
> _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
> _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
> _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
> - _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
> + _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
> + _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
> + _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
> };
> #undef _R
>
> @@ -253,6 +257,13 @@ enum rtl8168_8101_registers {
> DBG_REG = 0xd1,
> #define FIX_NAK_1 (1 << 4)
> #define FIX_NAK_2 (1 << 3)
> + EFUSEAR = 0xdc,
> +#define EFUSEAR_FLAG 0x80000000
> +#define EFUSEAR_WRITE_CMD 0x80000000
> +#define EFUSEAR_READ_CMD 0x00000000
> +#define EFUSEAR_REG_MASK 0x03ff
> +#define EFUSEAR_REG_SHIFT 8
> +#define EFUSEAR_DATA_MASK 0xff
> };
>
> enum rtl_register_content {
> @@ -568,6 +579,14 @@ static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
> mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
> }
>
> +static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
> +{
> + int val;
> +
> + val = mdio_read(ioaddr, reg_addr);
> + mdio_write(ioaddr, reg_addr, (val | p) & ~m);
> +}
> +
> static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
> int val)
> {
> @@ -651,6 +670,24 @@ static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
> return value;
> }
>
> +static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
> +{
> + u8 value = 0xff;
> + unsigned int i;
> +
> + RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
> +
> + for (i = 0; i < 300; i++) {
> + if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
> + value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
> + break;
> + }
> + udelay(100);
> + }
> +
> + return value;
> +}
> +
> static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
> {
> RTL_W16(IntrMask, 0x0000);
> @@ -1243,7 +1280,10 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
> int mac_version;
> } mac_info[] = {
> /* 8168D family. */
> - { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
> + { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
> + { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
> + { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
> + { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
>
> /* 8168C family. */
> { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
> @@ -1648,74 +1688,903 @@ static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
> rtl8168c_3_hw_phy_config(ioaddr);
> }
>
> -static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
> +static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
> {
> struct phy_reg phy_reg_init_0[] = {
> { 0x1f, 0x0001 },
> - { 0x09, 0x2770 },
> - { 0x08, 0x04d0 },
> - { 0x0b, 0xad15 },
> - { 0x0c, 0x5bf0 },
> - { 0x1c, 0xf101 },
> + { 0x06, 0x4064 },
> + { 0x07, 0x2863 },
> + { 0x08, 0x059c },
> + { 0x09, 0x26b4 },
> + { 0x0a, 0x6a19 },
> + { 0x0b, 0xdcc8 },
> + { 0x10, 0xf06d },
> + { 0x14, 0x7f68 },
> + { 0x18, 0x7fd9 },
> + { 0x1c, 0xf0ff },
> + { 0x1d, 0x3d9c },
> { 0x1f, 0x0003 },
> - { 0x14, 0x94d7 },
> - { 0x12, 0xf4d6 },
> - { 0x09, 0xca0f },
> - { 0x1f, 0x0002 },
> - { 0x0b, 0x0b10 },
> - { 0x0c, 0xd1f7 },
> - { 0x1f, 0x0002 },
> - { 0x06, 0x5461 },
> + { 0x12, 0xf49f },
> + { 0x13, 0x070b },
> + { 0x1a, 0x05ad },
> + { 0x14, 0x94c0 }
> + };
> + struct phy_reg phy_reg_init_1[] = {
> { 0x1f, 0x0002 },
> - { 0x05, 0x6662 },
> + { 0x06, 0x5561 },
> + { 0x1f, 0x0005 },
> + { 0x05, 0x8332 },
> + { 0x06, 0x5561 }
> + };
> + struct phy_reg phy_reg_init_2[] = {
> + { 0x1f, 0x0005 },
> + { 0x05, 0xffc2 },
> + { 0x1f, 0x0005 },
> + { 0x05, 0x8000 },
> + { 0x06, 0xf8f9 },
> + { 0x06, 0xfaef },
> + { 0x06, 0x59ee },
> + { 0x06, 0xf8ea },
> + { 0x06, 0x00ee },
> + { 0x06, 0xf8eb },
> + { 0x06, 0x00e0 },
> + { 0x06, 0xf87c },
> + { 0x06, 0xe1f8 },
> + { 0x06, 0x7d59 },
> + { 0x06, 0x0fef },
> + { 0x06, 0x0139 },
> + { 0x06, 0x029e },
> + { 0x06, 0x06ef },
> + { 0x06, 0x1039 },
> + { 0x06, 0x089f },
> + { 0x06, 0x2aee },
> + { 0x06, 0xf8ea },
> + { 0x06, 0x00ee },
> + { 0x06, 0xf8eb },
> + { 0x06, 0x01e0 },
> + { 0x06, 0xf87c },
> + { 0x06, 0xe1f8 },
> + { 0x06, 0x7d58 },
> + { 0x06, 0x409e },
> + { 0x06, 0x0f39 },
> + { 0x06, 0x46aa },
> + { 0x06, 0x0bbf },
> + { 0x06, 0x8290 },
> + { 0x06, 0xd682 },
> + { 0x06, 0x9802 },
> + { 0x06, 0x014f },
> + { 0x06, 0xae09 },
> + { 0x06, 0xbf82 },
> + { 0x06, 0x98d6 },
> + { 0x06, 0x82a0 },
> + { 0x06, 0x0201 },
> + { 0x06, 0x4fef },
> + { 0x06, 0x95fe },
> + { 0x06, 0xfdfc },
> + { 0x06, 0x05f8 },
> + { 0x06, 0xf9fa },
> + { 0x06, 0xeef8 },
> + { 0x06, 0xea00 },
> + { 0x06, 0xeef8 },
> + { 0x06, 0xeb00 },
> + { 0x06, 0xe2f8 },
> + { 0x06, 0x7ce3 },
> + { 0x06, 0xf87d },
> + { 0x06, 0xa511 },
> + { 0x06, 0x1112 },
> + { 0x06, 0xd240 },
> + { 0x06, 0xd644 },
> + { 0x06, 0x4402 },
> + { 0x06, 0x8217 },
> + { 0x06, 0xd2a0 },
> + { 0x06, 0xd6aa },
> + { 0x06, 0xaa02 },
> + { 0x06, 0x8217 },
> + { 0x06, 0xae0f },
> + { 0x06, 0xa544 },
> + { 0x06, 0x4402 },
> + { 0x06, 0xae4d },
> + { 0x06, 0xa5aa },
> + { 0x06, 0xaa02 },
> + { 0x06, 0xae47 },
> + { 0x06, 0xaf82 },
> + { 0x06, 0x13ee },
> + { 0x06, 0x834e },
> + { 0x06, 0x00ee },
> + { 0x06, 0x834d },
> + { 0x06, 0x0fee },
> + { 0x06, 0x834c },
> + { 0x06, 0x0fee },
> + { 0x06, 0x834f },
> + { 0x06, 0x00ee },
> + { 0x06, 0x8351 },
> + { 0x06, 0x00ee },
> + { 0x06, 0x834a },
> + { 0x06, 0xffee },
> + { 0x06, 0x834b },
> + { 0x06, 0xffe0 },
> + { 0x06, 0x8330 },
> + { 0x06, 0xe183 },
> + { 0x06, 0x3158 },
> + { 0x06, 0xfee4 },
> + { 0x06, 0xf88a },
> + { 0x06, 0xe5f8 },
> + { 0x06, 0x8be0 },
> + { 0x06, 0x8332 },
> + { 0x06, 0xe183 },
> + { 0x06, 0x3359 },
> + { 0x06, 0x0fe2 },
> + { 0x06, 0x834d },
> + { 0x06, 0x0c24 },
> + { 0x06, 0x5af0 },
> + { 0x06, 0x1e12 },
> + { 0x06, 0xe4f8 },
> + { 0x06, 0x8ce5 },
> + { 0x06, 0xf88d },
> + { 0x06, 0xaf82 },
> + { 0x06, 0x13e0 },
> + { 0x06, 0x834f },
> + { 0x06, 0x10e4 },
> + { 0x06, 0x834f },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4e78 },
> + { 0x06, 0x009f },
> + { 0x06, 0x0ae0 },
> + { 0x06, 0x834f },
> + { 0x06, 0xa010 },
> + { 0x06, 0xa5ee },
> + { 0x06, 0x834e },
> + { 0x06, 0x01e0 },
> + { 0x06, 0x834e },
> + { 0x06, 0x7805 },
> + { 0x06, 0x9e9a },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4e78 },
> + { 0x06, 0x049e },
> + { 0x06, 0x10e0 },
> + { 0x06, 0x834e },
> + { 0x06, 0x7803 },
> + { 0x06, 0x9e0f },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4e78 },
> + { 0x06, 0x019e },
> + { 0x06, 0x05ae },
> + { 0x06, 0x0caf },
> + { 0x06, 0x81f8 },
> + { 0x06, 0xaf81 },
> + { 0x06, 0xa3af },
> + { 0x06, 0x81dc },
> + { 0x06, 0xaf82 },
> + { 0x06, 0x13ee },
> + { 0x06, 0x8348 },
> + { 0x06, 0x00ee },
> + { 0x06, 0x8349 },
> + { 0x06, 0x00e0 },
> + { 0x06, 0x8351 },
> + { 0x06, 0x10e4 },
> + { 0x06, 0x8351 },
> + { 0x06, 0x5801 },
> + { 0x06, 0x9fea },
> + { 0x06, 0xd000 },
> + { 0x06, 0xd180 },
> + { 0x06, 0x1f66 },
> + { 0x06, 0xe2f8 },
> + { 0x06, 0xeae3 },
> + { 0x06, 0xf8eb },
> + { 0x06, 0x5af8 },
> + { 0x06, 0x1e20 },
> + { 0x06, 0xe6f8 },
> + { 0x06, 0xeae5 },
> + { 0x06, 0xf8eb },
> + { 0x06, 0xd302 },
> + { 0x06, 0xb3fe },
> + { 0x06, 0xe2f8 },
> + { 0x06, 0x7cef },
> + { 0x06, 0x325b },
> + { 0x06, 0x80e3 },
> + { 0x06, 0xf87d },
> + { 0x06, 0x9e03 },
> + { 0x06, 0x7dff },
> + { 0x06, 0xff0d },
> + { 0x06, 0x581c },
> + { 0x06, 0x551a },
> + { 0x06, 0x6511 },
> + { 0x06, 0xa190 },
> + { 0x06, 0xd3e2 },
> + { 0x06, 0x8348 },
> + { 0x06, 0xe383 },
> + { 0x06, 0x491b },
> + { 0x06, 0x56ab },
> + { 0x06, 0x08ef },
> + { 0x06, 0x56e6 },
> + { 0x06, 0x8348 },
> + { 0x06, 0xe783 },
> + { 0x06, 0x4910 },
> + { 0x06, 0xd180 },
> + { 0x06, 0x1f66 },
> + { 0x06, 0xa004 },
> + { 0x06, 0xb9e2 },
> + { 0x06, 0x8348 },
> + { 0x06, 0xe383 },
> + { 0x06, 0x49ef },
> + { 0x06, 0x65e2 },
> + { 0x06, 0x834a },
> + { 0x06, 0xe383 },
> + { 0x06, 0x4b1b },
> + { 0x06, 0x56aa },
> + { 0x06, 0x0eef },
> + { 0x06, 0x56e6 },
> + { 0x06, 0x834a },
> + { 0x06, 0xe783 },
> + { 0x06, 0x4be2 },
> + { 0x06, 0x834d },
> + { 0x06, 0xe683 },
> + { 0x06, 0x4ce0 },
> + { 0x06, 0x834d },
> + { 0x06, 0xa000 },
> + { 0x06, 0x0caf },
> + { 0x06, 0x81dc },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4d10 },
> + { 0x06, 0xe483 },
> + { 0x06, 0x4dae },
> + { 0x06, 0x0480 },
> + { 0x06, 0xe483 },
> + { 0x06, 0x4de0 },
> + { 0x06, 0x834e },
> + { 0x06, 0x7803 },
> + { 0x06, 0x9e0b },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4e78 },
> + { 0x06, 0x049e },
> + { 0x06, 0x04ee },
> + { 0x06, 0x834e },
> + { 0x06, 0x02e0 },
> + { 0x06, 0x8332 },
> + { 0x06, 0xe183 },
> + { 0x06, 0x3359 },
> + { 0x06, 0x0fe2 },
> + { 0x06, 0x834d },
> + { 0x06, 0x0c24 },
> + { 0x06, 0x5af0 },
> + { 0x06, 0x1e12 },
> + { 0x06, 0xe4f8 },
> + { 0x06, 0x8ce5 },
> + { 0x06, 0xf88d },
> + { 0x06, 0xe083 },
> + { 0x06, 0x30e1 },
> + { 0x06, 0x8331 },
> + { 0x06, 0x6801 },
> + { 0x06, 0xe4f8 },
> + { 0x06, 0x8ae5 },
> + { 0x06, 0xf88b },
> + { 0x06, 0xae37 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4e03 },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4ce1 },
> + { 0x06, 0x834d },
> + { 0x06, 0x1b01 },
> + { 0x06, 0x9e04 },
> + { 0x06, 0xaaa1 },
> + { 0x06, 0xaea8 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4e04 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4f00 },
> + { 0x06, 0xaeab },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4f78 },
> + { 0x06, 0x039f },
> + { 0x06, 0x14ee },
> + { 0x06, 0x834e },
> + { 0x06, 0x05d2 },
> + { 0x06, 0x40d6 },
> + { 0x06, 0x5554 },
> + { 0x06, 0x0282 },
> + { 0x06, 0x17d2 },
> + { 0x06, 0xa0d6 },
> + { 0x06, 0xba00 },
> + { 0x06, 0x0282 },
> + { 0x06, 0x17fe },
> + { 0x06, 0xfdfc },
> + { 0x06, 0x05f8 },
> + { 0x06, 0xe0f8 },
> + { 0x06, 0x60e1 },
> + { 0x06, 0xf861 },
> + { 0x06, 0x6802 },
> + { 0x06, 0xe4f8 },
> + { 0x06, 0x60e5 },
> + { 0x06, 0xf861 },
> + { 0x06, 0xe0f8 },
> + { 0x06, 0x48e1 },
> + { 0x06, 0xf849 },
> + { 0x06, 0x580f },
> + { 0x06, 0x1e02 },
> + { 0x06, 0xe4f8 },
> + { 0x06, 0x48e5 },
> + { 0x06, 0xf849 },
> + { 0x06, 0xd000 },
> + { 0x06, 0x0282 },
> + { 0x06, 0x5bbf },
> + { 0x06, 0x8350 },
> + { 0x06, 0xef46 },
> + { 0x06, 0xdc19 },
> + { 0x06, 0xddd0 },
> + { 0x06, 0x0102 },
> + { 0x06, 0x825b },
> + { 0x06, 0x0282 },
> + { 0x06, 0x77e0 },
> + { 0x06, 0xf860 },
> + { 0x06, 0xe1f8 },
> + { 0x06, 0x6158 },
> + { 0x06, 0xfde4 },
> + { 0x06, 0xf860 },
> + { 0x06, 0xe5f8 },
> + { 0x06, 0x61fc },
> + { 0x06, 0x04f9 },
> + { 0x06, 0xfafb },
> + { 0x06, 0xc6bf },
> + { 0x06, 0xf840 },
> + { 0x06, 0xbe83 },
> + { 0x06, 0x50a0 },
> + { 0x06, 0x0101 },
> + { 0x06, 0x071b },
> + { 0x06, 0x89cf },
> + { 0x06, 0xd208 },
> + { 0x06, 0xebdb },
> + { 0x06, 0x19b2 },
> + { 0x06, 0xfbff },
> + { 0x06, 0xfefd },
> + { 0x06, 0x04f8 },
> + { 0x06, 0xe0f8 },
> + { 0x06, 0x48e1 },
> + { 0x06, 0xf849 },
> + { 0x06, 0x6808 },
> + { 0x06, 0xe4f8 },
> + { 0x06, 0x48e5 },
> + { 0x06, 0xf849 },
> + { 0x06, 0x58f7 },
> + { 0x06, 0xe4f8 },
> + { 0x06, 0x48e5 },
> + { 0x06, 0xf849 },
> + { 0x06, 0xfc04 },
> + { 0x06, 0x4d20 },
> + { 0x06, 0x0002 },
> + { 0x06, 0x4e22 },
> + { 0x06, 0x0002 },
> + { 0x06, 0x4ddf },
> + { 0x06, 0xff01 },
> + { 0x06, 0x4edd },
> + { 0x06, 0xff01 },
> + { 0x05, 0x83d4 },
> + { 0x06, 0x8000 },
> + { 0x05, 0x83d8 },
> + { 0x06, 0x8051 },
> + { 0x02, 0x6010 },
> + { 0x03, 0xdc00 },
> + { 0x05, 0xfff6 },
> + { 0x06, 0x00fc },
> { 0x1f, 0x0000 },
> - { 0x14, 0x0060 },
> +
> { 0x1f, 0x0000 },
> - { 0x0d, 0xf8a0 },
> + { 0x0d, 0xf880 },
> + { 0x1f, 0x0000 }
> + };
> +
> + rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
> +
> + mdio_write(ioaddr, 0x1f, 0x0002);
> + mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
> + mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
> +
> + rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
> +
> + if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
> + struct phy_reg phy_reg_init[] = {
> + { 0x1f, 0x0002 },
> + { 0x05, 0x669a },
> + { 0x1f, 0x0005 },
> + { 0x05, 0x8330 },
> + { 0x06, 0x669a },
> + { 0x1f, 0x0002 }
> + };
> + int val;
> +
> + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
> +
> + val = mdio_read(ioaddr, 0x0d);
> +
> + if ((val & 0x00ff) != 0x006c) {
> + u32 set[] = {
> + 0x0065, 0x0066, 0x0067, 0x0068,
> + 0x0069, 0x006a, 0x006b, 0x006c
> + };
> + int i;
> +
> + mdio_write(ioaddr, 0x1f, 0x0002);
> +
> + val &= 0xff00;
> + for (i = 0; i < ARRAY_SIZE(set); i++)
> + mdio_write(ioaddr, 0x0d, val | set[i]);
> + }
> + } else {
> + struct phy_reg phy_reg_init[] = {
> + { 0x1f, 0x0002 },
> + { 0x05, 0x6662 },
> + { 0x1f, 0x0005 },
> + { 0x05, 0x8330 },
> + { 0x06, 0x6662 }
> + };
> +
> + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
> + }
> +
> + mdio_write(ioaddr, 0x1f, 0x0002);
> + mdio_patch(ioaddr, 0x0d, 0x0300);
> + mdio_patch(ioaddr, 0x0f, 0x0010);
> +
> + mdio_write(ioaddr, 0x1f, 0x0002);
> + mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
> + mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
> +
> + rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
> +}
> +
> +static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
> +{
> + struct phy_reg phy_reg_init_0[] = {
> + { 0x1f, 0x0001 },
> + { 0x06, 0x4064 },
> + { 0x07, 0x2863 },
> + { 0x08, 0x059c },
> + { 0x09, 0x26b4 },
> + { 0x0a, 0x6a19 },
> + { 0x0b, 0xdcc8 },
> + { 0x10, 0xf06d },
> + { 0x14, 0x7f68 },
> + { 0x18, 0x7fd9 },
> + { 0x1c, 0xf0ff },
> + { 0x1d, 0x3d9c },
> + { 0x1f, 0x0003 },
> + { 0x12, 0xf49f },
> + { 0x13, 0x070b },
> + { 0x1a, 0x05ad },
> + { 0x14, 0x94c0 },
> +
> + { 0x1f, 0x0002 },
> + { 0x06, 0x5561 },
> { 0x1f, 0x0005 },
> - { 0x05, 0xffc2 }
> + { 0x05, 0x8332 },
> + { 0x06, 0x5561 }
> + };
> + struct phy_reg phy_reg_init_1[] = {
> + { 0x1f, 0x0005 },
> + { 0x05, 0xffc2 },
> + { 0x1f, 0x0005 },
> + { 0x05, 0x8000 },
> + { 0x06, 0xf8f9 },
> + { 0x06, 0xfaee },
> + { 0x06, 0xf8ea },
> + { 0x06, 0x00ee },
> + { 0x06, 0xf8eb },
> + { 0x06, 0x00e2 },
> + { 0x06, 0xf87c },
> + { 0x06, 0xe3f8 },
> + { 0x06, 0x7da5 },
> + { 0x06, 0x1111 },
> + { 0x06, 0x12d2 },
> + { 0x06, 0x40d6 },
> + { 0x06, 0x4444 },
> + { 0x06, 0x0281 },
> + { 0x06, 0xc6d2 },
> + { 0x06, 0xa0d6 },
> + { 0x06, 0xaaaa },
> + { 0x06, 0x0281 },
> + { 0x06, 0xc6ae },
> + { 0x06, 0x0fa5 },
> + { 0x06, 0x4444 },
> + { 0x06, 0x02ae },
> + { 0x06, 0x4da5 },
> + { 0x06, 0xaaaa },
> + { 0x06, 0x02ae },
> + { 0x06, 0x47af },
> + { 0x06, 0x81c2 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4e00 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4d0f },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4c0f },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4f00 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x5100 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4aff },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4bff },
> + { 0x06, 0xe083 },
> + { 0x06, 0x30e1 },
> + { 0x06, 0x8331 },
> + { 0x06, 0x58fe },
> + { 0x06, 0xe4f8 },
> + { 0x06, 0x8ae5 },
> + { 0x06, 0xf88b },
> + { 0x06, 0xe083 },
> + { 0x06, 0x32e1 },
> + { 0x06, 0x8333 },
> + { 0x06, 0x590f },
> + { 0x06, 0xe283 },
> + { 0x06, 0x4d0c },
> + { 0x06, 0x245a },
> + { 0x06, 0xf01e },
> + { 0x06, 0x12e4 },
> + { 0x06, 0xf88c },
> + { 0x06, 0xe5f8 },
> + { 0x06, 0x8daf },
> + { 0x06, 0x81c2 },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4f10 },
> + { 0x06, 0xe483 },
> + { 0x06, 0x4fe0 },
> + { 0x06, 0x834e },
> + { 0x06, 0x7800 },
> + { 0x06, 0x9f0a },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4fa0 },
> + { 0x06, 0x10a5 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4e01 },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4e78 },
> + { 0x06, 0x059e },
> + { 0x06, 0x9ae0 },
> + { 0x06, 0x834e },
> + { 0x06, 0x7804 },
> + { 0x06, 0x9e10 },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4e78 },
> + { 0x06, 0x039e },
> + { 0x06, 0x0fe0 },
> + { 0x06, 0x834e },
> + { 0x06, 0x7801 },
> + { 0x06, 0x9e05 },
> + { 0x06, 0xae0c },
> + { 0x06, 0xaf81 },
> + { 0x06, 0xa7af },
> + { 0x06, 0x8152 },
> + { 0x06, 0xaf81 },
> + { 0x06, 0x8baf },
> + { 0x06, 0x81c2 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4800 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4900 },
> + { 0x06, 0xe083 },
> + { 0x06, 0x5110 },
> + { 0x06, 0xe483 },
> + { 0x06, 0x5158 },
> + { 0x06, 0x019f },
> + { 0x06, 0xead0 },
> + { 0x06, 0x00d1 },
> + { 0x06, 0x801f },
> + { 0x06, 0x66e2 },
> + { 0x06, 0xf8ea },
> + { 0x06, 0xe3f8 },
> + { 0x06, 0xeb5a },
> + { 0x06, 0xf81e },
> + { 0x06, 0x20e6 },
> + { 0x06, 0xf8ea },
> + { 0x06, 0xe5f8 },
> + { 0x06, 0xebd3 },
> + { 0x06, 0x02b3 },
> + { 0x06, 0xfee2 },
> + { 0x06, 0xf87c },
> + { 0x06, 0xef32 },
> + { 0x06, 0x5b80 },
> + { 0x06, 0xe3f8 },
> + { 0x06, 0x7d9e },
> + { 0x06, 0x037d },
> + { 0x06, 0xffff },
> + { 0x06, 0x0d58 },
> + { 0x06, 0x1c55 },
> + { 0x06, 0x1a65 },
> + { 0x06, 0x11a1 },
> + { 0x06, 0x90d3 },
> + { 0x06, 0xe283 },
> + { 0x06, 0x48e3 },
> + { 0x06, 0x8349 },
> + { 0x06, 0x1b56 },
> + { 0x06, 0xab08 },
> + { 0x06, 0xef56 },
> + { 0x06, 0xe683 },
> + { 0x06, 0x48e7 },
> + { 0x06, 0x8349 },
> + { 0x06, 0x10d1 },
> + { 0x06, 0x801f },
> + { 0x06, 0x66a0 },
> + { 0x06, 0x04b9 },
> + { 0x06, 0xe283 },
> + { 0x06, 0x48e3 },
> + { 0x06, 0x8349 },
> + { 0x06, 0xef65 },
> + { 0x06, 0xe283 },
> + { 0x06, 0x4ae3 },
> + { 0x06, 0x834b },
> + { 0x06, 0x1b56 },
> + { 0x06, 0xaa0e },
> + { 0x06, 0xef56 },
> + { 0x06, 0xe683 },
> + { 0x06, 0x4ae7 },
> + { 0x06, 0x834b },
> + { 0x06, 0xe283 },
> + { 0x06, 0x4de6 },
> + { 0x06, 0x834c },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4da0 },
> + { 0x06, 0x000c },
> + { 0x06, 0xaf81 },
> + { 0x06, 0x8be0 },
> + { 0x06, 0x834d },
> + { 0x06, 0x10e4 },
> + { 0x06, 0x834d },
> + { 0x06, 0xae04 },
> + { 0x06, 0x80e4 },
> + { 0x06, 0x834d },
> + { 0x06, 0xe083 },
> + { 0x06, 0x4e78 },
> + { 0x06, 0x039e },
> + { 0x06, 0x0be0 },
> + { 0x06, 0x834e },
> + { 0x06, 0x7804 },
> + { 0x06, 0x9e04 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4e02 },
> + { 0x06, 0xe083 },
> + { 0x06, 0x32e1 },
> + { 0x06, 0x8333 },
> + { 0x06, 0x590f },
> + { 0x06, 0xe283 },
> + { 0x06, 0x4d0c },
> + { 0x06, 0x245a },
> + { 0x06, 0xf01e },
> + { 0x06, 0x12e4 },
> + { 0x06, 0xf88c },
> + { 0x06, 0xe5f8 },
> + { 0x06, 0x8de0 },
> + { 0x06, 0x8330 },
> + { 0x06, 0xe183 },
> + { 0x06, 0x3168 },
> + { 0x06, 0x01e4 },
> + { 0x06, 0xf88a },
> + { 0x06, 0xe5f8 },
> + { 0x06, 0x8bae },
> + { 0x06, 0x37ee },
> + { 0x06, 0x834e },
> + { 0x06, 0x03e0 },
> + { 0x06, 0x834c },
> + { 0x06, 0xe183 },
> + { 0x06, 0x4d1b },
> + { 0x06, 0x019e },
> + { 0x06, 0x04aa },
> + { 0x06, 0xa1ae },
> + { 0x06, 0xa8ee },
> + { 0x06, 0x834e },
> + { 0x06, 0x04ee },
> + { 0x06, 0x834f },
> + { 0x06, 0x00ae },
> + { 0x06, 0xabe0 },
> + { 0x06, 0x834f },
> + { 0x06, 0x7803 },
> + { 0x06, 0x9f14 },
> + { 0x06, 0xee83 },
> + { 0x06, 0x4e05 },
> + { 0x06, 0xd240 },
> + { 0x06, 0xd655 },
> + { 0x06, 0x5402 },
> + { 0x06, 0x81c6 },
> + { 0x06, 0xd2a0 },
> + { 0x06, 0xd6ba },
> + { 0x06, 0x0002 },
> + { 0x06, 0x81c6 },
> + { 0x06, 0xfefd },
> + { 0x06, 0xfc05 },
> + { 0x06, 0xf8e0 },
> + { 0x06, 0xf860 },
> + { 0x06, 0xe1f8 },
> + { 0x06, 0x6168 },
> + { 0x06, 0x02e4 },
> + { 0x06, 0xf860 },
> + { 0x06, 0xe5f8 },
> + { 0x06, 0x61e0 },
> + { 0x06, 0xf848 },
> + { 0x06, 0xe1f8 },
> + { 0x06, 0x4958 },
> + { 0x06, 0x0f1e },
> + { 0x06, 0x02e4 },
> + { 0x06, 0xf848 },
> + { 0x06, 0xe5f8 },
> + { 0x06, 0x49d0 },
> + { 0x06, 0x0002 },
> + { 0x06, 0x820a },
> + { 0x06, 0xbf83 },
> + { 0x06, 0x50ef },
> + { 0x06, 0x46dc },
> + { 0x06, 0x19dd },
> + { 0x06, 0xd001 },
> + { 0x06, 0x0282 },
> + { 0x06, 0x0a02 },
> + { 0x06, 0x8226 },
> + { 0x06, 0xe0f8 },
> + { 0x06, 0x60e1 },
> + { 0x06, 0xf861 },
> + { 0x06, 0x58fd },
> + { 0x06, 0xe4f8 },
> + { 0x06, 0x60e5 },
> + { 0x06, 0xf861 },
> + { 0x06, 0xfc04 },
> + { 0x06, 0xf9fa },
> + { 0x06, 0xfbc6 },
> + { 0x06, 0xbff8 },
> + { 0x06, 0x40be },
> + { 0x06, 0x8350 },
> + { 0x06, 0xa001 },
> + { 0x06, 0x0107 },
> + { 0x06, 0x1b89 },
> + { 0x06, 0xcfd2 },
> + { 0x06, 0x08eb },
> + { 0x06, 0xdb19 },
> + { 0x06, 0xb2fb },
> + { 0x06, 0xfffe },
> + { 0x06, 0xfd04 },
> + { 0x06, 0xf8e0 },
> + { 0x06, 0xf848 },
> + { 0x06, 0xe1f8 },
> + { 0x06, 0x4968 },
> + { 0x06, 0x08e4 },
> + { 0x06, 0xf848 },
> + { 0x06, 0xe5f8 },
> + { 0x06, 0x4958 },
> + { 0x06, 0xf7e4 },
> + { 0x06, 0xf848 },
> + { 0x06, 0xe5f8 },
> + { 0x06, 0x49fc },
> + { 0x06, 0x044d },
> + { 0x06, 0x2000 },
> + { 0x06, 0x024e },
> + { 0x06, 0x2200 },
> + { 0x06, 0x024d },
> + { 0x06, 0xdfff },
> + { 0x06, 0x014e },
> + { 0x06, 0xddff },
> + { 0x06, 0x0100 },
> + { 0x05, 0x83d8 },
> + { 0x06, 0x8000 },
> + { 0x03, 0xdc00 },
> + { 0x05, 0xfff6 },
> + { 0x06, 0x00fc },
> + { 0x1f, 0x0000 },
> +
> + { 0x1f, 0x0000 },
> + { 0x0d, 0xf880 },
> + { 0x1f, 0x0000 }
> };
>
> rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
>
> - if (mdio_read(ioaddr, 0x06) == 0xc400) {
> - struct phy_reg phy_reg_init_1[] = {
> + if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
> + struct phy_reg phy_reg_init[] = {
> + { 0x1f, 0x0002 },
> + { 0x05, 0x669a },
> { 0x1f, 0x0005 },
> - { 0x01, 0x0300 },
> - { 0x1f, 0x0000 },
> - { 0x11, 0x401c },
> - { 0x16, 0x4100 },
> + { 0x05, 0x8330 },
> + { 0x06, 0x669a },
> +
> + { 0x1f, 0x0002 }
> + };
> + int val;
> +
> + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
> +
> + val = mdio_read(ioaddr, 0x0d);
> + if ((val & 0x00ff) != 0x006c) {
> + u32 set[] = {
> + 0x0065, 0x0066, 0x0067, 0x0068,
> + 0x0069, 0x006a, 0x006b, 0x006c
> + };
> + int i;
> +
> + mdio_write(ioaddr, 0x1f, 0x0002);
> +
> + val &= 0xff00;
> + for (i = 0; i < ARRAY_SIZE(set); i++)
> + mdio_write(ioaddr, 0x0d, val | set[i]);
> + }
> + } else {
> + struct phy_reg phy_reg_init[] = {
> + { 0x1f, 0x0002 },
> + { 0x05, 0x2642 },
> { 0x1f, 0x0005 },
> - { 0x07, 0x0010 },
> - { 0x05, 0x83dc },
> - { 0x06, 0x087d },
> - { 0x05, 0x8300 },
> - { 0x06, 0x0101 },
> - { 0x06, 0x05f8 },
> - { 0x06, 0xf9fa },
> - { 0x06, 0xfbef },
> - { 0x06, 0x79e2 },
> - { 0x06, 0x835f },
> - { 0x06, 0xe0f8 },
> - { 0x06, 0x9ae1 },
> - { 0x06, 0xf89b },
> - { 0x06, 0xef31 },
> - { 0x06, 0x3b65 },
> - { 0x06, 0xaa07 },
> - { 0x06, 0x81e4 },
> - { 0x06, 0xf89a },
> - { 0x06, 0xe5f8 },
> - { 0x06, 0x9baf },
> - { 0x06, 0x06ae },
> - { 0x05, 0x83dc },
> - { 0x06, 0x8300 },
> + { 0x05, 0x8330 },
> + { 0x06, 0x2642 }
> };
>
> - rtl_phy_write(ioaddr, phy_reg_init_1,
> - ARRAY_SIZE(phy_reg_init_1));
> + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
> }
>
> - mdio_write(ioaddr, 0x1f, 0x0000);
> + mdio_write(ioaddr, 0x1f, 0x0002);
> + mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
> + mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
> +
> + mdio_write(ioaddr, 0x1f, 0x0001);
> + mdio_write(ioaddr, 0x17, 0x0cc0);
> +
> + mdio_write(ioaddr, 0x1f, 0x0002);
> + mdio_patch(ioaddr, 0x0f, 0x0017);
> +
> + rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
> +}
> +
> +static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
> +{
> + struct phy_reg phy_reg_init[] = {
> + { 0x1f, 0x0002 },
> + { 0x10, 0x0008 },
> + { 0x0d, 0x006c },
> +
> + { 0x1f, 0x0000 },
> + { 0x0d, 0xf880 },
> +
> + { 0x1f, 0x0001 },
> + { 0x17, 0x0cc0 },
> +
> + { 0x1f, 0x0001 },
> + { 0x0b, 0xa4d8 },
> + { 0x09, 0x281c },
> + { 0x07, 0x2883 },
> + { 0x0a, 0x6b35 },
> + { 0x1d, 0x3da4 },
> + { 0x1c, 0xeffd },
> + { 0x14, 0x7f52 },
> + { 0x18, 0x7fc6 },
> + { 0x08, 0x0601 },
> + { 0x06, 0x4063 },
> + { 0x10, 0xf074 },
> + { 0x1f, 0x0003 },
> + { 0x13, 0x0789 },
> + { 0x12, 0xf4bd },
> + { 0x1a, 0x04fd },
> + { 0x14, 0x84b0 },
> + { 0x1f, 0x0000 },
> + { 0x00, 0x9200 },
> +
> + { 0x1f, 0x0005 },
> + { 0x01, 0x0340 },
> + { 0x1f, 0x0001 },
> + { 0x04, 0x4000 },
> + { 0x03, 0x1d21 },
> + { 0x02, 0x0c32 },
> + { 0x01, 0x0200 },
> + { 0x00, 0x5554 },
> + { 0x04, 0x4800 },
> + { 0x04, 0x4000 },
> + { 0x04, 0xf000 },
> + { 0x03, 0xdf01 },
> + { 0x02, 0xdf20 },
> + { 0x01, 0x101a },
> + { 0x00, 0xa0ff },
> + { 0x04, 0xf800 },
> + { 0x04, 0xf000 },
> + { 0x1f, 0x0000 },
> +
> + { 0x1f, 0x0007 },
> + { 0x1e, 0x0023 },
> + { 0x16, 0x0000 },
> + { 0x1f, 0x0000 }
> + };
> +
> + rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
> }
>
> static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
> @@ -1792,7 +2661,13 @@ static void rtl_hw_phy_config(struct net_device *dev)
> rtl8168cp_2_hw_phy_config(ioaddr);
> break;
> case RTL_GIGA_MAC_VER_25:
> - rtl8168d_hw_phy_config(ioaddr);
> + rtl8168d_1_hw_phy_config(ioaddr);
> + break;
> + case RTL_GIGA_MAC_VER_26:
> + rtl8168d_2_hw_phy_config(ioaddr);
> + break;
> + case RTL_GIGA_MAC_VER_27:
> + rtl8168d_3_hw_phy_config(ioaddr);
> break;
>
> default:
> @@ -2200,6 +3075,11 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
> tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
> if (!tp->pcie_cap && netif_msg_probe(tp))
> dev_info(&pdev->dev, "no PCI Express capability\n");
> + else {
> + pci_write_config_word(pdev, tp->pcie_cap + PCI_EXP_DEVSTA,
> + PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
> + PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
> + }
>
> RTL_W16(IntrMask, 0x0000);
>
> @@ -2863,6 +3743,8 @@ static void rtl_hw_start_8168(struct net_device *dev)
> break;
>
> case RTL_GIGA_MAC_VER_25:
> + case RTL_GIGA_MAC_VER_26:
> + case RTL_GIGA_MAC_VER_27:
> rtl_hw_start_8168d(ioaddr, pdev);
> break;
>
--
Simon Farnsworth
^ permalink raw reply
* Re: [net-next-2.6 PATCH 1/9] vxge: Modify __vxge_hw_device_is_privilaged() to not assume function-0 as privilaged function.
From: David Miller @ 2009-10-05 9:48 UTC (permalink / raw)
To: Sreenivasa.Honnur; +Cc: netdev, support
In-Reply-To: <78C9135A3D2ECE4B8162EBDCE82CAD7705C1618F@nekter>
From: "Sreenivasa Honnur" <Sreenivasa.Honnur@neterion.com>
Date: Mon, 5 Oct 2009 05:40:18 -0400
> I could apply these patches with "patch -p1 patch_file" command.
davem@sunset:~/src/GIT/net-next-2.6$ git am --signoff x.mbox
Applying: vxge: Modify __vxge_hw_device_is_privilaged() to not assume function-0 as privilaged function.
error: /drivers/net/vxge/vxge-config.c: does not exist in index
error: patch failed: drivers/net/vxge/vxge-config.c:461
error: drivers/net/vxge/vxge-config.c: patch does not apply
error: /drivers/net/vxge/vxge-version.h: does not exist in index
Patch failed at 0001 vxge: Modify __vxge_hw_device_is_privilaged() to not assume function-0 as privilaged function.
GIT is more strict than patch in many ways (not just in respect
to paths).
^ permalink raw reply
* [PATCH 1/4] ethoc: fix typo to compute number of tx descriptors
From: Thomas Chou @ 2009-10-05 9:33 UTC (permalink / raw)
Cc: netdev, Thomas Chou
It should be max() instead of min(). Use 1/4 of available
descriptors for tx, and there should be at least 2 tx
descriptors.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
drivers/net/ethoc.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index b7311bc..7475620 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -655,7 +655,7 @@ static int ethoc_open(struct net_device *dev)
/* calculate the number of TX/RX buffers */
num_bd = (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ;
- priv->num_tx = min(min_tx, num_bd / 4);
+ priv->num_tx = max(min_tx, num_bd / 4);
priv->num_rx = num_bd - priv->num_tx;
ethoc_write(priv, TX_BD_NUM, priv->num_tx);
--
1.6.2.5
^ permalink raw reply related
* [PATCH 3/4] ethoc: align received packet to make IP header at word boundary
From: Thomas Chou @ 2009-10-05 9:33 UTC (permalink / raw)
Cc: netdev, Thomas Chou
In-Reply-To: <1254735200-2718-2-git-send-email-thomas@wytron.com.tw>
The packet buffer is allocated at 4 bytes boundary, but the IP header
length and version bits is located at byte 14. These bit fields access
as 32 bits word and caused exception on processors that do not support
unaligned access.
The patch adds 2 bytes offset to make the bit fields word aligned.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
drivers/net/ethoc.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index f92747f..0c6c7f4 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -399,6 +399,10 @@ static int ethoc_rx(struct net_device *dev, int limit)
if (ethoc_update_rx_stats(priv, &bd) == 0) {
int size = bd.stat >> 16;
struct sk_buff *skb = netdev_alloc_skb(dev, size);
+
+ size -= 4; /* strip the CRC */
+ skb_reserve(skb, 2); /* align TCP/IP header */
+
if (likely(skb)) {
void *src = phys_to_virt(bd.addr);
memcpy_fromio(skb_put(skb, size), src, size);
--
1.6.2.5
^ permalink raw reply related
* [PATCH 2/4] ethoc: fix buffer address mapping
From: Thomas Chou @ 2009-10-05 9:33 UTC (permalink / raw)
Cc: netdev, Thomas Chou
In-Reply-To: <1254735200-2718-1-git-send-email-thomas@wytron.com.tw>
The pointer address in buffer descriptors is physical address. The
pointer that processor used to access packet is virtual address.
Though the higher bits of pointer address used by the MAC may be
truncated to zero in special case, it is not always true in larger
designs.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
drivers/net/ethoc.c | 7 +++----
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index 7475620..f92747f 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -284,7 +284,7 @@ static int ethoc_init_ring(struct ethoc *dev)
dev->cur_rx = 0;
/* setup transmission buffers */
- bd.addr = 0;
+ bd.addr = virt_to_phys(dev->membase);
bd.stat = TX_BD_IRQ | TX_BD_CRC;
for (i = 0; i < dev->num_tx; i++) {
@@ -295,7 +295,6 @@ static int ethoc_init_ring(struct ethoc *dev)
bd.addr += ETHOC_BUFSIZ;
}
- bd.addr = dev->num_tx * ETHOC_BUFSIZ;
bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
for (i = 0; i < dev->num_rx; i++) {
@@ -401,7 +400,7 @@ static int ethoc_rx(struct net_device *dev, int limit)
int size = bd.stat >> 16;
struct sk_buff *skb = netdev_alloc_skb(dev, size);
if (likely(skb)) {
- void *src = priv->membase + bd.addr;
+ void *src = phys_to_virt(bd.addr);
memcpy_fromio(skb_put(skb, size), src, size);
skb->protocol = eth_type_trans(skb, dev);
priv->stats.rx_packets++;
@@ -823,7 +822,7 @@ static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
else
bd.stat &= ~TX_BD_PAD;
- dest = priv->membase + bd.addr;
+ dest = phys_to_virt(bd.addr);
memcpy_toio(dest, skb->data, skb->len);
bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
--
1.6.2.5
^ permalink raw reply related
* [PATCH] net-next:can: add TI CAN (HECC) driver
From: Anant Gole @ 2009-10-05 10:02 UTC (permalink / raw)
To: netdev-u79uwXL29TY76Z2rM5mHXA
Cc: socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
linux-arm-kernel-xIg/pKzrS19vn6HldHNs0ANdhmdF6hFW
TI HECC (High End CAN Controller) module is found on many TI devices. It
has 32 hardware mailboxes with full implementation of CAN protocol 2.0B
with bus speeds up to 1Mbps. Specifications of the module are available
on TI web <http://www.ti.com>
Signed-off-by: Anant Gole <anantgole-l0cyMroinI0@public.gmane.org>
---
drivers/net/can/Kconfig | 7 +
drivers/net/can/Makefile | 1 +
drivers/net/can/ti_hecc.c | 1006 ++++++++++++++++++++++++++++++++++
include/linux/can/platform/ti_hecc.h | 40 ++
4 files changed, 1054 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/can/ti_hecc.c
create mode 100644 include/linux/can/platform/ti_hecc.h
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index df32c10..57a8733 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -95,6 +95,13 @@ config CAN_AT91
---help---
This is a driver for the SoC CAN controller in Atmel's AT91SAM9263.
+config CAN_TI_HECC
+ depends on CAN_DEV
+ tristate "TI High End CAN Controller"
+ ---help---
+ Driver for TI HECC (High End CAN Controller) module found on many
+ TI devices. The device specifications are available from www.ti.com
+
config CAN_DEBUG_DEVICES
bool "CAN devices debugging messages"
depends on CAN
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 0dea627..31f4ab5 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -11,5 +11,6 @@ obj-y += usb/
obj-$(CONFIG_CAN_SJA1000) += sja1000/
obj-$(CONFIG_CAN_AT91) += at91_can.o
+obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o
ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/ti_hecc.c b/drivers/net/can/ti_hecc.c
new file mode 100644
index 0000000..9090103
--- /dev/null
+++ b/drivers/net/can/ti_hecc.c
@@ -0,0 +1,1006 @@
+/*
+ * TI HECC (CAN) device driver
+ *
+ * This driver supports TI's HECC (High End CAN Controller module) and the
+ * specs for the same is available at <http://www.ti.com>
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/*
+ * Your platform definitions should specify module ram offsets and interrupt
+ * number to use as follows:
+ *
+ * static struct ti_hecc_platform_data am3517_evm_hecc_pdata = {
+ * .scc_hecc_offset = 0,
+ * .scc_ram_offset = 0x3000,
+ * .hecc_ram_offset = 0x3000,
+ * .mbx_offset = 0x2000,
+ * .int_line = 0,
+ * .revision = 1,
+ * };
+ *
+ * Please see include/can/platform/ti_hecc.h for description of above fields
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <linux/can.h>
+#include <linux/can/dev.h>
+#include <linux/can/error.h>
+#include <linux/can/platform/ti_hecc.h>
+
+#define DRV_NAME "ti_hecc"
+#define HECC_MODULE_VERSION "0.6"
+MODULE_VERSION(HECC_MODULE_VERSION);
+#define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
+
+/* TX / RX Mailbox Configuration */
+#define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
+#define MAX_TX_PRIO 0x3F /* hardware value - do not change */
+
+/*
+ * Important Note: TX mailbox configuration
+ * TX mailboxes should be restricted to the number of SKB buffers to avoid
+ * maintaining SKB buffers separately. TX mailboxes should be a power of 2
+ * for the mailbox logic to work. Top mailbox numbers are reserved for RX
+ * and lower mailboxes for TX.
+ *
+ * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT
+ * 4 (default) 2
+ * 8 3
+ * 16 4
+ */
+#define HECC_MB_TX_SHIFT 2 /* as per table above */
+#define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT)
+
+#if (HECC_MAX_TX_MBOX > CAN_ECHO_SKB_MAX)
+#error "HECC: MAX TX mailboxes should be equal or less than CAN_ECHO_SKB_MAX"
+#endif
+
+#define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT)
+#define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT)
+#define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
+#define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
+#define HECC_TX_MBOX_MASK (~(BIT(HECC_MAX_TX_MBOX) - 1))
+#define HECC_DEF_NAPI_WEIGHT HECC_MAX_RX_MBOX
+
+/*
+ * Important Note: RX mailbox configuration
+ * RX mailboxes are further logically split into two - main and buffer
+ * mailboxes. The goal is to get all packets into main mailboxes as
+ * driven by mailbox number and receive priority (higher to lower) and
+ * buffer mailboxes are used to receive pkts while main mailboxes are being
+ * processed. This ensures in-order packet reception.
+ *
+ * Here are the recommended values for buffer mailbox. Note that RX mailboxes
+ * start after TX mailboxes:
+ *
+ * HECC_MAX_RX_MBOX HECC_RX_BUFFER_MBOX No of buffer mailboxes
+ * 28 12 8
+ * 16 20 4
+ */
+
+#define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
+#define HECC_RX_BUFFER_MBOX 12 /* as per table above */
+#define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1)
+#define HECC_RX_HIGH_MBOX_MASK (~(BIT(HECC_RX_BUFFER_MBOX) - 1))
+
+/* TI HECC module registers */
+#define HECC_CANME 0x0 /* Mailbox enable */
+#define HECC_CANMD 0x4 /* Mailbox direction */
+#define HECC_CANTRS 0x8 /* Transmit request set */
+#define HECC_CANTRR 0xC /* Transmit request */
+#define HECC_CANTA 0x10 /* Transmission acknowledge */
+#define HECC_CANAA 0x14 /* Abort acknowledge */
+#define HECC_CANRMP 0x18 /* Receive message pending */
+#define HECC_CANRML 0x1C /* Remote message lost */
+#define HECC_CANRFP 0x20 /* Remote frame pending */
+#define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */
+#define HECC_CANMC 0x28 /* Master control */
+#define HECC_CANBTC 0x2C /* Bit timing configuration */
+#define HECC_CANES 0x30 /* Error and status */
+#define HECC_CANTEC 0x34 /* Transmit error counter */
+#define HECC_CANREC 0x38 /* Receive error counter */
+#define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */
+#define HECC_CANGIM 0x40 /* Global interrupt mask */
+#define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */
+#define HECC_CANMIM 0x48 /* Mailbox interrupt mask */
+#define HECC_CANMIL 0x4C /* Mailbox interrupt level */
+#define HECC_CANOPC 0x50 /* Overwrite protection control */
+#define HECC_CANTIOC 0x54 /* Transmit I/O control */
+#define HECC_CANRIOC 0x58 /* Receive I/O control */
+#define HECC_CANLNT 0x5C /* HECC only: Local network time */
+#define HECC_CANTOC 0x60 /* HECC only: Time-out control */
+#define HECC_CANTOS 0x64 /* HECC only: Time-out status */
+#define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */
+#define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */
+
+/* Mailbox registers */
+#define HECC_CANMID 0x0
+#define HECC_CANMCF 0x4
+#define HECC_CANMDL 0x8
+#define HECC_CANMDH 0xC
+
+#define HECC_SET_REG 0xFFFFFFFF
+#define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */
+#define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */
+
+#define HECC_CANMC_SCM BIT(13) /* SCC compat mode */
+#define HECC_CANMC_CCR BIT(12) /* Change config request */
+#define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */
+#define HECC_CANMC_ABO BIT(7) /* Auto Bus On */
+#define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */
+#define HECC_CANMC_SRES BIT(5) /* Software reset */
+
+#define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */
+#define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */
+
+#define HECC_CANMID_IDE BIT(31) /* Extended frame format */
+#define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */
+#define HECC_CANMID_AAM BIT(29) /* Auto answer mode */
+
+#define HECC_CANES_FE BIT(24) /* form error */
+#define HECC_CANES_BE BIT(23) /* bit error */
+#define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */
+#define HECC_CANES_CRCE BIT(21) /* CRC error */
+#define HECC_CANES_SE BIT(20) /* stuff bit error */
+#define HECC_CANES_ACKE BIT(19) /* ack error */
+#define HECC_CANES_BO BIT(18) /* Bus off status */
+#define HECC_CANES_EP BIT(17) /* Error passive status */
+#define HECC_CANES_EW BIT(16) /* Error warning status */
+#define HECC_CANES_SMA BIT(5) /* suspend mode ack */
+#define HECC_CANES_CCE BIT(4) /* Change config enabled */
+#define HECC_CANES_PDA BIT(3) /* Power down mode ack */
+
+#define HECC_CANBTC_SAM BIT(7) /* sample points */
+
+#define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\
+ HECC_CANES_CRCE | HECC_CANES_SE |\
+ HECC_CANES_ACKE)
+
+#define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */
+
+#define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */
+#define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */
+#define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */
+#define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */
+#define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */
+#define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */
+#define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */
+#define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */
+#define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */
+#define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */
+#define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */
+#define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */
+#define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */
+#define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */
+#define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */
+
+/* CAN Bittiming constants as per HECC specs */
+static struct can_bittiming_const ti_hecc_bittiming_const = {
+ .name = DRV_NAME,
+ .tseg1_min = 1,
+ .tseg1_max = 16,
+ .tseg2_min = 1,
+ .tseg2_max = 8,
+ .sjw_max = 4,
+ .brp_min = 1,
+ .brp_max = 256,
+ .brp_inc = 1,
+};
+
+struct ti_hecc_priv {
+ struct can_priv can; /* MUST be first member/field */
+ struct napi_struct napi;
+ struct net_device *ndev;
+ struct clk *clk;
+ void __iomem *base;
+ u32 scc_ram_offset;
+ u32 hecc_ram_offset;
+ u32 mbx_offset;
+ u32 int_line;
+ spinlock_t mbx_lock; /* CANME register needs protection */
+ u32 tx_head;
+ u32 tx_tail;
+ u32 rx_next;
+};
+
+static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
+{
+ return priv->tx_head & HECC_TX_MB_MASK;
+}
+
+static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
+{
+ return priv->tx_tail & HECC_TX_MB_MASK;
+}
+
+static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
+{
+ return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
+}
+
+static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
+{
+ __raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4);
+}
+
+static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
+ u32 reg, u32 val)
+{
+ __raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 +
+ reg);
+}
+
+static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
+{
+ return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 +
+ reg);
+}
+
+static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
+{
+ __raw_writel(val, priv->base + reg);
+}
+
+static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
+{
+ return __raw_readl(priv->base + reg);
+}
+
+static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
+ u32 bit_mask)
+{
+ hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
+}
+
+static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
+ u32 bit_mask)
+{
+ hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
+}
+
+static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
+{
+ return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
+}
+
+static int ti_hecc_get_state(const struct net_device *ndev,
+ enum can_state *state)
+{
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+ *state = priv->can.state;
+ return 0;
+}
+
+static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
+{
+ struct can_bittiming *bit_timing = &priv->can.bittiming;
+ u32 can_btc;
+
+ can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
+ can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
+ & 0xF) << 3;
+ if (bit_timing->brp > 4 && priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
+ can_btc |= HECC_CANBTC_SAM;
+ else
+ dev_info(priv->ndev->dev.parent,
+ "WARN: Triple sampling not set due to h/w limitations"
+ " at %d bitrate", bit_timing->bitrate);
+
+ can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
+ can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
+
+ /* ERM being set to 0 by default meaning resync at falling edge */
+
+ hecc_write(priv, HECC_CANBTC, can_btc);
+ dev_info(priv->ndev->dev.parent, "setting CANBTC=%#x\n", can_btc);
+
+ return 0;
+}
+
+static void ti_hecc_reset(struct net_device *ndev)
+{
+ u32 cnt;
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+
+ dev_dbg(ndev->dev.parent, "resetting hecc ...\n");
+ hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
+
+ /* Set change control request and wait till enabled */
+ hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
+
+ /*
+ * INFO: It has been observed that at times CCE bit may not be
+ * set and hw seems to be ok even if this bit is not set so
+ * timing out with a timing of 1ms to respect the specs
+ */
+ cnt = HECC_CCE_WAIT_COUNT;
+ while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
+ --cnt;
+ udelay(10);
+ }
+
+ /*
+ * Note: On HECC, BTC can be programmed only in initialization mode, so
+ * it is expected that the can bittiming parameters are set via ip
+ * utility before the device is opened
+ */
+ ti_hecc_set_btc(priv);
+
+ /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
+ hecc_write(priv, HECC_CANMC, 0);
+
+ /*
+ * INFO: CAN net stack handles bus off and hence disabling auto-bus-on
+ * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
+ */
+
+ /*
+ * INFO: It has been observed that at times CCE bit may not be
+ * set and hw seems to be ok even if this bit is not set so
+ */
+ cnt = HECC_CCE_WAIT_COUNT;
+ while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
+ --cnt;
+ udelay(10);
+ }
+
+ /* Enable TX and RX I/O Control pins */
+ hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
+ hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
+
+ /* Clear registers for clean operation */
+ hecc_write(priv, HECC_CANTA, HECC_SET_REG);
+ hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
+ hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
+ hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
+ hecc_write(priv, HECC_CANME, 0);
+ hecc_write(priv, HECC_CANMD, 0);
+
+ /* SCC compat mode NOT supported (and not needed too) */
+ hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
+}
+
+static void ti_hecc_start(struct net_device *ndev)
+{
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+ u32 cnt, mbxno, mbx_mask;
+
+ /* put HECC in initialization mode and set btc */
+ ti_hecc_reset(ndev);
+
+ priv->tx_head = priv->tx_tail = HECC_TX_MASK;
+ priv->rx_next = HECC_RX_FIRST_MBOX;
+
+ /* Enable local and global acceptance mask registers */
+ hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
+
+ /* Prepare configured mailboxes to receive messages */
+ for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
+ mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
+ mbx_mask = BIT(mbxno);
+ hecc_clear_bit(priv, HECC_CANME, mbx_mask);
+ hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
+ hecc_write_lam(priv, mbxno, HECC_SET_REG);
+ hecc_set_bit(priv, HECC_CANMD, mbx_mask);
+ hecc_set_bit(priv, HECC_CANME, mbx_mask);
+ hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
+ }
+
+ /* Prevent message over-write & Enable interrupts */
+ hecc_write(priv, HECC_CANOPC, HECC_SET_REG);
+ if (priv->int_line) {
+ hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
+ hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
+ HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
+ } else {
+ hecc_write(priv, HECC_CANMIL, 0);
+ hecc_write(priv, HECC_CANGIM,
+ HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
+ }
+ priv->can.state = CAN_STATE_ERROR_ACTIVE;
+}
+
+static void ti_hecc_stop(struct net_device *ndev)
+{
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+
+ /* Disable interrupts and disable mailboxes */
+ hecc_write(priv, HECC_CANGIM, 0);
+ hecc_write(priv, HECC_CANMIM, 0);
+ hecc_write(priv, HECC_CANME, 0);
+ priv->can.state = CAN_STATE_STOPPED;
+}
+
+static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+ int ret = 0;
+
+ switch (mode) {
+ case CAN_MODE_START:
+ ti_hecc_start(ndev);
+ netif_wake_queue(ndev);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * ti_hecc_xmit: HECC Transmit
+ *
+ * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
+ * priority of the mailbox for tranmission is dependent upon priority setting
+ * field in mailbox registers. The mailbox with highest value in priority field
+ * is transmitted first. Only when two mailboxes have the same value in
+ * priority field the highest numbered mailbox is transmitted first.
+ *
+ * To utilize the HECC priority feature as described above we start with the
+ * highest numbered mailbox with highest priority level and move on to the next
+ * mailbox with the same priority level and so on. Once we loop through all the
+ * transmit mailboxes we choose the next priority level (lower) and so on
+ * until we reach the lowest priority level on the lowest numbered mailbox
+ * when we stop transmission until all mailboxes are transmitted and then
+ * restart at highest numbered mailbox with highest priority.
+ *
+ * Two counters (head and tail) are used to track the next mailbox to transmit
+ * and to track the echo buffer for already transmitted mailbox. The queue
+ * is stopped when all the mailboxes are busy or when there is a priority
+ * value roll-over happens.
+ */
+static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+ struct can_frame *cf = (struct can_frame *)skb->data;
+ u32 mbxno, mbx_mask, data;
+ unsigned long flags;
+
+ mbxno = get_tx_head_mb(priv);
+ mbx_mask = BIT(mbxno);
+ spin_lock_irqsave(&priv->mbx_lock, flags);
+ if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
+ spin_unlock_irqrestore(&priv->mbx_lock, flags);
+ netif_stop_queue(ndev);
+ dev_err(priv->ndev->dev.parent,
+ "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
+ priv->tx_head, priv->tx_tail);
+ return NETDEV_TX_BUSY;
+ }
+ spin_unlock_irqrestore(&priv->mbx_lock, flags);
+
+ /* Prepare mailbox for transmission */
+ data = min_t(u8, cf->can_dlc, 8);
+ if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
+ data |= HECC_CANMCF_RTR;
+ data |= get_tx_head_prio(priv) << 8;
+ hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
+
+ if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
+ data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
+ else /* Standard frame format */
+ data = (cf->can_id & CAN_SFF_MASK) << 18;
+ hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
+ hecc_write_mbx(priv, mbxno, HECC_CANMDL,
+ be32_to_cpu(*(u32 *)(cf->data)));
+ if (cf->can_dlc > 4) {
+ hecc_write_mbx(priv, mbxno, HECC_CANMDH,
+ be32_to_cpu(*(u32 *)(cf->data + 4)));
+ } else {
+ *(u32 *)(cf->data + 4) = 0;
+ }
+ can_put_echo_skb(skb, ndev, mbxno);
+
+ spin_lock_irqsave(&priv->mbx_lock, flags);
+ --priv->tx_head;
+ if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
+ (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
+ netif_stop_queue(ndev);
+ }
+ hecc_set_bit(priv, HECC_CANME, mbx_mask);
+ spin_unlock_irqrestore(&priv->mbx_lock, flags);
+
+ hecc_clear_bit(priv, HECC_CANMD, mbx_mask);
+ hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
+ hecc_write(priv, HECC_CANTRS, mbx_mask);
+
+ return NETDEV_TX_OK;
+}
+
+static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno)
+{
+ struct net_device_stats *stats = &priv->ndev->stats;
+ struct can_frame *cf;
+ struct sk_buff *skb;
+ u32 data, mbx_mask;
+ unsigned long flags;
+
+ skb = netdev_alloc_skb(priv->ndev, sizeof(struct can_frame));
+ if (!skb) {
+ if (printk_ratelimit())
+ dev_err(priv->ndev->dev.parent,
+ "ti_hecc_rx_pkt: netdev_alloc_skb() failed\n");
+ return -ENOMEM;
+ }
+ skb->protocol = htons(ETH_P_CAN);
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+ mbx_mask = BIT(mbxno);
+ cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame));
+ data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
+ if (data & HECC_CANMID_IDE)
+ cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
+ else
+ cf->can_id = (data >> 18) & CAN_SFF_MASK;
+ data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
+ if (data & HECC_CANMCF_RTR)
+ cf->can_id |= CAN_RTR_FLAG;
+ cf->can_dlc = data & 0xF;
+ data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
+ *(u32 *)(cf->data) = cpu_to_be32(data);
+ if (cf->can_dlc > 4) {
+ data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
+ *(u32 *)(cf->data + 4) = cpu_to_be32(data);
+ } else {
+ *(u32 *)(cf->data + 4) = 0;
+ }
+ spin_lock_irqsave(&priv->mbx_lock, flags);
+ hecc_clear_bit(priv, HECC_CANME, mbx_mask);
+ hecc_write(priv, HECC_CANRMP, mbx_mask);
+ /* enable mailbox only if it is part of rx buffer mailboxes */
+ if (priv->rx_next < HECC_RX_BUFFER_MBOX)
+ hecc_set_bit(priv, HECC_CANME, mbx_mask);
+ spin_unlock_irqrestore(&priv->mbx_lock, flags);
+
+ stats->rx_bytes += cf->can_dlc;
+ netif_receive_skb(skb);
+ stats->rx_packets++;
+
+ return 0;
+}
+
+/*
+ * ti_hecc_rx_poll - HECC receive pkts
+ *
+ * The receive mailboxes start from highest numbered mailbox till last xmit
+ * mailbox. On CAN frame reception the hardware places the data into highest
+ * numbered mailbox that matches the CAN ID filter. Since all receive mailboxes
+ * have same filtering (ALL CAN frames) packets will arrive in the highest
+ * available RX mailbox and we need to ensure in-order packet reception.
+ *
+ * To ensure the packets are received in the right order we logically divide
+ * the RX mailboxes into main and buffer mailboxes. Packets are received as per
+ * mailbox priotity (higher to lower) in the main bank and once it is full we
+ * disable further reception into main mailboxes. While the main mailboxes are
+ * processed in NAPI, further packets are received in buffer mailboxes.
+ *
+ * We maintain a RX next mailbox counter to process packets and once all main
+ * mailboxe packets are passed to the upper stack we enable all of them but
+ * continue to process packets received in buffer mailboxes. With each packet
+ * received from buffer mailbox we enable it immediately so as to handle the
+ * overflow from higher mailboxes.
+ */
+static int ti_hecc_rx_poll(struct napi_struct *napi, int quota)
+{
+ struct net_device *ndev = napi->dev;
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+ u32 num_pkts = 0;
+ u32 mbx_mask;
+ unsigned long pending_pkts, flags;
+
+ if (!netif_running(ndev))
+ return 0;
+
+ while ((pending_pkts = hecc_read(priv, HECC_CANRMP)) &&
+ num_pkts < quota) {
+ mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */
+ if (mbx_mask & pending_pkts) {
+ if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0)
+ return num_pkts;
+ ++num_pkts;
+ } else if (priv->rx_next > HECC_RX_BUFFER_MBOX) {
+ break; /* pkt not received yet */
+ }
+ --priv->rx_next;
+ if (priv->rx_next == HECC_RX_BUFFER_MBOX) {
+ /* enable high bank mailboxes */
+ spin_lock_irqsave(&priv->mbx_lock, flags);
+ mbx_mask = hecc_read(priv, HECC_CANME);
+ mbx_mask |= HECC_RX_HIGH_MBOX_MASK;
+ hecc_write(priv, HECC_CANME, mbx_mask);
+ spin_unlock_irqrestore(&priv->mbx_lock, flags);
+ } else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) {
+ priv->rx_next = HECC_RX_FIRST_MBOX;
+ break;
+ }
+ }
+
+ /* Enable packet interrupt if all pkts are handled */
+ if (hecc_read(priv, HECC_CANRMP) == 0) {
+ napi_complete(napi);
+ /* Re-enable RX mailbox interrupts */
+ mbx_mask = hecc_read(priv, HECC_CANMIM);
+ mbx_mask |= HECC_TX_MBOX_MASK;
+ hecc_write(priv, HECC_CANMIM, mbx_mask);
+ }
+
+ return num_pkts;
+}
+
+static int ti_hecc_error(struct net_device *ndev, int int_status,
+ int err_status)
+{
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &ndev->stats;
+ struct can_frame *cf;
+ struct sk_buff *skb;
+
+ /* propogate the error condition to the can stack */
+ skb = netdev_alloc_skb(ndev, sizeof(struct can_frame));
+ if (!skb) {
+ if (printk_ratelimit())
+ dev_err(priv->ndev->dev.parent,
+ "ti_hecc_error: netdev_alloc_skb() failed\n");
+ return -ENOMEM;
+ }
+ skb->protocol = htons(ETH_P_CAN);
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame));
+ memset(cf, 0, sizeof(struct can_frame));
+ cf->can_id = CAN_ERR_FLAG;
+ cf->can_dlc = CAN_ERR_DLC;
+
+ if (int_status & HECC_CANGIF_WLIF) { /* warning level int */
+ if ((int_status & HECC_CANGIF_BOIF) == 0) {
+ priv->can.state = CAN_STATE_ERROR_WARNING;
+ ++priv->can.can_stats.error_warning;
+ cf->can_id |= CAN_ERR_CRTL;
+ if (hecc_read(priv, HECC_CANTEC) > 96)
+ cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
+ if (hecc_read(priv, HECC_CANREC) > 96)
+ cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
+ }
+ hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW);
+ dev_dbg(priv->ndev->dev.parent, "Error Warning interrupt\n");
+ hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
+ }
+
+ if (int_status & HECC_CANGIF_EPIF) { /* error passive int */
+ if ((int_status & HECC_CANGIF_BOIF) == 0) {
+ priv->can.state = CAN_STATE_ERROR_PASSIVE;
+ ++priv->can.can_stats.error_passive;
+ cf->can_id |= CAN_ERR_CRTL;
+ if (hecc_read(priv, HECC_CANTEC) > 127)
+ cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
+ if (hecc_read(priv, HECC_CANREC) > 127)
+ cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
+ }
+ hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP);
+ dev_dbg(priv->ndev->dev.parent, "Error passive interrupt\n");
+ hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
+ }
+
+ /*
+ * Need to check busoff condition in error status register too to
+ * ensure warning interrupts don't hog the system
+ */
+ if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) {
+ priv->can.state = CAN_STATE_BUS_OFF;
+ cf->can_id |= CAN_ERR_BUSOFF;
+ hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO);
+ hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
+ /* Disable all interrupts in bus-off to avoid int hog */
+ hecc_write(priv, HECC_CANGIM, 0);
+ can_bus_off(ndev);
+ }
+
+ if (err_status & HECC_BUS_ERROR) {
+ ++priv->can.can_stats.bus_error;
+ cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
+ cf->data[2] |= CAN_ERR_PROT_UNSPEC;
+ if (err_status & HECC_CANES_FE) {
+ hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE);
+ cf->data[2] |= CAN_ERR_PROT_FORM;
+ }
+ if (err_status & HECC_CANES_BE) {
+ hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE);
+ cf->data[2] |= CAN_ERR_PROT_BIT;
+ }
+ if (err_status & HECC_CANES_SE) {
+ hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE);
+ cf->data[2] |= CAN_ERR_PROT_STUFF;
+ }
+ if (err_status & HECC_CANES_CRCE) {
+ hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE);
+ cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
+ CAN_ERR_PROT_LOC_CRC_DEL;
+ }
+ if (err_status & HECC_CANES_ACKE) {
+ hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE);
+ cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
+ CAN_ERR_PROT_LOC_ACK_DEL;
+ }
+ }
+
+ netif_receive_skb(skb);
+ stats->rx_packets++;
+ stats->rx_bytes += cf->can_dlc;
+ return 0;
+}
+
+static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &ndev->stats;
+ u32 mbxno, mbx_mask, int_status, err_status;
+ unsigned long ack, flags;
+
+ int_status = hecc_read(priv,
+ (priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0);
+
+ if (!int_status)
+ return IRQ_NONE;
+
+ err_status = hecc_read(priv, HECC_CANES);
+ if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO |
+ HECC_CANES_EP | HECC_CANES_EW))
+ ti_hecc_error(ndev, int_status, err_status);
+
+ if (int_status & HECC_CANGIF_GMIF) {
+ while (priv->tx_tail - priv->tx_head > 0) {
+ mbxno = get_tx_tail_mb(priv);
+ mbx_mask = BIT(mbxno);
+ if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
+ break;
+ hecc_clear_bit(priv, HECC_CANMIM, mbx_mask);
+ hecc_write(priv, HECC_CANTA, mbx_mask);
+ spin_lock_irqsave(&priv->mbx_lock, flags);
+ hecc_clear_bit(priv, HECC_CANME, mbx_mask);
+ spin_unlock_irqrestore(&priv->mbx_lock, flags);
+ stats->tx_bytes += hecc_read_mbx(priv, mbxno,
+ HECC_CANMCF) & 0xF;
+ stats->tx_packets++;
+ can_get_echo_skb(ndev, mbxno);
+ --priv->tx_tail;
+ }
+
+ /* restart queue if wrap-up or if queue stalled on last pkt */
+ if (((priv->tx_head == priv->tx_tail) &&
+ ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
+ (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
+ ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
+ netif_wake_queue(ndev);
+
+ /* Disable RX mailbox interrupts and let NAPI reenable them */
+ if (hecc_read(priv, HECC_CANRMP)) {
+ ack = hecc_read(priv, HECC_CANMIM);
+ ack &= BIT(HECC_MAX_TX_MBOX) - 1;
+ hecc_write(priv, HECC_CANMIM, ack);
+ napi_schedule(&priv->napi);
+ }
+ }
+
+ /* clear all interrupt conditions - read back to avoid spurious ints */
+ if (priv->int_line) {
+ hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
+ int_status = hecc_read(priv, HECC_CANGIF1);
+ } else {
+ hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
+ int_status = hecc_read(priv, HECC_CANGIF0);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int ti_hecc_open(struct net_device *ndev)
+{
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+ int err;
+
+ err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
+ ndev->name, ndev);
+ if (err) {
+ dev_err(ndev->dev.parent, "error requesting interrupt\n");
+ return err;
+ }
+
+ /* Open common can device */
+ err = open_candev(ndev);
+ if (err) {
+ dev_err(ndev->dev.parent, "open_candev() failed %d\n", err);
+ free_irq(ndev->irq, ndev);
+ return err;
+ }
+
+ clk_enable(priv->clk);
+ ti_hecc_start(ndev);
+ napi_enable(&priv->napi);
+ netif_start_queue(ndev);
+
+ return 0;
+}
+
+static int ti_hecc_close(struct net_device *ndev)
+{
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+
+ netif_stop_queue(ndev);
+ napi_disable(&priv->napi);
+ ti_hecc_stop(ndev);
+ free_irq(ndev->irq, ndev);
+ clk_disable(priv->clk);
+ close_candev(ndev);
+
+ return 0;
+}
+
+static const struct net_device_ops ti_hecc_netdev_ops = {
+ .ndo_open = ti_hecc_open,
+ .ndo_stop = ti_hecc_close,
+ .ndo_start_xmit = ti_hecc_xmit,
+};
+
+static int ti_hecc_probe(struct platform_device *pdev)
+{
+ struct net_device *ndev = (struct net_device *)0;
+ struct ti_hecc_priv *priv;
+ struct ti_hecc_platform_data *pdata;
+ struct resource *mem, *irq;
+ void __iomem *addr;
+ int err = -ENODEV;
+
+ pdata = pdev->dev.platform_data;
+ if (!pdata) {
+ dev_err(&pdev->dev, "No platform data\n");
+ goto probe_exit;
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem) {
+ dev_err(&pdev->dev, "No mem resources\n");
+ goto probe_exit;
+ }
+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!irq) {
+ dev_err(&pdev->dev, "No irq resource\n");
+ goto probe_exit;
+ }
+ if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) {
+ dev_err(&pdev->dev, "HECC region already claimed\n");
+ err = -EBUSY;
+ goto probe_exit;
+ }
+ addr = ioremap(mem->start, resource_size(mem));
+ if (!addr) {
+ dev_err(&pdev->dev, "ioremap failed\n");
+ err = -ENOMEM;
+ goto probe_exit_free_region;
+ }
+
+ ndev = alloc_candev(sizeof(struct ti_hecc_priv));
+ if (!ndev) {
+ dev_err(&pdev->dev, "alloc_candev failed\n");
+ err = -ENOMEM;
+ goto probe_exit_iounmap;
+ }
+
+ priv = netdev_priv(ndev);
+ priv->ndev = ndev;
+ priv->base = addr;
+ priv->scc_ram_offset = pdata->scc_ram_offset;
+ priv->hecc_ram_offset = pdata->hecc_ram_offset;
+ priv->mbx_offset = pdata->mbx_offset;
+ priv->int_line = pdata->int_line;
+
+ priv->can.bittiming_const = &ti_hecc_bittiming_const;
+ priv->can.do_set_mode = ti_hecc_do_set_mode;
+ priv->can.do_get_state = ti_hecc_get_state;
+
+ ndev->irq = irq->start;
+ ndev->flags |= IFF_ECHO;
+ platform_set_drvdata(pdev, ndev);
+ SET_NETDEV_DEV(ndev, &pdev->dev);
+ ndev->netdev_ops = &ti_hecc_netdev_ops;
+
+ priv->clk = clk_get(&pdev->dev, "hecc_ck");
+ if (IS_ERR(priv->clk)) {
+ dev_err(&pdev->dev, "No clock available\n");
+ err = PTR_ERR(priv->clk);
+ priv->clk = NULL;
+ goto probe_exit_candev;
+ }
+ priv->can.clock.freq = clk_get_rate(priv->clk);
+ netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll,
+ HECC_DEF_NAPI_WEIGHT);
+
+ err = register_candev(ndev);
+ if (err) {
+ dev_err(&pdev->dev, "register_candev() failed\n");
+ goto probe_exit_clk;
+ }
+ dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
+ priv->base, (u32) ndev->irq);
+
+ return 0;
+
+probe_exit_clk:
+ clk_put(priv->clk);
+probe_exit_candev:
+ free_candev(ndev);
+probe_exit_iounmap:
+ iounmap(addr);
+probe_exit_free_region:
+ release_mem_region(mem->start, resource_size(mem));
+probe_exit:
+ return err;
+}
+
+static int __devexit ti_hecc_remove(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct ti_hecc_priv *priv = netdev_priv(ndev);
+
+ clk_put(priv->clk);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ iounmap(priv->base);
+ release_mem_region(res->start, resource_size(res));
+ unregister_candev(ndev);
+ free_candev(ndev);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+/* TI HECC netdevice driver: platform driver structure */
+static struct platform_driver ti_hecc_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ },
+ .probe = ti_hecc_probe,
+ .remove = __devexit_p(ti_hecc_remove),
+};
+
+static int __init ti_hecc_init_driver(void)
+{
+ printk(KERN_INFO DRV_DESC "\n");
+ return platform_driver_register(&ti_hecc_driver);
+}
+module_init(ti_hecc_init_driver);
+
+static void __exit ti_hecc_exit_driver(void)
+{
+ printk(KERN_INFO DRV_DESC " unloaded\n");
+ platform_driver_unregister(&ti_hecc_driver);
+}
+module_exit(ti_hecc_exit_driver);
+
+MODULE_AUTHOR("Anant Gole <anantgole-l0cyMroinI0@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION(DRV_DESC);
diff --git a/include/linux/can/platform/ti_hecc.h b/include/linux/can/platform/ti_hecc.h
new file mode 100644
index 0000000..4688c7b
--- /dev/null
+++ b/include/linux/can/platform/ti_hecc.h
@@ -0,0 +1,40 @@
+/*
+ * TI HECC (High End CAN Controller) driver platform header
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/**
+ * struct hecc_platform_data - HECC Platform Data
+ *
+ * @scc_hecc_offset: mostly 0 - should really never change
+ * @scc_ram_offset: SCC RAM offset
+ * @hecc_ram_offset: HECC RAM offset
+ * @mbx_offset: Mailbox RAM offset
+ * @int_line: Interrupt line to use - 0 or 1
+ * @version: version for future use
+ *
+ * Platform data structure to get all platform specific settings.
+ * this structure also accounts the fact that the IP may have different
+ * RAM and mailbox offsets for different SOC's
+ */
+struct ti_hecc_platform_data {
+ u32 scc_hecc_offset;
+ u32 scc_ram_offset;
+ u32 hecc_ram_offset;
+ u32 mbx_offset;
+ u32 int_line;
+ u32 version;
+};
+
+
--
1.6.2.4
^ permalink raw reply related
* [PATCH 4/4] ethoc: use system memory as buffer
From: Thomas Chou @ 2009-10-05 9:33 UTC (permalink / raw)
Cc: netdev, Thomas Chou
In-Reply-To: <1254735200-2718-3-git-send-email-thomas@wytron.com.tw>
This patch enabled the ethoc to allocate system memory as buffer
when there is no dedicated buffer memory.
Some hardware designs may not have dedicated buffer memory such as
on chip or off chip SRAM. In this case, only one memory resource is
supplied in the platform data instead of two. Then a DMA buffer can
be allocated from system memory and used for the transfer.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
drivers/net/ethoc.c | 64 +++++++++++++++++++++++++++++++++++----------------
1 files changed, 44 insertions(+), 20 deletions(-)
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index 0c6c7f4..6d82dc6 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -19,6 +19,10 @@
#include <linux/platform_device.h>
#include <net/ethoc.h>
+static int buffer_size = 0x8000; /* 32 KBytes */
+module_param(buffer_size, int, 0);
+MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
+
/* register offsets */
#define MODER 0x00
#define INT_SOURCE 0x04
@@ -167,6 +171,7 @@
* struct ethoc - driver-private device structure
* @iobase: pointer to I/O memory region
* @membase: pointer to buffer memory region
+ * @dma_alloc: dma allocated buffer size
* @num_tx: number of send buffers
* @cur_tx: last send buffer written
* @dty_tx: last buffer actually sent
@@ -185,6 +190,7 @@
struct ethoc {
void __iomem *iobase;
void __iomem *membase;
+ int dma_alloc;
unsigned int num_tx;
unsigned int cur_tx;
@@ -906,22 +912,19 @@ static int ethoc_probe(struct platform_device *pdev)
/* obtain buffer memory space */
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (!res) {
- dev_err(&pdev->dev, "cannot obtain memory space\n");
- ret = -ENXIO;
- goto free;
- }
-
- mem = devm_request_mem_region(&pdev->dev, res->start,
+ if (res) {
+ mem = devm_request_mem_region(&pdev->dev, res->start,
res->end - res->start + 1, res->name);
- if (!mem) {
- dev_err(&pdev->dev, "cannot request memory space\n");
- ret = -ENXIO;
- goto free;
+ if (!mem) {
+ dev_err(&pdev->dev, "cannot request memory space\n");
+ ret = -ENXIO;
+ goto free;
+ }
+
+ netdev->mem_start = mem->start;
+ netdev->mem_end = mem->end;
}
- netdev->mem_start = mem->start;
- netdev->mem_end = mem->end;
/* obtain device IRQ number */
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -936,6 +939,7 @@ static int ethoc_probe(struct platform_device *pdev)
/* setup driver-private data */
priv = netdev_priv(netdev);
priv->netdev = netdev;
+ priv->dma_alloc = 0;
priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
mmio->end - mmio->start + 1);
@@ -945,12 +949,27 @@ static int ethoc_probe(struct platform_device *pdev)
goto error;
}
- priv->membase = devm_ioremap_nocache(&pdev->dev, netdev->mem_start,
- mem->end - mem->start + 1);
- if (!priv->membase) {
- dev_err(&pdev->dev, "cannot remap memory space\n");
- ret = -ENXIO;
- goto error;
+ if (netdev->mem_end) {
+ priv->membase = devm_ioremap_nocache(&pdev->dev,
+ netdev->mem_start, mem->end - mem->start + 1);
+ if (!priv->membase) {
+ dev_err(&pdev->dev, "cannot remap memory space\n");
+ ret = -ENXIO;
+ goto error;
+ }
+ } else {
+ /* Allocate buffer memory */
+ priv->membase = dma_alloc_coherent(NULL,
+ buffer_size, (void *)&netdev->mem_start,
+ GFP_KERNEL);
+ if (!priv->membase) {
+ dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
+ buffer_size);
+ ret = -ENOMEM;
+ goto error;
+ }
+ netdev->mem_end = netdev->mem_start + buffer_size;
+ priv->dma_alloc = buffer_size;
}
/* Allow the platform setup code to pass in a MAC address. */
@@ -1037,6 +1056,9 @@ free_mdio:
kfree(priv->mdio->irq);
mdiobus_free(priv->mdio);
free:
+ if (priv->dma_alloc)
+ dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
+ netdev->mem_start);
free_netdev(netdev);
out:
return ret;
@@ -1062,7 +1084,9 @@ static int ethoc_remove(struct platform_device *pdev)
kfree(priv->mdio->irq);
mdiobus_free(priv->mdio);
}
-
+ if (priv->dma_alloc)
+ dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
+ netdev->mem_start);
unregister_netdev(netdev);
free_netdev(netdev);
}
--
1.6.2.5
^ permalink raw reply related
* RE: [net-next-2.6 PATCH 1/9] vxge: Modify __vxge_hw_device_is_privilaged() to not assume function-0 as privilaged function.
From: Sreenivasa Honnur @ 2009-10-05 10:07 UTC (permalink / raw)
To: David Miller; +Cc: netdev, support
In-Reply-To: <20091005.024837.62378837.davem@davemloft.net>
OK, I will re-create and submit them again.
-----Original Message-----
From: David Miller [mailto:davem@davemloft.net]
Sent: Monday, October 05, 2009 3:19 PM
To: Sreenivasa Honnur
Cc: netdev@vger.kernel.org; support
Subject: Re: [net-next-2.6 PATCH 1/9] vxge: Modify
__vxge_hw_device_is_privilaged() to not assume function-0 as privilaged
function.
From: "Sreenivasa Honnur" <Sreenivasa.Honnur@neterion.com>
Date: Mon, 5 Oct 2009 05:40:18 -0400
> I could apply these patches with "patch -p1 patch_file" command.
davem@sunset:~/src/GIT/net-next-2.6$ git am --signoff x.mbox
Applying: vxge: Modify __vxge_hw_device_is_privilaged() to not assume
function-0 as privilaged function.
error: /drivers/net/vxge/vxge-config.c: does not exist in index
error: patch failed: drivers/net/vxge/vxge-config.c:461
error: drivers/net/vxge/vxge-config.c: patch does not apply
error: /drivers/net/vxge/vxge-version.h: does not exist in index Patch
failed at 0001 vxge: Modify __vxge_hw_device_is_privilaged() to not
assume function-0 as privilaged function.
GIT is more strict than patch in many ways (not just in respect to
paths).
^ permalink raw reply
* net-next-2.6 is open...
From: David Miller @ 2009-10-05 10:36 UTC (permalink / raw)
To: netdev
As people have probably noticed net-next-2.6 is open for business
at the usual location:
git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6.git
Pace yourselves and don't let net-next-2.6 development get in the way
of fixing net-2.6 bugs. :-)
Thanks!
^ permalink raw reply
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