* Re: [PATCH net-next-2.6] bridge: 64bit rx/tx counters
From: Andrew Morton @ 2010-08-12 15:07 UTC (permalink / raw)
To: Eric Dumazet
Cc: David Miller, Stephen Hemminger, netdev, bhutchings, Nick Piggin
In-Reply-To: <1281615375.2494.20.camel@edumazet-laptop>
On Thu, 12 Aug 2010 14:16:15 +0200 Eric Dumazet <eric.dumazet@gmail.com> wrote:
> > And all this open-coded per-cpu counter stuff added all over the place.
> > Were percpu_counters tested or reviewed and found inadequate and unfixable?
> > If so, please do tell.
> >
>
> percpu_counters tries hard to maintain a view of the current value of
> the (global) counter. This adds a cost because of a shared cache line
> and locking. (__percpu_counter_sum() is not very scalable on big hosts,
> it locks the percpu_counter lock for a possibly long iteration)
Could be. Is percpu_counter_read_positive() unsuitable?
>
> For network stats we dont want to maintain this central value, we do the
> folding only when necessary.
hm. Well, why? That big walk across all possible CPUs could be really
expensive for some applications. Especially if num_possible_cpus is
much larger than num_online_cpus, which iirc can happen in
virtualisation setups; probably it can happen in non-virtualised
machines too.
> And this folding has zero effect on
> concurrent writers (counter updates)
The fastpath looks a little expensive in the code you've added. The
write_seqlock() does an rmw and a wmb() and the stats inc is a 64-bit
rmw whereas percpu_counters do a simple 32-bit add. So I'd expect that
at some suitable batch value, percpu-counters are faster on 32-bit.
They'll usually be slower on 64-bit, until that num_possible_cpus walk
bites you.
percpu_counters might need some work to make them irq-friendly. That
bare spin_lock().
btw, I worry a bit about seqlocks in the presence of interrupts:
static inline void write_seqcount_begin(seqcount_t *s)
{
s->sequence++;
smp_wmb();
}
are we assuming that the ++ there is atomic wrt interrupts? I think
so. Is that always true for all architectures, compiler versions, etc?
> For network stack, we also need to update two values, a packet counter
> and a bytes counter. percpu_counter is not very good for the 'bytes
> counter', since we would have to use a arbitrary big bias value.
OK, that's a nasty problem for percpu-counters.
> Using several percpu_counter would also probably use more cache lines.
>
> Also please note this stuff is only needed for 32bit arches.
>
> Using percpu_counter would slow down network stack on modern arches.
Was this ever quantified?
>
> I am very well aware of the percpu_counter stuff, I believe I tried to
> optimize it a bit in the past.
^ permalink raw reply
* Re: [Bugme-new] [Bug 16568] New: Regression and incompatibility with Windows SP2-SP3-Vista TCP stack causing lost connections
From: Eric Dumazet @ 2010-08-12 15:09 UTC (permalink / raw)
To: Andrew Morton; +Cc: netdev, bugzilla-daemon, bugme-daemon, yuriy
In-Reply-To: <20100812074041.cf62b793.akpm@linux-foundation.org>
Le jeudi 12 août 2010 à 07:40 -0700, Andrew Morton a écrit :
> (switched to email. Please respond via emailed reply-to-all, not via the
> bugzilla web interface).
>
>
> On Thu, 12 Aug 2010 08:20:01 GMT bugzilla-daemon@bugzilla.kernel.org wrote:
>
> > https://bugzilla.kernel.org/show_bug.cgi?id=16568
> >
> > Summary: Regression and incompatibility with Windows
> > SP2-SP3-Vista TCP stack causing lost connections
> > Product: Networking
> > Version: 2.5
> > Kernel Version: 2.6.30+
> > Platform: All
> > OS/Version: Linux
> > Tree: Mainline
> > Status: NEW
> > Severity: high
> > Priority: P1
> > Component: IPV4
> > AssignedTo: shemminger@linux-foundation.org
> > ReportedBy: yuriy@ucoz.com
> > Regression: No
> >
> >
> > Hi.
> > I administer about 50 highly-loaded web servers (free CMS hosting) under linux.
> > Having on most of them kernel versions between 2.6.24 and 2.6.29 at the
> > beginnig of the year, I made TCP sysctls tunings for increasing DDOS and
> > different flooding protection (our servers have attacks rather often).
> > tcp_tw_recyle=1 was among of them, as many manuals in the net recommend to do
> > this and linux documentation does not say anything bad. Having periodic kernel
> > panics connected with bugs in ethernet card drivers and ext3 and after founding
> > that 2.6.31+ kernels work faster with ext3, I upgraded almost all kernels to
> > 2.6.32.8, which was already being tested on several servers for several months.
> > Somewhen after that we began to receive complaints from our users (site owners)
> > that they (and their visitors) see very unstable work of their sites. It looked
> > like HTTP-connections were just lost in a random way. Not everybody had the
> > problem, just a small percent. We tried to find problem with internet providers
> > or buggy firewalls, but finally came to conclusion that problem is connected
> > with our servers. Analizing situations with lost connections using tcpdump i
> > found that client host send packets, BUT LINUX JUST IGNORES THEM, there was
> > SYN-packet repeated 3 times with interval of 3 secs, but NO SYN-ACK reply.
> > Most problems had users with Windows SP3 (i.e. almost all users with SP3 had
> > the problem). I booted one server with old 2.6.24 kernel and found that problem
> > dissappeared. Then began look for exact kernel version, that introduced
> > incompatibility. Using binary search I compiled several kernels between 2.6.24
> > and 2.6.32.8 and found that 2.6.29.6 DO NO have the problem, but 2.6.30 DOES.
> > Studing commits made to tcp_input.c and tcp_ipv4.c (which i supposed were
> > involved) between that releases I found this one.
> > author Eric Dumazet <dada1@cosmosbay.com>
> > Wed, 11 Mar 2009 16:23:57 +0000 (09:23 -0700)
> > committer David S. Miller <davem@davemloft.net>
> > Wed, 11 Mar 2009 16:23:57 +0000 (09:23 -0700)
> > commit fc1ad92dfc4e363a055053746552cdb445ba5c57
> >
> > tcp: allow timestamps even if SYN packet has tsval=0
> >
> > Some systems send SYN packets with apparently wrong RFC1323 timestamp
> > option values [timestamp tsval=0 tsecr=0].
> > It might be for security reasons (http://www.secuobs.com/plugs/25220.shtml )
> > Linux TCP stack ignores this option and sends back a SYN+ACK packet
> > without timestamp option, thus many TCP flows cannot use timestamps
> > and lose some benefit of RFC1323.
> > Other operating systems seem to not care about initial tsval value, and let
> > tcp flows to negotiate timestamp option.
> >
> > net/ipv4/tcp_ipv4.c diff :
> >
> > --- a/net/ipv4/tcp_ipv4.c
> > +++ b/net/ipv4/tcp_ipv4.c
> > @@ -1226,15 +1226,6 @@ int tcp_v4_conn_request(struct sock *sk, struct sk_buff
> > *skb)
> > if (want_cookie && !tmp_opt.saw_tstamp)
> > tcp_clear_options(&tmp_opt);
> >
> > - if (tmp_opt.saw_tstamp && !tmp_opt.rcv_tsval) {
> > - /* Some OSes (unknown ones, but I see them on web server, which
> > - * contains information interesting only for windows'
> > - * users) do not send their stamp in SYN. It is easy case.
> > - * We simply do not advertise TS support.
> > - */
> > - tmp_opt.saw_tstamp = 0;
> > - tmp_opt.tstamp_ok = 0;
> > - }
> > tmp_opt.tstamp_ok = tmp_opt.saw_tstamp;
> >
> > tcp_openreq_init(req, &tmp_opt, skb);
> >
> > Removing that was not very good. Having analized lost connections from SP3 I
> > know that they have timestamps turned on and timestamp value is 0. Here is it:
> > 13:39:10.430498 IP 192.168.99.130.3493 > 192.168.99.100.80: S
> > 2507911465:2507911465(0) win 65535 <mss 1460,nop,wscale 3,nop,nop,timestamp 0
> > 0,nop,nop,sackOK>
> > 0x0000: 4500 0040 2bda 4000 8006 86a6 c0a8 6382 E..@+.@.......c.
> > 0x0010: c0a8 6364 0da5 0050 957b b129 0000 0000 ..cd...P.{.)....
> > 0x0020: b002 ffff 992c 0000 0204 05b4 0103 0303 .....,..........
> > 0x0030: 0101 080a 0000 0000 0000 0000 0101 0402 ................
> >
> > Having above code fragment removed we got tmp_opt.tstamp_ok=1, as i understand.
> > But a little later in source code of tcp_ipv4.c read:
> > /* VJ's idea. We save last timestamp seen
> > * from the destination in peer table, when entering
> > * state TIME-WAIT, and check against it before
> > * accepting new connection request.
> > *
> > * If "isn" is not zero, this request hit alive
> > * timewait bucket, so that all the necessary checks
> > * are made in the function processing timewait state.
> > */
> > if (tmp_opt.saw_tstamp &&
> > tcp_death_row.sysctl_tw_recycle &&
> > (dst = inet_csk_route_req(sk, req)) != NULL &&
> > (peer = rt_get_peer((struct rtable *)dst)) != NULL &&
> > peer->v4daddr == saddr) {
> > if ((u32)get_seconds() - peer->tcp_ts_stamp < TCP_PAWS_MSL &&
> > (s32)(peer->tcp_ts - req->ts_recent) >
> > TCP_PAWS_WINDOW) {
> > NET_INC_STATS_BH(sock_net(sk), LINUX_MIB_PAWSPASSIVEREJECTED);
> > goto drop_and_release;
> > }
> > }
> > which in some way (tmp_opt.saw_tstamp && tcp_death_row.sysctl_tw_recycle are
> > true), random way, having not closed time-wait sockets from the pear, leads to
> > packet ignorence.
> >
> > As for me, i understand, that i should not enable tw_recycle, BUT DOCUMENTATION
> > DOES NOT STATE, that enabling it i'll got random and rather often lost of
> > connections from some types of popular clients (like Windows).
> > Concerning above stated commit, it should include something to prevent above
> > condition to become true if tmp_opt.rcv_tsval==0. I'm not sure, but something
> > like
> > if (tmp_opt.saw_tstamp &&
> > + tmp_opt.rcv_tsval &&
> > tcp_death_row.sysctl_tw_recycle &&
> > (dst = inet_csk_route_req(sk, req)) != NULL &&
> > (peer = rt_get_peer((struct rtable *)dst)) != NULL &&
> >
> > just to not provide regression and strong TCP-stack incompatibility in case
> > tw_recycle is enabled.
> > Also documentation does not state, that tw_recyle should not be used at all for
> > internet servers, because web-clients, which are behind NAT, will have problems
> > connected with the same above condition because successive connections from
> > different clients (which have common IP) could have incompatible timestamps.
> >
> > Sorry if i detracted somebody busy from his work with my unimportant problem.
> >
>
> --
Hi Yuriy
Interesting analysis but wrong conclusions :)
Clients using RFC1323 (timestamps) and behind a NAT device will barf on
your setup. No matter they use Windows SP3 or other operating system.
Only because RFC1323 is more often enabled at client level (a registry
change on Windows XP, Vista or Seven I dont know), you start noticing
your server drops more connections than before.
Point is :
Dont mess with tcp_tw_recycle=1, tcp_timestamps=1 on public machines
Its a non working setup, for clients behind NAT devices (since their
TSVAL will probably lead to incorrect behavior on server, with infamous
LINUX_MIB_PAWSPASSIVEREJECTED status seen on netstat -s, as you
discovered.
And your patch solves nothing for this very common case, unless the NAT
device is able to overwrite TSVAL values with its own values (very
unlikely !!!)
A working setup is (and is the default) :
tcp_tw_recycle=0
tcp_timestamps=1
Documentation might be improved, but I feel whole "tcp_tw_recycle"
affair is really too tricky to be ever documented (not mentioning using
it ;) )
^ permalink raw reply
* Re: [PATCH] netpoll: use non-BH variant of RCU
From: Paul E. McKenney @ 2010-08-12 15:42 UTC (permalink / raw)
To: David Miller; +Cc: herbert, linville, netdev
In-Reply-To: <20100811.230936.183035599.davem@davemloft.net>
On Wed, Aug 11, 2010 at 11:09:36PM -0700, David Miller wrote:
> From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
> Date: Wed, 11 Aug 2010 15:00:47 -0700
>
> > @@ -113,6 +113,12 @@ int rcu_my_thread_group_empty(void)
> > return thread_group_empty(current);
> > }
> > EXPORT_SYMBOL_GPL(rcu_my_thread_group_empty);
> > +
> > +void rcu_read_unlock_bh_irqsoff_check(void)
> > +{
> > + WARN_ON_ONCE(in_irq() || irqs_disabled());
> > +}
> > +EXPORT_SYMBOL_GPL(rcu_read_unlock_bh_irqsoff_check);
> > #endif /* #ifdef CONFIG_PROVE_RCU */
>
> Is this WARN_ON_ONCE() test inverted? It seems to be called where we
> "should be" in an IRQ or have IRQs disabled.
You are quite correct. (Beat head against wall.) :-/
------------------------------------------------------------------------
#!/bin/bash
for ((i=0;i<100;i++))
do
echo "De Morgan when converting rcu_lockdep_assert() to WARN_ON_ONCE()"
done
------------------------------------------------------------------------
This does sort of defeat the purpose of writing something 100 times, but
I am after all a software developer!!!
Thank you very much for catching this, and please see below for a
replacement patch.
Thanx, Paul
commit 2c9ace45088a25b474167d04b416d279f4ea3401
Author: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Date: Wed Aug 11 14:54:33 2010 -0700
rcu: add rcu_read_lock_bh_irqsoff() and rcu_read_unlock_bh_irqsoff()
The rcu_read_lock_bh() and rcu_read_unlock_bh() functions can no
longer be used when interrupts are disabled due to new debug checks in
the _local_bh_enable() function. This commit therefore supplies new
functions that may only be called with either interrupts disabled or
from interrupt handlers, and this is checked for under CONFIG_PROVE_RCU.
Requested-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index 9fbc54a..08cdc58 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -270,10 +270,13 @@ extern int rcu_my_thread_group_empty(void);
(p); \
})
+void rcu_read_unlock_bh_irqsoff_check(void);
+
#else /* #ifdef CONFIG_PROVE_RCU */
#define rcu_dereference_check(p, c) rcu_dereference_raw(p)
#define rcu_dereference_protected(p, c) (p)
+#define rcu_read_unlock_bh_irqsoff_check() do { } while (0)
#endif /* #else #ifdef CONFIG_PROVE_RCU */
@@ -361,13 +364,13 @@ static inline void rcu_read_unlock(void)
*/
static inline void rcu_read_lock_bh(void)
{
- __rcu_read_lock_bh();
+ local_bh_disable();
__acquire(RCU_BH);
rcu_read_acquire_bh();
}
/*
- * rcu_read_unlock_bh - marks the end of a softirq-only RCU critical section
+ * rcu_read_unlock_bh() - marks the end of a softirq-only RCU critical section
*
* See rcu_read_lock_bh() for more information.
*/
@@ -375,7 +378,34 @@ static inline void rcu_read_unlock_bh(void)
{
rcu_read_release_bh();
__release(RCU_BH);
- __rcu_read_unlock_bh();
+ local_bh_enable();
+}
+
+/**
+ * rcu_read_lock_bh_irqsoff() - mark the beginning of an RCU-bh critical section
+ *
+ * This is equivalent of rcu_read_lock_bh(), but to be used where the
+ * caller either is in an irq handler or has irqs disabled. Note that
+ * this function assumes that PREEMPT_RT kernels run irq handlers at
+ * higher priority than softirq handlers!
+ */
+static inline void rcu_read_lock_bh_irqsoff(void)
+{
+ rcu_read_unlock_bh_irqsoff_check();
+ __acquire(RCU_BH);
+ rcu_read_acquire_bh();
+}
+
+/*
+ * rcu_read_unlock_bh_irqsoff - marks the end of an RCU-bh critical section
+ *
+ * See rcu_read_lock_bh_irqsoff() for more information.
+ */
+static inline void rcu_read_unlock_bh_irqsoff(void)
+{
+ rcu_read_release_bh();
+ __release(RCU_BH);
+ rcu_read_unlock_bh_irqsoff_check();
}
/**
diff --git a/include/linux/rcutiny.h b/include/linux/rcutiny.h
index e2e8931..009c7f3 100644
--- a/include/linux/rcutiny.h
+++ b/include/linux/rcutiny.h
@@ -36,8 +36,6 @@ static inline void rcu_note_context_switch(int cpu)
#define __rcu_read_lock() preempt_disable()
#define __rcu_read_unlock() preempt_enable()
-#define __rcu_read_lock_bh() local_bh_disable()
-#define __rcu_read_unlock_bh() local_bh_enable()
#define call_rcu_sched call_rcu
#define rcu_init_sched() do { } while (0)
diff --git a/include/linux/rcutree.h b/include/linux/rcutree.h
index c0ed1c0..98b50d8 100644
--- a/include/linux/rcutree.h
+++ b/include/linux/rcutree.h
@@ -75,15 +75,6 @@ static inline int rcu_preempt_depth(void)
#endif /* #else #ifdef CONFIG_TREE_PREEMPT_RCU */
-static inline void __rcu_read_lock_bh(void)
-{
- local_bh_disable();
-}
-static inline void __rcu_read_unlock_bh(void)
-{
- local_bh_enable();
-}
-
extern void call_rcu_sched(struct rcu_head *head,
void (*func)(struct rcu_head *rcu));
extern void synchronize_rcu_bh(void);
diff --git a/kernel/rcupdate.c b/kernel/rcupdate.c
index 4d16983..ae6ae40 100644
--- a/kernel/rcupdate.c
+++ b/kernel/rcupdate.c
@@ -113,6 +113,12 @@ int rcu_my_thread_group_empty(void)
return thread_group_empty(current);
}
EXPORT_SYMBOL_GPL(rcu_my_thread_group_empty);
+
+void rcu_read_unlock_bh_irqsoff_check(void)
+{
+ WARN_ON_ONCE(!in_irq() && !irqs_disabled());
+}
+EXPORT_SYMBOL_GPL(rcu_read_unlock_bh_irqsoff_check);
#endif /* #ifdef CONFIG_PROVE_RCU */
#ifdef CONFIG_DEBUG_OBJECTS_RCU_HEAD
^ permalink raw reply related
* Re: sky2 driver fails to handle "rx length error: status 0x5d60100 length 2982" gracefully
From: Stephen Hemminger @ 2010-08-12 16:00 UTC (permalink / raw)
To: Maciej Żenczykowski; +Cc: Stephen Hemminger, Linux NetDev
In-Reply-To: <AANLkTikDOerA4g+-=v+wM8cmysnemCTqEx0ncCCERLY6@mail.gmail.com>
On Wed, 11 Aug 2010 22:36:57 -0700
Maciej Żenczykowski <zenczykowski@gmail.com> wrote:
> Here's lspci (it's an otherwise stock MacBook Pro 4,1 with a
> non-standard wireless atheros mini-pci nic, replacing the std
> broadcom.)
>
> $ lspci
> 00:00.0 Host bridge: Intel Corporation Mobile PM965/GM965/GL960 Memory
> Controller Hub (rev 03)
> 00:01.0 PCI bridge: Intel Corporation Mobile PM965/GM965/GL960 PCI
> Express Root Port (rev 03)
> 00:1a.0 USB Controller: Intel Corporation 82801H (ICH8 Family) USB
> UHCI Controller #4 (rev 03)
> 00:1a.1 USB Controller: Intel Corporation 82801H (ICH8 Family) USB
> UHCI Controller #5 (rev 03)
> 00:1a.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2
> EHCI Controller #2 (rev 03)
> 00:1b.0 Audio device: Intel Corporation 82801H (ICH8 Family) HD Audio
> Controller (rev 03)
> 00:1c.0 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express
> Port 1 (rev 03)
> 00:1c.2 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express
> Port 3 (rev 03)
> 00:1c.4 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express
> Port 5 (rev 03)
> 00:1c.5 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express
> Port 6 (rev 03)
> 00:1d.0 USB Controller: Intel Corporation 82801H (ICH8 Family) USB
> UHCI Controller #1 (rev 03)
> 00:1d.1 USB Controller: Intel Corporation 82801H (ICH8 Family) USB
> UHCI Controller #2 (rev 03)
> 00:1d.2 USB Controller: Intel Corporation 82801H (ICH8 Family) USB
> UHCI Controller #3 (rev 03)
> 00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2
> EHCI Controller #1 (rev 03)
> 00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev f3)
> 00:1f.0 ISA bridge: Intel Corporation 82801HEM (ICH8M) LPC Interface
> Controller (rev 03)
> 00:1f.1 IDE interface: Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E)
> IDE Controller (rev 03)
> 00:1f.2 IDE interface: Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E)
> SATA IDE Controller (rev 03)
> 00:1f.3 SMBus: Intel Corporation 82801H (ICH8 Family) SMBus Controller (rev 03)
> 01:00.0 VGA compatible controller: nVidia Corporation G84 [GeForce
> 8600M GT] (rev a1)
> 0b:00.0 Network controller: Atheros Communications Inc. AR928X
> Wireless Network Adapter (PCI-Express) (rev 01)
> 0c:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8058
> PCI-E Gigabit Ethernet Controller (rev 13)
> 0d:03.0 FireWire (IEEE 1394): Texas Instruments TSB82AA2 IEEE-1394b
> Link Layer Controller (rev 02)
>
> (more verbose lspci included in bugzilla entry)
>
> At least one other person has seen this on a desktop non-mac machine
> (see bugzilla) entry.
> What would you like from dmesg?
> Is the following enough?
>
> Aug 9 12:09:11 nike kernel: sky2: driver version 1.27
> Aug 9 12:09:11 nike kernel: sky2 0000:0c:00.0: PCI INT A -> GSI 17
> (level, low) -> IRQ 17
> Aug 9 12:09:11 nike kernel: sky2 0000:0c:00.0: Yukon-2 EC Ultra chip revision 3
> Aug 9 12:09:11 nike kernel: sky2 0000:0c:00.0: eth0: addr 00:1f:5b:xx:xx:xx
> ...
> Aug 9 12:09:22 nike kernel: sky2 0000:0c:00.0: eth0: enabling interface
> Aug 9 12:09:22 nike kernel: ADDRCONF(NETDEV_UP): eth0: link is not ready
> ...
> Aug 9 12:09:25 nike kernel: sky2 0000:0c:00.0: eth0: Link is up at
> 1000 Mbps, full duplex, flow control rx
> Aug 9 12:09:25 nike kernel: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
> ...
> Aug 11 16:21:19 nike kernel: sky2 0000:0c:00.0: eth0: rx length error:
> status 0x5d60100 length 2982
> Aug 11 16:21:27 nike kernel: eth0: hw csum failure.
> ...
>
> I'd just like to point out that this has happened something like 5
> times in the past 30 days on a machine which is on 24/7 with wired
> ethernet plugged in nearly 100% of the time.
Probably he only thing the driver can do in these cases is automatically
turn off checksumming if it suspects the chip is having problems.
Is there a known good older kernel version?
^ permalink raw reply
* RE: e1000e crashes with 2.6.34.x and ThinkPad T60
From: Allan, Bruce W @ 2010-08-12 16:12 UTC (permalink / raw)
To: Marc Haber
Cc: Tantilov, Emil S, Linux Kernel Developers,
Linux Kernel Network Developers, e1000-devel@lists.sf.net
In-Reply-To: <20100812105029.GA6816@torres.zugschlus.de>
On Thursday, August 12, 2010 3:50 AM, Marc Haber wrote:
> Hi,
>
> On Tue, Aug 10, 2010 at 09:34:52AM -0700, Allan, Bruce W wrote:
>> [adding e1000-devel, the Intel wired ethernet developers mailing
>> list]
>
> Thanks.
>
>> We have had other recent reports of issues with this part that are
>> due to ASPM L1 being enabled. Would you please try disabling L1
>> after the driver is loaded as follows (assuming your adapter is
>> still PCI bus/device/number 02:00.0 as indicated in the lspci output
>> you provided earlier): 1) First check the hexadecimal value of the
>> LnkCtl register - # setpci -s 2:0.0 0xf0
>
> $ sudo setpci --version
> setpci version 3.1.7
> $ sudo setpci -s 2:0.0 0xf0
> setpci: Missing width.
> Try `setpci --help' for more information.
> $
>
> Looking at --help doesn't help me, sorry.
>
> Greetings
> Marc
Hmm, that's a newer version than I am familiar with. Apparently in
more recent versions, the tool is requiring a width be specified for
unnamed registers and/or registers for which the width is unknown.
That being the case, append the width specifier .B (one byte) to the
register address. For example:
# setpci -s 2:0.0 0xf0.B
HTH,
Bruce.
^ permalink raw reply
* Re: sky2 driver fails to handle "rx length error: status 0x5d60100 length 2982" gracefully
From: Stephen Hemminger @ 2010-08-12 16:16 UTC (permalink / raw)
To: Maciej Żenczykowski; +Cc: Stephen Hemminger, Linux NetDev
In-Reply-To: <20100812120044.5b1880ad@s6510>
> > Aug 11 16:21:19 nike kernel: sky2 0000:0c:00.0: eth0: rx length error:
> > status 0x5d60100 length 2982
> > Aug 11 16:21:27 nike kernel: eth0: hw csum failure.
Are you trying to run with Jumbo >1500 MTU?
^ permalink raw reply
* Re: Fw: [PATCH net-next] drivers/s390/net/qeth_l3_main.c: Use %pI6
From: Ursula Braun @ 2010-08-12 16:36 UTC (permalink / raw)
To: Ursula Braun1; +Cc: blaschka, linux-s390, netdev, linux-kernel
In-Reply-To: <OF89C50871.5ED34E2A-ONC125777D.005A40DE-C125777D.005A4DDE@de.ibm.com>
ACK
Thanks Joe - we make sure your patch is submitted to Dave Miller within
our next submission of qeth patches.
Ursula
> From: Joe Perches <joe@perches.com>
> To: Frank Blaschka <blaschka@linux.vnet.ibm.com>
> Subject: [PATCH net-next] drivers/s390/net/qeth_l3_main.c: Use %pI6
> Format an ipv6 address using vsprintf extensions.
>
> Signed-off-by: Joe Perches <joe@perches.com>
> ---
> drivers/s390/net/qeth_l3_main.c | 7 +------
> 1 files changed, 1 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/s390/net/qeth_l3_main.c
> b/drivers/s390/net/qeth_l3_main.c
> index e22ae24..561bdc8 100644
> --- a/drivers/s390/net/qeth_l3_main.c
> +++ b/drivers/s390/net/qeth_l3_main.c
> @@ -103,12 +103,7 @@ int qeth_l3_string_to_ipaddr4(const char *buf,
> __u8 *addr)
>
> void qeth_l3_ipaddr6_to_string(const __u8 *addr, char *buf)
> {
> - sprintf(buf, "%02x%02x:%02x%02x:%02x%02x:%02x%02x"
> - ":%02x%02x:%02x%02x:%02x%02x:%
> 02x%02x",
> - addr[0], addr[1], addr[2],
> addr[3],
> - addr[4], addr[5], addr[6],
> addr[7],
> - addr[8], addr[9], addr[10],
> addr[11],
> - addr[12], addr[13], addr[14],
> addr[15]);
> + sprintf(buf, "%pI6", addr);
> }
>
> int qeth_l3_string_to_ipaddr6(const char *buf, __u8 *addr)
>
>
^ permalink raw reply
* mmotm 2010-08-11 - lockdep whinges at e1000e driver ifconfig up
From: Valdis.Kletnieks @ 2010-08-12 16:37 UTC (permalink / raw)
To: Andrew Morton, davem, jeffrey.t.kirsher, jesse.brandeburg, kaber,
jengelh, eric.dumazet
Cc: linux-kernel, netdev, e1000-devel, netfilter
In-Reply-To: <201008112340.o7BNenDe021017@imap1.linux-foundation.org>
[-- Attachment #1: Type: text/plain, Size: 6017 bytes --]
On Wed, 11 Aug 2010 16:10:49 PDT, akpm@linux-foundation.org said:
> The mm-of-the-moment snapshot 2010-08-11-16-10 has been uploaded to
>
> http://userweb.kernel.org/~akpm/mmotm/
Not sure if it's an e1000e bug, or an iptables bug that happened to trip on
like the first few packets accepted after the interface came up, so I'll cc:
everybody and let ya'll fight over it. :)
[ 431.011194] e1000e 0000:00:19.0: irq 46 for MSI/MSI-X
[ 431.062183] e1000e 0000:00:19.0: irq 46 for MSI/MSI-X
[ 431.064607] ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 432.691161] e1000e: eth0 NIC Link is Up 100 Mbps Full Duplex, Flow Control: None
[ 432.691177] e1000e 0000:00:19.0: eth0: 10/100 speed: disabling TSO
[ 432.695461] ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 432.697278]
[ 432.697279] =================================
[ 432.697477] [ INFO: inconsistent lock state ]
[ 432.697581] 2.6.35-mmotm0811 #1
[ 432.697682] ---------------------------------
[ 432.697785] inconsistent {SOFTIRQ-ON-W} -> {IN-SOFTIRQ-W} usage.
[ 432.697890] kworker/0:0/0 [HC0[0]:SC1[2]:HE1:SE0] takes:
[ 432.697994] (&(&lock->lock)->rlock){+.?...}, at: [<ffffffff814d39c8>] ip6t_do_table+0xc1/0x646
[ 432.698028] {SOFTIRQ-ON-W} state was registered at:
[ 432.698028] [<ffffffff8106762f>] __lock_acquire+0x3a3/0xd6a
[ 432.698028] [<ffffffff81068514>] lock_acquire+0x10a/0x130
[ 432.698028] [<ffffffff81557cd9>] _raw_spin_lock+0x36/0x45
[ 432.698028] [<ffffffff814d3375>] xt_info_wrlock+0x1c/0x1e
[ 432.698028] [<ffffffff814d48df>] get_counters+0x93/0x14a
[ 432.698028] [<ffffffff814d49c3>] alloc_counters.clone.3+0x2d/0x41
[ 432.698028] [<ffffffff814d4f98>] do_ip6t_get_ctl+0x110/0x367
[ 432.698028] [<ffffffff814402a7>] nf_sockopt+0x5c/0x88
[ 432.698028] [<ffffffff814402e6>] nf_getsockopt+0x13/0x15
[ 432.698028] [<ffffffff814ba05e>] ipv6_getsockopt+0x94/0xc3
[ 432.698028] [<ffffffff814c1175>] rawv6_getsockopt+0x48/0x54
[ 432.698028] [<ffffffff8141533a>] sock_common_getsockopt+0xf/0x11
[ 432.698028] [<ffffffff814147dd>] sys_getsockopt+0x75/0x93
[ 432.698028] [<ffffffff8100272b>] system_call_fastpath+0x16/0x1b
[ 432.698028] irq event stamp: 3554312
[ 432.698028] hardirqs last enabled at (3554312): [<ffffffff8103fcb9>] _local_bh_enable_ip+0x139/0x178
[ 432.698028] hardirqs last disabled at (3554311): [<ffffffff8103fc3a>] _local_bh_enable_ip+0xba/0x178
[ 432.698028] softirqs last enabled at (3554260): [<ffffffff81040282>] __do_softirq+0x273/0x289
[ 432.698028] softirqs last disabled at (3554277): [<ffffffff8100364c>] call_softirq+0x1c/0x28
[ 432.698028]
[ 432.698028] other info that might help us debug this:
[ 432.698028] 3 locks held by kworker/0:0/0:
[ 432.698028] #0: (&idev->mc_ifc_timer){+.-...}, at: [<ffffffff810468f9>] run_timer_softirq+0x1d2/0x442
[ 432.698028] #1: (rcu_read_lock){.+.+..}, at: [<ffffffff814c3c2a>] rcu_read_lock+0x0/0x35
[ 432.698028] #2: (rcu_read_lock){.+.+..}, at: [<ffffffff8143e840>] rcu_read_lock+0x0/0x35
[ 432.698028]
[ 432.698028] stack backtrace:
[ 432.698028] Pid: 0, comm: kworker/0:0 Not tainted 2.6.35-mmotm0811 #1
[ 432.698028] Call Trace:
[ 432.698028] <IRQ> [<ffffffff810670a2>] valid_state+0x17c/0x18e
[ 432.698028] [<ffffffff81066967>] ? check_usage_forwards+0x0/0x87
[ 432.698028] [<ffffffff81067193>] mark_lock+0xdf/0x1d8
[ 432.698028] [<ffffffff810675b1>] __lock_acquire+0x325/0xd6a
[ 432.698028] [<ffffffff8106768f>] ? __lock_acquire+0x403/0xd6a
[ 432.698028] [<ffffffff810687fc>] ? mark_held_locks+0x50/0x72
[ 432.698028] [<ffffffff814d39c8>] ? ip6t_do_table+0xc1/0x646
[ 432.698028] [<ffffffff81068514>] lock_acquire+0x10a/0x130
[ 432.698028] [<ffffffff814d39c8>] ? ip6t_do_table+0xc1/0x646
[ 432.698028] [<ffffffff8103fce6>] ? _local_bh_enable_ip+0x166/0x178
[ 432.698028] [<ffffffff81557cd9>] _raw_spin_lock+0x36/0x45
[ 432.698028] [<ffffffff814d39c8>] ? ip6t_do_table+0xc1/0x646
[ 432.698028] [<ffffffff814d39c8>] ip6t_do_table+0xc1/0x646
[ 432.698028] [<ffffffff8103fce6>] ? _local_bh_enable_ip+0x166/0x178
[ 432.698028] [<ffffffff8103fd10>] ? local_bh_enable+0xd/0xf
[ 432.698028] [<ffffffff8144234b>] ? nf_conntrack_in+0x4a9/0x5b9
[ 432.698028] [<ffffffff814d5ee7>] ip6table_filter_hook+0x17/0x1c
[ 432.698028] [<ffffffff8143ec43>] nf_iterate+0x41/0x84
[ 432.698028] [<ffffffff814c3ec5>] ? dst_output+0x0/0x70
[ 432.698028] [<ffffffff8143ecf9>] nf_hook_slow+0x73/0xde
[ 432.698028] [<ffffffff814c3ec5>] ? dst_output+0x0/0x70
[ 432.698028] [<ffffffff8104710a>] ? msleep_interruptible+0x5b/0x72
[ 432.698028] [<ffffffff814c508e>] NF_HOOK.clone.21+0x3e/0x52
[ 432.698028] [<ffffffff81499c6c>] ? xfrm_lookup+0x11/0x2e
[ 432.698028] [<ffffffff814c531f>] mld_sendpack+0x27d/0x3dd
[ 432.698028] [<ffffffff814c5ad6>] mld_ifc_timer_expire+0x1ca/0x207
[ 432.698028] [<ffffffff810469eb>] run_timer_softirq+0x2c4/0x442
[ 432.698028] [<ffffffff810468f9>] ? run_timer_softirq+0x1d2/0x442
[ 432.698028] [<ffffffff81059222>] ? __run_hrtimer+0x1ec/0x234
[ 432.698028] [<ffffffff814c590c>] ? mld_ifc_timer_expire+0x0/0x207
[ 432.698028] [<ffffffff81040080>] ? __do_softirq+0x71/0x289
[ 432.698028] [<ffffffff81040155>] __do_softirq+0x146/0x289
[ 432.698028] [<ffffffff810a29bc>] ? time_hardirqs_off+0x1b/0x2f
[ 432.698028] [<ffffffff8100364c>] call_softirq+0x1c/0x28
[ 432.698028] [<ffffffff81004bc3>] do_softirq+0x44/0xf1
[ 432.698028] [<ffffffff8104035a>] irq_exit+0x4a/0xb4
[ 432.698028] [<ffffffff8101a3dd>] smp_apic_timer_interrupt+0x79/0x87
[ 432.698028] [<ffffffff81003113>] apic_timer_interrupt+0x13/0x20
[ 432.698028] <EOI> [<ffffffff81277630>] ? acpi_idle_enter_simple+0x122/0x15a
[ 432.698028] [<ffffffff8127762b>] ? acpi_idle_enter_simple+0x11d/0x15a
[ 432.698028] [<ffffffff813b9c3c>] cpuidle_idle_call+0x9b/0x15d
[ 432.698028] [<ffffffff81000c73>] cpu_idle+0x85/0x169
[ 432.698028] [<ffffffff81b5e906>] start_secondary+0x1b1/0x1b5
[ 497.031095] ADDRCONF(NETDEV_UP): wlan0: link is not ready
[-- Attachment #2: Type: application/pgp-signature, Size: 227 bytes --]
^ permalink raw reply
* Re: sky2 driver fails to handle "rx length error: status 0x5d60100 length 2982" gracefully
From: Maciej Żenczykowski @ 2010-08-12 16:58 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: Stephen Hemminger, Linux NetDev
In-Reply-To: <20100812121600.2e971e66@s6510>
I'm not sure if there is a known good kernel. It seems to be getting
worse over time (as I upgrade kernels), but maybe the hardware is
aging and the situation is becoming more likely. When it first
started happening it was like once every 2-3 months or even rarer.
Now it has happened again since the last time I posted to this
thread...
Aug 12 08:29:08 nike kernel: sky2 0000:0c:00.0: eth0: rx length error:
status 0x5e50100 length 3013
> Are you trying to run with Jumbo >1500 MTU?
No, normal 1500 MTU network, with ipv4 and ipv6 native traffic. Not a
huge amount of traffic either.
And indeed the problem seems to happen just as easily (if not easier)
when the machine (and thus the network) is close(r) to idle (ie.
overnight, etc) - although that might just be a matter of more time
passing.
Are you sure there is nothing the driver could do on seeing such an error?
It seems like since "ip link set eth0 down && ip link set eth0 up"
fixes it, what it should do is some sort of partial reset...
I will try to verify if 'ethtool -K eth0 rx off && ethtool -K eth0 rx
on' is enough to fix the problem (when it happens once again).
Afterwards I'll turn of rx csum (ethtool -K eth0 rx off) and will see
if it happens again.
^ permalink raw reply
* Re: Problem with non aligned DMA in usbnet on ARM
From: Matthieu CASTET @ 2010-08-12 17:01 UTC (permalink / raw)
To: mfuzzey@gmail.com
Cc: Greg KH, Russell King - ARM Linux, linux-usb,
netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
fchen
In-Reply-To: <4C6324B2.2080606@gmail.com>
Martin Fuzzey a écrit :
> Greg KH wrote:
>> Can you fix this in the host controller driver?
>>
>>
> Technically yes (by copying the unaligned buffers).
>
> But if we do decide that USB must support unaligned buffers wouldn't it
> be better to have the HCD indicate it's alignment requirement to the
> core and have the core do the copying?
>
> Gary King sent a message to this thread but only to the arm list saying
> he has the same problem with the tegra hcd (which doesn't seem to be in
> the tree yet.) I don't know if any of the other in tree HCDs have this
> problem.
dwc otg also got this limitation. I don't know if the version submitted
for inclusion handle unaligned buffers.
Matthieu
^ permalink raw reply
* Re: Problem with non aligned DMA in usbnet on ARM
From: Matthieu CASTET @ 2010-08-12 17:08 UTC (permalink / raw)
To: mfuzzey-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Cc: Russell King - ARM Linux, Gary King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-usb, netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Greg KH
In-Reply-To: <4C632217.9000608-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1069 bytes --]
Martin Fuzzey a écrit :
>> We don't want to add support for this to DMA bounce. DMA bounce is already
>> a pain in the backside and causes its own set of problems - please let it
>> die a long slow but quite death.
>>
>> If you want to see the kind of pain dmabounce causes, look at this long
>> standing and as yet unsolved bug:
>>
>> http://bugzilla.kernel.org/show_bug.cgi?id=7760
>>
>>
> Well I don't know the dmabounce code but why is using it likely to cause
> OOM problems (at least why more so than copying the buffer in the HCD or
> the usb core). In both cases there will be two copies of the buffer in
> memory which could I agree be a problem in memory constrained systems.
> But if we _do_ want to accept unaligned buffers from usb drivers I can't
> see a way round that.
>
memmove is our friend :
the buffer allocated in usbnet got an offset.
All you have to do it remove this offset and memmove the data. That what
I did [1], and why it is better to do it in usb driver.
Matthieu
[1] http://article.gmane.org/gmane.linux.usb.general/28700
[-- Attachment #2: gadget-align.diff --]
[-- Type: text/x-diff, Size: 2251 bytes --]
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index 1edbc12..ed3ee67 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -214,4 +214,14 @@ static inline bool gadget_supports_altsettings(struct usb_gadget *gadget)
return true;
}
+/**
+ * gadget_dma32 - return true if we want buffer aligned on 32 bits (for dma)
+ * @gadget: the gadget in question
+ */
+static inline bool gadget_dma32(struct usb_gadget *gadget)
+{
+ if (gadget_is_musbhdrc(gadget))
+ return true;
+ return false;
+}
#endif /* __GADGET_CHIPS_H */
diff --git a/drivers/usb/gadget/u_ether.c b/drivers/usb/gadget/u_ether.c
index 84ca195..697af90 100644
--- a/drivers/usb/gadget/u_ether.c
+++ b/drivers/usb/gadget/u_ether.c
@@ -249,7 +249,12 @@ rx_submit(struct eth_dev *dev, struct usb_request *req, gfp_t gfp_flags)
* but on at least one, checksumming fails otherwise. Note:
* RNDIS headers involve variable numbers of LE32 values.
*/
- skb_reserve(skb, NET_IP_ALIGN);
+ /*
+ * RX: Do not move data by IP_ALIGN:
+ * if your DMA controller cannot handle it
+ */
+ if (!gadget_dma32(dev->gadget))
+ skb_reserve(skb, NET_IP_ALIGN);
req->buf = skb->data;
req->length = size;
@@ -282,6 +287,12 @@ static void rx_complete(struct usb_ep *ep, struct usb_request *req)
/* normal completion */
case 0:
skb_put(skb, req->actual);
+ if (gadget_dma32(dev->gadget) && NET_IP_ALIGN) {
+ u8 *data = skb->data;
+ size_t len = skb_headlen(skb);
+ skb_reserve(skb, NET_IP_ALIGN);
+ memmove(skb->data, data, len);
+ }
if (dev->unwrap) {
unsigned long flags;
@@ -573,6 +584,24 @@ static netdev_tx_t eth_start_xmit(struct sk_buff *skb,
length = skb->len;
}
+
+ /*
+ * Align data to 32bit if the dma controller requires it
+ */
+ if (gadget_dma32(dev->gadget)) {
+ unsigned long align = (unsigned long)skb->data & 3;
+ if (WARN_ON(skb_headroom(skb) < align)) {
+ dev_kfree_skb_any(skb);
+ goto drop;
+ } else if (align) {
+ u8 *data = skb->data;
+ size_t len = skb_headlen(skb);
+ skb->data -= align;
+ memmove(skb->data, data, len);
+ skb_set_tail_pointer(skb, len);
+ }
+ }
+
req->buf = skb->data;
req->context = skb;
req->complete = tx_complete;
^ permalink raw reply related
* Re: Re[2]: [Bugme-new] [Bug 16568] New: Regression and incompatibility with Windows SP2-SP3-Vista TCP stack causing lost connections
From: Eric Dumazet @ 2010-08-12 17:18 UTC (permalink / raw)
To: Yuriy; +Cc: Andrew Morton, netdev, bugzilla-daemon, bugme-daemon
In-Reply-To: <68743058.20100812194607@ucoz.com>
Le jeudi 12 août 2010 à 19:46 +0300, Yuriy a écrit :
> Thanks for reply.
>
> Main idea that i wanted to say is just to document this feature appropriately as internet is full of recommendations to enable it.
> Just few words like "do not used it on public servers" would be much better than now.
Sure, but we dont maintain nor correct the recommandations found on
various Internet pages ;)
BTW, a google search on "tcp_tw_recycle" gives many results on problems
with this setting, not improvements.
Also, many "recommandations" found on Internet suggest to disable
tcp_timestamps, only because it adds 12 bytes to TCP header.
Apparently you chose to follow the tcp_tw_recycle=1 recommandation, not
the tcp_timestamps=0 one ;)
^ permalink raw reply
* [PATCH] Add firmware label support to iproute2
From: Narendra K @ 2010-08-12 17:35 UTC (permalink / raw)
To: netdev; +Cc: matt_domsch, charles_rose, jordan_hargrave
Hello,
We have proposed solutions to resolve the specific issue of
"eth0 does not always map to Integrated NIC port 1 on the
server chassis". Below are the approaches we proposed which
were not acceptable -
1. Create char device node for every network device and have udev
create alternate names in the form of /dev/netdev/.
http://marc.info/?l=linux-netdev&m=125510301513312&w=2
2. Achieve the above in userspace only using udev
3. Provide an option in the installers for users to rename network
interfaces based on various policies such as chassis label, mac
addresses etc.
https://www.redhat.com/archives/anaconda-devel-list/2009-November/msg00516.html
The approach to export firmware provided index and labels was more
acceptable.
http://marc.info/?l=linux-pci&m=126713402415401&w=3 -
This feature is now part of the kernel and firmware labels of
network devices are available to user space via sysfs.
http://git.kernel.org/?p=linux/kernel/git/next/linux-next.git;a=commit;
h=911e1c9b05a8e3559a7aa89083930700a0b9e7ee
(PCI: export SMBIOS provided firmware instance and label to sysfs)
cat /sys/class/net/ethN/device/label
Embedded NIC N
Next step would be to enable applications to support the firmware
names.
With the patch below, Iproute2 can support firmware labels like
"Embedded NIC 1". We can refer to the network interfaces with firmware
names as labeled on the system chassis. With this "Embedded NIC 1"
would always refer to the 'integrated NIC port 1' on the system chassis.
Requirements -
1. Package be linked to libnetdevname library which maps firmware names
to kernel names. It is available here -
git clone http://linux.dell.com/git/libnetdevname.git
2. The kernel patch mentioned above.
Please let us know your views on this approach and if acceptable,
please consider this patch for inclusion.
From: Narendra K <narendra_k@dell.com>
Subject: [PATCH] Add firmware label support to iproute2
This patch enables iproute2 to support firmware provided
labels for network devices. Ex:
/sbin/ip maddr show dev "Embedded NIC N"
/sbin/ip addr show dev "Embedded NIC N"
/sbin/tc qdisc add dev "Embedded NIC N" root tbf rate Xkbit \
latency Yms burst 1540
The patch makes calls to libnetdevname library which maps
the "Embedded NIC N" names to ethN kernel names.
This makes sure that above commands that use "Embedded NIC 1" as
the dev argument, will refer to the integrated port 1 on the
chassis label.
Signed-off-by: Jordan Hargrave <jordan_hargrave@dell.com>
Signed-off-by: Narendra K <narendra_k@dell.com>
---
Makefile | 5 +++++
ip/ipaddress.c | 14 ++++++++++++++
ip/iplink.c | 14 ++++++++++++++
ip/ipmaddr.c | 18 ++++++++++++++++++
lib/ll_map.c | 16 ++++++++++++++++
tc/f_fw.c | 15 +++++++++++++++
tc/tc_class.c | 25 +++++++++++++++++++++++++
tc/tc_filter.c | 25 +++++++++++++++++++++++++
tc/tc_qdisc.c | 24 ++++++++++++++++++++++++
9 files changed, 156 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
index 77a85c6..ee82640 100644
--- a/Makefile
+++ b/Makefile
@@ -35,6 +35,11 @@ YACCFLAGS = -d -t -v
LDLIBS += -L../lib -lnetlink -lutil
+ifeq ($(shell test -L /usr/local/lib/libnetdevname.so; echo $$?),0)
+LDLIBS +=-lnetdevname
+DEFINES += -DLIBNETDEVNAME_PRESENT
+endif
+
SUBDIRS=lib ip tc misc netem genl
LIBNETLINK=../lib/libnetlink.a ../lib/libutil.a
diff --git a/ip/ipaddress.c b/ip/ipaddress.c
index 3a411b1..6fafa2e 100644
--- a/ip/ipaddress.c
+++ b/ip/ipaddress.c
@@ -28,6 +28,10 @@
#include <linux/if_arp.h>
#include <linux/sockios.h>
+#ifdef LIBNETDEVNAME_PRESENT
+#include <netdevname.h>
+#endif
+
#include "rt_names.h"
#include "utils.h"
#include "ll_map.h"
@@ -712,6 +716,10 @@ static int ipaddr_list_or_flush(int argc, char **argv, int flush)
char *filter_dev = NULL;
int no_link = 0;
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
+
ipaddr_reset_filter(oneline);
filter.showqueue = 1;
@@ -787,7 +795,13 @@ static int ipaddr_list_or_flush(int argc, char **argv, int flush)
usage();
if (filter_dev)
duparg2("dev", *argv);
+#ifndef LIBNETDEVNAME_PRESENT
filter_dev = *argv;
+#else
+ if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
+ show_firmware_alias_usage(*argv);
+ filter_dev = kernel_name;
+#endif
}
argv++; argc--;
}
diff --git a/ip/iplink.c b/ip/iplink.c
index cb2c4f5..e9f70e2 100644
--- a/ip/iplink.c
+++ b/ip/iplink.c
@@ -28,6 +28,10 @@
#include <sys/ioctl.h>
#include <linux/sockios.h>
+#ifdef LIBNETDEVNAME_PRESENT
+#include <netdevname.h>
+#endif
+
#include "rt_names.h"
#include "utils.h"
#include "ip_common.h"
@@ -703,6 +707,10 @@ static int do_set(int argc, char **argv)
char *newname = NULL;
int htype, halen;
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
+
while (argc > 0) {
if (strcmp(*argv, "up") == 0) {
mask |= IFF_UP;
@@ -798,7 +806,13 @@ static int do_set(int argc, char **argv)
usage();
if (dev)
duparg2("dev", *argv);
+#ifndef LIBNETDEVNAME_PRESENT
dev = *argv;
+#else
+ if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
+ show_firmware_alias_usage(*argv);
+ dev = kernel_name;
+#endif
}
argc--; argv++;
}
diff --git a/ip/ipmaddr.c b/ip/ipmaddr.c
index 44ffdfc..b5c8380 100644
--- a/ip/ipmaddr.c
+++ b/ip/ipmaddr.c
@@ -26,6 +26,10 @@
#include <linux/if_arp.h>
#include <linux/sockios.h>
+#ifdef LIBNETDEVNAME_PRESENT
+#include <netdevname.h>
+#endif
+
#include "rt_names.h"
#include "utils.h"
@@ -245,6 +249,9 @@ static int multiaddr_list(int argc, char **argv)
{
struct ma_info *list = NULL;
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
if (!filter.family)
filter.family = preferred_family;
@@ -257,7 +264,13 @@ static int multiaddr_list(int argc, char **argv)
usage();
if (filter.dev)
duparg2("dev", *argv);
+#ifndef LIBNETDEVNAME_PRESENT
filter.dev = *argv;
+#else
+ if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
+ show_firmware_alias_usage(*argv);
+ filter.dev = kernel_name;
+#endif
}
argv++; argc--;
}
@@ -289,7 +302,12 @@ int multiaddr_modify(int cmd, int argc, char **argv)
NEXT_ARG();
if (ifr.ifr_name[0])
duparg("dev", *argv);
+#ifndef LIBNETDEVNAME_PRESENT
strncpy(ifr.ifr_name, *argv, IFNAMSIZ);
+#else
+ if (netdev_alias_to_kernelname(*argv, ifr.ifr_name) < 0)
+ show_firmware_alias_usage(*argv);
+#endif
} else {
if (matches(*argv, "address") == 0) {
NEXT_ARG();
diff --git a/lib/ll_map.c b/lib/ll_map.c
index b8b49aa..1476255 100644
--- a/lib/ll_map.c
+++ b/lib/ll_map.c
@@ -19,9 +19,15 @@
#include <netinet/in.h>
#include <string.h>
+#ifdef LIBNETDEVNAME_PRESENT
+#include <netdevname.h>
+#include <linux/if.h>
+#endif
+
#include "libnetlink.h"
#include "ll_map.h"
+
extern unsigned int if_nametoindex (const char *);
struct idxmap
@@ -163,8 +169,18 @@ unsigned ll_name_to_index(const char *name)
int i;
unsigned idx;
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
if (name == NULL)
return 0;
+
+#ifdef LIBNETDEVNAME_PRESENT
+ if (netdev_alias_to_kernelname(name, kernel_name) < 0)
+ show_firmware_alias_usage(name);
+ strncpy(name, kernel_name, IFNAMSIZ);
+#endif
+
if (icache && strcmp(name, ncache) == 0)
return icache;
for (i=0; i<16; i++) {
diff --git a/tc/f_fw.c b/tc/f_fw.c
index 219b404..244bc8a 100644
--- a/tc/f_fw.c
+++ b/tc/f_fw.c
@@ -20,6 +20,11 @@
#include <arpa/inet.h>
#include <string.h>
#include <linux/if.h> /* IFNAMSIZ */
+
+#ifdef LIBNETDEVNAME_PRESENT
+#include <netdevname.h>
+#endif
+
#include "utils.h"
#include "tc_util.h"
@@ -39,6 +44,10 @@ static int fw_parse_opt(struct filter_util *qu, char *handle, int argc, char **a
__u32 mask = 0;
int mask_set = 0;
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
+
memset(&tp, 0, sizeof(tp));
if (handle) {
@@ -100,7 +109,13 @@ static int fw_parse_opt(struct filter_util *qu, char *handle, int argc, char **a
fprintf(stderr, "Illegal indev\n");
return -1;
}
+#ifndef LIBNETDEVNAME_PRESENT
strncpy(d, *argv, sizeof (d) - 1);
+#else
+ if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
+ show_firmware_alias_usage(*argv);
+ strncpy(d, kernel_name, sizeof (d) - 1);
+#endif
addattr_l(n, MAX_MSG, TCA_FW_INDEV, d, strlen(d) + 1);
} else if (strcmp(*argv, "help") == 0) {
explain();
diff --git a/tc/tc_class.c b/tc/tc_class.c
index 9d4eea5..bff90f8 100644
--- a/tc/tc_class.c
+++ b/tc/tc_class.c
@@ -21,6 +21,11 @@
#include <string.h>
#include <math.h>
+#ifdef LIBNETDEVNAME_PRESENT
+#include <netdevname.h>
+#include <linux/if.h>
+#endif
+
#include "utils.h"
#include "tc_util.h"
#include "tc_common.h"
@@ -52,6 +57,10 @@ int tc_class_modify(int cmd, unsigned flags, int argc, char **argv)
char d[16];
char k[16];
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
+
memset(&req, 0, sizeof(req));
memset(&est, 0, sizeof(est));
memset(d, 0, sizeof(d));
@@ -67,7 +76,13 @@ int tc_class_modify(int cmd, unsigned flags, int argc, char **argv)
NEXT_ARG();
if (d[0])
duparg("dev", *argv);
+#ifndef LIBNETDEVNAME_PRESENT
strncpy(d, *argv, sizeof(d)-1);
+#else
+ if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
+ show_firmware_alias_usage(*argv);
+ strncpy(d, kernel_name, sizeof (d) - 1);
+#endif
} else if (strcmp(*argv, "classid") == 0) {
__u32 handle;
NEXT_ARG();
@@ -237,6 +252,10 @@ int tc_class_list(int argc, char **argv)
struct tcmsg t;
char d[16];
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
+
memset(&t, 0, sizeof(t));
t.tcm_family = AF_UNSPEC;
memset(d, 0, sizeof(d));
@@ -246,7 +265,13 @@ int tc_class_list(int argc, char **argv)
NEXT_ARG();
if (d[0])
duparg("dev", *argv);
+#ifndef LIBNETDEVNAME_PRESENT
strncpy(d, *argv, sizeof(d)-1);
+#else
+ if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
+ show_firmware_alias_usage(*argv);
+ strncpy(d, kernel_name, sizeof (d) - 1);
+#endif
} else if (strcmp(*argv, "qdisc") == 0) {
NEXT_ARG();
if (filter_qdisc)
diff --git a/tc/tc_filter.c b/tc/tc_filter.c
index 919c57c..e144f9d 100644
--- a/tc/tc_filter.c
+++ b/tc/tc_filter.c
@@ -21,6 +21,11 @@
#include <string.h>
#include <linux/if_ether.h>
+#ifdef LIBNETDEVNAME_PRESENT
+#include <netdevname.h>
+#include <linux/if.h>
+#endif
+
#include "rt_names.h"
#include "utils.h"
#include "tc_util.h"
@@ -61,6 +66,10 @@ int tc_filter_modify(int cmd, unsigned flags, int argc, char **argv)
char k[16];
struct tc_estimator est;
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
+
memset(&req, 0, sizeof(req));
memset(&est, 0, sizeof(est));
memset(d, 0, sizeof(d));
@@ -80,7 +89,13 @@ int tc_filter_modify(int cmd, unsigned flags, int argc, char **argv)
NEXT_ARG();
if (d[0])
duparg("dev", *argv);
+#ifndef LIBNETDEVNAME_PRESENT
strncpy(d, *argv, sizeof(d)-1);
+#else
+ if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
+ show_firmware_alias_usage(*argv);
+ strncpy(d, kernel_name, sizeof (d) - 1);
+#endif
} else if (strcmp(*argv, "root") == 0) {
if (req.t.tcm_parent) {
fprintf(stderr, "Error: \"root\" is duplicate parent ID\n");
@@ -268,6 +283,10 @@ int tc_filter_list(int argc, char **argv)
__u32 protocol = 0;
char *fhandle = NULL;
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
+
memset(&t, 0, sizeof(t));
t.tcm_family = AF_UNSPEC;
memset(d, 0, sizeof(d));
@@ -277,7 +296,13 @@ int tc_filter_list(int argc, char **argv)
NEXT_ARG();
if (d[0])
duparg("dev", *argv);
+#ifndef LIBNETDEVNAME_PRESENT
strncpy(d, *argv, sizeof(d)-1);
+#else
+ if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
+ show_firmware_alias_usage(*argv);
+ strncpy(d, kernel_name, sizeof (d) - 1);
+#endif
} else if (strcmp(*argv, "root") == 0) {
if (t.tcm_parent) {
fprintf(stderr, "Error: \"root\" is duplicate parent ID\n");
diff --git a/tc/tc_qdisc.c b/tc/tc_qdisc.c
index c7f2988..3a9b05c 100644
--- a/tc/tc_qdisc.c
+++ b/tc/tc_qdisc.c
@@ -21,6 +21,10 @@
#include <string.h>
#include <math.h>
#include <malloc.h>
+#ifdef LIBNETDEVNAME_PRESENT
+#include <netdevname.h>
+#include <linux/if.h>
+#endif
#include "utils.h"
#include "tc_util.h"
@@ -60,6 +64,10 @@ int tc_qdisc_modify(int cmd, unsigned flags, int argc, char **argv)
char buf[TCA_BUF_MAX];
} req;
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
+
memset(&req, 0, sizeof(req));
memset(&stab, 0, sizeof(stab));
memset(&est, 0, sizeof(est));
@@ -76,7 +84,13 @@ int tc_qdisc_modify(int cmd, unsigned flags, int argc, char **argv)
NEXT_ARG();
if (d[0])
duparg("dev", *argv);
+#ifndef LIBNETDEVNAME_PRESENT
strncpy(d, *argv, sizeof(d)-1);
+#else
+ if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
+ show_firmware_alias_usage(*argv);
+ strncpy(d, kernel_name, sizeof (d) - 1);
+#endif
} else if (strcmp(*argv, "handle") == 0) {
__u32 handle;
if (req.t.tcm_handle)
@@ -282,6 +296,10 @@ int tc_qdisc_list(int argc, char **argv)
struct tcmsg t;
char d[16];
+#ifdef LIBNETDEVNAME_PRESENT
+ char kernel_name[IFNAMSIZ];
+#endif
+
memset(&t, 0, sizeof(t));
t.tcm_family = AF_UNSPEC;
memset(&d, 0, sizeof(d));
@@ -289,7 +307,13 @@ int tc_qdisc_list(int argc, char **argv)
while (argc > 0) {
if (strcmp(*argv, "dev") == 0) {
NEXT_ARG();
+#ifndef LIBNETDEVNAME_PRESENT
strncpy(d, *argv, sizeof(d)-1);
+#else
+ if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
+ show_firmware_alias_usage(*argv);
+ strncpy(d, kernel_name, sizeof (d) - 1);
+#endif
#ifdef TC_H_INGRESS
} else if (strcmp(*argv, "ingress") == 0) {
if (t.tcm_parent) {
--
1.7.0.1
With regards,
Narendra K
^ permalink raw reply related
* Re[2]: [Bugme-new] [Bug 16568] New: Regression and incompatibility with Windows SP2-SP3-Vista TCP stack causing lost connections
From: Yuriy @ 2010-08-12 16:46 UTC (permalink / raw)
To: Eric Dumazet; +Cc: Andrew Morton, netdev, bugzilla-daemon, bugme-daemon
In-Reply-To: <1281625773.2494.38.camel@edumazet-laptop>
Hi, Eric.
You wrote 12.08.2010, 18:09:33:
ED> Le jeudi 12 août 2010 à 07:40 -0700, Andrew Morton a écrit :
>> (switched to email. Please respond via emailed reply-to-all, not via the
>> bugzilla web interface).
>> On Thu, 12 Aug 2010 08:20:01 GMT bugzilla-daemon@bugzilla.kernel.org wrote:
>> > https://bugzilla.kernel.org/show_bug.cgi?id=16568
>> >
>> > Summary: Regression and incompatibility with Windows
>> > SP2-SP3-Vista TCP stack causing lost connections
>> > Product: Networking
>> > Version: 2.5
>> > Kernel Version: 2.6.30+
>> > Platform: All
>> > OS/Version: Linux
>> > Tree: Mainline
>> > Status: NEW
>> > Severity: high
>> > Priority: P1
>> > Component: IPV4
>> > AssignedTo: shemminger@linux-foundation.org
>> > ReportedBy: yuriy@ucoz.com
>> > Regression: No
>> >
>> >
>> > Hi.
>> > I administer about 50 highly-loaded web servers (free CMS hosting) under linux.
>> > Having on most of them kernel versions between 2.6.24 and 2.6.29 at the
>> > beginnig of the year, I made TCP sysctls tunings for increasing DDOS and
>> > different flooding protection (our servers have attacks rather often).
>> > tcp_tw_recyle=1 was among of them, as many manuals in the net recommend to do
>> > this and linux documentation does not say anything bad. Having periodic kernel
>> > panics connected with bugs in ethernet card drivers and ext3 and after founding
>> > that 2.6.31+ kernels work faster with ext3, I upgraded almost all kernels to
>> > 2.6.32.8, which was already being tested on several servers for several months.
>> > Somewhen after that we began to receive complaints from our users (site owners)
>> > that they (and their visitors) see very unstable work of their sites. It looked
>> > like HTTP-connections were just lost in a random way. Not everybody had the
>> > problem, just a small percent. We tried to find problem with internet providers
>> > or buggy firewalls, but finally came to conclusion that problem is connected
>> > with our servers. Analizing situations with lost connections using tcpdump i
>> > found that client host send packets, BUT LINUX JUST IGNORES THEM, there was
>> > SYN-packet repeated 3 times with interval of 3 secs, but NO SYN-ACK reply.
>> > Most problems had users with Windows SP3 (i.e. almost all users with SP3 had
>> > the problem). I booted one server with old 2.6.24 kernel and found that problem
>> > dissappeared. Then began look for exact kernel version, that introduced
>> > incompatibility. Using binary search I compiled several kernels between 2.6.24
>> > and 2.6.32.8 and found that 2.6.29.6 DO NO have the problem, but 2.6.30 DOES.
>> > Studing commits made to tcp_input.c and tcp_ipv4.c (which i supposed were
>> > involved) between that releases I found this one.
>> > author Eric Dumazet <dada1@cosmosbay.com>
>> > Wed, 11 Mar 2009 16:23:57 +0000 (09:23 -0700)
>> > committer David S. Miller <davem@davemloft.net>
>> > Wed, 11 Mar 2009 16:23:57 +0000 (09:23 -0700)
>> > commit fc1ad92dfc4e363a055053746552cdb445ba5c57
>> >
>> > tcp: allow timestamps even if SYN packet has tsval=0
>> >
>> > Some systems send SYN packets with apparently wrong RFC1323 timestamp
>> > option values [timestamp tsval=0 tsecr=0].
>> > It might be for security reasons (http://www.secuobs.com/plugs/25220.shtml )
>> > Linux TCP stack ignores this option and sends back a SYN+ACK packet
>> > without timestamp option, thus many TCP flows cannot use timestamps
>> > and lose some benefit of RFC1323.
>> > Other operating systems seem to not care about initial tsval value, and let
>> > tcp flows to negotiate timestamp option.
>> >
>> > net/ipv4/tcp_ipv4.c diff :
>> >
>> > --- a/net/ipv4/tcp_ipv4.c
>> > +++ b/net/ipv4/tcp_ipv4.c
>> > @@ -1226,15 +1226,6 @@ int tcp_v4_conn_request(struct sock *sk, struct sk_buff
>> > *skb)
>> > if (want_cookie && !tmp_opt.saw_tstamp)
>> > tcp_clear_options(&tmp_opt);
>> >
>> > - if (tmp_opt.saw_tstamp && !tmp_opt.rcv_tsval) {
>> > - /* Some OSes (unknown ones, but I see them on web server, which
>> > - * contains information interesting only for windows'
>> > - * users) do not send their stamp in SYN. It is easy case.
>> > - * We simply do not advertise TS support.
>> > - */
>> > - tmp_opt.saw_tstamp = 0;
>> > - tmp_opt.tstamp_ok = 0;
>> > - }
>> > tmp_opt.tstamp_ok = tmp_opt.saw_tstamp;
>> >
>> > tcp_openreq_init(req, &tmp_opt, skb);
>> >
>> > Removing that was not very good. Having analized lost connections from SP3 I
>> > know that they have timestamps turned on and timestamp value is 0. Here is it:
>> > 13:39:10.430498 IP 192.168.99.130.3493 > 192.168.99.100.80: S
>> > 2507911465:2507911465(0) win 65535 <mss 1460,nop,wscale 3,nop,nop,timestamp 0
>> > 0,nop,nop,sackOK>
>> > 0x0000: 4500 0040 2bda 4000 8006 86a6 c0a8 6382 E..@+.@.......c.
>> > 0x0010: c0a8 6364 0da5 0050 957b b129 0000 0000 ..cd...P.{.)....
>> > 0x0020: b002 ffff 992c 0000 0204 05b4 0103 0303 .....,..........
>> > 0x0030: 0101 080a 0000 0000 0000 0000 0101 0402 ................
>> >
>> > Having above code fragment removed we got tmp_opt.tstamp_ok=1, as i understand.
>> > But a little later in source code of tcp_ipv4.c read:
>> > /* VJ's idea. We save last timestamp seen
>> > * from the destination in peer table, when entering
>> > * state TIME-WAIT, and check against it before
>> > * accepting new connection request.
>> > *
>> > * If "isn" is not zero, this request hit alive
>> > * timewait bucket, so that all the necessary checks
>> > * are made in the function processing timewait state.
>> > */
>> > if (tmp_opt.saw_tstamp &&
>> > tcp_death_row.sysctl_tw_recycle &&
>> > (dst = inet_csk_route_req(sk, req)) != NULL &&
>> > (peer = rt_get_peer((struct rtable *)dst)) != NULL &&
>> > peer->v4daddr == saddr) {
>> > if ((u32)get_seconds() - peer->tcp_ts_stamp < TCP_PAWS_MSL &&
>> > (s32)(peer->tcp_ts - req->ts_recent) >
>> > TCP_PAWS_WINDOW) {
>> > NET_INC_STATS_BH(sock_net(sk), LINUX_MIB_PAWSPASSIVEREJECTED);
>> > goto drop_and_release;
>> > }
>> > }
>> > which in some way (tmp_opt.saw_tstamp && tcp_death_row.sysctl_tw_recycle are
>> > true), random way, having not closed time-wait sockets from the pear, leads to
>> > packet ignorence.
>> >
>> > As for me, i understand, that i should not enable tw_recycle, BUT DOCUMENTATION
>> > DOES NOT STATE, that enabling it i'll got random and rather often lost of
>> > connections from some types of popular clients (like Windows).
>> > Concerning above stated commit, it should include something to prevent above
>> > condition to become true if tmp_opt.rcv_tsval==0. I'm not sure, but something
>> > like
>> > if (tmp_opt.saw_tstamp &&
>> > + tmp_opt.rcv_tsval &&
>> > tcp_death_row.sysctl_tw_recycle &&
>> > (dst = inet_csk_route_req(sk, req)) != NULL &&
>> > (peer = rt_get_peer((struct rtable *)dst)) != NULL &&
>> >
>> > just to not provide regression and strong TCP-stack incompatibility in case
>> > tw_recycle is enabled.
>> > Also documentation does not state, that tw_recyle should not be used at all for
>> > internet servers, because web-clients, which are behind NAT, will have problems
>> > connected with the same above condition because successive connections from
>> > different clients (which have common IP) could have incompatible timestamps.
>> >
>> > Sorry if i detracted somebody busy from his work with my unimportant problem.
>> >
>> --
ED> Hi Yuriy
ED> Interesting analysis but wrong conclusions :)
ED> Clients using RFC1323 (timestamps) and behind a NAT device will barf on
ED> your setup. No matter they use Windows SP3 or other operating system.
ED> Only because RFC1323 is more often enabled at client level (a registry
ED> change on Windows XP, Vista or Seven I dont know), you start noticing
ED> your server drops more connections than before.
ED> Point is :
ED> Dont mess with tcp_tw_recycle=1, tcp_timestamps=1 on public machines
ED> Its a non working setup, for clients behind NAT devices (since their
ED> TSVAL will probably lead to incorrect behavior on server, with infamous
ED> LINUX_MIB_PAWSPASSIVEREJECTED status seen on netstat -s, as you
ED> discovered.
ED> And your patch solves nothing for this very common case, unless the NAT
ED> device is able to overwrite TSVAL values with its own values (very
ED> unlikely !!!)
ED> A working setup is (and is the default) :
ED> tcp_tw_recycle=0
ED> tcp_timestamps=1
ED> Documentation might be improved, but I feel whole "tcp_tw_recycle"
ED> affair is really too tricky to be ever documented (not mentioning using
ED> it ;) )
Thanks for reply.
Main idea that i wanted to say is just to document this feature appropriately as internet is full of recommendations to enable it.
Just few words like "do not used it on public servers" would be much better than now.
--
Regards,
Yuriy mailto:yuriy@ucoz.com
^ permalink raw reply
* Re: [PATCH] Add firmware label support to iproute2
From: Stephen Hemminger @ 2010-08-12 18:10 UTC (permalink / raw)
To: Narendra K; +Cc: netdev, matt_domsch, charles_rose, jordan_hargrave
In-Reply-To: <20100812173537.GA29784@auslistsprd01.us.dell.com>
On Thu, 12 Aug 2010 12:35:37 -0500
Narendra K <Narendra_K@dell.com> wrote:
> +ifeq ($(shell test -L /usr/local/lib/libnetdevname.so; echo $$?),0)
> +LDLIBS +=-lnetdevname
> +DEFINES += -DLIBNETDEVNAME_PRESENT
> +endif
I assume any user or distro using libnetdevname will put it in
the standard path not /usr/lib, don't hard code the path here.
why not build a sample program like the ATM checks?
^ permalink raw reply
* Re: [PATCH] Add firmware label support to iproute2
From: Stephen Hemminger @ 2010-08-12 18:12 UTC (permalink / raw)
To: Narendra K; +Cc: netdev, matt_domsch, charles_rose, jordan_hargrave
In-Reply-To: <20100812173537.GA29784@auslistsprd01.us.dell.com>
On Thu, 12 Aug 2010 12:35:37 -0500
Narendra K <Narendra_K@dell.com> wrote:
> +#ifndef LIBNETDEVNAME_PRESENT
> filter_dev = *argv;
> +#else
> + if (netdev_alias_to_kernelname(*argv, kernel_name) < 0)
> + show_firmware_alias_usage(*argv);
> + filter_dev = kernel_name;
> +#endif
> }
like the kernel, I don't like ifdef cases in main code.
You should put in stub inline that returns appropriate error.
What happens if alias matches existing interface name?
^ permalink raw reply
* Re: [PATCH] iproute2: dont filter cached routes on iproute_get
From: Fabio Comolli @ 2010-08-12 18:58 UTC (permalink / raw)
To: Ulrich Weber; +Cc: Andreas Henriksson, shemminger, netdev
In-Reply-To: <4C63BCED.5000209@astaro.com>
Works for me (for ipv4, I cannot test ipv6).
You can add my Tested-By in case you need it.
Regards,
Fabio
On Thu, Aug 12, 2010 at 11:20 AM, Ulrich Weber <uweber@astaro.com> wrote:
> The patch should be applied on top of iproute2 v2.6.35.
>
> Cheers
> Ulrich
>
> On 08/12/2010 11:12 AM, Fabio Comolli wrote:
>> Hi.
>> Is this patch supposed to be applied on top of plain iproute2 v2.6.35
>> or on top of the previous Andreas' patch?
>>
>>
>>
>> On Thu, Aug 12, 2010 at 11:05 AM, Ulrich Weber <uweber@astaro.com> wrote:
>>> iproute_get will return cloned routes for IPv4
>>> and cloned as well non-cloned routes for IPv6.
>>>
>>> Therefore RTM_F_CLONED flag should not be checked
>>> for iproute_get routes. Check in print_route will
>>> always fail because valid values are 0 and 1.
>>>
>>> Signed-off-by: Ulrich Weber <uweber@astaro.com>
>>> ---
>>> ip/iproute.c | 1 +
>>> 1 files changed, 1 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/ip/iproute.c b/ip/iproute.c
>>> index 711576e..b43933c 100644
>>> --- a/ip/iproute.c
>>> +++ b/ip/iproute.c
>>> @@ -1286,6 +1286,7 @@ int iproute_get(int argc, char **argv)
>>> memset(&req, 0, sizeof(req));
>>>
>>> iproute_reset_filter();
>>> + filter.cloned = 2;
>>>
>>> req.n.nlmsg_len = NLMSG_LENGTH(sizeof(struct rtmsg));
>>> req.n.nlmsg_flags = NLM_F_REQUEST;
>>> --
>>> 1.7.0.4
>>>
>>>
>
>
> --
> Ulrich Weber | uweber@astaro.com | Software Engineer
> Astaro GmbH & Co. KG | www.astaro.com | Phone +49-721-25516-0 | Fax –200
> An der RaumFabrik 33a | 76227 Karlsruhe | Germany
>
^ permalink raw reply
* Re: [iproute2] iproute2: Fix 'addr flush secondary' logic.
From: Brian Haley @ 2010-08-12 19:00 UTC (permalink / raw)
To: Ben Greear; +Cc: netdev
In-Reply-To: <4C6328A8.4070703@candelatech.com>
On 08/11/2010 06:48 PM, Ben Greear wrote:
> Looks like the code was broken in several different places.
>
> * It ran only a single filter if there were multiple.
> * Don't want to flush in a loop if you are doing primary
> because otherwise promoted seconaries will get deleted
> for each additional loop (10 in upstream code).
> * No idea what a while (0); statement at the end of a for
> loop does, but I don't think it needed to be there!
>
> The attached patch makes it work for me, supporting
> flushing primary or secondary addresses.
> diff --git a/ip/ipaddress.c b/ip/ipaddress.c
> index 5f0789c..803df17 100644
> --- a/ip/ipaddress.c
> +++ b/ip/ipaddress.c
> @@ -637,7 +637,7 @@ int print_addrinfo_primary(const struct sockaddr_nl *who, struct nlmsghdr *n,
> {
> struct ifaddrmsg *ifa = NLMSG_DATA(n);
>
> - if (!ifa->ifa_flags & IFA_F_SECONDARY)
> + if (ifa->ifa_flags & IFA_F_SECONDARY)
return 0;
This should be:
if (!(ifa->ifa_flags & IFA_F_SECONDARY))
as this function does the opposite of what it seems.
> @@ -648,7 +648,7 @@ int print_addrinfo_secondary(const struct sockaddr_nl *who, struct nlmsghdr *n,
> {
> struct ifaddrmsg *ifa = NLMSG_DATA(n);
>
> - if (ifa->ifa_flags & IFA_F_SECONDARY)
> + if (!(ifa->ifa_flags & IFA_F_SECONDARY))
return 0;
>From testing, the original code here was correct.
> @@ -865,6 +865,13 @@ static int ipaddr_list_or_flush(int argc, char **argv, int flush)
> printf("\n*** Round %d, deleting %d addresses ***\n", round, filter.flushed);
> fflush(stdout);
> }
> +
> + /* If we are flushing, and specifying primary, then we want to flush only a single round.
> + * Otherwise, we'll start flushing secondaries that were promoted to primaries
> + */
> + if (!(filter.flags & IFA_F_SECONDARY) && (filter.flagmask & IFA_F_SECONDARY)) {
> + return 0;
> + }
This doesn't seem to do anything, I see all my IPv4 addresses flushed if I
run 'ip -4 -s a flush primary dev eth2'. And it says it only deleted one
when it deleted two addresses :-/ Also, if it did work, it should really goto
a few lines above so it prints the summary stats:
if (filter.flushed == 0) {
flush_done:
if (show_stats) {
Even when I corrected the lines above, it didn't work:
# ip -4 a s dev eth2
2: eth2: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP qlen 1000
inet 192.168.6.4/24 brd 192.168.6.255 scope global eth2
# ip a a 192.168.6.100/24 brd + dev eth2
# ip -4 a s dev eth2
2: eth2: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP qlen 1000
inet 192.168.6.4/24 brd 192.168.6.255 scope global eth2
inet 192.168.6.100/24 brd 192.168.6.255 scope global secondary eth2
# ./ip -4 -s -s -o a flush primary dev eth2
2: eth2 inet 192.168.6.4/24 brd 192.168.6.255 scope global eth2
*** Round 1, deleting 1 addresses ***
[missing *** Flush is complete after 1 round ***]
# ip -4 a s dev eth2
[nothing]
Where did my .100 secondary address go? Now this will bug me until I figure
out why. Maybe it's because I'm booted to 2.6.32.
> diff --git a/lib/libnetlink.c b/lib/libnetlink.c
> index cfeb894..d18e8a0 100644
Can you give an example of how you tested this double filter change? My
distro /sbin/ip seemed to work just fine.
> - if (status) {
> + if (msglen) {
> fprintf(stderr, "!!!Remnant of size %d\n", status);
> exit(1);
> }
Should the arg to the fprintf() be msglen too?
-Brian
^ permalink raw reply
* Re: [iproute2] iproute2: Fix 'addr flush secondary' logic.
From: Ben Greear @ 2010-08-12 19:10 UTC (permalink / raw)
To: Brian Haley; +Cc: netdev
In-Reply-To: <4C6444EA.1070704@hp.com>
On 08/12/2010 12:00 PM, Brian Haley wrote:
> On 08/11/2010 06:48 PM, Ben Greear wrote:
>> Looks like the code was broken in several different places.
>>
>> * It ran only a single filter if there were multiple.
>> * Don't want to flush in a loop if you are doing primary
>> because otherwise promoted seconaries will get deleted
>> for each additional loop (10 in upstream code).
>> * No idea what a while (0); statement at the end of a for
>> loop does, but I don't think it needed to be there!
>>
>> The attached patch makes it work for me, supporting
>> flushing primary or secondary addresses.
>
>> diff --git a/ip/ipaddress.c b/ip/ipaddress.c
>> index 5f0789c..803df17 100644
>> --- a/ip/ipaddress.c
>> +++ b/ip/ipaddress.c
>> @@ -637,7 +637,7 @@ int print_addrinfo_primary(const struct sockaddr_nl *who, struct nlmsghdr *n,
>> {
>> struct ifaddrmsg *ifa = NLMSG_DATA(n);
>>
>> - if (!ifa->ifa_flags& IFA_F_SECONDARY)
>> + if (ifa->ifa_flags& IFA_F_SECONDARY)
> return 0;
>
> This should be:
>
> if (!(ifa->ifa_flags& IFA_F_SECONDARY))
>
> as this function does the opposite of what it seems.
I see no reason to let it do the opposite of what it seems.
From what I can tell, the original code never even called this
method anyway since it was the second filter and only the first
filter was used.
>> @@ -648,7 +648,7 @@ int print_addrinfo_secondary(const struct sockaddr_nl *who, struct nlmsghdr *n,
>> {
>> struct ifaddrmsg *ifa = NLMSG_DATA(n);
>>
>> - if (ifa->ifa_flags& IFA_F_SECONDARY)
>> + if (!(ifa->ifa_flags& IFA_F_SECONDARY))
> return 0;
>
>> From testing, the original code here was correct.
It deleted addresses, but not how it was intended to work,
I think.
>> @@ -865,6 +865,13 @@ static int ipaddr_list_or_flush(int argc, char **argv, int flush)
>> printf("\n*** Round %d, deleting %d addresses ***\n", round, filter.flushed);
>> fflush(stdout);
>> }
>> +
>> + /* If we are flushing, and specifying primary, then we want to flush only a single round.
>> + * Otherwise, we'll start flushing secondaries that were promoted to primaries
>> + */
>> + if (!(filter.flags& IFA_F_SECONDARY)&& (filter.flagmask& IFA_F_SECONDARY)) {
>> + return 0;
>> + }
>
> This doesn't seem to do anything, I see all my IPv4 addresses flushed if I
> run 'ip -4 -s a flush primary dev eth2'. And it says it only deleted one
> when it deleted two addresses :-/ Also, if it did work, it should really goto
> a few lines above so it prints the summary stats:
>
> if (filter.flushed == 0) {
> flush_done:
> if (show_stats) {
>
> Even when I corrected the lines above, it didn't work:
>
> # ip -4 a s dev eth2
> 2: eth2:<BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP qlen 1000
> inet 192.168.6.4/24 brd 192.168.6.255 scope global eth2
>
> # ip a a 192.168.6.100/24 brd + dev eth2
> # ip -4 a s dev eth2
> 2: eth2:<BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP qlen 1000
> inet 192.168.6.4/24 brd 192.168.6.255 scope global eth2
> inet 192.168.6.100/24 brd 192.168.6.255 scope global secondary eth2
>
> # ./ip -4 -s -s -o a flush primary dev eth2
> 2: eth2 inet 192.168.6.4/24 brd 192.168.6.255 scope global eth2
>
> *** Round 1, deleting 1 addresses ***
> [missing *** Flush is complete after 1 round ***]
>
> # ip -4 a s dev eth2
> [nothing]
>
> Where did my .100 secondary address go? Now this will bug me until I figure
> out why. Maybe it's because I'm booted to 2.6.32.
Do you have the 'promote secondaries' sysctl enabled? I think you
need that to have the secondaries not just dissappear upon removal
of the primary.
>> diff --git a/lib/libnetlink.c b/lib/libnetlink.c
>> index cfeb894..d18e8a0 100644
>
> Can you give an example of how you tested this double filter change? My
> distro /sbin/ip seemed to work just fine.
>
>> - if (status) {
>> + if (msglen) {
>> fprintf(stderr, "!!!Remnant of size %d\n", status);
>> exit(1);
>> }
>
> Should the arg to the fprintf() be msglen too?
Yes, that should be fixed.
Thanks for the review..I'll make this change and show you the commands
I used for testing.
Thanks,
Ben
--
Ben Greear <greearb@candelatech.com>
Candela Technologies Inc http://www.candelatech.com
^ permalink raw reply
* Re: sky2 driver fails to handle "rx length error: status 0x5d60100 length 2982" gracefully
From: Stephen Hemminger @ 2010-08-12 19:18 UTC (permalink / raw)
To: Maciej Żenczykowski; +Cc: Stephen Hemminger, Linux NetDev
In-Reply-To: <AANLkTinM2m-dK2FYw5VBi3eBAhBRrrzZ+vH5aCtDoDVS@mail.gmail.com>
On Thu, 12 Aug 2010 09:58:01 -0700
Maciej Żenczykowski <zenczykowski@gmail.com> wrote:
> I'm not sure if there is a known good kernel. It seems to be getting
> worse over time (as I upgrade kernels), but maybe the hardware is
> aging and the situation is becoming more likely. When it first
> started happening it was like once every 2-3 months or even rarer.
> Now it has happened again since the last time I posted to this
> thread...
>
> Aug 12 08:29:08 nike kernel: sky2 0000:0c:00.0: eth0: rx length error:
> status 0x5e50100 length 3013
>
> > Are you trying to run with Jumbo >1500 MTU?
>
> No, normal 1500 MTU network, with ipv4 and ipv6 native traffic. Not a
> huge amount of traffic either.
> And indeed the problem seems to happen just as easily (if not easier)
> when the machine (and thus the network) is close(r) to idle (ie.
> overnight, etc) - although that might just be a matter of more time
> passing.
>
> Are you sure there is nothing the driver could do on seeing such an error?
> It seems like since "ip link set eth0 down && ip link set eth0 up"
> fixes it, what it should do is some sort of partial reset...
>
> I will try to verify if 'ethtool -K eth0 rx off && ethtool -K eth0 rx
> on' is enough to fix the problem (when it happens once again).
> Afterwards I'll turn of rx csum (ethtool -K eth0 rx off) and will see
> if it happens again.
The status values indicate that the GMAC (frame parser) got a reasonable
size frame but the DMA merged frames together. This indicates a timing
problem. There are some bits which even with NDA programmers manual doesn't
help with. The Linux driver expects the BIOS or EEPROM to set them correctly
because different problems different settings.
There is firmware in eeprom that configures internal state. On one motherboard
the vendor provided an update. There is no good way to update this from Linux,
you need to go system vendor and install firmware with their native OS (ie Windows
or MacOS).
^ permalink raw reply
* Re: sky2 driver fails to handle "rx length error: status 0x5d60100 length 2982" gracefully
From: Maciej Żenczykowski @ 2010-08-12 20:31 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: Stephen Hemminger, Linux NetDev
In-Reply-To: <20100812151819.282636fe@s6510>
> The status values indicate that the GMAC (frame parser) got a reasonable
> size frame but the DMA merged frames together. This indicates a timing
> problem. There are some bits which even with NDA programmers manual doesn't
> help with. The Linux driver expects the BIOS or EEPROM to set them correctly
> because different problems different settings.
>
> There is firmware in eeprom that configures internal state. On one motherboard
> the vendor provided an update. There is no good way to update this from Linux,
> you need to go system vendor and install firmware with their native OS (ie Windows
> or MacOS).
Perfectly reasonable response. If there was a firmware update fix,
I'd apply it...
That would presumably prevent this from ever happening in the first place.
But why doesn't the network driver reset the nic when it detects this
'rx length' error?
I'm not asking for the error to not happen (besides it happens very rarely)...
I'm asking, why does this error happening permanently hose the network driver.
Once this happens the network card is not usable - traffic does not
flow through it.
You need to "ip link set down && ... up" to fix it. Isn't this
something the driver could and should do all by itself?
^ permalink raw reply
* Re: TAHI CN-6-4-1 failed on Linux 2.6.32 kernel
From: Brian Haley @ 2010-08-12 21:10 UTC (permalink / raw)
To: Steve Chen; +Cc: usagi-users-ctl, netdev
In-Reply-To: <AANLkTim-zWhq9aGrvH2PdS3VjfBvmh=qL=1Sy3Z+VPgT@mail.gmail.com>
Hi Steve,
On 07/28/2010 11:20 PM, Steve Chen wrote:
> Hello,
>
> The TAHI correspondent node tests CN-6-4-1 (Processing in upper layer
> - Echo Checksum) failed for me in the 2.6.32 kernel. It appears that
> the Linux kernel is replying the ICMP echo request in
> icmpv6_echo_reply without much checking. Is this an intentional
> non-conformance to RFC3775 section 9.3.1?
Sorry for the late reply. I've run these tests in the past against
SLES11 (2.6.27 ?) back in January 2009 and this one passed from looking
at my logs. I don't have that system around anymore to check the config,
etc. I didn't see any obvious commit that would have broken it from a
quick look, do you have a test setup to do some debugging? It will
take a little time for me to re-configure mine to run this test.
-Brian
^ permalink raw reply
* Re: [PATCH staging] Add SBE 2T3E3 WAN driver
From: Krzysztof Halasa @ 2010-08-12 21:14 UTC (permalink / raw)
To: Greg KH; +Cc: netdev
In-Reply-To: <20100801002713.GA6751@kroah.com>
Greg,
I have added the TODO file and removed #define DRV_NAME "SBE 2T3E3".
The include/linux/pci_ids.h chunk is now also in Linus' tree, I'm still
not removing it from this patch to avoid dependency on the very tip.
Tested with 2.6.35.
TIA for looking into this.
BTW the original driver tarball is now accessible at
http://userweb.kernel.org/~chris/SBE_2T3_Linux_2.0c.tgz
+++
This is a driver for SBE Inc.'s dual port T3/E3 WAN cards. Based on
their original GPLed driver.
It needs at least a new generic HDLC setup code (not yet written) before
moving to drivers/net/wan.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
drivers/staging/Kconfig | 2 +
drivers/staging/Makefile | 1 +
drivers/staging/sbe-2t3e3/2t3e3.h | 894 ++++++++++++++++++++++++++++++++++
drivers/staging/sbe-2t3e3/Kconfig | 13 +
drivers/staging/sbe-2t3e3/Makefile | 4 +
drivers/staging/sbe-2t3e3/TODO | 6 +
drivers/staging/sbe-2t3e3/cpld.c | 366 ++++++++++++++
drivers/staging/sbe-2t3e3/ctrl.c | 362 ++++++++++++++
drivers/staging/sbe-2t3e3/ctrl.h | 131 +++++
drivers/staging/sbe-2t3e3/dc.c | 502 +++++++++++++++++++
drivers/staging/sbe-2t3e3/exar7250.c | 217 ++++++++
drivers/staging/sbe-2t3e3/exar7300.c | 182 +++++++
drivers/staging/sbe-2t3e3/intr.c | 635 ++++++++++++++++++++++++
drivers/staging/sbe-2t3e3/io.c | 352 +++++++++++++
drivers/staging/sbe-2t3e3/main.c | 171 +++++++
drivers/staging/sbe-2t3e3/maps.c | 104 ++++
drivers/staging/sbe-2t3e3/module.c | 210 ++++++++
drivers/staging/sbe-2t3e3/netdev.c | 142 ++++++
include/linux/pci_ids.h | 3 +
19 files changed, 4297 insertions(+), 0 deletions(-)
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 984a754..3a21878 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -147,5 +147,7 @@ source "drivers/staging/mrst-touchscreen/Kconfig"
source "drivers/staging/msm/Kconfig"
+source "drivers/staging/sbe-2t3e3/Kconfig"
+
endif # !STAGING_EXCLUDE_BUILD
endif # STAGING
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 9fa2513..39687c5 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -54,3 +54,4 @@ obj-$(CONFIG_ADIS16255) += adis16255/
obj-$(CONFIG_FB_XGI) += xgifb/
obj-$(CONFIG_TOUCHSCREEN_MRSTOUCH) += mrst-touchscreen/
obj-$(CONFIG_MSM_STAGING) += msm/
+obj-$(CONFIG_SBE_2T3E3) += sbe-2t3e3/
diff --git a/drivers/staging/sbe-2t3e3/2t3e3.h b/drivers/staging/sbe-2t3e3/2t3e3.h
new file mode 100644
index 0000000..fe9f086
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/2t3e3.h
@@ -0,0 +1,894 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#ifndef T3E3_H
+#define T3E3_H
+
+#include <linux/hdlc.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include "ctrl.h"
+
+/**************************************************************
+ * 21143
+ **************************************************************/
+
+/* CSR */
+#define SBE_2T3E3_21143_REG_BUS_MODE 0
+#define SBE_2T3E3_21143_REG_TRANSMIT_POLL_DEMAND 1
+#define SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND 2
+#define SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS 3
+#define SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS 4
+#define SBE_2T3E3_21143_REG_STATUS 5
+#define SBE_2T3E3_21143_REG_OPERATION_MODE 6
+#define SBE_2T3E3_21143_REG_INTERRUPT_ENABLE 7
+#define SBE_2T3E3_21143_REG_MISSED_FRAMES_AND_OVERFLOW_COUNTER 8
+#define SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT 9
+#define SBE_2T3E3_21143_REG_BOOT_ROM_PROGRAMMING_ADDRESS 10
+#define SBE_2T3E3_21143_REG_GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL 11
+#define SBE_2T3E3_21143_REG_SIA_STATUS 12
+#define SBE_2T3E3_21143_REG_SIA_CONNECTIVITY 13
+#define SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE 14
+#define SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT 15
+#define SBE_2T3E3_21143_REG_MAX 16
+
+/* CSR0 - BUS_MODE */
+#define SBE_2T3E3_21143_VAL_WRITE_AND_INVALIDATE_ENABLE 0x01000000
+#define SBE_2T3E3_21143_VAL_READ_LINE_ENABLE 0x00800000
+#define SBE_2T3E3_21143_VAL_READ_MULTIPLE_ENABLE 0x00200000
+#define SBE_2T3E3_21143_VAL_TRANSMIT_AUTOMATIC_POLLING_200us 0x00020000
+#define SBE_2T3E3_21143_VAL_TRANSMIT_AUTOMATIC_POLLING_DISABLED 0x00000000
+#define SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_32 0x0000c000
+#define SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_16 0x00008000
+#define SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_8 0x00004000
+#define SBE_2T3E3_21143_VAL_BUS_ARBITRATION_RR 0x00000002
+#define SBE_2T3E3_21143_VAL_SOFTWARE_RESET 0x00000001
+
+/* CSR5 - STATUS */
+#define SBE_2T3E3_21143_VAL_GENERAL_PURPOSE_PORT_INTERRUPT 0x04000000
+#define SBE_2T3E3_21143_VAL_ERROR_BITS 0x03800000
+#define SBE_2T3E3_21143_VAL_PARITY_ERROR 0x00000000
+#define SBE_2T3E3_21143_VAL_MASTER_ABORT 0x00800000
+#define SBE_2T3E3_21143_VAL_TARGET_ABORT 0x01000000
+#define SBE_2T3E3_21143_VAL_TRANSMISSION_PROCESS_STATE 0x00700000
+#define SBE_2T3E3_21143_VAL_TX_STOPPED 0x00000000
+#define SBE_2T3E3_21143_VAL_TX_SUSPENDED 0x00600000
+#define SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STATE 0x000e0000
+#define SBE_2T3E3_21143_VAL_RX_STOPPED 0x00000000
+#define SBE_2T3E3_21143_VAL_RX_SUSPENDED 0x000a0000
+#define SBE_2T3E3_21143_VAL_NORMAL_INTERRUPT_SUMMARY 0x00010000
+#define SBE_2T3E3_21143_VAL_ABNORMAL_INTERRUPT_SUMMARY 0x00008000
+#define SBE_2T3E3_21143_VAL_EARLY_RECEIVE_INTERRUPT 0x00004000
+#define SBE_2T3E3_21143_VAL_FATAL_BUS_ERROR 0x00002000
+#define SBE_2T3E3_21143_VAL_GENERAL_PURPOSE_TIMER_EXPIRED 0x00000800
+#define SBE_2T3E3_21143_VAL_EARLY_TRANSMIT_INTERRUPT 0x00000400
+#define SBE_2T3E3_21143_VAL_RECEIVE_WATCHDOG_TIMEOUT 0x00000200
+#define SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED 0x00000100
+#define SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE 0x00000080
+#define SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT 0x00000040
+#define SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW 0x00000020
+#define SBE_2T3E3_21143_VAL_TRANSMIT_JABBER_TIMEOUT 0x00000008
+#define SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE 0x00000004
+#define SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED 0x00000002
+#define SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT 0x00000001
+
+/* CSR6 - OPERATION_MODE */
+#define SBE_2T3E3_21143_VAL_SPECIAL_CAPTURE_EFFECT_ENABLE 0x80000000
+#define SBE_2T3E3_21143_VAL_RECEIVE_ALL 0x40000000
+#define SBE_2T3E3_21143_VAL_MUST_BE_ONE 0x02000000
+#define SBE_2T3E3_21143_VAL_SCRAMBLER_MODE 0x01000000
+#define SBE_2T3E3_21143_VAL_PCS_FUNCTION 0x00800000
+#define SBE_2T3E3_21143_VAL_TRANSMIT_THRESHOLD_MODE_10Mbs 0x00400000
+#define SBE_2T3E3_21143_VAL_TRANSMIT_THRESHOLD_MODE_100Mbs 0x00000000
+#define SBE_2T3E3_21143_VAL_STORE_AND_FORWARD 0x00200000
+#define SBE_2T3E3_21143_VAL_HEARTBEAT_DISABLE 0x00080000
+#define SBE_2T3E3_21143_VAL_PORT_SELECT 0x00040000
+#define SBE_2T3E3_21143_VAL_CAPTURE_EFFECT_ENABLE 0x00020000
+#define SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS 0x0000c000
+#define SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_1 0x00000000
+#define SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_2 0x00004000
+#define SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_3 0x00008000
+#define SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_4 0x0000c000
+#define SBE_2T3E3_21143_VAL_TRANSMISSION_START 0x00002000
+#define SBE_2T3E3_21143_VAL_OPERATING_MODE 0x00000c00
+#define SBE_2T3E3_21143_VAL_LOOPBACK_OFF 0x00000000
+#define SBE_2T3E3_21143_VAL_LOOPBACK_EXTERNAL 0x00000800
+#define SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL 0x00000400
+#define SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE 0x00000200
+#define SBE_2T3E3_21143_VAL_PASS_ALL_MULTICAST 0x00000080
+#define SBE_2T3E3_21143_VAL_PROMISCUOUS_MODE 0x00000040
+#define SBE_2T3E3_21143_VAL_PASS_BAD_FRAMES 0x00000008
+#define SBE_2T3E3_21143_VAL_RECEIVE_START 0x00000002
+
+/* CSR7 - INTERRUPT_ENABLE */
+#define SBE_2T3E3_21143_VAL_LINK_CHANGED_ENABLE 0x08000000
+#define SBE_2T3E3_21143_VAL_GENERAL_PURPOSE_PORT_ENABLE 0x04000000
+#define SBE_2T3E3_21143_VAL_NORMAL_INTERRUPT_SUMMARY_ENABLE 0x00010000
+#define SBE_2T3E3_21143_VAL_ABNORMAL_INTERRUPT_SUMMARY_ENABLE 0x00008000
+#define SBE_2T3E3_21143_VAL_EARLY_RECEIVE_INTERRUPT_ENABLE 0x00004000
+#define SBE_2T3E3_21143_VAL_FATAL_BUS_ERROR_ENABLE 0x00002000
+#define SBE_2T3E3_21143_VAL_LINK_FAIL_ENABLE 0x00001000
+#define SBE_2T3E3_21143_VAL_GENERAL_PURPOSE_TIMER_ENABLE 0x00000800
+#define SBE_2T3E3_21143_VAL_EARLY_TRANSMIT_INTERRUPT_ENABLE 0x00000400
+#define SBE_2T3E3_21143_VAL_RECEIVE_WATCHDOG_TIMEOUT_ENABLE 0x00000200
+#define SBE_2T3E3_21143_VAL_RECEIVE_STOPPED_ENABLE 0x00000100
+#define SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE_ENABLE 0x00000080
+#define SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT_ENABLE 0x00000040
+#define SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW_INTERRUPT_ENABLE 0x00000020
+#define SBE_2T3E3_21143_VAL_TRANSMIT_JABBER_TIMEOUT_ENABLE 0x00000008
+#define SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE_ENABLE 0x00000004
+#define SBE_2T3E3_21143_VAL_TRANSMIT_STOPPED_ENABLE 0x00000002
+#define SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT_ENABLE 0x00000001
+
+/* CSR8 - MISSED_FRAMES_AND_OVERFLOW_COUNTER */
+#define SBE_2T3E3_21143_VAL_OVERFLOW_COUNTER_OVERFLOW 0x10000000
+#define SBE_2T3E3_21143_VAL_OVERFLOW_COUNTER 0x0ffe0000
+#define SBE_2T3E3_21143_VAL_MISSED_FRAME_OVERFLOW 0x00010000
+#define SBE_2T3E3_21143_VAL_MISSED_FRAMES_COUNTER 0x0000ffff
+
+/* CSR9 - BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT */
+#define SBE_2T3E3_21143_VAL_MII_MANAGEMENT_DATA_IN 0x00080000
+#define SBE_2T3E3_21143_VAL_MII_MANAGEMENT_READ_MODE 0x00040000
+#define SBE_2T3E3_21143_VAL_MII_MANAGEMENT_DATA_OUT 0x00020000
+#define SBE_2T3E3_21143_VAL_MII_MANAGEMENT_CLOCK 0x00010000
+#define SBE_2T3E3_21143_VAL_READ_OPERATION 0x00004000
+#define SBE_2T3E3_21143_VAL_WRITE_OPERATION 0x00002000
+#define SBE_2T3E3_21143_VAL_BOOT_ROM_SELECT 0x00001000
+#define SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT 0x00000800
+#define SBE_2T3E3_21143_VAL_BOOT_ROM_DATA 0x000000ff
+#define SBE_2T3E3_21143_VAL_SERIAL_ROM_DATA_OUT 0x00000008
+#define SBE_2T3E3_21143_VAL_SERIAL_ROM_DATA_IN 0x00000004
+#define SBE_2T3E3_21143_VAL_SERIAL_ROM_CLOCK 0x00000002
+#define SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT 0x00000001
+
+/* CSR11 - GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL */
+#define SBE_2T3E3_21143_VAL_CYCLE_SIZE 0x80000000
+#define SBE_2T3E3_21143_VAL_TRANSMIT_TIMER 0x78000000
+#define SBE_2T3E3_21143_VAL_NUMBER_OF_TRANSMIT_PACKETS 0x07000000
+#define SBE_2T3E3_21143_VAL_RECEIVE_TIMER 0x00f00000
+#define SBE_2T3E3_21143_VAL_NUMBER_OF_RECEIVE_PACKETS 0x000e0000
+#define SBE_2T3E3_21143_VAL_CONTINUOUS_MODE 0x00010000
+#define SBE_2T3E3_21143_VAL_TIMER_VALUE 0x0000ffff
+
+/* CSR12 - SIA_STATUS */
+#define SBE_2T3E3_21143_VAL_10BASE_T_RECEIVE_PORT_ACTIVITY 0x00000200
+#define SBE_2T3E3_21143_VAL_AUI_RECEIVE_PORT_ACTIVITY 0x00000100
+#define SBE_2T3E3_21143_VAL_10Mbs_LINK_STATUS 0x00000004
+#define SBE_2T3E3_21143_VAL_100Mbs_LINK_STATUS 0x00000002
+#define SBE_2T3E3_21143_VAL_MII_RECEIVE_PORT_ACTIVITY 0x00000001
+
+/* CSR13 - SIA_CONNECTIVITY */
+#define SBE_2T3E3_21143_VAL_10BASE_T_OR_AUI 0x00000008
+#define SBE_2T3E3_21143_VAL_SIA_RESET 0x00000001
+
+/* CSR14 - SIA_TRANSMIT_AND_RECEIVE */
+#define SBE_2T3E3_21143_VAL_100BASE_TX_FULL_DUPLEX 0x00020000
+#define SBE_2T3E3_21143_VAL_COLLISION_DETECT_ENABLE 0x00000400
+#define SBE_2T3E3_21143_VAL_COLLISION_SQUELCH_ENABLE 0x00000200
+#define SBE_2T3E3_21143_VAL_RECEIVE_SQUELCH_ENABLE 0x00000100
+#define SBE_2T3E3_21143_VAL_LINK_PULSE_SEND_ENABLE 0x00000004
+#define SBE_2T3E3_21143_VAL_ENCODER_ENABLE 0x00000001
+
+/* CSR15 - SIA_AND_GENERAL_PURPOSE_PORT */
+#define SBE_2T3E3_21143_VAL_RECEIVE_WATCHDOG_DISABLE 0x00000010
+#define SBE_2T3E3_21143_VAL_AUI_BNC_MODE 0x00000008
+#define SBE_2T3E3_21143_VAL_HOST_UNJAB 0x00000002
+#define SBE_2T3E3_21143_VAL_JABBER_DISABLE 0x00000001
+
+/**************************************************************
+ * CPLD
+ **************************************************************/
+
+/* reg_map indexes */
+#define SBE_2T3E3_CPLD_REG_PCRA 0
+#define SBE_2T3E3_CPLD_REG_PCRB 1
+#define SBE_2T3E3_CPLD_REG_PLCR 2
+#define SBE_2T3E3_CPLD_REG_PLTR 3
+#define SBE_2T3E3_CPLD_REG_PPFR 4
+#define SBE_2T3E3_CPLD_REG_BOARD_ID 5
+#define SBE_2T3E3_CPLD_REG_FPGA_VERSION 6
+#define SBE_2T3E3_CPLD_REG_FRAMER_BASE_ADDRESS 7
+#define SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT 8
+#define SBE_2T3E3_CPLD_REG_STATIC_RESET 9
+#define SBE_2T3E3_CPLD_REG_PULSE_RESET 10
+#define SBE_2T3E3_CPLD_REG_FPGA_RECONFIGURATION 11
+#define SBE_2T3E3_CPLD_REG_LEDR 12
+#define SBE_2T3E3_CPLD_REG_PICSR 13
+#define SBE_2T3E3_CPLD_REG_PIER 14
+#define SBE_2T3E3_CPLD_REG_PCRC 15
+#define SBE_2T3E3_CPLD_REG_PBWF 16
+#define SBE_2T3E3_CPLD_REG_PBWL 17
+
+#define SBE_2T3E3_CPLD_REG_MAX 18
+
+/**********/
+
+/* val_map indexes */
+#define SBE_2T3E3_CPLD_VAL_LIU_SELECT 0
+#define SBE_2T3E3_CPLD_VAL_DAC_SELECT 1
+#define SBE_2T3E3_CPLD_VAL_LOOP_TIMING_SOURCE 2
+#define SBE_2T3E3_CPLD_VAL_LIU_FRAMER_RESET 3
+
+/* PCRA */
+#define SBE_2T3E3_CPLD_VAL_CRC32 0x40
+#define SBE_2T3E3_CPLD_VAL_TRANSPARENT_MODE 0x20
+#define SBE_2T3E3_CPLD_VAL_REAR_PANEL 0x10
+#define SBE_2T3E3_CPLD_VAL_RAW_MODE 0x08
+#define SBE_2T3E3_CPLD_VAL_ALT 0x04
+#define SBE_2T3E3_CPLD_VAL_LOOP_TIMING 0x02
+#define SBE_2T3E3_CPLD_VAL_LOCAL_CLOCK_E3 0x01
+
+/* PCRB */
+#define SBE_2T3E3_CPLD_VAL_PAD_COUNT 0x30
+#define SBE_2T3E3_CPLD_VAL_PAD_COUNT_1 0x00
+#define SBE_2T3E3_CPLD_VAL_PAD_COUNT_2 0x10
+#define SBE_2T3E3_CPLD_VAL_PAD_COUNT_3 0x20
+#define SBE_2T3E3_CPLD_VAL_PAD_COUNT_4 0x30
+#define SBE_2T3E3_CPLD_VAL_SCRAMBLER_TYPE 0x02
+#define SBE_2T3E3_CPLD_VAL_SCRAMBLER_ENABLE 0x01
+
+/* PCRC */
+#define SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_NONE 0x00
+#define SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_0 0x01
+#define SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_1 0x11
+#define SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_2 0x21
+
+/* PLTR */
+#define SBE_2T3E3_CPLD_VAL_LCV_COUNTER 0xff
+
+/* SCSR */
+#define SBE_2T3E3_CPLD_VAL_EEPROM_SELECT 0x10
+
+/* PICSR */
+#define SBE_2T3E3_CPLD_VAL_LOSS_OF_SIGNAL_THRESHOLD_LEVEL_1 0x80
+#define SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_CHANGE 0x40
+#define SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_ETHERNET_ASSERTED 0x20
+#define SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_FRAMER_ASSERTED 0x10
+#define SBE_2T3E3_CPLD_VAL_LCV_LIMIT_EXCEEDED 0x08
+#define SBE_2T3E3_CPLD_VAL_DMO_SIGNAL_DETECTED 0x04
+#define SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_DETECTED 0x02
+#define SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED 0x01
+
+/* PIER */
+#define SBE_2T3E3_CPLD_VAL_RECEIVE_LOS_CHANGE_ENABLE 0x40
+#define SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_ETHERNET_ENABLE 0x20
+#define SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_FRAMER_ENABLE 0x10
+#define SBE_2T3E3_CPLD_VAL_LCV_INTERRUPT_ENABLE 0x08
+#define SBE_2T3E3_CPLD_VAL_DMO_ENABLE 0x04
+#define SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_ENABLE 0x02
+#define SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_ENABLE 0x01
+
+/**************************************************************
+ * Framer
+ **************************************************************/
+
+/* reg_map indexes */
+/* common */
+#define SBE_2T3E3_FRAMER_REG_OPERATING_MODE 0
+#define SBE_2T3E3_FRAMER_REG_IO_CONTROL 1
+#define SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE 2
+#define SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS 3
+#define SBE_2T3E3_FRAMER_REG_PMON_LCV_EVENT_COUNT_MSB 28
+#define SBE_2T3E3_FRAMER_REG_PMON_LCV_EVENT_COUNT_LSB 29
+#define SBE_2T3E3_FRAMER_REG_PMON_FRAMING_BIT_ERROR_EVENT_COUNT_MSB 30
+#define SBE_2T3E3_FRAMER_REG_PMON_FRAMING_BIT_ERROR_EVENT_COUNT_LSB 31
+#define SBE_2T3E3_FRAMER_REG_PMON_PARITY_ERROR_EVENT_COUNT_MSB 32
+#define SBE_2T3E3_FRAMER_REG_PMON_PARITY_ERROR_EVENT_COUNT_LSB 33
+#define SBE_2T3E3_FRAMER_REG_PMON_FEBE_EVENT_COUNT_MSB 34
+#define SBE_2T3E3_FRAMER_REG_PMON_FEBE_EVENT_COUNT_LSB 35
+#define SBE_2T3E3_FRAMER_REG_PMON_CP_BIT_ERROR_EVENT_COUNT_MSB 36
+#define SBE_2T3E3_FRAMER_REG_PMON_CP_BIT_ERROR_EVENT_COUNT_LSB 37
+#define SBE_2T3E3_FRAMER_REG_PMON_HOLDING_REGISTER 38
+#define SBE_2T3E3_FRAMER_REG_ONE_SECOND_ERROR_STATUS 39
+#define SBE_2T3E3_FRAMER_REG_LCV_ONE_SECOND_ACCUMULATOR_MSB 40
+#define SBE_2T3E3_FRAMER_REG_LCV_ONE_SECOND_ACCUMULATOR_LSB 41
+#define SBE_2T3E3_FRAMER_REG_FRAME_PARITY_ERROR_ONE_SECOND_ACCUMULATOR_MSB 42
+#define SBE_2T3E3_FRAMER_REG_FRAME_PARITY_ERROR_ONE_SECOND_ACCUMULATOR_LSB 43
+#define SBE_2T3E3_FRAMER_REG_FRAME_CP_BIT_ERROR_ONE_SECOND_ACCUMULATOR_MSB 44
+#define SBE_2T3E3_FRAMER_REG_FRAME_CP_BIT_ERROR_ONE_SECOND_ACCUMULATOR_LSB 45
+#define SBE_2T3E3_FRAMER_REG_LINE_INTERFACE_DRIVE 46
+#define SBE_2T3E3_FRAMER_REG_LINE_INTERFACE_SCAN 47
+
+/* T3 */
+#define SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS 4
+#define SBE_2T3E3_FRAMER_REG_T3_RX_STATUS 5
+#define SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE 6
+#define SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS 7
+#define SBE_2T3E3_FRAMER_REG_T3_RX_SYNC_DETECT_ENABLE 8
+#define SBE_2T3E3_FRAMER_REG_T3_RX_FEAC 10
+#define SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS 11
+#define SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL 12
+#define SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_STATUS 13
+#define SBE_2T3E3_FRAMER_REG_T3_TX_CONFIGURATION 16
+#define SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS 17
+#define SBE_2T3E3_FRAMER_REG_T3_TX_FEAC 18
+#define SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_CONFIGURATION 19
+#define SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS 20
+#define SBE_2T3E3_FRAMER_REG_T3_TX_MBIT_MASK 21
+#define SBE_2T3E3_FRAMER_REG_T3_TX_FBIT_MASK 22
+#define SBE_2T3E3_FRAMER_REG_T3_TX_FBIT_MASK_2 23
+#define SBE_2T3E3_FRAMER_REG_T3_TX_FBIT_MASK_3 24
+
+/* E3 */
+#define SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_1 4
+#define SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2 5
+#define SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1 6
+#define SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2 7
+#define SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1 8
+#define SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2 9
+#define SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_CONTROL 12
+#define SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_STATUS 13
+#define SBE_2T3E3_FRAMER_REG_E3_RX_NR_BYTE 14
+#define SBE_2T3E3_FRAMER_REG_E3_RX_SERVICE_BITS 14
+#define SBE_2T3E3_FRAMER_REG_E3_RX_GC_BYTE 15
+#define SBE_2T3E3_FRAMER_REG_E3_TX_CONFIGURATION 16
+#define SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_CONFIGURATION 19
+#define SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS 19
+#define SBE_2T3E3_FRAMER_REG_E3_TX_GC_BYTE 21
+#define SBE_2T3E3_FRAMER_REG_E3_TX_SERVICE_BITS 21
+#define SBE_2T3E3_FRAMER_REG_E3_TX_MA_BYTE 22
+#define SBE_2T3E3_FRAMER_REG_E3_TX_NR_BYTE 23
+#define SBE_2T3E3_FRAMER_REG_E3_TX_FA1_ERROR_MASK 25
+#define SBE_2T3E3_FRAMER_REG_E3_TX_FAS_ERROR_MASK_UPPER 25
+#define SBE_2T3E3_FRAMER_REG_E3_TX_FA2_ERROR_MASK 26
+#define SBE_2T3E3_FRAMER_REG_E3_TX_FAS_ERROR_MASK_LOWER 26
+#define SBE_2T3E3_FRAMER_REG_E3_TX_BIP8_MASK 27
+#define SBE_2T3E3_FRAMER_REG_E3_TX_BIP4_MASK 27
+
+#define SBE_2T3E3_FRAMER_REG_MAX 48
+
+/**********/
+
+/* OPERATING_MODE */
+#define SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE 0x80
+#define SBE_2T3E3_FRAMER_VAL_T3_E3_SELECT 0x40
+#define SBE_2T3E3_FRAMER_VAL_INTERNAL_LOS_ENABLE 0x20
+#define SBE_2T3E3_FRAMER_VAL_RESET 0x10
+#define SBE_2T3E3_FRAMER_VAL_INTERRUPT_ENABLE_RESET 0x08
+#define SBE_2T3E3_FRAMER_VAL_FRAME_FORMAT_SELECT 0x04
+#define SBE_2T3E3_FRAMER_VAL_TIMING_ASYNCH_TXINCLK 0x03
+#define SBE_2T3E3_FRAMER_VAL_E3_G751 0x00
+#define SBE_2T3E3_FRAMER_VAL_E3_G832 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_CBIT 0x40
+#define SBE_2T3E3_FRAMER_VAL_T3_M13 0x44
+#define SBE_2T3E3_FRAMER_VAL_LOOPBACK_ON 0x80
+#define SBE_2T3E3_FRAMER_VAL_LOOPBACK_OFF 0x00
+
+/* IO_CONTROL */
+#define SBE_2T3E3_FRAMER_VAL_DISABLE_TX_LOSS_OF_CLOCK 0x80
+#define SBE_2T3E3_FRAMER_VAL_LOSS_OF_CLOCK_STATUS 0x40
+#define SBE_2T3E3_FRAMER_VAL_DISABLE_RX_LOSS_OF_CLOCK 0x20
+#define SBE_2T3E3_FRAMER_VAL_AMI_LINE_CODE 0x10
+#define SBE_2T3E3_FRAMER_VAL_UNIPOLAR 0x08
+#define SBE_2T3E3_FRAMER_VAL_TX_LINE_CLOCK_INVERT 0x04
+#define SBE_2T3E3_FRAMER_VAL_RX_LINE_CLOCK_INVERT 0x02
+#define SBE_2T3E3_FRAMER_VAL_REFRAME 0x01
+
+/* BLOCK_INTERRUPT_ENABLE */
+#define SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_ENABLE 0x80
+#define SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_ENABLE 0x02
+#define SBE_2T3E3_FRAMER_VAL_ONE_SECOND_INTERRUPT_ENABLE 0x01
+
+/* BLOCK_INTERRUPT_STATUS */
+#define SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_STATUS 0x80
+#define SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_STATUS 0x02
+#define SBE_2T3E3_FRAMER_VAL_ONE_SECOND_INTERRUPT_STATUS 0x01
+
+/**********/
+
+/* T3_RX_CONFIGURATION_STATUS */
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_AIS 0x80
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_LOS 0x40
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE 0x20
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_OOF 0x10
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FRAMING_ON_PARITY 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_F_SYNC_ALGO 0x02
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_M_SYNC_ALGO 0x01
+
+/* T3_RX_STATUS */
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FERF 0x10
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_AIC 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FEBE 0x07
+
+/* T3_RX_INTERRUPT_ENABLE */
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_CP_BIT_ERROR_INTERRUPT_ENABLE 0x80
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE 0x40
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_AIS_INTERRUPT_ENABLE 0x20
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE_INTERRUPT_ENABLE 0x10
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FERF_INTERRUPT_ENABLE 0x08
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_AIC_INTERRUPT_ENABLE 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE 0x02
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_P_BIT_INTERRUPT_ENABLE 0x01
+
+/* T3_RX_INTERRUPT_STATUS */
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_CP_BIT_ERROR_INTERRUPT_STATUS 0x80
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_STATUS 0x40
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_AIS_INTERRUPT_STATUS 0x20
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE_INTERRUPT_STATUS 0x10
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FERF_INTERRUPT_STATUS 0x08
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_AIC_INTERRUPT_STATUS 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_STATUS 0x02
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_P_BIT_INTERRUPT_STATUS 0x01
+
+/* T3_RX_FEAC_INTERRUPT_ENABLE_STATUS */
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID 0x10
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_ENABLE 0x08
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_STATUS 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_ENABLE 0x02
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_STATUS 0x01
+
+/* T3_RX_LAPD_CONTROL */
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_LAPD_ENABLE 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_LAPD_INTERRUPT_ENABLE 0x02
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_LAPD_INTERRUPT_STATUS 0x01
+
+/* T3_RX_LAPD_STATUS */
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_ABORT 0x40
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_LAPD_TYPE 0x30
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_CR_TYPE 0x08
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FCS_ERROR 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_END_OF_MESSAGE 0x02
+#define SBE_2T3E3_FRAMER_VAL_T3_RX_FLAG_PRESENT 0x01
+
+/* T3_TX_CONFIGURATION */
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_YELLOW_ALARM 0x80
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_X_BIT 0x40
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_IDLE 0x20
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_AIS 0x10
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_LOS 0x08
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_FERF_ON_LOS 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_FERF_ON_OOF 0x02
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_FERF_ON_AIS 0x01
+
+/* T3_TX_FEAC_CONFIGURATION_STATUS */
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_FEAC_INTERRUPT_ENABLE 0x10
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_FEAC_INTERRUPT_STATUS 0x08
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_FEAC_ENABLE 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_FEAC_GO 0x02
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_FEAC_BUSY 0x01
+
+/* T3_TX_LAPD_STATUS */
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_DL_START 0x08
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_DL_BUSY 0x04
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_LAPD_INTERRUPT_ENABLE 0x02
+#define SBE_2T3E3_FRAMER_VAL_T3_TX_LAPD_INTERRUPT_STATUS 0x01
+
+/**********/
+
+/* E3_RX_CONFIGURATION_STATUS_1 */
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_PAYLOAD_TYPE 0xe0
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_ALGO 0x10
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_T_MARK_ALGO 0x08
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_PAYLOAD_EXPECTED 0x07
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_BIP4 0x01
+
+/* E3_RX_CONFIGURATION_STATUS_2 */
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_ALGO 0x80
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LOF 0x40
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_OOF 0x20
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LOS 0x10
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_AIS 0x08
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_PAYLOAD_UNSTABLE 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_T_MARK 0x02
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_FERF 0x01
+
+/* E3_RX_INTERRUPT_ENABLE_1 */
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_COFA_INTERRUPT_ENABLE 0x10
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE 0x08
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_INTERRUPT_ENABLE 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE 0x02
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_AIS_INTERRUPT_ENABLE 0x01
+
+/* E3_RX_INTERRUPT_ENABLE_2 */
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_TTB_CHANGE_INTERRUPT_ENABLE 0x40
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_ENABLE 0x10
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_ENABLE 0x08
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_BIP8_ERROR_INTERRUPT_ENABLE 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_BIP4_ERROR_INTERRUPT_ENABLE 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_ENABLE 0x02
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_PAYLOAD_MISMATCH_INTERRUPT_ENABLE 0x01
+
+/* E3_RX_INTERRUPT_STATUS_1 */
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_COFA_INTERRUPT_STATUS 0x10
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_STATUS 0x08
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_INTERRUPT_STATUS 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_STATUS 0x02
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_AIS_INTERRUPT_STATUS 0x01
+
+/* E3_RX_INTERRUPT_STATUS_2 */
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_TTB_CHANGE_INTERRUPT_STATUS 0x40
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_STATUS 0x10
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_STATUS 0x08
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_BIP8_ERROR_INTERRUPT_STATUS 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_BIP4_ERROR_INTERRUPT_STATUS 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_STATUS 0x02
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_PAYLOAD_MISMATCH_INTERRUPT_STATUS 0x01
+
+/* E3_RX_LAPD_CONTROL */
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_DL_FROM_NR 0x08
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LAPD_ENABLE 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LAPD_INTERRUPT_ENABLE 0x02
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LAPD_INTERRUPT_STATUS 0x01
+
+/* E3_RX_LAPD_STATUS */
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_ABORT 0x40
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_LAPD_TYPE 0x30
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_CR_TYPE 0x08
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_FCS_ERROR 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_END_OF_MESSAGE 0x02
+#define SBE_2T3E3_FRAMER_VAL_E3_RX_FLAG_PRESENT 0x01
+
+/* E3_TX_CONFIGURATION */
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_BIP4_ENABLE 0x80
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_A_SOURCE_SELECT 0x60
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_DL_IN_NR 0x10
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_N_SOURCE_SELECT 0x18
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_AIS_ENABLE 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_LOS_ENABLE 0x02
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_MA_RX 0x01
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_FAS_SOURCE_SELECT 0x01
+
+/* E3_TX_LAPD_CONFIGURATION */
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_AUTO_RETRANSMIT 0x08
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_LAPD_MESSAGE_LENGTH 0x02
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_LAPD_ENABLE 0x01
+
+/* E3_TX_LAPD_STATUS_INTERRUPT */
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_DL_START 0x08
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_DL_BUSY 0x04
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_LAPD_INTERRUPT_ENABLE 0x02
+#define SBE_2T3E3_FRAMER_VAL_E3_TX_LAPD_INTERRUPT_STATUS 0x01
+
+
+
+
+
+
+/**************************************************************
+ * LIU
+ **************************************************************/
+
+/* reg_map indexes */
+#define SBE_2T3E3_LIU_REG_REG0 0
+#define SBE_2T3E3_LIU_REG_REG1 1
+#define SBE_2T3E3_LIU_REG_REG2 2
+#define SBE_2T3E3_LIU_REG_REG3 3
+#define SBE_2T3E3_LIU_REG_REG4 4
+
+#define SBE_2T3E3_LIU_REG_MAX 5
+
+/**********/
+
+/* REG0 */
+#define SBE_2T3E3_LIU_VAL_RECEIVE_LOSS_OF_LOCK_STATUS 0x10
+#define SBE_2T3E3_LIU_VAL_RECEIVE_LOSS_OF_SIGNAL_STATUS 0x08
+#define SBE_2T3E3_LIU_VAL_ANALOG_LOSS_OF_SIGNAL_STATUS 0x04
+#define SBE_2T3E3_LIU_VAL_DIGITAL_LOSS_OF_SIGNAL_STATUS 0x02
+#define SBE_2T3E3_LIU_VAL_DMO_STATUS 0x01
+
+/* REG1 */
+#define SBE_2T3E3_LIU_VAL_TRANSMITTER_OFF 0x10
+#define SBE_2T3E3_LIU_VAL_TRANSMIT_ALL_ONES 0x08
+#define SBE_2T3E3_LIU_VAL_TRANSMIT_CLOCK_INVERT 0x04
+#define SBE_2T3E3_LIU_VAL_TRANSMIT_LEVEL_SELECT 0x02
+#define SBE_2T3E3_LIU_VAL_TRANSMIT_BINARY_DATA 0x01
+
+/* REG2 */
+#define SBE_2T3E3_LIU_VAL_DECODER_DISABLE 0x10
+#define SBE_2T3E3_LIU_VAL_ENCODER_DISABLE 0x08
+#define SBE_2T3E3_LIU_VAL_ANALOG_LOSS_OF_SIGNAL_DISABLE 0x04
+#define SBE_2T3E3_LIU_VAL_DIGITAL_LOSS_OF_SIGNAL_DISABLE 0x02
+#define SBE_2T3E3_LIU_VAL_RECEIVE_EQUALIZATION_DISABLE 0x01
+
+/* REG3 */
+#define SBE_2T3E3_LIU_VAL_RECEIVE_BINARY_DATA 0x10
+#define SBE_2T3E3_LIU_VAL_RECOVERED_DATA_MUTING 0x08
+#define SBE_2T3E3_LIU_VAL_RECEIVE_CLOCK_OUTPUT_2 0x04
+#define SBE_2T3E3_LIU_VAL_INVERT_RECEIVE_CLOCK_2 0x02
+#define SBE_2T3E3_LIU_VAL_INVERT_RECEIVE_CLOCK_1 0x01
+
+/* REG4 */
+#define SBE_2T3E3_LIU_VAL_T3_MODE_SELECT 0x00
+#define SBE_2T3E3_LIU_VAL_E3_MODE_SELECT 0x04
+#define SBE_2T3E3_LIU_VAL_LOCAL_LOOPBACK 0x02
+#define SBE_2T3E3_LIU_VAL_REMOTE_LOOPBACK 0x01
+#define SBE_2T3E3_LIU_VAL_LOOPBACK_OFF 0x00
+#define SBE_2T3E3_LIU_VAL_LOOPBACK_REMOTE 0x01
+#define SBE_2T3E3_LIU_VAL_LOOPBACK_ANALOG 0x02
+#define SBE_2T3E3_LIU_VAL_LOOPBACK_DIGITAL 0x03
+
+/**********************************************************************
+ *
+ * descriptor list and data buffer
+ *
+ **********************************************************************/
+typedef struct {
+ u32 rdes0;
+ u32 rdes1;
+ u32 rdes2;
+ u32 rdes3;
+} t3e3_rx_desc_t;
+
+#define SBE_2T3E3_RX_DESC_RING_SIZE 64
+
+/* RDES0 */
+#define SBE_2T3E3_RX_DESC_21143_OWN 0X80000000
+#define SBE_2T3E3_RX_DESC_FRAME_LENGTH 0x3fff0000
+#define SBE_2T3E3_RX_DESC_FRAME_LENGTH_SHIFT 16
+#define SBE_2T3E3_RX_DESC_ERROR_SUMMARY 0x00008000
+#define SBE_2T3E3_RX_DESC_DESC_ERROR 0x00004000
+#define SBE_2T3E3_RX_DESC_DATA_TYPE 0x00003000
+#define SBE_2T3E3_RX_DESC_RUNT_FRAME 0x00000800
+#define SBE_2T3E3_RX_DESC_FIRST_DESC 0x00000200
+#define SBE_2T3E3_RX_DESC_LAST_DESC 0x00000100
+#define SBE_2T3E3_RX_DESC_FRAME_TOO_LONG 0x00000080
+#define SBE_2T3E3_RX_DESC_COLLISION_SEEN 0x00000040
+#define SBE_2T3E3_RX_DESC_FRAME_TYPE 0x00000020
+#define SBE_2T3E3_RX_DESC_RECEIVE_WATCHDOG 0x00000010
+#define SBE_2T3E3_RX_DESC_MII_ERROR 0x00000008
+#define SBE_2T3E3_RX_DESC_DRIBBLING_BIT 0x00000004
+#define SBE_2T3E3_RX_DESC_CRC_ERROR 0x00000002
+
+/* RDES1 */
+#define SBE_2T3E3_RX_DESC_END_OF_RING 0x02000000
+#define SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED 0x01000000
+#define SBE_2T3E3_RX_DESC_BUFFER_2_SIZE 0x003ff800
+#define SBE_2T3E3_RX_DESC_BUFFER_1_SIZE 0x000007ff
+
+/*********************/
+
+typedef struct {
+ u32 tdes0;
+ u32 tdes1;
+ u32 tdes2;
+ u32 tdes3;
+} t3e3_tx_desc_t;
+
+#define SBE_2T3E3_TX_DESC_RING_SIZE 256
+
+/* TDES0 */
+#define SBE_2T3E3_TX_DESC_21143_OWN 0x80000000
+#define SBE_2T3E3_TX_DESC_ERROR_SUMMARY 0x00008000
+#define SBE_2T3E3_TX_DESC_TRANSMIT_JABBER_TIMEOUT 0x00004000
+#define SBE_2T3E3_TX_DESC_LOSS_OF_CARRIER 0x00000800
+#define SBE_2T3E3_TX_DESC_NO_CARRIER 0x00000400
+#define SBE_2T3E3_TX_DESC_LINK_FAIL_REPORT 0x00000004
+#define SBE_2T3E3_TX_DESC_UNDERFLOW_ERROR 0x00000002
+#define SBE_2T3E3_TX_DESC_DEFFERED 0x00000001
+
+/* TDES1 */
+#define SBE_2T3E3_TX_DESC_INTERRUPT_ON_COMPLETION 0x80000000
+#define SBE_2T3E3_TX_DESC_LAST_SEGMENT 0x40000000
+#define SBE_2T3E3_TX_DESC_FIRST_SEGMENT 0x20000000
+#define SBE_2T3E3_TX_DESC_CRC_DISABLE 0x04000000
+#define SBE_2T3E3_TX_DESC_END_OF_RING 0x02000000
+#define SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED 0x01000000
+#define SBE_2T3E3_TX_DESC_DISABLE_PADDING 0x00800000
+#define SBE_2T3E3_TX_DESC_BUFFER_2_SIZE 0x003ff800
+#define SBE_2T3E3_TX_DESC_BUFFER_1_SIZE 0x000007ff
+
+
+#define SBE_2T3E3_MTU 1600
+#define SBE_2T3E3_CRC16_LENGTH 2
+#define SBE_2T3E3_CRC32_LENGTH 4
+
+#define MCLBYTES (SBE_2T3E3_MTU + 128)
+
+struct channel {
+ struct pci_dev *pdev;
+ struct net_device *dev;
+ struct card *card;
+ unsigned long addr; /* DECchip */
+
+ int leds;
+
+ /* pci specific */
+ struct {
+ u32 slot; /* should be 0 or 1 */
+ u32 command;
+ u8 cache_size;
+ } h;
+
+ /* statistics */
+ t3e3_stats_t s;
+
+ /* running */
+ struct {
+ u32 flags;
+ } r;
+
+ /* parameters */
+ t3e3_param_t p;
+
+ u32 liu_regs[SBE_2T3E3_LIU_REG_MAX]; /* LIU registers */
+ u32 framer_regs[SBE_2T3E3_FRAMER_REG_MAX]; /* Framer registers */
+
+ /* Ethernet Controller */
+ struct {
+ u_int16_t card_serial_number[3];
+
+ u32 reg[SBE_2T3E3_21143_REG_MAX]; /* registers i.e. CSR */
+
+ u32 interrupt_enable_mask;
+
+ /* receive chain/ring */
+ t3e3_rx_desc_t *rx_ring;
+ struct sk_buff *rx_data[SBE_2T3E3_RX_DESC_RING_SIZE];
+ u32 rx_ring_current_read;
+
+ /* transmit chain/ring */
+ t3e3_tx_desc_t *tx_ring;
+ struct sk_buff *tx_data[SBE_2T3E3_TX_DESC_RING_SIZE];
+ u32 tx_ring_current_read;
+ u32 tx_ring_current_write;
+ int tx_full;
+ int tx_free_cnt;
+ spinlock_t tx_lock;
+ } ether;
+
+ int32_t interrupt_active;
+ int32_t rcv_count;
+};
+
+struct card {
+ spinlock_t bootrom_lock;
+ unsigned long bootrom_addr;
+ struct timer_list timer; /* for updating LEDs */
+ struct channel channels[0];
+};
+
+#define SBE_2T3E3_FLAG_NETWORK_UP 0x00000001
+#define SBE_2T3E3_FLAG_NO_ERROR_MESSAGES 0x00000002
+
+extern const u32 cpld_reg_map[][2];
+extern const u32 cpld_val_map[][2];
+extern const u32 t3e3_framer_reg_map[];
+extern const u32 t3e3_liu_reg_map[];
+
+void t3e3_init(struct channel *);
+void t3e3_if_up(struct channel *);
+void t3e3_if_down(struct channel *);
+int t3e3_if_start_xmit(struct sk_buff *skb, struct net_device *dev);
+void t3e3_if_config(struct channel *, u32, char *,
+ t3e3_resp_t *, int *);
+void t3e3_set_frame_type(struct channel *, u32);
+u32 t3e3_eeprom_read_word(struct channel *, u32);
+void t3e3_read_card_serial_number(struct channel *);
+
+/* interrupt handlers */
+irqreturn_t t3e3_intr(int irq, void *dev_instance);
+void dc_intr(struct channel *);
+void dc_intr_rx(struct channel *);
+void dc_intr_tx(struct channel *);
+void dc_intr_tx_underflow(struct channel *);
+void exar7250_intr(struct channel *);
+void exar7250_E3_intr(struct channel *, u32);
+void exar7250_T3_intr(struct channel *, u32);
+
+/* Ethernet controller */
+u32 bootrom_read(struct channel *, u32);
+void bootrom_write(struct channel *, u32, u32);
+void dc_init(struct channel *);
+void dc_start(struct channel *);
+void dc_stop(struct channel *);
+void dc_start_intr(struct channel *);
+void dc_stop_intr(struct channel *);
+void dc_reset(struct channel *);
+void dc_restart(struct channel *);
+void dc_receiver_onoff(struct channel *, u32);
+void dc_transmitter_onoff(struct channel *, u32);
+void dc_set_loopback(struct channel *, u32);
+u32 dc_init_descriptor_list(struct channel *);
+void dc_clear_descriptor_list(struct channel *);
+void dc_drop_descriptor_list(struct channel *);
+void dc_set_output_port(struct channel *);
+void t3e3_sc_init(struct channel *);
+
+/* CPLD */
+void cpld_init(struct channel *sc);
+u32 cpld_read(struct channel *sc, u32 reg);
+void cpld_set_crc(struct channel *, u32);
+void cpld_start_intr(struct channel *);
+void cpld_stop_intr(struct channel *);
+#if 0
+void cpld_led_onoff(struct channel *, u32, u32, u32, u32);
+#endif
+void cpld_set_clock(struct channel *sc, u32 mode);
+void cpld_set_scrambler(struct channel *, u32);
+void cpld_select_panel(struct channel *, u32);
+void cpld_set_frame_mode(struct channel *, u32);
+void cpld_set_frame_type(struct channel *, u32);
+void cpld_set_pad_count(struct channel *, u32);
+void cpld_set_fractional_mode(struct channel *, u32, u32, u32);
+void cpld_LOS_update(struct channel *);
+
+/* Framer */
+extern u32 exar7250_read(struct channel *, u32);
+extern void exar7250_write(struct channel *, u32, u32);
+void exar7250_init(struct channel *);
+void exar7250_start_intr(struct channel *, u32);
+void exar7250_stop_intr(struct channel *, u32);
+void exar7250_set_frame_type(struct channel *, u32);
+void exar7250_set_loopback(struct channel *, u32);
+void exar7250_unipolar_onoff(struct channel *, u32);
+
+/* LIU */
+u32 exar7300_read(struct channel *, u32);
+void exar7300_write(struct channel *, u32, u32);
+void exar7300_init(struct channel *);
+void exar7300_line_build_out_onoff(struct channel *, u32);
+void exar7300_set_frame_type(struct channel *, u32);
+void exar7300_set_loopback(struct channel *, u32);
+void exar7300_transmit_all_ones_onoff(struct channel *, u32);
+void exar7300_receive_equalization_onoff(struct channel *, u32);
+void exar7300_unipolar_onoff(struct channel *, u32);
+
+void update_led(struct channel *, int);
+int setup_device(struct net_device *dev, struct channel *sc);
+
+static inline int has_two_ports(struct pci_dev *pdev)
+{
+ return pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P0;
+}
+
+#define dev_to_priv(dev) (*(struct channel **) ((hdlc_device*)(dev) + 1))
+
+static inline u32 dc_read(unsigned long addr, u32 reg)
+{
+ return inl(addr + (reg << 3));
+}
+
+static inline void dc_write(unsigned long addr, u32 reg, u32 val)
+{
+ outl(val, addr + (reg << 3));
+}
+
+static inline void dc_set_bits(unsigned long addr, u32 reg, u32 bits)
+{
+ dc_write(addr, reg, dc_read(addr, reg) | bits);
+}
+
+static inline void dc_clear_bits(unsigned long addr, u32 reg, u32 bits)
+{
+ dc_write(addr, reg, dc_read(addr, reg) & ~bits);
+}
+
+#define CPLD_MAP_REG(reg, sc) (cpld_reg_map[(reg)][(sc)->h.slot])
+
+static inline void cpld_write(struct channel *channel, unsigned reg, u32 val)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&channel->card->bootrom_lock, flags);
+ bootrom_write(channel, CPLD_MAP_REG(reg, channel), val);
+ spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
+}
+
+#define exar7250_set_bit(sc, reg, bit) \
+ exar7250_write((sc), (reg), \
+ exar7250_read(sc, reg) | (bit))
+
+#define exar7250_clear_bit(sc, reg, bit) \
+ exar7250_write((sc), (reg), \
+ exar7250_read(sc, reg) & ~(bit))
+
+#define exar7300_set_bit(sc, reg, bit) \
+ exar7300_write((sc), (reg), \
+ exar7300_read(sc, reg) | (bit))
+
+#define exar7300_clear_bit(sc, reg, bit) \
+ exar7300_write((sc), (reg), \
+ exar7300_read(sc, reg) & ~(bit))
+
+
+#endif /* T3E3_H */
diff --git a/drivers/staging/sbe-2t3e3/Kconfig b/drivers/staging/sbe-2t3e3/Kconfig
new file mode 100644
index 0000000..8ec86cf
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/Kconfig
@@ -0,0 +1,13 @@
+config SBE_2T3E3
+ tristate "SBE wanPMC-2T3E3 support"
+ depends on HDLC && PCI
+ help
+ Driver for wanPMC-2T3E3 cards by SBE Inc.
+
+ If you have such a card, say Y here and see
+ <http://www.kernel.org/pub/linux/utils/net/hdlc/>.
+
+ To compile this as a module, choose M here: the
+ module will be called sbe-2t3e3.
+
+ If unsure, say N.
diff --git a/drivers/staging/sbe-2t3e3/Makefile b/drivers/staging/sbe-2t3e3/Makefile
new file mode 100644
index 0000000..2c7b097
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_SBE_2T3E3) += sbe-2t3e3.o
+
+sbe-2t3e3-objs := module.o netdev.o maps.o \
+ main.o cpld.o intr.o ctrl.o io.o dc.o exar7250.o exar7300.o
diff --git a/drivers/staging/sbe-2t3e3/TODO b/drivers/staging/sbe-2t3e3/TODO
new file mode 100644
index 0000000..624b20f
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/TODO
@@ -0,0 +1,6 @@
+TODO:
+ - additional cleaning and tests
+ - wait for the new configuration interface in generic HDLC layer and
+ when available, convert the driver to it
+
+Please send patches to Krzysztof Halasa <khc@pm.waw.pl>.
\ No newline at end of file
diff --git a/drivers/staging/sbe-2t3e3/cpld.c b/drivers/staging/sbe-2t3e3/cpld.c
new file mode 100644
index 0000000..b0fc2dd
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/cpld.c
@@ -0,0 +1,366 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include <linux/delay.h>
+#include "2t3e3.h"
+#include "ctrl.h"
+
+#define bootrom_set_bit(sc, reg, bit) \
+ bootrom_write((sc), (reg), \
+ bootrom_read((sc), (reg)) | (bit))
+
+#define bootrom_clear_bit(sc, reg, bit) \
+ bootrom_write((sc), (reg), \
+ bootrom_read((sc), (reg)) & ~(bit))
+
+static inline void cpld_set_bit(struct channel *channel, unsigned reg, u32 bit)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&channel->card->bootrom_lock, flags);
+ bootrom_set_bit(channel, CPLD_MAP_REG(reg, channel), bit);
+ spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
+}
+
+static inline void cpld_clear_bit(struct channel *channel, unsigned reg, u32 bit)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&channel->card->bootrom_lock, flags);
+ bootrom_clear_bit(channel, CPLD_MAP_REG(reg, channel), bit);
+ spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
+}
+
+void cpld_init(struct channel *sc)
+{
+ u32 val;
+#if 0
+ /* reset LIU and Framer */
+ val = cpld_val_map[SBE_2T3E3_CPLD_VAL_LIU_FRAMER_RESET][sc->h.slot];
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_STATIC_RESET, val);
+ udelay(10000); /* TODO - how long? */
+ val = 0;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_STATIC_RESET, val);
+#endif
+
+ /* PCRA */
+ val = SBE_2T3E3_CPLD_VAL_CRC32 |
+ cpld_val_map[SBE_2T3E3_CPLD_VAL_LOOP_TIMING_SOURCE][sc->h.slot];
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRA, val);
+
+ /* PCRB */
+ val = 0;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRB, val);
+
+ /* PCRC */
+ val = 0;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC, val);
+
+ /* PBWF */
+ val = 0;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWF, val);
+
+ /* PBWL */
+ val = 0;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWL, val);
+
+ /* PLTR */
+ val = SBE_2T3E3_CPLD_VAL_LCV_COUNTER;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PLTR, val);
+ udelay(1000);
+
+ /* PLCR */
+ val = 0;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PLCR, val);
+ udelay(1000);
+
+ /* PPFR */
+ val = 0x55;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PPFR, val);
+ /* TODO: this doesn't work!!! */
+
+ /* SERIAL_CHIP_SELECT */
+ val = 0;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, val);
+
+ /* PICSR */
+ val = SBE_2T3E3_CPLD_VAL_DMO_SIGNAL_DETECTED |
+ SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_DETECTED |
+ SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PICSR, val);
+
+ cpld_start_intr(sc);
+
+ udelay(1000);
+}
+
+void cpld_start_intr(struct channel *sc)
+{
+ u32 val;
+
+ /* PIER */
+ val = SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_ETHERNET_ENABLE |
+ SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_FRAMER_ENABLE;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PIER, val);
+#if 0
+ /*
+ do you want to hang up your computer?
+ ENABLE REST OF INTERRUPTS !!!
+ you have been warned :).
+ */
+#endif
+}
+
+void cpld_stop_intr(struct channel *sc)
+{
+ u32 val;
+
+ /* PIER */
+ val = 0;
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PIER, val);
+}
+
+void cpld_set_frame_mode(struct channel *sc, u32 mode)
+{
+ if (sc->p.frame_mode == mode)
+ return;
+
+ switch (mode) {
+ case SBE_2T3E3_FRAME_MODE_HDLC:
+ cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_TRANSPARENT_MODE |
+ SBE_2T3E3_CPLD_VAL_RAW_MODE);
+ exar7250_unipolar_onoff(sc, SBE_2T3E3_OFF);
+ exar7300_unipolar_onoff(sc, SBE_2T3E3_OFF);
+ break;
+ case SBE_2T3E3_FRAME_MODE_TRANSPARENT:
+ cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_RAW_MODE);
+ cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_TRANSPARENT_MODE);
+ exar7250_unipolar_onoff(sc, SBE_2T3E3_OFF);
+ exar7300_unipolar_onoff(sc, SBE_2T3E3_OFF);
+ break;
+ case SBE_2T3E3_FRAME_MODE_RAW:
+ cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_RAW_MODE);
+ exar7250_unipolar_onoff(sc, SBE_2T3E3_ON);
+ exar7300_unipolar_onoff(sc, SBE_2T3E3_ON);
+ break;
+ default:
+ return;
+ }
+
+ sc->p.frame_mode = mode;
+}
+
+/* set rate of the local clock */
+void cpld_set_frame_type(struct channel *sc, u32 type)
+{
+ switch (type) {
+ case SBE_2T3E3_FRAME_TYPE_E3_G751:
+ case SBE_2T3E3_FRAME_TYPE_E3_G832:
+ cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_LOCAL_CLOCK_E3);
+ break;
+ case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
+ case SBE_2T3E3_FRAME_TYPE_T3_M13:
+ cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_LOCAL_CLOCK_E3);
+ break;
+ default:
+ return;
+ }
+}
+
+void cpld_set_scrambler(struct channel *sc, u32 mode)
+{
+ if (sc->p.scrambler == mode)
+ return;
+
+ switch (mode) {
+ case SBE_2T3E3_SCRAMBLER_OFF:
+ cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
+ SBE_2T3E3_CPLD_VAL_SCRAMBLER_ENABLE);
+ break;
+ case SBE_2T3E3_SCRAMBLER_LARSCOM:
+ cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
+ SBE_2T3E3_CPLD_VAL_SCRAMBLER_TYPE);
+ cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
+ SBE_2T3E3_CPLD_VAL_SCRAMBLER_ENABLE);
+ break;
+ case SBE_2T3E3_SCRAMBLER_ADC_KENTROX_DIGITAL:
+ cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
+ SBE_2T3E3_CPLD_VAL_SCRAMBLER_TYPE);
+ cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
+ SBE_2T3E3_CPLD_VAL_SCRAMBLER_ENABLE);
+ break;
+ default:
+ return;
+ }
+
+ sc->p.scrambler = mode;
+}
+
+
+void cpld_set_crc(struct channel *sc, u32 crc)
+{
+ if (sc->p.crc == crc)
+ return;
+
+ switch (crc) {
+ case SBE_2T3E3_CRC_16:
+ cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_CRC32);
+ break;
+ case SBE_2T3E3_CRC_32:
+ cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_CRC32);
+ break;
+ default:
+ return;
+ }
+
+ sc->p.crc = crc;
+}
+
+
+void cpld_select_panel(struct channel *sc, u32 panel)
+{
+ if (sc->p.panel == panel)
+ return;
+ switch (panel) {
+ case SBE_2T3E3_PANEL_FRONT:
+ cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_REAR_PANEL);
+ break;
+ case SBE_2T3E3_PANEL_REAR:
+ cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_REAR_PANEL);
+ break;
+ default:
+ return;
+ }
+
+ udelay(100);
+
+ sc->p.panel = panel;
+}
+
+
+extern void cpld_set_clock(struct channel *sc, u32 mode)
+{
+ if (sc->p.clock_source == mode)
+ return;
+
+ switch (mode) {
+ case SBE_2T3E3_TIMING_LOCAL:
+ cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_ALT);
+ break;
+ case SBE_2T3E3_TIMING_LOOP:
+ cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
+ SBE_2T3E3_CPLD_VAL_ALT);
+ break;
+ default:
+ return;
+ }
+
+ sc->p.clock_source = mode;
+}
+
+void cpld_set_pad_count(struct channel *sc, u32 count)
+{
+ u32 val;
+
+ if (sc->p.pad_count == count)
+ return;
+
+ switch (count) {
+ case SBE_2T3E3_PAD_COUNT_1:
+ val = SBE_2T3E3_CPLD_VAL_PAD_COUNT_1;
+ break;
+ case SBE_2T3E3_PAD_COUNT_2:
+ val = SBE_2T3E3_CPLD_VAL_PAD_COUNT_2;
+ break;
+ case SBE_2T3E3_PAD_COUNT_3:
+ val = SBE_2T3E3_CPLD_VAL_PAD_COUNT_3;
+ break;
+ case SBE_2T3E3_PAD_COUNT_4:
+ val = SBE_2T3E3_CPLD_VAL_PAD_COUNT_4;
+ break;
+ default:
+ return;
+ }
+
+ cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
+ SBE_2T3E3_CPLD_VAL_PAD_COUNT);
+ cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRB, val);
+ sc->p.pad_count = count;
+}
+
+void cpld_LOS_update(struct channel *sc)
+{
+ u_int8_t los;
+
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PICSR,
+ SBE_2T3E3_CPLD_VAL_DMO_SIGNAL_DETECTED |
+ SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_DETECTED |
+ SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED);
+ los = cpld_read(sc, SBE_2T3E3_CPLD_REG_PICSR) &
+ SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED;
+
+ if (los != sc->s.LOS)
+ dev_info(&sc->pdev->dev, "SBE 2T3E3: LOS status: %s\n",
+ los ? "Loss of signal" : "Signal OK");
+ sc->s.LOS = los;
+}
+
+void cpld_set_fractional_mode(struct channel *sc, u32 mode,
+ u32 start, u32 stop)
+{
+ if (mode == SBE_2T3E3_FRACTIONAL_MODE_NONE) {
+ start = 0;
+ stop = 0;
+ }
+
+ if (sc->p.fractional_mode == mode && sc->p.bandwidth_start == start &&
+ sc->p.bandwidth_stop == stop)
+ return;
+
+ switch (mode) {
+ case SBE_2T3E3_FRACTIONAL_MODE_NONE:
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
+ SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_NONE);
+ break;
+ case SBE_2T3E3_FRACTIONAL_MODE_0:
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
+ SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_0);
+ break;
+ case SBE_2T3E3_FRACTIONAL_MODE_1:
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
+ SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_1);
+ break;
+ case SBE_2T3E3_FRACTIONAL_MODE_2:
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
+ SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_2);
+ break;
+ default:
+ printk(KERN_ERR "wrong mode in set_fractional_mode\n");
+ return;
+ }
+
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWF, start);
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWL, stop);
+
+ sc->p.fractional_mode = mode;
+ sc->p.bandwidth_start = start;
+ sc->p.bandwidth_stop = stop;
+}
diff --git a/drivers/staging/sbe-2t3e3/ctrl.c b/drivers/staging/sbe-2t3e3/ctrl.c
new file mode 100644
index 0000000..d9dd216
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/ctrl.c
@@ -0,0 +1,362 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include <linux/types.h>
+#include "2t3e3.h"
+#include "ctrl.h"
+
+void t3e3_set_frame_type(struct channel *sc, u32 mode)
+{
+ if (sc->p.frame_type == mode)
+ return;
+
+ if (sc->r.flags & SBE_2T3E3_FLAG_NETWORK_UP) {
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: changing frame type during active connection\n");
+ return;
+ }
+
+ exar7300_set_frame_type(sc, mode);
+ exar7250_set_frame_type(sc, mode);
+ cpld_set_frame_type(sc, mode);
+
+ sc->p.frame_type = mode;
+}
+
+void t3e3_set_loopback(struct channel *sc, u32 mode)
+{
+ u32 tx, rx;
+
+ if (sc->p.loopback == mode)
+ return;
+
+ tx = sc->p.transmitter_on;
+ rx = sc->p.receiver_on;
+ if (tx == SBE_2T3E3_ON)
+ dc_transmitter_onoff(sc, SBE_2T3E3_OFF);
+ if (rx == SBE_2T3E3_ON)
+ dc_receiver_onoff(sc, SBE_2T3E3_OFF);
+
+ /* stop current loopback if any exists */
+ switch (sc->p.loopback) {
+ case SBE_2T3E3_LOOPBACK_NONE:
+ break;
+ case SBE_2T3E3_LOOPBACK_ETHERNET:
+ dc_set_loopback(sc, SBE_2T3E3_21143_VAL_LOOPBACK_OFF);
+ break;
+ case SBE_2T3E3_LOOPBACK_FRAMER:
+ exar7250_set_loopback(sc, SBE_2T3E3_FRAMER_VAL_LOOPBACK_OFF);
+ break;
+ case SBE_2T3E3_LOOPBACK_LIU_DIGITAL:
+ case SBE_2T3E3_LOOPBACK_LIU_ANALOG:
+ case SBE_2T3E3_LOOPBACK_LIU_REMOTE:
+ exar7300_set_loopback(sc, SBE_2T3E3_LIU_VAL_LOOPBACK_OFF);
+ break;
+ default:
+ return;
+ }
+
+ switch (mode) {
+ case SBE_2T3E3_LOOPBACK_NONE:
+ break;
+ case SBE_2T3E3_LOOPBACK_ETHERNET:
+ dc_set_loopback(sc, SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL);
+ break;
+ case SBE_2T3E3_LOOPBACK_FRAMER:
+ exar7250_set_loopback(sc, SBE_2T3E3_FRAMER_VAL_LOOPBACK_ON);
+ break;
+ case SBE_2T3E3_LOOPBACK_LIU_DIGITAL:
+ exar7300_set_loopback(sc, SBE_2T3E3_LIU_VAL_LOOPBACK_DIGITAL);
+ break;
+ case SBE_2T3E3_LOOPBACK_LIU_ANALOG:
+ exar7300_set_loopback(sc, SBE_2T3E3_LIU_VAL_LOOPBACK_ANALOG);
+ break;
+ case SBE_2T3E3_LOOPBACK_LIU_REMOTE:
+ exar7300_set_loopback(sc, SBE_2T3E3_LIU_VAL_LOOPBACK_REMOTE);
+ break;
+ default:
+ return;
+ }
+
+ sc->p.loopback = mode;
+
+ if (tx == SBE_2T3E3_ON)
+ dc_transmitter_onoff(sc, SBE_2T3E3_ON);
+ if (rx == SBE_2T3E3_ON)
+ dc_receiver_onoff(sc, SBE_2T3E3_ON);
+}
+
+
+void t3e3_reg_read(struct channel *sc, u32 *reg, u32 *val)
+{
+ u32 i;
+
+ *val = 0;
+
+ switch (reg[0]) {
+ case SBE_2T3E3_CHIP_21143:
+ if (!(reg[1] & 7))
+ *val = dc_read(sc->addr, reg[1] / 8);
+ break;
+ case SBE_2T3E3_CHIP_CPLD:
+ for (i = 0; i < SBE_2T3E3_CPLD_REG_MAX; i++)
+ if (cpld_reg_map[i][sc->h.slot] == reg[1]) {
+ *val = cpld_read(sc, i);
+ break;
+ }
+ break;
+ case SBE_2T3E3_CHIP_FRAMER:
+ for (i = 0; i < SBE_2T3E3_FRAMER_REG_MAX; i++)
+ if (t3e3_framer_reg_map[i] == reg[1]) {
+ *val = exar7250_read(sc, i);
+ break;
+ }
+ break;
+ case SBE_2T3E3_CHIP_LIU:
+ for (i = 0; i < SBE_2T3E3_LIU_REG_MAX; i++)
+ if (t3e3_liu_reg_map[i] == reg[1]) {
+ *val = exar7300_read(sc, i);
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void t3e3_reg_write(struct channel *sc, u32 *reg)
+{
+ u32 i;
+
+ switch (reg[0]) {
+ case SBE_2T3E3_CHIP_21143:
+ dc_write(sc->addr, reg[1], reg[2]);
+ break;
+ case SBE_2T3E3_CHIP_CPLD:
+ for (i = 0; i < SBE_2T3E3_CPLD_REG_MAX; i++)
+ if (cpld_reg_map[i][sc->h.slot] == reg[1]) {
+ cpld_write(sc, i, reg[2]);
+ break;
+ }
+ break;
+ case SBE_2T3E3_CHIP_FRAMER:
+ for (i = 0; i < SBE_2T3E3_FRAMER_REG_MAX; i++)
+ if (t3e3_framer_reg_map[i] == reg[1]) {
+ exar7250_write(sc, i, reg[2]);
+ break;
+ }
+ break;
+ case SBE_2T3E3_CHIP_LIU:
+ for (i = 0; i < SBE_2T3E3_LIU_REG_MAX; i++)
+ if (t3e3_liu_reg_map[i] == reg[1]) {
+ exar7300_write(sc, i, reg[2]);
+ break;
+ }
+ break;
+ }
+}
+
+void t3e3_port_get(struct channel *sc, t3e3_param_t *param)
+{
+ memcpy(param, &(sc->p), sizeof(t3e3_param_t));
+}
+
+void t3e3_port_set(struct channel *sc, t3e3_param_t *param)
+{
+ if (param->frame_mode != 0xff)
+ cpld_set_frame_mode(sc, param->frame_mode);
+
+ if (param->fractional_mode != 0xff)
+ cpld_set_fractional_mode(sc, param->fractional_mode,
+ param->bandwidth_start,
+ param->bandwidth_stop);
+
+ if (param->pad_count != 0xff)
+ cpld_set_pad_count(sc, param->pad_count);
+
+ if (param->crc != 0xff)
+ cpld_set_crc(sc, param->crc);
+
+ if (param->receiver_on != 0xff)
+ dc_receiver_onoff(sc, param->receiver_on);
+
+ if (param->transmitter_on != 0xff)
+ dc_transmitter_onoff(sc, param->transmitter_on);
+
+ if (param->frame_type != 0xff)
+ t3e3_set_frame_type(sc, param->frame_type);
+
+ if (param->panel != 0xff)
+ cpld_select_panel(sc, param->panel);
+
+ if (param->line_build_out != 0xff)
+ exar7300_line_build_out_onoff(sc, param->line_build_out);
+
+ if (param->receive_equalization != 0xff)
+ exar7300_receive_equalization_onoff(sc, param->receive_equalization);
+
+ if (param->transmit_all_ones != 0xff)
+ exar7300_transmit_all_ones_onoff(sc, param->transmit_all_ones);
+
+ if (param->loopback != 0xff)
+ t3e3_set_loopback(sc, param->loopback);
+
+ if (param->clock_source != 0xff)
+ cpld_set_clock(sc, param->clock_source);
+
+ if (param->scrambler != 0xff)
+ cpld_set_scrambler(sc, param->scrambler);
+}
+
+void t3e3_port_get_stats(struct channel *sc,
+ t3e3_stats_t *stats)
+{
+ u32 result;
+
+ sc->s.LOC = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL)
+ & SBE_2T3E3_FRAMER_VAL_LOSS_OF_CLOCK_STATUS ? 1 : 0;
+
+ switch (sc->p.frame_type) {
+ case SBE_2T3E3_FRAME_TYPE_E3_G751:
+ case SBE_2T3E3_FRAME_TYPE_E3_G832:
+ result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
+ sc->s.LOF = result & SBE_2T3E3_FRAMER_VAL_E3_RX_LOF ? 1 : 0;
+ sc->s.OOF = result & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
+#if 0
+ sc->s.LOS = result & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS ? 1 : 0;
+#else
+ cpld_LOS_update(sc);
+#endif
+ sc->s.AIS = result & SBE_2T3E3_FRAMER_VAL_E3_RX_AIS ? 1 : 0;
+ sc->s.FERF = result & SBE_2T3E3_FRAMER_VAL_E3_RX_FERF ? 1 : 0;
+ break;
+
+ case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
+ case SBE_2T3E3_FRAME_TYPE_T3_M13:
+ result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
+ sc->s.AIS = result & SBE_2T3E3_FRAMER_VAL_T3_RX_AIS ? 1 : 0;
+#if 0
+ sc->s.LOS = result & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS ? 1 : 0;
+#else
+ cpld_LOS_update(sc);
+#endif
+ sc->s.IDLE = result & SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE ? 1 : 0;
+ sc->s.OOF = result & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
+
+ result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_STATUS);
+ sc->s.FERF = result & SBE_2T3E3_FRAMER_VAL_T3_RX_FERF ? 1 : 0;
+ sc->s.AIC = result & SBE_2T3E3_FRAMER_VAL_T3_RX_AIC ? 1 : 0;
+ sc->s.FEBE_code = result & SBE_2T3E3_FRAMER_VAL_T3_RX_FEBE;
+
+ sc->s.FEAC = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC);
+ break;
+
+ default:
+ break;
+ }
+
+ result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_PMON_LCV_EVENT_COUNT_MSB) << 8;
+ result += exar7250_read(sc, SBE_2T3E3_FRAMER_REG_PMON_HOLDING_REGISTER);
+ sc->s.LCV += result;
+
+ result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_PMON_FRAMING_BIT_ERROR_EVENT_COUNT_MSB) << 8;
+ result += exar7250_read(sc, SBE_2T3E3_FRAMER_REG_PMON_HOLDING_REGISTER);
+ sc->s.FRAMING_BIT += result;
+
+ result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_PMON_PARITY_ERROR_EVENT_COUNT_MSB) << 8;
+ result += exar7250_read(sc, SBE_2T3E3_FRAMER_REG_PMON_HOLDING_REGISTER);
+ sc->s.PARITY_ERROR += result;
+
+ result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_PMON_FEBE_EVENT_COUNT_MSB) << 8;
+ result += exar7250_read(sc, SBE_2T3E3_FRAMER_REG_PMON_HOLDING_REGISTER);
+ sc->s.FEBE_count += result;
+
+ result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_PMON_CP_BIT_ERROR_EVENT_COUNT_MSB) << 8;
+ result += exar7250_read(sc, SBE_2T3E3_FRAMER_REG_PMON_HOLDING_REGISTER);
+ sc->s.CP_BIT += result;
+
+ memcpy(stats, &(sc->s), sizeof(t3e3_stats_t));
+}
+
+void t3e3_port_del_stats(struct channel *sc)
+{
+ memset(&(sc->s), 0, sizeof(t3e3_stats_t));
+}
+
+void t3e3_if_config(struct channel *sc, u32 cmd, char *set,
+ t3e3_resp_t *ret, int *rlen)
+{
+ t3e3_param_t *param = (t3e3_param_t *)set;
+ u32 *data = (u32 *)set;
+
+ /* turn off all interrupt */
+ /* cpld_stop_intr(sc); */
+
+ switch (cmd) {
+ case SBE_2T3E3_PORT_GET:
+ t3e3_port_get(sc, &(ret->u.param));
+ *rlen = sizeof(ret->u.param);
+ break;
+ case SBE_2T3E3_PORT_SET:
+ t3e3_port_set(sc, param);
+ *rlen = 0;
+ break;
+ case SBE_2T3E3_PORT_GET_STATS:
+ t3e3_port_get_stats(sc, &(ret->u.stats));
+ *rlen = sizeof(ret->u.stats);
+ break;
+ case SBE_2T3E3_PORT_DEL_STATS:
+ t3e3_port_del_stats(sc);
+ *rlen = 0;
+ break;
+ case SBE_2T3E3_PORT_READ_REGS:
+ t3e3_reg_read(sc, data, &(ret->u.data));
+ *rlen = sizeof(ret->u.data);
+ break;
+ case SBE_2T3E3_PORT_WRITE_REGS:
+#if 0
+ printk(KERN_DEBUG "SBE_2T3E3_PORT_WRITE_REGS, 0x%x, 0x%x, 0x%x\n",
+ ((int*)data)[0], ((int*)data)[1], ((int*)data)[2]);
+#endif
+ t3e3_reg_write(sc, data);
+ *rlen = 0;
+ break;
+ case SBE_2T3E3_LOG_LEVEL:
+ *rlen = 0;
+ break;
+ default:
+ *rlen = 0;
+ break;
+ }
+
+ /* turn on interrupt */
+ /* cpld_start_intr(sc); */
+}
+
+void t3e3_sc_init(struct channel *sc)
+{
+ memset(sc, 0, sizeof(*sc));
+
+ sc->p.frame_mode = SBE_2T3E3_FRAME_MODE_HDLC;
+ sc->p.fractional_mode = SBE_2T3E3_FRACTIONAL_MODE_NONE;
+ sc->p.crc = SBE_2T3E3_CRC_32;
+ sc->p.receiver_on = SBE_2T3E3_OFF;
+ sc->p.transmitter_on = SBE_2T3E3_OFF;
+ sc->p.frame_type = SBE_2T3E3_FRAME_TYPE_T3_CBIT;
+ sc->p.panel = SBE_2T3E3_PANEL_FRONT;
+ sc->p.line_build_out = SBE_2T3E3_OFF;
+ sc->p.receive_equalization = SBE_2T3E3_OFF;
+ sc->p.transmit_all_ones = SBE_2T3E3_OFF;
+ sc->p.loopback = SBE_2T3E3_LOOPBACK_NONE;
+ sc->p.clock_source = SBE_2T3E3_TIMING_LOCAL;
+ sc->p.scrambler = SBE_2T3E3_SCRAMBLER_OFF;
+ sc->p.pad_count = SBE_2T3E3_PAD_COUNT_1;
+}
diff --git a/drivers/staging/sbe-2t3e3/ctrl.h b/drivers/staging/sbe-2t3e3/ctrl.h
new file mode 100644
index 0000000..c11a588
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/ctrl.h
@@ -0,0 +1,131 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#ifndef CTRL_H
+#define CTRL_H
+
+#define SBE_2T3E3_OFF 0
+#define SBE_2T3E3_ON 1
+
+#define SBE_2T3E3_LED_NONE 0
+#define SBE_2T3E3_LED_GREEN 1
+#define SBE_2T3E3_LED_YELLOW 2
+
+#define SBE_2T3E3_CABLE_LENGTH_LESS_THAN_255_FEET 0
+#define SBE_2T3E3_CABLE_LENGTH_GREATER_THAN_255_FEET 1
+
+#define SBE_2T3E3_CRC_16 0
+#define SBE_2T3E3_CRC_32 1
+
+#define SBE_2T3E3_PANEL_FRONT 0
+#define SBE_2T3E3_PANEL_REAR 1
+
+#define SBE_2T3E3_FRAME_MODE_HDLC 0
+#define SBE_2T3E3_FRAME_MODE_TRANSPARENT 1
+#define SBE_2T3E3_FRAME_MODE_RAW 2
+
+#define SBE_2T3E3_FRAME_TYPE_E3_G751 0
+#define SBE_2T3E3_FRAME_TYPE_E3_G832 1
+#define SBE_2T3E3_FRAME_TYPE_T3_CBIT 2
+#define SBE_2T3E3_FRAME_TYPE_T3_M13 3
+
+#define SBE_2T3E3_FRACTIONAL_MODE_NONE 0
+#define SBE_2T3E3_FRACTIONAL_MODE_0 1
+#define SBE_2T3E3_FRACTIONAL_MODE_1 2
+#define SBE_2T3E3_FRACTIONAL_MODE_2 3
+
+#define SBE_2T3E3_SCRAMBLER_OFF 0
+#define SBE_2T3E3_SCRAMBLER_LARSCOM 1
+#define SBE_2T3E3_SCRAMBLER_ADC_KENTROX_DIGITAL 2
+
+#define SBE_2T3E3_TIMING_LOCAL 0
+#define SBE_2T3E3_TIMING_LOOP 1
+
+#define SBE_2T3E3_LOOPBACK_NONE 0
+#define SBE_2T3E3_LOOPBACK_ETHERNET 1
+#define SBE_2T3E3_LOOPBACK_FRAMER 2
+#define SBE_2T3E3_LOOPBACK_LIU_DIGITAL 3
+#define SBE_2T3E3_LOOPBACK_LIU_ANALOG 4
+#define SBE_2T3E3_LOOPBACK_LIU_REMOTE 5
+
+#define SBE_2T3E3_PAD_COUNT_1 1
+#define SBE_2T3E3_PAD_COUNT_2 2
+#define SBE_2T3E3_PAD_COUNT_3 3
+#define SBE_2T3E3_PAD_COUNT_4 4
+
+#define SBE_2T3E3_CHIP_21143 0
+#define SBE_2T3E3_CHIP_CPLD 1
+#define SBE_2T3E3_CHIP_FRAMER 2
+#define SBE_2T3E3_CHIP_LIU 3
+
+#define SBE_2T3E3_LOG_LEVEL_NONE 0
+#define SBE_2T3E3_LOG_LEVEL_ERROR 1
+#define SBE_2T3E3_LOG_LEVEL_WARNING 2
+#define SBE_2T3E3_LOG_LEVEL_INFO 3
+
+/* commands */
+#define SBE_2T3E3_PORT_GET 0
+#define SBE_2T3E3_PORT_SET 1
+#define SBE_2T3E3_PORT_GET_STATS 2
+#define SBE_2T3E3_PORT_DEL_STATS 3
+#define SBE_2T3E3_PORT_READ_REGS 4
+#define SBE_2T3E3_LOG_LEVEL 5
+#define SBE_2T3E3_PORT_WRITE_REGS 6
+
+#define NG_SBE_2T3E3_NODE_TYPE "sbe2T3E3"
+#define NG_SBE_2T3E3_COOKIE 0x03800891
+
+typedef struct t3e3_param {
+ u_int8_t frame_mode; /* FRAME_MODE_* */
+ u_int8_t crc; /* CRC_* */
+ u_int8_t receiver_on; /* ON/OFF */
+ u_int8_t transmitter_on; /* ON/OFF */
+ u_int8_t frame_type; /* FRAME_TYPE_* */
+ u_int8_t panel; /* PANEL_* */
+ u_int8_t line_build_out; /* ON/OFF */
+ u_int8_t receive_equalization; /* ON/OFF */
+ u_int8_t transmit_all_ones; /* ON/OFF */
+ u_int8_t loopback; /* LOOPBACK_* */
+ u_int8_t clock_source; /* TIMING_* */
+ u_int8_t scrambler; /* SCRAMBLER_* */
+ u_int8_t pad_count; /* PAD_COUNT_* */
+ u_int8_t log_level; /* LOG_LEVEL_* - unused */
+ u_int8_t fractional_mode; /* FRACTIONAL_MODE_* */
+ u_int8_t bandwidth_start; /* 0-255 */
+ u_int8_t bandwidth_stop; /* 0-255 */
+} t3e3_param_t;
+
+typedef struct t3e3_stats {
+ u_int64_t in_bytes;
+ u32 in_packets, in_dropped;
+ u32 in_errors, in_error_desc, in_error_coll, in_error_drib,
+ in_error_crc, in_error_mii;
+ u_int64_t out_bytes;
+ u32 out_packets, out_dropped;
+ u32 out_errors, out_error_jab, out_error_lost_carr,
+ out_error_no_carr, out_error_link_fail, out_error_underflow,
+ out_error_dereferred;
+ u_int8_t LOC, LOF, OOF, LOS, AIS, FERF, IDLE, AIC, FEAC;
+ u_int16_t FEBE_code;
+ u32 LCV, FRAMING_BIT, PARITY_ERROR, FEBE_count, CP_BIT;
+} t3e3_stats_t;
+
+
+typedef struct t3e3_resp {
+ union {
+ t3e3_param_t param;
+ t3e3_stats_t stats;
+ u32 data;
+ } u;
+} t3e3_resp_t;
+
+#endif /* CTRL_H */
diff --git a/drivers/staging/sbe-2t3e3/dc.c b/drivers/staging/sbe-2t3e3/dc.c
new file mode 100644
index 0000000..126a972
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/dc.c
@@ -0,0 +1,502 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include <linux/netdevice.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include "2t3e3.h"
+#include "ctrl.h"
+
+void dc_init(struct channel *sc)
+{
+ u32 val;
+
+ dc_stop(sc);
+ /*dc_reset(sc);*/ /* do not want to reset here */
+
+ /*
+ * BUS_MODE (CSR0)
+ */
+ val = SBE_2T3E3_21143_VAL_READ_LINE_ENABLE |
+ SBE_2T3E3_21143_VAL_READ_MULTIPLE_ENABLE |
+ SBE_2T3E3_21143_VAL_TRANSMIT_AUTOMATIC_POLLING_200us |
+ SBE_2T3E3_21143_VAL_BUS_ARBITRATION_RR;
+
+ if (sc->h.command & 16)
+ val |= SBE_2T3E3_21143_VAL_WRITE_AND_INVALIDATE_ENABLE;
+
+ switch (sc->h.cache_size) {
+ case 32:
+ val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_32;
+ break;
+ case 16:
+ val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_16;
+ break;
+ case 8:
+ val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_8;
+ break;
+ default:
+ break;
+ }
+
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE, val);
+
+ /* OPERATION_MODE (CSR6) */
+ val = SBE_2T3E3_21143_VAL_RECEIVE_ALL |
+ SBE_2T3E3_21143_VAL_MUST_BE_ONE |
+ SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_1 |
+ SBE_2T3E3_21143_VAL_LOOPBACK_OFF |
+ SBE_2T3E3_21143_VAL_PASS_ALL_MULTICAST |
+ SBE_2T3E3_21143_VAL_PROMISCUOUS_MODE |
+ SBE_2T3E3_21143_VAL_PASS_BAD_FRAMES;
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
+ if (sc->p.loopback == SBE_2T3E3_LOOPBACK_ETHERNET)
+ sc->p.loopback = SBE_2T3E3_LOOPBACK_NONE;
+
+#if 0 /* No need to clear this register - and it may be in use */
+ /*
+ * BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT (CSR9)
+ */
+ val = 0;
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, val);
+#endif
+
+ /*
+ * GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL (CSR11)
+ */
+ val = SBE_2T3E3_21143_VAL_CYCLE_SIZE |
+ SBE_2T3E3_21143_VAL_TRANSMIT_TIMER |
+ SBE_2T3E3_21143_VAL_NUMBER_OF_TRANSMIT_PACKETS |
+ SBE_2T3E3_21143_VAL_RECEIVE_TIMER |
+ SBE_2T3E3_21143_VAL_NUMBER_OF_RECEIVE_PACKETS;
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL, val);
+
+ /* prepare descriptors and data for receive and transmit procecsses */
+ if (dc_init_descriptor_list(sc) != 0)
+ return;
+
+ /* clear ethernet interrupts status */
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
+
+ /* SIA mode registers */
+ dc_set_output_port(sc);
+}
+
+void dc_start(struct channel *sc)
+{
+ u32 val;
+
+ if (!(sc->r.flags & SBE_2T3E3_FLAG_NETWORK_UP))
+ return;
+
+ dc_init(sc);
+
+ /* get actual LOS and OOF status */
+ switch (sc->p.frame_type) {
+ case SBE_2T3E3_FRAME_TYPE_E3_G751:
+ case SBE_2T3E3_FRAME_TYPE_E3_G832:
+ val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
+ dev_dbg(&sc->pdev->dev, "Start Framer Rx Status = %02X\n", val);
+ sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
+ break;
+ case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
+ case SBE_2T3E3_FRAME_TYPE_T3_M13:
+ val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
+ dev_dbg(&sc->pdev->dev, "Start Framer Rx Status = %02X\n", val);
+ sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
+ break;
+ default:
+ break;
+ }
+ cpld_LOS_update(sc);
+
+ /* start receive and transmit processes */
+ dc_transmitter_onoff(sc, SBE_2T3E3_ON);
+ dc_receiver_onoff(sc, SBE_2T3E3_ON);
+
+ /* start interrupts */
+ dc_start_intr(sc);
+}
+
+#define MAX_INT_WAIT_CNT 12000
+void dc_stop(struct channel *sc)
+{
+ int wcnt;
+
+ /* stop receive and transmit processes */
+ dc_receiver_onoff(sc, SBE_2T3E3_OFF);
+ dc_transmitter_onoff(sc, SBE_2T3E3_OFF);
+
+ /* turn off ethernet interrupts */
+ dc_stop_intr(sc);
+
+ /* wait to ensure the interrupts have been completed */
+ for (wcnt = 0; wcnt < MAX_INT_WAIT_CNT; wcnt++) {
+ udelay(5);
+ if (!sc->interrupt_active)
+ break;
+ }
+ if (wcnt >= MAX_INT_WAIT_CNT)
+ dev_warn(&sc->pdev->dev, "SBE 2T3E3: Interrupt active too long\n");
+
+ /* clear all receive/transmit data */
+ dc_drop_descriptor_list(sc);
+}
+
+void dc_start_intr(struct channel *sc)
+{
+ if (sc->p.loopback == SBE_2T3E3_LOOPBACK_NONE && sc->s.OOF)
+ return;
+
+ if (sc->p.receiver_on || sc->p.transmitter_on) {
+ if (!sc->ether.interrupt_enable_mask)
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
+
+ sc->ether.interrupt_enable_mask =
+ SBE_2T3E3_21143_VAL_NORMAL_INTERRUPT_SUMMARY_ENABLE |
+ SBE_2T3E3_21143_VAL_ABNORMAL_INTERRUPT_SUMMARY_ENABLE |
+ SBE_2T3E3_21143_VAL_RECEIVE_STOPPED_ENABLE |
+ SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE_ENABLE |
+ SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT_ENABLE |
+ SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW_INTERRUPT_ENABLE |
+ SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE_ENABLE |
+ SBE_2T3E3_21143_VAL_TRANSMIT_STOPPED_ENABLE |
+ SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT_ENABLE;
+
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE,
+ sc->ether.interrupt_enable_mask);
+ }
+}
+
+void dc_stop_intr(struct channel *sc)
+{
+ sc->ether.interrupt_enable_mask = 0;
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
+}
+
+void dc_reset(struct channel *sc)
+{
+ /* turn off ethernet interrupts */
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
+
+ /* software reset */
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE,
+ SBE_2T3E3_21143_VAL_SOFTWARE_RESET);
+ udelay(4); /* 50 PCI cycles < 2us */
+
+ /* clear hardware configuration */
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE, 0);
+
+ /* clear software configuration */
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, 0);
+
+ /* turn off SIA reset */
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
+ SBE_2T3E3_21143_VAL_SIA_RESET);
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE, 0);
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT, 0);
+}
+
+
+void dc_receiver_onoff(struct channel *sc, u32 mode)
+{
+ u32 i, state = 0;
+
+ if (sc->p.receiver_on == mode)
+ return;
+
+ switch (mode) {
+ case SBE_2T3E3_OFF:
+ if (dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
+ SBE_2T3E3_21143_VAL_RECEIVE_START) {
+ dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_RECEIVE_START);
+
+ for (i = 0; i < 16; i++) {
+ state = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS) &
+ SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STATE;
+ if (state == SBE_2T3E3_21143_VAL_RX_STOPPED)
+ break;
+ udelay(5);
+ }
+ if (state != SBE_2T3E3_21143_VAL_RX_STOPPED)
+ dev_warn(&sc->pdev->dev, "SBE 2T3E3: Rx failed to stop\n");
+ else
+ dev_info(&sc->pdev->dev, "SBE 2T3E3: Rx off\n");
+ }
+ break;
+ case SBE_2T3E3_ON:
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_RECEIVE_START);
+ udelay(100);
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND, 0xFFFFFFFF);
+ break;
+ default:
+ return;
+ }
+
+ sc->p.receiver_on = mode;
+}
+
+void dc_transmitter_onoff(struct channel *sc, u32 mode)
+{
+ u32 i, state = 0;
+
+ if (sc->p.transmitter_on == mode)
+ return;
+
+ switch (mode) {
+ case SBE_2T3E3_OFF:
+ if (dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
+ SBE_2T3E3_21143_VAL_TRANSMISSION_START) {
+ dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_TRANSMISSION_START);
+
+ for (i = 0; i < 16; i++) {
+ state = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS) &
+ SBE_2T3E3_21143_VAL_TRANSMISSION_PROCESS_STATE;
+ if (state == SBE_2T3E3_21143_VAL_TX_STOPPED)
+ break;
+ udelay(5);
+ }
+ if (state != SBE_2T3E3_21143_VAL_TX_STOPPED)
+ dev_warn(&sc->pdev->dev, "SBE 2T3E3: Tx failed to stop\n");
+ }
+ break;
+ case SBE_2T3E3_ON:
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_TRANSMISSION_START);
+ udelay(100);
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_POLL_DEMAND, 0xFFFFFFFF);
+ break;
+ default:
+ return;
+ }
+
+ sc->p.transmitter_on = mode;
+}
+
+
+
+void dc_set_loopback(struct channel *sc, u32 mode)
+{
+ u32 val;
+
+ switch (mode) {
+ case SBE_2T3E3_21143_VAL_LOOPBACK_OFF:
+ case SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL:
+ break;
+ default:
+ return;
+ }
+
+#if 0
+ /* restart SIA */
+ dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
+ SBE_2T3E3_21143_VAL_SIA_RESET);
+ udelay(1000);
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
+ SBE_2T3E3_21143_VAL_SIA_RESET);
+#endif
+
+ /* select loopback mode */
+ val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
+ ~SBE_2T3E3_21143_VAL_OPERATING_MODE;
+ val |= mode;
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
+
+ if (mode == SBE_2T3E3_21143_VAL_LOOPBACK_OFF)
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
+ else
+ dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
+}
+
+u32 dc_init_descriptor_list(struct channel *sc)
+{
+ u32 i, j;
+ struct sk_buff *m;
+
+ if (sc->ether.rx_ring == NULL)
+ sc->ether.rx_ring = kzalloc(SBE_2T3E3_RX_DESC_RING_SIZE *
+ sizeof(t3e3_rx_desc_t), GFP_KERNEL);
+ if (sc->ether.rx_ring == NULL) {
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
+ return ENOMEM;
+ }
+
+ if (sc->ether.tx_ring == NULL)
+ sc->ether.tx_ring = kzalloc(SBE_2T3E3_TX_DESC_RING_SIZE *
+ sizeof(t3e3_tx_desc_t), GFP_KERNEL);
+ if (sc->ether.tx_ring == NULL) {
+#ifdef T3E3_USE_CONTIGMALLOC
+ t3e3_contigmemory_size = SBE_2T3E3_RX_DESC_RING_SIZE *
+ sizeof(t3e3_rx_desc_t);
+#endif
+ kfree(sc->ether.rx_ring);
+ sc->ether.rx_ring = NULL;
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
+ return ENOMEM;
+ }
+
+
+ /*
+ * Receive ring
+ */
+ for (i = 0; i < SBE_2T3E3_RX_DESC_RING_SIZE; i++) {
+ sc->ether.rx_ring[i].rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
+ sc->ether.rx_ring[i].rdes1 =
+ SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED | SBE_2T3E3_MTU;
+
+ if (sc->ether.rx_data[i] == NULL) {
+ if (!(m = dev_alloc_skb(MCLBYTES))) {
+ for (j = 0; j < i; j++) {
+ dev_kfree_skb_any(sc->ether.rx_data[j]);
+ sc->ether.rx_data[j] = NULL;
+ }
+#ifdef T3E3_USE_CONTIGMALLOC
+ t3e3_contigmemory_size = SBE_2T3E3_RX_DESC_RING_SIZE *
+ sizeof(t3e3_rx_desc_t);
+#endif
+ kfree(sc->ether.rx_ring);
+ sc->ether.rx_ring = NULL;
+#ifdef T3E3_USE_CONTIGMALLOC
+ t3e3_contigmemory_size = SBE_2T3E3_TX_DESC_RING_SIZE *
+ sizeof(t3e3_tx_desc_t);
+#endif
+ kfree(sc->ether.tx_ring);
+ sc->ether.tx_ring = NULL;
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: token_alloc err:"
+ " no buffer space for RX ring\n");
+ return ENOBUFS;
+ }
+ sc->ether.rx_data[i] = m;
+ }
+ sc->ether.rx_ring[i].rdes2 = virt_to_phys(sc->ether.rx_data[i]->data);
+
+ sc->ether.rx_ring[i].rdes3 = virt_to_phys(
+ &sc->ether.rx_ring[(i + 1) % SBE_2T3E3_RX_DESC_RING_SIZE]);
+ }
+ sc->ether.rx_ring[SBE_2T3E3_RX_DESC_RING_SIZE - 1].rdes1 |=
+ SBE_2T3E3_RX_DESC_END_OF_RING;
+ sc->ether.rx_ring_current_read = 0;
+
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS,
+ virt_to_phys(&sc->ether.rx_ring[0]));
+
+ /*
+ * Transmit ring
+ */
+ for (i = 0; i < SBE_2T3E3_TX_DESC_RING_SIZE; i++) {
+ sc->ether.tx_ring[i].tdes0 = 0;
+ sc->ether.tx_ring[i].tdes1 = SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED |
+ SBE_2T3E3_TX_DESC_DISABLE_PADDING;
+
+ sc->ether.tx_ring[i].tdes2 = 0;
+ sc->ether.tx_data[i] = NULL;
+
+ sc->ether.tx_ring[i].tdes3 = virt_to_phys(
+ &sc->ether.tx_ring[(i + 1) % SBE_2T3E3_TX_DESC_RING_SIZE]);
+ }
+ sc->ether.tx_ring[SBE_2T3E3_TX_DESC_RING_SIZE - 1].tdes1 |=
+ SBE_2T3E3_TX_DESC_END_OF_RING;
+
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS,
+ virt_to_phys(&sc->ether.tx_ring[0]));
+ sc->ether.tx_ring_current_read = 0;
+ sc->ether.tx_ring_current_write = 0;
+ sc->ether.tx_free_cnt = SBE_2T3E3_TX_DESC_RING_SIZE;
+ spin_lock_init(&sc->ether.tx_lock);
+
+ return 0;
+}
+
+void dc_clear_descriptor_list(struct channel *sc)
+{
+ u32 i;
+
+ /* clear CSR3 and CSR4 */
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS, 0);
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS, 0);
+
+ /* free all data buffers on TX ring */
+ for (i = 0; i < SBE_2T3E3_TX_DESC_RING_SIZE; i++) {
+ if (sc->ether.tx_data[i] != NULL) {
+ dev_kfree_skb_any(sc->ether.tx_data[i]);
+ sc->ether.tx_data[i] = NULL;
+ }
+ }
+}
+
+void dc_drop_descriptor_list(struct channel *sc)
+{
+ u32 i;
+
+ dc_clear_descriptor_list(sc);
+
+ /* free all data buffers on RX ring */
+ for (i = 0; i < SBE_2T3E3_RX_DESC_RING_SIZE; i++) {
+ if (sc->ether.rx_data[i] != NULL) {
+ dev_kfree_skb_any(sc->ether.rx_data[i]);
+ sc->ether.rx_data[i] = NULL;
+ }
+ }
+
+ if (sc->ether.rx_ring != NULL) {
+#ifdef T3E3_USE_CONTIGMALLOC
+ t3e3_contigmemory_size = SBE_2T3E3_RX_DESC_RING_SIZE *
+ sizeof(t3e3_rx_desc_t);
+#endif
+ kfree(sc->ether.rx_ring);
+ sc->ether.rx_ring = NULL;
+ }
+
+ if (sc->ether.tx_ring != NULL) {
+#ifdef T3E3_USE_CONTIGMALLOC
+ t3e3_contigmemory_size = SBE_2T3E3_TX_DESC_RING_SIZE *
+ sizeof(t3e3_tx_desc_t);
+#endif
+ kfree(sc->ether.tx_ring);
+ sc->ether.tx_ring = NULL;
+ }
+}
+
+
+void dc_set_output_port(struct channel *sc)
+{
+ dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_PORT_SELECT);
+
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_STATUS, 0x00000301);
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY, 0);
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE, 0);
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT, 0x08000011);
+
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_TRANSMIT_THRESHOLD_MODE_100Mbs |
+ SBE_2T3E3_21143_VAL_HEARTBEAT_DISABLE |
+ SBE_2T3E3_21143_VAL_PORT_SELECT |
+ SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
+}
+
+void dc_restart(struct channel *sc)
+{
+ dev_warn(&sc->pdev->dev, "SBE 2T3E3: 21143 restart\n");
+
+ dc_stop(sc);
+ dc_reset(sc);
+ dc_init(sc); /* stop + reset + init */
+ dc_start(sc);
+}
diff --git a/drivers/staging/sbe-2t3e3/exar7250.c b/drivers/staging/sbe-2t3e3/exar7250.c
new file mode 100644
index 0000000..809f446
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/exar7250.c
@@ -0,0 +1,217 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include "2t3e3.h"
+#include "ctrl.h"
+
+void exar7250_init(struct channel *sc)
+{
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE,
+ SBE_2T3E3_FRAMER_VAL_T3_CBIT |
+ SBE_2T3E3_FRAMER_VAL_INTERRUPT_ENABLE_RESET |
+ SBE_2T3E3_FRAMER_VAL_TIMING_ASYNCH_TXINCLK);
+
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL,
+ SBE_2T3E3_FRAMER_VAL_DISABLE_TX_LOSS_OF_CLOCK |
+ SBE_2T3E3_FRAMER_VAL_DISABLE_RX_LOSS_OF_CLOCK |
+ SBE_2T3E3_FRAMER_VAL_AMI_LINE_CODE |
+ SBE_2T3E3_FRAMER_VAL_RX_LINE_CLOCK_INVERT);
+
+ exar7250_set_frame_type(sc, SBE_2T3E3_FRAME_TYPE_T3_CBIT);
+}
+
+void exar7250_set_frame_type(struct channel *sc, u32 type)
+{
+ u32 val;
+
+ switch (type) {
+ case SBE_2T3E3_FRAME_TYPE_E3_G751:
+ case SBE_2T3E3_FRAME_TYPE_E3_G832:
+ case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
+ case SBE_2T3E3_FRAME_TYPE_T3_M13:
+ break;
+ default:
+ return;
+ }
+
+ exar7250_stop_intr(sc, type);
+
+ val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE);
+ val &= ~(SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE |
+ SBE_2T3E3_FRAMER_VAL_T3_E3_SELECT |
+ SBE_2T3E3_FRAMER_VAL_FRAME_FORMAT_SELECT);
+ switch (type) {
+ case SBE_2T3E3_FRAME_TYPE_E3_G751:
+ val |= SBE_2T3E3_FRAMER_VAL_E3_G751;
+ break;
+ case SBE_2T3E3_FRAME_TYPE_E3_G832:
+ val |= SBE_2T3E3_FRAMER_VAL_E3_G832;
+ break;
+ case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
+ val |= SBE_2T3E3_FRAMER_VAL_T3_CBIT;
+ break;
+ case SBE_2T3E3_FRAME_TYPE_T3_M13:
+ val |= SBE_2T3E3_FRAMER_VAL_T3_M13;
+ break;
+ default:
+ return;
+ }
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE, val);
+ exar7250_start_intr(sc, type);
+}
+
+
+void exar7250_start_intr(struct channel *sc, u32 type)
+{
+ u32 val;
+
+ switch (type) {
+ case SBE_2T3E3_FRAME_TYPE_E3_G751:
+ case SBE_2T3E3_FRAME_TYPE_E3_G832:
+ val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
+#if 0
+ sc->s.LOS = val & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS ? 1 : 0;
+#else
+ cpld_LOS_update(sc);
+#endif
+ sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1);
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1,
+ SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE);
+#if 0
+ /*SBE_2T3E3_FRAMER_VAL_E3_RX_COFA_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_AIS_INTERRUPT_ENABLE);*/
+#endif
+
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2);
+#if 0
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2,
+ SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_ENABLE);
+#endif
+ break;
+
+ case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
+ case SBE_2T3E3_FRAME_TYPE_T3_M13:
+ val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
+#if 0
+ sc->s.LOS = val & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS ? 1 : 0;
+#else
+ cpld_LOS_update(sc);
+#endif
+ sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
+
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS);
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE,
+ SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE);
+#if 0
+ /* SBE_2T3E3_FRAMER_VAL_T3_RX_CP_BIT_ERROR_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_AIS_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_FERF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_AIC_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_P_BIT_INTERRUPT_ENABLE);*/
+#endif
+
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS);
+#if 0
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS,
+ SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_ENABLE);
+#endif
+
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL, 0);
+ break;
+
+ default:
+ return;
+ }
+
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS);
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE,
+ SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_ENABLE);
+}
+
+
+void exar7250_stop_intr(struct channel *sc, u32 type)
+{
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE, 0);
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS);
+
+ switch (type) {
+ case SBE_2T3E3_FRAME_TYPE_E3_G751:
+ case SBE_2T3E3_FRAME_TYPE_E3_G832:
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1, 0);
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1);
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2, 0);
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2);
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_CONTROL, 0);
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_CONTROL);
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS, 0);
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS);
+ break;
+
+ case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
+ case SBE_2T3E3_FRAME_TYPE_T3_M13:
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE, 0);
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS);
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS, 0);
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS);
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL, 0);
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL);
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS, 0);
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS);
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS, 0);
+ exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS);
+ break;
+ }
+}
+
+
+
+
+void exar7250_unipolar_onoff(struct channel *sc, u32 mode)
+{
+ switch (mode) {
+ case SBE_2T3E3_OFF:
+ exar7300_clear_bit(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL,
+ SBE_2T3E3_FRAMER_VAL_UNIPOLAR);
+ break;
+ case SBE_2T3E3_ON:
+ exar7300_set_bit(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL,
+ SBE_2T3E3_FRAMER_VAL_UNIPOLAR);
+ break;
+ }
+}
+
+void exar7250_set_loopback(struct channel *sc, u32 mode)
+{
+ switch (mode) {
+ case SBE_2T3E3_FRAMER_VAL_LOOPBACK_OFF:
+ exar7300_clear_bit(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE,
+ SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE);
+ break;
+ case SBE_2T3E3_FRAMER_VAL_LOOPBACK_ON:
+ exar7300_set_bit(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE,
+ SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE);
+ break;
+ }
+}
diff --git a/drivers/staging/sbe-2t3e3/exar7300.c b/drivers/staging/sbe-2t3e3/exar7300.c
new file mode 100644
index 0000000..d10d696
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/exar7300.c
@@ -0,0 +1,182 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include "2t3e3.h"
+#include "ctrl.h"
+
+void exar7300_init(struct channel *sc)
+{
+ exar7300_write(sc, SBE_2T3E3_LIU_REG_REG1, 0);
+
+ /* enable line decodeer and encoder */
+ exar7300_write(sc, SBE_2T3E3_LIU_REG_REG2, 0);
+ exar7300_write(sc, SBE_2T3E3_LIU_REG_REG3, 0);
+ exar7300_write(sc, SBE_2T3E3_LIU_REG_REG4,
+ SBE_2T3E3_LIU_VAL_T3_MODE_SELECT |
+ SBE_2T3E3_LIU_VAL_LOOPBACK_OFF);
+}
+
+void exar7300_set_loopback(struct channel *sc, u32 mode)
+{
+ u32 val;
+
+ switch (mode) {
+ case SBE_2T3E3_LIU_VAL_LOOPBACK_OFF:
+ case SBE_2T3E3_LIU_VAL_LOOPBACK_REMOTE:
+ case SBE_2T3E3_LIU_VAL_LOOPBACK_ANALOG:
+ case SBE_2T3E3_LIU_VAL_LOOPBACK_DIGITAL:
+ break;
+ default:
+ return;
+ }
+
+ val = exar7300_read(sc, SBE_2T3E3_LIU_REG_REG4);
+ val &= ~(SBE_2T3E3_LIU_VAL_LOCAL_LOOPBACK | SBE_2T3E3_LIU_VAL_REMOTE_LOOPBACK);
+ val |= mode;
+ exar7300_write(sc, SBE_2T3E3_LIU_REG_REG4, val);
+
+#if 0
+ /* TODO - is it necessary? idea from 2T3E3_HW_Test_code */
+ switch (mode) {
+ case SBE_2T3E3_LIU_VAL_LOOPBACK_OFF:
+ break;
+ case SBE_2T3E3_LIU_VAL_LOOPBACK_REMOTE:
+ exar7300_receive_equalization_onoff(sc, SBE_2T3E3_ON);
+ break;
+ case SBE_2T3E3_LIU_VAL_LOOPBACK_ANALOG:
+ exar7300_receive_equalization_onoff(sc, SBE_2T3E3_OFF);
+ break;
+ case SBE_2T3E3_LIU_VAL_LOOPBACK_DIGITAL:
+ exar7300_receive_equalization_onoff(sc, SBE_2T3E3_ON);
+ break;
+ }
+#endif
+}
+
+void exar7300_set_frame_type(struct channel *sc, u32 type)
+{
+ u32 val;
+
+ switch (type) {
+ case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
+ case SBE_2T3E3_FRAME_TYPE_T3_M13:
+ case SBE_2T3E3_FRAME_TYPE_E3_G751:
+ case SBE_2T3E3_FRAME_TYPE_E3_G832:
+ break;
+ default:
+ return;
+ }
+
+ val = exar7300_read(sc, SBE_2T3E3_LIU_REG_REG4);
+ val &= ~(SBE_2T3E3_LIU_VAL_T3_MODE_SELECT |
+ SBE_2T3E3_LIU_VAL_E3_MODE_SELECT);
+
+ switch (type) {
+ case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
+ case SBE_2T3E3_FRAME_TYPE_T3_M13:
+ val |= SBE_2T3E3_LIU_VAL_T3_MODE_SELECT;
+ break;
+ case SBE_2T3E3_FRAME_TYPE_E3_G751:
+ case SBE_2T3E3_FRAME_TYPE_E3_G832:
+ val |= SBE_2T3E3_LIU_VAL_E3_MODE_SELECT;
+ break;
+ default:
+ return;
+ }
+
+ exar7300_write(sc, SBE_2T3E3_LIU_REG_REG4, val);
+}
+
+
+void exar7300_transmit_all_ones_onoff(struct channel *sc, u32 mode)
+{
+ if (sc->p.transmit_all_ones == mode)
+ return;
+
+ switch (mode) {
+ case SBE_2T3E3_ON:
+ exar7300_set_bit(sc, SBE_2T3E3_LIU_REG_REG1,
+ SBE_2T3E3_LIU_VAL_TRANSMIT_ALL_ONES);
+ break;
+ case SBE_2T3E3_OFF:
+ exar7300_clear_bit(sc, SBE_2T3E3_LIU_REG_REG1,
+ SBE_2T3E3_LIU_VAL_TRANSMIT_ALL_ONES);
+ break;
+ default:
+ return;
+ }
+
+ sc->p.transmit_all_ones = mode;
+}
+
+void exar7300_receive_equalization_onoff(struct channel *sc, u32 mode)
+{
+ if (sc->p.receive_equalization == mode)
+ return;
+
+ switch (mode) {
+ case SBE_2T3E3_OFF:
+ exar7300_set_bit(sc, SBE_2T3E3_LIU_REG_REG2,
+ SBE_2T3E3_LIU_VAL_RECEIVE_EQUALIZATION_DISABLE);
+ break;
+ case SBE_2T3E3_ON:
+ exar7300_clear_bit(sc, SBE_2T3E3_LIU_REG_REG2,
+ SBE_2T3E3_LIU_VAL_RECEIVE_EQUALIZATION_DISABLE);
+ break;
+ default:
+ return;
+ }
+
+ sc->p.receive_equalization = mode;
+}
+
+void exar7300_line_build_out_onoff(struct channel *sc, u32 mode)
+{
+ if (sc->p.line_build_out == mode)
+ return;
+
+ switch (mode) {
+ case SBE_2T3E3_OFF:
+ exar7300_set_bit(sc, SBE_2T3E3_LIU_REG_REG1,
+ SBE_2T3E3_LIU_VAL_TRANSMIT_LEVEL_SELECT);
+ exar7300_receive_equalization_onoff(sc, SBE_2T3E3_OFF);
+ break;
+ case SBE_2T3E3_ON:
+ exar7300_clear_bit(sc, SBE_2T3E3_LIU_REG_REG1,
+ SBE_2T3E3_LIU_VAL_TRANSMIT_LEVEL_SELECT);
+ exar7300_receive_equalization_onoff(sc, SBE_2T3E3_ON);
+ break;
+ default:
+ return;
+ }
+
+ sc->p.line_build_out = mode;
+}
+
+/* TODO - what about encoder in raw mode??? disable it too? */
+void exar7300_unipolar_onoff(struct channel *sc, u32 mode)
+{
+ switch (mode) {
+ case SBE_2T3E3_OFF:
+ exar7300_clear_bit(sc, SBE_2T3E3_LIU_REG_REG3,
+ SBE_2T3E3_LIU_VAL_DECODER_DISABLE);
+ exar7300_clear_bit(sc, SBE_2T3E3_LIU_REG_REG1,
+ SBE_2T3E3_LIU_VAL_TRANSMIT_BINARY_DATA);
+ break;
+ case SBE_2T3E3_ON:
+ exar7300_set_bit(sc, SBE_2T3E3_LIU_REG_REG3,
+ SBE_2T3E3_LIU_VAL_DECODER_DISABLE);
+ exar7300_set_bit(sc, SBE_2T3E3_LIU_REG_REG1,
+ SBE_2T3E3_LIU_VAL_TRANSMIT_BINARY_DATA);
+ break;
+ }
+}
diff --git a/drivers/staging/sbe-2t3e3/intr.c b/drivers/staging/sbe-2t3e3/intr.c
new file mode 100644
index 0000000..7ad1a83
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/intr.c
@@ -0,0 +1,635 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include <linux/hdlc.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include "2t3e3.h"
+
+irqreturn_t t3e3_intr(int irq, void *dev_instance)
+{
+ struct channel *sc = dev_to_priv(dev_instance);
+ u32 val;
+ irqreturn_t ret = IRQ_NONE;
+
+ sc->interrupt_active = 1;
+
+ val = cpld_read(sc, SBE_2T3E3_CPLD_REG_PICSR);
+
+ if (val & SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_CHANGE) {
+ dev_dbg(&sc->pdev->dev,
+ "Rx LOS Chng Int r=%02x (LOS|OOF=%02x)\n",
+ val, (sc->s.LOS << 4) | sc->s.OOF);
+ cpld_LOS_update(sc);
+ ret = IRQ_HANDLED;
+ }
+
+ if (val & SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_ETHERNET_ASSERTED) {
+ dc_intr(sc);
+ ret = IRQ_HANDLED;
+ }
+
+ if (val & SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_FRAMER_ASSERTED) {
+ exar7250_intr(sc);
+ ret = IRQ_HANDLED;
+ }
+
+ /*
+ we don't care about other interrupt sources (DMO, LOS, LCV) because
+ they are handled by Framer too
+ */
+
+ sc->interrupt_active = 0;
+ return ret;
+}
+
+void dc_intr(struct channel *sc)
+{
+ u32 val;
+
+ /* disable ethernet interrupts */
+ /* grrr this clears interrupt summary bits !!! */
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
+
+ while ((val = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS)) &
+ (SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED |
+ SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE |
+ SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT |
+ SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW |
+ SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE |
+ SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED |
+ SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT)) {
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, val);
+
+ dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Ethernet controller interrupt! (CSR5 = %08X)\n",
+ val);
+
+ if (val & (SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT |
+ SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE |
+ SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED)) {
+ if (val & SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT)
+ dev_dbg(&sc->pdev->dev,
+ "Receive interrupt (LOS=%d, OOF=%d)\n",
+ sc->s.LOS, sc->s.OOF);
+ if (val & SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE)
+ dev_dbg(&sc->pdev->dev,
+ "Receive buffer unavailable\n");
+ if (val & SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED)
+ dev_dbg(&sc->pdev->dev,
+ "Receive process stopped\n");
+ dc_intr_rx(sc);
+ }
+
+ if (val & SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW) {
+ dev_dbg(&sc->pdev->dev, "Transmit underflow\n");
+ dc_intr_tx_underflow(sc);
+ }
+
+ if (val & (SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE |
+ SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT |
+ SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED)) {
+ if (val & SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT)
+ dev_dbg(&sc->pdev->dev, "Transmit interrupt\n");
+ if (val & SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE)
+ dev_dbg(&sc->pdev->dev,
+ "Transmit buffer unavailable\n");
+ if (val & SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED)
+ dev_dbg(&sc->pdev->dev,
+ "Transmit process stopped\n");
+ dc_intr_tx(sc);
+ }
+ }
+
+ /* enable ethernet interrupts */
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE,
+ sc->ether.interrupt_enable_mask);
+}
+
+void dc_intr_rx(struct channel *sc)
+{
+ u32 current_read;
+ u32 error_mask, error;
+ t3e3_rx_desc_t *current_desc;
+ struct sk_buff *m, *m2;
+ unsigned rcv_len;
+
+ sc->rcv_count++; /* for the activity LED */
+
+ current_read = sc->ether.rx_ring_current_read;
+ dev_dbg(&sc->pdev->dev, "intr_rx current_read = %d\n", current_read);
+
+ /* when ethernet loopback is set, ignore framer signals */
+ if ((sc->p.loopback != SBE_2T3E3_LOOPBACK_ETHERNET) && sc->s.OOF) {
+ while (!(sc->ether.rx_ring[current_read].rdes0 &
+ SBE_2T3E3_RX_DESC_21143_OWN)) {
+ current_desc = &sc->ether.rx_ring[current_read];
+ current_desc->rdes1 &= SBE_2T3E3_RX_DESC_END_OF_RING |
+ SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED;
+ current_desc->rdes1 |= SBE_2T3E3_MTU;
+ current_desc->rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
+ current_read = (current_read + 1) % SBE_2T3E3_RX_DESC_RING_SIZE;
+ }
+ sc->ether.rx_ring_current_read = current_read;
+ return;
+ }
+
+ while (!(sc->ether.rx_ring[current_read].rdes0 &
+ SBE_2T3E3_RX_DESC_21143_OWN)) {
+ current_desc = &sc->ether.rx_ring[current_read];
+
+ dev_dbg(&sc->pdev->dev, "rdes0: %08X rdes1: %08X\n",
+ current_desc->rdes0, current_desc->rdes1);
+
+ m = sc->ether.rx_data[current_read];
+ rcv_len = (current_desc->rdes0 & SBE_2T3E3_RX_DESC_FRAME_LENGTH) >>
+ SBE_2T3E3_RX_DESC_FRAME_LENGTH_SHIFT;
+
+ dev_dbg(&sc->pdev->dev, "mbuf was received (mbuf len = %d)\n",
+ rcv_len);
+
+ switch (sc->p.crc) {
+ case SBE_2T3E3_CRC_16:
+ rcv_len -= SBE_2T3E3_CRC16_LENGTH;
+ break;
+ case SBE_2T3E3_CRC_32:
+ rcv_len -= SBE_2T3E3_CRC32_LENGTH;
+ break;
+ default:
+ break;
+ }
+
+ if (current_desc->rdes0 & SBE_2T3E3_RX_DESC_LAST_DESC) {
+
+ /* TODO: is collision possible? */
+ error_mask = SBE_2T3E3_RX_DESC_DESC_ERROR |
+ SBE_2T3E3_RX_DESC_COLLISION_SEEN |
+ SBE_2T3E3_RX_DESC_DRIBBLING_BIT;
+
+ switch (sc->p.frame_mode) {
+ case SBE_2T3E3_FRAME_MODE_HDLC:
+ error_mask |= SBE_2T3E3_RX_DESC_MII_ERROR;
+ if (sc->p.crc == SBE_2T3E3_CRC_32)
+ error_mask |= SBE_2T3E3_RX_DESC_CRC_ERROR;
+ break;
+ case SBE_2T3E3_FRAME_MODE_TRANSPARENT:
+ case SBE_2T3E3_FRAME_MODE_RAW:
+ break;
+ default:
+ error_mask = 0;
+ }
+
+ if (sc->s.LOS) {
+ error_mask &= ~(SBE_2T3E3_RX_DESC_DRIBBLING_BIT ||
+ SBE_2T3E3_RX_DESC_MII_ERROR);
+ }
+
+ error = current_desc->rdes0 & error_mask;
+ if (error) {
+ sc->s.in_errors++;
+ dev_dbg(&sc->pdev->dev,
+ "error interrupt: NO_ERROR_MESSAGE = %d\n",
+ sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES ? 1 : 0);
+
+ current_desc->rdes1 &= SBE_2T3E3_RX_DESC_END_OF_RING |
+ SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED;
+ current_desc->rdes1 |= SBE_2T3E3_MTU;
+ current_desc->rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
+
+ if (error & SBE_2T3E3_RX_DESC_DESC_ERROR) {
+ if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
+ dev_err(&sc->pdev->dev,
+ "SBE 2T3E3: descriptor error\n");
+ sc->s.in_error_desc++;
+ }
+
+ if (error & SBE_2T3E3_RX_DESC_COLLISION_SEEN) {
+ if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
+ dev_err(&sc->pdev->dev,
+ "SBE 2T3E3: collision seen\n");
+ sc->s.in_error_coll++;
+ } else {
+ if (error & SBE_2T3E3_RX_DESC_DRIBBLING_BIT) {
+ if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
+ dev_err(&sc->pdev->dev,
+ "SBE 2T3E3: dribbling bits error\n");
+ sc->s.in_error_drib++;
+ }
+
+ if (error & SBE_2T3E3_RX_DESC_CRC_ERROR) {
+ if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
+ dev_err(&sc->pdev->dev,
+ "SBE 2T3E3: crc error\n");
+ sc->s.in_error_crc++;
+ }
+ }
+
+ if (error & SBE_2T3E3_RX_DESC_MII_ERROR) {
+ if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: mii error\n");
+ sc->s.in_error_mii++;
+ }
+
+ current_read = (current_read + 1) % SBE_2T3E3_RX_DESC_RING_SIZE;
+ sc->r.flags |= SBE_2T3E3_FLAG_NO_ERROR_MESSAGES;
+ continue;
+ }
+ }
+
+ current_desc->rdes1 &= SBE_2T3E3_RX_DESC_END_OF_RING |
+ SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED;
+ current_desc->rdes1 |= SBE_2T3E3_MTU;
+
+ if (rcv_len > 1600) {
+ sc->s.in_errors++;
+ sc->s.in_dropped++;
+ if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: oversized rx: rdes0 = %08X\n",
+ current_desc->rdes0);
+ } else {
+ m2 = dev_alloc_skb(MCLBYTES);
+ if (m2 != NULL) {
+ current_desc->rdes2 = virt_to_phys(m2->data);
+ sc->ether.rx_data[current_read] = m2;
+ sc->s.in_packets++;
+ sc->s.in_bytes += rcv_len;
+ m->dev = sc->dev;
+ skb_put(m, rcv_len);
+ skb_reset_mac_header(m);
+ m->protocol = hdlc_type_trans(m, m->dev);
+ netif_rx(m);
+
+ /* good packet was received so we will show error messages again... */
+ if (sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES) {
+ dev_dbg(&sc->pdev->dev,
+ "setting ERROR_MESSAGES->0\n");
+ sc->r.flags &= ~SBE_2T3E3_FLAG_NO_ERROR_MESSAGES;
+ }
+
+ } else {
+ sc->s.in_errors++;
+ sc->s.in_dropped++;
+ }
+ }
+ current_desc->rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
+ current_read = (current_read + 1) % SBE_2T3E3_RX_DESC_RING_SIZE;
+ }
+
+ sc->ether.rx_ring_current_read = current_read;
+
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND, 0xFFFFFFFF);
+}
+
+void dc_intr_tx(struct channel *sc)
+{
+ u32 current_read, current_write;
+ u32 last_segment, error;
+ t3e3_tx_desc_t *current_desc;
+
+ spin_lock(&sc->ether.tx_lock);
+
+ current_read = sc->ether.tx_ring_current_read;
+ current_write = sc->ether.tx_ring_current_write;
+
+ while (current_read != current_write) {
+ current_desc = &sc->ether.tx_ring[current_read];
+
+ if (current_desc->tdes0 & SBE_2T3E3_RX_DESC_21143_OWN)
+ break;
+
+ dev_dbg(&sc->pdev->dev,
+ "txeof: tdes0 = %08X tdes1 = %08X\n",
+ current_desc->tdes0, current_desc->tdes1);
+
+ error = current_desc->tdes0 & (SBE_2T3E3_TX_DESC_ERROR_SUMMARY |
+ SBE_2T3E3_TX_DESC_TRANSMIT_JABBER_TIMEOUT |
+ SBE_2T3E3_TX_DESC_LOSS_OF_CARRIER |
+ SBE_2T3E3_TX_DESC_NO_CARRIER |
+ SBE_2T3E3_TX_DESC_LINK_FAIL_REPORT |
+ SBE_2T3E3_TX_DESC_UNDERFLOW_ERROR |
+ SBE_2T3E3_TX_DESC_DEFFERED);
+
+ last_segment = current_desc->tdes1 & SBE_2T3E3_TX_DESC_LAST_SEGMENT;
+
+ current_desc->tdes0 = 0;
+ current_desc->tdes1 &= SBE_2T3E3_TX_DESC_END_OF_RING |
+ SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED;
+ current_desc->tdes2 = 0;
+ sc->ether.tx_free_cnt++;
+
+ if (last_segment != SBE_2T3E3_TX_DESC_LAST_SEGMENT) {
+ current_read = (current_read + 1) % SBE_2T3E3_TX_DESC_RING_SIZE;
+ continue;
+ }
+
+
+ if (sc->ether.tx_data[current_read]) {
+ sc->s.out_packets++;
+ sc->s.out_bytes += sc->ether.tx_data[current_read]->len;
+ dev_kfree_skb_any(sc->ether.tx_data[current_read]);
+ sc->ether.tx_data[current_read] = NULL;
+ }
+
+ if (error > 0) {
+ sc->s.out_errors++;
+
+ if (error & SBE_2T3E3_TX_DESC_TRANSMIT_JABBER_TIMEOUT) {
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: transmit jabber timeout\n");
+ sc->s.out_error_jab++;
+ }
+
+ if (sc->p.loopback != SBE_2T3E3_LOOPBACK_ETHERNET) {
+ if (error & SBE_2T3E3_TX_DESC_LOSS_OF_CARRIER) {
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: loss of carrier\n");
+ sc->s.out_error_lost_carr++;
+ }
+
+ if (error & SBE_2T3E3_TX_DESC_NO_CARRIER) {
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: no carrier\n");
+ sc->s.out_error_no_carr++;
+ }
+ }
+
+ if (error & SBE_2T3E3_TX_DESC_LINK_FAIL_REPORT) {
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: link fail report\n");
+ sc->s.out_error_link_fail++;
+ }
+
+ if (error & SBE_2T3E3_TX_DESC_UNDERFLOW_ERROR) {
+ dev_err(&sc->pdev->dev, "SBE 2T3E3:"
+ " transmission underflow error\n");
+ sc->s.out_error_underflow++;
+ spin_unlock(&sc->ether.tx_lock);
+
+ dc_restart(sc);
+ return;
+ }
+
+ if (error & SBE_2T3E3_TX_DESC_DEFFERED) {
+ dev_err(&sc->pdev->dev, "SBE 2T3E3: transmission deferred\n");
+ sc->s.out_error_dereferred++;
+ }
+ }
+
+ current_read = (current_read + 1) % SBE_2T3E3_TX_DESC_RING_SIZE;
+ }
+
+ sc->ether.tx_ring_current_read = current_read;
+
+ /* Relieve flow control when the TX queue is drained at least half way */
+ if (sc->ether.tx_full &&
+ (sc->ether.tx_free_cnt >= (SBE_2T3E3_TX_DESC_RING_SIZE / 2))) {
+ sc->ether.tx_full = 0;
+ netif_wake_queue(sc->dev);
+ }
+ spin_unlock(&sc->ether.tx_lock);
+}
+
+
+void dc_intr_tx_underflow(struct channel *sc)
+{
+ u32 val;
+
+ dc_transmitter_onoff(sc, SBE_2T3E3_OFF);
+
+ val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE);
+ dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS);
+
+ switch (val & SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS) {
+ case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_1:
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_2);
+ break;
+ case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_2:
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_3);
+ break;
+ case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_3:
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_4);
+ break;
+ case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_4:
+ default:
+ dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
+ SBE_2T3E3_21143_VAL_STORE_AND_FORWARD);
+ break;
+ }
+
+ dc_transmitter_onoff(sc, SBE_2T3E3_ON);
+}
+
+
+
+
+void exar7250_intr(struct channel *sc)
+{
+ u32 status, old_OOF;
+
+#if 0
+ /* disable interrupts */
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE, 0);
+#endif
+
+ old_OOF = sc->s.OOF;
+
+ status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS);
+ dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt! (REG[0x05] = %02X)\n", status);
+
+ switch (sc->p.frame_type) {
+ case SBE_2T3E3_FRAME_TYPE_E3_G751:
+ case SBE_2T3E3_FRAME_TYPE_E3_G832:
+ exar7250_E3_intr(sc, status);
+ break;
+
+ case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
+ case SBE_2T3E3_FRAME_TYPE_T3_M13:
+ exar7250_T3_intr(sc, status);
+ break;
+
+ default:
+ break;
+ }
+
+ if (sc->s.OOF != old_OOF) {
+ if (sc->s.OOF) {
+ if (sc->p.loopback == SBE_2T3E3_LOOPBACK_NONE) {
+ dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Disabling eth interrupts\n");
+ /* turn off ethernet interrupts */
+ dc_stop_intr(sc);
+ }
+ } else if (sc->r.flags & SBE_2T3E3_FLAG_NETWORK_UP) {
+ dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Enabling eth interrupts\n");
+ /* start interrupts */
+ sc->s.OOF = 1;
+ dc_intr_rx(sc);
+ sc->s.OOF = 0;
+ if (sc->p.receiver_on) {
+ dc_receiver_onoff(sc, SBE_2T3E3_OFF);
+ dc_receiver_onoff(sc, SBE_2T3E3_ON);
+ }
+ dc_start_intr(sc);
+ }
+ }
+#if 0
+ /* reenable interrupts */
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE,
+ SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_ENABLE
+ );
+#endif
+}
+
+
+void exar7250_T3_intr(struct channel *sc, u32 block_status)
+{
+ u32 status, result;
+
+ if (block_status & SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_STATUS) {
+ status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS);
+
+ if (status) {
+ dev_dbg(&sc->pdev->dev,
+ "Framer interrupt T3 RX (REG[0x13] = %02X)\n",
+ status);
+
+ result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
+
+#if 0
+ if (status & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_STATUS) {
+ dev_dbg(&sc->pdev->dev,
+ "Framer interrupt T3: LOS\n");
+ sc->s.LOS = result & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS ? 1 : 0;
+
+ }
+#else
+ cpld_LOS_update(sc);
+#endif
+ if (status & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_STATUS) {
+ sc->s.OOF = result & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
+ dev_dbg(&sc->pdev->dev,
+ "Framer interrupt T3: OOF (%d)\n",
+ sc->s.OOF);
+ }
+
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE,
+ SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE);
+#if 0
+ SBE_2T3E3_FRAMER_VAL_T3_RX_CP_BIT_ERROR_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_AIS_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_FERF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_AIC_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_P_BIT_INTERRUPT_ENABLE
+#endif
+ }
+
+ status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS);
+ if (status) {
+ dev_dbg(&sc->pdev->dev,
+ "Framer interrupt T3 RX (REG[0x17] = %02X)\n",
+ status);
+#if 0
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS,
+ SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_ENABLE
+ );
+#endif
+ }
+
+ status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL);
+ if (status)
+ dev_dbg(&sc->pdev->dev,
+ "Framer interrupt T3 RX (REG[0x18] = %02X)\n",
+ status);
+ }
+
+
+ if (block_status & SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_STATUS) {
+ status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS);
+ dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt T3 TX (REG[0x31] = %02X)\n",
+ status);
+
+ status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS);
+ dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt T3 TX (REG[0x34] = %02X)\n",
+ status);
+ }
+}
+
+
+void exar7250_E3_intr(struct channel *sc, u32 block_status)
+{
+ u32 status, result;
+
+ if (block_status & SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_STATUS) {
+ status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1);
+
+ if (status) {
+ dev_dbg(&sc->pdev->dev,
+ "Framer interrupt E3 RX (REG[0x14] = %02X)\n",
+ status);
+
+ result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
+
+#if 0
+ if (status & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_STATUS) {
+ dev_dbg(&sc->pdev->dev,
+ "Framer interrupt E3: LOS\n");
+ sc->s.LOS = result & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS ? 1 : 0;
+ }
+#else
+ cpld_LOS_update(sc);
+#endif
+ if (status & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_STATUS) {
+ sc->s.OOF = result & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
+ dev_dbg(&sc->pdev->dev,
+ "Framer interrupt E3: OOF (%d)\n",
+ sc->s.OOF);
+ }
+
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1,
+ SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE
+ );
+#if 0
+ SBE_2T3E3_FRAMER_VAL_E3_RX_COFA_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_AIS_INTERRUPT_ENABLE
+#endif
+ }
+
+ status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2);
+ if (status) {
+ dev_dbg(&sc->pdev->dev,
+ "Framer interrupt E3 RX (REG[0x15] = %02X)\n",
+ status);
+
+#if 0
+ exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2,
+ SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_ENABLE |
+ SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_ENABLE);
+#endif
+ }
+
+ }
+
+ if (block_status & SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_STATUS) {
+ status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS);
+ dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt E3 TX (REG[0x34] = %02X)\n",
+ status);
+ }
+}
diff --git a/drivers/staging/sbe-2t3e3/io.c b/drivers/staging/sbe-2t3e3/io.c
new file mode 100644
index 0000000..b458ff0
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/io.c
@@ -0,0 +1,352 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include <linux/ip.h>
+#include <asm/system.h>
+#include "2t3e3.h"
+#include "ctrl.h"
+
+/* All access to registers done via the 21143 on port 0 must be
+ * protected via the card->bootrom_lock. */
+
+/* priviate define to be used here only - must be protected by card->bootrom_lock */
+#define cpld_write_nolock(channel, reg, val) \
+ bootrom_write((channel), CPLD_MAP_REG(reg, channel), val)
+
+u32 cpld_read(struct channel *channel, u32 reg)
+{
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&channel->card->bootrom_lock, flags);
+ val = bootrom_read((channel), CPLD_MAP_REG(reg, channel));
+ spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
+ return val;
+}
+
+/****************************************
+ * Access via BootROM port
+ ****************************************/
+
+u32 bootrom_read(struct channel *channel, u32 reg)
+{
+ unsigned long addr = channel->card->bootrom_addr;
+ u32 result;
+
+ /* select BootROM address */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_PROGRAMMING_ADDRESS, reg & 0x3FFFF);
+
+ /* select reading from BootROM */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_READ_OPERATION |
+ SBE_2T3E3_21143_VAL_BOOT_ROM_SELECT);
+
+ udelay(2); /* 20 PCI cycles */
+
+ /* read from BootROM */
+ result = dc_read(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT) & 0xff;
+
+ /* reset CSR9 */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
+
+ return result;
+}
+
+void bootrom_write(struct channel *channel, u32 reg, u32 val)
+{
+ unsigned long addr = channel->card->bootrom_addr;
+
+ /* select BootROM address */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_PROGRAMMING_ADDRESS, reg & 0x3FFFF);
+
+ /* select writting to BootROM */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_WRITE_OPERATION |
+ SBE_2T3E3_21143_VAL_BOOT_ROM_SELECT |
+ (val & 0xff));
+
+ udelay(2); /* 20 PCI cycles */
+
+ /* reset CSR9 */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
+}
+
+
+/****************************************
+ * Access via Serial I/O port
+ ****************************************/
+
+static u32 serialrom_read_bit(struct channel *channel)
+{
+ unsigned long addr = channel->card->bootrom_addr;
+ u32 bit;
+
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_READ_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CLOCK |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock high */
+
+ bit = (dc_read(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT) &
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_DATA_OUT) > 0 ? 1 : 0;
+
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_READ_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
+
+ return bit;
+}
+
+static void serialrom_write_bit(struct channel *channel, u32 bit)
+{
+ unsigned long addr = channel->card->bootrom_addr;
+ u32 lastbit = -1;
+
+ bit &= 1;
+
+ if (bit != lastbit) {
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_WRITE_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT |
+ (bit << 2)); /* clock low */
+
+ lastbit = bit;
+ }
+
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_WRITE_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CLOCK |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT |
+ (bit << 2)); /* clock high */
+
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_WRITE_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT |
+ (bit << 2)); /* clock low */
+}
+
+/****************************************
+ * Access to SerialROM (eeprom)
+ ****************************************/
+
+u32 t3e3_eeprom_read_word(struct channel *channel, u32 address)
+{
+ unsigned long addr = channel->card->bootrom_addr;
+ u32 i, val;
+ unsigned long flags;
+
+ address &= 0x3f;
+
+ spin_lock_irqsave(&channel->card->bootrom_lock, flags);
+
+ /* select correct Serial Chip */
+ cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT,
+ SBE_2T3E3_CPLD_VAL_EEPROM_SELECT);
+
+ /* select reading from Serial I/O Bus */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_READ_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
+
+ /* select read operation */
+ serialrom_write_bit(channel, 0);
+ serialrom_write_bit(channel, 1);
+ serialrom_write_bit(channel, 1);
+ serialrom_write_bit(channel, 0);
+
+ for (i = 0x20; i; i >>= 1)
+ serialrom_write_bit(channel, address & i ? 1 : 0);
+
+ val = 0;
+ for (i = 0x8000; i; i >>= 1)
+ val |= (serialrom_read_bit(channel) ? i : 0);
+
+ /* Reset 21143's CSR9 */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_READ_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
+
+ /* Unselect Serial Chip */
+ cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, 0);
+
+ spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
+
+ return ntohs(val);
+}
+
+
+/****************************************
+ * Access to Framer
+ ****************************************/
+
+u32 exar7250_read(struct channel *channel, u32 reg)
+{
+ u32 result;
+ unsigned long flags;
+
+#if 0
+ switch (reg) {
+ case SBE_2T3E3_FRAMER_REG_OPERATING_MODE:
+ return channel->framer_regs[reg];
+ break;
+ default:
+ }
+#endif
+
+ spin_lock_irqsave(&channel->card->bootrom_lock, flags);
+
+ result = bootrom_read(channel, cpld_reg_map[SBE_2T3E3_CPLD_REG_FRAMER_BASE_ADDRESS]
+ [channel->h.slot] + (t3e3_framer_reg_map[reg] << 2));
+
+ spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
+
+ return result;
+}
+
+void exar7250_write(struct channel *channel, u32 reg, u32 val)
+{
+ unsigned long flags;
+
+ val &= 0xff;
+ channel->framer_regs[reg] = val;
+
+ spin_lock_irqsave(&channel->card->bootrom_lock, flags);
+
+ bootrom_write(channel, cpld_reg_map[SBE_2T3E3_CPLD_REG_FRAMER_BASE_ADDRESS]
+ [channel->h.slot] + (t3e3_framer_reg_map[reg] << 2), val);
+
+ spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
+}
+
+
+/****************************************
+ * Access to LIU
+ ****************************************/
+
+u32 exar7300_read(struct channel *channel, u32 reg)
+{
+ unsigned long addr = channel->card->bootrom_addr, flags;
+ u32 i, val;
+
+#if 0
+ switch (reg) {
+ case SBE_2T3E3_LIU_REG_REG1:
+ case SBE_2T3E3_LIU_REG_REG2:
+ case SBE_2T3E3_LIU_REG_REG3:
+ case SBE_2T3E3_LIU_REG_REG4:
+ return channel->liu_regs[reg];
+ break;
+ default:
+ }
+#endif
+
+ /* select correct Serial Chip */
+
+ spin_lock_irqsave(&channel->card->bootrom_lock, flags);
+
+ cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT,
+ cpld_val_map[SBE_2T3E3_CPLD_VAL_LIU_SELECT][channel->h.slot]);
+
+ /* select reading from Serial I/O Bus */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_READ_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
+
+ /* select read operation */
+ serialrom_write_bit(channel, 1);
+
+ /* Exar7300 register address is 4 bit long */
+ reg = t3e3_liu_reg_map[reg];
+ for (i = 0; i < 4; i++, reg >>= 1) /* 4 bits of SerialROM address */
+ serialrom_write_bit(channel, reg & 1);
+ for (i = 0; i < 3; i++) /* remaining 3 bits of SerialROM address */
+ serialrom_write_bit(channel, 0);
+
+ val = 0; /* Exar7300 register value is 5 bit long */
+ for (i = 0; i < 8; i++) /* 8 bits of SerialROM value */
+ val += (serialrom_read_bit(channel) << i);
+
+ /* Reset 21143's CSR9 */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_READ_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
+
+ /* Unselect Serial Chip */
+ cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, 0);
+
+ spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
+
+ return val;
+}
+
+void exar7300_write(struct channel *channel, u32 reg, u32 val)
+{
+ unsigned long addr = channel->card->bootrom_addr, flags;
+ u32 i;
+
+ channel->liu_regs[reg] = val;
+
+ /* select correct Serial Chip */
+
+ spin_lock_irqsave(&channel->card->bootrom_lock, flags);
+
+ cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT,
+ cpld_val_map[SBE_2T3E3_CPLD_VAL_LIU_SELECT][channel->h.slot]);
+
+ /* select writting to Serial I/O Bus */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_WRITE_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
+
+ /* select write operation */
+ serialrom_write_bit(channel, 0);
+
+ /* Exar7300 register address is 4 bit long */
+ reg = t3e3_liu_reg_map[reg];
+ for (i = 0; i < 4; i++) { /* 4 bits */
+ serialrom_write_bit(channel, reg & 1);
+ reg >>= 1;
+ }
+ for (i = 0; i < 3; i++) /* remaining 3 bits of SerialROM address */
+ serialrom_write_bit(channel, 0);
+
+ /* Exar7300 register value is 5 bit long */
+ for (i = 0; i < 5; i++) {
+ serialrom_write_bit(channel, val & 1);
+ val >>= 1;
+ }
+ for (i = 0; i < 3; i++) /* remaining 3 bits of SerialROM value */
+ serialrom_write_bit(channel, 0);
+
+ /* Reset 21143_CSR9 */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT,
+ SBE_2T3E3_21143_VAL_WRITE_OPERATION |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_SELECT |
+ SBE_2T3E3_21143_VAL_SERIAL_ROM_CHIP_SELECT); /* clock low */
+ dc_write(addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, 0);
+
+ /* Unselect Serial Chip */
+ cpld_write_nolock(channel, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, 0);
+
+ spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
+}
diff --git a/drivers/staging/sbe-2t3e3/main.c b/drivers/staging/sbe-2t3e3/main.c
new file mode 100644
index 0000000..f3dbef6
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/main.c
@@ -0,0 +1,171 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include "2t3e3.h"
+
+void t3e3_init(struct channel *sc)
+{
+ cpld_init(sc);
+ dc_reset(sc);
+ dc_init(sc);
+ exar7250_init(sc);
+ exar7300_init(sc);
+}
+
+int t3e3_if_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct channel *sc = dev_to_priv(dev);
+ u32 current_write, last_write;
+ unsigned long flags;
+ struct sk_buff *skb2;
+
+ if (skb == NULL) {
+ sc->s.out_errors++;
+ return 0;
+ }
+
+ if (sc->p.transmitter_on != SBE_2T3E3_ON) {
+ sc->s.out_errors++;
+ sc->s.out_dropped++;
+ dev_kfree_skb_any(skb);
+ return 0;
+ }
+
+ if (sc->s.OOF && sc->p.loopback == SBE_2T3E3_LOOPBACK_NONE) {
+ sc->s.out_dropped++;
+ dev_kfree_skb_any(skb);
+ return 0;
+ }
+
+ spin_lock_irqsave(&sc->ether.tx_lock, flags);
+
+ current_write = sc->ether.tx_ring_current_write;
+ for (skb2 = skb; skb2 != NULL; skb2 = NULL) {
+ if (skb2->len) {
+ if ((sc->ether.tx_ring[current_write].tdes1 &
+ SBE_2T3E3_TX_DESC_BUFFER_1_SIZE) > 0)
+ break;
+ current_write = (current_write + 1) % SBE_2T3E3_TX_DESC_RING_SIZE;
+ /*
+ * Leave at least 1 tx desc free so that dc_intr_tx() can
+ * identify empty list
+ */
+ if (current_write == sc->ether.tx_ring_current_read)
+ break;
+ }
+ }
+ if (skb2 != NULL) {
+ netif_stop_queue(sc->dev);
+ sc->ether.tx_full = 1;
+ dev_dbg(&sc->pdev->dev, "SBE 2T3E3: out of descriptors\n");
+ spin_unlock_irqrestore(&sc->ether.tx_lock, flags);
+ return NETDEV_TX_BUSY;
+ }
+
+ current_write = last_write = sc->ether.tx_ring_current_write;
+ dev_dbg(&sc->pdev->dev, "sending mbuf (current_write = %d)\n",
+ current_write);
+
+ for (skb2 = skb; skb2 != NULL; skb2 = NULL) {
+ if (skb2->len) {
+ dev_dbg(&sc->pdev->dev,
+ "sending mbuf (len = %d, next = %p)\n",
+ skb2->len, NULL);
+
+ sc->ether.tx_free_cnt--;
+ sc->ether.tx_ring[current_write].tdes0 = 0;
+ sc->ether.tx_ring[current_write].tdes1 &=
+ SBE_2T3E3_TX_DESC_END_OF_RING |
+ SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED;
+/* DISABLE_PADDING sometimes gets lost somehow, hands off... */
+ sc->ether.tx_ring[current_write].tdes1 |=
+ SBE_2T3E3_TX_DESC_DISABLE_PADDING | skb2->len;
+
+ if (current_write == sc->ether.tx_ring_current_write) {
+ sc->ether.tx_ring[current_write].tdes1 |=
+ SBE_2T3E3_TX_DESC_FIRST_SEGMENT;
+ } else {
+ sc->ether.tx_ring[current_write].tdes0 =
+ SBE_2T3E3_TX_DESC_21143_OWN;
+ }
+
+ sc->ether.tx_ring[current_write].tdes2 = virt_to_phys(skb2->data);
+ sc->ether.tx_data[current_write] = NULL;
+
+ last_write = current_write;
+ current_write = (current_write + 1) % SBE_2T3E3_TX_DESC_RING_SIZE;
+ }
+ }
+
+ sc->ether.tx_data[last_write] = skb;
+ sc->ether.tx_ring[last_write].tdes1 |=
+ SBE_2T3E3_TX_DESC_LAST_SEGMENT |
+ SBE_2T3E3_TX_DESC_INTERRUPT_ON_COMPLETION;
+ sc->ether.tx_ring[sc->ether.tx_ring_current_write].tdes0 |=
+ SBE_2T3E3_TX_DESC_21143_OWN;
+ sc->ether.tx_ring_current_write = current_write;
+
+ dev_dbg(&sc->pdev->dev, "txput: tdes0 = %08X tdes1 = %08X\n",
+ sc->ether.tx_ring[last_write].tdes0,
+ sc->ether.tx_ring[last_write].tdes1);
+
+ dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_POLL_DEMAND,
+ 0xffffffff);
+
+ spin_unlock_irqrestore(&sc->ether.tx_lock, flags);
+ return 0;
+}
+
+
+void t3e3_read_card_serial_number(struct channel *sc)
+{
+ u32 i;
+
+ for (i = 0; i < 3; i++)
+ sc->ether.card_serial_number[i] = t3e3_eeprom_read_word(sc, 10 + i);
+
+ printk(KERN_INFO "SBE wanPMC-2T3E3 serial number: %04X%04X%04X\n",
+ sc->ether.card_serial_number[0], sc->ether.card_serial_number[1],
+ sc->ether.card_serial_number[2]);
+}
+
+/*
+ bit 0 led1 (green)
+ bit 1 led1 (yellow)
+
+ bit 2 led2 (green)
+ bit 3 led2 (yellow)
+
+ bit 4 led3 (green)
+ bit 5 led3 (yellow)
+
+ bit 6 led4 (green)
+ bit 7 led4 (yellow)
+*/
+
+void update_led(struct channel *sc, int blinker)
+{
+ int leds;
+ if (sc->s.LOS)
+ leds = 0; /* led1 = off */
+ else if (sc->s.OOF)
+ leds = 2; /* led1 = yellow */
+ else if ((blinker & 1) && sc->rcv_count) {
+ leds = 0; /* led1 = off */
+ sc->rcv_count = 0;
+ } else
+ leds = 1; /* led1 = green */
+ cpld_write(sc, SBE_2T3E3_CPLD_REG_LEDR, leds);
+ sc->leds = leds;
+}
diff --git a/drivers/staging/sbe-2t3e3/maps.c b/drivers/staging/sbe-2t3e3/maps.c
new file mode 100644
index 0000000..7084fbe
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/maps.c
@@ -0,0 +1,104 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include <linux/kernel.h>
+#include "2t3e3.h"
+
+const u32 cpld_reg_map[][2] =
+{
+ { 0x0000, 0x0080 }, /* 0 - Port Control Register A (PCRA) */
+ { 0x0004, 0x0084 }, /* 1 - Port Control Register B (PCRB) */
+ { 0x0008, 0x0088 }, /* 2 - LCV Count Register (PLCR) */
+ { 0x000c, 0x008c }, /* 3 - LCV Threshold register (PLTR) */
+ { 0x0010, 0x0090 }, /* 4 - Payload Fill Register (PPFR) */
+ { 0x0200, 0x0200 }, /* 5 - Board ID / FPGA Programming Status Register */
+ { 0x0204, 0x0204 }, /* 6 - FPGA Version Register */
+ { 0x0800, 0x1000 }, /* 7 - Framer Registers Base Address */
+ { 0x2000, 0x2000 }, /* 8 - Serial Chip Select Register */
+ { 0x2004, 0x2004 }, /* 9 - Static Reset Register */
+ { 0x2008, 0x2008 }, /* 10 - Pulse Reset Register */
+ { 0x200c, 0x200c }, /* 11 - FPGA Reconfiguration Register */
+ { 0x2010, 0x2014 }, /* 12 - LED Register (LEDR) */
+ { 0x2018, 0x201c }, /* 13 - LIU Control and Status Register (PISCR) */
+ { 0x2020, 0x2024 }, /* 14 - Interrupt Enable Register (PIER) */
+ { 0x0068, 0x00e8 }, /* 15 - Port Control Register C (PCRC) */
+ { 0x006c, 0x00ec }, /* 16 - Port Bandwidth Start (PBWF) */
+ { 0x0070, 0x00f0 }, /* 17 - Port Bandwidth Stop (PBWL) */
+};
+
+const u32 cpld_val_map[][2] =
+{
+ { 0x01, 0x02 }, /* LIU1 / LIU2 select for Serial Chip Select */
+ { 0x04, 0x08 }, /* DAC1 / DAC2 select for Serial Chip Select */
+ { 0x00, 0x04 }, /* LOOP1 / LOOP2 - select of loop timing source */
+ { 0x01, 0x02 } /* PORT1 / PORT2 - select LIU and Framer for reset */
+};
+
+const u32 t3e3_framer_reg_map[] = {
+ 0x00, /* 0 - OPERATING_MODE */
+ 0x01, /* 1 - IO_CONTROL */
+ 0x04, /* 2 - BLOCK_INTERRUPT_ENABLE */
+ 0x05, /* 3 - BLOCK_INTERRUPT_STATUS */
+ 0x10, /* 4 - T3_RX_CONFIGURATION_STATUS, E3_RX_CONFIGURATION_STATUS_1 */
+ 0x11, /* 5 - T3_RX_STATUS, E3_RX_CONFIGURATION_STATUS_2 */
+ 0x12, /* 6 - T3_RX_INTERRUPT_ENABLE, E3_RX_INTERRUPT_ENABLE_1 */
+ 0x13, /* 7 - T3_RX_INTERRUPT_STATUS, E3_RX_INTERRUPT_ENABLE_2 */
+ 0x14, /* 8 - T3_RX_SYNC_DETECT_ENABLE, E3_RX_INTERRUPT_STATUS_1 */
+ 0x15, /* 9 - E3_RX_INTERRUPT_STATUS_2 */
+ 0x16, /* 10 - T3_RX_FEAC */
+ 0x17, /* 11 - T3_RX_FEAC_INTERRUPT_ENABLE_STATUS */
+ 0x18, /* 12 - T3_RX_LAPD_CONTROL, E3_RX_LAPD_CONTROL */
+ 0x19, /* 13 - T3_RX_LAPD_STATUS, E3_RX_LAPD_STATUS */
+ 0x1a, /* 14 - E3_RX_NR_BYTE, E3_RX_SERVICE_BITS */
+ 0x1b, /* 15 - E3_RX_GC_BYTE */
+ 0x30, /* 16 - T3_TX_CONFIGURATION, E3_TX_CONFIGURATION */
+ 0x31, /* 17 - T3_TX_FEAC_CONFIGURATION_STATUS */
+ 0x32, /* 18 - T3_TX_FEAC */
+ 0x33, /* 19 - T3_TX_LAPD_CONFIGURATION, E3_TX_LAPD_CONFIGURATION */
+ 0x34, /* 20 - T3_TX_LAPD_STATUS, E3_TX_LAPD_STATUS_INTERRUPT */
+ 0x35, /* 21 - T3_TX_MBIT_MASK, E3_TX_GC_BYTE, E3_TX_SERVICE_BITS */
+ 0x36, /* 22 - T3_TX_FBIT_MASK, E3_TX_MA_BYTE */
+ 0x37, /* 23 - T3_TX_FBIT_MASK_2, E3_TX_NR_BYTE */
+ 0x38, /* 24 - T3_TX_FBIT_MASK_3 */
+ 0x48, /* 25 - E3_TX_FA1_ERROR_MASK, E3_TX_FAS_ERROR_MASK_UPPER */
+ 0x49, /* 26 - E3_TX_FA2_ERROR_MASK, E3_TX_FAS_ERROR_MASK_LOWER */
+ 0x4a, /* 27 - E3_TX_BIP8_MASK, E3_TX_BIP4_MASK */
+ 0x50, /* 28 - PMON_LCV_EVENT_COUNT_MSB */
+ 0x51, /* 29 - PMON_LCV_EVENT_COUNT_LSB */
+ 0x52, /* 30 - PMON_FRAMING_BIT_ERROR_EVENT_COUNT_MSB */
+ 0x53, /* 31 - PMON_FRAMING_BIT_ERROR_EVENT_COUNT_LSB */
+ 0x54, /* 32 - PMON_PARITY_ERROR_EVENT_COUNT_MSB */
+ 0x55, /* 33 - PMON_PARITY_ERROR_EVENT_COUNT_LSB */
+ 0x56, /* 34 - PMON_FEBE_EVENT_COUNT_MSB */
+ 0x57, /* 35 - PMON_FEBE_EVENT_COUNT_LSB */
+ 0x58, /* 36 - PMON_CP_BIT_ERROR_EVENT_COUNT_MSB */
+ 0x59, /* 37 - PMON_CP_BIT_ERROR_EVENT_COUNT_LSB */
+ 0x6c, /* 38 - PMON_HOLDING_REGISTER */
+ 0x6d, /* 39 - ONE_SECOND_ERROR_STATUS */
+ 0x6e, /* 40 - LCV_ONE_SECOND_ACCUMULATOR_MSB */
+ 0x6f, /* 41 - LCV_ONE_SECOND_ACCUMULATOR_LSB */
+ 0x70, /* 42 - FRAME_PARITY_ERROR_ONE_SECOND_ACCUMULATOR_MSB */
+ 0x71, /* 43 - FRAME_PARITY_ERROR_ONE_SECOND_ACCUMULATOR_LSB */
+ 0x72, /* 44 - FRAME_CP_BIT_ERROR_ONE_SECOND_ACCUMULATOR_MSB */
+ 0x73, /* 45 - FRAME_CP_BIT_ERROR_ONE_SECOND_ACCUMULATOR_LSB */
+ 0x80, /* 46 - LINE_INTERFACE_DRIVE */
+ 0x81 /* 47 - LINE_INTERFACE_SCAN */
+};
+
+const u32 t3e3_liu_reg_map[] =
+{
+ 0x00, /* REG0 */
+ 0x01, /* REG1 */
+ 0x02, /* REG2 */
+ 0x03, /* REG3 */
+ 0x04 /* REG4 */
+};
diff --git a/drivers/staging/sbe-2t3e3/module.c b/drivers/staging/sbe-2t3e3/module.c
new file mode 100644
index 0000000..e87fe81
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/module.c
@@ -0,0 +1,210 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/hdlc.h>
+#include <linux/if_arp.h>
+#include <linux/interrupt.h>
+#include "2t3e3.h"
+
+static void check_leds(unsigned long arg)
+{
+ struct card *card = (struct card *)arg;
+ struct channel *channel0 = &card->channels[0];
+ static int blinker;
+
+ update_led(channel0, ++blinker);
+ if (has_two_ports(channel0->pdev))
+ update_led(&card->channels[1], blinker);
+
+ card->timer.expires = jiffies + HZ / 10;
+ add_timer(&card->timer);
+}
+
+static void t3e3_remove_channel(struct channel *channel)
+{
+ struct pci_dev *pdev = channel->pdev;
+ struct net_device *dev = channel->dev;
+
+ /* system hangs if board asserts irq while module is unloaded */
+ cpld_stop_intr(channel);
+ free_irq(dev->irq, dev);
+ dc_drop_descriptor_list(channel);
+ unregister_hdlc_device(dev);
+ free_netdev(dev);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
+}
+
+static int __devinit t3e3_init_channel(struct channel *channel, struct pci_dev *pdev, struct card *card)
+{
+ struct net_device *dev;
+ unsigned int val;
+ int err;
+
+ err = pci_enable_device(pdev);
+ if (err)
+ return err;
+
+ err = pci_request_regions(pdev, "SBE 2T3E3");
+ if (err)
+ goto disable;
+
+ dev = alloc_hdlcdev(channel);
+ if (!dev) {
+ printk(KERN_ERR "SBE 2T3E3" ": Out of memory\n");
+ goto free_regions;
+ }
+
+ t3e3_sc_init(channel);
+ dev_to_priv(dev) = channel;
+
+ channel->pdev = pdev;
+ channel->dev = dev;
+ channel->card = card;
+ channel->addr = pci_resource_start(pdev, 0);
+ if (pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P1)
+ channel->h.slot = 1;
+ else
+ channel->h.slot = 0;
+
+ if (setup_device(dev, channel))
+ goto free_regions;
+
+ pci_read_config_dword(channel->pdev, 0x40, &val); /* mask sleep mode */
+ pci_write_config_dword(channel->pdev, 0x40, val & 0x3FFFFFFF);
+
+ pci_read_config_byte(channel->pdev, PCI_CACHE_LINE_SIZE, &channel->h.cache_size);
+ pci_read_config_dword(channel->pdev, PCI_COMMAND, &channel->h.command);
+ t3e3_init(channel);
+
+ if (request_irq(dev->irq, &t3e3_intr, IRQF_SHARED, dev->name, dev)) {
+ printk(KERN_WARNING "%s: could not get irq: %d\n", dev->name, dev->irq);
+ goto free_regions;
+ }
+
+ pci_set_drvdata(pdev, channel);
+ return 0;
+
+free_regions:
+ pci_release_regions(pdev);
+disable:
+ pci_disable_device(pdev);
+ return err;
+}
+
+static void __devexit t3e3_remove_card(struct pci_dev *pdev)
+{
+ struct channel *channel0 = pci_get_drvdata(pdev);
+ struct card *card = channel0->card;
+
+ del_timer(&card->timer);
+ if (has_two_ports(channel0->pdev)) {
+ t3e3_remove_channel(&card->channels[1]);
+ pci_dev_put(card->channels[1].pdev);
+ }
+ t3e3_remove_channel(channel0);
+ kfree(card);
+}
+
+static int __devinit t3e3_init_card(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ /* pdev points to channel #0 */
+ struct pci_dev *pdev1 = NULL;
+ struct card *card;
+ int channels = 1, err;
+
+ if (has_two_ports(pdev)) {
+ while ((pdev1 = pci_get_subsys(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
+ PCI_VENDOR_ID_SBE, PCI_SUBDEVICE_ID_SBE_2T3E3_P1,
+ pdev1)))
+ if (pdev1->bus == pdev->bus &&
+ pdev1->devfn == pdev->devfn + 8 /* next device on the same bus */)
+ break; /* found the second channel */
+
+ if (!pdev1) {
+ printk(KERN_ERR "SBE 2T3E3" ": Can't find the second channel\n");
+ return -EFAULT;
+ }
+ channels = 2;
+ /* holds the reference for pdev1 */
+ }
+
+ card = kzalloc(sizeof(struct card) + channels * sizeof(struct channel), GFP_KERNEL);
+ if (!card) {
+ printk(KERN_ERR "SBE 2T3E3" ": Out of memory\n");
+ return -ENOBUFS;
+ }
+
+ spin_lock_init(&card->bootrom_lock);
+ card->bootrom_addr = pci_resource_start(pdev, 0);
+
+ err = t3e3_init_channel(&card->channels[0], pdev, card);
+ if (err)
+ goto free_card;
+
+ if (channels == 2) {
+ err = t3e3_init_channel(&card->channels[1], pdev1, card);
+ if (err) {
+ t3e3_remove_channel(&card->channels[0]);
+ goto free_card;
+ }
+ }
+
+ /* start LED timer */
+ init_timer(&card->timer);
+ card->timer.function = check_leds;
+ card->timer.expires = jiffies + HZ / 10;
+ card->timer.data = (unsigned long)card;
+ add_timer(&card->timer);
+ return 0;
+
+free_card:
+ kfree(card);
+ return err;
+}
+
+static struct pci_device_id t3e3_pci_tbl[] __devinitdata = {
+ { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
+ PCI_VENDOR_ID_SBE, PCI_SUBDEVICE_ID_SBE_T3E3, 0, 0, 0 },
+ { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
+ PCI_VENDOR_ID_SBE, PCI_SUBDEVICE_ID_SBE_2T3E3_P0, 0, 0, 0 },
+ /* channel 1 will be initialized after channel 0 */
+ { 0, }
+};
+
+static struct pci_driver t3e3_pci_driver = {
+ .name = "SBE T3E3",
+ .id_table = t3e3_pci_tbl,
+ .probe = t3e3_init_card,
+ .remove = t3e3_remove_card,
+};
+
+static int __init t3e3_init_module(void)
+{
+ return pci_register_driver(&t3e3_pci_driver);
+}
+
+static void __exit t3e3_cleanup_module(void)
+{
+ pci_unregister_driver(&t3e3_pci_driver);
+}
+
+module_init(t3e3_init_module);
+module_exit(t3e3_cleanup_module);
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(pci, t3e3_pci_tbl);
diff --git a/drivers/staging/sbe-2t3e3/netdev.c b/drivers/staging/sbe-2t3e3/netdev.c
new file mode 100644
index 0000000..c7b5e8b
--- /dev/null
+++ b/drivers/staging/sbe-2t3e3/netdev.c
@@ -0,0 +1,142 @@
+/*
+ * SBE 2T3E3 synchronous serial card driver for Linux
+ *
+ * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This code is based on a driver written by SBE Inc.
+ */
+
+#include <linux/capability.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/hdlc.h>
+#include <linux/if_arp.h>
+#include <linux/interrupt.h>
+#include "2t3e3.h"
+
+int t3e3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ struct channel *sc = dev_to_priv(dev);
+ int cmd_2t3e3, len, rlen;
+ t3e3_param_t param;
+ t3e3_resp_t resp;
+ void *data = ifr->ifr_data + sizeof(cmd_2t3e3) + sizeof(len);
+
+ if (cmd == SIOCWANDEV)
+ return hdlc_ioctl(dev, ifr, cmd);
+ if (!capable(CAP_SYS_ADMIN))
+ return -EPERM;
+ if (cmd != SIOCDEVPRIVATE + 15)
+ return -EINVAL;
+
+ if (copy_from_user(&cmd_2t3e3, ifr->ifr_data, sizeof(cmd_2t3e3)))
+ return -EFAULT;
+ if (copy_from_user(&len, ifr->ifr_data + sizeof(cmd_2t3e3), sizeof(len)))
+ return -EFAULT;
+
+ if (len > sizeof(param))
+ return -EFAULT;
+
+ if (len)
+ if (copy_from_user(¶m, data, len))
+ return -EFAULT;
+
+ t3e3_if_config(sc, cmd_2t3e3, (char *)¶m, &resp, &rlen);
+
+ if (rlen)
+ if (copy_to_user(data, &resp, rlen))
+ return -EFAULT;
+
+ return 0;
+}
+
+static struct net_device_stats* t3e3_get_stats(struct net_device *dev)
+{
+ struct net_device_stats *nstats = &dev->stats;
+ struct channel *sc = dev_to_priv(dev);
+ t3e3_stats_t *stats = &sc->s;
+
+ memset(nstats, 0, sizeof(struct net_device_stats));
+ nstats->rx_packets = stats->in_packets;
+ nstats->tx_packets = stats->out_packets;
+ nstats->rx_bytes = stats->in_bytes;
+ nstats->tx_bytes = stats->out_bytes;
+
+ nstats->rx_errors = stats->in_errors;
+ nstats->tx_errors = stats->out_errors;
+ nstats->rx_crc_errors = stats->in_error_crc;
+
+
+ nstats->rx_dropped = stats->in_dropped;
+ nstats->tx_dropped = stats->out_dropped;
+ nstats->tx_carrier_errors = stats->out_error_lost_carr +
+ stats->out_error_no_carr;
+
+ return nstats;
+}
+
+int t3e3_open(struct net_device *dev)
+{
+ struct channel *sc = dev_to_priv(dev);
+ int ret = hdlc_open(dev);
+
+ if (ret)
+ return ret;
+
+ sc->r.flags |= SBE_2T3E3_FLAG_NETWORK_UP;
+ dc_start(dev_to_priv(dev));
+ netif_start_queue(dev);
+ try_module_get(THIS_MODULE);
+ return 0;
+}
+
+int t3e3_close(struct net_device *dev)
+{
+ struct channel *sc = dev_to_priv(dev);
+ hdlc_close(dev);
+ netif_stop_queue(dev);
+ dc_stop(sc);
+ sc->r.flags &= ~SBE_2T3E3_FLAG_NETWORK_UP;
+ module_put(THIS_MODULE);
+ return 0;
+}
+
+static int t3e3_attach(struct net_device *dev, unsigned short foo1,
+ unsigned short foo2)
+{
+ return 0;
+}
+
+static const struct net_device_ops t3e3_ops = {
+ .ndo_open = t3e3_open,
+ .ndo_stop = t3e3_close,
+ .ndo_change_mtu = hdlc_change_mtu,
+ .ndo_start_xmit = hdlc_start_xmit,
+ .ndo_do_ioctl = t3e3_ioctl,
+ .ndo_get_stats = t3e3_get_stats,
+};
+
+int setup_device(struct net_device *dev, struct channel *sc)
+{
+ hdlc_device *hdlc = dev_to_hdlc(dev);
+ int retval;
+
+ dev->base_addr = pci_resource_start(sc->pdev, 0);
+ dev->irq = sc->pdev->irq;
+ dev->netdev_ops = &t3e3_ops;
+ dev->tx_queue_len = 100;
+ hdlc->xmit = t3e3_if_start_xmit;
+ hdlc->attach = t3e3_attach;
+ if ((retval = register_hdlc_device(dev))) {
+ dev_err(&sc->pdev->dev, "error registering HDLC device\n");
+ return retval;
+ }
+ return 0;
+}
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 3bedcc1..1ee7ab0 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1494,6 +1494,9 @@
#define PCI_DEVICE_ID_SBE_WANXL100 0x0301
#define PCI_DEVICE_ID_SBE_WANXL200 0x0302
#define PCI_DEVICE_ID_SBE_WANXL400 0x0104
+#define PCI_SUBDEVICE_ID_SBE_T3E3 0x0009
+#define PCI_SUBDEVICE_ID_SBE_2T3E3_P0 0x0901
+#define PCI_SUBDEVICE_ID_SBE_2T3E3_P1 0x0902
#define PCI_VENDOR_ID_TOSHIBA 0x1179
#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1 0x0101
^ permalink raw reply related
* Re: [PATCH staging] Add SBE 2T3E3 WAN driver
From: Greg KH @ 2010-08-12 21:23 UTC (permalink / raw)
To: Krzysztof Halasa; +Cc: netdev
In-Reply-To: <m3bp97tty8.fsf@intrepid.localdomain>
On Thu, Aug 12, 2010 at 11:14:07PM +0200, Krzysztof Halasa wrote:
> Greg,
>
> I have added the TODO file and removed #define DRV_NAME "SBE 2T3E3".
> The include/linux/pci_ids.h chunk is now also in Linus' tree, I'm still
> not removing it from this patch to avoid dependency on the very tip.
> Tested with 2.6.35.
>
> TIA for looking into this.
> BTW the original driver tarball is now accessible at
> http://userweb.kernel.org/~chris/SBE_2T3_Linux_2.0c.tgz
Thanks for puttting it up.
I'll queue this up in a few weeks after the 2.6.36 merge window closes
and things settle down.
greg k-h
^ permalink raw reply
* Re: [PATCH net-next-2.6] bridge: 64bit rx/tx counters
From: Eric Dumazet @ 2010-08-12 21:47 UTC (permalink / raw)
To: Andrew Morton
Cc: David Miller, Stephen Hemminger, netdev, bhutchings, Nick Piggin
In-Reply-To: <20100812080731.c9456ef9.akpm@linux-foundation.org>
Le jeudi 12 août 2010 à 08:07 -0700, Andrew Morton a écrit :
> On Thu, 12 Aug 2010 14:16:15 +0200 Eric Dumazet <eric.dumazet@gmail.com> wrote:
>
> > > And all this open-coded per-cpu counter stuff added all over the place.
> > > Were percpu_counters tested or reviewed and found inadequate and unfixable?
> > > If so, please do tell.
> > >
> >
> > percpu_counters tries hard to maintain a view of the current value of
> > the (global) counter. This adds a cost because of a shared cache line
> > and locking. (__percpu_counter_sum() is not very scalable on big hosts,
> > it locks the percpu_counter lock for a possibly long iteration)
>
> Could be. Is percpu_counter_read_positive() unsuitable?
>
I bet most people want precise counters when doing 'ifconfig lo'
SNMP applications would be very surprised to get non increasing values
between two samples, or inexact values.
> >
> > For network stats we dont want to maintain this central value, we do the
> > folding only when necessary.
>
> hm. Well, why? That big walk across all possible CPUs could be really
> expensive for some applications. Especially if num_possible_cpus is
> much larger than num_online_cpus, which iirc can happen in
> virtualisation setups; probably it can happen in non-virtualised
> machines too.
>
Agreed.
> > And this folding has zero effect on
> > concurrent writers (counter updates)
>
> The fastpath looks a little expensive in the code you've added. The
> write_seqlock() does an rmw and a wmb() and the stats inc is a 64-bit
> rmw whereas percpu_counters do a simple 32-bit add. So I'd expect that
> at some suitable batch value, percpu-counters are faster on 32-bit.
>
Hmm... 6 instructions (16 bytes of text) are a "little expensive" versus
120 instructions if we use percpu_counter ?
Following code from drivers/net/loopback.c
u64_stats_update_begin(&lb_stats->syncp);
lb_stats->bytes += len;
lb_stats->packets++;
u64_stats_update_end(&lb_stats->syncp);
maps on i386 to :
ff 46 10 incl 0x10(%esi) // u64_stats_update_begin(&lb_stats->syncp);
89 f8 mov %edi,%eax
99 cltd
01 7e 08 add %edi,0x8(%esi)
11 56 0c adc %edx,0xc(%esi)
83 06 01 addl $0x1,(%esi)
83 56 04 00 adcl $0x0,0x4(%esi)
ff 46 10 incl 0x10(%esi) // u64_stats_update_end(&lb_stats->syncp);
Exactly 6 added instructions compared to previous kernel (32bit
counters), only on 32bit hosts. These instructions are not expensive (no
conditional branches, no extra register pressure) and access private cpu
data.
While two calls to __percpu_counter_add() add about 120 instructions,
even on 64bit hosts, wasting precious cpu cycles.
> They'll usually be slower on 64-bit, until that num_possible_cpus walk
> bites you.
>
But are you aware we already fold SNMP values using for_each_possible()
macros, before adding 64bit counters ? Not related to 64bit stuff
really...
> percpu_counters might need some work to make them irq-friendly. That
> bare spin_lock().
>
> btw, I worry a bit about seqlocks in the presence of interrupts:
>
Please note that nothing is assumed about interrupts and seqcounts
Both readers and writers must mask them if necessary.
In most situations, masking softirq is enough for networking cases
(updates are performed from softirq handler, reads from process context)
> static inline void write_seqcount_begin(seqcount_t *s)
> {
> s->sequence++;
> smp_wmb();
> }
>
> are we assuming that the ++ there is atomic wrt interrupts? I think
> so. Is that always true for all architectures, compiler versions, etc?
>
s->sequence++ is certainly not atomic wrt interrupts on RISC arches
> > For network stack, we also need to update two values, a packet counter
> > and a bytes counter. percpu_counter is not very good for the 'bytes
> > counter', since we would have to use a arbitrary big bias value.
>
> OK, that's a nasty problem for percpu-counters.
>
> > Using several percpu_counter would also probably use more cache lines.
> >
> > Also please note this stuff is only needed for 32bit arches.
> >
> > Using percpu_counter would slow down network stack on modern arches.
>
> Was this ever quantified?
A single misplacement of dst refcount was responsible for a 25% tbench
slowdown on a small machine (8 cores). Without any lock, only atomic
operations on a shared cache line...
So I think we could easily quantify a big slow down adding two
percpu_counters add() in a driver fastpath and a 16 or 32 cores machine.
(It would be a revert of percpu stuff we added last years)
Improvements would be
0) Just forget about 64bit stuff on 32bit arches as we did from linux
0.99. People should not run 40Gb links on 32bit kernels :)
1) If we really want percpu_counter() stuff, find a way to make it
hierarchical or use a a very big BIAS (2^30 ?). And/Or reduce
percpu_counter_add() complexity for increasing unsigned counters.
2) Avoid the write_seqcount_begin()/end() stuff when a writer changes
only the low order parts of the 64bit counter.
(ie maintain a 32bit percpu value, and only atomicaly touch the
shared upper 32bits (and the seqcount) when overflowing this 32bit
percpu value.
Not sure its worth the added conditional branch.
Thanks
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox