* [PATCH] hostap: remove netif_stop_queue from init
From: Meelis Roos @ 2010-12-17 21:27 UTC (permalink / raw)
To: David Miller; +Cc: j, netdev, linux-wireless
In-Reply-To: <20101210.094747.193727608.davem@davemloft.net>
Fix runtime warning with backtrace from hostap by removing
netif_stop_queue() call before register_netdev. Tested to work fine on
hostap_pci Prism 2.5.
Signed-off-by: Meelis Roos <mroos@linux.ee>
diff --git a/drivers/net/wireless/hostap/hostap_main.c b/drivers/net/wireless/hostap/hostap_main.c
index 25a2722..1d9aed6 100644
--- a/drivers/net/wireless/hostap/hostap_main.c
+++ b/drivers/net/wireless/hostap/hostap_main.c
@@ -891,7 +891,6 @@ void hostap_setup_dev(struct net_device *dev, local_info_t *local,
SET_ETHTOOL_OPS(dev, &prism2_ethtool_ops);
- netif_stop_queue(dev);
}
static int hostap_enable_hostapd(local_info_t *local, int rtnl_locked)
--
Meelis Roos (mroos@linux.ee)
^ permalink raw reply related
* Re: [PATCH] hostap: remove netif_stop_queue from init
From: David Miller @ 2010-12-17 21:32 UTC (permalink / raw)
To: mroos-Y27EyoLml9s
Cc: j, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-wireless-u79uwXL29TY76Z2rM5mHXA,
linville-2XuSBdqkA4R54TAoqtyWWQ
In-Reply-To: <alpine.SOC.1.00.1012172324340.24976-ptEonEWSGqKptlylMvRsHA@public.gmane.org>
From: Meelis Roos <mroos-Y27EyoLml9s@public.gmane.org>
Date: Fri, 17 Dec 2010 23:27:50 +0200 (EET)
> Fix runtime warning with backtrace from hostap by removing
> netif_stop_queue() call before register_netdev. Tested to work fine on
> hostap_pci Prism 2.5.
>
> Signed-off-by: Meelis Roos <mroos-Y27EyoLml9s@public.gmane.org>
Acked-by: David S. Miller <davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org>
John, please apply this.
--
To unsubscribe from this list: send the line "unsubscribe linux-wireless" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH net-next-2.6 v2 1/1] can: c_can: Added support for Bosch C_CAN controller
From: Marc Kleine-Budde @ 2010-12-17 21:33 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1292407130-19791-1-git-send-email-bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
[-- Attachment #1.1: Type: text/plain, Size: 41896 bytes --]
On 12/15/2010 10:58 AM, Bhupesh Sharma wrote:
> Bosch C_CAN controller is a full-CAN implementation which is compliant
> to CAN protocol version 2.0 part A and B. Bosch C_CAN user manual can be
> obtained from:
> http://www.semiconductors.bosch.de/pdf/Users_Manual_C_CAN.pdf
No time to do a real review, some comments and lots of nitpicking inline....
regards, Marc
>
> This patch adds the support for this controller.
> The following are the design choices made while writing the controller driver:
> 1. Interface Register set IF1 has be used only in the current design.
> 2. Out of the 32 Message objects available, 16 are kept aside for RX purposes
> and the rest for TX purposes.
> 3. NAPI implementation is such that both the TX and RX paths function in
> polling mode.
>
> Changes since V1:
> 1. Implemented C_CAN as a platform driver with means of providing the
> platform details and register offsets which may vary for different SoCs
> through platform data struct.
> 2. Implemented NAPI.
> 3. Removed memcpy calls globally.
> 4. Implemented CAN_CTRLMODE_*
> 5. Implemented and used priv->can.do_get_berr_counter.
> 6. Implemented c_can registers as a struct instead of enum.
> 7. Improved the TX path by implementing routines to get next Tx and echo msg
> objects.
>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
> ---
> drivers/net/can/Kconfig | 7 +
> drivers/net/can/Makefile | 1 +
> drivers/net/can/c_can.c | 1217 ++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1225 insertions(+), 0 deletions(-)
> create mode 100644 drivers/net/can/c_can.c
>
> diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
> index 9d9e453..25d9d2e 100644
> --- a/drivers/net/can/Kconfig
> +++ b/drivers/net/can/Kconfig
> @@ -41,6 +41,13 @@ config CAN_AT91
> ---help---
> This is a driver for the SoC CAN controller in Atmel's AT91SAM9263.
>
> +config CAN_C_CAN
> + tristate "Bosch C_CAN controller"
> + depends on CAN_DEV
> + ---help---
> + If you say yes to this option, support will be included for the
> + Bosch C_CAN controller.
> +
> config CAN_TI_HECC
> depends on CAN_DEV && ARCH_OMAP3
> tristate "TI High End CAN Controller"
> diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
> index 0057537..b6cbe74 100644
> --- a/drivers/net/can/Makefile
> +++ b/drivers/net/can/Makefile
> @@ -12,6 +12,7 @@ obj-y += usb/
> obj-$(CONFIG_CAN_SJA1000) += sja1000/
> obj-$(CONFIG_CAN_MSCAN) += mscan/
> obj-$(CONFIG_CAN_AT91) += at91_can.o
> +obj-$(CONFIG_CAN_C_CAN) += c_can.o
> obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o
> obj-$(CONFIG_CAN_MCP251X) += mcp251x.o
> obj-$(CONFIG_CAN_BFIN) += bfin_can.o
> diff --git a/drivers/net/can/c_can.c b/drivers/net/can/c_can.c
> new file mode 100644
> index 0000000..c281c17
> --- /dev/null
> +++ b/drivers/net/can/c_can.c
> @@ -0,0 +1,1217 @@
> +/*
> + * CAN bus driver for Bosch C_CAN controller
> + *
> + * Copyright (C) 2010 ST Microelectronics
> + * Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
> + *
> + * Borrowed heavily from the C_CAN driver originally written by:
> + * Copyright (C) 2007
> + * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
> + * - Simon Kallweit, intefo AG <simon.kallweit-+G9qxTFKJT/tRgLqZ5aouw@public.gmane.org>
> + *
I recognize some stuff from the at91_can driver, too :)
> + * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
> + * Bosch C_CAN user manual can be obtained from:
> + * http://www.semiconductors.bosch.de/pdf/Users_Manual_C_CAN.pdf
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/version.h>
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +#include <linux/delay.h>
> +#include <linux/netdevice.h>
> +#include <linux/if_arp.h>
> +#include <linux/if_ether.h>
> +#include <linux/list.h>
> +#include <linux/delay.h>
> +#include <linux/workqueue.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk.h>
> +
> +#include <linux/can.h>
> +#include <linux/can/dev.h>
> +#include <linux/can/error.h>
> +
> +#define DRV_NAME "c_can"
You can use KBUILD_MODNAME, no need to define DRV_NAME.
> +
> +/* control register */
> +#define CONTROL_TEST (1 << 7)
> +#define CONTROL_CCE (1 << 6)
> +#define CONTROL_DISABLE_AR (1 << 5)
> +#define CONTROL_ENABLE_AR (0 << 5)
> +#define CONTROL_EIE (1 << 3)
> +#define CONTROL_SIE (1 << 2)
> +#define CONTROL_IE (1 << 1)
> +#define CONTROL_INIT (1 << 0)
> +
> +/* test register */
> +#define TEST_RX (1 << 7)
> +#define TEST_TX1 (1 << 6)
> +#define TEST_TX2 (1 << 5)
> +#define TEST_LBACK (1 << 4)
> +#define TEST_SILENT (1 << 3)
> +#define TEST_BASIC (1 << 2)
You can use BIT(n) instead of (1 << n).
> +
> +/* status register */
> +#define STATUS_BOFF (1 << 7)
> +#define STATUS_EWARN (1 << 6)
> +#define STATUS_EPASS (1 << 5)
> +#define STATUS_RXOK (1 << 4)
> +#define STATUS_TXOK (1 << 3)
> +#define STATUS_LEC_MASK 0x07
> +#define LEC_STUFF_ERROR 1
> +#define LEC_FORM_ERROR 2
> +#define LEC_ACK_ERROR 3
> +#define LEC_BIT1_ERROR 4
> +#define LEC_BIT0_ERROR 5
> +#define LEC_CRC_ERROR 6
> +
> +/* error counter register */
> +#define ERR_COUNTER_TEC_MASK 0xff
> +#define ERR_COUNTER_TEC_SHIFT 0x0
nitpick, I'd just use a pure decimal 0 :)
> +#define ERR_COUNTER_REC_SHIFT 8
> +#define ERR_COUNTER_REC_MASK (0x7f << ERR_COUNTER_REC_SHIFT)
> +#define ERR_COUNTER_RP_SHIFT 15
> +#define ERR_COUNTER_RP_MASK (0x1 << ERR_COUNTER_RP_SHIFT)
> +
> +/* bit-timing register */
> +#define BTR_BRP_MASK 0x3f
> +#define BTR_BRP_SHIFT 0
> +#define BTR_SJW_SHIFT 6
> +#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
> +#define BTR_TSEG1_SHIFT 8
> +#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
> +#define BTR_TSEG2_SHIFT 12
> +#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
> +
> +/* brp extension register */
> +#define BRP_EXT_BRPE_MASK 0x0f
> +#define BRP_EXT_BRPE_SHIFT 0
> +
> +/* IFx command request */
> +#define IF_COMR_BUSY (1 << 15)
> +
> +/* IFx command mask */
> +#define IF_COMM_WR (1 << 7)
> +#define IF_COMM_MASK (1 << 6)
> +#define IF_COMM_ARB (1 << 5)
> +#define IF_COMM_CONTROL (1 << 4)
> +#define IF_COMM_CLR_INT_PND (1 << 3)
> +#define IF_COMM_TXRQST (1 << 2)
> +#define IF_COMM_DATAA (1 << 1)
> +#define IF_COMM_DATAB (1 << 0)
> +#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
> + IF_COMM_CONTROL | IF_COMM_TXRQST | \
> + IF_COMM_DATAA | IF_COMM_DATAB)
> +
> +/* IFx arbitration */
> +#define IF_ARB_MSGVAL (1 << 15)
> +#define IF_ARB_MSGXTD (1 << 14)
> +#define IF_ARB_TRANSMIT (1 << 13)
> +
> +/* IFx message control */
> +#define IF_MCONT_NEWDAT (1 << 15)
> +#define IF_MCONT_MSGLST (1 << 14)
> +#define IF_MCONT_INTPND (1 << 13)
> +#define IF_MCONT_UMASK (1 << 12)
> +#define IF_MCONT_TXIE (1 << 11)
> +#define IF_MCONT_RXIE (1 << 10)
> +#define IF_MCONT_RMTEN (1 << 9)
> +#define IF_MCONT_TXRQST (1 << 8)
> +#define IF_MCONT_EOB (1 << 7)
> +
> +/*
> + * IFx register masks:
> + * allow easy operation on 16-bit registers when the
> + * argument is 32-bit instead
> + */
> +#define IFX_WRITE_LOW_16BIT(x) (x & 0xFFFF)
> +#define IFX_WRITE_HIGH_16BIT(x) ((x & 0xFFFF0000) >> 16)
> +
> +/* message object split */
> +#define C_CAN_NO_OF_OBJECTS 31
> +#define C_CAN_MSG_OBJ_RX_NUM 16
> +#define C_CAN_MSG_OBJ_TX_NUM 16
> +
> +#define C_CAN_MSG_OBJ_RX_FIRST 0
> +#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
> + C_CAN_MSG_OBJ_RX_NUM - 1)
> +
> +#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
> +#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
> + C_CAN_MSG_OBJ_TX_NUM - 1)
> +#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
> +#define RECEIVE_OBJECT_BITS 0x0000ffff
> +
> +/* status interrupt */
> +#define STATUS_INTERRUPT 0x8000
> +
> +/* napi related */
> +#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
> +
> +/* c_can IF registers */
> +struct c_can_if_regs {
> + u16 com_reg;
> + u16 com_mask;
> + u16 mask1;
> + u16 mask2;
> + u16 arb1;
> + u16 arb2;
> + u16 msg_cntrl;
> + u16 data_a1;
> + u16 data_a2;
> + u16 data_b1;
> + u16 data_b2;
The later code _mighy_ be easier to read if you define data as an array
of u16, but let's see...
> + u16 _reserved[13];
> +};
> +
> +/* c_can hardware registers */
> +struct c_can_regs {
> + u16 control;
> + u16 status;
> + u16 error_counter;
> + u16 btr;
> + u16 ir;
> + u16 test;
> + u16 brp_ext;
> + u16 _reserved1;
> + struct c_can_if_regs ifreg[2]; /* [0] = IF1 and [1] = IF2 */
> + u16 _reserved2[8];
> + u16 txrqst1;
> + u16 txrqst2;
> + u16 _reserved3[6];
> + u16 newdat1;
> + u16 newdat2;
> + u16 _reserved4[6];
> + u16 intpnd1;
> + u16 intpnd2;
> + u16 _reserved5[6];
> + u16 msgval1;
> + u16 msgval2;
> + u16 _reserved6[6];
> +};
> +
> +/*
> + * c_can error types:
> + * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
> + */
> +enum c_can_bus_error_types {
> + C_CAN_NO_ERROR = 0,
> + C_CAN_BUS_OFF,
> + C_CAN_ERROR_WARNING,
> + C_CAN_ERROR_PASSIVE
^
please add a ","
> +};
> +
> +enum c_can_interrupt_mode {
> + ENABLE_MODULE_INTERRUPT = 0,
> + DISABLE_MODULE_INTERRUPT,
> + ENABLE_ALL_INTERRUPTS,
> + DISABLE_ALL_INTERRUPTS
same here
> +};
> +
> +/* c_can private data structure */
> +struct c_can_priv {
> + struct can_priv can; /* must be the first member */
> + struct napi_struct napi;
> + struct net_device *dev;
> + int tx_object;
> + int current_status;
> + int last_status;
> + u16 (*read_reg) (struct c_can_priv *priv, void *reg);
> + void (*write_reg) (struct c_can_priv *priv, void *reg, u16 val);
> + struct c_can_regs __iomem *reg_base;
> + unsigned long irq_flags; /* for request_irq() */
> + unsigned int tx_next;
> + unsigned int tx_echo;
> + struct clk *clk;
> +};
> +
> +static struct can_bittiming_const c_can_bittiming_const = {
> + .name = DRV_NAME,
use KBUILD_MODNAME here
> + .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
> + .tseg1_max = 16,
> + .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
> + .tseg2_max = 8,
> + .sjw_max = 4,
> + .brp_min = 1,
> + .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
> + .brp_inc = 1,
> +};
> +
> +static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
> +{
> + return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
> + C_CAN_MSG_OBJ_TX_FIRST;
> +}
> +
> +static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
> +{
> + return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
> + C_CAN_MSG_OBJ_TX_FIRST;
> +}
> +
> +/* 16-bit c_can registers can be arranged differently in the memory
> + * architecture of different implementations. For example: 16-bit
> + * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
> + * Handle the same by providing a common read/write interface.
> + */
/*
* this is the preferred multi-line comment style,
* please adjust
*/
> +static u16 c_can_read_reg_aligned_to_16bit(void *reg)
> +{
> + return readw(reg);
> +}
> +
> +static void c_can_write_reg_aligned_to_16bit(void *reg, u16 val)
> +{
> + writew(val, reg);
> +}
> +
> +static u16 c_can_read_reg_aligned_to_32bit(struct c_can_priv *priv, void *reg)
> +{
> + return readw(reg + (u32)reg - (u32)priv->reg_base);
as Wolfgang said not 64 bit safe.....what about casting the reg_base to
void __iomem *?
> +}
> +
> +static void c_can_write_reg_aligned_to_32bit(struct c_can_priv *priv,
> + void *reg, u16 val)
> +{
> + writew(val, reg + (u32)reg - (u32)priv->reg_base);
> +}
> +
> +static u32 c_can_read_reg32(struct c_can_priv *priv, void *reg)
> +{
> + u32 val = priv->read_reg(priv, reg);
> + val |= ((u32) priv->read_reg(priv, reg + 2)) << 16;
> + return val;
> +}
> +
> +static inline int c_can_configure_interrupts(struct c_can_priv *priv,
> + enum c_can_interrupt_mode intr_mode)
> +{
> + unsigned int cntrl_save = priv->read_reg(priv,
> + &priv->reg_base->control);
> +
> + switch (intr_mode) {
> + case ENABLE_MODULE_INTERRUPT:
> + cntrl_save |= CONTROL_IE;
> + break;
> + case DISABLE_MODULE_INTERRUPT:
> + cntrl_save &= ~CONTROL_IE;
> + break;
> + case ENABLE_ALL_INTERRUPTS:
> + cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
> + break;
> + case DISABLE_ALL_INTERRUPTS:
> + cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
> + break;
> + default:
> + return -EOPNOTSUPP;
> + }
> +
> + priv->write_reg(priv, &priv->reg_base->control, cntrl_save);
> +
> + return 0;
> +}
> +
> +static inline int c_can_object_get(struct net_device *dev,
> + int iface, int objno, int mask)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> + int timeout = (6 / priv->can.clock.freq);
> +
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].com_mask,
> + IFX_WRITE_LOW_16BIT(mask));
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].com_reg,
> + IFX_WRITE_LOW_16BIT(objno + 1));
> +
> + /* as per specs, after writting the message object number in the
> + * IF command request register the transfer b/w interface
> + * register and message RAM must be complete in 6 CAN-CLK
> + * period. The delay accounts for the same
> + */
> + udelay(timeout);
> + if ((priv->read_reg(priv, &priv->reg_base->ifreg[iface].com_reg)) &
> + IF_COMR_BUSY) {
> + dev_info(dev->dev.parent, "timed out in object get\n");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +static inline int c_can_object_put(struct net_device *dev,
> + int iface, int objno, int mask)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> + int timeout = (6 / priv->can.clock.freq);
> +
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].com_mask,
> + (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].com_reg,
> + IFX_WRITE_LOW_16BIT(objno + 1));
> +
> + /* as per specs, after writting the message object number in the
> + * IF command request register the transfer b/w interface
> + * register and message RAM must be complete in 6 CAN-CLK
> + * period. The delay accounts for the same
> + */
> + udelay(timeout);
> + if ((priv->read_reg(priv, &priv->reg_base->ifreg[iface].com_reg)) &
> + IF_COMR_BUSY) {
> + dev_info(dev->dev.parent, "timed out in object put\n");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +int c_can_write_msg_object(struct net_device *dev,
> + int iface, struct can_frame *frame, int objno)
> +{
> + u16 flags = 0;
> + unsigned int id;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + if (frame->can_id & CAN_EFF_FLAG) {
> + id = frame->can_id & CAN_EFF_MASK;
> + flags |= IF_ARB_MSGXTD;
> + } else
> + id = ((frame->can_id & CAN_SFF_MASK) << 18);
> +
> + if (!(frame->can_id & CAN_RTR_FLAG))
> + flags |= IF_ARB_TRANSMIT;
> +
> + flags |= IF_ARB_MSGVAL;
> +
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].arb1,
> + IFX_WRITE_LOW_16BIT(id));
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].arb2, flags |
> + IFX_WRITE_HIGH_16BIT(id));
> +
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].data_a1,
> + (*(u16 *)(frame->data)));
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].data_a2,
> + (*(u32 *)(frame->data)) >> 16);
> +
> + if (frame->can_dlc > 4) {
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].data_b1,
> + (*(u16 *)(frame->data + 4)));
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].data_b2,
> + (*(u32 *)(frame->data + 4)) >> 16);
> + } else
> + *(u32 *)(frame->data + 4) = 0;
look at the pch can driver, it uses an array for ifreg->data and is
endianess safe.
> +
> + return frame->can_dlc;
> +}
> +
> +static int c_can_read_msg_object(struct net_device *dev, int iface, int objno)
> +{
> + u16 flags;
> + int ctrl;
> + unsigned int val, data;
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct net_device_stats *stats = &dev->stats;
> + struct sk_buff *skb;
> + struct can_frame *frame;
> +
> + skb = alloc_can_skb(dev, &frame);
> + if (!skb) {
> + stats->rx_dropped++;
> + return -ENOMEM;
> + }
> +
> + val = c_can_object_get(dev, iface, objno, IF_COMM_ALL &
> + ~IF_COMM_TXRQST);
> + if (val < 0)
> + return val;
> +
> + ctrl = priv->read_reg(priv, &priv->reg_base->ifreg[iface].msg_cntrl);
> + if (ctrl & IF_MCONT_MSGLST) {
> + stats->rx_errors++;
> + dev_info(dev->dev.parent, "msg lost in buffer %d\n", objno);
> + }
> +
> + frame->can_dlc = get_can_dlc(ctrl & 0x0F);
> + data = priv->read_reg(priv, &priv->reg_base->ifreg[iface].data_a1) |
> + (priv->read_reg(priv, &priv->reg_base->ifreg[iface].data_a2) <<
> + 16);
> + *(u32 *)(frame->data) = data;
> + if (frame->can_dlc > 4) {
> + data = priv->read_reg(priv,
> + &priv->reg_base->ifreg[iface].data_b1) |
> + (priv->read_reg(priv,
> + &priv->reg_base->ifreg[iface].data_b2) <<
> + 16);
> + *(u32 *)(frame->data + 4) = data;
> + } else
> + *(u32 *)(frame->data + 4) = 0;
dito
> +
> + flags = priv->read_reg(priv, &priv->reg_base->ifreg[iface].arb2);
> + val = priv->read_reg(priv, &priv->reg_base->ifreg[iface].arb1) |
> + (flags << 16);
> +
> + if (flags & IF_ARB_MSGXTD)
> + frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG;
> + else
> + frame->can_id = (val >> 18) & CAN_SFF_MASK;
> +
> + if (flags & IF_ARB_TRANSMIT)
> + frame->can_id |= CAN_RTR_FLAG;
> +
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].msg_cntrl, ctrl &
> + ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT));
> +
> + val = c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
> + if (val < 0)
> + return val;
> +
> + netif_receive_skb(skb);
> +
> + stats->rx_packets++;
> + stats->rx_bytes += frame->can_dlc;
> +
> + return 0;
> +}
> +
> +static int c_can_setup_receive_object(struct net_device *dev, int iface,
> + int objno, unsigned int mask,
> + unsigned int id, unsigned int mcont)
> +{
> + int ret;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].mask1,
> + IFX_WRITE_LOW_16BIT(mask));
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].mask2,
> + IFX_WRITE_HIGH_16BIT(mask));
> +
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].arb1,
> + IFX_WRITE_LOW_16BIT(id));
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].arb2,
> + (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
> +
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].msg_cntrl, mcont);
> + ret = c_can_object_put(dev, iface, objno, IF_COMM_ALL &
> + ~IF_COMM_TXRQST);
> + if (ret < 0)
> + return ret;
> +
> + dev_dbg(dev->dev.parent, "obj no:%d, msgval:0x%08x\n", objno,
> + c_can_read_reg32(priv, &priv->reg_base->msgval1));
> +
> + return 0;
> +}
> +
> +static int c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
> +{
> + int ret;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].arb1, 0);
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].arb2, 0);
> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].msg_cntrl, 0);
> +
> + ret = c_can_object_put(dev, iface, objno,
> + IF_COMM_ARB | IF_COMM_CONTROL);
> + if (ret < 0)
> + return ret;
> +
> + dev_dbg(dev->dev.parent, "obj no:%d, msgval:0x%08x\n", objno,
> + c_can_read_reg32(priv, &priv->reg_base->msgval1));
> +
> + return 0;
> +}
> +
> +static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
> + struct net_device *dev)
> +{
> + u32 val;
> + u32 msg_obj_no;
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct can_frame *frame = (struct can_frame *)skb->data;
> +
> + if (can_dropped_invalid_skb(dev, skb))
> + return NETDEV_TX_OK;
> +
> + msg_obj_no = get_tx_next_msg_obj(priv);
> +
> + /* prepare message object for transmission */
> + val = c_can_write_msg_object(dev, 0, frame, msg_obj_no);
> +
> + /* enable interrupt for this message object */
> + priv->write_reg(priv, &priv->reg_base->ifreg[0].msg_cntrl,
> + IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
> + (val & 0xf));
> + val = c_can_object_put(dev, 0, msg_obj_no, IF_COMM_ALL);
> + if (val < 0)
> + return val;
> +
> + can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
> +
> + priv->tx_next++;
> + if ((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
> + netif_stop_queue(dev);
> +
> + return NETDEV_TX_OK;
> +}
> +
> +static int c_can_set_bittiming(struct net_device *dev)
> +{
> + unsigned int reg_btr, reg_brpe, ctrl_save;
> + u8 brp, brpe, sjw, tseg1, tseg2;
> + u32 ten_bit_brp;
> + struct c_can_priv *priv = netdev_priv(dev);
> + const struct can_bittiming *bt = &priv->can.bittiming;
> +
> + /* c_can provides a 6-bit brp and 4-bit brpe fields */
> + ten_bit_brp = bt->brp - 1;
> + brp = ten_bit_brp & BTR_BRP_MASK;
> + brpe = ten_bit_brp >> 6;
> +
> + sjw = bt->sjw - 1;
> + tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
> + tseg2 = bt->phase_seg2 - 1;
> +
> + reg_btr = ((brp) | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
> + (tseg2 << BTR_TSEG2_SHIFT));
> +
> + reg_brpe = brpe & BRP_EXT_BRPE_MASK;
> +
> + dev_dbg(dev->dev.parent,
> + "brp = %d, brpe = %d, sjw = %d, seg1 = %d, seg2 = %d\n",
> + brp, brpe, sjw, tseg1, tseg2);
> + dev_dbg(dev->dev.parent, "setting BTR to %04x\n", reg_btr);
> + dev_dbg(dev->dev.parent, "setting BRPE to %04x\n", reg_brpe);
> +
> + ctrl_save = priv->read_reg(priv, &priv->reg_base->control);
> + priv->write_reg(priv, &priv->reg_base->control,
> + ctrl_save | CONTROL_CCE | CONTROL_INIT);
> + priv->write_reg(priv, &priv->reg_base->btr, reg_btr);
> + priv->write_reg(priv, &priv->reg_base->brp_ext, reg_brpe);
> + priv->write_reg(priv, &priv->reg_base->control, ctrl_save);
> +
> + return 0;
> +}
> +
> +/*
> + * Configure C_CAN message objects for Tx and Rx purposes:
> + * C_CAN provides a total of 32 message objects that can be configured
> + * either for Tx or Rx purposes. Here the first 16 message objects are used as
> + * a reception FIFO. The end of reception FIFO is signified by the EoB bit
> + * being SET. The remaining 16 message objects are kept aside for Tx purposes.
> + * See user guide document for further details on configuring message
> + * objects.
> + */
> +static int c_can_configure_msg_objects(struct net_device *dev)
> +{
> + int i;
> +
> + /* first invalidate all message objects */
> + for (i = 0; i <= C_CAN_NO_OF_OBJECTS; i++)
> + c_can_inval_msg_object(dev, 0, i);
> +
> + /* setup receive message objects */
> + for (i = C_CAN_MSG_OBJ_RX_FIRST + 1 ; i < C_CAN_MSG_OBJ_RX_LAST; i++)
> + c_can_setup_receive_object(dev, 0, i, 0, 0,
> + ((IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB));
> +
> + c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
> + IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK);
> + return 0;
> +}
> +
> +/*
> + * Configure C_CAN chip:
> + * - enable/disable auto-retransmission
> + * - set operating mode
> + * - configure message objects
> + */
> +static int c_can_chip_config(struct net_device *dev)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
> + /* disable automatic retransmission */
> + priv->write_reg(priv, &priv->reg_base->control,
> + CONTROL_DISABLE_AR);
> + else
> + /* enable automatic retransmission */
> + priv->write_reg(priv, &priv->reg_base->control,
> + CONTROL_ENABLE_AR);
> +
> + if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
> + /* loopback mode : useful for self-test function */
> + priv->write_reg(priv, &priv->reg_base->control, (CONTROL_EIE |
> + CONTROL_SIE | CONTROL_IE | CONTROL_TEST));
> + priv->write_reg(priv, &priv->reg_base->test, TEST_LBACK);
> + } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
> + /* silent mode : bus-monitoring mode */
> + priv->write_reg(priv, &priv->reg_base->control, (CONTROL_EIE |
> + CONTROL_SIE | CONTROL_IE | CONTROL_TEST));
> + priv->write_reg(priv, &priv->reg_base->test, TEST_SILENT);
> + } else if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY &
> + CAN_CTRLMODE_LOOPBACK)) {
> + /* loopback + silent mode : useful for hot self-test */
> + priv->write_reg(priv, &priv->reg_base->control, (CONTROL_EIE |
> + CONTROL_SIE | CONTROL_IE | CONTROL_TEST));
> + priv->write_reg(priv, &priv->reg_base->test,
> + (TEST_LBACK | TEST_SILENT));
> + } else
> + /* normal mode*/
> + priv->write_reg(priv, &priv->reg_base->control,
> + (CONTROL_EIE | CONTROL_SIE | CONTROL_IE));
> +
> + /* configure message objects */
> + c_can_configure_msg_objects(dev);
> +
> + return 0;
> +}
> +
> +static int c_can_start(struct net_device *dev)
> +{
> + int err;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /* enable status change, error and module interrupts */
> + c_can_configure_interrupts(priv, ENABLE_ALL_INTERRUPTS);
> +
> + /* basic c_can configuration */
> + err = c_can_chip_config(dev);
> + if (err)
> + return err;
> +
> + priv->can.state = CAN_STATE_ERROR_ACTIVE;
> +
> + /* reset tx helper pointers */
> + priv->tx_next = priv->tx_echo = 0;
> +
> + return 0;
> +}
> +
> +static int c_can_stop(struct net_device *dev)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /* disable all interrupts */
> + c_can_configure_interrupts(priv, DISABLE_ALL_INTERRUPTS);
> +
> + /* set the state as STOPPED */
> + priv->can.state = CAN_STATE_STOPPED;
> +
> + return 0;
> +}
> +
> +static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
> +{
> + switch (mode) {
> + case CAN_MODE_START:
> + c_can_start(dev);
> + netif_wake_queue(dev);
> + dev_info(dev->dev.parent,
> + "c_can CAN_MODE_START requested\n");
> + break;
> + default:
> + return -EOPNOTSUPP;
> + }
> +
> + return 0;
> +}
> +
> +static int c_can_get_state(const struct net_device *dev,
> + enum can_state *state)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + *state = priv->can.state;
> +
> + return 0;
> +}
> +
> +static int c_can_get_berr_counter(const struct net_device *dev,
> + struct can_berr_counter *bec)
> +{
> + unsigned int reg_err_counter;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + reg_err_counter = priv->read_reg(priv, &priv->reg_base->error_counter);
> + bec->rxerr = ((reg_err_counter & ERR_COUNTER_REC_MASK) >>
> + ERR_COUNTER_REC_SHIFT);
> + bec->txerr = (reg_err_counter & ERR_COUNTER_TEC_MASK);
> +
> + return 0;
> +}
> +
> +/*
> + * theory of operation:
> + *
> + * priv->tx_echo holds the number of the oldest can_frame put for
> + * transmission into the hardware, but not yet ACKed by the CAN tx
> + * complete IRQ.
> + *
> + * We iterate from priv->tx_echo to priv->tx_next and check if the
> + * packet has been transmitted, echo it back to the CAN framework. If
> + * we discover a not yet transmitted package, stop looking for more.
> + */
> +static void c_can_do_tx(struct net_device *dev)
> +{
> + u32 val;
> + u32 msg_obj_no;
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct net_device_stats *stats = &dev->stats;
> +
> + for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
> + msg_obj_no = get_tx_echo_msg_obj(priv);
> + c_can_inval_msg_object(dev, 0, msg_obj_no);
> + val = c_can_read_reg32(priv, &priv->reg_base->txrqst1);
> + if (!(val & (1 << msg_obj_no))) {
> + can_get_echo_skb(dev,
> + msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
> + stats->tx_bytes += priv->read_reg(priv,
> + &priv->reg_base->ifreg[0].msg_cntrl)
> + & 0xF;
> + stats->tx_packets++;
> + }
> + }
> +
> + /* restart queue if wrap-up or if queue stalled on last pkt */
> + if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
> + ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
> + netif_wake_queue(dev);
> +}
> +
> +/*
> + * c_can_do_rx_poll - read multiple CAN messages from message objects
> + */
> +static int c_can_do_rx_poll(struct net_device *dev, int quota)
> +{
> + u32 num_rx_pkts = 0;
> + unsigned int msg_obj;
> + struct c_can_priv *priv = netdev_priv(dev);
> + u32 val = c_can_read_reg32(priv, &priv->reg_base->newdat1);
> +
> + while (val & RECEIVE_OBJECT_BITS) {
> + for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST;
> + msg_obj <= C_CAN_MSG_OBJ_RX_LAST; msg_obj++) {
> + if (val & (1 << msg_obj)) {
> + c_can_read_msg_object(dev, 0, msg_obj);
> + num_rx_pkts++;
> + quota--;
> + }
> + }
> +
> + val = c_can_read_reg32(priv, &priv->reg_base->newdat1);
> + }
> +
> + return num_rx_pkts;
> +}
> +
> +static int c_can_err(struct net_device *dev,
> + enum c_can_bus_error_types error_type,
> + int lec_type)
> +{
> + unsigned int reg_err_counter;
> + unsigned int rx_err_passive;
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct net_device_stats *stats = &dev->stats;
> + struct can_frame *cf;
> + struct sk_buff *skb;
> + struct can_berr_counter bec;
> +
> + /* propogate the error condition to the CAN stack */
> + skb = alloc_can_err_skb(dev, &cf);
> + if (unlikely(!skb))
> + return 0;
> +
> + c_can_get_berr_counter(dev, &bec);
> + reg_err_counter = priv->read_reg(priv, &priv->reg_base->error_counter);
> + rx_err_passive = ((reg_err_counter & ERR_COUNTER_RP_MASK) >>
> + ERR_COUNTER_RP_SHIFT);
> +
> + if (error_type & C_CAN_ERROR_WARNING) {
> + /* error warning state */
> + priv->can.can_stats.error_warning++;
> + priv->can.state = CAN_STATE_ERROR_WARNING;
> + cf->can_id |= CAN_ERR_CRTL;
> + if (bec.rxerr > 96)
> + cf->data[1] = CAN_ERR_CRTL_RX_WARNING;
> + if (bec.txerr > 96)
> + cf->data[1] = CAN_ERR_CRTL_TX_WARNING;
> + }
> + if (error_type & C_CAN_ERROR_PASSIVE) {
> + /* error passive state */
> + priv->can.can_stats.error_passive++;
> + priv->can.state = CAN_STATE_ERROR_PASSIVE;
> + cf->can_id |= CAN_ERR_CRTL;
> + if (rx_err_passive)
> + cf->data[1] = CAN_ERR_CRTL_RX_PASSIVE;
> + if (bec.txerr > 127)
> + cf->data[1] = CAN_ERR_CRTL_TX_PASSIVE;
> + }
> + if (error_type & C_CAN_BUS_OFF) {
> + /* bus-off state */
> + priv->can.state = CAN_STATE_BUS_OFF;
> + cf->can_id |= CAN_ERR_BUSOFF;
> + /* disable all interrupts in bus-off mode to ensure that
> + * the CPU is not hogged down
> + */
> + c_can_configure_interrupts(priv, DISABLE_ALL_INTERRUPTS);
> + can_bus_off(dev);
> + }
> +
> + /* check for 'last error code' which tells us the
> + * type of the last error to occur on the CAN bus
> + */
> + if (lec_type) {
> + /* common for all type of bus errors */
> + priv->can.can_stats.bus_error++;
> + stats->rx_errors++;
> + cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
> + cf->data[2] |= CAN_ERR_PROT_UNSPEC;
> +
> + if (lec_type & LEC_STUFF_ERROR) {
> + dev_info(dev->dev.parent, "stuff error\n");
> + cf->data[2] |= CAN_ERR_PROT_STUFF;
> + }
> + if (lec_type & LEC_FORM_ERROR) {
> + dev_info(dev->dev.parent, "form error\n");
> + cf->data[2] |= CAN_ERR_PROT_FORM;
> + }
> + if (lec_type & LEC_ACK_ERROR) {
> + dev_info(dev->dev.parent, "ack error\n");
> + cf->data[2] |= (CAN_ERR_PROT_LOC_ACK |
> + CAN_ERR_PROT_LOC_ACK_DEL);
> + }
> + if (lec_type & LEC_BIT1_ERROR) {
> + dev_info(dev->dev.parent, "bit1 error\n");
> + cf->data[2] |= CAN_ERR_PROT_BIT1;
> + }
> + if (lec_type & LEC_BIT0_ERROR) {
> + dev_info(dev->dev.parent, "bit0 error\n");
> + cf->data[2] |= CAN_ERR_PROT_BIT0;
> + }
> + if (lec_type & LEC_CRC_ERROR) {
> + dev_info(dev->dev.parent, "CRC error\n");
> + cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
> + CAN_ERR_PROT_LOC_CRC_DEL);
> + }
> + }
> +
> + netif_receive_skb(skb);
> + stats->rx_packets++;
> + stats->rx_bytes += cf->can_dlc;
> +
> + return 1;
> +}
> +
> +static int c_can_poll(struct napi_struct *napi, int quota)
> +{
> + u16 irqstatus;
> + int lec_type = 0;
> + int work_done = 0;
> + struct net_device *dev = napi->dev;
> + struct c_can_priv *priv = netdev_priv(dev);
> + enum c_can_bus_error_types error_type = C_CAN_NO_ERROR;
> +
> + irqstatus = priv->read_reg(priv, &priv->reg_base->ir);
> +
> + /* status events have the highest priority */
> + if (irqstatus == STATUS_INTERRUPT) {
> + priv->current_status = priv->read_reg(priv,
> + &priv->reg_base->status);
> +
> + /* handle Tx/Rx events */
> + if (priv->current_status & STATUS_TXOK)
> + priv->write_reg(priv, &priv->reg_base->status,
> + (priv->current_status & ~STATUS_TXOK));
> +
> + if (priv->current_status & STATUS_RXOK)
> + priv->write_reg(priv, &priv->reg_base->status,
> + (priv->current_status & ~STATUS_RXOK));
> +
> + /* handle bus error events */
> + if (priv->current_status & STATUS_EWARN) {
> + dev_info(dev->dev.parent,
> + "entered error warning state\n");
> + error_type = C_CAN_ERROR_WARNING;
> + }
> + if ((priv->current_status & STATUS_EPASS) &&
> + (!(priv->last_status & STATUS_EPASS))) {
> + dev_info(dev->dev.parent,
> + "entered error passive state\n");
> + error_type = C_CAN_ERROR_PASSIVE;
> + }
> + if ((priv->current_status & STATUS_BOFF) &&
> + (!(priv->last_status & STATUS_BOFF))) {
> + dev_info(dev->dev.parent,
> + "entered bus off state\n");
> + error_type = C_CAN_BUS_OFF;
> + }
> + if (priv->current_status & STATUS_LEC_MASK)
> + lec_type = (priv->current_status & STATUS_LEC_MASK);
> +
> + /* handle bus recovery events */
> + if ((!(priv->current_status & STATUS_EPASS)) &&
> + (priv->last_status & STATUS_EPASS)) {
> + dev_info(dev->dev.parent,
> + "left error passive state\n");
> + priv->can.state = CAN_STATE_ERROR_ACTIVE;
> + }
> + if ((!(priv->current_status & STATUS_BOFF)) &&
> + (priv->last_status & STATUS_BOFF)) {
> + dev_info(dev->dev.parent,
> + "left bus off state\n");
> + priv->can.state = CAN_STATE_ERROR_ACTIVE;
> + }
> +
> + priv->last_status = priv->current_status;
> +
> + /* handle error on the bus */
> + if (error_type != C_CAN_NO_ERROR)
> + work_done += c_can_err(dev, error_type, lec_type);
> + } else if ((irqstatus > C_CAN_MSG_OBJ_RX_FIRST) &&
> + (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
> + /* handle events corresponding to receive message objects */
> + work_done += c_can_do_rx_poll(dev, (quota - work_done));
> + quota--;
> + } else if ((irqstatus > C_CAN_MSG_OBJ_TX_FIRST) &&
> + (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
> + /* handle events corresponding to transmit message objects */
> + c_can_do_tx(dev);
> + }
> +
> + if (work_done < quota) {
> + napi_complete(napi);
> + /* enable all IRQs */
> + c_can_configure_interrupts(priv, ENABLE_ALL_INTERRUPTS);
> + }
> +
> + return work_done;
> +}
> +
> +static irqreturn_t c_can_isr(int irq, void *dev_id)
> +{
> + struct net_device *dev = (struct net_device *)dev_id;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /* disable all interrupts and schedule the NAPI */
> + c_can_configure_interrupts(priv, DISABLE_ALL_INTERRUPTS);
> + napi_schedule(&priv->napi);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int c_can_open(struct net_device *dev)
> +{
> + int err;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /* open the can device */
> + err = open_candev(dev);
> + if (err) {
> + dev_err(dev->dev.parent, "failed to open can device\n");
> + return err;
> + }
> +
> + /* register interrupt handler */
> + err = request_irq(dev->irq, &c_can_isr, priv->irq_flags, dev->name,
> + (void *)dev);
> + if (err < 0) {
> + dev_err(dev->dev.parent, "failed to attach interrupt\n");
> + goto exit_irq_fail;
> + }
> +
> + /* start the c_can controller */
> + err = c_can_start(dev);
> + if (err)
> + goto exit_start_fail;
> + napi_enable(&priv->napi);
> +
> + netif_start_queue(dev);
> +
> + return 0;
> +
> +exit_start_fail:
> + free_irq(dev->irq, dev);
> +exit_irq_fail:
> + close_candev(dev);
> + return err;
> +}
> +
> +static int c_can_close(struct net_device *dev)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + netif_stop_queue(dev);
> + napi_disable(&priv->napi);
> + c_can_stop(dev);
> + free_irq(dev->irq, dev);
> + close_candev(dev);
> +
> + return 0;
> +}
> +
> +static const struct net_device_ops c_can_netdev_ops = {
> + .ndo_open = c_can_open,
> + .ndo_stop = c_can_close,
> + .ndo_start_xmit = c_can_start_xmit,
> +};
> +
> +static int c_can_probe(struct platform_device *pdev)
> +{
> + int ret;
> + void __iomem *addr;
> + struct net_device *dev;
> + struct c_can_priv *priv;
> + struct resource *mem, *irq;
> + struct clk *clk;
> +
> + /* get the appropriate clk */
> + clk = clk_get(&pdev->dev, NULL);
> + if (IS_ERR(clk)) {
> + dev_err(&pdev->dev, "no clock defined\n");
> + ret = -ENODEV;
> + goto exit;
> + }
> +
> + /* get the platform data */
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
> + if (!mem || (irq <= 0)) {
> + ret = -ENODEV;
> + goto exit_free_clk;
> + }
> +
> + if (!request_mem_region(mem->start, resource_size(mem), DRV_NAME)) {
> + dev_err(&pdev->dev, "resource unavailable\n");
> + ret = -ENODEV;
> + goto exit_free_clk;
> + }
> +
> + addr = ioremap(mem->start, resource_size(mem));
> + if (!addr) {
> + dev_err(&pdev->dev, "failed to map can port\n");
> + ret = -ENOMEM;
> + goto exit_release_mem;
> + }
> +
> + /* allocate the c_can device */
> + dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
> + if (!dev) {
> + ret = -ENOMEM;
> + goto exit_iounmap;
> + }
> +
> + priv = netdev_priv(dev);
> +
> + priv->irq_flags = irq->flags;
> + priv->reg_base = addr;
> + priv->can.clock.freq = clk_get_rate(clk);
> + priv->clk = clk;
> +
> + switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
> + case IORESOURCE_MEM_32BIT:
> + priv->read_reg = c_can_read_reg_aligned_to_32bit;
> + priv->write_reg = c_can_write_reg_aligned_to_32bit;
> + break;
> + case IORESOURCE_MEM_16BIT:
> + default:
> + priv->read_reg = c_can_read_reg_aligned_to_16bit;
> + priv->write_reg = c_can_write_reg_aligned_to_16bit;
> + break;
> + }
> +
> + priv->dev = dev;
> + priv->can.bittiming_const = &c_can_bittiming_const;
> + priv->can.do_set_bittiming = c_can_set_bittiming;
> + priv->can.do_get_state = c_can_get_state;
> + priv->can.do_set_mode = c_can_set_mode;
> + priv->can.do_get_berr_counter = c_can_get_berr_counter;
> + priv->can.ctrlmode_supported = CAN_CTRLMODE_ONE_SHOT |
> + CAN_CTRLMODE_LOOPBACK |
> + CAN_CTRLMODE_LISTENONLY |
> + CAN_CTRLMODE_BERR_REPORTING;
> +
> + netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
> +
> + dev->irq = irq->start;
> + dev->flags |= IFF_ECHO; /* we support local echo */
> + dev->netdev_ops = &c_can_netdev_ops;
> + platform_set_drvdata(pdev, dev);
> + SET_NETDEV_DEV(dev, &pdev->dev);
> +
> + ret = register_candev(dev);
> + if (ret) {
> + dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
> + DRV_NAME, ret);
> + goto exit_free_device;
> + }
> +
> + dev_info(&pdev->dev, "%s device registered (reg_base=%p, irq=%d)\n",
> + DRV_NAME, priv->reg_base, dev->irq);
> + return 0;
> +
> +exit_free_device:
> + platform_set_drvdata(pdev, NULL);
> + free_candev(dev);
> +exit_iounmap:
> + iounmap(addr);
> +exit_release_mem:
> + release_mem_region(mem->start, resource_size(mem));
> +exit_free_clk:
> + clk_put(clk);
> +exit:
> + dev_err(&pdev->dev, "probe failed\n");
> +
> + return ret;
> +}
> +
> +static int c_can_remove(struct platform_device *pdev)
> +{
> + struct net_device *dev = platform_get_drvdata(pdev);
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct resource *mem;
> +
> + /* disable all interrupts */
> + c_can_configure_interrupts(priv, DISABLE_ALL_INTERRUPTS);
> +
> + unregister_candev(dev);
> + platform_set_drvdata(pdev, NULL);
> +
> + free_candev(dev);
> + iounmap(priv->reg_base);
> +
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + release_mem_region(mem->start, resource_size(mem));
> +
> + clk_put(priv->clk);
> +
> + return 0;
> +}
> +
> +static struct platform_driver c_can_driver = {
> + .driver = {
> + .name = DRV_NAME,
> + .owner = THIS_MODULE,
> + },
> + .probe = c_can_probe,
> + .remove = c_can_remove,
> +};
> +
> +static int __init c_can_init(void)
> +{
> + return platform_driver_register(&c_can_driver);
> +}
> +module_init(c_can_init);
> +
> +static void __exit c_can_exit(void)
> +{
> + platform_driver_unregister(&c_can_driver);
> +}
> +module_exit(c_can_exit);
> +
> +MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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_______________________________________________
Socketcan-core mailing list
Socketcan-core-0fE9KPoRgkgATYTw5x5z8w@public.gmane.org
https://lists.berlios.de/mailman/listinfo/socketcan-core
^ permalink raw reply
* [PATCH] dev_alloc_name: fix kernel-doc formatting, typos, etc.
From: Randy Dunlap @ 2010-12-17 21:40 UTC (permalink / raw)
To: netdev; +Cc: davem
From: Randy Dunlap <randy.dunlap@oracle.com>
The '%' sign needs to be duplicated so that the kernel-doc tools
will print a '%' sign instead of just printed "ltd".
Also fixes some punctuation/grammar and formatting.
Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
---
net/core/dev.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
--- lnx-2637-rc6.orig/net/core/dev.c
+++ lnx-2637-rc6/net/core/dev.c
@@ -925,13 +925,14 @@ static int __dev_alloc_name(struct net *
* @dev: device
* @name: name format string
*
- * Passed a format string - eg "lt%d" it will try and find a suitable
+ * Passed a format string - e.g. "lt%%d", it will try to find a suitable
* id. It scans list of devices to build up a free map, then chooses
* the first empty slot. The caller must hold the dev_base or rtnl lock
* while allocating the name and adding the device in order to avoid
* duplicates.
- * Limited to bits_per_byte * page size devices (ie 32K on most platforms).
- * Returns the number of the unit assigned or a negative errno code.
+ * Limited to bits_per_byte * page size devices
+ * (i.e. 32K on most platforms).
+ * Returns: the number of the unit assigned or a negative errno code.
*/
int dev_alloc_name(struct net_device *dev, const char *name)
^ permalink raw reply
* [PATCHv4] fragment locally generated tunnel-mode IPSec6 packets as needed
From: David L Stevens @ 2010-12-17 21:42 UTC (permalink / raw)
To: Herbert Xu, davem; +Cc: netdev
This patch modifies IPsec6 to fragment IPv6 packets that are
locally generated as needed.
This version of the patch only fragments in tunnel mode, so that fragment
headers will not be obscured by ESP in transport mode.
Signed-off-by: David L Stevens <dlstevens@us.ibm.com>
diff -ruNp linux-2.6.36-rc8/include/net/ip6_route.h linux-2.6.36-rc8DLS/include/net/ip6_route.h
--- linux-2.6.36-rc8/include/net/ip6_route.h 2010-10-14 16:26:43.000000000 -0700
+++ linux-2.6.36-rc8DLS/include/net/ip6_route.h 2010-12-12 09:22:48.582141401 -0800
@@ -164,5 +164,15 @@ static inline int ipv6_unicast_destinati
return rt->rt6i_flags & RTF_LOCAL;
}
+int ip6_fragment(struct sk_buff *skb, int (*output)(struct sk_buff *));
+
+static inline int ip6_skb_dst_mtu(struct sk_buff *skb)
+{
+ struct ipv6_pinfo *np = skb->sk ? inet6_sk(skb->sk) : NULL;
+
+ return (np && np->pmtudisc == IPV6_PMTUDISC_PROBE) ?
+ skb_dst(skb)->dev->mtu : dst_mtu(skb_dst(skb));
+}
+
#endif
#endif
diff -ruNp linux-2.6.36-rc8/net/ipv6/ip6_output.c linux-2.6.36-rc8DLS/net/ipv6/ip6_output.c
--- linux-2.6.36-rc8/net/ipv6/ip6_output.c 2010-10-14 16:26:43.000000000 -0700
+++ linux-2.6.36-rc8DLS/net/ipv6/ip6_output.c 2010-12-14 09:51:45.260779308 -0800
@@ -56,7 +56,7 @@
#include <net/checksum.h>
#include <linux/mroute6.h>
-static int ip6_fragment(struct sk_buff *skb, int (*output)(struct sk_buff *));
+int ip6_fragment(struct sk_buff *skb, int (*output)(struct sk_buff *));
int __ip6_local_out(struct sk_buff *skb)
{
@@ -145,14 +145,6 @@ static int ip6_finish_output2(struct sk_
return -EINVAL;
}
-static inline int ip6_skb_dst_mtu(struct sk_buff *skb)
-{
- struct ipv6_pinfo *np = skb->sk ? inet6_sk(skb->sk) : NULL;
-
- return (np && np->pmtudisc == IPV6_PMTUDISC_PROBE) ?
- skb_dst(skb)->dev->mtu : dst_mtu(skb_dst(skb));
-}
-
static int ip6_finish_output(struct sk_buff *skb)
{
if ((skb->len > ip6_skb_dst_mtu(skb) && !skb_is_gso(skb)) ||
@@ -601,7 +593,7 @@ int ip6_find_1stfragopt(struct sk_buff *
return offset;
}
-static int ip6_fragment(struct sk_buff *skb, int (*output)(struct sk_buff *))
+int ip6_fragment(struct sk_buff *skb, int (*output)(struct sk_buff *))
{
struct sk_buff *frag;
struct rt6_info *rt = (struct rt6_info*)skb_dst(skb);
diff -ruNp linux-2.6.36-rc8/net/ipv6/xfrm6_output.c linux-2.6.36-rc8DLS/net/ipv6/xfrm6_output.c
--- linux-2.6.36-rc8/net/ipv6/xfrm6_output.c 2010-10-14 16:26:43.000000000 -0700
+++ linux-2.6.36-rc8DLS/net/ipv6/xfrm6_output.c 2010-12-17 09:28:40.426989866 -0800
@@ -17,6 +17,7 @@
#include <linux/netfilter_ipv6.h>
#include <net/dst.h>
#include <net/ipv6.h>
+#include <net/ip6_route.h>
#include <net/xfrm.h>
int xfrm6_find_1stfragopt(struct xfrm_state *x, struct sk_buff *skb,
@@ -88,8 +89,21 @@ static int xfrm6_output_finish(struct sk
return xfrm_output(skb);
}
+static int __xfrm6_output(struct sk_buff *skb)
+{
+ struct dst_entry *dst = skb_dst(skb);
+ struct xfrm_state *x = dst->xfrm;
+
+ if ((x && x->props.mode == XFRM_MODE_TUNNEL) &&
+ ((skb->len > ip6_skb_dst_mtu(skb) && !skb_is_gso(skb)) ||
+ dst_allfrag(skb_dst(skb)))) {
+ return ip6_fragment(skb, xfrm6_output_finish);
+ }
+ return xfrm6_output_finish(skb);
+}
+
int xfrm6_output(struct sk_buff *skb)
{
return NF_HOOK(NFPROTO_IPV6, NF_INET_POST_ROUTING, skb, NULL,
- skb_dst(skb)->dev, xfrm6_output_finish);
+ skb_dst(skb)->dev, __xfrm6_output);
}
^ permalink raw reply
* Re: [PATCH net-next-2.6 v2 1/1] can: c_can: Added support for Bosch C_CAN controller
From: Wolfgang Grandegger @ 2010-12-17 21:45 UTC (permalink / raw)
To: Marc Kleine-Budde
Cc: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <4D0BD744.5030609-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Hi Marc,
On 12/17/2010 10:33 PM, Marc Kleine-Budde wrote:
> On 12/15/2010 10:58 AM, Bhupesh Sharma wrote:
>> Bosch C_CAN controller is a full-CAN implementation which is compliant
>> to CAN protocol version 2.0 part A and B. Bosch C_CAN user manual can be
>> obtained from:
>> http://www.semiconductors.bosch.de/pdf/Users_Manual_C_CAN.pdf
>
> No time to do a real review, some comments and lots of nitpicking inline....
>
> regards, Marc
>
>>
>> This patch adds the support for this controller.
>> The following are the design choices made while writing the controller driver:
>> 1. Interface Register set IF1 has be used only in the current design.
>> 2. Out of the 32 Message objects available, 16 are kept aside for RX purposes
>> and the rest for TX purposes.
>> 3. NAPI implementation is such that both the TX and RX paths function in
>> polling mode.
>>
>> Changes since V1:
>> 1. Implemented C_CAN as a platform driver with means of providing the
>> platform details and register offsets which may vary for different SoCs
>> through platform data struct.
>> 2. Implemented NAPI.
>> 3. Removed memcpy calls globally.
>> 4. Implemented CAN_CTRLMODE_*
>> 5. Implemented and used priv->can.do_get_berr_counter.
>> 6. Implemented c_can registers as a struct instead of enum.
>> 7. Improved the TX path by implementing routines to get next Tx and echo msg
>> objects.
>>
>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
>> ---
>> drivers/net/can/Kconfig | 7 +
>> drivers/net/can/Makefile | 1 +
>> drivers/net/can/c_can.c | 1217 ++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 1225 insertions(+), 0 deletions(-)
>> create mode 100644 drivers/net/can/c_can.c
>>
>> diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
>> index 9d9e453..25d9d2e 100644
>> --- a/drivers/net/can/Kconfig
>> +++ b/drivers/net/can/Kconfig
>> @@ -41,6 +41,13 @@ config CAN_AT91
>> ---help---
>> This is a driver for the SoC CAN controller in Atmel's AT91SAM9263.
>>
>> +config CAN_C_CAN
>> + tristate "Bosch C_CAN controller"
>> + depends on CAN_DEV
>> + ---help---
>> + If you say yes to this option, support will be included for the
>> + Bosch C_CAN controller.
>> +
>> config CAN_TI_HECC
>> depends on CAN_DEV && ARCH_OMAP3
>> tristate "TI High End CAN Controller"
>> diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
>> index 0057537..b6cbe74 100644
>> --- a/drivers/net/can/Makefile
>> +++ b/drivers/net/can/Makefile
>> @@ -12,6 +12,7 @@ obj-y += usb/
>> obj-$(CONFIG_CAN_SJA1000) += sja1000/
>> obj-$(CONFIG_CAN_MSCAN) += mscan/
>> obj-$(CONFIG_CAN_AT91) += at91_can.o
>> +obj-$(CONFIG_CAN_C_CAN) += c_can.o
>> obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o
>> obj-$(CONFIG_CAN_MCP251X) += mcp251x.o
>> obj-$(CONFIG_CAN_BFIN) += bfin_can.o
>> diff --git a/drivers/net/can/c_can.c b/drivers/net/can/c_can.c
>> new file mode 100644
>> index 0000000..c281c17
>> --- /dev/null
>> +++ b/drivers/net/can/c_can.c
>> @@ -0,0 +1,1217 @@
>> +/*
>> + * CAN bus driver for Bosch C_CAN controller
>> + *
>> + * Copyright (C) 2010 ST Microelectronics
>> + * Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
>> + *
>> + * Borrowed heavily from the C_CAN driver originally written by:
>> + * Copyright (C) 2007
>> + * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
>> + * - Simon Kallweit, intefo AG <simon.kallweit-+G9qxTFKJT/tRgLqZ5aouw@public.gmane.org>
>> + *
>
> I recognize some stuff from the at91_can driver, too :)
>
>> + * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
>> + * Bosch C_CAN user manual can be obtained from:
>> + * http://www.semiconductors.bosch.de/pdf/Users_Manual_C_CAN.pdf
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/version.h>
>> +#include <linux/module.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/delay.h>
>> +#include <linux/netdevice.h>
>> +#include <linux/if_arp.h>
>> +#include <linux/if_ether.h>
>> +#include <linux/list.h>
>> +#include <linux/delay.h>
>> +#include <linux/workqueue.h>
>> +#include <linux/io.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/clk.h>
>> +
>> +#include <linux/can.h>
>> +#include <linux/can/dev.h>
>> +#include <linux/can/error.h>
>> +
>> +#define DRV_NAME "c_can"
>
> You can use KBUILD_MODNAME, no need to define DRV_NAME.
>
>> +
>> +/* control register */
>> +#define CONTROL_TEST (1 << 7)
>> +#define CONTROL_CCE (1 << 6)
>> +#define CONTROL_DISABLE_AR (1 << 5)
>> +#define CONTROL_ENABLE_AR (0 << 5)
>> +#define CONTROL_EIE (1 << 3)
>> +#define CONTROL_SIE (1 << 2)
>> +#define CONTROL_IE (1 << 1)
>> +#define CONTROL_INIT (1 << 0)
>> +
>> +/* test register */
>> +#define TEST_RX (1 << 7)
>> +#define TEST_TX1 (1 << 6)
>> +#define TEST_TX2 (1 << 5)
>> +#define TEST_LBACK (1 << 4)
>> +#define TEST_SILENT (1 << 3)
>> +#define TEST_BASIC (1 << 2)
>
> You can use BIT(n) instead of (1 << n).
>
>> +
>> +/* status register */
>> +#define STATUS_BOFF (1 << 7)
>> +#define STATUS_EWARN (1 << 6)
>> +#define STATUS_EPASS (1 << 5)
>> +#define STATUS_RXOK (1 << 4)
>> +#define STATUS_TXOK (1 << 3)
>> +#define STATUS_LEC_MASK 0x07
>> +#define LEC_STUFF_ERROR 1
>> +#define LEC_FORM_ERROR 2
>> +#define LEC_ACK_ERROR 3
>> +#define LEC_BIT1_ERROR 4
>> +#define LEC_BIT0_ERROR 5
>> +#define LEC_CRC_ERROR 6
>> +
>> +/* error counter register */
>> +#define ERR_COUNTER_TEC_MASK 0xff
>> +#define ERR_COUNTER_TEC_SHIFT 0x0
>
> nitpick, I'd just use a pure decimal 0 :)
>
>> +#define ERR_COUNTER_REC_SHIFT 8
>> +#define ERR_COUNTER_REC_MASK (0x7f << ERR_COUNTER_REC_SHIFT)
>> +#define ERR_COUNTER_RP_SHIFT 15
>> +#define ERR_COUNTER_RP_MASK (0x1 << ERR_COUNTER_RP_SHIFT)
>> +
>> +/* bit-timing register */
>> +#define BTR_BRP_MASK 0x3f
>> +#define BTR_BRP_SHIFT 0
>> +#define BTR_SJW_SHIFT 6
>> +#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
>> +#define BTR_TSEG1_SHIFT 8
>> +#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
>> +#define BTR_TSEG2_SHIFT 12
>> +#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
>> +
>> +/* brp extension register */
>> +#define BRP_EXT_BRPE_MASK 0x0f
>> +#define BRP_EXT_BRPE_SHIFT 0
>> +
>> +/* IFx command request */
>> +#define IF_COMR_BUSY (1 << 15)
>> +
>> +/* IFx command mask */
>> +#define IF_COMM_WR (1 << 7)
>> +#define IF_COMM_MASK (1 << 6)
>> +#define IF_COMM_ARB (1 << 5)
>> +#define IF_COMM_CONTROL (1 << 4)
>> +#define IF_COMM_CLR_INT_PND (1 << 3)
>> +#define IF_COMM_TXRQST (1 << 2)
>> +#define IF_COMM_DATAA (1 << 1)
>> +#define IF_COMM_DATAB (1 << 0)
>> +#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
>> + IF_COMM_CONTROL | IF_COMM_TXRQST | \
>> + IF_COMM_DATAA | IF_COMM_DATAB)
>> +
>> +/* IFx arbitration */
>> +#define IF_ARB_MSGVAL (1 << 15)
>> +#define IF_ARB_MSGXTD (1 << 14)
>> +#define IF_ARB_TRANSMIT (1 << 13)
>> +
>> +/* IFx message control */
>> +#define IF_MCONT_NEWDAT (1 << 15)
>> +#define IF_MCONT_MSGLST (1 << 14)
>> +#define IF_MCONT_INTPND (1 << 13)
>> +#define IF_MCONT_UMASK (1 << 12)
>> +#define IF_MCONT_TXIE (1 << 11)
>> +#define IF_MCONT_RXIE (1 << 10)
>> +#define IF_MCONT_RMTEN (1 << 9)
>> +#define IF_MCONT_TXRQST (1 << 8)
>> +#define IF_MCONT_EOB (1 << 7)
>> +
>> +/*
>> + * IFx register masks:
>> + * allow easy operation on 16-bit registers when the
>> + * argument is 32-bit instead
>> + */
>> +#define IFX_WRITE_LOW_16BIT(x) (x & 0xFFFF)
>> +#define IFX_WRITE_HIGH_16BIT(x) ((x & 0xFFFF0000) >> 16)
>> +
>> +/* message object split */
>> +#define C_CAN_NO_OF_OBJECTS 31
>> +#define C_CAN_MSG_OBJ_RX_NUM 16
>> +#define C_CAN_MSG_OBJ_TX_NUM 16
>> +
>> +#define C_CAN_MSG_OBJ_RX_FIRST 0
>> +#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
>> + C_CAN_MSG_OBJ_RX_NUM - 1)
>> +
>> +#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
>> +#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
>> + C_CAN_MSG_OBJ_TX_NUM - 1)
>> +#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
>> +#define RECEIVE_OBJECT_BITS 0x0000ffff
>> +
>> +/* status interrupt */
>> +#define STATUS_INTERRUPT 0x8000
>> +
>> +/* napi related */
>> +#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
>> +
>> +/* c_can IF registers */
>> +struct c_can_if_regs {
>> + u16 com_reg;
>> + u16 com_mask;
>> + u16 mask1;
>> + u16 mask2;
>> + u16 arb1;
>> + u16 arb2;
>> + u16 msg_cntrl;
>> + u16 data_a1;
>> + u16 data_a2;
>> + u16 data_b1;
>> + u16 data_b2;
>
> The later code _mighy_ be easier to read if you define data as an array
> of u16, but let's see...
>
>> + u16 _reserved[13];
>> +};
>> +
>> +/* c_can hardware registers */
>> +struct c_can_regs {
>> + u16 control;
>> + u16 status;
>> + u16 error_counter;
>> + u16 btr;
>> + u16 ir;
>> + u16 test;
>> + u16 brp_ext;
>> + u16 _reserved1;
>> + struct c_can_if_regs ifreg[2]; /* [0] = IF1 and [1] = IF2 */
>> + u16 _reserved2[8];
>> + u16 txrqst1;
>> + u16 txrqst2;
>> + u16 _reserved3[6];
>> + u16 newdat1;
>> + u16 newdat2;
>> + u16 _reserved4[6];
>> + u16 intpnd1;
>> + u16 intpnd2;
>> + u16 _reserved5[6];
>> + u16 msgval1;
>> + u16 msgval2;
>> + u16 _reserved6[6];
>> +};
>> +
>> +/*
>> + * c_can error types:
>> + * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
>> + */
>> +enum c_can_bus_error_types {
>> + C_CAN_NO_ERROR = 0,
>> + C_CAN_BUS_OFF,
>> + C_CAN_ERROR_WARNING,
>> + C_CAN_ERROR_PASSIVE
> ^
> please add a ","
>> +};
>> +
>> +enum c_can_interrupt_mode {
>> + ENABLE_MODULE_INTERRUPT = 0,
>> + DISABLE_MODULE_INTERRUPT,
>> + ENABLE_ALL_INTERRUPTS,
>> + DISABLE_ALL_INTERRUPTS
> same here
>> +};
>> +
>> +/* c_can private data structure */
>> +struct c_can_priv {
>> + struct can_priv can; /* must be the first member */
>> + struct napi_struct napi;
>> + struct net_device *dev;
>> + int tx_object;
>> + int current_status;
>> + int last_status;
>> + u16 (*read_reg) (struct c_can_priv *priv, void *reg);
>> + void (*write_reg) (struct c_can_priv *priv, void *reg, u16 val);
>> + struct c_can_regs __iomem *reg_base;
>> + unsigned long irq_flags; /* for request_irq() */
>> + unsigned int tx_next;
>> + unsigned int tx_echo;
>> + struct clk *clk;
>> +};
>> +
>> +static struct can_bittiming_const c_can_bittiming_const = {
>> + .name = DRV_NAME,
>
> use KBUILD_MODNAME here
>> + .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
>> + .tseg1_max = 16,
>> + .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
>> + .tseg2_max = 8,
>> + .sjw_max = 4,
>> + .brp_min = 1,
>> + .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
>> + .brp_inc = 1,
>> +};
>> +
>> +static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
>> +{
>> + return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
>> + C_CAN_MSG_OBJ_TX_FIRST;
>> +}
>> +
>> +static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
>> +{
>> + return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
>> + C_CAN_MSG_OBJ_TX_FIRST;
>> +}
>> +
>> +/* 16-bit c_can registers can be arranged differently in the memory
>> + * architecture of different implementations. For example: 16-bit
>> + * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
>> + * Handle the same by providing a common read/write interface.
>> + */
>
> /*
> * this is the preferred multi-line comment style,
> * please adjust
> */
>> +static u16 c_can_read_reg_aligned_to_16bit(void *reg)
>> +{
>> + return readw(reg);
>> +}
>> +
>> +static void c_can_write_reg_aligned_to_16bit(void *reg, u16 val)
>> +{
>> + writew(val, reg);
>> +}
>> +
>> +static u16 c_can_read_reg_aligned_to_32bit(struct c_can_priv *priv, void *reg)
>> +{
>> + return readw(reg + (u32)reg - (u32)priv->reg_base);
>
> as Wolfgang said not 64 bit safe.....what about casting the reg_base to
> void __iomem *?
You will get.
error: invalid operands to binary + (have ‘void *’ and ‘void *’)
>> +}
>> +
>> +static void c_can_write_reg_aligned_to_32bit(struct c_can_priv *priv,
>> + void *reg, u16 val)
>> +{
>> + writew(val, reg + (u32)reg - (u32)priv->reg_base);
>> +}
>> +
>> +static u32 c_can_read_reg32(struct c_can_priv *priv, void *reg)
>> +{
>> + u32 val = priv->read_reg(priv, reg);
>> + val |= ((u32) priv->read_reg(priv, reg + 2)) << 16;
>> + return val;
>> +}
>> +
>> +static inline int c_can_configure_interrupts(struct c_can_priv *priv,
>> + enum c_can_interrupt_mode intr_mode)
>> +{
>> + unsigned int cntrl_save = priv->read_reg(priv,
>> + &priv->reg_base->control);
>> +
>> + switch (intr_mode) {
>> + case ENABLE_MODULE_INTERRUPT:
>> + cntrl_save |= CONTROL_IE;
>> + break;
>> + case DISABLE_MODULE_INTERRUPT:
>> + cntrl_save &= ~CONTROL_IE;
>> + break;
>> + case ENABLE_ALL_INTERRUPTS:
>> + cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
>> + break;
>> + case DISABLE_ALL_INTERRUPTS:
>> + cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
>> + break;
>> + default:
>> + return -EOPNOTSUPP;
>> + }
>> +
>> + priv->write_reg(priv, &priv->reg_base->control, cntrl_save);
>> +
>> + return 0;
>> +}
>> +
>> +static inline int c_can_object_get(struct net_device *dev,
>> + int iface, int objno, int mask)
>> +{
>> + struct c_can_priv *priv = netdev_priv(dev);
>> + int timeout = (6 / priv->can.clock.freq);
>> +
>> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].com_mask,
>> + IFX_WRITE_LOW_16BIT(mask));
>> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].com_reg,
>> + IFX_WRITE_LOW_16BIT(objno + 1));
>> +
>> + /* as per specs, after writting the message object number in the
>> + * IF command request register the transfer b/w interface
>> + * register and message RAM must be complete in 6 CAN-CLK
>> + * period. The delay accounts for the same
>> + */
>> + udelay(timeout);
>> + if ((priv->read_reg(priv, &priv->reg_base->ifreg[iface].com_reg)) &
>> + IF_COMR_BUSY) {
>> + dev_info(dev->dev.parent, "timed out in object get\n");
>> + return -ETIMEDOUT;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static inline int c_can_object_put(struct net_device *dev,
>> + int iface, int objno, int mask)
>> +{
>> + struct c_can_priv *priv = netdev_priv(dev);
>> + int timeout = (6 / priv->can.clock.freq);
>> +
>> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].com_mask,
>> + (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
>> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].com_reg,
>> + IFX_WRITE_LOW_16BIT(objno + 1));
>> +
>> + /* as per specs, after writting the message object number in the
>> + * IF command request register the transfer b/w interface
>> + * register and message RAM must be complete in 6 CAN-CLK
>> + * period. The delay accounts for the same
>> + */
>> + udelay(timeout);
>> + if ((priv->read_reg(priv, &priv->reg_base->ifreg[iface].com_reg)) &
>> + IF_COMR_BUSY) {
>> + dev_info(dev->dev.parent, "timed out in object put\n");
>> + return -ETIMEDOUT;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +int c_can_write_msg_object(struct net_device *dev,
>> + int iface, struct can_frame *frame, int objno)
>> +{
>> + u16 flags = 0;
>> + unsigned int id;
>> + struct c_can_priv *priv = netdev_priv(dev);
>> +
>> + if (frame->can_id & CAN_EFF_FLAG) {
>> + id = frame->can_id & CAN_EFF_MASK;
>> + flags |= IF_ARB_MSGXTD;
>> + } else
>> + id = ((frame->can_id & CAN_SFF_MASK) << 18);
>> +
>> + if (!(frame->can_id & CAN_RTR_FLAG))
>> + flags |= IF_ARB_TRANSMIT;
>> +
>> + flags |= IF_ARB_MSGVAL;
>> +
>> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].arb1,
>> + IFX_WRITE_LOW_16BIT(id));
>> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].arb2, flags |
>> + IFX_WRITE_HIGH_16BIT(id));
>> +
>> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].data_a1,
>> + (*(u16 *)(frame->data)));
>> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].data_a2,
>> + (*(u32 *)(frame->data)) >> 16);
>> +
>> + if (frame->can_dlc > 4) {
>> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].data_b1,
>> + (*(u16 *)(frame->data + 4)));
>> + priv->write_reg(priv, &priv->reg_base->ifreg[iface].data_b2,
>> + (*(u32 *)(frame->data + 4)) >> 16);
>> + } else
>> + *(u32 *)(frame->data + 4) = 0;
>
> look at the pch can driver, it uses an array for ifreg->data and is
> endianess safe.
Marc, you did review the pch_can driver. Do you think as well that the
CAN core used for the PCH is C_CAN?
Wolfgang.
^ permalink raw reply
* Re: [PATCH] dev_alloc_name: fix kernel-doc formatting, typos, etc.
From: Stephen Hemminger @ 2010-12-17 21:53 UTC (permalink / raw)
To: Randy Dunlap; +Cc: netdev, davem
In-Reply-To: <20101217134046.61eb94dd.randy.dunlap@oracle.com>
On Fri, 17 Dec 2010 13:40:46 -0800
Randy Dunlap <randy.dunlap@oracle.com> wrote:
> - * Passed a format string - eg "lt%d" it will try and find a suitable
> + * Passed a format string - e.g. "lt%%d", it will try to find a suitable
This is wrong.
The obvious case of:
alloc_etherdev() ends up calling __dev_alloc_name with "eth%d"
in fact __dev_alloc_name called with "lt%%d" will return -EINVAL
--
^ permalink raw reply
* Re: [PATCH] dev_alloc_name: fix kernel-doc formatting, typos, etc.
From: Randy Dunlap @ 2010-12-17 22:00 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: netdev, davem
In-Reply-To: <20101217135355.1f88ffff@nehalam>
On Fri, 17 Dec 2010 13:53:55 -0800 Stephen Hemminger wrote:
> On Fri, 17 Dec 2010 13:40:46 -0800
> Randy Dunlap <randy.dunlap@oracle.com> wrote:
>
> > - * Passed a format string - eg "lt%d" it will try and find a suitable
> > + * Passed a format string - e.g. "lt%%d", it will try to find a suitable
>
> This is wrong.
> The obvious case of:
> alloc_etherdev() ends up calling __dev_alloc_name with "eth%d"
> in fact __dev_alloc_name called with "lt%%d" will return -EINVAL
OK, thanks.
I'll see if a tool fix is possible.
---
~Randy
*** Remember to use Documentation/SubmitChecklist when testing your code ***
^ permalink raw reply
* [PATCH] tcp: use RTAX_CWND for outgoing connections properly
From: Jiri Kosina @ 2010-12-17 22:14 UTC (permalink / raw)
To: David Miller, netdev, Eric Dumazet; +Cc: linux-kernel, Vojtech Pavlik
For outgoing connections, the initial value of cwnd is always set to 2 (in
tcp_v4_init_sock()) regardless of setting of RTAX_CWND. For incoming
connections, this is handled properly in tcp_init_metrics().
As a result of this, Linux TCP stack always uses cwnd == 2 at the beginning of
outgoing TCP session (i.e. waits for ACK after 2 packets once the connection
has been established) and grows it in accordance with slow-start algorithm
only after it receives ACK for first two packets.
When slow-start triggers later during the connection (e.g. after idle),
cwnd is properly re-initialized to RTAX_CWND value (if specified) through
tcp_cwnd_restart() -> tcp_init_cwnd().
Initialize tp->snd_cwnd properly so that RTAX_CWND value is being used
also in the slow-start phase for the first packets in the connection.
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
---
net/ipv4/tcp_output.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 61c2463..6dbc55b 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -2572,6 +2572,8 @@ static void tcp_connect_init(struct sock *sk)
&rcv_wscale,
dst_metric(dst, RTAX_INITRWND));
+ tp->snd_cwnd = tcp_init_cwnd(tp, dst);
+
tp->rx_opt.rcv_wscale = rcv_wscale;
tp->rcv_ssthresh = tp->rcv_wnd;
--
1.7.3.1
^ permalink raw reply related
* [PATCH] net/e1000e : Fix to use dev_kfree_skb_any() instead of dev_kfree_skb() in _jumbo_rx_irq
From: Prasanna Panchamukhi @ 2010-12-17 22:31 UTC (permalink / raw)
To: e1000-devel, netdev
Several "Warning: kfree_skb on hard IRQ" messages have been observed from
the net/e1000e driver, e1000_clean_jumbo_rx_irq() routine calling
dev_kfree_skb(). This patch fixes the above warning messages by
calling dev_kfree_skb_any() instead of dev_kfree_skb().
Signed-off-by: Prasanna S. Panchamukhi<prasanna.panchamukhi@riverbed.com>
---
drivers/net/e1000e/netdev.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index c4ca162..1068abc 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -1320,7 +1320,7 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
/* an error means any chain goes out the window
* too */
if (rx_ring->rx_skb_top)
- dev_kfree_skb(rx_ring->rx_skb_top);
+ dev_kfree_skb_any(rx_ring->rx_skb_top);
rx_ring->rx_skb_top = NULL;
goto next_desc;
}
@@ -1393,7 +1393,7 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
/* eth type trans needs skb->data to point to something */
if (!pskb_may_pull(skb, ETH_HLEN)) {
e_err("pskb_may_pull failed.\n");
- dev_kfree_skb(skb);
+ dev_kfree_skb_any(skb);
goto next_desc;
}
--
1.7.0.4
------------------------------------------------------------------------------
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^ permalink raw reply related
* Re: "x86: allocate space within a region top-down" causes bar0 access issue
From: Jon Mason @ 2010-12-17 23:12 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
Ramkrishna Vepa
In-Reply-To: <201012171316.12761.bjorn.helgaas@hp.com>
On Fri, Dec 17, 2010 at 12:16:12PM -0800, Bjorn Helgaas wrote:
> On Friday, December 17, 2010 12:44:58 pm Jon Mason wrote:
> > The following patch is causing problem with the vxge driver/adapter on
> > HP x86-64 systems. Reads to bar0 to return 0xffffffffffffffff instead
> > of their intended value. This prevents the vxge module from loading
> > by failing sanity checks in the driver for certain values in bar0. We
> > are not seeing any issues with this patch on non-HP systems in our
> > lab.
> >
> > Can this patch be removed from 2.6.37 until a better solution can be
> > found?
>
> There were several issues related to that patch, and it's about to
> be reverted. I am curious about the failure you're seeing, though,
> and I'd like to understand the cause and make sure it's one of the
> issues I've already investigated.
>
> Can you send me the complete dmesg log of a failing boot?
>
> Thanks,
> Bjorn
Below is the dmesg of a failing system.
Thanks,
Jon
Initializing cgroup subsys cpuset
Initializing cgroup subsys cpu
Linux version 2.6.37-rc1-5-default (root@SuSE-11) (gcc version 4.3.2 [gcc-4_3-branch revision 141291] (SUSE Linux) ) #2 SMP Wed Dec 15 14:33:28 PST 2010
Command line: root=/dev/disk/by-id/ata-GB0160CAABV_5RX52XN5-part2 resume=/dev/disk/by-id/ata-GB0160CAABV_5RX52XN5-part1 splash=silent crashkernel=256M-:128M@16M vga=0x317
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 00000000dff90000 (usable)
BIOS-e820: 00000000dff9e000 - 00000000dffa0000 type 9
BIOS-e820: 00000000dffa0000 - 00000000dffae000 (ACPI data)
BIOS-e820: 00000000dffae000 - 00000000dffe0000 (ACPI NVS)
BIOS-e820: 00000000dffe0000 - 00000000dffee000 (reserved)
BIOS-e820: 00000000dfff0000 - 00000000f0000000 (reserved)
BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
BIOS-e820: 00000000ffe00000 - 0000000100000000 (reserved)
BIOS-e820: 0000000100000000 - 0000000220000000 (usable)
NX (Execute Disable) protection: active
DMI present.
DMI: ProLiant ML150 G5/ProLiant ML150 G5, BIOS O17 01/15/2009
e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved)
e820 remove range: 00000000000a0000 - 0000000000100000 (usable)
No AGP bridge found
last_pfn = 0x220000 max_arch_pfn = 0x400000000
MTRR default type: uncachable
MTRR fixed ranges enabled:
00000-9FFFF write-back
A0000-DFFFF uncachable
E0000-EFFFF write-through
F0000-FFFFF write-protect
MTRR variable ranges enabled:
0 base 0000000000 mask 3E00000000 write-back
1 base 0200000000 mask 3FE0000000 write-back
2 base 00E0000000 mask 3FE0000000 uncachable
3 disabled
4 disabled
5 disabled
6 disabled
7 disabled
x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
e820 update range: 00000000e0000000 - 0000000100000000 (usable) ==> (reserved)
last_pfn = 0xdff90 max_arch_pfn = 0x400000000
found SMP MP-table at [ffff8800000ff780] ff780
initial memory mapped : 0 - 20000000
init_memory_mapping: 0000000000000000-00000000dff90000
0000000000 - 00dfe00000 page 2M
00dfe00000 - 00dff90000 page 4k
kernel direct mapping tables up to dff90000 @ 1fffa000-20000000
init_memory_mapping: 0000000100000000-0000000220000000
0100000000 - 0220000000 page 2M
kernel direct mapping tables up to 220000000 @ dff86000-dff90000
RAMDISK: 37406000 - 37ff0000
crashkernel reservation failed - memory is in use.
ACPI: RSDP 00000000000f9da0 00024 (v02 HP )
ACPI: XSDT 00000000dffa0100 0007C (v01 HP ProLiant 20090115 HP 00000097)
ACPI: FACP 00000000dffa0290 000F4 (v04 HP ProLiant 20090115 HP 00000097)
ACPI: DSDT 00000000dffa0690 04EE4 (v02 HP ProLiant 00000077 INTL 20051117)
ACPI: FACS 00000000dffae000 00040
ACPI: APIC 00000000dffa0390 00092 (v02 HP ProLiant 20090115 HP 00000097)
ACPI: MCFG 00000000dffa0480 0003C (v01 HP ProLiant 20090115 HP 00000097)
ACPI: SPMI 00000000dffa04c0 00041 (v05 HP ProLiant 20090115 HP 00000097)
ACPI: SLIC 00000000dffa0510 00176 (v01 HP ProLiant 20090115 HP 00000097)
ACPI: OEMB 00000000dffae040 00071 (v01 HP ProLiant 20090115 HP 00000097)
ACPI: HPET 00000000dffa5580 00038 (v01 HP ProLiant 20090115 HP 00000097)
ACPI: EINJ 00000000dffa55c0 00130 (v01 HP ProLiant 20090115 HP 00000097)
ACPI: BERT 00000000dffa5750 00030 (v01 HP ProLiant 20090115 HP 00000097)
ACPI: ERST 00000000dffa5780 001B0 (v01 HP ProLiant 20090115 HP 00000097)
ACPI: HEST 00000000dffa5930 000A8 (v01 HP ProLiant 20090115 HP 00000097)
ACPI: Local APIC address 0xfee00000
No NUMA configuration found
Faking a node at 0000000000000000-0000000220000000
Initmem setup node 0 0000000000000000-0000000220000000
NODE_DATA [000000021ffd9000 - 000000021fffffff]
[ffffea0000000000-ffffea00077fffff] PMD -> [ffff880217e00000-ffff88021effffff] on node 0
Zone PFN ranges:
DMA 0x00000010 -> 0x00001000
DMA32 0x00001000 -> 0x00100000
Normal 0x00100000 -> 0x00220000
Movable zone start PFN for each node
early_node_map[3] active PFN ranges
0: 0x00000010 -> 0x0000009f
0: 0x00000100 -> 0x000dff90
0: 0x00100000 -> 0x00220000
On node 0 totalpages: 2096927
DMA zone: 56 pages used for memmap
DMA zone: 6 pages reserved
DMA zone: 3921 pages, LIFO batch:0
DMA32 zone: 14280 pages used for memmap
DMA32 zone: 899016 pages, LIFO batch:31
Normal zone: 16128 pages used for memmap
Normal zone: 1163520 pages, LIFO batch:31
ACPI: PM-Timer IO Port: 0x808
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
ACPI: LAPIC (acpi_id[0x02] lapic_id[0x01] enabled)
ACPI: LAPIC (acpi_id[0x03] lapic_id[0x02] enabled)
ACPI: LAPIC (acpi_id[0x04] lapic_id[0x03] enabled)
ACPI: LAPIC (acpi_id[0x05] lapic_id[0x84] disabled)
ACPI: LAPIC (acpi_id[0x06] lapic_id[0x85] disabled)
ACPI: LAPIC (acpi_id[0x07] lapic_id[0x86] disabled)
ACPI: LAPIC (acpi_id[0x08] lapic_id[0x87] disabled)
ACPI: LAPIC_NMI (acpi_id[0xff] high dfl lint[0x1])
ACPI: IOAPIC (id[0x04] address[0xfec00000] gsi_base[0])
IOAPIC[0]: apic_id 4, version 32, address 0xfec00000, GSI 0-23
ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
ACPI: IRQ0 used by override.
ACPI: IRQ2 used by override.
ACPI: IRQ9 used by override.
Using ACPI (MADT) for SMP configuration information
ACPI: HPET id: 0x8086a301 base: 0xfed00000
SMP: Allowing 8 CPUs, 4 hotplug CPUs
nr_irqs_gsi: 40
PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
PM: Registered nosave memory: 00000000000a0000 - 00000000000e0000
PM: Registered nosave memory: 00000000000e0000 - 0000000000100000
PM: Registered nosave memory: 00000000dff90000 - 00000000dff9e000
PM: Registered nosave memory: 00000000dff9e000 - 00000000dffa0000
PM: Registered nosave memory: 00000000dffa0000 - 00000000dffae000
PM: Registered nosave memory: 00000000dffae000 - 00000000dffe0000
PM: Registered nosave memory: 00000000dffe0000 - 00000000dffee000
PM: Registered nosave memory: 00000000dffee000 - 00000000dfff0000
PM: Registered nosave memory: 00000000dfff0000 - 00000000f0000000
PM: Registered nosave memory: 00000000f0000000 - 00000000fee00000
PM: Registered nosave memory: 00000000fee00000 - 00000000fee01000
PM: Registered nosave memory: 00000000fee01000 - 00000000ffe00000
PM: Registered nosave memory: 00000000ffe00000 - 0000000100000000
Allocating PCI resources starting at f0000000 (gap: f0000000:ee00000)
setup_percpu: NR_CPUS:4096 nr_cpumask_bits:8 nr_cpu_ids:8 nr_node_ids:1
PERCPU: Embedded 27 pages/cpu @ffff8800dfc00000 s79168 r8192 d23232 u262144
pcpu-alloc: s79168 r8192 d23232 u262144 alloc=1*2097152
pcpu-alloc: [0] 0 1 2 3 4 5 6 7
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 2066457
Policy zone: Normal
Kernel command line: root=/dev/disk/by-id/ata-GB0160CAABV_5RX52XN5-part2 resume=/dev/disk/by-id/ata-GB0160CAABV_5RX52XN5-part1 splash=silent crashkernel=256M-:128M@16M vga=0x317
PID hash table entries: 4096 (order: 3, 32768 bytes)
Checking aperture...
No AGP bridge found
Memory: 8110212k/8912896k available (2942k kernel code, 525188k absent, 277496k reserved, 5969k data, 1260k init)
Hierarchical RCU implementation.
NR_IRQS:4352
Extended CMOS year: 2000
Console: colour dummy device 80x25
console [tty0] enabled
allocated 83886080 bytes of page_cgroup
please try 'cgroup_disable=memory' option if you don't want memory cgroups
hpet clockevent registered
Fast TSC calibration using PIT
Detected 2493.477 MHz processor.
Calibrating delay loop (skipped), value calculated using timer frequency.. 4986.95 BogoMIPS (lpj=9973908)
pid_max: default: 32768 minimum: 301
Security Framework initialized
SELinux: Disabled at boot.
AppArmor: AppArmor disabled by boot time parameter
Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
Mount-cache hash table entries: 256
Initializing cgroup subsys ns
ns_cgroup deprecated: consider using the 'clone_children' flag without the ns_cgroup.
Initializing cgroup subsys cpuacct
Initializing cgroup subsys memory
Initializing cgroup subsys devices
Initializing cgroup subsys freezer
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 0
mce: CPU supports 6 MCE banks
CPU0: Thermal monitoring enabled (TM2)
using mwait in idle threads.
Performance Events: PEBS fmt0+, Core2 events, Intel PMU driver.
... version: 2
... bit width: 40
... generic registers: 2
... value mask: 000000ffffffffff
... max period: 000000007fffffff
... fixed-purpose events: 3
... event mask: 0000000700000003
ACPI: Core revision 20101013
Setting APIC routing to flat
..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
CPU0: Intel(R) Xeon(R) CPU E5420 @ 2.50GHz stepping 06
Booting Node 0, Processors #1 #2 #3
Brought up 4 CPUs
Total of 4 processors activated (19949.50 BogoMIPS).
NET: Registered protocol family 16
ACPI: bus type pci registered
PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820
PCI: Using configuration type 1 for base access
bio: create slab <bio-0> at 0
ACPI: EC: Look up EC in DSDT
ACPI: Executed 1 blocks of module-level executable AML code
ACPI: Interpreter enabled
ACPI: (supports S0 S4 S5)
ACPI: Using IOAPIC for interrupt routing
PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
pci_root PNP0A08:00: host bridge window [io 0x0000-0x0bff]
pci_root PNP0A08:00: host bridge window [io 0x0d00-0xffff]
pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff]
pci_root PNP0A08:00: host bridge window [mem 0x000d0000-0x000dffff]
pci_root PNP0A08:00: host bridge window [mem 0xf0000000-0xffffffff]
pci 0000:00:00.0: [8086:65c0] type 0 class 0x000600
pci 0000:00:00.0: PME# supported from D0 D3hot D3cold
pci 0000:00:00.0: PME# disabled
pci 0000:00:02.0: [8086:65e2] type 1 class 0x000604
pci 0000:00:02.0: PME# supported from D0 D3hot D3cold
pci 0000:00:02.0: PME# disabled
pci 0000:00:03.0: [8086:65e3] type 1 class 0x000604
pci 0000:00:03.0: PME# supported from D0 D3hot D3cold
pci 0000:00:03.0: PME# disabled
pci 0000:00:04.0: [8086:65f8] type 1 class 0x000604
pci 0000:00:04.0: PME# supported from D0 D3hot D3cold
pci 0000:00:04.0: PME# disabled
pci 0000:00:05.0: [8086:65e5] type 1 class 0x000604
pci 0000:00:05.0: PME# supported from D0 D3hot D3cold
pci 0000:00:05.0: PME# disabled
pci 0000:00:06.0: [8086:65f9] type 1 class 0x000604
pci 0000:00:06.0: PME# supported from D0 D3hot D3cold
pci 0000:00:06.0: PME# disabled
pci 0000:00:07.0: [8086:65e7] type 1 class 0x000604
pci 0000:00:07.0: PME# supported from D0 D3hot D3cold
pci 0000:00:07.0: PME# disabled
pci 0000:00:10.0: [8086:65f0] type 0 class 0x000600
pci 0000:00:10.1: [8086:65f0] type 0 class 0x000600
pci 0000:00:10.2: [8086:65f0] type 0 class 0x000600
pci 0000:00:11.0: [8086:65f1] type 0 class 0x000600
pci 0000:00:13.0: [8086:65f3] type 0 class 0x000600
pci 0000:00:15.0: [8086:65f5] type 0 class 0x000600
pci 0000:00:16.0: [8086:65f6] type 0 class 0x000600
pci 0000:00:1a.0: [8086:2937] type 0 class 0x000c03
pci 0000:00:1a.0: reg 20: [io 0xe800-0xe81f]
pci 0000:00:1a.1: [8086:2938] type 0 class 0x000c03
pci 0000:00:1a.1: reg 20: [io 0xe880-0xe89f]
pci 0000:00:1a.2: [8086:2939] type 0 class 0x000c03
pci 0000:00:1a.2: reg 20: [io 0xec00-0xec1f]
pci 0000:00:1a.7: [8086:293c] type 0 class 0x000c03
pci 0000:00:1a.7: reg 10: [mem 0xfcdffc00-0xfcdfffff]
pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold
pci 0000:00:1a.7: PME# disabled
pci 0000:00:1c.0: [8086:2940] type 1 class 0x000604
pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
pci 0000:00:1c.0: PME# disabled
pci 0000:00:1c.4: [8086:2948] type 1 class 0x000604
pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
pci 0000:00:1c.4: PME# disabled
pci 0000:00:1c.5: [8086:294a] type 1 class 0x000604
pci 0000:00:1c.5: PME# supported from D0 D3hot D3cold
pci 0000:00:1c.5: PME# disabled
pci 0000:00:1d.0: [8086:2934] type 0 class 0x000c03
pci 0000:00:1d.0: reg 20: [io 0xe080-0xe09f]
pci 0000:00:1d.1: [8086:2935] type 0 class 0x000c03
pci 0000:00:1d.1: reg 20: [io 0xe400-0xe41f]
pci 0000:00:1d.2: [8086:2936] type 0 class 0x000c03
pci 0000:00:1d.2: reg 20: [io 0xe480-0xe49f]
pci 0000:00:1d.7: [8086:293a] type 0 class 0x000c03
pci 0000:00:1d.7: reg 10: [mem 0xfcdff800-0xfcdffbff]
pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
pci 0000:00:1d.7: PME# disabled
pci 0000:00:1e.0: [8086:244e] type 1 class 0x000604
pci 0000:00:1f.0: [8086:2916] type 0 class 0x000601
pci 0000:00:1f.0: quirk: [io 0x0800-0x087f] claimed by ICH6 ACPI/GPIO/TCO
pci 0000:00:1f.0: quirk: [io 0x0480-0x04bf] claimed by ICH6 GPIO
pci 0000:00:1f.0: ICH7 LPC Generic IO decode 4 PIO at 0ca0 (mask 0007)
pci 0000:00:1f.2: [8086:2920] type 0 class 0x000101
pci 0000:00:1f.2: reg 10: [io 0x0000-0x0007]
pci 0000:00:1f.2: reg 14: [io 0x0000-0x0003]
pci 0000:00:1f.2: reg 18: [io 0x0000-0x0007]
pci 0000:00:1f.2: reg 1c: [io 0x0000-0x0003]
pci 0000:00:1f.2: reg 20: [io 0xff90-0xff9f]
pci 0000:00:1f.2: reg 24: [io 0xffa0-0xffaf]
pci 0000:00:1f.3: [8086:2930] type 0 class 0x000c05
pci 0000:00:1f.3: reg 10: [mem 0xffffffc00-0xffffffcff 64bit]
pci 0000:00:1f.3: reg 20: [io 0x0400-0x041f]
pci 0000:00:1f.5: [8086:2926] type 0 class 0x000101
pci 0000:00:1f.5: reg 10: [io 0xe000-0xe007]
pci 0000:00:1f.5: reg 14: [io 0xdc00-0xdc03]
pci 0000:00:1f.5: reg 18: [io 0xd880-0xd887]
pci 0000:00:1f.5: reg 1c: [io 0xd800-0xd803]
pci 0000:00:1f.5: reg 20: [io 0xd480-0xd48f]
pci 0000:00:1f.5: reg 24: [io 0xd400-0xd40f]
pci 0000:00:02.0: PCI bridge to [bus 01-01]
pci 0000:00:02.0: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:00:02.0: bridge window [mem 0xfff00000-0x000fffff] (disabled)
pci 0000:00:02.0: bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
pci 0000:00:03.0: PCI bridge to [bus 02-02]
pci 0000:00:03.0: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:00:03.0: bridge window [mem 0xfff00000-0x000fffff] (disabled)
pci 0000:00:03.0: bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
pci 0000:00:04.0: PCI bridge to [bus 03-03]
pci 0000:00:04.0: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:00:04.0: bridge window [mem 0xfff00000-0x000fffff] (disabled)
pci 0000:00:04.0: bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
pci 0000:00:05.0: PCI bridge to [bus 04-04]
pci 0000:00:05.0: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:00:05.0: bridge window [mem 0xfff00000-0x000fffff] (disabled)
pci 0000:00:05.0: bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
pci 0000:05:00.0: [17d5:5833] type 0 class 0x000200
pci 0000:05:00.0: reg 10: [mem 0xfff000000-0xfff7fffff 64bit pref]
pci 0000:05:00.0: reg 18: [mem 0xfffcfe000-0xfffcfffff 64bit pref]
pci 0000:05:00.0: reg 20: [mem 0xfffcfc000-0xfffcfdfff 64bit pref]
pci 0000:05:00.0: reg 30: [mem 0xfce80000-0xfcefffff pref]
pci 0000:05:00.0: supports D1 D2
pci 0000:05:00.0: PME# supported from D0 D1 D2
pci 0000:05:00.0: PME# disabled
pci 0000:00:06.0: PCI bridge to [bus 05-05]
pci 0000:00:06.0: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:00:06.0: bridge window [mem 0xfce00000-0xfcefffff]
pci 0000:00:06.0: bridge window [mem 0xfff000000-0xfffcfffff 64bit pref]
pci 0000:00:07.0: PCI bridge to [bus 06-06]
pci 0000:00:07.0: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:00:07.0: bridge window [mem 0xfff00000-0x000fffff] (disabled)
pci 0000:00:07.0: bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
pci 0000:09:00.0: [1033:0125] type 1 class 0x000604
pci 0000:09:00.0: supports D1
pci 0000:09:00.0: PME# supported from D0 D1 D3hot D3cold
pci 0000:09:00.0: PME# disabled
pci 0000:09:00.1: [1033:0125] type 1 class 0x000604
pci 0000:09:00.1: reg 10: [mem 0xfdeffc00-0xfdeffc7f 64bit]
pci 0000:09:00.1: supports D1
pci 0000:09:00.1: PME# supported from D0 D1 D3hot D3cold
pci 0000:09:00.1: PME# disabled
pci 0000:09:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'
pci 0000:00:1c.0: PCI bridge to [bus 09-0b]
pci 0000:00:1c.0: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:00:1c.0: bridge window [mem 0xfde00000-0xfdffffff]
pci 0000:00:1c.0: bridge window [mem 0xfffd00000-0xfffefffff 64bit pref]
pci 0000:0b:04.0: [17d5:5832] type 0 class 0x000200
pci 0000:0b:04.0: reg 10: [mem 0xfffef8000-0xfffefffff 64bit pref]
pci 0000:0b:04.0: reg 18: [mem 0xfffd00000-0xfffdfffff 64bit pref]
pci 0000:0b:04.0: reg 20: [mem 0xfffef7800-0xfffef7fff 64bit pref]
pci 0000:0b:04.0: reg 30: [mem 0xfdf00000-0xfdffffff pref]
pci 0000:0b:04.0: supports D1 D2
pci 0000:0b:04.0: PME# supported from D0 D1 D2 D3hot
pci 0000:0b:04.0: PME# disabled
pci 0000:09:00.0: PCI bridge to [bus 0b-0b]
pci 0000:09:00.0: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:09:00.0: bridge window [mem 0xfdf00000-0xfdffffff]
pci 0000:09:00.0: bridge window [mem 0xfffd00000-0xfffefffff 64bit pref]
pci 0000:09:00.1: PCI bridge to [bus 0a-0a]
pci 0000:09:00.1: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:09:00.1: bridge window [mem 0xfff00000-0x000fffff] (disabled)
pci 0000:09:00.1: bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
pci 0000:08:00.0: [102b:0522] type 0 class 0x000300
pci 0000:08:00.0: reg 10: [mem 0xfb000000-0xfbffffff pref]
pci 0000:08:00.0: reg 14: [mem 0xfddfc000-0xfddfffff]
pci 0000:08:00.0: reg 18: [mem 0xfd000000-0xfd7fffff]
pci 0000:08:00.0: reg 30: [mem 0xfdde0000-0xfddeffff pref]
pci 0000:08:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'
pci 0000:00:1c.4: PCI bridge to [bus 08-08]
pci 0000:00:1c.4: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:00:1c.4: bridge window [mem 0xfd000000-0xfddfffff]
pci 0000:00:1c.4: bridge window [mem 0xfb000000-0xfbffffff 64bit pref]
pci 0000:07:00.0: [14e4:165a] type 0 class 0x000200
pci 0000:07:00.0: reg 10: [mem 0xfcff0000-0xfcffffff 64bit]
pci 0000:07:00.0: PME# supported from D3hot D3cold
pci 0000:07:00.0: PME# disabled
pci 0000:00:1c.5: PCI bridge to [bus 07-07]
pci 0000:00:1c.5: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:00:1c.5: bridge window [mem 0xfcf00000-0xfcffffff]
pci 0000:00:1c.5: bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
pci 0000:00:1e.0: PCI bridge to [bus 0c-0c] (subtractive decode)
pci 0000:00:1e.0: bridge window [io 0xf000-0x0000] (disabled)
pci 0000:00:1e.0: bridge window [mem 0xfff00000-0x000fffff] (disabled)
pci 0000:00:1e.0: bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
pci 0000:00:1e.0: bridge window [io 0x0000-0x0bff] (subtractive decode)
pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode)
pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
pci 0000:00:1e.0: bridge window [mem 0x000d0000-0x000dffff] (subtractive decode)
pci 0000:00:1e.0: bridge window [mem 0xf0000000-0xffffffff] (subtractive decode)
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.NPE2._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.NPE3._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.NPE4._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.NPE6._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0P1._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0PE._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0P3._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.BCM_._PRT]
ACPI: PCI Interrupt Link [LNKA] (IRQs 5 6 7 10 *11 12 14 15)
ACPI: PCI Interrupt Link [LNKB] (IRQs 5 6 7 *10 11 12 14 15)
ACPI: PCI Interrupt Link [LNKC] (IRQs *5 6 7 10 11 12 14 15)
ACPI: PCI Interrupt Link [LNKD] (IRQs *3 4 6 10 11 12 14 15)
ACPI: PCI Interrupt Link [LNKE] (IRQs 5 6 7 10 11 12 14 15) *0, disabled.
ACPI: PCI Interrupt Link [LNKF] (IRQs 5 6 *7 10 11 12 14 15)
ACPI: PCI Interrupt Link [LNKG] (IRQs 5 6 7 10 11 12 14 15) *0, disabled.
ACPI: PCI Interrupt Link [LNKH] (IRQs 5 *6 7 10 11 12 14 15)
vgaarb: device added: PCI:0000:08:00.0,decodes=io+mem,owns=io+mem,locks=none
vgaarb: loaded
PCI: Using ACPI for IRQ routing
PCI: pci_cache_line_size set to 64 bytes
pci 0000:00:06.0: no compatible bridge window for [mem 0xfff000000-0xfffcfffff 64bit pref]
pci 0000:00:1c.0: no compatible bridge window for [mem 0xfffd00000-0xfffefffff 64bit pref]
pci 0000:09:00.0: no compatible bridge window for [mem 0xfffd00000-0xfffefffff 64bit pref]
pci 0000:00:1f.3: no compatible bridge window for [mem 0xffffffc00-0xffffffcff 64bit]
pci 0000:05:00.0: no compatible bridge window for [mem 0xfff000000-0xfff7fffff 64bit pref]
pci 0000:05:00.0: no compatible bridge window for [mem 0xfffcfe000-0xfffcfffff 64bit pref]
pci 0000:05:00.0: no compatible bridge window for [mem 0xfffcfc000-0xfffcfdfff 64bit pref]
pci 0000:0b:04.0: no compatible bridge window for [mem 0xfffef8000-0xfffefffff 64bit pref]
pci 0000:0b:04.0: no compatible bridge window for [mem 0xfffd00000-0xfffdfffff 64bit pref]
pci 0000:0b:04.0: no compatible bridge window for [mem 0xfffef7800-0xfffef7fff 64bit pref]
reserve RAM buffer: 000000000009fc00 - 000000000009ffff
reserve RAM buffer: 00000000dff90000 - 00000000dfffffff
HPET: 4 timers in total, 0 timers will be used for per-cpu timer
hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0
hpet0: 4 comparators, 64-bit 14.318180 MHz counter
Switching to clocksource tsc
pnp: PnP ACPI init
ACPI: bus type pnp registered
pnp 00:00: [bus 00-ff]
pnp 00:00: [io 0x0cf8-0x0cff]
pnp 00:00: [io 0x0000-0x0bff window]
pnp 00:00: [io 0x0d00-0xffff window]
pnp 00:00: [mem 0x000a0000-0x000bffff window]
pnp 00:00: [mem 0x000d0000-0x000dffff window]
pnp 00:00: [mem 0xe0000000-0xdfffffff window disabled]
pnp 00:00: [mem 0xf0000000-0xffffffff window]
pnp 00:00: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
pnp 00:01: [mem 0xfe000000-0xfebfffff]
pnp 00:01: Plug and Play ACPI device, IDs PNP0c01 (active)
pnp 00:02: [dma 4]
pnp 00:02: [io 0x0000-0x000f]
pnp 00:02: [io 0x0081-0x0083]
pnp 00:02: [io 0x0087]
pnp 00:02: [io 0x0089-0x008b]
pnp 00:02: [io 0x008f]
pnp 00:02: [io 0x00c0-0x00df]
pnp 00:02: Plug and Play ACPI device, IDs PNP0200 (active)
pnp 00:03: [io 0x0070-0x0071]
pnp 00:03: [irq 8]
pnp 00:03: Plug and Play ACPI device, IDs PNP0b00 (active)
pnp 00:04: [io 0x0061]
pnp 00:04: Plug and Play ACPI device, IDs PNP0800 (active)
pnp 00:05: [io 0x00f0-0x00ff]
pnp 00:05: [irq 13]
pnp 00:05: Plug and Play ACPI device, IDs PNP0c04 (active)
pnp 00:06: [io 0x03f8-0x03ff]
pnp 00:06: [irq 4]
pnp 00:06: [dma 0 disabled]
pnp 00:06: Plug and Play ACPI device, IDs PNP0501 (active)
pnp 00:07: [io 0x0000-0xffffffffffffffff disabled]
pnp 00:07: [io 0x0a00-0x0a7f]
pnp 00:07: [io 0x0a80-0x0a83]
pnp 00:07: [io 0x0a84-0x0a85]
pnp 00:07: [io 0x0a88-0x0a8f]
pnp 00:07: [io 0x0a90-0x0a9f]
pnp 00:07: [io 0x0b00-0x0bfe]
pnp 00:07: Plug and Play ACPI device, IDs PNP0c02 (active)
pnp 00:08: [io 0x0010-0x001f]
pnp 00:08: [io 0x0022-0x003f]
pnp 00:08: [io 0x0044-0x005f]
pnp 00:08: [io 0x0062-0x0063]
pnp 00:08: [io 0x0065-0x006f]
pnp 00:08: [io 0x0072-0x007f]
pnp 00:08: [io 0x0080]
pnp 00:08: [io 0x0084-0x0086]
pnp 00:08: [io 0x0088]
pnp 00:08: [io 0x008c-0x008e]
pnp 00:08: [io 0x0090-0x009f]
pnp 00:08: [io 0x00a2-0x00bf]
pnp 00:08: [io 0x00e0-0x00ef]
pnp 00:08: [mem 0xffa00000-0xfffffffe]
pnp 00:08: [io 0x0ca4-0x0ca5]
pnp 00:08: [io 0x0ca7-0x0ca8]
pnp 00:08: [io 0x0ca0]
pnp 00:08: [io 0x0ca1]
pnp 00:08: [io 0x0ca2]
pnp 00:08: [io 0x0ca3]
pnp 00:08: [io 0x04d0-0x04d1]
pnp 00:08: [io 0x0800-0x087f]
pnp 00:08: [io 0x0000-0xffffffffffffffff disabled]
pnp 00:08: [io 0x0480-0x04bf]
pnp 00:08: [mem 0xfed1c000-0xfed1ffff]
pnp 00:08: [mem 0xfed20000-0xfed8ffff]
pnp 00:08: Plug and Play ACPI device, IDs PNP0c02 (active)
pnp 00:09: [mem 0xfed00000-0xfed003ff]
pnp 00:09: Plug and Play ACPI device, IDs PNP0103 (active)
pnp 00:0a: [io 0x0060]
pnp 00:0a: [io 0x0064]
pnp 00:0a: [mem 0xfec00000-0xfec00fff]
pnp 00:0a: [mem 0xfee00000-0xfee00fff]
pnp 00:0a: Plug and Play ACPI device, IDs PNP0c02 (active)
pnp 00:0b: [mem 0xe0000000-0xefffffff]
pnp 00:0b: Plug and Play ACPI device, IDs PNP0c02 (active)
pnp 00:0c: [io 0x0ca2]
pnp 00:0c: [io 0x0ca3]
pnp 00:0c: Plug and Play ACPI device, IDs IPI0001 (active)
pnp 00:0d: [io 0x0ca0]
pnp 00:0d: Plug and Play ACPI device, IDs HPI0002 (active)
pnp 00:0e: [mem 0x00000000-0x0009ffff]
pnp 00:0e: [mem 0x000c0000-0x000cffff]
pnp 00:0e: [mem 0x000e0000-0x000fffff]
pnp 00:0e: [mem 0x00100000-0xdfffffff]
pnp 00:0e: [mem 0x00000000-0xffffffffffffffff disabled]
pnp 00:0e: disabling [mem 0x00000000-0x0009ffff] because it overlaps 0000:05:00.0 BAR 0 [mem 0x00000000-0x007fffff 64bit pref]
pnp 00:0e: disabling [mem 0x000c0000-0x000cffff] because it overlaps 0000:05:00.0 BAR 0 [mem 0x00000000-0x007fffff 64bit pref]
pnp 00:0e: disabling [mem 0x000e0000-0x000fffff] because it overlaps 0000:05:00.0 BAR 0 [mem 0x00000000-0x007fffff 64bit pref]
pnp 00:0e: disabling [mem 0x00100000-0xdfffffff] because it overlaps 0000:05:00.0 BAR 0 [mem 0x00000000-0x007fffff 64bit pref]
pnp 00:0e: disabling [mem 0x00000000-0x0009ffff disabled] because it overlaps 0000:0b:04.0 BAR 2 [mem 0x00000000-0x000fffff 64bit pref]
pnp 00:0e: disabling [mem 0x000c0000-0x000cffff disabled] because it overlaps 0000:0b:04.0 BAR 2 [mem 0x00000000-0x000fffff 64bit pref]
pnp 00:0e: disabling [mem 0x000e0000-0x000fffff disabled] because it overlaps 0000:0b:04.0 BAR 2 [mem 0x00000000-0x000fffff 64bit pref]
pnp 00:0e: Plug and Play ACPI device, IDs PNP0c01 (active)
pnp: PnP ACPI: found 15 devices
ACPI: ACPI bus type pnp unregistered
system 00:01: [mem 0xfe000000-0xfebfffff] has been reserved
system 00:07: [io 0x0a00-0x0a7f] has been reserved
system 00:07: [io 0x0a80-0x0a83] has been reserved
system 00:07: [io 0x0a84-0x0a85] has been reserved
system 00:07: [io 0x0a88-0x0a8f] has been reserved
system 00:07: [io 0x0a90-0x0a9f] has been reserved
system 00:07: [io 0x0b00-0x0bfe] has been reserved
system 00:08: [io 0x0ca4-0x0ca5] has been reserved
system 00:08: [io 0x0ca7-0x0ca8] has been reserved
system 00:08: [io 0x0ca0] has been reserved
system 00:08: [io 0x0ca1] has been reserved
system 00:08: [io 0x0ca2] has been reserved
system 00:08: [io 0x0ca3] has been reserved
system 00:08: [io 0x04d0-0x04d1] has been reserved
system 00:08: [io 0x0800-0x087f] has been reserved
system 00:08: [io 0x0480-0x04bf] has been reserved
system 00:08: [mem 0xffa00000-0xfffffffe] could not be reserved
system 00:08: [mem 0xfed1c000-0xfed1ffff] has been reserved
system 00:08: [mem 0xfed20000-0xfed8ffff] has been reserved
system 00:0a: [mem 0xfec00000-0xfec00fff] could not be reserved
system 00:0a: [mem 0xfee00000-0xfee00fff] has been reserved
system 00:0b: [mem 0xe0000000-0xefffffff] has been reserved
pci 0000:00:06.0: BAR 9: assigned [mem 0xff000000-0xffbfffff 64bit pref]
pci 0000:00:04.0: BAR 8: assigned [mem 0xffc00000-0xffdfffff]
pci 0000:00:04.0: BAR 9: assigned [mem 0xfcb00000-0xfccfffff 64bit pref]
pci 0000:00:1c.0: BAR 9: assigned [mem 0xfc900000-0xfcafffff 64bit pref]
pci 0000:00:1c.5: BAR 9: assigned [mem 0xfc700000-0xfc8fffff 64bit pref]
pci 0000:00:04.0: BAR 7: assigned [io 0xc000-0xcfff]
pci 0000:00:06.0: BAR 7: assigned [io 0xb000-0xbfff]
pci 0000:00:1c.0: BAR 7: assigned [io 0xa000-0xafff]
pci 0000:00:1c.4: BAR 7: assigned [io 0x9000-0x9fff]
pci 0000:00:1c.5: BAR 7: assigned [io 0x8000-0x8fff]
pci 0000:00:1f.3: BAR 0: assigned [mem 0xfeffff00-0xfeffffff 64bit]
pci 0000:00:1f.3: BAR 0: set to [mem 0xfeffff00-0xfeffffff 64bit] (PCI address [0xfeffff00-0xfeffffff])
pci 0000:00:02.0: PCI bridge to [bus 01-01]
pci 0000:00:02.0: bridge window [io disabled]
pci 0000:00:02.0: bridge window [mem disabled]
pci 0000:00:02.0: bridge window [mem pref disabled]
pci 0000:00:03.0: PCI bridge to [bus 02-02]
pci 0000:00:03.0: bridge window [io disabled]
pci 0000:00:03.0: bridge window [mem disabled]
pci 0000:00:03.0: bridge window [mem pref disabled]
pci 0000:00:04.0: PCI bridge to [bus 03-03]
pci 0000:00:04.0: bridge window [io 0xc000-0xcfff]
pci 0000:00:04.0: bridge window [mem 0xffc00000-0xffdfffff]
pci 0000:00:04.0: bridge window [mem 0xfcb00000-0xfccfffff 64bit pref]
pci 0000:00:05.0: PCI bridge to [bus 04-04]
pci 0000:00:05.0: bridge window [io disabled]
pci 0000:00:05.0: bridge window [mem disabled]
pci 0000:00:05.0: bridge window [mem pref disabled]
pci 0000:05:00.0: BAR 0: assigned [mem 0xff000000-0xff7fffff 64bit pref]
pci 0000:05:00.0: BAR 0: set to [mem 0xff000000-0xff7fffff 64bit pref] (PCI address [0xff000000-0xff7fffff])
pci 0000:05:00.0: BAR 2: assigned [mem 0xffbfe000-0xffbfffff 64bit pref]
pci 0000:05:00.0: BAR 2: set to [mem 0xffbfe000-0xffbfffff 64bit pref] (PCI address [0xffbfe000-0xffbfffff])
pci 0000:05:00.0: BAR 4: assigned [mem 0xffbfc000-0xffbfdfff 64bit pref]
pci 0000:05:00.0: BAR 4: set to [mem 0xffbfc000-0xffbfdfff 64bit pref] (PCI address [0xffbfc000-0xffbfdfff])
pci 0000:00:06.0: PCI bridge to [bus 05-05]
pci 0000:00:06.0: bridge window [io 0xb000-0xbfff]
pci 0000:00:06.0: bridge window [mem 0xfce00000-0xfcefffff]
pci 0000:00:06.0: bridge window [mem 0xff000000-0xffbfffff 64bit pref]
pci 0000:00:07.0: PCI bridge to [bus 06-06]
pci 0000:00:07.0: bridge window [io disabled]
pci 0000:00:07.0: bridge window [mem disabled]
pci 0000:00:07.0: bridge window [mem pref disabled]
pci 0000:09:00.0: BAR 9: assigned [mem 0xfc900000-0xfcafffff 64bit pref]
pci 0000:0b:04.0: BAR 2: assigned [mem 0xfca00000-0xfcafffff 64bit pref]
pci 0000:0b:04.0: BAR 2: set to [mem 0xfca00000-0xfcafffff 64bit pref] (PCI address [0xfca00000-0xfcafffff])
pci 0000:0b:04.0: BAR 0: assigned [mem 0xfc9f8000-0xfc9fffff 64bit pref]
pci 0000:0b:04.0: BAR 0: set to [mem 0xfc9f8000-0xfc9fffff 64bit pref] (PCI address [0xfc9f8000-0xfc9fffff])
pci 0000:0b:04.0: BAR 4: assigned [mem 0xfc9f7800-0xfc9f7fff 64bit pref]
pci 0000:0b:04.0: BAR 4: set to [mem 0xfc9f7800-0xfc9f7fff 64bit pref] (PCI address [0xfc9f7800-0xfc9f7fff])
pci 0000:09:00.0: PCI bridge to [bus 0b-0b]
pci 0000:09:00.0: bridge window [io disabled]
pci 0000:09:00.0: bridge window [mem 0xfdf00000-0xfdffffff]
pci 0000:09:00.0: bridge window [mem 0xfc900000-0xfcafffff 64bit pref]
pci 0000:09:00.1: PCI bridge to [bus 0a-0a]
pci 0000:09:00.1: bridge window [io disabled]
pci 0000:09:00.1: bridge window [mem disabled]
pci 0000:09:00.1: bridge window [mem pref disabled]
pci 0000:00:1c.0: PCI bridge to [bus 09-0b]
pci 0000:00:1c.0: bridge window [io 0xa000-0xafff]
pci 0000:00:1c.0: bridge window [mem 0xfde00000-0xfdffffff]
pci 0000:00:1c.0: bridge window [mem 0xfc900000-0xfcafffff 64bit pref]
pci 0000:00:1c.4: PCI bridge to [bus 08-08]
pci 0000:00:1c.4: bridge window [io 0x9000-0x9fff]
pci 0000:00:1c.4: bridge window [mem 0xfd000000-0xfddfffff]
pci 0000:00:1c.4: bridge window [mem 0xfb000000-0xfbffffff 64bit pref]
pci 0000:00:1c.5: PCI bridge to [bus 07-07]
pci 0000:00:1c.5: bridge window [io 0x8000-0x8fff]
pci 0000:00:1c.5: bridge window [mem 0xfcf00000-0xfcffffff]
pci 0000:00:1c.5: bridge window [mem 0xfc700000-0xfc8fffff 64bit pref]
pci 0000:00:1e.0: PCI bridge to [bus 0c-0c]
pci 0000:00:1e.0: bridge window [io disabled]
pci 0000:00:1e.0: bridge window [mem disabled]
pci 0000:00:1e.0: bridge window [mem pref disabled]
pci 0000:00:02.0: setting latency timer to 64
pci 0000:00:03.0: setting latency timer to 64
pci 0000:00:04.0: enabling device (0104 -> 0107)
pci 0000:00:04.0: setting latency timer to 64
pci 0000:00:05.0: setting latency timer to 64
pci 0000:00:06.0: enabling device (0106 -> 0107)
pci 0000:00:06.0: setting latency timer to 64
pci 0000:00:07.0: setting latency timer to 64
pci 0000:00:1c.0: enabling device (0106 -> 0107)
pci 0000:00:1c.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
pci 0000:00:1c.0: setting latency timer to 64
pci 0000:09:00.0: setting latency timer to 64
pci 0000:09:00.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16
pci 0000:09:00.1: setting latency timer to 64
pci 0000:00:1c.4: PCI INT A -> GSI 16 (level, low) -> IRQ 16
pci 0000:00:1c.4: setting latency timer to 64
pci 0000:00:1c.5: enabling device (0106 -> 0107)
pci 0000:00:1c.5: PCI INT B -> GSI 17 (level, low) -> IRQ 17
pci 0000:00:1c.5: setting latency timer to 64
pci 0000:00:1e.0: setting latency timer to 64
pci_bus 0000:00: resource 4 [io 0x0000-0x0bff]
pci_bus 0000:00: resource 5 [io 0x0d00-0xffff]
pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff]
pci_bus 0000:00: resource 7 [mem 0x000d0000-0x000dffff]
pci_bus 0000:00: resource 8 [mem 0xf0000000-0xffffffff]
pci_bus 0000:03: resource 0 [io 0xc000-0xcfff]
pci_bus 0000:03: resource 1 [mem 0xffc00000-0xffdfffff]
pci_bus 0000:03: resource 2 [mem 0xfcb00000-0xfccfffff 64bit pref]
pci_bus 0000:05: resource 0 [io 0xb000-0xbfff]
pci_bus 0000:05: resource 1 [mem 0xfce00000-0xfcefffff]
pci_bus 0000:05: resource 2 [mem 0xff000000-0xffbfffff 64bit pref]
pci_bus 0000:09: resource 0 [io 0xa000-0xafff]
pci_bus 0000:09: resource 1 [mem 0xfde00000-0xfdffffff]
pci_bus 0000:09: resource 2 [mem 0xfc900000-0xfcafffff 64bit pref]
pci_bus 0000:0b: resource 1 [mem 0xfdf00000-0xfdffffff]
pci_bus 0000:0b: resource 2 [mem 0xfc900000-0xfcafffff 64bit pref]
pci_bus 0000:08: resource 0 [io 0x9000-0x9fff]
pci_bus 0000:08: resource 1 [mem 0xfd000000-0xfddfffff]
pci_bus 0000:08: resource 2 [mem 0xfb000000-0xfbffffff 64bit pref]
pci_bus 0000:07: resource 0 [io 0x8000-0x8fff]
pci_bus 0000:07: resource 1 [mem 0xfcf00000-0xfcffffff]
pci_bus 0000:07: resource 2 [mem 0xfc700000-0xfc8fffff 64bit pref]
pci_bus 0000:0c: resource 4 [io 0x0000-0x0bff]
pci_bus 0000:0c: resource 5 [io 0x0d00-0xffff]
pci_bus 0000:0c: resource 6 [mem 0x000a0000-0x000bffff]
pci_bus 0000:0c: resource 7 [mem 0x000d0000-0x000dffff]
pci_bus 0000:0c: resource 8 [mem 0xf0000000-0xffffffff]
NET: Registered protocol family 2
IP route cache hash table entries: 262144 (order: 9, 2097152 bytes)
TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
TCP: Hash tables configured (established 524288 bind 65536)
TCP reno registered
UDP hash table entries: 4096 (order: 5, 131072 bytes)
UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
NET: Registered protocol family 1
pci 0000:08:00.0: Boot video device
PCI: CLS 64 bytes, default 64
Unpacking initramfs...
Freeing initrd memory: 12200k freed
PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
Placing 64MB software IO TLB between ffff8800dbc00000 - ffff8800dfc00000
software IO TLB at phys 0xdbc00000 - 0xdfc00000
audit: initializing netlink socket (disabled)
type=2000 audit(1292626705.684:1): initialized
HugeTLB registered 2 MB page size, pre-allocated 0 pages
VFS: Disk quotas dquot_6.5.2
Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
msgmni has been set to 15864
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
pcieport 0000:00:02.0: ACPI _OSC control granted for 0x1d
pcieport 0000:00:02.0: setting latency timer to 64
pcieport 0000:00:02.0: irq 40 for MSI/MSI-X
pcieport 0000:00:03.0: ACPI _OSC control granted for 0x1d
pcieport 0000:00:03.0: setting latency timer to 64
pcieport 0000:00:03.0: irq 41 for MSI/MSI-X
pcieport 0000:00:04.0: ACPI _OSC control granted for 0x1d
pcieport 0000:00:04.0: setting latency timer to 64
pcieport 0000:00:04.0: irq 42 for MSI/MSI-X
pcieport 0000:00:05.0: ACPI _OSC control granted for 0x1d
pcieport 0000:00:05.0: setting latency timer to 64
pcieport 0000:00:05.0: irq 43 for MSI/MSI-X
pcieport 0000:00:06.0: ACPI _OSC control granted for 0x1d
pcieport 0000:00:06.0: setting latency timer to 64
pcieport 0000:00:06.0: irq 44 for MSI/MSI-X
pcieport 0000:00:07.0: ACPI _OSC control granted for 0x1d
pcieport 0000:00:07.0: setting latency timer to 64
pcieport 0000:00:07.0: irq 45 for MSI/MSI-X
pcieport 0000:00:1c.0: ACPI _OSC control granted for 0x1d
pcieport 0000:00:1c.0: setting latency timer to 64
pcieport 0000:00:1c.0: irq 46 for MSI/MSI-X
pcieport 0000:00:1c.4: ACPI _OSC control granted for 0x1d
pcieport 0000:00:1c.4: setting latency timer to 64
pcieport 0000:00:1c.4: irq 47 for MSI/MSI-X
pcieport 0000:00:1c.5: ACPI _OSC control granted for 0x1d
pcieport 0000:00:1c.5: setting latency timer to 64
pcieport 0000:00:1c.5: irq 48 for MSI/MSI-X
aer 0000:00:02.0:pcie02: service driver aer loaded
aer 0000:00:03.0:pcie02: service driver aer loaded
aer 0000:00:04.0:pcie02: service driver aer loaded
aer 0000:00:05.0:pcie02: service driver aer loaded
aer 0000:00:06.0:pcie02: service driver aer loaded
aer 0000:00:07.0:pcie02: service driver aer loaded
vesafb: framebuffer at 0xfb000000, mapped to 0xffffc90011800000, using 3072k, total 8128k
vesafb: mode is 1024x768x16, linelength=2048, pages=4
vesafb: scrolling: redraw
vesafb: Truecolor: size=0:5:6:5, shift=0:11:5:0
Console: switching to colour frame buffer device 128x48
fb0: VESA VGA frame buffer device
Non-volatile memory driver v1.3
Linux agpgart interface v0.103
Serial: 8250/16550 driver, 8 ports, IRQ sharing disabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
00:06: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
PNP: No PS/2 controller found. Probing ports directly.
Clocksource tsc unstable (delta = -8588848793 ns)
Switching to clocksource hpet
serio: i8042 KBD port at 0x60,0x64 irq 1
mice: PS/2 mouse device common for all mice
cpuidle: using governor ladder
cpuidle: using governor menu
TCP cubic registered
Registering the dns_resolver key type
registered taskstats version 1
Freeing unused kernel memory: 1260k freed
Write protecting the kernel read-only data: 6144k
Freeing unused kernel memory: 1136k freed
Freeing unused kernel memory: 460k freed
ACPI: acpi_idle registered with cpuidle
SCSI subsystem initialized
libata version 3.00 loaded.
ata_piix 0000:00:1f.2: version 2.13
ata_piix 0000:00:1f.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19
ata_piix 0000:00:1f.2: MAP [ P0 P2 P1 P3 ]
ata_piix 0000:00:1f.2: setting latency timer to 64
scsi0 : ata_piix
scsi1 : ata_piix
ata1: SATA max UDMA/133 cmd 0x1f0 ctl 0x3f6 bmdma 0xff90 irq 14
ata2: SATA max UDMA/133 cmd 0x170 ctl 0x376 bmdma 0xff98 irq 15
ata_piix 0000:00:1f.5: PCI INT B -> GSI 19 (level, low) -> IRQ 19
ata_piix 0000:00:1f.5: MAP [ P0 -- P1 -- ]
ata_piix 0000:00:1f.5: setting latency timer to 64
scsi2 : ata_piix
scsi3 : ata_piix
ata3: SATA max UDMA/133 cmd 0xe000 ctl 0xdc00 bmdma 0xd480 irq 19
ata4: SATA max UDMA/133 cmd 0xd880 ctl 0xd800 bmdma 0xd488 irq 19
ata4: SATA link down (SStatus 0 SControl 300)
ata3: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
ata3.00: ATAPI: TSSTcorpDVD-ROM TS-H353B, IG01, max UDMA/100
ata3.00: configured for UDMA/100
ata1.00: SATA link down (SStatus 0 SControl 300)
ata1.01: SATA link down (SStatus 0 SControl 300)
ata2.00: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
ata2.01: SATA link down (SStatus 0 SControl 300)
ata2.00: ATA-7: GB0160CAABV, HPG1, max UDMA/100
ata2.00: 312581808 sectors, multi 16: LBA48 NCQ (depth 0/32)
ata2.00: configured for UDMA/100
scsi 1:0:0:0: Direct-Access ATA GB0160CAABV n/a PQ: 0 ANSI: 5
scsi 2:0:0:0: CD-ROM TSSTcorp DVD-ROM TS-H353B IG01 PQ: 0 ANSI: 5
Uniform Multi-Platform E-IDE driver
BIOS EDD facility v0.16 2004-Jun-25, 1 devices found
udevd (89): /proc/89/oom_adj is deprecated, please use /proc/89/oom_score_adj instead.
udevd version 128 started
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
sd 1:0:0:0: [sda] 312581808 512-byte logical blocks: (160 GB/149 GiB)
sd 1:0:0:0: [sda] Write Protect is off
sd 1:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 1:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
sda: sda1 sda2
usbcore: registered new device driver usb
sd 1:0:0:0: [sda] Attached SCSI disk
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci_hcd 0000:00:1a.7: PCI INT C -> GSI 18 (level, low) -> IRQ 18
ehci_hcd 0000:00:1a.7: setting latency timer to 64
ehci_hcd 0000:00:1a.7: EHCI Host Controller
ehci_hcd 0000:00:1a.7: new USB bus registered, assigned bus number 1
ehci_hcd 0000:00:1a.7: debug port 1
ehci_hcd 0000:00:1a.7: cache line size of 64 is not supported
ehci_hcd 0000:00:1a.7: irq 18, io mem 0xfcdffc00
ehci_hcd 0000:00:1a.7: USB 2.0 started, EHCI 1.00
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: EHCI Host Controller
usb usb1: Manufacturer: Linux 2.6.37-rc1-5-default ehci_hcd
usb usb1: SerialNumber: 0000:00:1a.7
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 6 ports detected
ehci_hcd 0000:00:1d.7: PCI INT A -> GSI 23 (level, low) -> IRQ 23
ehci_hcd 0000:00:1d.7: setting latency timer to 64
ehci_hcd 0000:00:1d.7: EHCI Host Controller
ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 2
ehci_hcd 0000:00:1d.7: debug port 1
ehci_hcd 0000:00:1d.7: cache line size of 64 is not supported
ehci_hcd 0000:00:1d.7: irq 23, io mem 0xfcdff800
ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00
usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb2: Product: EHCI Host Controller
usb usb2: Manufacturer: Linux 2.6.37-rc1-5-default ehci_hcd
usb usb2: SerialNumber: 0000:00:1d.7
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 6 ports detected
uhci_hcd: USB Universal Host Controller Interface driver
uhci_hcd 0000:00:1a.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
uhci_hcd 0000:00:1a.0: setting latency timer to 64
uhci_hcd 0000:00:1a.0: UHCI Host Controller
uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 3
uhci_hcd 0000:00:1a.0: irq 16, io base 0x0000e800
usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb3: Product: UHCI Host Controller
usb usb3: Manufacturer: Linux 2.6.37-rc1-5-default uhci_hcd
usb usb3: SerialNumber: 0000:00:1a.0
hub 3-0:1.0: USB hub found
hub 3-0:1.0: 2 ports detected
uhci_hcd 0000:00:1a.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
uhci_hcd 0000:00:1a.1: setting latency timer to 64
uhci_hcd 0000:00:1a.1: UHCI Host Controller
uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4
uhci_hcd 0000:00:1a.1: irq 21, io base 0x0000e880
usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb4: Product: UHCI Host Controller
usb usb4: Manufacturer: Linux 2.6.37-rc1-5-default uhci_hcd
usb usb4: SerialNumber: 0000:00:1a.1
hub 4-0:1.0: USB hub found
hub 4-0:1.0: 2 ports detected
uhci_hcd 0000:00:1a.2: PCI INT D -> GSI 19 (level, low) -> IRQ 19
uhci_hcd 0000:00:1a.2: setting latency timer to 64
uhci_hcd 0000:00:1a.2: UHCI Host Controller
uhci_hcd 0000:00:1a.2: new USB bus registered, assigned bus number 5
uhci_hcd 0000:00:1a.2: irq 19, io base 0x0000ec00
usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb5: Product: UHCI Host Controller
usb usb5: Manufacturer: Linux 2.6.37-rc1-5-default uhci_hcd
usb usb5: SerialNumber: 0000:00:1a.2
hub 5-0:1.0: USB hub found
hub 5-0:1.0: 2 ports detected
uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 23 (level, low) -> IRQ 23
uhci_hcd 0000:00:1d.0: setting latency timer to 64
uhci_hcd 0000:00:1d.0: UHCI Host Controller
uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 6
uhci_hcd 0000:00:1d.0: irq 23, io base 0x0000e080
usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb6: Product: UHCI Host Controller
usb usb6: Manufacturer: Linux 2.6.37-rc1-5-default uhci_hcd
usb usb6: SerialNumber: 0000:00:1d.0
hub 6-0:1.0: USB hub found
hub 6-0:1.0: 2 ports detected
uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 19 (level, low) -> IRQ 19
uhci_hcd 0000:00:1d.1: setting latency timer to 64
uhci_hcd 0000:00:1d.1: UHCI Host Controller
uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 7
uhci_hcd 0000:00:1d.1: irq 19, io base 0x0000e400
usb 6-1: new full speed USB device using uhci_hcd and address 2
usb usb7: New USB device found, idVendor=1d6b, idProduct=0001
usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb7: Product: UHCI Host Controller
usb usb7: Manufacturer: Linux 2.6.37-rc1-5-default uhci_hcd
usb usb7: SerialNumber: 0000:00:1d.1
hub 7-0:1.0: USB hub found
hub 7-0:1.0: 2 ports detected
uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
usb 6-1: New USB device found, idVendor=0000, idProduct=0000
usb 6-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 6-1: Product: SE USB Device
usb 6-1: Manufacturer: ServerEngines
usb 6-1: SerialNumber: 601615E48484F2
uhci_hcd 0000:00:1d.2: setting latency timer to 64
uhci_hcd 0000:00:1d.2: UHCI Host Controller
uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 8
uhci_hcd 0000:00:1d.2: irq 18, io base 0x0000e480
usb usb8: New USB device found, idVendor=1d6b, idProduct=0001
usb usb8: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb8: Product: UHCI Host Controller
usb usb8: Manufacturer: Linux 2.6.37-rc1-5-default uhci_hcd
usb usb8: SerialNumber: 0000:00:1d.2
hub 8-0:1.0: USB hub found
hub 8-0:1.0: 2 ports detected
input: ServerEngines SE USB Device as /devices/pci0000:00/0000:00:1d.0/usb6/6-1/6-1:1.0/input/input0
generic-usb 0003:0000:0000.0001: input,hidraw0: USB HID v1.11 Keyboard [ServerEngines SE USB Device] on usb-0000:00:1d.0-1/input0
input: ServerEngines SE USB Device as /devices/pci0000:00/0000:00:1d.0/usb6/6-1/6-1:1.1/input/input1
generic-usb 0003:0000:0000.0002: input,hidraw1: USB HID v1.11 Mouse [ServerEngines SE USB Device] on usb-0000:00:1d.0-1/input1
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
PM: Starting manual resume from disk
EXT3-fs: barriers not enabled
kjournald starting. Commit interval 5 seconds
EXT3-fs (sda2): using internal journal
EXT3-fs (sda2): mounted filesystem with ordered data mode
udevd version 128 started
sd 1:0:0:0: Attached scsi generic sg0 type 0
scsi 2:0:0:0: Attached scsi generic sg1 type 5
input: PC Speaker as /devices/platform/pcspkr/input/input2
vxge: Copyright(c) 2002-2010 Exar Corp.
vxge: Driver version: 2.0.9.20840-k
vxge 0000:05:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
vxge 0000:05:00.0: setting latency timer to 64
vxge: Reading of hardware info failed.Please try upgrading the firmware.
vxge 0000:05:00.0: PCI INT A disabled
vxge: probe of 0000:05:00.0 failed with error -22
pci_hotplug: PCI Hot Plug PCI Core version: 0.5
iTCO_vendor_support: vendor-support=0
sr0: scsi3-mmc drive: 62x/62x cd/rw xa/form2 cdda tray
cdrom: Uniform CD-ROM driver Revision: 3.20
sr 2:0:0:0: Attached scsi CD-ROM sr0
input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input3
ACPI: Power Button [PWRB]
input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input4
ACPI: Power Button [PWRF]
i801_smbus 0000:00:1f.3: PCI INT C -> GSI 18 (level, low) -> IRQ 18
iTCO_wdt: Intel TCO WatchDog Timer Driver v1.06
iTCO_wdt: Found a ICH9R TCO device (Version=2, TCOBASE=0x0860)
iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
S2IO 0000:0b:04.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
S2IO 0000:0b:04.0: irq 49 for MSI/MSI-X
S2IO 0000:0b:04.0: irq 50 for MSI/MSI-X
tg3.c:v3.115 (October 14, 2010)
tg3 0000:07:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17
tg3 0000:07:00.0: setting latency timer to 64
EDAC MC: Ver: 2.1.0 Dec 15 2010
rtc_cmos 00:03: RTC can wake from S4
S2IO 0000:0b:04.0: restoring config space at offset 0x1 (was 0x2300042, writing 0x2300046)
rtc_cmos 00:03: rtc core: registered rtc_cmos as rtc0
rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet irqs
tg3 0000:07:00.0: eth1: Tigon3 [partno(N/A) rev a200] (PCI Express) MAC address 00:1e:0b:fc:9c:2b
tg3 0000:07:00.0: eth1: attached PHY is 5722/5756 (10/100/1000Base-T Ethernet) (WireSpeed[1])
tg3 0000:07:00.0: eth1: RXcsums[1] LinkChgREG[0] MIirq[0] ASF[0] TSOcap[1]
tg3 0000:07:00.0: eth1: dma_rwctrl[76180000] dma_mask[64-bit]
EDAC MC0: Giving out device to 'i5100_edac.c' 'i5100': DEV 0000:00:10.1
s2io: Copyright(c) 2002-2010 Exar Corp.
s2io: eth0: Neterion 10 Gigabit Ethernet-SR PCIe 1.0a Adapter (rev 2)
s2io: eth0: Driver version 2.0.26.27
s2io: eth0: MAC Address: 00:0c:fc:00:39:f3
s2io: Serial number: SXT0721133
s2io: eth0: Device is on PCI-E bus
s2io: eth0: 1-Buffer receive mode enabled
s2io: eth0: NAPI enabled
s2io: eth0: Using 5 Tx fifo(s)
s2io: eth0: Using 1 Rx ring(s)
s2io: eth0: Interrupt type MSI-X
s2io: eth0: Multiqueue support disabled
s2io: eth0: Default steering enabled for transmit
s2io: eth0: Large receive offload enabled
Adding 2104476k swap on /dev/sda1. Priority:-1 extents:1 across:2104476k
device-mapper: uevent: version 1.0.3
device-mapper: ioctl: 4.18.0-ioctl (2010-06-29) initialised: dm-devel@redhat.com
loop: module loaded
fuse init (API version 7.15)
microcode: CPU0 sig=0x10676, pf=0x40, revision=0x60c
microcode: CPU1 sig=0x10676, pf=0x40, revision=0x60c
microcode: CPU2 sig=0x10676, pf=0x40, revision=0x60c
microcode: CPU3 sig=0x10676, pf=0x40, revision=0x60c
microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
tg3 0000:07:00.0: irq 49 for MSI/MSI-X
tg3 0000:07:00.0: eth1: Link is up at 100 Mbps, full duplex
tg3 0000:07:00.0: eth1: Flow control is off for TX and off for RX
NET: Registered protocol family 10
lo: Disabled Privacy Extensions
eth1: no IPv6 routers present
The information and any attached documents contained in this message
may be confidential and/or legally privileged. The message is
intended solely for the addressee(s). If you are not the intended
recipient, you are hereby notified that any use, dissemination, or
reproduction is strictly prohibited and may be unlawful. If you are
not the intended recipient, please contact the sender immediately by
return e-mail and destroy all copies of the original message.
^ permalink raw reply
* Re: [PATCH net-next] bnx2x: Add Nic partitioning mode (57712 devices)
From: Dimitris Michailidis @ 2010-12-17 23:13 UTC (permalink / raw)
To: Matt Domsch
Cc: Eilon Greenstein, Dmitry Kravkov, davem@davemloft.net,
netdev@vger.kernel.org, narendra_k@dell.com,
jordan_hargrave@dell.com
In-Reply-To: <20101217024509.GA5854@auslistsprd01.us.dell.com>
Matt Domsch wrote:
> On Thu, Dec 09, 2010 at 04:49:25PM +0200, Eilon Greenstein wrote:
>> On Mon, 2010-12-06 at 10:21 -0800, Dimitris Michailidis wrote:
>>> Matt Domsch wrote:
>> ...
>>> /sys/class/net/<ifname>/dev_id indicates the physical port <ifname> is
>>> associated with. At least a few drivers set up dev_id this way.
>>>
>>>
>> So we are on agreement? This can satisf all needs? If so, we will add
>> this scheme to the bnx2x as well.
>
> I don't think that's enough. Necessary, but not sufficient.
>
> If dev_id is a field that starts over with each PCI device (e.g. is
> used to distinguish multiple ports that share the same PCI
> device), that's enough to handle the Chelsio case, but not the NPAR &
> SR-IOV case.
My understanding is that dev_id indicates the physical port of the card
associated with an interface. It does not reset when you move to a new
function of the device.
>
> If the above is true, then a value of dev_id=0 for all 1:1 PCI Device
> : Port relations is fine, leaving the three drivers that set dev_id
> non-zero are all multi-port, single PCI device controllers.
>
> cxgb4/t4_hw.c: adap->port[i]->dev_id = j;
The HW cxgb4 deals with is multi-function (actually the driver uses
primarily function 4 nowadays) but it's virtualizable and the association
between functions and ports very flexible. For example, you may have a
2-port card but maybe the driver will be given just (a slice of) port 1. So
the driver will create one netdev with dev_id==1 and there won't be anything
with dev_id 0. You cannot determine this by looking at anything PCI-related
or any static table.
For this driver you can get two pieces of information for an interface:
- /sys/class/net/<interface>/device points to the PCI function handling the
interface
- /sys/class/net/<interface>/dev_id indicates the physical port of the interface
You can have several interfaces with same device link and different dev_id.
While the current driver doesn't do it you could also have several
interfaces with different device links but same dev_id (NPAR situation,
notice again that dev_ids are not per PCI function), or interfaces with
different device and dev_id, or even interfaces with same device and dev_id.
> mlx4/en_netdev.c: dev->dev_id = port - 1;
> sfc/siena.c: efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
>
> Is that truly how these three controllers work: they set dev_id when
> there are multiple physical ports that a single PCI d/b/d/f drives?
>
> My naming convention of:
> pci<slot>#<port>
> wants to express this relationship. If I have a card with 2 PCI
> devices, and 2 physical ports on each device, I have 4 ports to
> describe. The dev_ids would look like: 0,1 0,1 , so I can't use that
> value directly.
I think they'd be 0,1,2,3 for drivers that set dev_id and 0,0,0,0 otherwise.
I can make a list of PCI devices on the same card,
> look at the dev_id field of each, and run a counter:
>
> for each slot:
> int port=1;
> for each pci device:
> for each in net/<interface>/dev_id:
> use name pci<slot>#<port>
> port++
>
> OK? Can someone with such a card send me tree /sys, so I can see the
> tree does really look like I expect:
>
> /sys/devices/pci0000:00/0000:00:1c.0/0000:0b:00.0/net/eth0/dev_id = 0
> /sys/devices/pci0000:00/0000:00:1c.0/0000:0b:00.0/net/eth1/dev_id = 1
>
> simply finding a net/ subdir under a PCI device, each of the
> directories in net/ are interface names, with different dev_id values.
This would be the common case but in general the dev_ids don't need to be
consecutive or start at 0, nor does a particular dev_id need to appear just
once.
> Now for the partitioned devices (NPAR or SR-IOV). Here, we have
> multiple PCI devices mapped to the same port.
>
> My naming convention of:
> pci<slot>#<port>_<partition>
> wants to express this relationship.
>
> I need a way to express which port a given partition maps to. I'm
> also presuming this is a static mapping right now, that it won't
> change around during runtime (ala Xsigo, which I have no solution here
> for; if the mapping isn't static, this is going to get trickier).
>
> As dev_ids are only unique per PCI device, we would need a pointer to
> the "base" device. However, in the Broadcom 57712 case, there is no
> such "base" device. :-( So, using dev_id here doesn't seem like the
> right approach for these devices.
dev_ids can handle NPAR but I do understand that dev_id 0 is ambiguous. Two
functions with dev_id 0 mean one thing for a driver that sets dev_id and a
very different thing for one that doesn't.
> What if we did something like this?
>
> /sys/devices/net_ports/port0/
> /sys/devices/pci0000:00/0000:00:1c.0/0000:0b:00.0/net/eth0/port ->
> /../../../../../net_ports/port0
> /sys/devices/pci0000:00/0000:00:1c.0/0000:0b:00.1/net/eth1/port ->
> /../../../../../net_ports/port0
>
>
> In this case, the port0 "name" is simply a way to group interfaces
> into ports, it's not how ports are labeled on the chassis.
If I understand you right a "port" is a group of interfaces sharing one
physical port without saying which one. I think dev_id does the same and
specifies which physical port.
>
> Do network drivers know how many ports they have?
> What are the characteristics of network ports? Ideally, physical
> location (PCI slot), and index within that physical location.
This index is the dev_id for drivers that set it.
> These
> right now I'm deriving from SMBIOS and PCI, and if not explicitly
> exposed, counting devices on the same slot and assigning port numbers
> that way, but I would love to have explicit information from the
> drivers.
>
> Thoughts?
>
> Thanks,
> Matt
>
^ permalink raw reply
* Re: [NETWORK] Firmware file for tehuti
From: Joe Jin @ 2010-12-18 0:09 UTC (permalink / raw)
To: Ben Hutchings
Cc: Alexander Indenbaum, Andy Gospodarek, netdev, linux-kernel,
Guru Anbalagane, greg.marsden@oracle.com, DuanZhenzhong,
Jaswinder Singh Rajput
In-Reply-To: <1292594691.3136.840.camel@localhost>
> My first version of the patch to use request_firmware() used
> "tehuti/firmware.bin". I then found Jaswinder's patch at
> <http://git.infradead.org/users/jaswinder/firm-jsr-2.6.git?a=commitdiff;h=e41f3e5f8c5110871e376a2566b8eea2932b813b>,
> which used the name "tehuti/bdx.bin". For some reason I changed the
> name of the firmware file in my patch to match that, but not the code.
>
Thanks for the confirmation.
> Ben.
>
--
Oracle<http://www.oracle.com>
Joe Jin | Team Leader, Software Development | +8610.8278.6295
ORACLE | Linux and Virtualization
Incubator Building 2-A ZPark | Beijing China, 100094
^ permalink raw reply
* Re: "x86: allocate space within a region top-down" causes bar0 access issue
From: Bjorn Helgaas @ 2010-12-18 0:17 UTC (permalink / raw)
To: Jon Mason
Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
Ramkrishna Vepa
In-Reply-To: <20101217231210.GH4622@exar.com>
On Friday, December 17, 2010 04:12:11 pm Jon Mason wrote:
> On Fri, Dec 17, 2010 at 12:16:12PM -0800, Bjorn Helgaas wrote:
> > On Friday, December 17, 2010 12:44:58 pm Jon Mason wrote:
> > > The following patch is causing problem with the vxge driver/adapter on
> > > HP x86-64 systems. Reads to bar0 to return 0xffffffffffffffff instead
> > > of their intended value. This prevents the vxge module from loading
> > > by failing sanity checks in the driver for certain values in bar0. We
> > > are not seeing any issues with this patch on non-HP systems in our
> > > lab.
> > >
> > > Can this patch be removed from 2.6.37 until a better solution can be
> > > found?
> >
> > There were several issues related to that patch, and it's about to
> > be reverted. I am curious about the failure you're seeing, though,
> > and I'd like to understand the cause and make sure it's one of the
> > issues I've already investigated.
> >
> > Can you send me the complete dmesg log of a failing boot?
>
> Below is the dmesg of a failing system.
Thanks. This is interesting. All the reported PCI windows are below 4GB:
> ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
> pci_root PNP0A08:00: host bridge window [io 0x0000-0x0bff]
> pci_root PNP0A08:00: host bridge window [io 0x0d00-0xffff]
> pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff]
> pci_root PNP0A08:00: host bridge window [mem 0x000d0000-0x000dffff]
> pci_root PNP0A08:00: host bridge window [mem 0xf0000000-0xffffffff]
But the BIOS configured many devices *above* 4GB (and they probably
work fine there), so we complain about them, zero out their resources,
then think they conflict with some PNP devices (which they really
don't):
> pci 0000:00:1f.3: reg 10: [mem 0xffffffc00-0xffffffcff 64bit]
> pci 0000:05:00.0: reg 10: [mem 0xfff000000-0xfff7fffff 64bit pref]
> pci 0000:05:00.0: reg 18: [mem 0xfffcfe000-0xfffcfffff 64bit pref]
> pci 0000:05:00.0: reg 20: [mem 0xfffcfc000-0xfffcfdfff 64bit pref]
> pci 0000:00:06.0: PCI bridge to [bus 05-05]
> pci 0000:00:06.0: bridge window [mem 0xfff000000-0xfffcfffff 64bit pref]
> pci 0000:00:1c.0: PCI bridge to [bus 09-0b]
> pci 0000:00:1c.0: bridge window [mem 0xfffd00000-0xfffefffff 64bit pref]
> pci 0000:0b:04.0: reg 10: [mem 0xfffef8000-0xfffefffff 64bit pref]
> pci 0000:0b:04.0: reg 18: [mem 0xfffd00000-0xfffdfffff 64bit pref]
> pci 0000:0b:04.0: reg 20: [mem 0xfffef7800-0xfffef7fff 64bit pref]
> pci 0000:09:00.0: PCI bridge to [bus 0b-0b]
> pci 0000:09:00.0: bridge window [mem 0xfffd00000-0xfffefffff 64bit pref]
...
> pci 0000:00:06.0: no compatible bridge window for [mem 0xfff000000-0xfffcfffff 64bit pref]
> pci 0000:00:1c.0: no compatible bridge window for [mem 0xfffd00000-0xfffefffff 64bit pref]
> pci 0000:09:00.0: no compatible bridge window for [mem 0xfffd00000-0xfffefffff 64bit pref]
> pci 0000:00:1f.3: no compatible bridge window for [mem 0xffffffc00-0xffffffcff 64bit]
> pci 0000:05:00.0: no compatible bridge window for [mem 0xfff000000-0xfff7fffff 64bit pref]
> pci 0000:05:00.0: no compatible bridge window for [mem 0xfffcfe000-0xfffcfffff 64bit pref]
> pci 0000:05:00.0: no compatible bridge window for [mem 0xfffcfc000-0xfffcfdfff 64bit pref]
> pci 0000:0b:04.0: no compatible bridge window for [mem 0xfffef8000-0xfffefffff 64bit pref]
> pci 0000:0b:04.0: no compatible bridge window for [mem 0xfffd00000-0xfffdfffff 64bit pref]
> pci 0000:0b:04.0: no compatible bridge window for [mem 0xfffef7800-0xfffef7fff 64bit pref]
...
> pnp 00:0e: disabling [mem 0x00000000-0x0009ffff] because it overlaps 0000:05:00.0 BAR 0 [mem 0x00000000-0x007fffff 64bit pref]
> pnp 00:0e: disabling [mem 0x000c0000-0x000cffff] because it overlaps 0000:05:00.0 BAR 0 [mem 0x00000000-0x007fffff 64bit pref]
ACPI helpfully tells us that the high 6MB below 4GB is reserved, but
we don't handle that correctly:
> pnp 00:08: [mem 0xffa00000-0xfffffffe]
> system 00:08: [mem 0xffa00000-0xfffffffe] could not be reserved
And finally, we drop some of those PCI devices, including the vxge
device on top of that ACPI PNP0C02 device, which of course doesn't
work:
> pci 0000:00:06.0: BAR 9: assigned [mem 0xff000000-0xffbfffff 64bit pref]
> pci 0000:05:00.0: BAR 0: assigned [mem 0xff000000-0xff7fffff 64bit pref]
> vxge: Reading of hardware info failed.Please try upgrading the firmware.
> vxge: probe of 0000:05:00.0 failed with error -22
So there's probably a BIOS bug (not reporting the windows above 4GB),
and definitely a Linux bus (allowing PCI to allocate things on top
of ACPI devices).
This is a known Linux issue, and the top-down allocation scheme made
it much more likely that we'd run into problems like this. Reverting
to bottom-up allocation doesn't fix the problem, but makes it much less
likely that we'll trip over it.
Thanks a lot for reporting this and collecting the dmesg!
Bjorn
^ permalink raw reply
* Re: [PATCH v2] kptr_restrict for hiding kernel pointers from unprivileged users
From: Andrew Morton @ 2010-12-18 0:44 UTC (permalink / raw)
To: Dan Rosenberg
Cc: linux-kernel, linux-security-module, netdev, jmorris, eugeneteo,
kees.cook, mingo, davem
In-Reply-To: <1292025924.2965.20.camel@Dan>
On Fri, 10 Dec 2010 19:05:24 -0500
Dan Rosenberg <drosenberg@vsecurity.com> wrote:
> The below patch adds the %pK format specifier, the
> CONFIG_SECURITY_KPTR_RESTRICT configuration option, and the
> kptr_restrict sysctl.
>
> The %pK format specifier is designed to hide exposed kernel pointers
> from unprivileged users, specifically via /proc interfaces. Its
> behavior depends on the kptr_restrict sysctl, whose default value
> depends on CONFIG_SECURITY_KPTR_RESTRICT. If kptr_restrict is set to 0,
> no deviation from the standard %p behavior occurs. If kptr_restrict is
> set to 1, if the current user (intended to be a reader via seq_printf(),
> etc.) does not have CAP_SYSLOG (which is currently in the LSM tree),
> kernel pointers using %pK are printed as 0's. This was chosen over the
> default "(null)", which cannot be parsed by userland %p, which expects
> "(nil)".
>
> v2 improves checking for inappropriate context, on suggestion by Peter
> Zijlstra. Thanks to Thomas Graf for suggesting use of a centralized
> format specifier.
The changelog doesn't describe why CONFIG_SECURITY_KPTR_RESTRICT
exists, nor why the kptr_restrict sysctl exists. I can kinda guess why
this was done, but it would be much better if your reasoning was
present here.
And I'd question whether we need CONFIG_SECURITY_KPTR_RESTRICT at all.
Disabling it saves no memory. Its presence just increases the level of
incompatibility between different vendor's kernels and potentially
doubles the number of kernels which distros must ship (which they of
course won't do). It might be better to add a kptr_restrict=1 kernel boot
option (although people sometimes have problems with boot options in
embedded environments).
All that being said, distro initscripts can just set the sysctl to the
desired value before any non-root process has even started, but this
apparently is far too hard for them :(
Finally, the changelog and the documentation changes don't tell us the
full /proc path to the kptr_restrict pseudo-file. That would be useful
info. Seems that it's /proc/sys/kernel/kptr_restrict?
>
> ...
>
> --- a/lib/vsprintf.c
> +++ b/lib/vsprintf.c
> @@ -936,6 +936,8 @@ char *uuid_string(char *buf, char *end, const u8 *addr,
> return string(buf, end, uuid, spec);
> }
>
> +int kptr_restrict = CONFIG_SECURITY_KPTR_RESTRICT;
> +
> /*
> * Show a '%p' thing. A kernel extension is that the '%p' is followed
> * by an extra set of alphanumeric characters that are extended format
> @@ -979,6 +981,7 @@ char *uuid_string(char *buf, char *end, const u8 *addr,
> * Implements a "recursive vsnprintf".
> * Do not use this feature without some mechanism to verify the
> * correctness of the format string and va_list arguments.
> + * - 'K' For a kernel pointer that should be hidden from unprivileged users
> *
> * Note: The difference between 'S' and 'F' is that on ia64 and ppc64
> * function pointers are really function descriptors, which contain a
> @@ -1035,6 +1038,21 @@ char *pointer(const char *fmt, char *buf, char *end, void *ptr,
> return buf + vsnprintf(buf, end - buf,
> ((struct va_format *)ptr)->fmt,
> *(((struct va_format *)ptr)->va));
> + case 'K':
> + if (kptr_restrict) {
> + if (in_irq() || in_serving_softirq() || in_nmi())
> + WARN(1, "%%pK used in interrupt context.\n");
> +
> + else if (capable(CAP_SYSLOG))
> + break;
And the reason why it's unusable in interrupt context is that we can't
meaningfully check CAP_SYSLOG from interrupt.
Fair enough, but this does restrict %pK's usefulness.
I think I'd be more comfortable with a WARN_ONCE here. If someone
screws up then we don't want to spew thousands of repeated warnings at
our poor users - one will do.
So what's next? We need to convert 1,000,000 %p callsites to use %pK?
That'll be fun. Please consider adding a new checkpatch rule which
detects %p and asks people whether they should have used %pK.
^ permalink raw reply
* Re: [PATCH v2] kptr_restrict for hiding kernel pointers from unprivileged users
From: Andrew Morton @ 2010-12-18 0:53 UTC (permalink / raw)
To: Dan Rosenberg
Cc: linux-kernel, linux-security-module, netdev, jmorris, eugeneteo,
kees.cook, mingo, davem
In-Reply-To: <1292025924.2965.20.camel@Dan>
On Fri, 10 Dec 2010 19:05:24 -0500
Dan Rosenberg <drosenberg@vsecurity.com> wrote:
> + case 'K':
> + if (kptr_restrict) {
> + if (in_irq() || in_serving_softirq() || in_nmi())
> + WARN(1, "%%pK used in interrupt context.\n");
> +
> + else if (capable(CAP_SYSLOG))
> + break;
> +
> + if (spec.field_width == -1) {
> + spec.field_width = 2 * sizeof(void *);
> + spec.flags |= ZEROPAD;
> + }
> + return number(buf, end, 0, spec);
> + }
> + break;
Also, we should emit the runtime warning even if kptr_restrict is
false. Otherwise programmers might ship buggy code because they didn't
enable kptr_restrict during testing.
So what I ended up with was
case 'K':
/*
* %pK cannot be used in IRQ context because it tests
* CAP_SYSLOG.
*/
if (in_irq() || in_serving_softirq() || in_nmi())
WARN_ONCE(1, "%%pK used in interrupt context.\n");
if (!kptr_restrict)
break; /* %pK does not obscure pointers */
if (capable(CAP_SYSLOG))
break; /* privileged apps expose pointers */
if (spec.field_width == -1) {
spec.field_width = 2 * sizeof(void *);
spec.flags |= ZEROPAD;
}
return number(buf, end, 0, spec);
How does that look?
Also... permitting root to bypass the %pK obscuring seems pretty lame,
really. I bet a *lot* of the existing %p sites are already root-only
(eg, driver initialisation). So much of the value is lost.
^ permalink raw reply
* [RFC PATCH 3/3] igb: example of how to update igb to make use of in-kernel Toeplitz hashing
From: Alexander Duyck @ 2010-12-18 1:00 UTC (permalink / raw)
To: netdev
In-Reply-To: <20101218004210.28602.18499.stgit@gitlad.jf.intel.com>
This change allows igb to make use of the in-kernel Toeplitz hashing so
that RX and TX hash queues can be matched up.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
---
drivers/net/igb/igb_main.c | 22 ++++++++++------------
1 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index 72a2fad..9e6a437 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -45,6 +45,7 @@
#include <linux/interrupt.h>
#include <linux/if_ether.h>
#include <linux/aer.h>
+#include <linux/toeplitz.h>
#ifdef CONFIG_IGB_DCA
#include <linux/dca.h>
#endif
@@ -1691,6 +1692,7 @@ static const struct net_device_ops igb_netdev_ops = {
.ndo_open = igb_open,
.ndo_stop = igb_close,
.ndo_start_xmit = igb_xmit_frame_adv,
+ .ndo_select_queue = toeplitz_select_queue,
.ndo_get_stats64 = igb_get_stats64,
.ndo_set_rx_mode = igb_set_rx_mode,
.ndo_set_multicast_list = igb_set_rx_mode,
@@ -2660,19 +2662,14 @@ static void igb_setup_mrqc(struct igb_adapter *adapter)
u32 dword;
u8 bytes[4];
} reta;
- static const u8 rsshash[40] = {
- 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
- 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
- 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
- 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
/* Fill out hash function seeds */
for (j = 0; j < 10; j++) {
- u32 rsskey = rsshash[(j * 4)];
- rsskey |= rsshash[(j * 4) + 1] << 8;
- rsskey |= rsshash[(j * 4) + 2] << 16;
- rsskey |= rsshash[(j * 4) + 3] << 24;
- array_wr32(E1000_RSSRK(0), j, rsskey);
+ u32 toeplitz_key = (u32)toeplitz_get_key_byte((4 * j));
+ toeplitz_key |= (u32)toeplitz_get_key_byte((4 * j) + 1) << 8;
+ toeplitz_key |= (u32)toeplitz_get_key_byte((4 * j) + 2) << 16;
+ toeplitz_key |= (u32)toeplitz_get_key_byte((4 * j) + 3) << 24;
+ array_wr32(E1000_RSSRK(0), j, toeplitz_key);
}
num_rx_queues = adapter->rss_queues;
@@ -2700,8 +2697,9 @@ static void igb_setup_mrqc(struct igb_adapter *adapter)
shift = 6;
}
- for (j = 0; j < (32 * 4); j++) {
- reta.bytes[j & 3] = (j % num_rx_queues) << shift;
+ for (j = 0; j < 128; j++) {
+ u32 entry = ((j * num_rx_queues) & 0xFF80) >> 7;
+ reta.bytes[j & 3] = entry << shift;
if (shift2)
reta.bytes[j & 3] |= num_rx_queues << shift2;
if ((j & 3) == 3)
^ permalink raw reply related
* [RFC PATCH 1/3] net: add simplified 16 bit Toeplitz hash function for transmit side hashing
From: Alexander Duyck @ 2010-12-18 1:00 UTC (permalink / raw)
To: netdev
In-Reply-To: <20101218004210.28602.18499.stgit@gitlad.jf.intel.com>
This change provides transmit side scaling functionality by providing a
hash function that uses the 16 bit key to determine the queue number
that should be used for transmit.
The advantages of the 16 bit key are two fold. First it allows for a much
simpler computation as the number of outcomes are reduced to 64K, and
generation of the hash can be done using only 64bytes of data with 4
lookups in said data. The second advantage is that both TX and RX sides
will generate the same hash while using the same function. This is due the
fact that both source and destination will see the same key even though the
destination port is offset 16 bits from the source. The downside of this
is that the resultant hash is only 16 bits wide itself. It can be expanded
to 32 bits, but the 2nd 16 bits will be identical to the first.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
---
include/linux/netdevice.h | 2 +
include/linux/toeplitz.h | 89 +++++++++++++++++++++++++++++++++++++++++++++
net/core/dev.c | 68 ++++++++++++++++++++++++++++++++++
3 files changed, 159 insertions(+), 0 deletions(-)
create mode 100644 include/linux/toeplitz.h
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index cc916c5..01b5989 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -2370,6 +2370,8 @@ static inline u32 dev_ethtool_get_flags(struct net_device *dev)
return dev->ethtool_ops->get_flags(dev);
}
+extern u16 toeplitz_select_queue(struct net_device *dev, struct sk_buff *skb);
+
/* Logging, debugging and troubleshooting/diagnostic helpers. */
/* netdev_printk helpers, similar to dev_printk */
diff --git a/include/linux/toeplitz.h b/include/linux/toeplitz.h
new file mode 100644
index 0000000..2360cf4
--- /dev/null
+++ b/include/linux/toeplitz.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2010, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Author: Alexander Duyck <alexander.h.duyck@intel.com>
+ */
+
+#ifndef _LINUX_TOEPLITZ_H
+#define _LINUX_TOEPLITZ_H
+
+/*
+ * The code below implements a simplified version of toeplitz hashing. To
+ * simplify it I have reduced the key size from 40 bytes to a repeating
+ * pattern of 2 bytes. Doing this does two things. First it reduces the
+ * computation complexity significantly since I can XOR together all of the
+ * input into a single 16 bit value when computing the hash. Secondly it
+ * allows both directions of a flow to generate the same hash since now we
+ * are looking at the XORed result of the source against the destination as
+ * input.
+ */
+#define TOEPLITZ_KEY_0 0xE3
+#define TOEPLITZ_KEY_1 0xAF
+
+static inline u8 toeplitz_get_key_byte(int byte_number)
+{
+ if (byte_number & 0x1)
+ return TOEPLITZ_KEY_1;
+ else
+ return TOEPLITZ_KEY_0;
+}
+
+#define TOEPLITZ_KEY (((u64)(TOEPLITZ_KEY_1) << 32) | \
+ ((u64)(TOEPLITZ_KEY_0) << 24) | \
+ ((u64)(TOEPLITZ_KEY_1) << 16) | \
+ ((u64)(TOEPLITZ_KEY_0) << 8) | \
+ ((u64)(TOEPLITZ_KEY_1)))
+
+#define TOEPLITZ_PRECOMPUTED_VALUE(_input) ( \
+ ((((~_input >> 0) & 0x1) - 1) & ((TOEPLITZ_KEY >> 1) & 0xFFFFFFFF)) ^ \
+ ((((~_input >> 1) & 0x1) - 1) & ((TOEPLITZ_KEY >> 2) & 0xFFFFFFFF)) ^ \
+ ((((~_input >> 2) & 0x1) - 1) & ((TOEPLITZ_KEY >> 3) & 0xFFFFFFFF)) ^ \
+ ((((~_input >> 3) & 0x1) - 1) & ((TOEPLITZ_KEY >> 4) & 0xFFFFFFFF)))
+
+static const u32 toeplitz_input_values[16] = {
+ TOEPLITZ_PRECOMPUTED_VALUE(0x0),
+ TOEPLITZ_PRECOMPUTED_VALUE(0x1),
+ TOEPLITZ_PRECOMPUTED_VALUE(0x2),
+ TOEPLITZ_PRECOMPUTED_VALUE(0x3),
+ TOEPLITZ_PRECOMPUTED_VALUE(0x4),
+ TOEPLITZ_PRECOMPUTED_VALUE(0x5),
+ TOEPLITZ_PRECOMPUTED_VALUE(0x6),
+ TOEPLITZ_PRECOMPUTED_VALUE(0x7),
+ TOEPLITZ_PRECOMPUTED_VALUE(0x8),
+ TOEPLITZ_PRECOMPUTED_VALUE(0x9),
+ TOEPLITZ_PRECOMPUTED_VALUE(0xA),
+ TOEPLITZ_PRECOMPUTED_VALUE(0xB),
+ TOEPLITZ_PRECOMPUTED_VALUE(0xC),
+ TOEPLITZ_PRECOMPUTED_VALUE(0xD),
+ TOEPLITZ_PRECOMPUTED_VALUE(0xE),
+ TOEPLITZ_PRECOMPUTED_VALUE(0xF)
+};
+
+static inline u16 toeplitz_compute_hash(u32 input)
+{
+ u16 result = 0;
+
+ input ^= input >> 16;
+
+ result ^= toeplitz_input_values[(input & 0x000F)];
+ result ^= toeplitz_input_values[(input & 0x00F0) >> 4] >> 4;
+ result ^= toeplitz_input_values[(input & 0x0F00) >> 8] >> 8;
+ result ^= toeplitz_input_values[(input & 0xF000) >> 12] >> 12;
+
+ return result;
+}
+
+#endif /* _LINUX_TOEPLITZ_H */
diff --git a/net/core/dev.c b/net/core/dev.c
index 92d414a..8b4e4d3 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -132,6 +132,7 @@
#include <trace/events/skb.h>
#include <linux/pci.h>
#include <linux/inetdevice.h>
+#include <linux/toeplitz.h>
#include "net-sysfs.h"
@@ -2170,6 +2171,73 @@ u16 __skb_tx_hash(const struct net_device *dev, const struct sk_buff *skb,
}
EXPORT_SYMBOL(__skb_tx_hash);
+static inline u16 toeplitz_hash_skb(const struct net_device *dev,
+ const struct sk_buff *skb)
+{
+ union {
+ unsigned char *network;
+ struct iphdr *ipv4;
+ struct ipv6hdr *ipv6;
+ } hdr;
+ __be32 input;
+ u16 hash;
+ __be16 protocol = vlan_get_protocol(skb);
+
+ /* snag network header to get L4 type and address */
+ hdr.network = skb_network_header(skb);
+
+ /* Currently only IPv4/IPv6 with TCP is supported */
+ switch (protocol) {
+ case __constant_htons(ETH_P_IP):
+ input = hdr.ipv4->saddr ^ hdr.ipv4->daddr;
+ if (hdr.ipv4->protocol == IPPROTO_TCP)
+ input ^= *(__be32 *)tcp_hdr(skb);
+ break;
+ case __constant_htons(ETH_P_IPV6):
+ input = hdr.ipv6->saddr.s6_addr32[0] ^
+ hdr.ipv6->saddr.s6_addr32[1] ^
+ hdr.ipv6->saddr.s6_addr32[2] ^
+ hdr.ipv6->saddr.s6_addr32[3] ^
+ hdr.ipv6->daddr.s6_addr32[0] ^
+ hdr.ipv6->daddr.s6_addr32[1] ^
+ hdr.ipv6->daddr.s6_addr32[2] ^
+ hdr.ipv6->daddr.s6_addr32[3];
+ if (hdr.ipv6->nexthdr == IPPROTO_TCP)
+ input ^= *(__be32 *)tcp_hdr(skb);
+ break;
+ default:
+ return 0;
+ }
+
+ hash = toeplitz_compute_hash(ntohl(input)) & 0x7F;
+
+ return (dev->real_num_tx_queues * hash) >> 7;
+}
+
+u16 toeplitz_select_queue(struct net_device *dev, struct sk_buff *skb)
+{
+ struct sock *sk = skb->sk;
+ int queue_index = sk_tx_queue_get(sk);
+
+ if (queue_index >= 0 && queue_index < dev->real_num_tx_queues)
+ return queue_index;
+
+ queue_index = 0;
+
+ if (dev->real_num_tx_queues > 1)
+ queue_index = toeplitz_hash_skb(dev, skb);
+
+ if (sk) {
+ struct dst_entry *dst =
+ rcu_dereference_check(sk->sk_dst_cache, 1);
+ if (dst && skb_dst(skb) == dst)
+ sk_tx_queue_set(sk, queue_index);
+ }
+
+ return queue_index;
+}
+EXPORT_SYMBOL(toeplitz_select_queue);
+
static inline u16 dev_cap_txqueue(struct net_device *dev, u16 queue_index)
{
if (unlikely(queue_index >= dev->real_num_tx_queues)) {
^ permalink raw reply related
* [RFC PATCH 2/3] ixgbe: example of how to update ixgbe to make use of in-kernel Toeplitz hash
From: Alexander Duyck @ 2010-12-18 1:00 UTC (permalink / raw)
To: netdev
In-Reply-To: <20101218004210.28602.18499.stgit@gitlad.jf.intel.com>
This change allows ixgbe to make use of the in-kernel Toeplitz hashing so
that RX and TX hash queues can be matched up.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
---
drivers/net/ixgbe/ixgbe_main.c | 47 ++++++++++++++++++++++------------------
1 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index a060610..0d0fcde 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -42,6 +42,7 @@
#include <linux/ethtool.h>
#include <linux/if_vlan.h>
#include <scsi/fc/fc_fcoe.h>
+#include <linux/toeplitz.h>
#include "ixgbe.h"
#include "ixgbe_common.h"
@@ -2847,27 +2848,31 @@ static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
{
struct ixgbe_hw *hw = &adapter->hw;
- static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
- 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
- 0x6A3E67EA, 0x14364D17, 0x3BED200D};
- u32 mrqc = 0, reta = 0;
+ u32 mrqc = 0;
u32 rxcsum;
- int i, j;
+ int i, j, indices;
int mask;
/* Fill out hash function seeds */
- for (i = 0; i < 10; i++)
- IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
+ for (i = 0; i < 10; i++) {
+ u32 toeplitz_key = (u32)toeplitz_get_key_byte((4 * i));
+ toeplitz_key |= (u32)toeplitz_get_key_byte((4 * i) + 1) << 8;
+ toeplitz_key |= (u32)toeplitz_get_key_byte((4 * i) + 2) << 16;
+ toeplitz_key |= (u32)toeplitz_get_key_byte((4 * i) + 3) << 24;
+ IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), toeplitz_key);
+ }
/* Fill out redirection table */
- for (i = 0, j = 0; i < 128; i++, j++) {
- if (j == adapter->ring_feature[RING_F_RSS].indices)
- j = 0;
+ indices = adapter->ring_feature[RING_F_RSS].indices;
+ for (i = 0; i < 32; i++) {
+ u32 reta = 0;
/* reta = 4-byte sliding window of
* 0x00..(indices-1)(indices-1)00..etc. */
- reta = (reta << 8) | (j * 0x11);
- if ((i & 3) == 3)
- IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
+ for (j = 0; j < 4; j++) {
+ u32 entry = (indices * ((i * 4) + j)) >> 7;
+ reta |= entry << (8 * j);
+ }
+ IXGBE_WRITE_REG(hw, IXGBE_RETA(i), reta);
}
/* Disable indicating checksum in descriptor, enables RSS hash */
@@ -6643,14 +6648,8 @@ static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
#endif
}
}
-#endif
-
- if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
- while (unlikely(txq >= dev->real_num_tx_queues))
- txq -= dev->real_num_tx_queues;
- return txq;
- }
+#endif
if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
if (skb->priority == TC_PRIO_CONTROL)
txq = adapter->ring_feature[RING_F_DCB].indices-1;
@@ -6660,7 +6659,13 @@ static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
return txq;
}
- return skb_tx_hash(dev, skb);
+ if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
+ while (unlikely(txq >= dev->real_num_tx_queues))
+ txq -= dev->real_num_tx_queues;
+ return txq;
+ }
+
+ return toeplitz_select_queue(dev, skb);
}
netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
^ permalink raw reply related
* [RFC PATCH 0/3] Simplified 16 bit Toeplitz hash algorithm
From: Alexander Duyck @ 2010-12-18 1:00 UTC (permalink / raw)
To: netdev
This patch series is meant to be a proof of concept for simplifying the cost
of Toeplitz hashing by reducing the complexity of the key to a 16 bit
repeating value. The resultant advantages are that the hash computation
performance is significantly increased, and that the resultant hash is the
same for flows in either direction.
The idea for this occurred to me while working on the ATR hashing algorithms
and improving their performance. ATR implements a 32 bit repeating key which
results in us being able to XOR everything down to a 32 bit value. By using a
16 bit key we are able to cut down the 12 to 36 byte input value to only 2
bytes via XOR operations. This reduces the resultant hash to 16 bits, however
since queue selection only requires 7 bits for RSS that still leaves us with a
large enough resultant key.
I'm currently not planning to do any more work on this in the near future as I
have several other projects in which I am currently engaged. However I just
wanted to put this code out there in case anyone had a use for it.
Thanks,
Alex
---
Alexander Duyck (3):
igb: example of how to update igb to make use of in-kernel Toeplitz hashing
ixgbe: example of how to update ixgbe to make use of in-kernel Toeplitz hash
net: add simplified 16 bit Toeplitz hash function for transmit side hashing
drivers/net/igb/igb_main.c | 22 ++++------
drivers/net/ixgbe/ixgbe_main.c | 47 ++++++++++++---------
include/linux/netdevice.h | 2 +
include/linux/toeplitz.h | 89 ++++++++++++++++++++++++++++++++++++++++
net/core/dev.c | 68 +++++++++++++++++++++++++++++++
5 files changed, 195 insertions(+), 33 deletions(-)
create mode 100644 include/linux/toeplitz.h
--
^ permalink raw reply
* Re: [PATCH v2] kptr_restrict for hiding kernel pointers from unprivileged users
From: Dan Rosenberg @ 2010-12-18 1:12 UTC (permalink / raw)
To: Andrew Morton
Cc: linux-kernel, linux-security-module, netdev, jmorris, eugeneteo,
kees.cook, mingo, davem
In-Reply-To: <20101217164431.08f3e730.akpm@linux-foundation.org>
> The changelog doesn't describe why CONFIG_SECURITY_KPTR_RESTRICT
> exists, nor why the kptr_restrict sysctl exists. I can kinda guess why
> this was done, but it would be much better if your reasoning was
> present here.
>
> And I'd question whether we need CONFIG_SECURITY_KPTR_RESTRICT at all.
> Disabling it saves no memory. Its presence just increases the level of
> incompatibility between different vendor's kernels and potentially
> doubles the number of kernels which distros must ship (which they of
> course won't do). It might be better to add a kptr_restrict=1 kernel boot
> option (although people sometimes have problems with boot options in
> embedded environments).
>
> All that being said, distro initscripts can just set the sysctl to the
> desired value before any non-root process has even started, but this
> apparently is far too hard for them :(
>
> Finally, the changelog and the documentation changes don't tell us the
> full /proc path to the kptr_restrict pseudo-file. That would be useful
> info. Seems that it's /proc/sys/kernel/kptr_restrict?
>
I'll send a clean-up patch tomorrow fixing the documentation issues.
I'm also willing to take more feedback on the need for a config - this
was the approach that was recommended to me recently with
dmesg_restrict, but I also understand your reasoning.
> >
> > ...
> >
> > --- a/lib/vsprintf.c
> > +++ b/lib/vsprintf.c
> > @@ -936,6 +936,8 @@ char *uuid_string(char *buf, char *end, const u8 *addr,
> > return string(buf, end, uuid, spec);
> > }
> >
> > +int kptr_restrict = CONFIG_SECURITY_KPTR_RESTRICT;
> > +
> > /*
> > * Show a '%p' thing. A kernel extension is that the '%p' is followed
> > * by an extra set of alphanumeric characters that are extended format
> > @@ -979,6 +981,7 @@ char *uuid_string(char *buf, char *end, const u8 *addr,
> > * Implements a "recursive vsnprintf".
> > * Do not use this feature without some mechanism to verify the
> > * correctness of the format string and va_list arguments.
> > + * - 'K' For a kernel pointer that should be hidden from unprivileged users
> > *
> > * Note: The difference between 'S' and 'F' is that on ia64 and ppc64
> > * function pointers are really function descriptors, which contain a
> > @@ -1035,6 +1038,21 @@ char *pointer(const char *fmt, char *buf, char *end, void *ptr,
> > return buf + vsnprintf(buf, end - buf,
> > ((struct va_format *)ptr)->fmt,
> > *(((struct va_format *)ptr)->va));
> > + case 'K':
> > + if (kptr_restrict) {
> > + if (in_irq() || in_serving_softirq() || in_nmi())
> > + WARN(1, "%%pK used in interrupt context.\n");
> > +
> > + else if (capable(CAP_SYSLOG))
> > + break;
>
> And the reason why it's unusable in interrupt context is that we can't
> meaningfully check CAP_SYSLOG from interrupt.
>
> Fair enough, but this does restrict %pK's usefulness.
>
> I think I'd be more comfortable with a WARN_ONCE here. If someone
> screws up then we don't want to spew thousands of repeated warnings at
> our poor users - one will do.
>
>
Agreed.
>
> So what's next? We need to convert 1,000,000 %p callsites to use %pK?
> That'll be fun. Please consider adding a new checkpatch rule which
> detects %p and asks people whether they should have used %pK.
The goal of this format specifier is specifically for pointers that are
exposed to unprivileged users. I agree that hiding all kernel pointers
would be nice, but I don't expect the angry masses to ever agree to
that. For now, I'll isolate specific cases, especially in /proc, that
are clear risks in terms of information leakage. I'll also be skipping
over pointers written to the syslog, since I think hiding that
information is dmesg_restrict's job.
Thanks,
Dan
^ permalink raw reply
* Re: [PATCH v2] kptr_restrict for hiding kernel pointers from unprivileged users
From: Andrew Morton @ 2010-12-18 1:22 UTC (permalink / raw)
To: Dan Rosenberg
Cc: linux-kernel, linux-security-module, netdev, jmorris, eugeneteo,
kees.cook, mingo, davem
In-Reply-To: <1292634759.9764.26.camel@Dan>
On Fri, 17 Dec 2010 20:12:39 -0500
Dan Rosenberg <drosenberg@vsecurity.com> wrote:
> >
> > So what's next? We need to convert 1,000,000 %p callsites to use %pK?
> > That'll be fun. Please consider adding a new checkpatch rule which
> > detects %p and asks people whether they should have used %pK.
>
> The goal of this format specifier is specifically for pointers that are
> exposed to unprivileged users. I agree that hiding all kernel pointers
> would be nice, but I don't expect the angry masses to ever agree to
> that. For now, I'll isolate specific cases, especially in /proc, that
> are clear risks in terms of information leakage. I'll also be skipping
> over pointers written to the syslog, since I think hiding that
> information is dmesg_restrict's job.
Well... some administrators may wish to hide the pointer values even
for privileged callers. That's a pretty trivial add-on for the code
which you have, and means that those admins can also suppress the
pointers for IRQ-time callers. More /proc knobs :)
Then again, perhaps those admins would be OK if we simply disabled
plain old %p everywhere. In which case we're looking at a separate
patch, I suggest.
^ permalink raw reply
* Re: [PATCHv4] fragment locally generated tunnel-mode IPSec6 packets as needed
From: Herbert Xu @ 2010-12-18 2:16 UTC (permalink / raw)
To: David L Stevens; +Cc: davem, netdev
In-Reply-To: <1292622162.1700.3.camel@IBM-1B506CFC885>
On Fri, Dec 17, 2010 at 01:42:42PM -0800, David L Stevens wrote:
> This patch modifies IPsec6 to fragment IPv6 packets that are
> locally generated as needed.
>
> This version of the patch only fragments in tunnel mode, so that fragment
> headers will not be obscured by ESP in transport mode.
>
> Signed-off-by: David L Stevens <dlstevens@us.ibm.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Thanks,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH] net/e1000e : Fix to use dev_kfree_skb_any() instead of dev_kfree_skb() in _jumbo_rx_irq
From: Jeff Kirsher @ 2010-12-18 3:17 UTC (permalink / raw)
To: prasanna.panchamukhi; +Cc: e1000-devel, netdev
In-Reply-To: <4D0BE4BC.10004@riverbed.com>
On Fri, Dec 17, 2010 at 14:31, Prasanna Panchamukhi
<ppanchamukhi@riverbed.com> wrote:
>
> Several "Warning: kfree_skb on hard IRQ" messages have been observed from
> the net/e1000e driver, e1000_clean_jumbo_rx_irq() routine calling
> dev_kfree_skb(). This patch fixes the above warning messages by
> calling dev_kfree_skb_any() instead of dev_kfree_skb().
>
> Signed-off-by: Prasanna S. Panchamukhi<prasanna.panchamukhi@riverbed.com>
> ---
> drivers/net/e1000e/netdev.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
Thanks, I have added it to my tree for review and testing.
--
Cheers,
Jeff
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^ permalink raw reply
* [PATCH 1/1] TCP: increase default initial receive window.
From: Nandita Dukkipati @ 2010-12-18 3:20 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, Tom Herbert, Laurent Chavey, Yuchung Cheng,
Nandita Dukkipati
This patch changes the default initial receive window to 10 mss
(defined constant). The default window is limited to the maximum
of 10*1460 and 2*mss (when mss > 1460).
Signed-off-by: Nandita Dukkipati <nanditad@google.com>
---
include/net/tcp.h | 3 +++
net/ipv4/tcp_output.c | 11 ++++++++---
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/include/net/tcp.h b/include/net/tcp.h
index 2ab6c9c..6c25ba8 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -60,6 +60,9 @@ extern void tcp_time_wait(struct sock *sk, int state, int timeo);
*/
#define MAX_TCP_WINDOW 32767U
+/* Offer an initial receive window of 10 mss. */
+#define TCP_DEFAULT_INIT_RCVWND 10
+
/* Minimal accepted MSS. It is (60+60+8) - (20+20). */
#define TCP_MIN_MSS 88U
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 2d39066..dc7c096 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -228,10 +228,15 @@ void tcp_select_initial_window(int __space, __u32 mss,
}
}
- /* Set initial window to value enough for senders, following RFC5681. */
+ /* Set initial window to a value enough for senders starting with
+ * initial congestion window of TCP_DEFAULT_INIT_RCVWND. Place
+ * a limit on the initial window when mss is larger than 1460.
+ */
if (mss > (1 << *rcv_wscale)) {
- int init_cwnd = rfc3390_bytes_to_packets(mss);
-
+ int init_cwnd = TCP_DEFAULT_INIT_RCVWND;
+ if (mss > 1460)
+ init_cwnd =
+ max_t(u32, (1460 * TCP_DEFAULT_INIT_RCVWND) / mss, 2);
/* when initializing use the value from init_rcv_wnd
* rather than the default from above
*/
--
1.7.3.1
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