* Re: [PATCH net-next] icmp: add a global rate limitation
From: Eric Dumazet @ 2014-09-22 20:25 UTC (permalink / raw)
To: David Miller; +Cc: netdev
In-Reply-To: <20140922.160904.1566383839759663411.davem@davemloft.net>
On Mon, 2014-09-22 at 16:09 -0400, David Miller wrote:
> From: Eric Dumazet <eric.dumazet@gmail.com>
> Date: Fri, 19 Sep 2014 07:38:40 -0700
>
> > Current ICMP rate limiting uses inetpeer cache, which is an RBL tree
> > protected by a lock, meaning that hosts can be stuck hard if all cpus
> > want to check ICMP limits.
>
> However, the replacement uses a single global spinlock for
> synchronization.
>
> ...
> > Note that if we really want to send millions of ICMP messages per
> > second, we might extend idea and infra added in commit 04ca6973f7c1a
> > ("ip: make IP identifiers less predictable") :
> > add a token bucket in the ip_idents hash and no longer rely on inetpeer.
>
> That would be preferred.
>
> I don't really see how this patch makes things better. The code goes
> through a global spinlock unconditionally, and if it passes then it
> looks up the inetpeer anyways.
>
The inetpeer is only hit at most 1000 times per second, which is a
rather low rate.
> I need more information to be convinced that this is an improvement
> and that it actually solves the stated problem. I'm sure you also
> have some performance metrics to share, right? :-)
It does not use the global spinlock in the stress situation.
I tested this patch I can tell you it works ;)
+ /* Check if token bucket is empty and cannot be refilled
+ * without taking the spinlock.
+ */
+ if (!icmp_global.credit) {
+ delta = min_t(u32, now - icmp_global.stamp, HZ);
+ if (delta < HZ / 50)
+ return false;
+ }
+
So if we are under pressure (credit is exhausted), we exit early unless
20ms were elapsed, and in this case we'll refill the token bucket.
Thanks
^ permalink raw reply
* Re: [PATCH v3 net-next] tcp: avoid possible arithmetic overflows
From: David Miller @ 2014-09-22 20:27 UTC (permalink / raw)
To: eric.dumazet; +Cc: ycheng, joe, netdev, ncardwell
In-Reply-To: <1411417184.26859.147.camel@edumazet-glaptop2.roam.corp.google.com>
From: Eric Dumazet <eric.dumazet@gmail.com>
Date: Mon, 22 Sep 2014 13:19:44 -0700
> From: Eric Dumazet <edumazet@google.com>
>
> icsk_rto is a 32bit field, and icsk_backoff can reach 15 by default,
> or more if some sysctl (eg tcp_retries2) are changed.
>
> Better use 64bit to perform icsk_rto << icsk_backoff operations
>
> As Joe Perches suggested, add a helper for this.
>
> Yuchung spotted the tcp_v4_err() case.
>
> From: Eric Dumazet <edumazet@google.com>
I assume you meant "Signed-off-by: " on that last line, not "From: " :-)
Applied,
^ permalink raw reply
* Re: [PATCH v3 net-next] tcp: avoid possible arithmetic overflows
From: Eric Dumazet @ 2014-09-22 20:28 UTC (permalink / raw)
To: David Miller; +Cc: ycheng, joe, netdev, ncardwell
In-Reply-To: <20140922.162703.824025819934075774.davem@davemloft.net>
On Mon, 2014-09-22 at 16:27 -0400, David Miller wrote:
> From: Eric Dumazet <eric.dumazet@gmail.com>
> Date: Mon, 22 Sep 2014 13:19:44 -0700
>
> > From: Eric Dumazet <edumazet@google.com>
> >
> > icsk_rto is a 32bit field, and icsk_backoff can reach 15 by default,
> > or more if some sysctl (eg tcp_retries2) are changed.
> >
> > Better use 64bit to perform icsk_rto << icsk_backoff operations
> >
> > As Joe Perches suggested, add a helper for this.
> >
> > Yuchung spotted the tcp_v4_err() case.
> >
> > From: Eric Dumazet <edumazet@google.com>
>
> I assume you meant "Signed-off-by: " on that last line, not "From: " :-)
>
> Applied,
Arg, thanks David ;)
^ permalink raw reply
* Re: [PATCH net-next v2 2/5] net: tcp: add flag for ca to indicate that ECN is required
From: David Miller @ 2014-09-22 20:33 UTC (permalink / raw)
To: fw; +Cc: hagen, lars, eric.dumazet, fontana, hannes, glenn.judd, dborkman,
netdev
In-Reply-To: <1411248562-26581-3-git-send-email-fw@strlen.de>
From: Florian Westphal <fw@strlen.de>
Date: Sat, 20 Sep 2014 23:29:19 +0200
> From: Daniel Borkmann <dborkman@redhat.com>
>
> This patch adds a flag to TCP congestion algorithms that allows
> for requesting to mark IPv4/IPv6 sockets with transport as ECN
> capable, that is, ECT(0), when required by a congestion algorithm.
>
> It is currently used and needed in DataCenter TCP (DCTCP), as it
> requires both peers to assert ECT on all IP packets sent - it
> uses ECN feedback (i.e. CE, Congestion Encountered information)
> from switches inside the data center to derive feedback to the
> end hosts.
>
> Therefore, simply add a new flag to icsk_ca_ops. Note that DCTCP's
> algorithm/behaviour slightly diverges from RFC3168, therefore this
> is only (!) enabled iff the assigned congestion control ops module
> has requested this. By that, we can tightly couple this logic really
> only to the provided congestion control ops.
>
> Joint work with Florian Westphal and Glenn Judd.
>
> Signed-off-by: Daniel Borkmann <dborkman@redhat.com>
> Signed-off-by: Florian Westphal <fw@strlen.de>
> Signed-off-by: Glenn Judd <glenn.judd@morganstanley.com>
I don't think any administrator is going to be happy with this behavior.
If he explicitly sets the tcp_ecn sysctl to zero, and then an
unprivileged user can just start emitting ECN bits by selecting a
different congestion control algorithm, that is unexpected.
Please instead make datacenter TCP require ECN to be enabled.
Thanks.
^ permalink raw reply
* [PATCH] macvtap: Fix race between device delete and open.
From: Vladislav Yasevich @ 2014-09-22 20:34 UTC (permalink / raw)
To: netdev; +Cc: Vladislav Yasevich, Michael S. Tsirkin, Jason Wang
In macvtap device delete and open calls can race and
this causes a list curruption of the vlan queue_list.
The race intself is triggered by the idr accessors
that located the vlan device. The device is stored
into and removed from the idr under both an rtnl and
a mutex. However, when attempting to locate the device
in idr, only a mutex is taken. As a result, once cpu
perfoming a delete may take an rtnl and wait for the mutex,
while another cput doing an open() will take the idr
mutex first to fetch the device pointer and later take
an rtnl to add a queue for the device which may have
just gotten deleted.
With this patch, we now hold the rtnl for the duration
of the macvtap_open() call thus making sure that
open will not race with delete.
CC: Michael S. Tsirkin <mst@redhat.com>
CC: Jason Wang <jasowang@redhat.com>
Signed-off-by: Vladislav Yasevich <vyasevic@redhat.com>
---
drivers/net/macvtap.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/net/macvtap.c b/drivers/net/macvtap.c
index 3381c4f..0c6adaa 100644
--- a/drivers/net/macvtap.c
+++ b/drivers/net/macvtap.c
@@ -112,17 +112,15 @@ out:
return err;
}
+/* Requires RTNL */
static int macvtap_set_queue(struct net_device *dev, struct file *file,
struct macvtap_queue *q)
{
struct macvlan_dev *vlan = netdev_priv(dev);
- int err = -EBUSY;
- rtnl_lock();
if (vlan->numqueues == MAX_MACVTAP_QUEUES)
- goto out;
+ return -EBUSY;
- err = 0;
rcu_assign_pointer(q->vlan, vlan);
rcu_assign_pointer(vlan->taps[vlan->numvtaps], q);
sock_hold(&q->sk);
@@ -136,9 +134,7 @@ static int macvtap_set_queue(struct net_device *dev, struct file *file,
vlan->numvtaps++;
vlan->numqueues++;
-out:
- rtnl_unlock();
- return err;
+ return 0;
}
static int macvtap_disable_queue(struct macvtap_queue *q)
@@ -454,11 +450,12 @@ static void macvtap_sock_destruct(struct sock *sk)
static int macvtap_open(struct inode *inode, struct file *file)
{
struct net *net = current->nsproxy->net_ns;
- struct net_device *dev = dev_get_by_macvtap_minor(iminor(inode));
+ struct net_device *dev;
struct macvtap_queue *q;
- int err;
+ int err = -ENODEV;
- err = -ENODEV;
+ rtnl_lock();
+ dev = dev_get_by_macvtap_minor(iminor(inode));
if (!dev)
goto out;
@@ -498,6 +495,7 @@ out:
if (dev)
dev_put(dev);
+ rtnl_unlock();
return err;
}
--
1.9.3
^ permalink raw reply related
* [PATCH net-next] net: sched: fix compile warning in cls_u32
From: Eric Dumazet @ 2014-09-22 20:42 UTC (permalink / raw)
To: David Miller; +Cc: netdev
From: Eric Dumazet <edumazet@google.com>
$ grep CONFIG_CLS_U32_MARK .config
# CONFIG_CLS_U32_MARK is not set
net/sched/cls_u32.c: In function 'u32_change':
net/sched/cls_u32.c:852:1: warning: label 'errout' defined but not used
[-Wunused-label]
Signed-off-by: Eric Dumazet <edumazet@google.com>
---
net/sched/cls_u32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/sched/cls_u32.c b/net/sched/cls_u32.c
index e3fb5308d44a..ef97a646ee94 100644
--- a/net/sched/cls_u32.c
+++ b/net/sched/cls_u32.c
@@ -847,9 +847,9 @@ static int u32_change(struct net *net, struct sk_buff *in_skb,
#ifdef CONFIG_CLS_U32_MARK
free_percpu(n->pcpu_success);
+errout:
#endif
-errout:
#ifdef CONFIG_CLS_U32_PERF
free_percpu(n->pf);
#endif
^ permalink raw reply related
* Re: pull request (net): ipsec 2014-09-22
From: David Miller @ 2014-09-22 20:43 UTC (permalink / raw)
To: steffen.klassert; +Cc: herbert, netdev
In-Reply-To: <1411364320-5309-1-git-send-email-steffen.klassert@secunet.com>
From: Steffen Klassert <steffen.klassert@secunet.com>
Date: Mon, 22 Sep 2014 07:38:38 +0200
> We generate a blackhole or queueing route if a packet
> matches an IPsec policy but a state can't be resolved.
> Here we assume that dst_output() is called to kill
> these packets. Unfortunately this assumption is not
> true in all cases, so it is possible that these packets
> leave the system without the necessary transformations.
>
> This pull request contains two patches to fix this issue:
>
> 1) Fix for blackhole routed packets.
>
> 2) Fix for queue routed packets.
>
> Both patches are serious stable candidates.
>
> Please pull or let me know if there are problems.
Pulled and queued up for -stable, thanks.
^ permalink raw reply
* Re: [PATCH net] ip_tunnel: Don't allow to add the same tunnel multiple times.
From: David Miller @ 2014-09-22 20:45 UTC (permalink / raw)
To: steffen.klassert; +Cc: netdev
In-Reply-To: <20140922071108.GY6390@secunet.com>
From: Steffen Klassert <steffen.klassert@secunet.com>
Date: Mon, 22 Sep 2014 09:11:08 +0200
> When we try to add an already existing tunnel, we don't return
> an error. Instead we continue and call ip_tunnel_update().
> This means that we can change existing tunnels by adding
> the same tunnel multiple times. It is even possible to change
> the tunnel endpoints of the fallback device.
>
> We fix this by returning an error if we try to add an existing
> tunnel.
>
> Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
> ---
>
> I was not able to find a commit that introduced this bug.
> Looks like ipip and ip_gre had similar bugs already with
> the initial git commit.
I'm not so sure about this, perhaps the behavior of being able to
change a configuration using an ADD call is intentional?
^ permalink raw reply
* Re: [PATCH net-next] net: sched: fix compile warning in cls_u32
From: David Miller @ 2014-09-22 20:47 UTC (permalink / raw)
To: eric.dumazet; +Cc: netdev
In-Reply-To: <1411418573.26859.157.camel@edumazet-glaptop2.roam.corp.google.com>
From: Eric Dumazet <eric.dumazet@gmail.com>
Date: Mon, 22 Sep 2014 13:42:53 -0700
> From: Eric Dumazet <edumazet@google.com>
>
> $ grep CONFIG_CLS_U32_MARK .config
> # CONFIG_CLS_U32_MARK is not set
>
> net/sched/cls_u32.c: In function 'u32_change':
> net/sched/cls_u32.c:852:1: warning: label 'errout' defined but not used
> [-Wunused-label]
>
> Signed-off-by: Eric Dumazet <edumazet@google.com>
Applied, thanks Eric.
^ permalink raw reply
* [PATCH net-next v3] fec: Remove fec_enet_select_queue()
From: Fabio Estevam @ 2014-09-22 20:55 UTC (permalink / raw)
To: davem; +Cc: Frank.Li, netdev, Fabio Estevam
From: Fabio Estevam <fabio.estevam@freescale.com>
Sparse complains about fec_enet_select_queue() not being static.
Feedback from David Miller [1] was to remove this function instead of making it
static:
"Please just delete this function.
It's overriding code which does exactly the same thing.
Actually, more precisely, this code is duplicating code in a way that
bypasses many core facilitites of the networking. For example, this
override means that socket based flow steering, XPS, etc. are all
not happening on these devices.
Without ->ndo_select_queue(), the flow dissector does __netdev_pick_tx
which is exactly what you want to happen."
[1] http://www.spinics.net/lists/netdev/msg297653.html
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- Remove fec_enet_select_queue() instead of making it static.
drivers/net/ethernet/freescale/fec_main.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 09d7f5f..33a7410 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -2851,17 +2851,10 @@ static int fec_set_features(struct net_device *netdev,
return 0;
}
-u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
- void *accel_priv, select_queue_fallback_t fallback)
-{
- return skb_tx_hash(ndev, skb);
-}
-
static const struct net_device_ops fec_netdev_ops = {
.ndo_open = fec_enet_open,
.ndo_stop = fec_enet_close,
.ndo_start_xmit = fec_enet_start_xmit,
- .ndo_select_queue = fec_enet_select_queue,
.ndo_set_rx_mode = set_multicast_list,
.ndo_change_mtu = eth_change_mtu,
.ndo_validate_addr = eth_validate_addr,
--
1.9.1
^ permalink raw reply related
* [RFC PATCH linux-next] et131x: Promote staging et131x driver to drivers/net
From: Mark Einon @ 2014-09-22 21:28 UTC (permalink / raw)
To: gregkh, davem; +Cc: linux-kernel, netdev, devel, Mark Einon
This patch moves the et131x gigabit ethernet driver from drivers/staging
to drivers/net/ethernet/agere.
There are no known issues at this time.
Signed-off-by: Mark Einon <mark.einon@gmail.com>
---
This patch will only apply once the last few pending changes
make their way from staging-next to linux-next, but posting
now in the hope that feedback can be given and this change can
make it in before the next merge window.
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/agere/Kconfig | 31 +
drivers/net/ethernet/agere/Makefile | 5 +
drivers/net/ethernet/agere/et131x.c | 4412 +++++++++++++++++++++++++++++++++++
drivers/net/ethernet/agere/et131x.h | 1533 ++++++++++++
drivers/staging/Kconfig | 2 -
drivers/staging/Makefile | 1 -
drivers/staging/et131x/Kconfig | 10 -
drivers/staging/et131x/Makefile | 5 -
drivers/staging/et131x/README | 15 -
drivers/staging/et131x/et131x.c | 4412 -----------------------------------
drivers/staging/et131x/et131x.h | 1533 ------------
13 files changed, 5983 insertions(+), 5978 deletions(-)
create mode 100644 drivers/net/ethernet/agere/Kconfig
create mode 100644 drivers/net/ethernet/agere/Makefile
create mode 100644 drivers/net/ethernet/agere/et131x.c
create mode 100644 drivers/net/ethernet/agere/et131x.h
delete mode 100644 drivers/staging/et131x/Kconfig
delete mode 100644 drivers/staging/et131x/Makefile
delete mode 100644 drivers/staging/et131x/README
delete mode 100644 drivers/staging/et131x/et131x.c
delete mode 100644 drivers/staging/et131x/et131x.h
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index dc7406c..d48fc9c 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -20,6 +20,7 @@ config SUNGEM_PHY
source "drivers/net/ethernet/3com/Kconfig"
source "drivers/net/ethernet/adaptec/Kconfig"
source "drivers/net/ethernet/aeroflex/Kconfig"
+source "drivers/net/ethernet/agere/Kconfig"
source "drivers/net/ethernet/allwinner/Kconfig"
source "drivers/net/ethernet/alteon/Kconfig"
source "drivers/net/ethernet/altera/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 224a018..89207ac 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_VENDOR_3COM) += 3com/
obj-$(CONFIG_NET_VENDOR_8390) += 8390/
obj-$(CONFIG_NET_VENDOR_ADAPTEC) += adaptec/
obj-$(CONFIG_GRETH) += aeroflex/
+obj-$(CONFIG_NET_VENDOR_AGERE) += agere/
obj-$(CONFIG_NET_VENDOR_ALLWINNER) += allwinner/
obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
obj-$(CONFIG_ALTERA_TSE) += altera/
diff --git a/drivers/net/ethernet/agere/Kconfig b/drivers/net/ethernet/agere/Kconfig
new file mode 100644
index 0000000..b26b185a
--- /dev/null
+++ b/drivers/net/ethernet/agere/Kconfig
@@ -0,0 +1,31 @@
+#
+# Agere device configuration
+#
+
+config NET_VENDOR_AGERE
+ bool "Agere devices"
+ default y
+ depends on PCI
+ ---help---
+ If you have a network (Ethernet) card belonging to this class, say Y
+ and read the Ethernet-HOWTO, available from
+ <http://www.tldp.org/docs.html#howto>.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Atheros devices. If you say Y, you will be asked
+ for your specific card in the following questions.
+
+if NET_VENDOR_AGERE
+
+config ET131X
+ tristate "Agere ET-1310 Gigabit Ethernet support"
+ depends on PCI
+ select PHYLIB
+ ---help---
+ This driver supports Agere ET-1310 ethernet adapters.
+
+ To compile this driver as a module, choose M here. The module
+ will be called et131x.
+
+endif # NET_VENDOR_AGERE
diff --git a/drivers/net/ethernet/agere/Makefile b/drivers/net/ethernet/agere/Makefile
new file mode 100644
index 0000000..027ff94
--- /dev/null
+++ b/drivers/net/ethernet/agere/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Agere ET-131x ethernet driver
+#
+
+obj-$(CONFIG_ET131X) += et131x.o
diff --git a/drivers/net/ethernet/agere/et131x.c b/drivers/net/ethernet/agere/et131x.c
new file mode 100644
index 0000000..93afd61
--- /dev/null
+++ b/drivers/net/ethernet/agere/et131x.c
@@ -0,0 +1,4412 @@
+/* Agere Systems Inc.
+ * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ * http://www.agere.com
+ *
+ * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
+ *
+ *------------------------------------------------------------------------------
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software. Using this
+ * software indicates your acceptance of these terms and conditions. If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following Disclaimer as comments in the code as
+ * well as in the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following Disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/pci.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/sched.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/in.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/if_arp.h>
+#include <linux/ioport.h>
+#include <linux/crc32.h>
+#include <linux/random.h>
+#include <linux/phy.h>
+
+#include "et131x.h"
+
+MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
+MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
+
+/* EEPROM defines */
+#define MAX_NUM_REGISTER_POLLS 1000
+#define MAX_NUM_WRITE_RETRIES 2
+
+/* MAC defines */
+#define COUNTER_WRAP_16_BIT 0x10000
+#define COUNTER_WRAP_12_BIT 0x1000
+
+/* PCI defines */
+#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
+#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
+
+/* ISR defines */
+/* For interrupts, normal running is:
+ * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
+ * watchdog_interrupt & txdma_xfer_done
+ *
+ * In both cases, when flow control is enabled for either Tx or bi-direction,
+ * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
+ * buffer rings are running low.
+ */
+#define INT_MASK_DISABLE 0xffffffff
+
+/* NOTE: Masking out MAC_STAT Interrupt for now...
+ * #define INT_MASK_ENABLE 0xfff6bf17
+ * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
+ */
+#define INT_MASK_ENABLE 0xfffebf17
+#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
+
+/* General defines */
+/* Packet and header sizes */
+#define NIC_MIN_PACKET_SIZE 60
+
+/* Multicast list size */
+#define NIC_MAX_MCAST_LIST 128
+
+/* Supported Filters */
+#define ET131X_PACKET_TYPE_DIRECTED 0x0001
+#define ET131X_PACKET_TYPE_MULTICAST 0x0002
+#define ET131X_PACKET_TYPE_BROADCAST 0x0004
+#define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
+#define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
+
+/* Tx Timeout */
+#define ET131X_TX_TIMEOUT (1 * HZ)
+#define NIC_SEND_HANG_THRESHOLD 0
+
+/* MP_ADAPTER flags */
+#define FMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
+
+/* MP_SHARED flags */
+#define FMP_ADAPTER_LOWER_POWER 0x00200000
+
+#define FMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
+#define FMP_ADAPTER_HARDWARE_ERROR 0x04000000
+
+#define FMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
+
+/* Some offsets in PCI config space that are actually used. */
+#define ET1310_PCI_MAC_ADDRESS 0xA4
+#define ET1310_PCI_EEPROM_STATUS 0xB2
+#define ET1310_PCI_ACK_NACK 0xC0
+#define ET1310_PCI_REPLAY 0xC2
+#define ET1310_PCI_L0L1LATENCY 0xCF
+
+/* PCI Product IDs */
+#define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
+#define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
+
+/* Define order of magnitude converter */
+#define NANO_IN_A_MICRO 1000
+
+#define PARM_RX_NUM_BUFS_DEF 4
+#define PARM_RX_TIME_INT_DEF 10
+#define PARM_RX_MEM_END_DEF 0x2bc
+#define PARM_TX_TIME_INT_DEF 40
+#define PARM_TX_NUM_BUFS_DEF 4
+#define PARM_DMA_CACHE_DEF 0
+
+/* RX defines */
+#define FBR_CHUNKS 32
+#define MAX_DESC_PER_RING_RX 1024
+
+/* number of RFDs - default and min */
+#define RFD_LOW_WATER_MARK 40
+#define NIC_DEFAULT_NUM_RFD 1024
+#define NUM_FBRS 2
+
+#define MAX_PACKETS_HANDLED 256
+
+#define ALCATEL_MULTICAST_PKT 0x01000000
+#define ALCATEL_BROADCAST_PKT 0x02000000
+
+/* typedefs for Free Buffer Descriptors */
+struct fbr_desc {
+ u32 addr_lo;
+ u32 addr_hi;
+ u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
+};
+
+/* Packet Status Ring Descriptors
+ *
+ * Word 0:
+ *
+ * top 16 bits are from the Alcatel Status Word as enumerated in
+ * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
+ *
+ * 0: hp hash pass
+ * 1: ipa IP checksum assist
+ * 2: ipp IP checksum pass
+ * 3: tcpa TCP checksum assist
+ * 4: tcpp TCP checksum pass
+ * 5: wol WOL Event
+ * 6: rxmac_error RXMAC Error Indicator
+ * 7: drop Drop packet
+ * 8: ft Frame Truncated
+ * 9: jp Jumbo Packet
+ * 10: vp VLAN Packet
+ * 11-15: unused
+ * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
+ * 17: asw_RX_DV_event short receive event detected
+ * 18: asw_false_carrier_event bad carrier since last good packet
+ * 19: asw_code_err one or more nibbles signalled as errors
+ * 20: asw_CRC_err CRC error
+ * 21: asw_len_chk_err frame length field incorrect
+ * 22: asw_too_long frame length > 1518 bytes
+ * 23: asw_OK valid CRC + no code error
+ * 24: asw_multicast has a multicast address
+ * 25: asw_broadcast has a broadcast address
+ * 26: asw_dribble_nibble spurious bits after EOP
+ * 27: asw_control_frame is a control frame
+ * 28: asw_pause_frame is a pause frame
+ * 29: asw_unsupported_op unsupported OP code
+ * 30: asw_VLAN_tag VLAN tag detected
+ * 31: asw_long_evt Rx long event
+ *
+ * Word 1:
+ * 0-15: length length in bytes
+ * 16-25: bi Buffer Index
+ * 26-27: ri Ring Index
+ * 28-31: reserved
+ */
+struct pkt_stat_desc {
+ u32 word0;
+ u32 word1;
+};
+
+/* Typedefs for the RX DMA status word */
+
+/* rx status word 0 holds part of the status bits of the Rx DMA engine
+ * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
+ * which contains the Free Buffer ring 0 and 1 available offset.
+ *
+ * bit 0-9 FBR1 offset
+ * bit 10 Wrap flag for FBR1
+ * bit 16-25 FBR0 offset
+ * bit 26 Wrap flag for FBR0
+ */
+
+/* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
+ * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
+ * which contains the Packet Status Ring available offset.
+ *
+ * bit 0-15 reserved
+ * bit 16-27 PSRoffset
+ * bit 28 PSRwrap
+ * bit 29-31 unused
+ */
+
+/* struct rx_status_block is a structure representing the status of the Rx
+ * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
+ */
+struct rx_status_block {
+ u32 word0;
+ u32 word1;
+};
+
+/* Structure for look-up table holding free buffer ring pointers, addresses
+ * and state.
+ */
+struct fbr_lookup {
+ void *virt[MAX_DESC_PER_RING_RX];
+ u32 bus_high[MAX_DESC_PER_RING_RX];
+ u32 bus_low[MAX_DESC_PER_RING_RX];
+ void *ring_virtaddr;
+ dma_addr_t ring_physaddr;
+ void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+ dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
+ u32 local_full;
+ u32 num_entries;
+ dma_addr_t buffsize;
+};
+
+/* struct rx_ring is the structure representing the adaptor's local
+ * reference(s) to the rings
+ */
+struct rx_ring {
+ struct fbr_lookup *fbr[NUM_FBRS];
+ void *ps_ring_virtaddr;
+ dma_addr_t ps_ring_physaddr;
+ u32 local_psr_full;
+ u32 psr_entries;
+
+ struct rx_status_block *rx_status_block;
+ dma_addr_t rx_status_bus;
+
+ /* RECV */
+ struct list_head recv_list;
+ u32 num_ready_recv;
+
+ u32 num_rfd;
+
+ bool unfinished_receives;
+};
+
+/* TX defines */
+/* word 2 of the control bits in the Tx Descriptor ring for the ET-1310
+ *
+ * 0-15: length of packet
+ * 16-27: VLAN tag
+ * 28: VLAN CFI
+ * 29-31: VLAN priority
+ *
+ * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
+ *
+ * 0: last packet in the sequence
+ * 1: first packet in the sequence
+ * 2: interrupt the processor when this pkt sent
+ * 3: Control word - no packet data
+ * 4: Issue half-duplex backpressure : XON/XOFF
+ * 5: send pause frame
+ * 6: Tx frame has error
+ * 7: append CRC
+ * 8: MAC override
+ * 9: pad packet
+ * 10: Packet is a Huge packet
+ * 11: append VLAN tag
+ * 12: IP checksum assist
+ * 13: TCP checksum assist
+ * 14: UDP checksum assist
+ */
+#define TXDESC_FLAG_LASTPKT 0x0001
+#define TXDESC_FLAG_FIRSTPKT 0x0002
+#define TXDESC_FLAG_INTPROC 0x0004
+
+/* struct tx_desc represents each descriptor on the ring */
+struct tx_desc {
+ u32 addr_hi;
+ u32 addr_lo;
+ u32 len_vlan; /* control words how to xmit the */
+ u32 flags; /* data (detailed above) */
+};
+
+/* The status of the Tx DMA engine it sits in free memory, and is pointed to
+ * by 0x101c / 0x1020. This is a DMA10 type
+ */
+
+/* TCB (Transmit Control Block: Host Side) */
+struct tcb {
+ struct tcb *next; /* Next entry in ring */
+ u32 count; /* Used to spot stuck/lost packets */
+ u32 stale; /* Used to spot stuck/lost packets */
+ struct sk_buff *skb; /* Network skb we are tied to */
+ u32 index; /* Ring indexes */
+ u32 index_start;
+};
+
+/* Structure representing our local reference(s) to the ring */
+struct tx_ring {
+ /* TCB (Transmit Control Block) memory and lists */
+ struct tcb *tcb_ring;
+
+ /* List of TCBs that are ready to be used */
+ struct tcb *tcb_qhead;
+ struct tcb *tcb_qtail;
+
+ /* list of TCBs that are currently being sent. NOTE that access to all
+ * three of these (including used) are controlled via the
+ * TCBSendQLock. This lock should be secured prior to incementing /
+ * decrementing used, or any queue manipulation on send_head /
+ * tail
+ */
+ struct tcb *send_head;
+ struct tcb *send_tail;
+ int used;
+
+ /* The actual descriptor ring */
+ struct tx_desc *tx_desc_ring;
+ dma_addr_t tx_desc_ring_pa;
+
+ /* send_idx indicates where we last wrote to in the descriptor ring. */
+ u32 send_idx;
+
+ /* The location of the write-back status block */
+ u32 *tx_status;
+ dma_addr_t tx_status_pa;
+
+ /* Packets since the last IRQ: used for interrupt coalescing */
+ int since_irq;
+};
+
+/* Do not change these values: if changed, then change also in respective
+ * TXdma and Rxdma engines
+ */
+#define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
+#define NUM_TCB 64
+
+/* These values are all superseded by registry entries to facilitate tuning.
+ * Once the desired performance has been achieved, the optimal registry values
+ * should be re-populated to these #defines:
+ */
+#define TX_ERROR_PERIOD 1000
+
+#define LO_MARK_PERCENT_FOR_PSR 15
+#define LO_MARK_PERCENT_FOR_RX 15
+
+/* RFD (Receive Frame Descriptor) */
+struct rfd {
+ struct list_head list_node;
+ struct sk_buff *skb;
+ u32 len; /* total size of receive frame */
+ u16 bufferindex;
+ u8 ringindex;
+};
+
+/* Flow Control */
+#define FLOW_BOTH 0
+#define FLOW_TXONLY 1
+#define FLOW_RXONLY 2
+#define FLOW_NONE 3
+
+/* Struct to define some device statistics */
+struct ce_stats {
+ /* MIB II variables
+ *
+ * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
+ * MUST have 32, then we'll need another way to perform atomic
+ * operations
+ */
+ u32 multicast_pkts_rcvd;
+ u32 rcvd_pkts_dropped;
+
+ /* Tx Statistics. */
+ u32 tx_underflows;
+ u32 tx_collisions;
+ u32 tx_excessive_collisions;
+ u32 tx_first_collisions;
+ u32 tx_late_collisions;
+ u32 tx_max_pkt_errs;
+ u32 tx_deferred;
+
+ /* Rx Statistics. */
+ u32 rx_overflows;
+ u32 rx_length_errs;
+ u32 rx_align_errs;
+ u32 rx_crc_errs;
+ u32 rx_code_violations;
+ u32 rx_other_errs;
+
+ u32 interrupt_status;
+};
+
+/* The private adapter structure */
+struct et131x_adapter {
+ struct net_device *netdev;
+ struct pci_dev *pdev;
+ struct mii_bus *mii_bus;
+ struct phy_device *phydev;
+ struct napi_struct napi;
+
+ /* Flags that indicate current state of the adapter */
+ u32 flags;
+
+ /* local link state, to determine if a state change has occurred */
+ int link;
+
+ /* Configuration */
+ u8 rom_addr[ETH_ALEN];
+ u8 addr[ETH_ALEN];
+ bool has_eeprom;
+ u8 eeprom_data[2];
+
+ spinlock_t tcb_send_qlock; /* protects the tx_ring send tcb list */
+ spinlock_t tcb_ready_qlock; /* protects the tx_ring ready tcb list */
+ spinlock_t rcv_lock; /* protects the rx_ring receive list */
+
+ /* Packet Filter and look ahead size */
+ u32 packet_filter;
+
+ /* multicast list */
+ u32 multicast_addr_count;
+ u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
+
+ /* Pointer to the device's PCI register space */
+ struct address_map __iomem *regs;
+
+ /* Registry parameters */
+ u8 wanted_flow; /* Flow we want for 802.3x flow control */
+ u32 registry_jumbo_packet; /* Max supported ethernet packet size */
+
+ /* Derived from the registry: */
+ u8 flow; /* flow control validated by the far-end */
+
+ /* Minimize init-time */
+ struct timer_list error_timer;
+
+ /* variable putting the phy into coma mode when boot up with no cable
+ * plugged in after 5 seconds
+ */
+ u8 boot_coma;
+
+ /* Tx Memory Variables */
+ struct tx_ring tx_ring;
+
+ /* Rx Memory Variables */
+ struct rx_ring rx_ring;
+
+ /* Stats */
+ struct ce_stats stats;
+};
+
+static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
+{
+ u32 reg;
+ int i;
+
+ /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
+ * bits 7,1:0 both equal to 1, at least once after reset.
+ * Subsequent operations need only to check that bits 1:0 are equal
+ * to 1 prior to starting a single byte read/write
+ */
+ for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
+ /* Read registers grouped in DWORD1 */
+ if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
+ return -EIO;
+
+ /* I2C idle and Phy Queue Avail both true */
+ if ((reg & 0x3000) == 0x3000) {
+ if (status)
+ *status = reg;
+ return reg & 0xFF;
+ }
+ }
+ return -ETIMEDOUT;
+}
+
+/* eeprom_write - Write a byte to the ET1310's EEPROM
+ * @adapter: pointer to our private adapter structure
+ * @addr: the address to write
+ * @data: the value to write
+ *
+ * Returns 1 for a successful write.
+ */
+static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
+{
+ struct pci_dev *pdev = adapter->pdev;
+ int index = 0;
+ int retries;
+ int err = 0;
+ int writeok = 0;
+ u32 status;
+ u32 val = 0;
+
+ /* For an EEPROM, an I2C single byte write is defined as a START
+ * condition followed by the device address, EEPROM address, one byte
+ * of data and a STOP condition. The STOP condition will trigger the
+ * EEPROM's internally timed write cycle to the nonvolatile memory.
+ * All inputs are disabled during this write cycle and the EEPROM will
+ * not respond to any access until the internal write is complete.
+ */
+ err = eeprom_wait_ready(pdev, NULL);
+ if (err < 0)
+ return err;
+
+ /* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
+ * and bits 1:0 both =0. Bit 5 should be set according to the
+ * type of EEPROM being accessed (1=two byte addressing, 0=one
+ * byte addressing).
+ */
+ if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
+ LBCIF_CONTROL_LBCIF_ENABLE |
+ LBCIF_CONTROL_I2C_WRITE))
+ return -EIO;
+
+ /* Prepare EEPROM address for Step 3 */
+ for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
+ /* Write the address to the LBCIF Address Register */
+ if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
+ break;
+ /* Write the data to the LBCIF Data Register (the I2C write
+ * will begin).
+ */
+ if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
+ break;
+ /* Monitor bit 1:0 of the LBCIF Status Register. When bits
+ * 1:0 are both equal to 1, the I2C write has completed and the
+ * internal write cycle of the EEPROM is about to start.
+ * (bits 1:0 = 01 is a legal state while waiting from both
+ * equal to 1, but bits 1:0 = 10 is invalid and implies that
+ * something is broken).
+ */
+ err = eeprom_wait_ready(pdev, &status);
+ if (err < 0)
+ return 0;
+
+ /* Check bit 3 of the LBCIF Status Register. If equal to 1,
+ * an error has occurred.Don't break here if we are revision
+ * 1, this is so we do a blind write for load bug.
+ */
+ if ((status & LBCIF_STATUS_GENERAL_ERROR) &&
+ adapter->pdev->revision == 0)
+ break;
+
+ /* Check bit 2 of the LBCIF Status Register. If equal to 1 an
+ * ACK error has occurred on the address phase of the write.
+ * This could be due to an actual hardware failure or the
+ * EEPROM may still be in its internal write cycle from a
+ * previous write. This write operation was ignored and must be
+ *repeated later.
+ */
+ if (status & LBCIF_STATUS_ACK_ERROR) {
+ /* This could be due to an actual hardware failure
+ * or the EEPROM may still be in its internal write
+ * cycle from a previous write. This write operation
+ * was ignored and must be repeated later.
+ */
+ udelay(10);
+ continue;
+ }
+
+ writeok = 1;
+ break;
+ }
+
+ /* Set bit 6 of the LBCIF Control Register = 0.
+ */
+ udelay(10);
+
+ while (1) {
+ if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
+ LBCIF_CONTROL_LBCIF_ENABLE))
+ writeok = 0;
+
+ /* Do read until internal ACK_ERROR goes away meaning write
+ * completed
+ */
+ do {
+ pci_write_config_dword(pdev,
+ LBCIF_ADDRESS_REGISTER,
+ addr);
+ do {
+ pci_read_config_dword(pdev,
+ LBCIF_DATA_REGISTER,
+ &val);
+ } while ((val & 0x00010000) == 0);
+ } while (val & 0x00040000);
+
+ if ((val & 0xFF00) != 0xC000 || index == 10000)
+ break;
+ index++;
+ }
+ return writeok ? 0 : -EIO;
+}
+
+/* eeprom_read - Read a byte from the ET1310's EEPROM
+ * @adapter: pointer to our private adapter structure
+ * @addr: the address from which to read
+ * @pdata: a pointer to a byte in which to store the value of the read
+ * @eeprom_id: the ID of the EEPROM
+ * @addrmode: how the EEPROM is to be accessed
+ *
+ * Returns 1 for a successful read
+ */
+static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
+{
+ struct pci_dev *pdev = adapter->pdev;
+ int err;
+ u32 status;
+
+ /* A single byte read is similar to the single byte write, with the
+ * exception of the data flow:
+ */
+ err = eeprom_wait_ready(pdev, NULL);
+ if (err < 0)
+ return err;
+ /* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
+ * and bits 1:0 both =0. Bit 5 should be set according to the type
+ * of EEPROM being accessed (1=two byte addressing, 0=one byte
+ * addressing).
+ */
+ if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
+ LBCIF_CONTROL_LBCIF_ENABLE))
+ return -EIO;
+ /* Write the address to the LBCIF Address Register (I2C read will
+ * begin).
+ */
+ if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
+ return -EIO;
+ /* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
+ * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
+ * has occurred).
+ */
+ err = eeprom_wait_ready(pdev, &status);
+ if (err < 0)
+ return err;
+ /* Regardless of error status, read data byte from LBCIF Data
+ * Register.
+ */
+ *pdata = err;
+ /* Check bit 2 of the LBCIF Status Register. If = 1,
+ * then an error has occurred.
+ */
+ return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
+}
+
+static int et131x_init_eeprom(struct et131x_adapter *adapter)
+{
+ struct pci_dev *pdev = adapter->pdev;
+ u8 eestatus;
+
+ /* We first need to check the EEPROM Status code located at offset
+ * 0xB2 of config space
+ */
+ pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus);
+
+ /* THIS IS A WORKAROUND:
+ * I need to call this function twice to get my card in a
+ * LG M1 Express Dual running. I tried also a msleep before this
+ * function, because I thought there could be some time conditions
+ * but it didn't work. Call the whole function twice also work.
+ */
+ if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
+ dev_err(&pdev->dev,
+ "Could not read PCI config space for EEPROM Status\n");
+ return -EIO;
+ }
+
+ /* Determine if the error(s) we care about are present. If they are
+ * present we need to fail.
+ */
+ if (eestatus & 0x4C) {
+ int write_failed = 0;
+
+ if (pdev->revision == 0x01) {
+ int i;
+ static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
+
+ /* Re-write the first 4 bytes if we have an eeprom
+ * present and the revision id is 1, this fixes the
+ * corruption seen with 1310 B Silicon
+ */
+ for (i = 0; i < 3; i++)
+ if (eeprom_write(adapter, i, eedata[i]) < 0)
+ write_failed = 1;
+ }
+ if (pdev->revision != 0x01 || write_failed) {
+ dev_err(&pdev->dev,
+ "Fatal EEPROM Status Error - 0x%04x\n",
+ eestatus);
+
+ /* This error could mean that there was an error
+ * reading the eeprom or that the eeprom doesn't exist.
+ * We will treat each case the same and not try to
+ * gather additional information that normally would
+ * come from the eeprom, like MAC Address
+ */
+ adapter->has_eeprom = 0;
+ return -EIO;
+ }
+ }
+ adapter->has_eeprom = 1;
+
+ /* Read the EEPROM for information regarding LED behavior. Refer to
+ * ET1310_phy.c, et131x_xcvr_init(), for its use.
+ */
+ eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
+ eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
+
+ if (adapter->eeprom_data[0] != 0xcd)
+ /* Disable all optional features */
+ adapter->eeprom_data[1] = 0x00;
+
+ return 0;
+}
+
+/* et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
+ * @adapter: pointer to our adapter structure
+ */
+static void et131x_rx_dma_enable(struct et131x_adapter *adapter)
+{
+ /* Setup the receive dma configuration register for normal operation */
+ u32 csr = ET_RXDMA_CSR_FBR1_ENABLE;
+ struct rx_ring *rx_ring = &adapter->rx_ring;
+
+ if (rx_ring->fbr[1]->buffsize == 4096)
+ csr |= ET_RXDMA_CSR_FBR1_SIZE_LO;
+ else if (rx_ring->fbr[1]->buffsize == 8192)
+ csr |= ET_RXDMA_CSR_FBR1_SIZE_HI;
+ else if (rx_ring->fbr[1]->buffsize == 16384)
+ csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI;
+
+ csr |= ET_RXDMA_CSR_FBR0_ENABLE;
+ if (rx_ring->fbr[0]->buffsize == 256)
+ csr |= ET_RXDMA_CSR_FBR0_SIZE_LO;
+ else if (rx_ring->fbr[0]->buffsize == 512)
+ csr |= ET_RXDMA_CSR_FBR0_SIZE_HI;
+ else if (rx_ring->fbr[0]->buffsize == 1024)
+ csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI;
+ writel(csr, &adapter->regs->rxdma.csr);
+
+ csr = readl(&adapter->regs->rxdma.csr);
+ if (csr & ET_RXDMA_CSR_HALT_STATUS) {
+ udelay(5);
+ csr = readl(&adapter->regs->rxdma.csr);
+ if (csr & ET_RXDMA_CSR_HALT_STATUS) {
+ dev_err(&adapter->pdev->dev,
+ "RX Dma failed to exit halt state. CSR 0x%08x\n",
+ csr);
+ }
+ }
+}
+
+/* et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
+ * @adapter: pointer to our adapter structure
+ */
+static void et131x_rx_dma_disable(struct et131x_adapter *adapter)
+{
+ u32 csr;
+ /* Setup the receive dma configuration register */
+ writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE,
+ &adapter->regs->rxdma.csr);
+ csr = readl(&adapter->regs->rxdma.csr);
+ if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) {
+ udelay(5);
+ csr = readl(&adapter->regs->rxdma.csr);
+ if (!(csr & ET_RXDMA_CSR_HALT_STATUS))
+ dev_err(&adapter->pdev->dev,
+ "RX Dma failed to enter halt state. CSR 0x%08x\n",
+ csr);
+ }
+}
+
+/* et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
+ * @adapter: pointer to our adapter structure
+ *
+ * Mainly used after a return to the D0 (full-power) state from a lower state.
+ */
+static void et131x_tx_dma_enable(struct et131x_adapter *adapter)
+{
+ /* Setup the transmit dma configuration register for normal
+ * operation
+ */
+ writel(ET_TXDMA_SNGL_EPKT | (PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
+ &adapter->regs->txdma.csr);
+}
+
+static inline void add_10bit(u32 *v, int n)
+{
+ *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
+}
+
+static inline void add_12bit(u32 *v, int n)
+{
+ *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
+}
+
+/* et1310_config_mac_regs1 - Initialize the first part of MAC regs
+ * @adapter: pointer to our adapter structure
+ */
+static void et1310_config_mac_regs1(struct et131x_adapter *adapter)
+{
+ struct mac_regs __iomem *macregs = &adapter->regs->mac;
+ u32 station1;
+ u32 station2;
+ u32 ipg;
+
+ /* First we need to reset everything. Write to MAC configuration
+ * register 1 to perform reset.
+ */
+ writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
+ ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
+ ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC,
+ ¯egs->cfg1);
+
+ /* Next lets configure the MAC Inter-packet gap register */
+ ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
+ ipg |= 0x50 << 8; /* ifg enforce 0x50 */
+ writel(ipg, ¯egs->ipg);
+
+ /* Next lets configure the MAC Half Duplex register */
+ /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
+ writel(0x00A1F037, ¯egs->hfdp);
+
+ /* Next lets configure the MAC Interface Control register */
+ writel(0, ¯egs->if_ctrl);
+
+ /* Let's move on to setting up the mii management configuration */
+ writel(ET_MAC_MIIMGMT_CLK_RST, ¯egs->mii_mgmt_cfg);
+
+ /* Next lets configure the MAC Station Address register. These
+ * values are read from the EEPROM during initialization and stored
+ * in the adapter structure. We write what is stored in the adapter
+ * structure to the MAC Station Address registers high and low. This
+ * station address is used for generating and checking pause control
+ * packets.
+ */
+ station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
+ (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
+ station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
+ (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
+ (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
+ adapter->addr[2];
+ writel(station1, ¯egs->station_addr_1);
+ writel(station2, ¯egs->station_addr_2);
+
+ /* Max ethernet packet in bytes that will be passed by the mac without
+ * being truncated. Allow the MAC to pass 4 more than our max packet
+ * size. This is 4 for the Ethernet CRC.
+ *
+ * Packets larger than (registry_jumbo_packet) that do not contain a
+ * VLAN ID will be dropped by the Rx function.
+ */
+ writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len);
+
+ /* clear out MAC config reset */
+ writel(0, ¯egs->cfg1);
+}
+
+/* et1310_config_mac_regs2 - Initialize the second part of MAC regs
+ * @adapter: pointer to our adapter structure
+ */
+static void et1310_config_mac_regs2(struct et131x_adapter *adapter)
+{
+ int32_t delay = 0;
+ struct mac_regs __iomem *mac = &adapter->regs->mac;
+ struct phy_device *phydev = adapter->phydev;
+ u32 cfg1;
+ u32 cfg2;
+ u32 ifctrl;
+ u32 ctl;
+
+ ctl = readl(&adapter->regs->txmac.ctl);
+ cfg1 = readl(&mac->cfg1);
+ cfg2 = readl(&mac->cfg2);
+ ifctrl = readl(&mac->if_ctrl);
+
+ /* Set up the if mode bits */
+ cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK;
+ if (phydev->speed == SPEED_1000) {
+ cfg2 |= ET_MAC_CFG2_IFMODE_1000;
+ /* Phy mode bit */
+ ifctrl &= ~ET_MAC_IFCTRL_PHYMODE;
+ } else {
+ cfg2 |= ET_MAC_CFG2_IFMODE_100;
+ ifctrl |= ET_MAC_IFCTRL_PHYMODE;
+ }
+
+ /* We need to enable Rx/Tx */
+ cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE |
+ ET_MAC_CFG1_TX_FLOW;
+ /* Initialize loop back to off */
+ cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW);
+ if (adapter->flow == FLOW_RXONLY || adapter->flow == FLOW_BOTH)
+ cfg1 |= ET_MAC_CFG1_RX_FLOW;
+ writel(cfg1, &mac->cfg1);
+
+ /* Now we need to initialize the MAC Configuration 2 register */
+ /* preamble 7, check length, huge frame off, pad crc, crc enable
+ * full duplex off
+ */
+ cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT;
+ cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK;
+ cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC;
+ cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE;
+ cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME;
+ cfg2 &= ~ET_MAC_CFG2_IFMODE_FULL_DPLX;
+
+ /* Turn on duplex if needed */
+ if (phydev->duplex == DUPLEX_FULL)
+ cfg2 |= ET_MAC_CFG2_IFMODE_FULL_DPLX;
+
+ ifctrl &= ~ET_MAC_IFCTRL_GHDMODE;
+ if (phydev->duplex == DUPLEX_HALF)
+ ifctrl |= ET_MAC_IFCTRL_GHDMODE;
+
+ writel(ifctrl, &mac->if_ctrl);
+ writel(cfg2, &mac->cfg2);
+
+ do {
+ udelay(10);
+ delay++;
+ cfg1 = readl(&mac->cfg1);
+ } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100);
+
+ if (delay == 100) {
+ dev_warn(&adapter->pdev->dev,
+ "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
+ cfg1);
+ }
+
+ /* Enable txmac */
+ ctl |= ET_TX_CTRL_TXMAC_ENABLE | ET_TX_CTRL_FC_DISABLE;
+ writel(ctl, &adapter->regs->txmac.ctl);
+
+ /* Ready to start the RXDMA/TXDMA engine */
+ if (adapter->flags & FMP_ADAPTER_LOWER_POWER) {
+ et131x_rx_dma_enable(adapter);
+ et131x_tx_dma_enable(adapter);
+ }
+}
+
+/* et1310_in_phy_coma - check if the device is in phy coma
+ * @adapter: pointer to our adapter structure
+ *
+ * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
+ */
+static int et1310_in_phy_coma(struct et131x_adapter *adapter)
+{
+ u32 pmcsr = readl(&adapter->regs->global.pm_csr);
+
+ return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
+}
+
+static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
+{
+ struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
+ u32 hash1 = 0;
+ u32 hash2 = 0;
+ u32 hash3 = 0;
+ u32 hash4 = 0;
+ u32 pm_csr;
+
+ /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
+ * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
+ * specified) then we should pass NO multi-cast addresses to the
+ * driver.
+ */
+ if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
+ int i;
+
+ /* Loop through our multicast array and set up the device */
+ for (i = 0; i < adapter->multicast_addr_count; i++) {
+ u32 result;
+
+ result = ether_crc(6, adapter->multicast_list[i]);
+
+ result = (result & 0x3F800000) >> 23;
+
+ if (result < 32) {
+ hash1 |= (1 << result);
+ } else if ((31 < result) && (result < 64)) {
+ result -= 32;
+ hash2 |= (1 << result);
+ } else if ((63 < result) && (result < 96)) {
+ result -= 64;
+ hash3 |= (1 << result);
+ } else {
+ result -= 96;
+ hash4 |= (1 << result);
+ }
+ }
+ }
+
+ /* Write out the new hash to the device */
+ pm_csr = readl(&adapter->regs->global.pm_csr);
+ if (!et1310_in_phy_coma(adapter)) {
+ writel(hash1, &rxmac->multi_hash1);
+ writel(hash2, &rxmac->multi_hash2);
+ writel(hash3, &rxmac->multi_hash3);
+ writel(hash4, &rxmac->multi_hash4);
+ }
+}
+
+static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
+{
+ struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
+ u32 uni_pf1;
+ u32 uni_pf2;
+ u32 uni_pf3;
+ u32 pm_csr;
+
+ /* Set up unicast packet filter reg 3 to be the first two octets of
+ * the MAC address for both address
+ *
+ * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
+ * MAC address for second address
+ *
+ * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
+ * MAC address for first address
+ */
+ uni_pf3 = (adapter->addr[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT) |
+ (adapter->addr[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT) |
+ (adapter->addr[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT) |
+ adapter->addr[1];
+
+ uni_pf2 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT) |
+ (adapter->addr[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT) |
+ (adapter->addr[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT) |
+ adapter->addr[5];
+
+ uni_pf1 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT) |
+ (adapter->addr[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT) |
+ (adapter->addr[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT) |
+ adapter->addr[5];
+
+ pm_csr = readl(&adapter->regs->global.pm_csr);
+ if (!et1310_in_phy_coma(adapter)) {
+ writel(uni_pf1, &rxmac->uni_pf_addr1);
+ writel(uni_pf2, &rxmac->uni_pf_addr2);
+ writel(uni_pf3, &rxmac->uni_pf_addr3);
+ }
+}
+
+static void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
+{
+ struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
+ struct phy_device *phydev = adapter->phydev;
+ u32 sa_lo;
+ u32 sa_hi = 0;
+ u32 pf_ctrl = 0;
+ u32 __iomem *wolw;
+
+ /* Disable the MAC while it is being configured (also disable WOL) */
+ writel(0x8, &rxmac->ctrl);
+
+ /* Initialize WOL to disabled. */
+ writel(0, &rxmac->crc0);
+ writel(0, &rxmac->crc12);
+ writel(0, &rxmac->crc34);
+
+ /* We need to set the WOL mask0 - mask4 next. We initialize it to
+ * its default Values of 0x00000000 because there are not WOL masks
+ * as of this time.
+ */
+ for (wolw = &rxmac->mask0_word0; wolw <= &rxmac->mask4_word3; wolw++)
+ writel(0, wolw);
+
+ /* Lets setup the WOL Source Address */
+ sa_lo = (adapter->addr[2] << ET_RX_WOL_LO_SA3_SHIFT) |
+ (adapter->addr[3] << ET_RX_WOL_LO_SA4_SHIFT) |
+ (adapter->addr[4] << ET_RX_WOL_LO_SA5_SHIFT) |
+ adapter->addr[5];
+ writel(sa_lo, &rxmac->sa_lo);
+
+ sa_hi = (u32)(adapter->addr[0] << ET_RX_WOL_HI_SA1_SHIFT) |
+ adapter->addr[1];
+ writel(sa_hi, &rxmac->sa_hi);
+
+ /* Disable all Packet Filtering */
+ writel(0, &rxmac->pf_ctrl);
+
+ /* Let's initialize the Unicast Packet filtering address */
+ if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
+ et1310_setup_device_for_unicast(adapter);
+ pf_ctrl |= ET_RX_PFCTRL_UNICST_FILTER_ENABLE;
+ } else {
+ writel(0, &rxmac->uni_pf_addr1);
+ writel(0, &rxmac->uni_pf_addr2);
+ writel(0, &rxmac->uni_pf_addr3);
+ }
+
+ /* Let's initialize the Multicast hash */
+ if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
+ pf_ctrl |= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE;
+ et1310_setup_device_for_multicast(adapter);
+ }
+
+ /* Runt packet filtering. Didn't work in version A silicon. */
+ pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT;
+ pf_ctrl |= ET_RX_PFCTRL_FRAG_FILTER_ENABLE;
+
+ if (adapter->registry_jumbo_packet > 8192)
+ /* In order to transmit jumbo packets greater than 8k, the
+ * FIFO between RxMAC and RxDMA needs to be reduced in size
+ * to (16k - Jumbo packet size). In order to implement this,
+ * we must use "cut through" mode in the RxMAC, which chops
+ * packets down into segments which are (max_size * 16). In
+ * this case we selected 256 bytes, since this is the size of
+ * the PCI-Express TLP's that the 1310 uses.
+ *
+ * seg_en on, fc_en off, size 0x10
+ */
+ writel(0x41, &rxmac->mcif_ctrl_max_seg);
+ else
+ writel(0, &rxmac->mcif_ctrl_max_seg);
+
+ /* Initialize the MCIF water marks */
+ writel(0, &rxmac->mcif_water_mark);
+
+ /* Initialize the MIF control */
+ writel(0, &rxmac->mif_ctrl);
+
+ /* Initialize the Space Available Register */
+ writel(0, &rxmac->space_avail);
+
+ /* Initialize the the mif_ctrl register
+ * bit 3: Receive code error. One or more nibbles were signaled as
+ * errors during the reception of the packet. Clear this
+ * bit in Gigabit, set it in 100Mbit. This was derived
+ * experimentally at UNH.
+ * bit 4: Receive CRC error. The packet's CRC did not match the
+ * internally generated CRC.
+ * bit 5: Receive length check error. Indicates that frame length
+ * field value in the packet does not match the actual data
+ * byte length and is not a type field.
+ * bit 16: Receive frame truncated.
+ * bit 17: Drop packet enable
+ */
+ if (phydev && phydev->speed == SPEED_100)
+ writel(0x30038, &rxmac->mif_ctrl);
+ else
+ writel(0x30030, &rxmac->mif_ctrl);
+
+ /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
+ * filter is always enabled since it is where the runt packets are
+ * supposed to be dropped. For version A silicon, runt packet
+ * dropping doesn't work, so it is disabled in the pf_ctrl register,
+ * but we still leave the packet filter on.
+ */
+ writel(pf_ctrl, &rxmac->pf_ctrl);
+ writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl);
+}
+
+static void et1310_config_txmac_regs(struct et131x_adapter *adapter)
+{
+ struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
+
+ /* We need to update the Control Frame Parameters
+ * cfpt - control frame pause timer set to 64 (0x40)
+ * cfep - control frame extended pause timer set to 0x0
+ */
+ if (adapter->flow == FLOW_NONE)
+ writel(0, &txmac->cf_param);
+ else
+ writel(0x40, &txmac->cf_param);
+}
+
+static void et1310_config_macstat_regs(struct et131x_adapter *adapter)
+{
+ struct macstat_regs __iomem *macstat = &adapter->regs->macstat;
+ u32 __iomem *reg;
+
+ /* initialize all the macstat registers to zero on the device */
+ for (reg = &macstat->txrx_0_64_byte_frames;
+ reg <= &macstat->carry_reg2; reg++)
+ writel(0, reg);
+
+ /* Unmask any counters that we want to track the overflow of.
+ * Initially this will be all counters. It may become clear later
+ * that we do not need to track all counters.
+ */
+ writel(0xFFFFBE32, &macstat->carry_reg1_mask);
+ writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
+}
+
+/* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
+ * @adapter: pointer to our private adapter structure
+ * @addr: the address of the transceiver
+ * @reg: the register to read
+ * @value: pointer to a 16-bit value in which the value will be stored
+ */
+static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
+ u8 reg, u16 *value)
+{
+ struct mac_regs __iomem *mac = &adapter->regs->mac;
+ int status = 0;
+ u32 delay = 0;
+ u32 mii_addr;
+ u32 mii_cmd;
+ u32 mii_indicator;
+
+ /* Save a local copy of the registers we are dealing with so we can
+ * set them back
+ */
+ mii_addr = readl(&mac->mii_mgmt_addr);
+ mii_cmd = readl(&mac->mii_mgmt_cmd);
+
+ /* Stop the current operation */
+ writel(0, &mac->mii_mgmt_cmd);
+
+ /* Set up the register we need to read from on the correct PHY */
+ writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
+
+ writel(0x1, &mac->mii_mgmt_cmd);
+
+ do {
+ udelay(50);
+ delay++;
+ mii_indicator = readl(&mac->mii_mgmt_indicator);
+ } while ((mii_indicator & ET_MAC_MGMT_WAIT) && delay < 50);
+
+ /* If we hit the max delay, we could not read the register */
+ if (delay == 50) {
+ dev_warn(&adapter->pdev->dev,
+ "reg 0x%08x could not be read\n", reg);
+ dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
+ mii_indicator);
+
+ status = -EIO;
+ goto out;
+ }
+
+ /* If we hit here we were able to read the register and we need to
+ * return the value to the caller
+ */
+ *value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK;
+
+out:
+ /* Stop the read operation */
+ writel(0, &mac->mii_mgmt_cmd);
+
+ /* set the registers we touched back to the state at which we entered
+ * this function
+ */
+ writel(mii_addr, &mac->mii_mgmt_addr);
+ writel(mii_cmd, &mac->mii_mgmt_cmd);
+
+ return status;
+}
+
+static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
+{
+ struct phy_device *phydev = adapter->phydev;
+
+ if (!phydev)
+ return -EIO;
+
+ return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
+}
+
+/* et131x_mii_write - Write to a PHY reg through the MII interface of the MAC
+ * @adapter: pointer to our private adapter structure
+ * @reg: the register to read
+ * @value: 16-bit value to write
+ */
+static int et131x_mii_write(struct et131x_adapter *adapter, u8 addr, u8 reg,
+ u16 value)
+{
+ struct mac_regs __iomem *mac = &adapter->regs->mac;
+ int status = 0;
+ u32 delay = 0;
+ u32 mii_addr;
+ u32 mii_cmd;
+ u32 mii_indicator;
+
+ /* Save a local copy of the registers we are dealing with so we can
+ * set them back
+ */
+ mii_addr = readl(&mac->mii_mgmt_addr);
+ mii_cmd = readl(&mac->mii_mgmt_cmd);
+
+ /* Stop the current operation */
+ writel(0, &mac->mii_mgmt_cmd);
+
+ /* Set up the register we need to write to on the correct PHY */
+ writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
+
+ /* Add the value to write to the registers to the mac */
+ writel(value, &mac->mii_mgmt_ctrl);
+
+ do {
+ udelay(50);
+ delay++;
+ mii_indicator = readl(&mac->mii_mgmt_indicator);
+ } while ((mii_indicator & ET_MAC_MGMT_BUSY) && delay < 100);
+
+ /* If we hit the max delay, we could not write the register */
+ if (delay == 100) {
+ u16 tmp;
+
+ dev_warn(&adapter->pdev->dev,
+ "reg 0x%08x could not be written", reg);
+ dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
+ mii_indicator);
+ dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
+ readl(&mac->mii_mgmt_cmd));
+
+ et131x_mii_read(adapter, reg, &tmp);
+
+ status = -EIO;
+ }
+ /* Stop the write operation */
+ writel(0, &mac->mii_mgmt_cmd);
+
+ /* set the registers we touched back to the state at which we entered
+ * this function
+ */
+ writel(mii_addr, &mac->mii_mgmt_addr);
+ writel(mii_cmd, &mac->mii_mgmt_cmd);
+
+ return status;
+}
+
+static void et1310_phy_read_mii_bit(struct et131x_adapter *adapter,
+ u16 regnum,
+ u16 bitnum,
+ u8 *value)
+{
+ u16 reg;
+ u16 mask = 1 << bitnum;
+
+ /* Read the requested register */
+ et131x_mii_read(adapter, regnum, ®);
+
+ *value = (reg & mask) >> bitnum;
+}
+
+static void et1310_config_flow_control(struct et131x_adapter *adapter)
+{
+ struct phy_device *phydev = adapter->phydev;
+
+ if (phydev->duplex == DUPLEX_HALF) {
+ adapter->flow = FLOW_NONE;
+ } else {
+ char remote_pause, remote_async_pause;
+
+ et1310_phy_read_mii_bit(adapter, 5, 10, &remote_pause);
+ et1310_phy_read_mii_bit(adapter, 5, 11, &remote_async_pause);
+
+ if (remote_pause && remote_async_pause) {
+ adapter->flow = adapter->wanted_flow;
+ } else if (remote_pause && !remote_async_pause) {
+ if (adapter->wanted_flow == FLOW_BOTH)
+ adapter->flow = FLOW_BOTH;
+ else
+ adapter->flow = FLOW_NONE;
+ } else if (!remote_pause && !remote_async_pause) {
+ adapter->flow = FLOW_NONE;
+ } else {
+ if (adapter->wanted_flow == FLOW_BOTH)
+ adapter->flow = FLOW_RXONLY;
+ else
+ adapter->flow = FLOW_NONE;
+ }
+ }
+}
+
+/* et1310_update_macstat_host_counters - Update local copy of the statistics */
+static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
+{
+ struct ce_stats *stats = &adapter->stats;
+ struct macstat_regs __iomem *macstat =
+ &adapter->regs->macstat;
+
+ stats->tx_collisions += readl(&macstat->tx_total_collisions);
+ stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
+ stats->tx_deferred += readl(&macstat->tx_deferred);
+ stats->tx_excessive_collisions +=
+ readl(&macstat->tx_multiple_collisions);
+ stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
+ stats->tx_underflows += readl(&macstat->tx_undersize_frames);
+ stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
+
+ stats->rx_align_errs += readl(&macstat->rx_align_errs);
+ stats->rx_crc_errs += readl(&macstat->rx_code_errs);
+ stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
+ stats->rx_overflows += readl(&macstat->rx_oversize_packets);
+ stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
+ stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
+ stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
+}
+
+/* et1310_handle_macstat_interrupt
+ *
+ * One of the MACSTAT counters has wrapped. Update the local copy of
+ * the statistics held in the adapter structure, checking the "wrap"
+ * bit for each counter.
+ */
+static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
+{
+ u32 carry_reg1;
+ u32 carry_reg2;
+
+ /* Read the interrupt bits from the register(s). These are Clear On
+ * Write.
+ */
+ carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
+ carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
+
+ writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
+ writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
+
+ /* We need to do update the host copy of all the MAC_STAT counters.
+ * For each counter, check it's overflow bit. If the overflow bit is
+ * set, then increment the host version of the count by one complete
+ * revolution of the counter. This routine is called when the counter
+ * block indicates that one of the counters has wrapped.
+ */
+ if (carry_reg1 & (1 << 14))
+ adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
+ if (carry_reg1 & (1 << 8))
+ adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
+ if (carry_reg1 & (1 << 7))
+ adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
+ if (carry_reg1 & (1 << 2))
+ adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
+ if (carry_reg1 & (1 << 6))
+ adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
+ if (carry_reg1 & (1 << 3))
+ adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
+ if (carry_reg1 & (1 << 0))
+ adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
+ if (carry_reg2 & (1 << 16))
+ adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
+ if (carry_reg2 & (1 << 15))
+ adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
+ if (carry_reg2 & (1 << 6))
+ adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
+ if (carry_reg2 & (1 << 8))
+ adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
+ if (carry_reg2 & (1 << 5))
+ adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
+ if (carry_reg2 & (1 << 4))
+ adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
+ if (carry_reg2 & (1 << 2))
+ adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
+}
+
+static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
+{
+ struct net_device *netdev = bus->priv;
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+ u16 value;
+ int ret;
+
+ ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
+
+ if (ret < 0)
+ return ret;
+
+ return value;
+}
+
+static int et131x_mdio_write(struct mii_bus *bus, int phy_addr,
+ int reg, u16 value)
+{
+ struct net_device *netdev = bus->priv;
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ return et131x_mii_write(adapter, phy_addr, reg, value);
+}
+
+/* et1310_phy_power_switch - PHY power control
+ * @adapter: device to control
+ * @down: true for off/false for back on
+ *
+ * one hundred, ten, one thousand megs
+ * How would you like to have your LAN accessed
+ * Can't you see that this code processed
+ * Phy power, phy power..
+ */
+static void et1310_phy_power_switch(struct et131x_adapter *adapter, bool down)
+{
+ u16 data;
+ struct phy_device *phydev = adapter->phydev;
+
+ et131x_mii_read(adapter, MII_BMCR, &data);
+ data &= ~BMCR_PDOWN;
+ if (down)
+ data |= BMCR_PDOWN;
+ et131x_mii_write(adapter, phydev->addr, MII_BMCR, data);
+}
+
+/* et131x_xcvr_init - Init the phy if we are setting it into force mode */
+static void et131x_xcvr_init(struct et131x_adapter *adapter)
+{
+ u16 lcr2;
+ struct phy_device *phydev = adapter->phydev;
+
+ /* Set the LED behavior such that LED 1 indicates speed (off =
+ * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
+ * link and activity (on for link, blink off for activity).
+ *
+ * NOTE: Some customizations have been added here for specific
+ * vendors; The LED behavior is now determined by vendor data in the
+ * EEPROM. However, the above description is the default.
+ */
+ if ((adapter->eeprom_data[1] & 0x4) == 0) {
+ et131x_mii_read(adapter, PHY_LED_2, &lcr2);
+
+ lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T);
+ lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
+
+ if ((adapter->eeprom_data[1] & 0x8) == 0)
+ lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
+ else
+ lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
+
+ et131x_mii_write(adapter, phydev->addr, PHY_LED_2, lcr2);
+ }
+}
+
+/* et131x_configure_global_regs - configure JAGCore global regs
+ *
+ * Used to configure the global registers on the JAGCore
+ */
+static void et131x_configure_global_regs(struct et131x_adapter *adapter)
+{
+ struct global_regs __iomem *regs = &adapter->regs->global;
+
+ writel(0, ®s->rxq_start_addr);
+ writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
+
+ if (adapter->registry_jumbo_packet < 2048) {
+ /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
+ * block of RAM that the driver can split between Tx
+ * and Rx as it desires. Our default is to split it
+ * 50/50:
+ */
+ writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
+ writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
+ } else if (adapter->registry_jumbo_packet < 8192) {
+ /* For jumbo packets > 2k but < 8k, split 50-50. */
+ writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
+ writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
+ } else {
+ /* 9216 is the only packet size greater than 8k that
+ * is available. The Tx buffer has to be big enough
+ * for one whole packet on the Tx side. We'll make
+ * the Tx 9408, and give the rest to Rx
+ */
+ writel(0x01b3, ®s->rxq_end_addr);
+ writel(0x01b4, ®s->txq_start_addr);
+ }
+
+ /* Initialize the loopback register. Disable all loopbacks. */
+ writel(0, ®s->loopback);
+
+ /* MSI Register */
+ writel(0, ®s->msi_config);
+
+ /* By default, disable the watchdog timer. It will be enabled when
+ * a packet is queued.
+ */
+ writel(0, ®s->watchdog_timer);
+}
+
+/* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */
+static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
+{
+ struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
+ struct rx_ring *rx_local = &adapter->rx_ring;
+ struct fbr_desc *fbr_entry;
+ u32 entry;
+ u32 psr_num_des;
+ unsigned long flags;
+ u8 id;
+
+ /* Halt RXDMA to perform the reconfigure. */
+ et131x_rx_dma_disable(adapter);
+
+ /* Load the completion writeback physical address */
+ writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
+ writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
+
+ memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
+
+ /* Set the address and parameters of the packet status ring into the
+ * 1310's registers
+ */
+ writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
+ writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
+ writel(rx_local->psr_entries - 1, &rx_dma->psr_num_des);
+ writel(0, &rx_dma->psr_full_offset);
+
+ psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK;
+ writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
+ &rx_dma->psr_min_des);
+
+ spin_lock_irqsave(&adapter->rcv_lock, flags);
+
+ /* These local variables track the PSR in the adapter structure */
+ rx_local->local_psr_full = 0;
+
+ for (id = 0; id < NUM_FBRS; id++) {
+ u32 __iomem *num_des;
+ u32 __iomem *full_offset;
+ u32 __iomem *min_des;
+ u32 __iomem *base_hi;
+ u32 __iomem *base_lo;
+ struct fbr_lookup *fbr = rx_local->fbr[id];
+
+ if (id == 0) {
+ num_des = &rx_dma->fbr0_num_des;
+ full_offset = &rx_dma->fbr0_full_offset;
+ min_des = &rx_dma->fbr0_min_des;
+ base_hi = &rx_dma->fbr0_base_hi;
+ base_lo = &rx_dma->fbr0_base_lo;
+ } else {
+ num_des = &rx_dma->fbr1_num_des;
+ full_offset = &rx_dma->fbr1_full_offset;
+ min_des = &rx_dma->fbr1_min_des;
+ base_hi = &rx_dma->fbr1_base_hi;
+ base_lo = &rx_dma->fbr1_base_lo;
+ }
+
+ /* Now's the best time to initialize FBR contents */
+ fbr_entry = fbr->ring_virtaddr;
+ for (entry = 0; entry < fbr->num_entries; entry++) {
+ fbr_entry->addr_hi = fbr->bus_high[entry];
+ fbr_entry->addr_lo = fbr->bus_low[entry];
+ fbr_entry->word2 = entry;
+ fbr_entry++;
+ }
+
+ /* Set the address and parameters of Free buffer ring 1 and 0
+ * into the 1310's registers
+ */
+ writel(upper_32_bits(fbr->ring_physaddr), base_hi);
+ writel(lower_32_bits(fbr->ring_physaddr), base_lo);
+ writel(fbr->num_entries - 1, num_des);
+ writel(ET_DMA10_WRAP, full_offset);
+
+ /* This variable tracks the free buffer ring 1 full position,
+ * so it has to match the above.
+ */
+ fbr->local_full = ET_DMA10_WRAP;
+ writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
+ min_des);
+ }
+
+ /* Program the number of packets we will receive before generating an
+ * interrupt.
+ * For version B silicon, this value gets updated once autoneg is
+ *complete.
+ */
+ writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
+
+ /* The "time_done" is not working correctly to coalesce interrupts
+ * after a given time period, but rather is giving us an interrupt
+ * regardless of whether we have received packets.
+ * This value gets updated once autoneg is complete.
+ */
+ writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
+
+ spin_unlock_irqrestore(&adapter->rcv_lock, flags);
+}
+
+/* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
+ *
+ * Configure the transmit engine with the ring buffers we have created
+ * and prepare it for use.
+ */
+static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
+{
+ struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+
+ /* Load the hardware with the start of the transmit descriptor ring. */
+ writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi);
+ writel(lower_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_lo);
+
+ /* Initialise the transmit DMA engine */
+ writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
+
+ /* Load the completion writeback physical address */
+ writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi);
+ writel(lower_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_lo);
+
+ *tx_ring->tx_status = 0;
+
+ writel(0, &txdma->service_request);
+ tx_ring->send_idx = 0;
+}
+
+/* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */
+static void et131x_adapter_setup(struct et131x_adapter *adapter)
+{
+ /* Configure the JAGCore */
+ et131x_configure_global_regs(adapter);
+
+ et1310_config_mac_regs1(adapter);
+
+ /* Configure the MMC registers */
+ /* All we need to do is initialize the Memory Control Register */
+ writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
+
+ et1310_config_rxmac_regs(adapter);
+ et1310_config_txmac_regs(adapter);
+
+ et131x_config_rx_dma_regs(adapter);
+ et131x_config_tx_dma_regs(adapter);
+
+ et1310_config_macstat_regs(adapter);
+
+ et1310_phy_power_switch(adapter, 0);
+ et131x_xcvr_init(adapter);
+}
+
+/* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */
+static void et131x_soft_reset(struct et131x_adapter *adapter)
+{
+ u32 reg;
+
+ /* Disable MAC Core */
+ reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
+ ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
+ ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
+ writel(reg, &adapter->regs->mac.cfg1);
+
+ reg = ET_RESET_ALL;
+ writel(reg, &adapter->regs->global.sw_reset);
+
+ reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
+ ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
+ writel(reg, &adapter->regs->mac.cfg1);
+ writel(0, &adapter->regs->mac.cfg1);
+}
+
+/* et131x_enable_interrupts - enable interrupt
+ *
+ * Enable the appropriate interrupts on the ET131x according to our
+ * configuration
+ */
+static void et131x_enable_interrupts(struct et131x_adapter *adapter)
+{
+ u32 mask;
+
+ /* Enable all global interrupts */
+ if (adapter->flow == FLOW_TXONLY || adapter->flow == FLOW_BOTH)
+ mask = INT_MASK_ENABLE;
+ else
+ mask = INT_MASK_ENABLE_NO_FLOW;
+
+ writel(mask, &adapter->regs->global.int_mask);
+}
+
+/* et131x_disable_interrupts - interrupt disable
+ *
+ * Block all interrupts from the et131x device at the device itself
+ */
+static void et131x_disable_interrupts(struct et131x_adapter *adapter)
+{
+ /* Disable all global interrupts */
+ writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
+}
+
+/* et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 */
+static void et131x_tx_dma_disable(struct et131x_adapter *adapter)
+{
+ /* Setup the transmit dma configuration register */
+ writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,
+ &adapter->regs->txdma.csr);
+}
+
+/* et131x_enable_txrx - Enable tx/rx queues */
+static void et131x_enable_txrx(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ /* Enable the Tx and Rx DMA engines (if not already enabled) */
+ et131x_rx_dma_enable(adapter);
+ et131x_tx_dma_enable(adapter);
+
+ /* Enable device interrupts */
+ if (adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE)
+ et131x_enable_interrupts(adapter);
+
+ /* We're ready to move some data, so start the queue */
+ netif_start_queue(netdev);
+}
+
+/* et131x_disable_txrx - Disable tx/rx queues */
+static void et131x_disable_txrx(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ /* First thing is to stop the queue */
+ netif_stop_queue(netdev);
+
+ /* Stop the Tx and Rx DMA engines */
+ et131x_rx_dma_disable(adapter);
+ et131x_tx_dma_disable(adapter);
+
+ /* Disable device interrupts */
+ et131x_disable_interrupts(adapter);
+}
+
+/* et131x_init_send - Initialize send data structures */
+static void et131x_init_send(struct et131x_adapter *adapter)
+{
+ u32 ct;
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+ struct tcb *tcb = tx_ring->tcb_ring;
+
+ tx_ring->tcb_qhead = tcb;
+
+ memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
+
+ /* Go through and set up each TCB */
+ for (ct = 0; ct++ < NUM_TCB; tcb++)
+ /* Set the link pointer in HW TCB to the next TCB in the
+ * chain
+ */
+ tcb->next = tcb + 1;
+
+ /* Set the tail pointer */
+ tcb--;
+ tx_ring->tcb_qtail = tcb;
+ tcb->next = NULL;
+ /* Curr send queue should now be empty */
+ tx_ring->send_head = NULL;
+ tx_ring->send_tail = NULL;
+}
+
+/* et1310_enable_phy_coma - called when network cable is unplugged
+ *
+ * driver receive an phy status change interrupt while in D0 and check that
+ * phy_status is down.
+ *
+ * -- gate off JAGCore;
+ * -- set gigE PHY in Coma mode
+ * -- wake on phy_interrupt; Perform software reset JAGCore,
+ * re-initialize jagcore and gigE PHY
+ *
+ * Add D0-ASPM-PhyLinkDown Support:
+ * -- while in D0, when there is a phy_interrupt indicating phy link
+ * down status, call the MPSetPhyComa routine to enter this active
+ * state power saving mode
+ * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
+ * indicating linkup status, call the MPDisablePhyComa routine to
+ * restore JAGCore and gigE PHY
+ */
+static void et1310_enable_phy_coma(struct et131x_adapter *adapter)
+{
+ u32 pmcsr = readl(&adapter->regs->global.pm_csr);
+
+ /* Save the GbE PHY speed and duplex modes. Need to restore this
+ * when cable is plugged back in
+ */
+
+ /* Stop sending packets. */
+ adapter->flags |= FMP_ADAPTER_LOWER_POWER;
+
+ /* Wait for outstanding Receive packets */
+ et131x_disable_txrx(adapter->netdev);
+
+ /* Gate off JAGCore 3 clock domains */
+ pmcsr &= ~ET_PMCSR_INIT;
+ writel(pmcsr, &adapter->regs->global.pm_csr);
+
+ /* Program gigE PHY in to Coma mode */
+ pmcsr |= ET_PM_PHY_SW_COMA;
+ writel(pmcsr, &adapter->regs->global.pm_csr);
+}
+
+/* et1310_disable_phy_coma - Disable the Phy Coma Mode */
+static void et1310_disable_phy_coma(struct et131x_adapter *adapter)
+{
+ u32 pmcsr;
+
+ pmcsr = readl(&adapter->regs->global.pm_csr);
+
+ /* Disable phy_sw_coma register and re-enable JAGCore clocks */
+ pmcsr |= ET_PMCSR_INIT;
+ pmcsr &= ~ET_PM_PHY_SW_COMA;
+ writel(pmcsr, &adapter->regs->global.pm_csr);
+
+ /* Restore the GbE PHY speed and duplex modes;
+ * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
+ */
+
+ /* Re-initialize the send structures */
+ et131x_init_send(adapter);
+
+ /* Bring the device back to the state it was during init prior to
+ * autonegotiation being complete. This way, when we get the auto-neg
+ * complete interrupt, we can complete init by calling ConfigMacREGS2.
+ */
+ et131x_soft_reset(adapter);
+
+ /* setup et1310 as per the documentation ?? */
+ et131x_adapter_setup(adapter);
+
+ /* Allow Tx to restart */
+ adapter->flags &= ~FMP_ADAPTER_LOWER_POWER;
+
+ et131x_enable_txrx(adapter->netdev);
+}
+
+static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
+{
+ u32 tmp_free_buff_ring = *free_buff_ring;
+
+ tmp_free_buff_ring++;
+ /* This works for all cases where limit < 1024. The 1023 case
+ * works because 1023++ is 1024 which means the if condition is not
+ * taken but the carry of the bit into the wrap bit toggles the wrap
+ * value correctly
+ */
+ if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
+ tmp_free_buff_ring &= ~ET_DMA10_MASK;
+ tmp_free_buff_ring ^= ET_DMA10_WRAP;
+ }
+ /* For the 1023 case */
+ tmp_free_buff_ring &= (ET_DMA10_MASK | ET_DMA10_WRAP);
+ *free_buff_ring = tmp_free_buff_ring;
+ return tmp_free_buff_ring;
+}
+
+/* et131x_rx_dma_memory_alloc
+ *
+ * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
+ * and the Packet Status Ring.
+ */
+static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
+{
+ u8 id;
+ u32 i, j;
+ u32 bufsize;
+ u32 psr_size;
+ u32 fbr_chunksize;
+ struct rx_ring *rx_ring = &adapter->rx_ring;
+ struct fbr_lookup *fbr;
+
+ /* Alloc memory for the lookup table */
+ rx_ring->fbr[0] = kmalloc(sizeof(*fbr), GFP_KERNEL);
+ if (rx_ring->fbr[0] == NULL)
+ return -ENOMEM;
+ rx_ring->fbr[1] = kmalloc(sizeof(*fbr), GFP_KERNEL);
+ if (rx_ring->fbr[1] == NULL)
+ return -ENOMEM;
+
+ /* The first thing we will do is configure the sizes of the buffer
+ * rings. These will change based on jumbo packet support. Larger
+ * jumbo packets increases the size of each entry in FBR0, and the
+ * number of entries in FBR0, while at the same time decreasing the
+ * number of entries in FBR1.
+ *
+ * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
+ * entries are huge in order to accommodate a "jumbo" frame, then it
+ * will have less entries. Conversely, FBR1 will now be relied upon
+ * to carry more "normal" frames, thus it's entry size also increases
+ * and the number of entries goes up too (since it now carries
+ * "small" + "regular" packets.
+ *
+ * In this scheme, we try to maintain 512 entries between the two
+ * rings. Also, FBR1 remains a constant size - when it's size doubles
+ * the number of entries halves. FBR0 increases in size, however.
+ */
+ if (adapter->registry_jumbo_packet < 2048) {
+ rx_ring->fbr[0]->buffsize = 256;
+ rx_ring->fbr[0]->num_entries = 512;
+ rx_ring->fbr[1]->buffsize = 2048;
+ rx_ring->fbr[1]->num_entries = 512;
+ } else if (adapter->registry_jumbo_packet < 4096) {
+ rx_ring->fbr[0]->buffsize = 512;
+ rx_ring->fbr[0]->num_entries = 1024;
+ rx_ring->fbr[1]->buffsize = 4096;
+ rx_ring->fbr[1]->num_entries = 512;
+ } else {
+ rx_ring->fbr[0]->buffsize = 1024;
+ rx_ring->fbr[0]->num_entries = 768;
+ rx_ring->fbr[1]->buffsize = 16384;
+ rx_ring->fbr[1]->num_entries = 128;
+ }
+
+ rx_ring->psr_entries = rx_ring->fbr[0]->num_entries +
+ rx_ring->fbr[1]->num_entries;
+
+ for (id = 0; id < NUM_FBRS; id++) {
+ fbr = rx_ring->fbr[id];
+ /* Allocate an area of memory for Free Buffer Ring */
+ bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
+ fbr->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
+ bufsize,
+ &fbr->ring_physaddr,
+ GFP_KERNEL);
+ if (!fbr->ring_virtaddr) {
+ dev_err(&adapter->pdev->dev,
+ "Cannot alloc memory for Free Buffer Ring %d\n",
+ id);
+ return -ENOMEM;
+ }
+ }
+
+ for (id = 0; id < NUM_FBRS; id++) {
+ fbr = rx_ring->fbr[id];
+ fbr_chunksize = (FBR_CHUNKS * fbr->buffsize);
+
+ for (i = 0; i < fbr->num_entries / FBR_CHUNKS; i++) {
+ dma_addr_t fbr_physaddr;
+
+ fbr->mem_virtaddrs[i] = dma_alloc_coherent(
+ &adapter->pdev->dev, fbr_chunksize,
+ &fbr->mem_physaddrs[i],
+ GFP_KERNEL);
+
+ if (!fbr->mem_virtaddrs[i]) {
+ dev_err(&adapter->pdev->dev,
+ "Could not alloc memory\n");
+ return -ENOMEM;
+ }
+
+ /* See NOTE in "Save Physical Address" comment above */
+ fbr_physaddr = fbr->mem_physaddrs[i];
+
+ for (j = 0; j < FBR_CHUNKS; j++) {
+ u32 k = (i * FBR_CHUNKS) + j;
+
+ /* Save the Virtual address of this index for
+ * quick access later
+ */
+ fbr->virt[k] = (u8 *)fbr->mem_virtaddrs[i] +
+ (j * fbr->buffsize);
+
+ /* now store the physical address in the
+ * descriptor so the device can access it
+ */
+ fbr->bus_high[k] = upper_32_bits(fbr_physaddr);
+ fbr->bus_low[k] = lower_32_bits(fbr_physaddr);
+ fbr_physaddr += fbr->buffsize;
+ }
+ }
+ }
+
+ /* Allocate an area of memory for FIFO of Packet Status ring entries */
+ psr_size = sizeof(struct pkt_stat_desc) * rx_ring->psr_entries;
+
+ rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
+ psr_size,
+ &rx_ring->ps_ring_physaddr,
+ GFP_KERNEL);
+
+ if (!rx_ring->ps_ring_virtaddr) {
+ dev_err(&adapter->pdev->dev,
+ "Cannot alloc memory for Packet Status Ring\n");
+ return -ENOMEM;
+ }
+
+ /* NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
+ * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+ * are ever returned, make sure the high part is retrieved here before
+ * storing the adjusted address.
+ */
+
+ /* Allocate an area of memory for writeback of status information */
+ rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
+ sizeof(struct rx_status_block),
+ &rx_ring->rx_status_bus,
+ GFP_KERNEL);
+ if (!rx_ring->rx_status_block) {
+ dev_err(&adapter->pdev->dev,
+ "Cannot alloc memory for Status Block\n");
+ return -ENOMEM;
+ }
+ rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
+
+ /* The RFDs are going to be put on lists later on, so initialize the
+ * lists now.
+ */
+ INIT_LIST_HEAD(&rx_ring->recv_list);
+ return 0;
+}
+
+/* et131x_rx_dma_memory_free - Free all memory allocated within this module */
+static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
+{
+ u8 id;
+ u32 ii;
+ u32 bufsize;
+ u32 psr_size;
+ struct rfd *rfd;
+ struct rx_ring *rx_ring = &adapter->rx_ring;
+ struct fbr_lookup *fbr;
+
+ /* Free RFDs and associated packet descriptors */
+ WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
+
+ while (!list_empty(&rx_ring->recv_list)) {
+ rfd = list_entry(rx_ring->recv_list.next,
+ struct rfd, list_node);
+
+ list_del(&rfd->list_node);
+ rfd->skb = NULL;
+ kfree(rfd);
+ }
+
+ /* Free Free Buffer Rings */
+ for (id = 0; id < NUM_FBRS; id++) {
+ fbr = rx_ring->fbr[id];
+
+ if (!fbr || !fbr->ring_virtaddr)
+ continue;
+
+ /* First the packet memory */
+ for (ii = 0; ii < fbr->num_entries / FBR_CHUNKS; ii++) {
+ if (fbr->mem_virtaddrs[ii]) {
+ bufsize = fbr->buffsize * FBR_CHUNKS;
+
+ dma_free_coherent(&adapter->pdev->dev,
+ bufsize,
+ fbr->mem_virtaddrs[ii],
+ fbr->mem_physaddrs[ii]);
+
+ fbr->mem_virtaddrs[ii] = NULL;
+ }
+ }
+
+ bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
+
+ dma_free_coherent(&adapter->pdev->dev,
+ bufsize,
+ fbr->ring_virtaddr,
+ fbr->ring_physaddr);
+
+ fbr->ring_virtaddr = NULL;
+ }
+
+ /* Free Packet Status Ring */
+ if (rx_ring->ps_ring_virtaddr) {
+ psr_size = sizeof(struct pkt_stat_desc) * rx_ring->psr_entries;
+
+ dma_free_coherent(&adapter->pdev->dev, psr_size,
+ rx_ring->ps_ring_virtaddr,
+ rx_ring->ps_ring_physaddr);
+
+ rx_ring->ps_ring_virtaddr = NULL;
+ }
+
+ /* Free area of memory for the writeback of status information */
+ if (rx_ring->rx_status_block) {
+ dma_free_coherent(&adapter->pdev->dev,
+ sizeof(struct rx_status_block),
+ rx_ring->rx_status_block,
+ rx_ring->rx_status_bus);
+ rx_ring->rx_status_block = NULL;
+ }
+
+ /* Free the FBR Lookup Table */
+ kfree(rx_ring->fbr[0]);
+ kfree(rx_ring->fbr[1]);
+
+ /* Reset Counters */
+ rx_ring->num_ready_recv = 0;
+}
+
+/* et131x_init_recv - Initialize receive data structures */
+static int et131x_init_recv(struct et131x_adapter *adapter)
+{
+ struct rfd *rfd;
+ u32 rfdct;
+ struct rx_ring *rx_ring = &adapter->rx_ring;
+
+ /* Setup each RFD */
+ for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
+ rfd = kzalloc(sizeof(*rfd), GFP_ATOMIC | GFP_DMA);
+ if (!rfd)
+ return -ENOMEM;
+
+ rfd->skb = NULL;
+
+ /* Add this RFD to the recv_list */
+ list_add_tail(&rfd->list_node, &rx_ring->recv_list);
+
+ /* Increment the available RFD's */
+ rx_ring->num_ready_recv++;
+ }
+
+ return 0;
+}
+
+/* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */
+static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
+{
+ struct phy_device *phydev = adapter->phydev;
+
+ /* For version B silicon, we do not use the RxDMA timer for 10 and 100
+ * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
+ */
+ if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
+ writel(0, &adapter->regs->rxdma.max_pkt_time);
+ writel(1, &adapter->regs->rxdma.num_pkt_done);
+ }
+}
+
+/* NICReturnRFD - Recycle a RFD and put it back onto the receive list
+ * @adapter: pointer to our adapter
+ * @rfd: pointer to the RFD
+ */
+static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
+{
+ struct rx_ring *rx_local = &adapter->rx_ring;
+ struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
+ u16 buff_index = rfd->bufferindex;
+ u8 ring_index = rfd->ringindex;
+ unsigned long flags;
+ struct fbr_lookup *fbr = rx_local->fbr[ring_index];
+
+ /* We don't use any of the OOB data besides status. Otherwise, we
+ * need to clean up OOB data
+ */
+ if (buff_index < fbr->num_entries) {
+ u32 free_buff_ring;
+ u32 __iomem *offset;
+ struct fbr_desc *next;
+
+ if (ring_index == 0)
+ offset = &rx_dma->fbr0_full_offset;
+ else
+ offset = &rx_dma->fbr1_full_offset;
+
+ next = (struct fbr_desc *)(fbr->ring_virtaddr) +
+ INDEX10(fbr->local_full);
+
+ /* Handle the Free Buffer Ring advancement here. Write
+ * the PA / Buffer Index for the returned buffer into
+ * the oldest (next to be freed)FBR entry
+ */
+ next->addr_hi = fbr->bus_high[buff_index];
+ next->addr_lo = fbr->bus_low[buff_index];
+ next->word2 = buff_index;
+
+ free_buff_ring = bump_free_buff_ring(&fbr->local_full,
+ fbr->num_entries - 1);
+ writel(free_buff_ring, offset);
+ } else {
+ dev_err(&adapter->pdev->dev,
+ "%s illegal Buffer Index returned\n", __func__);
+ }
+
+ /* The processing on this RFD is done, so put it back on the tail of
+ * our list
+ */
+ spin_lock_irqsave(&adapter->rcv_lock, flags);
+ list_add_tail(&rfd->list_node, &rx_local->recv_list);
+ rx_local->num_ready_recv++;
+ spin_unlock_irqrestore(&adapter->rcv_lock, flags);
+
+ WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
+}
+
+/* nic_rx_pkts - Checks the hardware for available packets
+ *
+ * Returns rfd, a pointer to our MPRFD.
+ *
+ * Checks the hardware for available packets, using completion ring
+ * If packets are available, it gets an RFD from the recv_list, attaches
+ * the packet to it, puts the RFD in the RecvPendList, and also returns
+ * the pointer to the RFD.
+ */
+static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
+{
+ struct rx_ring *rx_local = &adapter->rx_ring;
+ struct rx_status_block *status;
+ struct pkt_stat_desc *psr;
+ struct rfd *rfd;
+ unsigned long flags;
+ struct list_head *element;
+ u8 ring_index;
+ u16 buff_index;
+ u32 len;
+ u32 word0;
+ u32 word1;
+ struct sk_buff *skb;
+ struct fbr_lookup *fbr;
+
+ /* RX Status block is written by the DMA engine prior to every
+ * interrupt. It contains the next to be used entry in the Packet
+ * Status Ring, and also the two Free Buffer rings.
+ */
+ status = rx_local->rx_status_block;
+ word1 = status->word1 >> 16; /* Get the useful bits */
+
+ /* Check the PSR and wrap bits do not match */
+ if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
+ return NULL; /* Looks like this ring is not updated yet */
+
+ /* The packet status ring indicates that data is available. */
+ psr = (struct pkt_stat_desc *)(rx_local->ps_ring_virtaddr) +
+ (rx_local->local_psr_full & 0xFFF);
+
+ /* Grab any information that is required once the PSR is advanced,
+ * since we can no longer rely on the memory being accurate
+ */
+ len = psr->word1 & 0xFFFF;
+ ring_index = (psr->word1 >> 26) & 0x03;
+ fbr = rx_local->fbr[ring_index];
+ buff_index = (psr->word1 >> 16) & 0x3FF;
+ word0 = psr->word0;
+
+ /* Indicate that we have used this PSR entry. */
+ /* FIXME wrap 12 */
+ add_12bit(&rx_local->local_psr_full, 1);
+ if ((rx_local->local_psr_full & 0xFFF) > rx_local->psr_entries - 1) {
+ /* Clear psr full and toggle the wrap bit */
+ rx_local->local_psr_full &= ~0xFFF;
+ rx_local->local_psr_full ^= 0x1000;
+ }
+
+ writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);
+
+ if (ring_index > 1 || buff_index > fbr->num_entries - 1) {
+ /* Illegal buffer or ring index cannot be used by S/W*/
+ dev_err(&adapter->pdev->dev,
+ "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
+ rx_local->local_psr_full & 0xFFF, len, buff_index);
+ return NULL;
+ }
+
+ /* Get and fill the RFD. */
+ spin_lock_irqsave(&adapter->rcv_lock, flags);
+
+ element = rx_local->recv_list.next;
+ rfd = list_entry(element, struct rfd, list_node);
+
+ if (!rfd) {
+ spin_unlock_irqrestore(&adapter->rcv_lock, flags);
+ return NULL;
+ }
+
+ list_del(&rfd->list_node);
+ rx_local->num_ready_recv--;
+
+ spin_unlock_irqrestore(&adapter->rcv_lock, flags);
+
+ rfd->bufferindex = buff_index;
+ rfd->ringindex = ring_index;
+
+ /* In V1 silicon, there is a bug which screws up filtering of runt
+ * packets. Therefore runt packet filtering is disabled in the MAC and
+ * the packets are dropped here. They are also counted here.
+ */
+ if (len < (NIC_MIN_PACKET_SIZE + 4)) {
+ adapter->stats.rx_other_errs++;
+ rfd->len = 0;
+ goto out;
+ }
+
+ if ((word0 & ALCATEL_MULTICAST_PKT) && !(word0 & ALCATEL_BROADCAST_PKT))
+ adapter->stats.multicast_pkts_rcvd++;
+
+ rfd->len = len;
+
+ skb = dev_alloc_skb(rfd->len + 2);
+ if (!skb) {
+ dev_err(&adapter->pdev->dev, "Couldn't alloc an SKB for Rx\n");
+ return NULL;
+ }
+
+ adapter->netdev->stats.rx_bytes += rfd->len;
+
+ memcpy(skb_put(skb, rfd->len), fbr->virt[buff_index], rfd->len);
+
+ skb->protocol = eth_type_trans(skb, adapter->netdev);
+ skb->ip_summed = CHECKSUM_NONE;
+ netif_receive_skb(skb);
+
+out:
+ nic_return_rfd(adapter, rfd);
+ return rfd;
+}
+
+/* et131x_handle_recv_pkts - Interrupt handler for receive processing
+ *
+ * Assumption, Rcv spinlock has been acquired.
+ */
+static int et131x_handle_recv_pkts(struct et131x_adapter *adapter, int budget)
+{
+ struct rfd *rfd = NULL;
+ int count = 0;
+ int limit = budget;
+ bool done = true;
+ struct rx_ring *rx_ring = &adapter->rx_ring;
+
+ if (budget > MAX_PACKETS_HANDLED)
+ limit = MAX_PACKETS_HANDLED;
+
+ /* Process up to available RFD's */
+ while (count < limit) {
+ if (list_empty(&rx_ring->recv_list)) {
+ WARN_ON(rx_ring->num_ready_recv != 0);
+ done = false;
+ break;
+ }
+
+ rfd = nic_rx_pkts(adapter);
+
+ if (rfd == NULL)
+ break;
+
+ /* Do not receive any packets until a filter has been set.
+ * Do not receive any packets until we have link.
+ * If length is zero, return the RFD in order to advance the
+ * Free buffer ring.
+ */
+ if (!adapter->packet_filter ||
+ !netif_carrier_ok(adapter->netdev) ||
+ rfd->len == 0)
+ continue;
+
+ /* Increment the number of packets we received */
+ adapter->netdev->stats.rx_packets++;
+
+ /* Set the status on the packet, either resources or success */
+ if (rx_ring->num_ready_recv < RFD_LOW_WATER_MARK)
+ dev_warn(&adapter->pdev->dev, "RFD's are running out\n");
+
+ count++;
+ }
+
+ if (count == limit || !done) {
+ rx_ring->unfinished_receives = true;
+ writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
+ &adapter->regs->global.watchdog_timer);
+ } else {
+ /* Watchdog timer will disable itself if appropriate. */
+ rx_ring->unfinished_receives = false;
+ }
+
+ return count;
+}
+
+/* et131x_tx_dma_memory_alloc
+ *
+ * Allocates memory that will be visible both to the device and to the CPU.
+ * The OS will pass us packets, pointers to which we will insert in the Tx
+ * Descriptor queue. The device will read this queue to find the packets in
+ * memory. The device will update the "status" in memory each time it xmits a
+ * packet.
+ */
+static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
+{
+ int desc_size = 0;
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+
+ /* Allocate memory for the TCB's (Transmit Control Block) */
+ tx_ring->tcb_ring = kcalloc(NUM_TCB, sizeof(struct tcb),
+ GFP_ATOMIC | GFP_DMA);
+ if (!tx_ring->tcb_ring)
+ return -ENOMEM;
+
+ desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
+ tx_ring->tx_desc_ring = dma_alloc_coherent(&adapter->pdev->dev,
+ desc_size,
+ &tx_ring->tx_desc_ring_pa,
+ GFP_KERNEL);
+ if (!tx_ring->tx_desc_ring) {
+ dev_err(&adapter->pdev->dev,
+ "Cannot alloc memory for Tx Ring\n");
+ return -ENOMEM;
+ }
+
+ /* Save physical address
+ *
+ * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
+ * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
+ * are ever returned, make sure the high part is retrieved here before
+ * storing the adjusted address.
+ */
+ /* Allocate memory for the Tx status block */
+ tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
+ sizeof(u32),
+ &tx_ring->tx_status_pa,
+ GFP_KERNEL);
+ if (!tx_ring->tx_status_pa) {
+ dev_err(&adapter->pdev->dev,
+ "Cannot alloc memory for Tx status block\n");
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+/* et131x_tx_dma_memory_free - Free all memory allocated within this module */
+static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
+{
+ int desc_size = 0;
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+
+ if (tx_ring->tx_desc_ring) {
+ /* Free memory relating to Tx rings here */
+ desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
+ dma_free_coherent(&adapter->pdev->dev,
+ desc_size,
+ tx_ring->tx_desc_ring,
+ tx_ring->tx_desc_ring_pa);
+ tx_ring->tx_desc_ring = NULL;
+ }
+
+ /* Free memory for the Tx status block */
+ if (tx_ring->tx_status) {
+ dma_free_coherent(&adapter->pdev->dev,
+ sizeof(u32),
+ tx_ring->tx_status,
+ tx_ring->tx_status_pa);
+
+ tx_ring->tx_status = NULL;
+ }
+ /* Free the memory for the tcb structures */
+ kfree(tx_ring->tcb_ring);
+}
+
+/* nic_send_packet - NIC specific send handler for version B silicon.
+ * @adapter: pointer to our adapter
+ * @tcb: pointer to struct tcb
+ */
+static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
+{
+ u32 i;
+ struct tx_desc desc[24]; /* 24 x 16 byte */
+ u32 frag = 0;
+ u32 thiscopy, remainder;
+ struct sk_buff *skb = tcb->skb;
+ u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
+ struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
+ struct phy_device *phydev = adapter->phydev;
+ dma_addr_t dma_addr;
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+
+ /* Part of the optimizations of this send routine restrict us to
+ * sending 24 fragments at a pass. In practice we should never see
+ * more than 5 fragments.
+ *
+ * NOTE: The older version of this function (below) can handle any
+ * number of fragments. If needed, we can call this function,
+ * although it is less efficient.
+ */
+
+ /* nr_frags should be no more than 18. */
+ BUILD_BUG_ON(MAX_SKB_FRAGS + 1 > 23);
+
+ memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
+
+ for (i = 0; i < nr_frags; i++) {
+ /* If there is something in this element, lets get a
+ * descriptor from the ring and get the necessary data
+ */
+ if (i == 0) {
+ /* If the fragments are smaller than a standard MTU,
+ * then map them to a single descriptor in the Tx
+ * Desc ring. However, if they're larger, as is
+ * possible with support for jumbo packets, then
+ * split them each across 2 descriptors.
+ *
+ * This will work until we determine why the hardware
+ * doesn't seem to like large fragments.
+ */
+ if (skb_headlen(skb) <= 1514) {
+ /* Low 16bits are length, high is vlan and
+ * unused currently so zero
+ */
+ desc[frag].len_vlan = skb_headlen(skb);
+ dma_addr = dma_map_single(&adapter->pdev->dev,
+ skb->data,
+ skb_headlen(skb),
+ DMA_TO_DEVICE);
+ desc[frag].addr_lo = lower_32_bits(dma_addr);
+ desc[frag].addr_hi = upper_32_bits(dma_addr);
+ frag++;
+ } else {
+ desc[frag].len_vlan = skb_headlen(skb) / 2;
+ dma_addr = dma_map_single(&adapter->pdev->dev,
+ skb->data,
+ (skb_headlen(skb) / 2),
+ DMA_TO_DEVICE);
+ desc[frag].addr_lo = lower_32_bits(dma_addr);
+ desc[frag].addr_hi = upper_32_bits(dma_addr);
+ frag++;
+
+ desc[frag].len_vlan = skb_headlen(skb) / 2;
+ dma_addr = dma_map_single(&adapter->pdev->dev,
+ skb->data +
+ (skb_headlen(skb) / 2),
+ (skb_headlen(skb) / 2),
+ DMA_TO_DEVICE);
+ desc[frag].addr_lo = lower_32_bits(dma_addr);
+ desc[frag].addr_hi = upper_32_bits(dma_addr);
+ frag++;
+ }
+ } else {
+ desc[frag].len_vlan = frags[i - 1].size;
+ dma_addr = skb_frag_dma_map(&adapter->pdev->dev,
+ &frags[i - 1],
+ 0,
+ frags[i - 1].size,
+ DMA_TO_DEVICE);
+ desc[frag].addr_lo = lower_32_bits(dma_addr);
+ desc[frag].addr_hi = upper_32_bits(dma_addr);
+ frag++;
+ }
+ }
+
+ if (phydev && phydev->speed == SPEED_1000) {
+ if (++tx_ring->since_irq == PARM_TX_NUM_BUFS_DEF) {
+ /* Last element & Interrupt flag */
+ desc[frag - 1].flags =
+ TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
+ tx_ring->since_irq = 0;
+ } else { /* Last element */
+ desc[frag - 1].flags = TXDESC_FLAG_LASTPKT;
+ }
+ } else {
+ desc[frag - 1].flags =
+ TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
+ }
+
+ desc[0].flags |= TXDESC_FLAG_FIRSTPKT;
+
+ tcb->index_start = tx_ring->send_idx;
+ tcb->stale = 0;
+
+ thiscopy = NUM_DESC_PER_RING_TX - INDEX10(tx_ring->send_idx);
+
+ if (thiscopy >= frag) {
+ remainder = 0;
+ thiscopy = frag;
+ } else {
+ remainder = frag - thiscopy;
+ }
+
+ memcpy(tx_ring->tx_desc_ring + INDEX10(tx_ring->send_idx),
+ desc,
+ sizeof(struct tx_desc) * thiscopy);
+
+ add_10bit(&tx_ring->send_idx, thiscopy);
+
+ if (INDEX10(tx_ring->send_idx) == 0 ||
+ INDEX10(tx_ring->send_idx) == NUM_DESC_PER_RING_TX) {
+ tx_ring->send_idx &= ~ET_DMA10_MASK;
+ tx_ring->send_idx ^= ET_DMA10_WRAP;
+ }
+
+ if (remainder) {
+ memcpy(tx_ring->tx_desc_ring,
+ desc + thiscopy,
+ sizeof(struct tx_desc) * remainder);
+
+ add_10bit(&tx_ring->send_idx, remainder);
+ }
+
+ if (INDEX10(tx_ring->send_idx) == 0) {
+ if (tx_ring->send_idx)
+ tcb->index = NUM_DESC_PER_RING_TX - 1;
+ else
+ tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
+ } else {
+ tcb->index = tx_ring->send_idx - 1;
+ }
+
+ spin_lock(&adapter->tcb_send_qlock);
+
+ if (tx_ring->send_tail)
+ tx_ring->send_tail->next = tcb;
+ else
+ tx_ring->send_head = tcb;
+
+ tx_ring->send_tail = tcb;
+
+ WARN_ON(tcb->next != NULL);
+
+ tx_ring->used++;
+
+ spin_unlock(&adapter->tcb_send_qlock);
+
+ /* Write the new write pointer back to the device. */
+ writel(tx_ring->send_idx, &adapter->regs->txdma.service_request);
+
+ /* For Gig only, we use Tx Interrupt coalescing. Enable the software
+ * timer to wake us up if this packet isn't followed by N more.
+ */
+ if (phydev && phydev->speed == SPEED_1000) {
+ writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
+ &adapter->regs->global.watchdog_timer);
+ }
+ return 0;
+}
+
+/* send_packet - Do the work to send a packet
+ *
+ * Assumption: Send spinlock has been acquired
+ */
+static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
+{
+ int status;
+ struct tcb *tcb;
+ unsigned long flags;
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+
+ /* All packets must have at least a MAC address and a protocol type */
+ if (skb->len < ETH_HLEN)
+ return -EIO;
+
+ /* Get a TCB for this packet */
+ spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
+
+ tcb = tx_ring->tcb_qhead;
+
+ if (tcb == NULL) {
+ spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
+ return -ENOMEM;
+ }
+
+ tx_ring->tcb_qhead = tcb->next;
+
+ if (tx_ring->tcb_qhead == NULL)
+ tx_ring->tcb_qtail = NULL;
+
+ spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
+
+ tcb->skb = skb;
+ tcb->next = NULL;
+
+ /* Call the NIC specific send handler. */
+ status = nic_send_packet(adapter, tcb);
+
+ if (status != 0) {
+ spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
+
+ if (tx_ring->tcb_qtail)
+ tx_ring->tcb_qtail->next = tcb;
+ else
+ /* Apparently ready Q is empty. */
+ tx_ring->tcb_qhead = tcb;
+
+ tx_ring->tcb_qtail = tcb;
+ spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
+ return status;
+ }
+ WARN_ON(tx_ring->used > NUM_TCB);
+ return 0;
+}
+
+/* free_send_packet - Recycle a struct tcb
+ * @adapter: pointer to our adapter
+ * @tcb: pointer to struct tcb
+ *
+ * Complete the packet if necessary
+ * Assumption - Send spinlock has been acquired
+ */
+static inline void free_send_packet(struct et131x_adapter *adapter,
+ struct tcb *tcb)
+{
+ unsigned long flags;
+ struct tx_desc *desc = NULL;
+ struct net_device_stats *stats = &adapter->netdev->stats;
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+ u64 dma_addr;
+
+ if (tcb->skb) {
+ stats->tx_bytes += tcb->skb->len;
+
+ /* Iterate through the TX descriptors on the ring
+ * corresponding to this packet and umap the fragments
+ * they point to
+ */
+ do {
+ desc = tx_ring->tx_desc_ring +
+ INDEX10(tcb->index_start);
+
+ dma_addr = desc->addr_lo;
+ dma_addr |= (u64)desc->addr_hi << 32;
+
+ dma_unmap_single(&adapter->pdev->dev,
+ dma_addr,
+ desc->len_vlan, DMA_TO_DEVICE);
+
+ add_10bit(&tcb->index_start, 1);
+ if (INDEX10(tcb->index_start) >=
+ NUM_DESC_PER_RING_TX) {
+ tcb->index_start &= ~ET_DMA10_MASK;
+ tcb->index_start ^= ET_DMA10_WRAP;
+ }
+ } while (desc != tx_ring->tx_desc_ring + INDEX10(tcb->index));
+
+ dev_kfree_skb_any(tcb->skb);
+ }
+
+ memset(tcb, 0, sizeof(struct tcb));
+
+ /* Add the TCB to the Ready Q */
+ spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
+
+ stats->tx_packets++;
+
+ if (tx_ring->tcb_qtail)
+ tx_ring->tcb_qtail->next = tcb;
+ else
+ /* Apparently ready Q is empty. */
+ tx_ring->tcb_qhead = tcb;
+
+ tx_ring->tcb_qtail = tcb;
+
+ spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
+ WARN_ON(tx_ring->used < 0);
+}
+
+/* et131x_free_busy_send_packets - Free and complete the stopped active sends
+ *
+ * Assumption - Send spinlock has been acquired
+ */
+static void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
+{
+ struct tcb *tcb;
+ unsigned long flags;
+ u32 freed = 0;
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+
+ /* Any packets being sent? Check the first TCB on the send list */
+ spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
+
+ tcb = tx_ring->send_head;
+
+ while (tcb != NULL && freed < NUM_TCB) {
+ struct tcb *next = tcb->next;
+
+ tx_ring->send_head = next;
+
+ if (next == NULL)
+ tx_ring->send_tail = NULL;
+
+ tx_ring->used--;
+
+ spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
+
+ freed++;
+ free_send_packet(adapter, tcb);
+
+ spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
+
+ tcb = tx_ring->send_head;
+ }
+
+ WARN_ON(freed == NUM_TCB);
+
+ spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
+
+ tx_ring->used = 0;
+}
+
+/* et131x_handle_send_pkts - Interrupt handler for sending processing
+ *
+ * Re-claim the send resources, complete sends and get more to send from
+ * the send wait queue.
+ *
+ * Assumption - Send spinlock has been acquired
+ */
+static void et131x_handle_send_pkts(struct et131x_adapter *adapter)
+{
+ unsigned long flags;
+ u32 serviced;
+ struct tcb *tcb;
+ u32 index;
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+
+ serviced = readl(&adapter->regs->txdma.new_service_complete);
+ index = INDEX10(serviced);
+
+ /* Has the ring wrapped? Process any descriptors that do not have
+ * the same "wrap" indicator as the current completion indicator
+ */
+ spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
+
+ tcb = tx_ring->send_head;
+
+ while (tcb &&
+ ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
+ index < INDEX10(tcb->index)) {
+ tx_ring->used--;
+ tx_ring->send_head = tcb->next;
+ if (tcb->next == NULL)
+ tx_ring->send_tail = NULL;
+
+ spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
+ free_send_packet(adapter, tcb);
+ spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
+
+ /* Goto the next packet */
+ tcb = tx_ring->send_head;
+ }
+ while (tcb &&
+ !((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
+ index > (tcb->index & ET_DMA10_MASK)) {
+ tx_ring->used--;
+ tx_ring->send_head = tcb->next;
+ if (tcb->next == NULL)
+ tx_ring->send_tail = NULL;
+
+ spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
+ free_send_packet(adapter, tcb);
+ spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
+
+ /* Goto the next packet */
+ tcb = tx_ring->send_head;
+ }
+
+ /* Wake up the queue when we hit a low-water mark */
+ if (tx_ring->used <= NUM_TCB / 3)
+ netif_wake_queue(adapter->netdev);
+
+ spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
+}
+
+static int et131x_get_settings(struct net_device *netdev,
+ struct ethtool_cmd *cmd)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ return phy_ethtool_gset(adapter->phydev, cmd);
+}
+
+static int et131x_set_settings(struct net_device *netdev,
+ struct ethtool_cmd *cmd)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ return phy_ethtool_sset(adapter->phydev, cmd);
+}
+
+static int et131x_get_regs_len(struct net_device *netdev)
+{
+#define ET131X_REGS_LEN 256
+ return ET131X_REGS_LEN * sizeof(u32);
+}
+
+static void et131x_get_regs(struct net_device *netdev,
+ struct ethtool_regs *regs, void *regs_data)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+ struct address_map __iomem *aregs = adapter->regs;
+ u32 *regs_buff = regs_data;
+ u32 num = 0;
+ u16 tmp;
+
+ memset(regs_data, 0, et131x_get_regs_len(netdev));
+
+ regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
+ adapter->pdev->device;
+
+ /* PHY regs */
+ et131x_mii_read(adapter, MII_BMCR, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_BMSR, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_PHYSID1, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_PHYSID2, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_ADVERTISE, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_LPA, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_EXPANSION, &tmp);
+ regs_buff[num++] = tmp;
+ /* Autoneg next page transmit reg */
+ et131x_mii_read(adapter, 0x07, &tmp);
+ regs_buff[num++] = tmp;
+ /* Link partner next page reg */
+ et131x_mii_read(adapter, 0x08, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_CTRL1000, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_STAT1000, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, 0x0b, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, 0x0c, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_MMD_CTRL, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_MMD_DATA, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, MII_ESTATUS, &tmp);
+ regs_buff[num++] = tmp;
+
+ et131x_mii_read(adapter, PHY_INDEX_REG, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_DATA_REG, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL + 1, &tmp);
+ regs_buff[num++] = tmp;
+
+ et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_CONFIG, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_PHY_CONTROL, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_PHY_STATUS, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_LED_1, &tmp);
+ regs_buff[num++] = tmp;
+ et131x_mii_read(adapter, PHY_LED_2, &tmp);
+ regs_buff[num++] = tmp;
+
+ /* Global regs */
+ regs_buff[num++] = readl(&aregs->global.txq_start_addr);
+ regs_buff[num++] = readl(&aregs->global.txq_end_addr);
+ regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
+ regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
+ regs_buff[num++] = readl(&aregs->global.pm_csr);
+ regs_buff[num++] = adapter->stats.interrupt_status;
+ regs_buff[num++] = readl(&aregs->global.int_mask);
+ regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
+ regs_buff[num++] = readl(&aregs->global.int_status_alias);
+ regs_buff[num++] = readl(&aregs->global.sw_reset);
+ regs_buff[num++] = readl(&aregs->global.slv_timer);
+ regs_buff[num++] = readl(&aregs->global.msi_config);
+ regs_buff[num++] = readl(&aregs->global.loopback);
+ regs_buff[num++] = readl(&aregs->global.watchdog_timer);
+
+ /* TXDMA regs */
+ regs_buff[num++] = readl(&aregs->txdma.csr);
+ regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
+ regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
+ regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
+ regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
+ regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
+ regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
+ regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
+ regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
+ regs_buff[num++] = readl(&aregs->txdma.service_request);
+ regs_buff[num++] = readl(&aregs->txdma.service_complete);
+ regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
+ regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
+ regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
+ regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
+ regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
+ regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
+ regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
+ regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
+ regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
+ regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
+ regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
+ regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
+ regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
+ regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
+ regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
+
+ /* RXDMA regs */
+ regs_buff[num++] = readl(&aregs->rxdma.csr);
+ regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
+ regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
+ regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
+ regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
+ regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
+ regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
+ regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
+ regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
+ regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
+ regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
+ regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
+ regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
+ regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
+ regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
+ regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
+}
+
+static void et131x_get_drvinfo(struct net_device *netdev,
+ struct ethtool_drvinfo *info)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
+ strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
+ strlcpy(info->bus_info, pci_name(adapter->pdev),
+ sizeof(info->bus_info));
+}
+
+static struct ethtool_ops et131x_ethtool_ops = {
+ .get_settings = et131x_get_settings,
+ .set_settings = et131x_set_settings,
+ .get_drvinfo = et131x_get_drvinfo,
+ .get_regs_len = et131x_get_regs_len,
+ .get_regs = et131x_get_regs,
+ .get_link = ethtool_op_get_link,
+};
+
+/* et131x_hwaddr_init - set up the MAC Address on the ET1310 */
+static void et131x_hwaddr_init(struct et131x_adapter *adapter)
+{
+ /* If have our default mac from init and no mac address from
+ * EEPROM then we need to generate the last octet and set it on the
+ * device
+ */
+ if (is_zero_ether_addr(adapter->rom_addr)) {
+ /* We need to randomly generate the last octet so we
+ * decrease our chances of setting the mac address to
+ * same as another one of our cards in the system
+ */
+ get_random_bytes(&adapter->addr[5], 1);
+ /* We have the default value in the register we are
+ * working with so we need to copy the current
+ * address into the permanent address
+ */
+ memcpy(adapter->rom_addr,
+ adapter->addr, ETH_ALEN);
+ } else {
+ /* We do not have an override address, so set the
+ * current address to the permanent address and add
+ * it to the device
+ */
+ memcpy(adapter->addr,
+ adapter->rom_addr, ETH_ALEN);
+ }
+}
+
+/* et131x_pci_init - initial PCI setup
+ *
+ * Perform the initial setup of PCI registers and if possible initialise
+ * the MAC address. At this point the I/O registers have yet to be mapped
+ */
+static int et131x_pci_init(struct et131x_adapter *adapter,
+ struct pci_dev *pdev)
+{
+ u16 max_payload;
+ int i, rc;
+
+ rc = et131x_init_eeprom(adapter);
+ if (rc < 0)
+ goto out;
+
+ if (!pci_is_pcie(pdev)) {
+ dev_err(&pdev->dev, "Missing PCIe capabilities\n");
+ goto err_out;
+ }
+
+ /* Let's set up the PORT LOGIC Register. */
+
+ /* Program the Ack/Nak latency and replay timers */
+ max_payload = pdev->pcie_mpss;
+
+ if (max_payload < 2) {
+ static const u16 acknak[2] = { 0x76, 0xD0 };
+ static const u16 replay[2] = { 0x1E0, 0x2ED };
+
+ if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
+ acknak[max_payload])) {
+ dev_err(&pdev->dev,
+ "Could not write PCI config space for ACK/NAK\n");
+ goto err_out;
+ }
+ if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
+ replay[max_payload])) {
+ dev_err(&pdev->dev,
+ "Could not write PCI config space for Replay Timer\n");
+ goto err_out;
+ }
+ }
+
+ /* l0s and l1 latency timers. We are using default values.
+ * Representing 001 for L0s and 010 for L1
+ */
+ if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
+ dev_err(&pdev->dev,
+ "Could not write PCI config space for Latency Timers\n");
+ goto err_out;
+ }
+
+ /* Change the max read size to 2k */
+ if (pcie_set_readrq(pdev, 2048)) {
+ dev_err(&pdev->dev,
+ "Couldn't change PCI config space for Max read size\n");
+ goto err_out;
+ }
+
+ /* Get MAC address from config space if an eeprom exists, otherwise
+ * the MAC address there will not be valid
+ */
+ if (!adapter->has_eeprom) {
+ et131x_hwaddr_init(adapter);
+ return 0;
+ }
+
+ for (i = 0; i < ETH_ALEN; i++) {
+ if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
+ adapter->rom_addr + i)) {
+ dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
+ goto err_out;
+ }
+ }
+ ether_addr_copy(adapter->addr, adapter->rom_addr);
+out:
+ return rc;
+err_out:
+ rc = -EIO;
+ goto out;
+}
+
+/* et131x_error_timer_handler
+ * @data: timer-specific variable; here a pointer to our adapter structure
+ *
+ * The routine called when the error timer expires, to track the number of
+ * recurring errors.
+ */
+static void et131x_error_timer_handler(unsigned long data)
+{
+ struct et131x_adapter *adapter = (struct et131x_adapter *)data;
+ struct phy_device *phydev = adapter->phydev;
+
+ if (et1310_in_phy_coma(adapter)) {
+ /* Bring the device immediately out of coma, to
+ * prevent it from sleeping indefinitely, this
+ * mechanism could be improved!
+ */
+ et1310_disable_phy_coma(adapter);
+ adapter->boot_coma = 20;
+ } else {
+ et1310_update_macstat_host_counters(adapter);
+ }
+
+ if (!phydev->link && adapter->boot_coma < 11)
+ adapter->boot_coma++;
+
+ if (adapter->boot_coma == 10) {
+ if (!phydev->link) {
+ if (!et1310_in_phy_coma(adapter)) {
+ /* NOTE - This was originally a 'sync with
+ * interrupt'. How to do that under Linux?
+ */
+ et131x_enable_interrupts(adapter);
+ et1310_enable_phy_coma(adapter);
+ }
+ }
+ }
+
+ /* This is a periodic timer, so reschedule */
+ mod_timer(&adapter->error_timer, jiffies + TX_ERROR_PERIOD * HZ / 1000);
+}
+
+/* et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx */
+static void et131x_adapter_memory_free(struct et131x_adapter *adapter)
+{
+ et131x_tx_dma_memory_free(adapter);
+ et131x_rx_dma_memory_free(adapter);
+}
+
+/* et131x_adapter_memory_alloc
+ * Allocate all the memory blocks for send, receive and others.
+ */
+static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
+{
+ int status;
+
+ /* Allocate memory for the Tx Ring */
+ status = et131x_tx_dma_memory_alloc(adapter);
+ if (status) {
+ dev_err(&adapter->pdev->dev,
+ "et131x_tx_dma_memory_alloc FAILED\n");
+ et131x_tx_dma_memory_free(adapter);
+ return status;
+ }
+ /* Receive buffer memory allocation */
+ status = et131x_rx_dma_memory_alloc(adapter);
+ if (status) {
+ dev_err(&adapter->pdev->dev,
+ "et131x_rx_dma_memory_alloc FAILED\n");
+ et131x_adapter_memory_free(adapter);
+ return status;
+ }
+
+ /* Init receive data structures */
+ status = et131x_init_recv(adapter);
+ if (status) {
+ dev_err(&adapter->pdev->dev, "et131x_init_recv FAILED\n");
+ et131x_adapter_memory_free(adapter);
+ }
+ return status;
+}
+
+static void et131x_adjust_link(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+ struct phy_device *phydev = adapter->phydev;
+
+ if (!phydev)
+ return;
+ if (phydev->link == adapter->link)
+ return;
+
+ /* Check to see if we are in coma mode and if
+ * so, disable it because we will not be able
+ * to read PHY values until we are out.
+ */
+ if (et1310_in_phy_coma(adapter))
+ et1310_disable_phy_coma(adapter);
+
+ adapter->link = phydev->link;
+ phy_print_status(phydev);
+
+ if (phydev->link) {
+ adapter->boot_coma = 20;
+ if (phydev->speed == SPEED_10) {
+ u16 register18;
+
+ et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
+ ®ister18);
+ et131x_mii_write(adapter, phydev->addr,
+ PHY_MPHY_CONTROL_REG, register18 | 0x4);
+ et131x_mii_write(adapter, phydev->addr, PHY_INDEX_REG,
+ register18 | 0x8402);
+ et131x_mii_write(adapter, phydev->addr, PHY_DATA_REG,
+ register18 | 511);
+ et131x_mii_write(adapter, phydev->addr,
+ PHY_MPHY_CONTROL_REG, register18);
+ }
+
+ et1310_config_flow_control(adapter);
+
+ if (phydev->speed == SPEED_1000 &&
+ adapter->registry_jumbo_packet > 2048) {
+ u16 reg;
+
+ et131x_mii_read(adapter, PHY_CONFIG, ®);
+ reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
+ reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
+ et131x_mii_write(adapter, phydev->addr, PHY_CONFIG,
+ reg);
+ }
+
+ et131x_set_rx_dma_timer(adapter);
+ et1310_config_mac_regs2(adapter);
+ } else {
+ adapter->boot_coma = 0;
+
+ if (phydev->speed == SPEED_10) {
+ u16 register18;
+
+ et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
+ ®ister18);
+ et131x_mii_write(adapter, phydev->addr,
+ PHY_MPHY_CONTROL_REG, register18 | 0x4);
+ et131x_mii_write(adapter, phydev->addr,
+ PHY_INDEX_REG, register18 | 0x8402);
+ et131x_mii_write(adapter, phydev->addr,
+ PHY_DATA_REG, register18 | 511);
+ et131x_mii_write(adapter, phydev->addr,
+ PHY_MPHY_CONTROL_REG, register18);
+ }
+
+ /* Free the packets being actively sent & stopped */
+ et131x_free_busy_send_packets(adapter);
+
+ /* Re-initialize the send structures */
+ et131x_init_send(adapter);
+
+ /* Bring the device back to the state it was during
+ * init prior to autonegotiation being complete. This
+ * way, when we get the auto-neg complete interrupt,
+ * we can complete init by calling config_mac_regs2.
+ */
+ et131x_soft_reset(adapter);
+
+ /* Setup ET1310 as per the documentation */
+ et131x_adapter_setup(adapter);
+
+ /* perform reset of tx/rx */
+ et131x_disable_txrx(netdev);
+ et131x_enable_txrx(netdev);
+ }
+}
+
+static int et131x_mii_probe(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+ struct phy_device *phydev = NULL;
+
+ phydev = phy_find_first(adapter->mii_bus);
+ if (!phydev) {
+ dev_err(&adapter->pdev->dev, "no PHY found\n");
+ return -ENODEV;
+ }
+
+ phydev = phy_connect(netdev, dev_name(&phydev->dev),
+ &et131x_adjust_link, PHY_INTERFACE_MODE_MII);
+
+ if (IS_ERR(phydev)) {
+ dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
+ return PTR_ERR(phydev);
+ }
+
+ phydev->supported &= (SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |
+ SUPPORTED_Autoneg |
+ SUPPORTED_MII |
+ SUPPORTED_TP);
+
+ if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
+ phydev->supported |= SUPPORTED_1000baseT_Half |
+ SUPPORTED_1000baseT_Full;
+
+ phydev->advertising = phydev->supported;
+ phydev->autoneg = AUTONEG_ENABLE;
+ adapter->phydev = phydev;
+
+ dev_info(&adapter->pdev->dev,
+ "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
+ phydev->drv->name, dev_name(&phydev->dev));
+
+ return 0;
+}
+
+/* et131x_adapter_init
+ *
+ * Initialize the data structures for the et131x_adapter object and link
+ * them together with the platform provided device structures.
+ */
+static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
+ struct pci_dev *pdev)
+{
+ static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
+
+ struct et131x_adapter *adapter;
+
+ /* Allocate private adapter struct and copy in relevant information */
+ adapter = netdev_priv(netdev);
+ adapter->pdev = pci_dev_get(pdev);
+ adapter->netdev = netdev;
+
+ /* Initialize spinlocks here */
+ spin_lock_init(&adapter->tcb_send_qlock);
+ spin_lock_init(&adapter->tcb_ready_qlock);
+ spin_lock_init(&adapter->rcv_lock);
+
+ adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
+
+ /* Set the MAC address to a default */
+ ether_addr_copy(adapter->addr, default_mac);
+
+ return adapter;
+}
+
+/* et131x_pci_remove
+ *
+ * Registered in the pci_driver structure, this function is called when the
+ * PCI subsystem detects that a PCI device which matches the information
+ * contained in the pci_device_id table has been removed.
+ */
+static void et131x_pci_remove(struct pci_dev *pdev)
+{
+ struct net_device *netdev = pci_get_drvdata(pdev);
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ unregister_netdev(netdev);
+ netif_napi_del(&adapter->napi);
+ phy_disconnect(adapter->phydev);
+ mdiobus_unregister(adapter->mii_bus);
+ kfree(adapter->mii_bus->irq);
+ mdiobus_free(adapter->mii_bus);
+
+ et131x_adapter_memory_free(adapter);
+ iounmap(adapter->regs);
+ pci_dev_put(pdev);
+
+ free_netdev(netdev);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+}
+
+/* et131x_up - Bring up a device for use. */
+static void et131x_up(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ et131x_enable_txrx(netdev);
+ phy_start(adapter->phydev);
+}
+
+/* et131x_down - Bring down the device */
+static void et131x_down(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ /* Save the timestamp for the TX watchdog, prevent a timeout */
+ netdev->trans_start = jiffies;
+
+ phy_stop(adapter->phydev);
+ et131x_disable_txrx(netdev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int et131x_suspend(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct net_device *netdev = pci_get_drvdata(pdev);
+
+ if (netif_running(netdev)) {
+ netif_device_detach(netdev);
+ et131x_down(netdev);
+ pci_save_state(pdev);
+ }
+
+ return 0;
+}
+
+static int et131x_resume(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct net_device *netdev = pci_get_drvdata(pdev);
+
+ if (netif_running(netdev)) {
+ pci_restore_state(pdev);
+ et131x_up(netdev);
+ netif_device_attach(netdev);
+ }
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
+#define ET131X_PM_OPS (&et131x_pm_ops)
+#else
+#define ET131X_PM_OPS NULL
+#endif
+
+/* et131x_isr - The Interrupt Service Routine for the driver.
+ * @irq: the IRQ on which the interrupt was received.
+ * @dev_id: device-specific info (here a pointer to a net_device struct)
+ *
+ * Returns a value indicating if the interrupt was handled.
+ */
+static irqreturn_t et131x_isr(int irq, void *dev_id)
+{
+ bool handled = true;
+ bool enable_interrupts = true;
+ struct net_device *netdev = (struct net_device *)dev_id;
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+ struct address_map __iomem *iomem = adapter->regs;
+ struct rx_ring *rx_ring = &adapter->rx_ring;
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+ u32 status;
+
+ if (!netif_device_present(netdev)) {
+ handled = false;
+ enable_interrupts = false;
+ goto out;
+ }
+
+ /* If the adapter is in low power state, then it should not
+ * recognize any interrupt
+ */
+
+ /* Disable Device Interrupts */
+ et131x_disable_interrupts(adapter);
+
+ /* Get a copy of the value in the interrupt status register
+ * so we can process the interrupting section
+ */
+ status = readl(&adapter->regs->global.int_status);
+
+ if (adapter->flow == FLOW_TXONLY || adapter->flow == FLOW_BOTH)
+ status &= ~INT_MASK_ENABLE;
+ else
+ status &= ~INT_MASK_ENABLE_NO_FLOW;
+
+ /* Make sure this is our interrupt */
+ if (!status) {
+ handled = false;
+ et131x_enable_interrupts(adapter);
+ goto out;
+ }
+
+ /* This is our interrupt, so process accordingly */
+ if (status & ET_INTR_WATCHDOG) {
+ struct tcb *tcb = tx_ring->send_head;
+
+ if (tcb)
+ if (++tcb->stale > 1)
+ status |= ET_INTR_TXDMA_ISR;
+
+ if (rx_ring->unfinished_receives)
+ status |= ET_INTR_RXDMA_XFR_DONE;
+ else if (tcb == NULL)
+ writel(0, &adapter->regs->global.watchdog_timer);
+
+ status &= ~ET_INTR_WATCHDOG;
+ }
+
+ if (status & (ET_INTR_RXDMA_XFR_DONE | ET_INTR_TXDMA_ISR)) {
+ enable_interrupts = false;
+ napi_schedule(&adapter->napi);
+ }
+
+ status &= ~(ET_INTR_TXDMA_ISR | ET_INTR_RXDMA_XFR_DONE);
+
+ if (!status)
+ goto out;
+
+ /* Handle the TXDMA Error interrupt */
+ if (status & ET_INTR_TXDMA_ERR) {
+ /* Following read also clears the register (COR) */
+ u32 txdma_err = readl(&iomem->txdma.tx_dma_error);
+
+ dev_warn(&adapter->pdev->dev,
+ "TXDMA_ERR interrupt, error = %d\n",
+ txdma_err);
+ }
+
+ /* Handle Free Buffer Ring 0 and 1 Low interrupt */
+ if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
+ /* This indicates the number of unused buffers in RXDMA free
+ * buffer ring 0 is <= the limit you programmed. Free buffer
+ * resources need to be returned. Free buffers are consumed as
+ * packets are passed from the network to the host. The host
+ * becomes aware of the packets from the contents of the packet
+ * status ring. This ring is queried when the packet done
+ * interrupt occurs. Packets are then passed to the OS. When
+ * the OS is done with the packets the resources can be
+ * returned to the ET1310 for re-use. This interrupt is one
+ * method of returning resources.
+ */
+
+ /* If the user has flow control on, then we will
+ * send a pause packet, otherwise just exit
+ */
+ if (adapter->flow == FLOW_TXONLY || adapter->flow == FLOW_BOTH) {
+ u32 pm_csr;
+
+ /* Tell the device to send a pause packet via the back
+ * pressure register (bp req and bp xon/xoff)
+ */
+ pm_csr = readl(&iomem->global.pm_csr);
+ if (!et1310_in_phy_coma(adapter))
+ writel(3, &iomem->txmac.bp_ctrl);
+ }
+ }
+
+ /* Handle Packet Status Ring Low Interrupt */
+ if (status & ET_INTR_RXDMA_STAT_LOW) {
+ /* Same idea as with the two Free Buffer Rings. Packets going
+ * from the network to the host each consume a free buffer
+ * resource and a packet status resource. These resources are
+ * passed to the OS. When the OS is done with the resources,
+ * they need to be returned to the ET1310. This is one method
+ * of returning the resources.
+ */
+ }
+
+ /* Handle RXDMA Error Interrupt */
+ if (status & ET_INTR_RXDMA_ERR) {
+ /* The rxdma_error interrupt is sent when a time-out on a
+ * request issued by the JAGCore has occurred or a completion is
+ * returned with an un-successful status. In both cases the
+ * request is considered complete. The JAGCore will
+ * automatically re-try the request in question. Normally
+ * information on events like these are sent to the host using
+ * the "Advanced Error Reporting" capability. This interrupt is
+ * another way of getting similar information. The only thing
+ * required is to clear the interrupt by reading the ISR in the
+ * global resources. The JAGCore will do a re-try on the
+ * request. Normally you should never see this interrupt. If
+ * you start to see this interrupt occurring frequently then
+ * something bad has occurred. A reset might be the thing to do.
+ */
+ /* TRAP();*/
+
+ dev_warn(&adapter->pdev->dev,
+ "RxDMA_ERR interrupt, error %x\n",
+ readl(&iomem->txmac.tx_test));
+ }
+
+ /* Handle the Wake on LAN Event */
+ if (status & ET_INTR_WOL) {
+ /* This is a secondary interrupt for wake on LAN. The driver
+ * should never see this, if it does, something serious is
+ * wrong. We will TRAP the message when we are in DBG mode,
+ * otherwise we will ignore it.
+ */
+ dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
+ }
+
+ /* Let's move on to the TxMac */
+ if (status & ET_INTR_TXMAC) {
+ u32 err = readl(&iomem->txmac.err);
+
+ /* When any of the errors occur and TXMAC generates an
+ * interrupt to report these errors, it usually means that
+ * TXMAC has detected an error in the data stream retrieved
+ * from the on-chip Tx Q. All of these errors are catastrophic
+ * and TXMAC won't be able to recover data when these errors
+ * occur. In a nutshell, the whole Tx path will have to be reset
+ * and re-configured afterwards.
+ */
+ dev_warn(&adapter->pdev->dev,
+ "TXMAC interrupt, error 0x%08x\n",
+ err);
+
+ /* If we are debugging, we want to see this error, otherwise we
+ * just want the device to be reset and continue
+ */
+ }
+
+ /* Handle RXMAC Interrupt */
+ if (status & ET_INTR_RXMAC) {
+ /* These interrupts are catastrophic to the device, what we need
+ * to do is disable the interrupts and set the flag to cause us
+ * to reset so we can solve this issue.
+ */
+ /* MP_SET_FLAG( adapter, FMP_ADAPTER_HARDWARE_ERROR); */
+
+ dev_warn(&adapter->pdev->dev,
+ "RXMAC interrupt, error 0x%08x. Requesting reset\n",
+ readl(&iomem->rxmac.err_reg));
+
+ dev_warn(&adapter->pdev->dev,
+ "Enable 0x%08x, Diag 0x%08x\n",
+ readl(&iomem->rxmac.ctrl),
+ readl(&iomem->rxmac.rxq_diag));
+
+ /* If we are debugging, we want to see this error, otherwise we
+ * just want the device to be reset and continue
+ */
+ }
+
+ /* Handle MAC_STAT Interrupt */
+ if (status & ET_INTR_MAC_STAT) {
+ /* This means at least one of the un-masked counters in the
+ * MAC_STAT block has rolled over. Use this to maintain the top,
+ * software managed bits of the counter(s).
+ */
+ et1310_handle_macstat_interrupt(adapter);
+ }
+
+ /* Handle SLV Timeout Interrupt */
+ if (status & ET_INTR_SLV_TIMEOUT) {
+ /* This means a timeout has occurred on a read or write request
+ * to one of the JAGCore registers. The Global Resources block
+ * has terminated the request and on a read request, returned a
+ * "fake" value. The most likely reasons are: Bad Address or the
+ * addressed module is in a power-down state and can't respond.
+ */
+ }
+
+out:
+ if (enable_interrupts)
+ et131x_enable_interrupts(adapter);
+
+ return IRQ_RETVAL(handled);
+}
+
+static int et131x_poll(struct napi_struct *napi, int budget)
+{
+ struct et131x_adapter *adapter =
+ container_of(napi, struct et131x_adapter, napi);
+ int work_done = et131x_handle_recv_pkts(adapter, budget);
+
+ et131x_handle_send_pkts(adapter);
+
+ if (work_done < budget) {
+ napi_complete(&adapter->napi);
+ et131x_enable_interrupts(adapter);
+ }
+
+ return work_done;
+}
+
+/* et131x_stats - Return the current device statistics */
+static struct net_device_stats *et131x_stats(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+ struct net_device_stats *stats = &adapter->netdev->stats;
+ struct ce_stats *devstat = &adapter->stats;
+
+ stats->rx_errors = devstat->rx_length_errs +
+ devstat->rx_align_errs +
+ devstat->rx_crc_errs +
+ devstat->rx_code_violations +
+ devstat->rx_other_errs;
+ stats->tx_errors = devstat->tx_max_pkt_errs;
+ stats->multicast = devstat->multicast_pkts_rcvd;
+ stats->collisions = devstat->tx_collisions;
+
+ stats->rx_length_errors = devstat->rx_length_errs;
+ stats->rx_over_errors = devstat->rx_overflows;
+ stats->rx_crc_errors = devstat->rx_crc_errs;
+ stats->rx_dropped = devstat->rcvd_pkts_dropped;
+
+ /* NOTE: Not used, can't find analogous statistics */
+ /* stats->rx_frame_errors = devstat->; */
+ /* stats->rx_fifo_errors = devstat->; */
+ /* stats->rx_missed_errors = devstat->; */
+
+ /* stats->tx_aborted_errors = devstat->; */
+ /* stats->tx_carrier_errors = devstat->; */
+ /* stats->tx_fifo_errors = devstat->; */
+ /* stats->tx_heartbeat_errors = devstat->; */
+ /* stats->tx_window_errors = devstat->; */
+ return stats;
+}
+
+/* et131x_open - Open the device for use. */
+static int et131x_open(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+ struct pci_dev *pdev = adapter->pdev;
+ unsigned int irq = pdev->irq;
+ int result;
+
+ /* Start the timer to track NIC errors */
+ init_timer(&adapter->error_timer);
+ adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
+ adapter->error_timer.function = et131x_error_timer_handler;
+ adapter->error_timer.data = (unsigned long)adapter;
+ add_timer(&adapter->error_timer);
+
+ result = request_irq(irq, et131x_isr,
+ IRQF_SHARED, netdev->name, netdev);
+ if (result) {
+ dev_err(&pdev->dev, "could not register IRQ %d\n", irq);
+ return result;
+ }
+
+ adapter->flags |= FMP_ADAPTER_INTERRUPT_IN_USE;
+
+ napi_enable(&adapter->napi);
+
+ et131x_up(netdev);
+
+ return result;
+}
+
+/* et131x_close - Close the device */
+static int et131x_close(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ et131x_down(netdev);
+ napi_disable(&adapter->napi);
+
+ adapter->flags &= ~FMP_ADAPTER_INTERRUPT_IN_USE;
+ free_irq(adapter->pdev->irq, netdev);
+
+ /* Stop the error timer */
+ return del_timer_sync(&adapter->error_timer);
+}
+
+/* et131x_ioctl - The I/O Control handler for the driver
+ * @netdev: device on which the control request is being made
+ * @reqbuf: a pointer to the IOCTL request buffer
+ * @cmd: the IOCTL command code
+ */
+static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf,
+ int cmd)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ if (!adapter->phydev)
+ return -EINVAL;
+
+ return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
+}
+
+/* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
+ * @adapter: pointer to our private adapter structure
+ *
+ * FIXME: lot of dups with MAC code
+ */
+static int et131x_set_packet_filter(struct et131x_adapter *adapter)
+{
+ int filter = adapter->packet_filter;
+ u32 ctrl;
+ u32 pf_ctrl;
+
+ ctrl = readl(&adapter->regs->rxmac.ctrl);
+ pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
+
+ /* Default to disabled packet filtering. Enable it in the individual
+ * case statements that require the device to filter something
+ */
+ ctrl |= 0x04;
+
+ /* Set us to be in promiscuous mode so we receive everything, this
+ * is also true when we get a packet filter of 0
+ */
+ if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
+ pf_ctrl &= ~7; /* Clear filter bits */
+ else {
+ /* Set us up with Multicast packet filtering. Three cases are
+ * possible - (1) we have a multi-cast list, (2) we receive ALL
+ * multicast entries or (3) we receive none.
+ */
+ if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
+ pf_ctrl &= ~2; /* Multicast filter bit */
+ else {
+ et1310_setup_device_for_multicast(adapter);
+ pf_ctrl |= 2;
+ ctrl &= ~0x04;
+ }
+
+ /* Set us up with Unicast packet filtering */
+ if (filter & ET131X_PACKET_TYPE_DIRECTED) {
+ et1310_setup_device_for_unicast(adapter);
+ pf_ctrl |= 4;
+ ctrl &= ~0x04;
+ }
+
+ /* Set us up with Broadcast packet filtering */
+ if (filter & ET131X_PACKET_TYPE_BROADCAST) {
+ pf_ctrl |= 1; /* Broadcast filter bit */
+ ctrl &= ~0x04;
+ } else {
+ pf_ctrl &= ~1;
+ }
+
+ /* Setup the receive mac configuration registers - Packet
+ * Filter control + the enable / disable for packet filter
+ * in the control reg.
+ */
+ writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
+ writel(ctrl, &adapter->regs->rxmac.ctrl);
+ }
+ return 0;
+}
+
+/* et131x_multicast - The handler to configure multicasting on the interface */
+static void et131x_multicast(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+ int packet_filter;
+ struct netdev_hw_addr *ha;
+ int i;
+
+ /* Before we modify the platform-independent filter flags, store them
+ * locally. This allows us to determine if anything's changed and if
+ * we even need to bother the hardware
+ */
+ packet_filter = adapter->packet_filter;
+
+ /* Clear the 'multicast' flag locally; because we only have a single
+ * flag to check multicast, and multiple multicast addresses can be
+ * set, this is the easiest way to determine if more than one
+ * multicast address is being set.
+ */
+ packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
+
+ /* Check the net_device flags and set the device independent flags
+ * accordingly
+ */
+ if (netdev->flags & IFF_PROMISC)
+ adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
+ else
+ adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
+
+ if ((netdev->flags & IFF_ALLMULTI) ||
+ (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST))
+ adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
+
+ if (netdev_mc_count(netdev) < 1) {
+ adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
+ adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
+ } else {
+ adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
+ }
+
+ /* Set values in the private adapter struct */
+ i = 0;
+ netdev_for_each_mc_addr(ha, netdev) {
+ if (i == NIC_MAX_MCAST_LIST)
+ break;
+ memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
+ }
+ adapter->multicast_addr_count = i;
+
+ /* Are the new flags different from the previous ones? If not, then no
+ * action is required
+ *
+ * NOTE - This block will always update the multicast_list with the
+ * hardware, even if the addresses aren't the same.
+ */
+ if (packet_filter != adapter->packet_filter)
+ et131x_set_packet_filter(adapter);
+}
+
+/* et131x_tx - The handler to tx a packet on the device */
+static netdev_tx_t et131x_tx(struct sk_buff *skb, struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+
+ /* stop the queue if it's getting full */
+ if (tx_ring->used >= NUM_TCB - 1 && !netif_queue_stopped(netdev))
+ netif_stop_queue(netdev);
+
+ /* Save the timestamp for the TX timeout watchdog */
+ netdev->trans_start = jiffies;
+
+ /* TCB is not available */
+ if (tx_ring->used >= NUM_TCB)
+ goto drop_err;
+
+ if ((adapter->flags & FMP_ADAPTER_FAIL_SEND_MASK) ||
+ !netif_carrier_ok(netdev))
+ goto drop_err;
+
+ if (send_packet(skb, adapter))
+ goto drop_err;
+
+ return NETDEV_TX_OK;
+
+drop_err:
+ dev_kfree_skb_any(skb);
+ adapter->netdev->stats.tx_dropped++;
+ return NETDEV_TX_OK;
+}
+
+/* et131x_tx_timeout - Timeout handler
+ *
+ * The handler called when a Tx request times out. The timeout period is
+ * specified by the 'tx_timeo" element in the net_device structure (see
+ * et131x_alloc_device() to see how this value is set).
+ */
+static void et131x_tx_timeout(struct net_device *netdev)
+{
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+ struct tx_ring *tx_ring = &adapter->tx_ring;
+ struct tcb *tcb;
+ unsigned long flags;
+
+ /* If the device is closed, ignore the timeout */
+ if (~(adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE))
+ return;
+
+ /* Any nonrecoverable hardware error?
+ * Checks adapter->flags for any failure in phy reading
+ */
+ if (adapter->flags & FMP_ADAPTER_NON_RECOVER_ERROR)
+ return;
+
+ /* Hardware failure? */
+ if (adapter->flags & FMP_ADAPTER_HARDWARE_ERROR) {
+ dev_err(&adapter->pdev->dev, "hardware error - reset\n");
+ return;
+ }
+
+ /* Is send stuck? */
+ spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
+ tcb = tx_ring->send_head;
+ spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
+
+ if (tcb) {
+ tcb->count++;
+
+ if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
+ dev_warn(&adapter->pdev->dev,
+ "Send stuck - reset. tcb->WrIndex %x\n",
+ tcb->index);
+
+ adapter->netdev->stats.tx_errors++;
+
+ /* perform reset of tx/rx */
+ et131x_disable_txrx(netdev);
+ et131x_enable_txrx(netdev);
+ }
+ }
+}
+
+/* et131x_change_mtu - The handler called to change the MTU for the device */
+static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
+{
+ int result = 0;
+ struct et131x_adapter *adapter = netdev_priv(netdev);
+
+ /* Make sure the requested MTU is valid */
+ if (new_mtu < 64 || new_mtu > 9216)
+ return -EINVAL;
+
+ et131x_disable_txrx(netdev);
+
+ /* Set the new MTU */
+ netdev->mtu = new_mtu;
+
+ /* Free Rx DMA memory */
+ et131x_adapter_memory_free(adapter);
+
+ /* Set the config parameter for Jumbo Packet support */
+ adapter->registry_jumbo_packet = new_mtu + 14;
+ et131x_soft_reset(adapter);
+
+ /* Alloc and init Rx DMA memory */
+ result = et131x_adapter_memory_alloc(adapter);
+ if (result != 0) {
+ dev_warn(&adapter->pdev->dev,
+ "Change MTU failed; couldn't re-alloc DMA memory\n");
+ return result;
+ }
+
+ et131x_init_send(adapter);
+
+ et131x_hwaddr_init(adapter);
+ memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
+
+ /* Init the device with the new settings */
+ et131x_adapter_setup(adapter);
+ et131x_enable_txrx(netdev);
+
+ return result;
+}
+
+static const struct net_device_ops et131x_netdev_ops = {
+ .ndo_open = et131x_open,
+ .ndo_stop = et131x_close,
+ .ndo_start_xmit = et131x_tx,
+ .ndo_set_rx_mode = et131x_multicast,
+ .ndo_tx_timeout = et131x_tx_timeout,
+ .ndo_change_mtu = et131x_change_mtu,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_get_stats = et131x_stats,
+ .ndo_do_ioctl = et131x_ioctl,
+};
+
+/* et131x_pci_setup - Perform device initialization
+ * @pdev: a pointer to the device's pci_dev structure
+ * @ent: this device's entry in the pci_device_id table
+ *
+ * Registered in the pci_driver structure, this function is called when the
+ * PCI subsystem finds a new PCI device which matches the information
+ * contained in the pci_device_id table. This routine is the equivalent to
+ * a device insertion routine.
+ */
+static int et131x_pci_setup(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ struct net_device *netdev;
+ struct et131x_adapter *adapter;
+ int rc;
+ int ii;
+
+ rc = pci_enable_device(pdev);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "pci_enable_device() failed\n");
+ goto out;
+ }
+
+ /* Perform some basic PCI checks */
+ if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
+ dev_err(&pdev->dev, "Can't find PCI device's base address\n");
+ rc = -ENODEV;
+ goto err_disable;
+ }
+
+ rc = pci_request_regions(pdev, DRIVER_NAME);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "Can't get PCI resources\n");
+ goto err_disable;
+ }
+
+ pci_set_master(pdev);
+
+ /* Check the DMA addressing support of this device */
+ if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
+ dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
+ dev_err(&pdev->dev, "No usable DMA addressing method\n");
+ rc = -EIO;
+ goto err_release_res;
+ }
+
+ /* Allocate netdev and private adapter structs */
+ netdev = alloc_etherdev(sizeof(struct et131x_adapter));
+ if (!netdev) {
+ dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
+ rc = -ENOMEM;
+ goto err_release_res;
+ }
+
+ netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
+ netdev->netdev_ops = &et131x_netdev_ops;
+
+ SET_NETDEV_DEV(netdev, &pdev->dev);
+ netdev->ethtool_ops = &et131x_ethtool_ops;
+
+ adapter = et131x_adapter_init(netdev, pdev);
+
+ rc = et131x_pci_init(adapter, pdev);
+ if (rc < 0)
+ goto err_free_dev;
+
+ /* Map the bus-relative registers to system virtual memory */
+ adapter->regs = pci_ioremap_bar(pdev, 0);
+ if (!adapter->regs) {
+ dev_err(&pdev->dev, "Cannot map device registers\n");
+ rc = -ENOMEM;
+ goto err_free_dev;
+ }
+
+ /* If Phy COMA mode was enabled when we went down, disable it here. */
+ writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
+
+ /* Issue a global reset to the et1310 */
+ et131x_soft_reset(adapter);
+
+ /* Disable all interrupts (paranoid) */
+ et131x_disable_interrupts(adapter);
+
+ /* Allocate DMA memory */
+ rc = et131x_adapter_memory_alloc(adapter);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "Could not alloc adapter memory (DMA)\n");
+ goto err_iounmap;
+ }
+
+ /* Init send data structures */
+ et131x_init_send(adapter);
+
+ netif_napi_add(netdev, &adapter->napi, et131x_poll, 64);
+
+ /* Copy address into the net_device struct */
+ memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
+
+ rc = -ENOMEM;
+
+ /* Setup the mii_bus struct */
+ adapter->mii_bus = mdiobus_alloc();
+ if (!adapter->mii_bus) {
+ dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
+ goto err_mem_free;
+ }
+
+ adapter->mii_bus->name = "et131x_eth_mii";
+ snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
+ (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
+ adapter->mii_bus->priv = netdev;
+ adapter->mii_bus->read = et131x_mdio_read;
+ adapter->mii_bus->write = et131x_mdio_write;
+ adapter->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int),
+ GFP_KERNEL);
+ if (!adapter->mii_bus->irq)
+ goto err_mdio_free;
+
+ for (ii = 0; ii < PHY_MAX_ADDR; ii++)
+ adapter->mii_bus->irq[ii] = PHY_POLL;
+
+ rc = mdiobus_register(adapter->mii_bus);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "failed to register MII bus\n");
+ goto err_mdio_free_irq;
+ }
+
+ rc = et131x_mii_probe(netdev);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "failed to probe MII bus\n");
+ goto err_mdio_unregister;
+ }
+
+ /* Setup et1310 as per the documentation */
+ et131x_adapter_setup(adapter);
+
+ /* Init variable for counting how long we do not have link status */
+ adapter->boot_coma = 0;
+ et1310_disable_phy_coma(adapter);
+
+ /* We can enable interrupts now
+ *
+ * NOTE - Because registration of interrupt handler is done in the
+ * device's open(), defer enabling device interrupts to that
+ * point
+ */
+
+ /* Register the net_device struct with the Linux network layer */
+ rc = register_netdev(netdev);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "register_netdev() failed\n");
+ goto err_phy_disconnect;
+ }
+
+ /* Register the net_device struct with the PCI subsystem. Save a copy
+ * of the PCI config space for this device now that the device has
+ * been initialized, just in case it needs to be quickly restored.
+ */
+ pci_set_drvdata(pdev, netdev);
+out:
+ return rc;
+
+err_phy_disconnect:
+ phy_disconnect(adapter->phydev);
+err_mdio_unregister:
+ mdiobus_unregister(adapter->mii_bus);
+err_mdio_free_irq:
+ kfree(adapter->mii_bus->irq);
+err_mdio_free:
+ mdiobus_free(adapter->mii_bus);
+err_mem_free:
+ et131x_adapter_memory_free(adapter);
+err_iounmap:
+ iounmap(adapter->regs);
+err_free_dev:
+ pci_dev_put(pdev);
+ free_netdev(netdev);
+err_release_res:
+ pci_release_regions(pdev);
+err_disable:
+ pci_disable_device(pdev);
+ goto out;
+}
+
+static const struct pci_device_id et131x_pci_table[] = {
+ { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
+ { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
+ {0,}
+};
+MODULE_DEVICE_TABLE(pci, et131x_pci_table);
+
+static struct pci_driver et131x_driver = {
+ .name = DRIVER_NAME,
+ .id_table = et131x_pci_table,
+ .probe = et131x_pci_setup,
+ .remove = et131x_pci_remove,
+ .driver.pm = ET131X_PM_OPS,
+};
+
+module_pci_driver(et131x_driver);
diff --git a/drivers/net/ethernet/agere/et131x.h b/drivers/net/ethernet/agere/et131x.h
new file mode 100644
index 0000000..0727523
--- /dev/null
+++ b/drivers/net/ethernet/agere/et131x.h
@@ -0,0 +1,1533 @@
+/*
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ * http://www.agere.com
+ *
+ * SOFTWARE LICENSE
+ *
+ * This software is provided subject to the following terms and conditions,
+ * which you should read carefully before using the software. Using this
+ * software indicates your acceptance of these terms and conditions. If you do
+ * not agree with these terms and conditions, do not use the software.
+ *
+ * Copyright © 2005 Agere Systems Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source or binary forms, with or without
+ * modifications, are permitted provided that the following conditions are met:
+ *
+ * . Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following Disclaimer as comments in the code as
+ * well as in the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * . Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following Disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * . Neither the name of Agere Systems Inc. nor the names of the contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * Disclaimer
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
+ * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
+ * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ */
+
+#define DRIVER_NAME "et131x"
+#define DRIVER_VERSION "v2.0"
+
+/* EEPROM registers */
+
+/* LBCIF Register Groups (addressed via 32-bit offsets) */
+#define LBCIF_DWORD0_GROUP 0xAC
+#define LBCIF_DWORD1_GROUP 0xB0
+
+/* LBCIF Registers (addressed via 8-bit offsets) */
+#define LBCIF_ADDRESS_REGISTER 0xAC
+#define LBCIF_DATA_REGISTER 0xB0
+#define LBCIF_CONTROL_REGISTER 0xB1
+#define LBCIF_STATUS_REGISTER 0xB2
+
+/* LBCIF Control Register Bits */
+#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
+#define LBCIF_CONTROL_PAGE_WRITE 0x02
+#define LBCIF_CONTROL_EEPROM_RELOAD 0x08
+#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
+#define LBCIF_CONTROL_I2C_WRITE 0x40
+#define LBCIF_CONTROL_LBCIF_ENABLE 0x80
+
+/* LBCIF Status Register Bits */
+#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
+#define LBCIF_STATUS_I2C_IDLE 0x02
+#define LBCIF_STATUS_ACK_ERROR 0x04
+#define LBCIF_STATUS_GENERAL_ERROR 0x08
+#define LBCIF_STATUS_CHECKSUM_ERROR 0x40
+#define LBCIF_STATUS_EEPROM_PRESENT 0x80
+
+/* START OF GLOBAL REGISTER ADDRESS MAP */
+/*
+ * 10bit registers
+ *
+ * Tx queue start address reg in global address map at address 0x0000
+ * tx queue end address reg in global address map at address 0x0004
+ * rx queue start address reg in global address map at address 0x0008
+ * rx queue end address reg in global address map at address 0x000C
+ */
+
+/*
+ * structure for power management control status reg in global address map
+ * located at address 0x0010
+ * jagcore_rx_rdy bit 9
+ * jagcore_tx_rdy bit 8
+ * phy_lped_en bit 7
+ * phy_sw_coma bit 6
+ * rxclk_gate bit 5
+ * txclk_gate bit 4
+ * sysclk_gate bit 3
+ * jagcore_rx_en bit 2
+ * jagcore_tx_en bit 1
+ * gigephy_en bit 0
+ */
+#define ET_PM_PHY_SW_COMA 0x40
+#define ET_PMCSR_INIT 0x38
+
+/*
+ * Interrupt status reg at address 0x0018
+ */
+#define ET_INTR_TXDMA_ISR 0x00000008
+#define ET_INTR_TXDMA_ERR 0x00000010
+#define ET_INTR_RXDMA_XFR_DONE 0x00000020
+#define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
+#define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
+#define ET_INTR_RXDMA_STAT_LOW 0x00000100
+#define ET_INTR_RXDMA_ERR 0x00000200
+#define ET_INTR_WATCHDOG 0x00004000
+#define ET_INTR_WOL 0x00008000
+#define ET_INTR_PHY 0x00010000
+#define ET_INTR_TXMAC 0x00020000
+#define ET_INTR_RXMAC 0x00040000
+#define ET_INTR_MAC_STAT 0x00080000
+#define ET_INTR_SLV_TIMEOUT 0x00100000
+
+/*
+ * Interrupt mask register at address 0x001C
+ * Interrupt alias clear mask reg at address 0x0020
+ * Interrupt status alias reg at address 0x0024
+ *
+ * Same masks as above
+ */
+
+/*
+ * Software reset reg at address 0x0028
+ * 0: txdma_sw_reset
+ * 1: rxdma_sw_reset
+ * 2: txmac_sw_reset
+ * 3: rxmac_sw_reset
+ * 4: mac_sw_reset
+ * 5: mac_stat_sw_reset
+ * 6: mmc_sw_reset
+ *31: selfclr_disable
+ */
+#define ET_RESET_ALL 0x007F
+
+/*
+ * SLV Timer reg at address 0x002C (low 24 bits)
+ */
+
+/*
+ * MSI Configuration reg at address 0x0030
+ */
+#define ET_MSI_VECTOR 0x0000001F
+#define ET_MSI_TC 0x00070000
+
+/*
+ * Loopback reg located at address 0x0034
+ */
+#define ET_LOOP_MAC 0x00000001
+#define ET_LOOP_DMA 0x00000002
+
+/*
+ * GLOBAL Module of JAGCore Address Mapping
+ * Located at address 0x0000
+ */
+struct global_regs { /* Location: */
+ u32 txq_start_addr; /* 0x0000 */
+ u32 txq_end_addr; /* 0x0004 */
+ u32 rxq_start_addr; /* 0x0008 */
+ u32 rxq_end_addr; /* 0x000C */
+ u32 pm_csr; /* 0x0010 */
+ u32 unused; /* 0x0014 */
+ u32 int_status; /* 0x0018 */
+ u32 int_mask; /* 0x001C */
+ u32 int_alias_clr_en; /* 0x0020 */
+ u32 int_status_alias; /* 0x0024 */
+ u32 sw_reset; /* 0x0028 */
+ u32 slv_timer; /* 0x002C */
+ u32 msi_config; /* 0x0030 */
+ u32 loopback; /* 0x0034 */
+ u32 watchdog_timer; /* 0x0038 */
+};
+
+/* START OF TXDMA REGISTER ADDRESS MAP */
+/*
+ * txdma control status reg at address 0x1000
+ */
+#define ET_TXDMA_CSR_HALT 0x00000001
+#define ET_TXDMA_DROP_TLP 0x00000002
+#define ET_TXDMA_CACHE_THRS 0x000000F0
+#define ET_TXDMA_CACHE_SHIFT 4
+#define ET_TXDMA_SNGL_EPKT 0x00000100
+#define ET_TXDMA_CLASS 0x00001E00
+
+/*
+ * structure for txdma packet ring base address hi reg in txdma address map
+ * located at address 0x1004
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for txdma packet ring base address low reg in txdma address map
+ * located at address 0x1008
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for txdma packet ring number of descriptor reg in txdma address
+ * map. Located at address 0x100C
+ *
+ * 31-10: unused
+ * 9-0: pr ndes
+ */
+#define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
+#define ET_DMA12_WRAP 0x1000
+#define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
+#define ET_DMA10_WRAP 0x0400
+#define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
+#define ET_DMA4_WRAP 0x0010
+
+#define INDEX12(x) ((x) & ET_DMA12_MASK)
+#define INDEX10(x) ((x) & ET_DMA10_MASK)
+#define INDEX4(x) ((x) & ET_DMA4_MASK)
+
+/*
+ * 10bit DMA with wrap
+ * txdma tx queue write address reg in txdma address map at 0x1010
+ * txdma tx queue write address external reg in txdma address map at 0x1014
+ * txdma tx queue read address reg in txdma address map at 0x1018
+ *
+ * u32
+ * txdma status writeback address hi reg in txdma address map at0x101C
+ * txdma status writeback address lo reg in txdma address map at 0x1020
+ *
+ * 10bit DMA with wrap
+ * txdma service request reg in txdma address map at 0x1024
+ * structure for txdma service complete reg in txdma address map at 0x1028
+ *
+ * 4bit DMA with wrap
+ * txdma tx descriptor cache read index reg in txdma address map at 0x102C
+ * txdma tx descriptor cache write index reg in txdma address map at 0x1030
+ *
+ * txdma error reg in txdma address map at address 0x1034
+ * 0: PyldResend
+ * 1: PyldRewind
+ * 4: DescrResend
+ * 5: DescrRewind
+ * 8: WrbkResend
+ * 9: WrbkRewind
+ */
+
+/*
+ * Tx DMA Module of JAGCore Address Mapping
+ * Located at address 0x1000
+ */
+struct txdma_regs { /* Location: */
+ u32 csr; /* 0x1000 */
+ u32 pr_base_hi; /* 0x1004 */
+ u32 pr_base_lo; /* 0x1008 */
+ u32 pr_num_des; /* 0x100C */
+ u32 txq_wr_addr; /* 0x1010 */
+ u32 txq_wr_addr_ext; /* 0x1014 */
+ u32 txq_rd_addr; /* 0x1018 */
+ u32 dma_wb_base_hi; /* 0x101C */
+ u32 dma_wb_base_lo; /* 0x1020 */
+ u32 service_request; /* 0x1024 */
+ u32 service_complete; /* 0x1028 */
+ u32 cache_rd_index; /* 0x102C */
+ u32 cache_wr_index; /* 0x1030 */
+ u32 tx_dma_error; /* 0x1034 */
+ u32 desc_abort_cnt; /* 0x1038 */
+ u32 payload_abort_cnt; /* 0x103c */
+ u32 writeback_abort_cnt; /* 0x1040 */
+ u32 desc_timeout_cnt; /* 0x1044 */
+ u32 payload_timeout_cnt; /* 0x1048 */
+ u32 writeback_timeout_cnt; /* 0x104c */
+ u32 desc_error_cnt; /* 0x1050 */
+ u32 payload_error_cnt; /* 0x1054 */
+ u32 writeback_error_cnt; /* 0x1058 */
+ u32 dropped_tlp_cnt; /* 0x105c */
+ u32 new_service_complete; /* 0x1060 */
+ u32 ethernet_packet_cnt; /* 0x1064 */
+};
+
+/* END OF TXDMA REGISTER ADDRESS MAP */
+
+/* START OF RXDMA REGISTER ADDRESS MAP */
+/*
+ * structure for control status reg in rxdma address map
+ * Located at address 0x2000
+ *
+ * CSR
+ * 0: halt
+ * 1-3: tc
+ * 4: fbr_big_endian
+ * 5: psr_big_endian
+ * 6: pkt_big_endian
+ * 7: dma_big_endian
+ * 8-9: fbr0_size
+ * 10: fbr0_enable
+ * 11-12: fbr1_size
+ * 13: fbr1_enable
+ * 14: unused
+ * 15: pkt_drop_disable
+ * 16: pkt_done_flush
+ * 17: halt_status
+ * 18-31: unused
+ */
+#define ET_RXDMA_CSR_HALT 0x0001
+#define ET_RXDMA_CSR_FBR0_SIZE_LO 0x0100
+#define ET_RXDMA_CSR_FBR0_SIZE_HI 0x0200
+#define ET_RXDMA_CSR_FBR0_ENABLE 0x0400
+#define ET_RXDMA_CSR_FBR1_SIZE_LO 0x0800
+#define ET_RXDMA_CSR_FBR1_SIZE_HI 0x1000
+#define ET_RXDMA_CSR_FBR1_ENABLE 0x2000
+#define ET_RXDMA_CSR_HALT_STATUS 0x00020000
+
+/*
+ * structure for dma writeback lo reg in rxdma address map
+ * located at address 0x2004
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for dma writeback hi reg in rxdma address map
+ * located at address 0x2008
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for number of packets done reg in rxdma address map
+ * located at address 0x200C
+ *
+ * 31-8: unused
+ * 7-0: num done
+ */
+
+/*
+ * structure for max packet time reg in rxdma address map
+ * located at address 0x2010
+ *
+ * 31-18: unused
+ * 17-0: time done
+ */
+
+/*
+ * structure for rx queue read address reg in rxdma address map
+ * located at address 0x2014
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for rx queue read address external reg in rxdma address map
+ * located at address 0x2018
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for rx queue write address reg in rxdma address map
+ * located at address 0x201C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring base address lo reg in rxdma address map
+ * located at address 0x2020
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring base address hi reg in rxdma address map
+ * located at address 0x2024
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for packet status ring number of descriptors reg in rxdma address
+ * map. Located at address 0x2028
+ *
+ * 31-12: unused
+ * 11-0: psr ndes
+ */
+#define ET_RXDMA_PSR_NUM_DES_MASK 0xFFF
+
+/*
+ * structure for packet status ring available offset reg in rxdma address map
+ * located at address 0x202C
+ *
+ * 31-13: unused
+ * 12: psr avail wrap
+ * 11-0: psr avail
+ */
+
+/*
+ * structure for packet status ring full offset reg in rxdma address map
+ * located at address 0x2030
+ *
+ * 31-13: unused
+ * 12: psr full wrap
+ * 11-0: psr full
+ */
+
+/*
+ * structure for packet status ring access index reg in rxdma address map
+ * located at address 0x2034
+ *
+ * 31-5: unused
+ * 4-0: psr_ai
+ */
+
+/*
+ * structure for packet status ring minimum descriptors reg in rxdma address
+ * map. Located at address 0x2038
+ *
+ * 31-12: unused
+ * 11-0: psr_min
+ */
+
+/*
+ * structure for free buffer ring base lo address reg in rxdma address map
+ * located at address 0x203C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring base hi address reg in rxdma address map
+ * located at address 0x2040
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring number of descriptors reg in rxdma address
+ * map. Located at address 0x2044
+ *
+ * 31-10: unused
+ * 9-0: fbr ndesc
+ */
+
+/*
+ * structure for free buffer ring 0 available offset reg in rxdma address map
+ * located at address 0x2048
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer ring 0 full offset reg in rxdma address map
+ * located at address 0x204C
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for free buffer cache 0 full offset reg in rxdma address map
+ * located at address 0x2050
+ *
+ * 31-5: unused
+ * 4-0: fbc rdi
+ */
+
+/*
+ * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
+ * located at address 0x2054
+ *
+ * 31-10: unused
+ * 9-0: fbr min
+ */
+
+/*
+ * structure for free buffer ring 1 base address lo reg in rxdma address map
+ * located at address 0x2058 - 0x205C
+ * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
+ */
+
+/*
+ * structure for free buffer ring 1 number of descriptors reg in rxdma address
+ * map. Located at address 0x2060
+ * Defined earlier (RXDMA_FBR_NUM_DES_t)
+ */
+
+/*
+ * structure for free buffer ring 1 available offset reg in rxdma address map
+ * located at address 0x2064
+ * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
+ */
+
+/*
+ * structure for free buffer ring 1 full offset reg in rxdma address map
+ * located at address 0x2068
+ * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
+ */
+
+/*
+ * structure for free buffer cache 1 read index reg in rxdma address map
+ * located at address 0x206C
+ * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
+ */
+
+/*
+ * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
+ * located at address 0x2070
+ * Defined Earlier (RXDMA_FBR_MIN_DES_t)
+ */
+
+/*
+ * Rx DMA Module of JAGCore Address Mapping
+ * Located at address 0x2000
+ */
+struct rxdma_regs { /* Location: */
+ u32 csr; /* 0x2000 */
+ u32 dma_wb_base_lo; /* 0x2004 */
+ u32 dma_wb_base_hi; /* 0x2008 */
+ u32 num_pkt_done; /* 0x200C */
+ u32 max_pkt_time; /* 0x2010 */
+ u32 rxq_rd_addr; /* 0x2014 */
+ u32 rxq_rd_addr_ext; /* 0x2018 */
+ u32 rxq_wr_addr; /* 0x201C */
+ u32 psr_base_lo; /* 0x2020 */
+ u32 psr_base_hi; /* 0x2024 */
+ u32 psr_num_des; /* 0x2028 */
+ u32 psr_avail_offset; /* 0x202C */
+ u32 psr_full_offset; /* 0x2030 */
+ u32 psr_access_index; /* 0x2034 */
+ u32 psr_min_des; /* 0x2038 */
+ u32 fbr0_base_lo; /* 0x203C */
+ u32 fbr0_base_hi; /* 0x2040 */
+ u32 fbr0_num_des; /* 0x2044 */
+ u32 fbr0_avail_offset; /* 0x2048 */
+ u32 fbr0_full_offset; /* 0x204C */
+ u32 fbr0_rd_index; /* 0x2050 */
+ u32 fbr0_min_des; /* 0x2054 */
+ u32 fbr1_base_lo; /* 0x2058 */
+ u32 fbr1_base_hi; /* 0x205C */
+ u32 fbr1_num_des; /* 0x2060 */
+ u32 fbr1_avail_offset; /* 0x2064 */
+ u32 fbr1_full_offset; /* 0x2068 */
+ u32 fbr1_rd_index; /* 0x206C */
+ u32 fbr1_min_des; /* 0x2070 */
+};
+
+/* END OF RXDMA REGISTER ADDRESS MAP */
+
+/* START OF TXMAC REGISTER ADDRESS MAP */
+/*
+ * structure for control reg in txmac address map
+ * located at address 0x3000
+ *
+ * bits
+ * 31-8: unused
+ * 7: cklseg_disable
+ * 6: ckbcnt_disable
+ * 5: cksegnum
+ * 4: async_disable
+ * 3: fc_disable
+ * 2: mcif_disable
+ * 1: mif_disable
+ * 0: txmac_en
+ */
+#define ET_TX_CTRL_FC_DISABLE 0x0008
+#define ET_TX_CTRL_TXMAC_ENABLE 0x0001
+
+/*
+ * structure for shadow pointer reg in txmac address map
+ * located at address 0x3004
+ * 31-27: reserved
+ * 26-16: txq rd ptr
+ * 15-11: reserved
+ * 10-0: txq wr ptr
+ */
+
+/*
+ * structure for error count reg in txmac address map
+ * located at address 0x3008
+ *
+ * 31-12: unused
+ * 11-8: reserved
+ * 7-4: txq_underrun
+ * 3-0: fifo_underrun
+ */
+
+/*
+ * structure for max fill reg in txmac address map
+ * located at address 0x300C
+ * 31-12: unused
+ * 11-0: max fill
+ */
+
+/*
+ * structure for cf parameter reg in txmac address map
+ * located at address 0x3010
+ * 31-16: cfep
+ * 15-0: cfpt
+ */
+
+/*
+ * structure for tx test reg in txmac address map
+ * located at address 0x3014
+ * 31-17: unused
+ * 16: reserved
+ * 15: txtest_en
+ * 14-11: unused
+ * 10-0: txq test pointer
+ */
+
+/*
+ * structure for error reg in txmac address map
+ * located at address 0x3018
+ *
+ * 31-9: unused
+ * 8: fifo_underrun
+ * 7-6: unused
+ * 5: ctrl2_err
+ * 4: txq_underrun
+ * 3: bcnt_err
+ * 2: lseg_err
+ * 1: segnum_err
+ * 0: seg0_err
+ */
+
+/*
+ * structure for error interrupt reg in txmac address map
+ * located at address 0x301C
+ *
+ * 31-9: unused
+ * 8: fifo_underrun
+ * 7-6: unused
+ * 5: ctrl2_err
+ * 4: txq_underrun
+ * 3: bcnt_err
+ * 2: lseg_err
+ * 1: segnum_err
+ * 0: seg0_err
+ */
+
+/*
+ * structure for error interrupt reg in txmac address map
+ * located at address 0x3020
+ *
+ * 31-2: unused
+ * 1: bp_req
+ * 0: bp_xonxoff
+ */
+
+/*
+ * Tx MAC Module of JAGCore Address Mapping
+ */
+struct txmac_regs { /* Location: */
+ u32 ctl; /* 0x3000 */
+ u32 shadow_ptr; /* 0x3004 */
+ u32 err_cnt; /* 0x3008 */
+ u32 max_fill; /* 0x300C */
+ u32 cf_param; /* 0x3010 */
+ u32 tx_test; /* 0x3014 */
+ u32 err; /* 0x3018 */
+ u32 err_int; /* 0x301C */
+ u32 bp_ctrl; /* 0x3020 */
+};
+
+/* END OF TXMAC REGISTER ADDRESS MAP */
+
+/* START OF RXMAC REGISTER ADDRESS MAP */
+
+/*
+ * structure for rxmac control reg in rxmac address map
+ * located at address 0x4000
+ *
+ * 31-7: reserved
+ * 6: rxmac_int_disable
+ * 5: async_disable
+ * 4: mif_disable
+ * 3: wol_disable
+ * 2: pkt_filter_disable
+ * 1: mcif_disable
+ * 0: rxmac_en
+ */
+#define ET_RX_CTRL_WOL_DISABLE 0x0008
+#define ET_RX_CTRL_RXMAC_ENABLE 0x0001
+
+/*
+ * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
+ * located at address 0x4004
+ * 31-16: crc
+ * 15-12: reserved
+ * 11: ignore_pp
+ * 10: ignore_mp
+ * 9: clr_intr
+ * 8: ignore_link_chg
+ * 7: ignore_uni
+ * 6: ignore_multi
+ * 5: ignore_broad
+ * 4-0: valid_crc 4-0
+ */
+
+/*
+ * structure for CRC 1 and CRC 2 reg in rxmac address map
+ * located at address 0x4008
+ *
+ * 31-16: crc2
+ * 15-0: crc1
+ */
+
+/*
+ * structure for CRC 3 and CRC 4 reg in rxmac address map
+ * located at address 0x400C
+ *
+ * 31-16: crc4
+ * 15-0: crc3
+ */
+
+/*
+ * structure for Wake On Lan Source Address Lo reg in rxmac address map
+ * located at address 0x4010
+ *
+ * 31-24: sa3
+ * 23-16: sa4
+ * 15-8: sa5
+ * 7-0: sa6
+ */
+#define ET_RX_WOL_LO_SA3_SHIFT 24
+#define ET_RX_WOL_LO_SA4_SHIFT 16
+#define ET_RX_WOL_LO_SA5_SHIFT 8
+
+/*
+ * structure for Wake On Lan Source Address Hi reg in rxmac address map
+ * located at address 0x4014
+ *
+ * 31-16: reserved
+ * 15-8: sa1
+ * 7-0: sa2
+ */
+#define ET_RX_WOL_HI_SA1_SHIFT 8
+
+/*
+ * structure for Wake On Lan mask reg in rxmac address map
+ * located at address 0x4018 - 0x4064
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Unicast Packet Filter Address 1 reg in rxmac address map
+ * located at address 0x4068
+ *
+ * 31-24: addr1_3
+ * 23-16: addr1_4
+ * 15-8: addr1_5
+ * 7-0: addr1_6
+ */
+#define ET_RX_UNI_PF_ADDR1_3_SHIFT 24
+#define ET_RX_UNI_PF_ADDR1_4_SHIFT 16
+#define ET_RX_UNI_PF_ADDR1_5_SHIFT 8
+
+/*
+ * structure for Unicast Packet Filter Address 2 reg in rxmac address map
+ * located at address 0x406C
+ *
+ * 31-24: addr2_3
+ * 23-16: addr2_4
+ * 15-8: addr2_5
+ * 7-0: addr2_6
+ */
+#define ET_RX_UNI_PF_ADDR2_3_SHIFT 24
+#define ET_RX_UNI_PF_ADDR2_4_SHIFT 16
+#define ET_RX_UNI_PF_ADDR2_5_SHIFT 8
+
+/*
+ * structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map
+ * located at address 0x4070
+ *
+ * 31-24: addr2_1
+ * 23-16: addr2_2
+ * 15-8: addr1_1
+ * 7-0: addr1_2
+ */
+#define ET_RX_UNI_PF_ADDR2_1_SHIFT 24
+#define ET_RX_UNI_PF_ADDR2_2_SHIFT 16
+#define ET_RX_UNI_PF_ADDR1_1_SHIFT 8
+
+/*
+ * structure for Multicast Hash reg in rxmac address map
+ * located at address 0x4074 - 0x4080
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Packet Filter Control reg in rxmac address map
+ * located at address 0x4084
+ *
+ * 31-23: unused
+ * 22-16: min_pkt_size
+ * 15-4: unused
+ * 3: filter_frag_en
+ * 2: filter_uni_en
+ * 1: filter_multi_en
+ * 0: filter_broad_en
+ */
+#define ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT 16
+#define ET_RX_PFCTRL_FRAG_FILTER_ENABLE 0x0008
+#define ET_RX_PFCTRL_UNICST_FILTER_ENABLE 0x0004
+#define ET_RX_PFCTRL_MLTCST_FILTER_ENABLE 0x0002
+#define ET_RX_PFCTRL_BRDCST_FILTER_ENABLE 0x0001
+
+/*
+ * structure for Memory Controller Interface Control Max Segment reg in rxmac
+ * address map. Located at address 0x4088
+ *
+ * 31-10: reserved
+ * 9-2: max_size
+ * 1: fc_en
+ * 0: seg_en
+ */
+#define ET_RX_MCIF_CTRL_MAX_SEG_SIZE_SHIFT 2
+#define ET_RX_MCIF_CTRL_MAX_SEG_FC_ENABLE 0x0002
+#define ET_RX_MCIF_CTRL_MAX_SEG_ENABLE 0x0001
+
+/*
+ * structure for Memory Controller Interface Water Mark reg in rxmac address
+ * map. Located at address 0x408C
+ *
+ * 31-26: unused
+ * 25-16: mark_hi
+ * 15-10: unused
+ * 9-0: mark_lo
+ */
+
+/*
+ * structure for Rx Queue Dialog reg in rxmac address map.
+ * located at address 0x4090
+ *
+ * 31-26: reserved
+ * 25-16: rd_ptr
+ * 15-10: reserved
+ * 9-0: wr_ptr
+ */
+
+/*
+ * structure for space available reg in rxmac address map.
+ * located at address 0x4094
+ *
+ * 31-17: reserved
+ * 16: space_avail_en
+ * 15-10: reserved
+ * 9-0: space_avail
+ */
+
+/*
+ * structure for management interface reg in rxmac address map.
+ * located at address 0x4098
+ *
+ * 31-18: reserved
+ * 17: drop_pkt_en
+ * 16-0: drop_pkt_mask
+ */
+
+/*
+ * structure for Error reg in rxmac address map.
+ * located at address 0x409C
+ *
+ * 31-4: unused
+ * 3: mif
+ * 2: async
+ * 1: pkt_filter
+ * 0: mcif
+ */
+
+/*
+ * Rx MAC Module of JAGCore Address Mapping
+ */
+struct rxmac_regs { /* Location: */
+ u32 ctrl; /* 0x4000 */
+ u32 crc0; /* 0x4004 */
+ u32 crc12; /* 0x4008 */
+ u32 crc34; /* 0x400C */
+ u32 sa_lo; /* 0x4010 */
+ u32 sa_hi; /* 0x4014 */
+ u32 mask0_word0; /* 0x4018 */
+ u32 mask0_word1; /* 0x401C */
+ u32 mask0_word2; /* 0x4020 */
+ u32 mask0_word3; /* 0x4024 */
+ u32 mask1_word0; /* 0x4028 */
+ u32 mask1_word1; /* 0x402C */
+ u32 mask1_word2; /* 0x4030 */
+ u32 mask1_word3; /* 0x4034 */
+ u32 mask2_word0; /* 0x4038 */
+ u32 mask2_word1; /* 0x403C */
+ u32 mask2_word2; /* 0x4040 */
+ u32 mask2_word3; /* 0x4044 */
+ u32 mask3_word0; /* 0x4048 */
+ u32 mask3_word1; /* 0x404C */
+ u32 mask3_word2; /* 0x4050 */
+ u32 mask3_word3; /* 0x4054 */
+ u32 mask4_word0; /* 0x4058 */
+ u32 mask4_word1; /* 0x405C */
+ u32 mask4_word2; /* 0x4060 */
+ u32 mask4_word3; /* 0x4064 */
+ u32 uni_pf_addr1; /* 0x4068 */
+ u32 uni_pf_addr2; /* 0x406C */
+ u32 uni_pf_addr3; /* 0x4070 */
+ u32 multi_hash1; /* 0x4074 */
+ u32 multi_hash2; /* 0x4078 */
+ u32 multi_hash3; /* 0x407C */
+ u32 multi_hash4; /* 0x4080 */
+ u32 pf_ctrl; /* 0x4084 */
+ u32 mcif_ctrl_max_seg; /* 0x4088 */
+ u32 mcif_water_mark; /* 0x408C */
+ u32 rxq_diag; /* 0x4090 */
+ u32 space_avail; /* 0x4094 */
+
+ u32 mif_ctrl; /* 0x4098 */
+ u32 err_reg; /* 0x409C */
+};
+
+/* END OF RXMAC REGISTER ADDRESS MAP */
+
+/* START OF MAC REGISTER ADDRESS MAP */
+/*
+ * structure for configuration #1 reg in mac address map.
+ * located at address 0x5000
+ *
+ * 31: soft reset
+ * 30: sim reset
+ * 29-20: reserved
+ * 19: reset rx mc
+ * 18: reset tx mc
+ * 17: reset rx func
+ * 16: reset tx fnc
+ * 15-9: reserved
+ * 8: loopback
+ * 7-6: reserved
+ * 5: rx flow
+ * 4: tx flow
+ * 3: syncd rx en
+ * 2: rx enable
+ * 1: syncd tx en
+ * 0: tx enable
+ */
+#define ET_MAC_CFG1_SOFT_RESET 0x80000000
+#define ET_MAC_CFG1_SIM_RESET 0x40000000
+#define ET_MAC_CFG1_RESET_RXMC 0x00080000
+#define ET_MAC_CFG1_RESET_TXMC 0x00040000
+#define ET_MAC_CFG1_RESET_RXFUNC 0x00020000
+#define ET_MAC_CFG1_RESET_TXFUNC 0x00010000
+#define ET_MAC_CFG1_LOOPBACK 0x00000100
+#define ET_MAC_CFG1_RX_FLOW 0x00000020
+#define ET_MAC_CFG1_TX_FLOW 0x00000010
+#define ET_MAC_CFG1_RX_ENABLE 0x00000004
+#define ET_MAC_CFG1_TX_ENABLE 0x00000001
+#define ET_MAC_CFG1_WAIT 0x0000000A /* RX & TX syncd */
+
+/*
+ * structure for configuration #2 reg in mac address map.
+ * located at address 0x5004
+ * 31-16: reserved
+ * 15-12: preamble
+ * 11-10: reserved
+ * 9-8: if mode
+ * 7-6: reserved
+ * 5: huge frame
+ * 4: length check
+ * 3: undefined
+ * 2: pad crc
+ * 1: crc enable
+ * 0: full duplex
+ */
+#define ET_MAC_CFG2_PREAMBLE_SHIFT 12
+#define ET_MAC_CFG2_IFMODE_MASK 0x0300
+#define ET_MAC_CFG2_IFMODE_1000 0x0200
+#define ET_MAC_CFG2_IFMODE_100 0x0100
+#define ET_MAC_CFG2_IFMODE_HUGE_FRAME 0x0020
+#define ET_MAC_CFG2_IFMODE_LEN_CHECK 0x0010
+#define ET_MAC_CFG2_IFMODE_PAD_CRC 0x0004
+#define ET_MAC_CFG2_IFMODE_CRC_ENABLE 0x0002
+#define ET_MAC_CFG2_IFMODE_FULL_DPLX 0x0001
+
+/*
+ * structure for Interpacket gap reg in mac address map.
+ * located at address 0x5008
+ *
+ * 31: reserved
+ * 30-24: non B2B ipg 1
+ * 23: undefined
+ * 22-16: non B2B ipg 2
+ * 15-8: Min ifg enforce
+ * 7-0: B2B ipg
+ *
+ * structure for half duplex reg in mac address map.
+ * located at address 0x500C
+ * 31-24: reserved
+ * 23-20: Alt BEB trunc
+ * 19: Alt BEB enable
+ * 18: BP no backoff
+ * 17: no backoff
+ * 16: excess defer
+ * 15-12: re-xmit max
+ * 11-10: reserved
+ * 9-0: collision window
+ */
+
+/*
+ * structure for Maximum Frame Length reg in mac address map.
+ * located at address 0x5010: bits 0-15 hold the length.
+ */
+
+/*
+ * structure for Reserve 1 reg in mac address map.
+ * located at address 0x5014 - 0x5018
+ * Defined earlier (u32)
+ */
+
+/*
+ * structure for Test reg in mac address map.
+ * located at address 0x501C
+ * test: bits 0-2, rest unused
+ */
+
+/*
+ * structure for MII Management Configuration reg in mac address map.
+ * located at address 0x5020
+ *
+ * 31: reset MII mgmt
+ * 30-6: unused
+ * 5: scan auto increment
+ * 4: preamble suppress
+ * 3: undefined
+ * 2-0: mgmt clock reset
+ */
+#define ET_MAC_MIIMGMT_CLK_RST 0x0007
+
+/*
+ * structure for MII Management Command reg in mac address map.
+ * located at address 0x5024
+ * bit 1: scan cycle
+ * bit 0: read cycle
+ */
+
+/*
+ * structure for MII Management Address reg in mac address map.
+ * located at address 0x5028
+ * 31-13: reserved
+ * 12-8: phy addr
+ * 7-5: reserved
+ * 4-0: register
+ */
+#define ET_MAC_MII_ADDR(phy, reg) ((phy) << 8 | (reg))
+
+/*
+ * structure for MII Management Control reg in mac address map.
+ * located at address 0x502C
+ * 31-16: reserved
+ * 15-0: phy control
+ */
+
+/*
+ * structure for MII Management Status reg in mac address map.
+ * located at address 0x5030
+ * 31-16: reserved
+ * 15-0: phy control
+ */
+#define ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK 0xFFFF
+
+/*
+ * structure for MII Management Indicators reg in mac address map.
+ * located at address 0x5034
+ * 31-3: reserved
+ * 2: not valid
+ * 1: scanning
+ * 0: busy
+ */
+#define ET_MAC_MGMT_BUSY 0x00000001 /* busy */
+#define ET_MAC_MGMT_WAIT 0x00000005 /* busy | not valid */
+
+/*
+ * structure for Interface Control reg in mac address map.
+ * located at address 0x5038
+ *
+ * 31: reset if module
+ * 30-28: reserved
+ * 27: tbi mode
+ * 26: ghd mode
+ * 25: lhd mode
+ * 24: phy mode
+ * 23: reset per mii
+ * 22-17: reserved
+ * 16: speed
+ * 15: reset pe100x
+ * 14-11: reserved
+ * 10: force quiet
+ * 9: no cipher
+ * 8: disable link fail
+ * 7: reset gpsi
+ * 6-1: reserved
+ * 0: enable jabber protection
+ */
+#define ET_MAC_IFCTRL_GHDMODE (1 << 26)
+#define ET_MAC_IFCTRL_PHYMODE (1 << 24)
+
+/*
+ * structure for Interface Status reg in mac address map.
+ * located at address 0x503C
+ *
+ * 31-10: reserved
+ * 9: excess_defer
+ * 8: clash
+ * 7: phy_jabber
+ * 6: phy_link_ok
+ * 5: phy_full_duplex
+ * 4: phy_speed
+ * 3: pe100x_link_fail
+ * 2: pe10t_loss_carrier
+ * 1: pe10t_sqe_error
+ * 0: pe10t_jabber
+ */
+
+/*
+ * structure for Mac Station Address, Part 1 reg in mac address map.
+ * located at address 0x5040
+ *
+ * 31-24: Octet6
+ * 23-16: Octet5
+ * 15-8: Octet4
+ * 7-0: Octet3
+ */
+#define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
+#define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
+#define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
+
+/*
+ * structure for Mac Station Address, Part 2 reg in mac address map.
+ * located at address 0x5044
+ *
+ * 31-24: Octet2
+ * 23-16: Octet1
+ * 15-0: reserved
+ */
+#define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
+#define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
+
+/*
+ * MAC Module of JAGCore Address Mapping
+ */
+struct mac_regs { /* Location: */
+ u32 cfg1; /* 0x5000 */
+ u32 cfg2; /* 0x5004 */
+ u32 ipg; /* 0x5008 */
+ u32 hfdp; /* 0x500C */
+ u32 max_fm_len; /* 0x5010 */
+ u32 rsv1; /* 0x5014 */
+ u32 rsv2; /* 0x5018 */
+ u32 mac_test; /* 0x501C */
+ u32 mii_mgmt_cfg; /* 0x5020 */
+ u32 mii_mgmt_cmd; /* 0x5024 */
+ u32 mii_mgmt_addr; /* 0x5028 */
+ u32 mii_mgmt_ctrl; /* 0x502C */
+ u32 mii_mgmt_stat; /* 0x5030 */
+ u32 mii_mgmt_indicator; /* 0x5034 */
+ u32 if_ctrl; /* 0x5038 */
+ u32 if_stat; /* 0x503C */
+ u32 station_addr_1; /* 0x5040 */
+ u32 station_addr_2; /* 0x5044 */
+};
+
+/* END OF MAC REGISTER ADDRESS MAP */
+
+/* START OF MAC STAT REGISTER ADDRESS MAP */
+/*
+ * structure for Carry Register One and it's Mask Register reg located in mac
+ * stat address map address 0x6130 and 0x6138.
+ *
+ * 31: tr64
+ * 30: tr127
+ * 29: tr255
+ * 28: tr511
+ * 27: tr1k
+ * 26: trmax
+ * 25: trmgv
+ * 24-17: unused
+ * 16: rbyt
+ * 15: rpkt
+ * 14: rfcs
+ * 13: rmca
+ * 12: rbca
+ * 11: rxcf
+ * 10: rxpf
+ * 9: rxuo
+ * 8: raln
+ * 7: rflr
+ * 6: rcde
+ * 5: rcse
+ * 4: rund
+ * 3: rovr
+ * 2: rfrg
+ * 1: rjbr
+ * 0: rdrp
+ */
+
+/*
+ * structure for Carry Register Two Mask Register reg in mac stat address map.
+ * located at address 0x613C
+ *
+ * 31-20: unused
+ * 19: tjbr
+ * 18: tfcs
+ * 17: txcf
+ * 16: tovr
+ * 15: tund
+ * 14: trfg
+ * 13: tbyt
+ * 12: tpkt
+ * 11: tmca
+ * 10: tbca
+ * 9: txpf
+ * 8: tdfr
+ * 7: tedf
+ * 6: tscl
+ * 5: tmcl
+ * 4: tlcl
+ * 3: txcl
+ * 2: tncl
+ * 1: tpfh
+ * 0: tdrp
+ */
+
+/*
+ * MAC STATS Module of JAGCore Address Mapping
+ */
+struct macstat_regs { /* Location: */
+ u32 pad[32]; /* 0x6000 - 607C */
+
+ /* counters */
+ u32 txrx_0_64_byte_frames; /* 0x6080 */
+ u32 txrx_65_127_byte_frames; /* 0x6084 */
+ u32 txrx_128_255_byte_frames; /* 0x6088 */
+ u32 txrx_256_511_byte_frames; /* 0x608C */
+ u32 txrx_512_1023_byte_frames; /* 0x6090 */
+ u32 txrx_1024_1518_byte_frames; /* 0x6094 */
+ u32 txrx_1519_1522_gvln_frames; /* 0x6098 */
+ u32 rx_bytes; /* 0x609C */
+ u32 rx_packets; /* 0x60A0 */
+ u32 rx_fcs_errs; /* 0x60A4 */
+ u32 rx_multicast_packets; /* 0x60A8 */
+ u32 rx_broadcast_packets; /* 0x60AC */
+ u32 rx_control_frames; /* 0x60B0 */
+ u32 rx_pause_frames; /* 0x60B4 */
+ u32 rx_unknown_opcodes; /* 0x60B8 */
+ u32 rx_align_errs; /* 0x60BC */
+ u32 rx_frame_len_errs; /* 0x60C0 */
+ u32 rx_code_errs; /* 0x60C4 */
+ u32 rx_carrier_sense_errs; /* 0x60C8 */
+ u32 rx_undersize_packets; /* 0x60CC */
+ u32 rx_oversize_packets; /* 0x60D0 */
+ u32 rx_fragment_packets; /* 0x60D4 */
+ u32 rx_jabbers; /* 0x60D8 */
+ u32 rx_drops; /* 0x60DC */
+ u32 tx_bytes; /* 0x60E0 */
+ u32 tx_packets; /* 0x60E4 */
+ u32 tx_multicast_packets; /* 0x60E8 */
+ u32 tx_broadcast_packets; /* 0x60EC */
+ u32 tx_pause_frames; /* 0x60F0 */
+ u32 tx_deferred; /* 0x60F4 */
+ u32 tx_excessive_deferred; /* 0x60F8 */
+ u32 tx_single_collisions; /* 0x60FC */
+ u32 tx_multiple_collisions; /* 0x6100 */
+ u32 tx_late_collisions; /* 0x6104 */
+ u32 tx_excessive_collisions; /* 0x6108 */
+ u32 tx_total_collisions; /* 0x610C */
+ u32 tx_pause_honored_frames; /* 0x6110 */
+ u32 tx_drops; /* 0x6114 */
+ u32 tx_jabbers; /* 0x6118 */
+ u32 tx_fcs_errs; /* 0x611C */
+ u32 tx_control_frames; /* 0x6120 */
+ u32 tx_oversize_frames; /* 0x6124 */
+ u32 tx_undersize_frames; /* 0x6128 */
+ u32 tx_fragments; /* 0x612C */
+ u32 carry_reg1; /* 0x6130 */
+ u32 carry_reg2; /* 0x6134 */
+ u32 carry_reg1_mask; /* 0x6138 */
+ u32 carry_reg2_mask; /* 0x613C */
+};
+
+/* END OF MAC STAT REGISTER ADDRESS MAP */
+
+/* START OF MMC REGISTER ADDRESS MAP */
+/*
+ * Main Memory Controller Control reg in mmc address map.
+ * located at address 0x7000
+ */
+#define ET_MMC_ENABLE 1
+#define ET_MMC_ARB_DISABLE 2
+#define ET_MMC_RXMAC_DISABLE 4
+#define ET_MMC_TXMAC_DISABLE 8
+#define ET_MMC_TXDMA_DISABLE 16
+#define ET_MMC_RXDMA_DISABLE 32
+#define ET_MMC_FORCE_CE 64
+
+/*
+ * Main Memory Controller Host Memory Access Address reg in mmc
+ * address map. Located at address 0x7004. Top 16 bits hold the address bits
+ */
+#define ET_SRAM_REQ_ACCESS 1
+#define ET_SRAM_WR_ACCESS 2
+#define ET_SRAM_IS_CTRL 4
+
+/*
+ * structure for Main Memory Controller Host Memory Access Data reg in mmc
+ * address map. Located at address 0x7008 - 0x7014
+ * Defined earlier (u32)
+ */
+
+/*
+ * Memory Control Module of JAGCore Address Mapping
+ */
+struct mmc_regs { /* Location: */
+ u32 mmc_ctrl; /* 0x7000 */
+ u32 sram_access; /* 0x7004 */
+ u32 sram_word1; /* 0x7008 */
+ u32 sram_word2; /* 0x700C */
+ u32 sram_word3; /* 0x7010 */
+ u32 sram_word4; /* 0x7014 */
+};
+
+/* END OF MMC REGISTER ADDRESS MAP */
+
+/*
+ * JAGCore Address Mapping
+ */
+struct address_map {
+ struct global_regs global;
+ /* unused section of global address map */
+ u8 unused_global[4096 - sizeof(struct global_regs)];
+ struct txdma_regs txdma;
+ /* unused section of txdma address map */
+ u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
+ struct rxdma_regs rxdma;
+ /* unused section of rxdma address map */
+ u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
+ struct txmac_regs txmac;
+ /* unused section of txmac address map */
+ u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
+ struct rxmac_regs rxmac;
+ /* unused section of rxmac address map */
+ u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
+ struct mac_regs mac;
+ /* unused section of mac address map */
+ u8 unused_mac[4096 - sizeof(struct mac_regs)];
+ struct macstat_regs macstat;
+ /* unused section of mac stat address map */
+ u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
+ struct mmc_regs mmc;
+ /* unused section of mmc address map */
+ u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
+ /* unused section of address map */
+ u8 unused_[1015808];
+ u8 unused_exp_rom[4096]; /* MGS-size TBD */
+ u8 unused__[524288]; /* unused section of address map */
+};
+
+/*
+ * Defines for generic MII registers 0x00 -> 0x0F can be found in
+ * include/linux/mii.h
+ */
+/* some defines for modem registers that seem to be 'reserved' */
+#define PHY_INDEX_REG 0x10
+#define PHY_DATA_REG 0x11
+#define PHY_MPHY_CONTROL_REG 0x12
+
+/* defines for specified registers */
+#define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
+ /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
+#define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
+#define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
+#define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
+#define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
+#define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
+#define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
+#define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
+#define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
+ /* TRU_VMI_LINK_CONTROL_REG 29 */
+ /* TRU_VMI_TIMING_CONTROL_REG */
+
+/* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
+#define ET_1000BT_MSTR_SLV 0x4000
+
+/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
+
+/* MI Register 19: Loopback Control Reg(0x13)
+ * 15: mii_en
+ * 14: pcs_en
+ * 13: pmd_en
+ * 12: all_digital_en
+ * 11: replica_en
+ * 10: line_driver_en
+ * 9-0: reserved
+ */
+
+/* MI Register 20: Reserved Reg(0x14) */
+
+/* MI Register 21: Management Interface Control Reg(0x15)
+ * 15-11: reserved
+ * 10-4: mi_error_count
+ * 3: reserved
+ * 2: ignore_10g_fr
+ * 1: reserved
+ * 0: preamble_suppress_en
+ */
+
+/* MI Register 22: PHY Configuration Reg(0x16)
+ * 15: crs_tx_en
+ * 14: reserved
+ * 13-12: tx_fifo_depth
+ * 11-10: speed_downshift
+ * 9: pbi_detect
+ * 8: tbi_rate
+ * 7: alternate_np
+ * 6: group_mdio_en
+ * 5: tx_clock_en
+ * 4: sys_clock_en
+ * 3: reserved
+ * 2-0: mac_if_mode
+ */
+#define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
+
+#define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
+#define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
+#define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
+#define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
+
+/* MI Register 23: PHY CONTROL Reg(0x17)
+ * 15: reserved
+ * 14: tdr_en
+ * 13: reserved
+ * 12-11: downshift_attempts
+ * 10-6: reserved
+ * 5: jabber_10baseT
+ * 4: sqe_10baseT
+ * 3: tp_loopback_10baseT
+ * 2: preamble_gen_en
+ * 1: reserved
+ * 0: force_int
+ */
+
+/* MI Register 24: Interrupt Mask Reg(0x18)
+ * 15-10: reserved
+ * 9: mdio_sync_lost
+ * 8: autoneg_status
+ * 7: hi_bit_err
+ * 6: np_rx
+ * 5: err_counter_full
+ * 4: fifo_over_underflow
+ * 3: rx_status
+ * 2: link_status
+ * 1: automatic_speed
+ * 0: int_en
+ */
+
+/* MI Register 25: Interrupt Status Reg(0x19)
+ * 15-10: reserved
+ * 9: mdio_sync_lost
+ * 8: autoneg_status
+ * 7: hi_bit_err
+ * 6: np_rx
+ * 5: err_counter_full
+ * 4: fifo_over_underflow
+ * 3: rx_status
+ * 2: link_status
+ * 1: automatic_speed
+ * 0: int_en
+ */
+
+/* MI Register 26: PHY Status Reg(0x1A)
+ * 15: reserved
+ * 14-13: autoneg_fault
+ * 12: autoneg_status
+ * 11: mdi_x_status
+ * 10: polarity_status
+ * 9-8: speed_status
+ * 7: duplex_status
+ * 6: link_status
+ * 5: tx_status
+ * 4: rx_status
+ * 3: collision_status
+ * 2: autoneg_en
+ * 1: pause_en
+ * 0: asymmetric_dir
+ */
+#define ET_PHY_AUTONEG_STATUS 0x1000
+#define ET_PHY_POLARITY_STATUS 0x0400
+#define ET_PHY_SPEED_STATUS 0x0300
+#define ET_PHY_DUPLEX_STATUS 0x0080
+#define ET_PHY_LSTATUS 0x0040
+#define ET_PHY_AUTONEG_ENABLE 0x0020
+
+/* MI Register 27: LED Control Reg 1(0x1B)
+ * 15-14: reserved
+ * 13-12: led_dup_indicate
+ * 11-10: led_10baseT
+ * 9-8: led_collision
+ * 7-4: reserved
+ * 3-2: pulse_dur
+ * 1: pulse_stretch1
+ * 0: pulse_stretch0
+ */
+
+/* MI Register 28: LED Control Reg 2(0x1C)
+ * 15-12: led_link
+ * 11-8: led_tx_rx
+ * 7-4: led_100BaseTX
+ * 3-0: led_1000BaseT
+ */
+#define ET_LED2_LED_LINK 0xF000
+#define ET_LED2_LED_TXRX 0x0F00
+#define ET_LED2_LED_100TX 0x00F0
+#define ET_LED2_LED_1000T 0x000F
+
+/* defines for LED control reg 2 values */
+#define LED_VAL_1000BT 0x0
+#define LED_VAL_100BTX 0x1
+#define LED_VAL_10BT 0x2
+#define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
+#define LED_VAL_LINKON 0x4
+#define LED_VAL_TX 0x5
+#define LED_VAL_RX 0x6
+#define LED_VAL_TXRX 0x7 /* TX or RX */
+#define LED_VAL_DUPLEXFULL 0x8
+#define LED_VAL_COLLISION 0x9
+#define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
+#define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
+#define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
+#define LED_VAL_BLINK 0xD
+#define LED_VAL_ON 0xE
+#define LED_VAL_OFF 0xF
+
+#define LED_LINK_SHIFT 12
+#define LED_TXRX_SHIFT 8
+#define LED_100TX_SHIFT 4
+
+/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 6e2d6fd..9d18a1c 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -24,8 +24,6 @@ menuconfig STAGING
if STAGING
-source "drivers/staging/et131x/Kconfig"
-
source "drivers/staging/slicoss/Kconfig"
source "drivers/staging/wlan-ng/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 74c679e..8c56326 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -4,7 +4,6 @@
obj-$(CONFIG_STAGING) += staging.o
obj-y += media/
-obj-$(CONFIG_ET131X) += et131x/
obj-$(CONFIG_SLICOSS) += slicoss/
obj-$(CONFIG_PRISM2_USB) += wlan-ng/
obj-$(CONFIG_COMEDI) += comedi/
diff --git a/drivers/staging/et131x/Kconfig b/drivers/staging/et131x/Kconfig
deleted file mode 100644
index 8190f2a..0000000
--- a/drivers/staging/et131x/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-config ET131X
- tristate "Agere ET-1310 Gigabit Ethernet support"
- depends on PCI && NET && NETDEVICES
- select PHYLIB
- default n
- ---help---
- This driver supports Agere ET-1310 ethernet adapters.
-
- To compile this driver as a module, choose M here. The module
- will be called et131x.
diff --git a/drivers/staging/et131x/Makefile b/drivers/staging/et131x/Makefile
deleted file mode 100644
index 027ff94..0000000
--- a/drivers/staging/et131x/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the Agere ET-131x ethernet driver
-#
-
-obj-$(CONFIG_ET131X) += et131x.o
diff --git a/drivers/staging/et131x/README b/drivers/staging/et131x/README
deleted file mode 100644
index 13c8168..0000000
--- a/drivers/staging/et131x/README
+++ /dev/null
@@ -1,15 +0,0 @@
-This is a driver for the ET1310 network device.
-
-Based on the driver found at https://sourceforge.net/projects/et131x/
-
-Cleaned up immensely by Olaf Hartman and Christoph Hellwig <hch@infradead.org>
-
-Note, the powermanagement options were removed from the vendor provided
-driver as they did not build properly at the time.
-
-TODO:
-
-Please send patches to:
- Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- Mark Einon <mark.einon@gmail.com>
-
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
deleted file mode 100644
index 93afd61..0000000
--- a/drivers/staging/et131x/et131x.c
+++ /dev/null
@@ -1,4412 +0,0 @@
-/* Agere Systems Inc.
- * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- * http://www.agere.com
- *
- * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
- *
- *------------------------------------------------------------------------------
- *
- * SOFTWARE LICENSE
- *
- * This software is provided subject to the following terms and conditions,
- * which you should read carefully before using the software. Using this
- * software indicates your acceptance of these terms and conditions. If you do
- * not agree with these terms and conditions, do not use the software.
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *
- * Redistribution and use in source or binary forms, with or without
- * modifications, are permitted provided that the following conditions are met:
- *
- * . Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following Disclaimer as comments in the code as
- * well as in the documentation and/or other materials provided with the
- * distribution.
- *
- * . Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following Disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * . Neither the name of Agere Systems Inc. nor the names of the contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * Disclaimer
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGE.
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/pci.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include <linux/sched.h>
-#include <linux/ptrace.h>
-#include <linux/slab.h>
-#include <linux/ctype.h>
-#include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/interrupt.h>
-#include <linux/in.h>
-#include <linux/delay.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/if_arp.h>
-#include <linux/ioport.h>
-#include <linux/crc32.h>
-#include <linux/random.h>
-#include <linux/phy.h>
-
-#include "et131x.h"
-
-MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
-MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
-MODULE_LICENSE("Dual BSD/GPL");
-MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
-
-/* EEPROM defines */
-#define MAX_NUM_REGISTER_POLLS 1000
-#define MAX_NUM_WRITE_RETRIES 2
-
-/* MAC defines */
-#define COUNTER_WRAP_16_BIT 0x10000
-#define COUNTER_WRAP_12_BIT 0x1000
-
-/* PCI defines */
-#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
-#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
-
-/* ISR defines */
-/* For interrupts, normal running is:
- * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
- * watchdog_interrupt & txdma_xfer_done
- *
- * In both cases, when flow control is enabled for either Tx or bi-direction,
- * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
- * buffer rings are running low.
- */
-#define INT_MASK_DISABLE 0xffffffff
-
-/* NOTE: Masking out MAC_STAT Interrupt for now...
- * #define INT_MASK_ENABLE 0xfff6bf17
- * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
- */
-#define INT_MASK_ENABLE 0xfffebf17
-#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
-
-/* General defines */
-/* Packet and header sizes */
-#define NIC_MIN_PACKET_SIZE 60
-
-/* Multicast list size */
-#define NIC_MAX_MCAST_LIST 128
-
-/* Supported Filters */
-#define ET131X_PACKET_TYPE_DIRECTED 0x0001
-#define ET131X_PACKET_TYPE_MULTICAST 0x0002
-#define ET131X_PACKET_TYPE_BROADCAST 0x0004
-#define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
-#define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
-
-/* Tx Timeout */
-#define ET131X_TX_TIMEOUT (1 * HZ)
-#define NIC_SEND_HANG_THRESHOLD 0
-
-/* MP_ADAPTER flags */
-#define FMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
-
-/* MP_SHARED flags */
-#define FMP_ADAPTER_LOWER_POWER 0x00200000
-
-#define FMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
-#define FMP_ADAPTER_HARDWARE_ERROR 0x04000000
-
-#define FMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
-
-/* Some offsets in PCI config space that are actually used. */
-#define ET1310_PCI_MAC_ADDRESS 0xA4
-#define ET1310_PCI_EEPROM_STATUS 0xB2
-#define ET1310_PCI_ACK_NACK 0xC0
-#define ET1310_PCI_REPLAY 0xC2
-#define ET1310_PCI_L0L1LATENCY 0xCF
-
-/* PCI Product IDs */
-#define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
-#define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
-
-/* Define order of magnitude converter */
-#define NANO_IN_A_MICRO 1000
-
-#define PARM_RX_NUM_BUFS_DEF 4
-#define PARM_RX_TIME_INT_DEF 10
-#define PARM_RX_MEM_END_DEF 0x2bc
-#define PARM_TX_TIME_INT_DEF 40
-#define PARM_TX_NUM_BUFS_DEF 4
-#define PARM_DMA_CACHE_DEF 0
-
-/* RX defines */
-#define FBR_CHUNKS 32
-#define MAX_DESC_PER_RING_RX 1024
-
-/* number of RFDs - default and min */
-#define RFD_LOW_WATER_MARK 40
-#define NIC_DEFAULT_NUM_RFD 1024
-#define NUM_FBRS 2
-
-#define MAX_PACKETS_HANDLED 256
-
-#define ALCATEL_MULTICAST_PKT 0x01000000
-#define ALCATEL_BROADCAST_PKT 0x02000000
-
-/* typedefs for Free Buffer Descriptors */
-struct fbr_desc {
- u32 addr_lo;
- u32 addr_hi;
- u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
-};
-
-/* Packet Status Ring Descriptors
- *
- * Word 0:
- *
- * top 16 bits are from the Alcatel Status Word as enumerated in
- * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
- *
- * 0: hp hash pass
- * 1: ipa IP checksum assist
- * 2: ipp IP checksum pass
- * 3: tcpa TCP checksum assist
- * 4: tcpp TCP checksum pass
- * 5: wol WOL Event
- * 6: rxmac_error RXMAC Error Indicator
- * 7: drop Drop packet
- * 8: ft Frame Truncated
- * 9: jp Jumbo Packet
- * 10: vp VLAN Packet
- * 11-15: unused
- * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
- * 17: asw_RX_DV_event short receive event detected
- * 18: asw_false_carrier_event bad carrier since last good packet
- * 19: asw_code_err one or more nibbles signalled as errors
- * 20: asw_CRC_err CRC error
- * 21: asw_len_chk_err frame length field incorrect
- * 22: asw_too_long frame length > 1518 bytes
- * 23: asw_OK valid CRC + no code error
- * 24: asw_multicast has a multicast address
- * 25: asw_broadcast has a broadcast address
- * 26: asw_dribble_nibble spurious bits after EOP
- * 27: asw_control_frame is a control frame
- * 28: asw_pause_frame is a pause frame
- * 29: asw_unsupported_op unsupported OP code
- * 30: asw_VLAN_tag VLAN tag detected
- * 31: asw_long_evt Rx long event
- *
- * Word 1:
- * 0-15: length length in bytes
- * 16-25: bi Buffer Index
- * 26-27: ri Ring Index
- * 28-31: reserved
- */
-struct pkt_stat_desc {
- u32 word0;
- u32 word1;
-};
-
-/* Typedefs for the RX DMA status word */
-
-/* rx status word 0 holds part of the status bits of the Rx DMA engine
- * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
- * which contains the Free Buffer ring 0 and 1 available offset.
- *
- * bit 0-9 FBR1 offset
- * bit 10 Wrap flag for FBR1
- * bit 16-25 FBR0 offset
- * bit 26 Wrap flag for FBR0
- */
-
-/* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
- * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
- * which contains the Packet Status Ring available offset.
- *
- * bit 0-15 reserved
- * bit 16-27 PSRoffset
- * bit 28 PSRwrap
- * bit 29-31 unused
- */
-
-/* struct rx_status_block is a structure representing the status of the Rx
- * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
- */
-struct rx_status_block {
- u32 word0;
- u32 word1;
-};
-
-/* Structure for look-up table holding free buffer ring pointers, addresses
- * and state.
- */
-struct fbr_lookup {
- void *virt[MAX_DESC_PER_RING_RX];
- u32 bus_high[MAX_DESC_PER_RING_RX];
- u32 bus_low[MAX_DESC_PER_RING_RX];
- void *ring_virtaddr;
- dma_addr_t ring_physaddr;
- void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
- u32 local_full;
- u32 num_entries;
- dma_addr_t buffsize;
-};
-
-/* struct rx_ring is the structure representing the adaptor's local
- * reference(s) to the rings
- */
-struct rx_ring {
- struct fbr_lookup *fbr[NUM_FBRS];
- void *ps_ring_virtaddr;
- dma_addr_t ps_ring_physaddr;
- u32 local_psr_full;
- u32 psr_entries;
-
- struct rx_status_block *rx_status_block;
- dma_addr_t rx_status_bus;
-
- /* RECV */
- struct list_head recv_list;
- u32 num_ready_recv;
-
- u32 num_rfd;
-
- bool unfinished_receives;
-};
-
-/* TX defines */
-/* word 2 of the control bits in the Tx Descriptor ring for the ET-1310
- *
- * 0-15: length of packet
- * 16-27: VLAN tag
- * 28: VLAN CFI
- * 29-31: VLAN priority
- *
- * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
- *
- * 0: last packet in the sequence
- * 1: first packet in the sequence
- * 2: interrupt the processor when this pkt sent
- * 3: Control word - no packet data
- * 4: Issue half-duplex backpressure : XON/XOFF
- * 5: send pause frame
- * 6: Tx frame has error
- * 7: append CRC
- * 8: MAC override
- * 9: pad packet
- * 10: Packet is a Huge packet
- * 11: append VLAN tag
- * 12: IP checksum assist
- * 13: TCP checksum assist
- * 14: UDP checksum assist
- */
-#define TXDESC_FLAG_LASTPKT 0x0001
-#define TXDESC_FLAG_FIRSTPKT 0x0002
-#define TXDESC_FLAG_INTPROC 0x0004
-
-/* struct tx_desc represents each descriptor on the ring */
-struct tx_desc {
- u32 addr_hi;
- u32 addr_lo;
- u32 len_vlan; /* control words how to xmit the */
- u32 flags; /* data (detailed above) */
-};
-
-/* The status of the Tx DMA engine it sits in free memory, and is pointed to
- * by 0x101c / 0x1020. This is a DMA10 type
- */
-
-/* TCB (Transmit Control Block: Host Side) */
-struct tcb {
- struct tcb *next; /* Next entry in ring */
- u32 count; /* Used to spot stuck/lost packets */
- u32 stale; /* Used to spot stuck/lost packets */
- struct sk_buff *skb; /* Network skb we are tied to */
- u32 index; /* Ring indexes */
- u32 index_start;
-};
-
-/* Structure representing our local reference(s) to the ring */
-struct tx_ring {
- /* TCB (Transmit Control Block) memory and lists */
- struct tcb *tcb_ring;
-
- /* List of TCBs that are ready to be used */
- struct tcb *tcb_qhead;
- struct tcb *tcb_qtail;
-
- /* list of TCBs that are currently being sent. NOTE that access to all
- * three of these (including used) are controlled via the
- * TCBSendQLock. This lock should be secured prior to incementing /
- * decrementing used, or any queue manipulation on send_head /
- * tail
- */
- struct tcb *send_head;
- struct tcb *send_tail;
- int used;
-
- /* The actual descriptor ring */
- struct tx_desc *tx_desc_ring;
- dma_addr_t tx_desc_ring_pa;
-
- /* send_idx indicates where we last wrote to in the descriptor ring. */
- u32 send_idx;
-
- /* The location of the write-back status block */
- u32 *tx_status;
- dma_addr_t tx_status_pa;
-
- /* Packets since the last IRQ: used for interrupt coalescing */
- int since_irq;
-};
-
-/* Do not change these values: if changed, then change also in respective
- * TXdma and Rxdma engines
- */
-#define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
-#define NUM_TCB 64
-
-/* These values are all superseded by registry entries to facilitate tuning.
- * Once the desired performance has been achieved, the optimal registry values
- * should be re-populated to these #defines:
- */
-#define TX_ERROR_PERIOD 1000
-
-#define LO_MARK_PERCENT_FOR_PSR 15
-#define LO_MARK_PERCENT_FOR_RX 15
-
-/* RFD (Receive Frame Descriptor) */
-struct rfd {
- struct list_head list_node;
- struct sk_buff *skb;
- u32 len; /* total size of receive frame */
- u16 bufferindex;
- u8 ringindex;
-};
-
-/* Flow Control */
-#define FLOW_BOTH 0
-#define FLOW_TXONLY 1
-#define FLOW_RXONLY 2
-#define FLOW_NONE 3
-
-/* Struct to define some device statistics */
-struct ce_stats {
- /* MIB II variables
- *
- * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
- * MUST have 32, then we'll need another way to perform atomic
- * operations
- */
- u32 multicast_pkts_rcvd;
- u32 rcvd_pkts_dropped;
-
- /* Tx Statistics. */
- u32 tx_underflows;
- u32 tx_collisions;
- u32 tx_excessive_collisions;
- u32 tx_first_collisions;
- u32 tx_late_collisions;
- u32 tx_max_pkt_errs;
- u32 tx_deferred;
-
- /* Rx Statistics. */
- u32 rx_overflows;
- u32 rx_length_errs;
- u32 rx_align_errs;
- u32 rx_crc_errs;
- u32 rx_code_violations;
- u32 rx_other_errs;
-
- u32 interrupt_status;
-};
-
-/* The private adapter structure */
-struct et131x_adapter {
- struct net_device *netdev;
- struct pci_dev *pdev;
- struct mii_bus *mii_bus;
- struct phy_device *phydev;
- struct napi_struct napi;
-
- /* Flags that indicate current state of the adapter */
- u32 flags;
-
- /* local link state, to determine if a state change has occurred */
- int link;
-
- /* Configuration */
- u8 rom_addr[ETH_ALEN];
- u8 addr[ETH_ALEN];
- bool has_eeprom;
- u8 eeprom_data[2];
-
- spinlock_t tcb_send_qlock; /* protects the tx_ring send tcb list */
- spinlock_t tcb_ready_qlock; /* protects the tx_ring ready tcb list */
- spinlock_t rcv_lock; /* protects the rx_ring receive list */
-
- /* Packet Filter and look ahead size */
- u32 packet_filter;
-
- /* multicast list */
- u32 multicast_addr_count;
- u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
-
- /* Pointer to the device's PCI register space */
- struct address_map __iomem *regs;
-
- /* Registry parameters */
- u8 wanted_flow; /* Flow we want for 802.3x flow control */
- u32 registry_jumbo_packet; /* Max supported ethernet packet size */
-
- /* Derived from the registry: */
- u8 flow; /* flow control validated by the far-end */
-
- /* Minimize init-time */
- struct timer_list error_timer;
-
- /* variable putting the phy into coma mode when boot up with no cable
- * plugged in after 5 seconds
- */
- u8 boot_coma;
-
- /* Tx Memory Variables */
- struct tx_ring tx_ring;
-
- /* Rx Memory Variables */
- struct rx_ring rx_ring;
-
- /* Stats */
- struct ce_stats stats;
-};
-
-static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
-{
- u32 reg;
- int i;
-
- /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
- * bits 7,1:0 both equal to 1, at least once after reset.
- * Subsequent operations need only to check that bits 1:0 are equal
- * to 1 prior to starting a single byte read/write
- */
- for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
- /* Read registers grouped in DWORD1 */
- if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
- return -EIO;
-
- /* I2C idle and Phy Queue Avail both true */
- if ((reg & 0x3000) == 0x3000) {
- if (status)
- *status = reg;
- return reg & 0xFF;
- }
- }
- return -ETIMEDOUT;
-}
-
-/* eeprom_write - Write a byte to the ET1310's EEPROM
- * @adapter: pointer to our private adapter structure
- * @addr: the address to write
- * @data: the value to write
- *
- * Returns 1 for a successful write.
- */
-static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
-{
- struct pci_dev *pdev = adapter->pdev;
- int index = 0;
- int retries;
- int err = 0;
- int writeok = 0;
- u32 status;
- u32 val = 0;
-
- /* For an EEPROM, an I2C single byte write is defined as a START
- * condition followed by the device address, EEPROM address, one byte
- * of data and a STOP condition. The STOP condition will trigger the
- * EEPROM's internally timed write cycle to the nonvolatile memory.
- * All inputs are disabled during this write cycle and the EEPROM will
- * not respond to any access until the internal write is complete.
- */
- err = eeprom_wait_ready(pdev, NULL);
- if (err < 0)
- return err;
-
- /* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
- * and bits 1:0 both =0. Bit 5 should be set according to the
- * type of EEPROM being accessed (1=two byte addressing, 0=one
- * byte addressing).
- */
- if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
- LBCIF_CONTROL_LBCIF_ENABLE |
- LBCIF_CONTROL_I2C_WRITE))
- return -EIO;
-
- /* Prepare EEPROM address for Step 3 */
- for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
- /* Write the address to the LBCIF Address Register */
- if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
- break;
- /* Write the data to the LBCIF Data Register (the I2C write
- * will begin).
- */
- if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
- break;
- /* Monitor bit 1:0 of the LBCIF Status Register. When bits
- * 1:0 are both equal to 1, the I2C write has completed and the
- * internal write cycle of the EEPROM is about to start.
- * (bits 1:0 = 01 is a legal state while waiting from both
- * equal to 1, but bits 1:0 = 10 is invalid and implies that
- * something is broken).
- */
- err = eeprom_wait_ready(pdev, &status);
- if (err < 0)
- return 0;
-
- /* Check bit 3 of the LBCIF Status Register. If equal to 1,
- * an error has occurred.Don't break here if we are revision
- * 1, this is so we do a blind write for load bug.
- */
- if ((status & LBCIF_STATUS_GENERAL_ERROR) &&
- adapter->pdev->revision == 0)
- break;
-
- /* Check bit 2 of the LBCIF Status Register. If equal to 1 an
- * ACK error has occurred on the address phase of the write.
- * This could be due to an actual hardware failure or the
- * EEPROM may still be in its internal write cycle from a
- * previous write. This write operation was ignored and must be
- *repeated later.
- */
- if (status & LBCIF_STATUS_ACK_ERROR) {
- /* This could be due to an actual hardware failure
- * or the EEPROM may still be in its internal write
- * cycle from a previous write. This write operation
- * was ignored and must be repeated later.
- */
- udelay(10);
- continue;
- }
-
- writeok = 1;
- break;
- }
-
- /* Set bit 6 of the LBCIF Control Register = 0.
- */
- udelay(10);
-
- while (1) {
- if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
- LBCIF_CONTROL_LBCIF_ENABLE))
- writeok = 0;
-
- /* Do read until internal ACK_ERROR goes away meaning write
- * completed
- */
- do {
- pci_write_config_dword(pdev,
- LBCIF_ADDRESS_REGISTER,
- addr);
- do {
- pci_read_config_dword(pdev,
- LBCIF_DATA_REGISTER,
- &val);
- } while ((val & 0x00010000) == 0);
- } while (val & 0x00040000);
-
- if ((val & 0xFF00) != 0xC000 || index == 10000)
- break;
- index++;
- }
- return writeok ? 0 : -EIO;
-}
-
-/* eeprom_read - Read a byte from the ET1310's EEPROM
- * @adapter: pointer to our private adapter structure
- * @addr: the address from which to read
- * @pdata: a pointer to a byte in which to store the value of the read
- * @eeprom_id: the ID of the EEPROM
- * @addrmode: how the EEPROM is to be accessed
- *
- * Returns 1 for a successful read
- */
-static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
-{
- struct pci_dev *pdev = adapter->pdev;
- int err;
- u32 status;
-
- /* A single byte read is similar to the single byte write, with the
- * exception of the data flow:
- */
- err = eeprom_wait_ready(pdev, NULL);
- if (err < 0)
- return err;
- /* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
- * and bits 1:0 both =0. Bit 5 should be set according to the type
- * of EEPROM being accessed (1=two byte addressing, 0=one byte
- * addressing).
- */
- if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
- LBCIF_CONTROL_LBCIF_ENABLE))
- return -EIO;
- /* Write the address to the LBCIF Address Register (I2C read will
- * begin).
- */
- if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
- return -EIO;
- /* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
- * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
- * has occurred).
- */
- err = eeprom_wait_ready(pdev, &status);
- if (err < 0)
- return err;
- /* Regardless of error status, read data byte from LBCIF Data
- * Register.
- */
- *pdata = err;
- /* Check bit 2 of the LBCIF Status Register. If = 1,
- * then an error has occurred.
- */
- return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
-}
-
-static int et131x_init_eeprom(struct et131x_adapter *adapter)
-{
- struct pci_dev *pdev = adapter->pdev;
- u8 eestatus;
-
- /* We first need to check the EEPROM Status code located at offset
- * 0xB2 of config space
- */
- pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus);
-
- /* THIS IS A WORKAROUND:
- * I need to call this function twice to get my card in a
- * LG M1 Express Dual running. I tried also a msleep before this
- * function, because I thought there could be some time conditions
- * but it didn't work. Call the whole function twice also work.
- */
- if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
- dev_err(&pdev->dev,
- "Could not read PCI config space for EEPROM Status\n");
- return -EIO;
- }
-
- /* Determine if the error(s) we care about are present. If they are
- * present we need to fail.
- */
- if (eestatus & 0x4C) {
- int write_failed = 0;
-
- if (pdev->revision == 0x01) {
- int i;
- static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
-
- /* Re-write the first 4 bytes if we have an eeprom
- * present and the revision id is 1, this fixes the
- * corruption seen with 1310 B Silicon
- */
- for (i = 0; i < 3; i++)
- if (eeprom_write(adapter, i, eedata[i]) < 0)
- write_failed = 1;
- }
- if (pdev->revision != 0x01 || write_failed) {
- dev_err(&pdev->dev,
- "Fatal EEPROM Status Error - 0x%04x\n",
- eestatus);
-
- /* This error could mean that there was an error
- * reading the eeprom or that the eeprom doesn't exist.
- * We will treat each case the same and not try to
- * gather additional information that normally would
- * come from the eeprom, like MAC Address
- */
- adapter->has_eeprom = 0;
- return -EIO;
- }
- }
- adapter->has_eeprom = 1;
-
- /* Read the EEPROM for information regarding LED behavior. Refer to
- * ET1310_phy.c, et131x_xcvr_init(), for its use.
- */
- eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
- eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
-
- if (adapter->eeprom_data[0] != 0xcd)
- /* Disable all optional features */
- adapter->eeprom_data[1] = 0x00;
-
- return 0;
-}
-
-/* et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
- * @adapter: pointer to our adapter structure
- */
-static void et131x_rx_dma_enable(struct et131x_adapter *adapter)
-{
- /* Setup the receive dma configuration register for normal operation */
- u32 csr = ET_RXDMA_CSR_FBR1_ENABLE;
- struct rx_ring *rx_ring = &adapter->rx_ring;
-
- if (rx_ring->fbr[1]->buffsize == 4096)
- csr |= ET_RXDMA_CSR_FBR1_SIZE_LO;
- else if (rx_ring->fbr[1]->buffsize == 8192)
- csr |= ET_RXDMA_CSR_FBR1_SIZE_HI;
- else if (rx_ring->fbr[1]->buffsize == 16384)
- csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI;
-
- csr |= ET_RXDMA_CSR_FBR0_ENABLE;
- if (rx_ring->fbr[0]->buffsize == 256)
- csr |= ET_RXDMA_CSR_FBR0_SIZE_LO;
- else if (rx_ring->fbr[0]->buffsize == 512)
- csr |= ET_RXDMA_CSR_FBR0_SIZE_HI;
- else if (rx_ring->fbr[0]->buffsize == 1024)
- csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI;
- writel(csr, &adapter->regs->rxdma.csr);
-
- csr = readl(&adapter->regs->rxdma.csr);
- if (csr & ET_RXDMA_CSR_HALT_STATUS) {
- udelay(5);
- csr = readl(&adapter->regs->rxdma.csr);
- if (csr & ET_RXDMA_CSR_HALT_STATUS) {
- dev_err(&adapter->pdev->dev,
- "RX Dma failed to exit halt state. CSR 0x%08x\n",
- csr);
- }
- }
-}
-
-/* et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
- * @adapter: pointer to our adapter structure
- */
-static void et131x_rx_dma_disable(struct et131x_adapter *adapter)
-{
- u32 csr;
- /* Setup the receive dma configuration register */
- writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE,
- &adapter->regs->rxdma.csr);
- csr = readl(&adapter->regs->rxdma.csr);
- if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) {
- udelay(5);
- csr = readl(&adapter->regs->rxdma.csr);
- if (!(csr & ET_RXDMA_CSR_HALT_STATUS))
- dev_err(&adapter->pdev->dev,
- "RX Dma failed to enter halt state. CSR 0x%08x\n",
- csr);
- }
-}
-
-/* et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
- * @adapter: pointer to our adapter structure
- *
- * Mainly used after a return to the D0 (full-power) state from a lower state.
- */
-static void et131x_tx_dma_enable(struct et131x_adapter *adapter)
-{
- /* Setup the transmit dma configuration register for normal
- * operation
- */
- writel(ET_TXDMA_SNGL_EPKT | (PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
- &adapter->regs->txdma.csr);
-}
-
-static inline void add_10bit(u32 *v, int n)
-{
- *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
-}
-
-static inline void add_12bit(u32 *v, int n)
-{
- *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
-}
-
-/* et1310_config_mac_regs1 - Initialize the first part of MAC regs
- * @adapter: pointer to our adapter structure
- */
-static void et1310_config_mac_regs1(struct et131x_adapter *adapter)
-{
- struct mac_regs __iomem *macregs = &adapter->regs->mac;
- u32 station1;
- u32 station2;
- u32 ipg;
-
- /* First we need to reset everything. Write to MAC configuration
- * register 1 to perform reset.
- */
- writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
- ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
- ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC,
- ¯egs->cfg1);
-
- /* Next lets configure the MAC Inter-packet gap register */
- ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
- ipg |= 0x50 << 8; /* ifg enforce 0x50 */
- writel(ipg, ¯egs->ipg);
-
- /* Next lets configure the MAC Half Duplex register */
- /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
- writel(0x00A1F037, ¯egs->hfdp);
-
- /* Next lets configure the MAC Interface Control register */
- writel(0, ¯egs->if_ctrl);
-
- /* Let's move on to setting up the mii management configuration */
- writel(ET_MAC_MIIMGMT_CLK_RST, ¯egs->mii_mgmt_cfg);
-
- /* Next lets configure the MAC Station Address register. These
- * values are read from the EEPROM during initialization and stored
- * in the adapter structure. We write what is stored in the adapter
- * structure to the MAC Station Address registers high and low. This
- * station address is used for generating and checking pause control
- * packets.
- */
- station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
- (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
- station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
- (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
- (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
- adapter->addr[2];
- writel(station1, ¯egs->station_addr_1);
- writel(station2, ¯egs->station_addr_2);
-
- /* Max ethernet packet in bytes that will be passed by the mac without
- * being truncated. Allow the MAC to pass 4 more than our max packet
- * size. This is 4 for the Ethernet CRC.
- *
- * Packets larger than (registry_jumbo_packet) that do not contain a
- * VLAN ID will be dropped by the Rx function.
- */
- writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len);
-
- /* clear out MAC config reset */
- writel(0, ¯egs->cfg1);
-}
-
-/* et1310_config_mac_regs2 - Initialize the second part of MAC regs
- * @adapter: pointer to our adapter structure
- */
-static void et1310_config_mac_regs2(struct et131x_adapter *adapter)
-{
- int32_t delay = 0;
- struct mac_regs __iomem *mac = &adapter->regs->mac;
- struct phy_device *phydev = adapter->phydev;
- u32 cfg1;
- u32 cfg2;
- u32 ifctrl;
- u32 ctl;
-
- ctl = readl(&adapter->regs->txmac.ctl);
- cfg1 = readl(&mac->cfg1);
- cfg2 = readl(&mac->cfg2);
- ifctrl = readl(&mac->if_ctrl);
-
- /* Set up the if mode bits */
- cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK;
- if (phydev->speed == SPEED_1000) {
- cfg2 |= ET_MAC_CFG2_IFMODE_1000;
- /* Phy mode bit */
- ifctrl &= ~ET_MAC_IFCTRL_PHYMODE;
- } else {
- cfg2 |= ET_MAC_CFG2_IFMODE_100;
- ifctrl |= ET_MAC_IFCTRL_PHYMODE;
- }
-
- /* We need to enable Rx/Tx */
- cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE |
- ET_MAC_CFG1_TX_FLOW;
- /* Initialize loop back to off */
- cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW);
- if (adapter->flow == FLOW_RXONLY || adapter->flow == FLOW_BOTH)
- cfg1 |= ET_MAC_CFG1_RX_FLOW;
- writel(cfg1, &mac->cfg1);
-
- /* Now we need to initialize the MAC Configuration 2 register */
- /* preamble 7, check length, huge frame off, pad crc, crc enable
- * full duplex off
- */
- cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT;
- cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK;
- cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC;
- cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE;
- cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME;
- cfg2 &= ~ET_MAC_CFG2_IFMODE_FULL_DPLX;
-
- /* Turn on duplex if needed */
- if (phydev->duplex == DUPLEX_FULL)
- cfg2 |= ET_MAC_CFG2_IFMODE_FULL_DPLX;
-
- ifctrl &= ~ET_MAC_IFCTRL_GHDMODE;
- if (phydev->duplex == DUPLEX_HALF)
- ifctrl |= ET_MAC_IFCTRL_GHDMODE;
-
- writel(ifctrl, &mac->if_ctrl);
- writel(cfg2, &mac->cfg2);
-
- do {
- udelay(10);
- delay++;
- cfg1 = readl(&mac->cfg1);
- } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100);
-
- if (delay == 100) {
- dev_warn(&adapter->pdev->dev,
- "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
- cfg1);
- }
-
- /* Enable txmac */
- ctl |= ET_TX_CTRL_TXMAC_ENABLE | ET_TX_CTRL_FC_DISABLE;
- writel(ctl, &adapter->regs->txmac.ctl);
-
- /* Ready to start the RXDMA/TXDMA engine */
- if (adapter->flags & FMP_ADAPTER_LOWER_POWER) {
- et131x_rx_dma_enable(adapter);
- et131x_tx_dma_enable(adapter);
- }
-}
-
-/* et1310_in_phy_coma - check if the device is in phy coma
- * @adapter: pointer to our adapter structure
- *
- * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
- */
-static int et1310_in_phy_coma(struct et131x_adapter *adapter)
-{
- u32 pmcsr = readl(&adapter->regs->global.pm_csr);
-
- return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
-}
-
-static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
-{
- struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
- u32 hash1 = 0;
- u32 hash2 = 0;
- u32 hash3 = 0;
- u32 hash4 = 0;
- u32 pm_csr;
-
- /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
- * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
- * specified) then we should pass NO multi-cast addresses to the
- * driver.
- */
- if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
- int i;
-
- /* Loop through our multicast array and set up the device */
- for (i = 0; i < adapter->multicast_addr_count; i++) {
- u32 result;
-
- result = ether_crc(6, adapter->multicast_list[i]);
-
- result = (result & 0x3F800000) >> 23;
-
- if (result < 32) {
- hash1 |= (1 << result);
- } else if ((31 < result) && (result < 64)) {
- result -= 32;
- hash2 |= (1 << result);
- } else if ((63 < result) && (result < 96)) {
- result -= 64;
- hash3 |= (1 << result);
- } else {
- result -= 96;
- hash4 |= (1 << result);
- }
- }
- }
-
- /* Write out the new hash to the device */
- pm_csr = readl(&adapter->regs->global.pm_csr);
- if (!et1310_in_phy_coma(adapter)) {
- writel(hash1, &rxmac->multi_hash1);
- writel(hash2, &rxmac->multi_hash2);
- writel(hash3, &rxmac->multi_hash3);
- writel(hash4, &rxmac->multi_hash4);
- }
-}
-
-static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
-{
- struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
- u32 uni_pf1;
- u32 uni_pf2;
- u32 uni_pf3;
- u32 pm_csr;
-
- /* Set up unicast packet filter reg 3 to be the first two octets of
- * the MAC address for both address
- *
- * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
- * MAC address for second address
- *
- * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
- * MAC address for first address
- */
- uni_pf3 = (adapter->addr[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT) |
- (adapter->addr[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT) |
- (adapter->addr[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT) |
- adapter->addr[1];
-
- uni_pf2 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT) |
- (adapter->addr[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT) |
- (adapter->addr[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT) |
- adapter->addr[5];
-
- uni_pf1 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT) |
- (adapter->addr[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT) |
- (adapter->addr[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT) |
- adapter->addr[5];
-
- pm_csr = readl(&adapter->regs->global.pm_csr);
- if (!et1310_in_phy_coma(adapter)) {
- writel(uni_pf1, &rxmac->uni_pf_addr1);
- writel(uni_pf2, &rxmac->uni_pf_addr2);
- writel(uni_pf3, &rxmac->uni_pf_addr3);
- }
-}
-
-static void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
-{
- struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
- struct phy_device *phydev = adapter->phydev;
- u32 sa_lo;
- u32 sa_hi = 0;
- u32 pf_ctrl = 0;
- u32 __iomem *wolw;
-
- /* Disable the MAC while it is being configured (also disable WOL) */
- writel(0x8, &rxmac->ctrl);
-
- /* Initialize WOL to disabled. */
- writel(0, &rxmac->crc0);
- writel(0, &rxmac->crc12);
- writel(0, &rxmac->crc34);
-
- /* We need to set the WOL mask0 - mask4 next. We initialize it to
- * its default Values of 0x00000000 because there are not WOL masks
- * as of this time.
- */
- for (wolw = &rxmac->mask0_word0; wolw <= &rxmac->mask4_word3; wolw++)
- writel(0, wolw);
-
- /* Lets setup the WOL Source Address */
- sa_lo = (adapter->addr[2] << ET_RX_WOL_LO_SA3_SHIFT) |
- (adapter->addr[3] << ET_RX_WOL_LO_SA4_SHIFT) |
- (adapter->addr[4] << ET_RX_WOL_LO_SA5_SHIFT) |
- adapter->addr[5];
- writel(sa_lo, &rxmac->sa_lo);
-
- sa_hi = (u32)(adapter->addr[0] << ET_RX_WOL_HI_SA1_SHIFT) |
- adapter->addr[1];
- writel(sa_hi, &rxmac->sa_hi);
-
- /* Disable all Packet Filtering */
- writel(0, &rxmac->pf_ctrl);
-
- /* Let's initialize the Unicast Packet filtering address */
- if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
- et1310_setup_device_for_unicast(adapter);
- pf_ctrl |= ET_RX_PFCTRL_UNICST_FILTER_ENABLE;
- } else {
- writel(0, &rxmac->uni_pf_addr1);
- writel(0, &rxmac->uni_pf_addr2);
- writel(0, &rxmac->uni_pf_addr3);
- }
-
- /* Let's initialize the Multicast hash */
- if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
- pf_ctrl |= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE;
- et1310_setup_device_for_multicast(adapter);
- }
-
- /* Runt packet filtering. Didn't work in version A silicon. */
- pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT;
- pf_ctrl |= ET_RX_PFCTRL_FRAG_FILTER_ENABLE;
-
- if (adapter->registry_jumbo_packet > 8192)
- /* In order to transmit jumbo packets greater than 8k, the
- * FIFO between RxMAC and RxDMA needs to be reduced in size
- * to (16k - Jumbo packet size). In order to implement this,
- * we must use "cut through" mode in the RxMAC, which chops
- * packets down into segments which are (max_size * 16). In
- * this case we selected 256 bytes, since this is the size of
- * the PCI-Express TLP's that the 1310 uses.
- *
- * seg_en on, fc_en off, size 0x10
- */
- writel(0x41, &rxmac->mcif_ctrl_max_seg);
- else
- writel(0, &rxmac->mcif_ctrl_max_seg);
-
- /* Initialize the MCIF water marks */
- writel(0, &rxmac->mcif_water_mark);
-
- /* Initialize the MIF control */
- writel(0, &rxmac->mif_ctrl);
-
- /* Initialize the Space Available Register */
- writel(0, &rxmac->space_avail);
-
- /* Initialize the the mif_ctrl register
- * bit 3: Receive code error. One or more nibbles were signaled as
- * errors during the reception of the packet. Clear this
- * bit in Gigabit, set it in 100Mbit. This was derived
- * experimentally at UNH.
- * bit 4: Receive CRC error. The packet's CRC did not match the
- * internally generated CRC.
- * bit 5: Receive length check error. Indicates that frame length
- * field value in the packet does not match the actual data
- * byte length and is not a type field.
- * bit 16: Receive frame truncated.
- * bit 17: Drop packet enable
- */
- if (phydev && phydev->speed == SPEED_100)
- writel(0x30038, &rxmac->mif_ctrl);
- else
- writel(0x30030, &rxmac->mif_ctrl);
-
- /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
- * filter is always enabled since it is where the runt packets are
- * supposed to be dropped. For version A silicon, runt packet
- * dropping doesn't work, so it is disabled in the pf_ctrl register,
- * but we still leave the packet filter on.
- */
- writel(pf_ctrl, &rxmac->pf_ctrl);
- writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl);
-}
-
-static void et1310_config_txmac_regs(struct et131x_adapter *adapter)
-{
- struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
-
- /* We need to update the Control Frame Parameters
- * cfpt - control frame pause timer set to 64 (0x40)
- * cfep - control frame extended pause timer set to 0x0
- */
- if (adapter->flow == FLOW_NONE)
- writel(0, &txmac->cf_param);
- else
- writel(0x40, &txmac->cf_param);
-}
-
-static void et1310_config_macstat_regs(struct et131x_adapter *adapter)
-{
- struct macstat_regs __iomem *macstat = &adapter->regs->macstat;
- u32 __iomem *reg;
-
- /* initialize all the macstat registers to zero on the device */
- for (reg = &macstat->txrx_0_64_byte_frames;
- reg <= &macstat->carry_reg2; reg++)
- writel(0, reg);
-
- /* Unmask any counters that we want to track the overflow of.
- * Initially this will be all counters. It may become clear later
- * that we do not need to track all counters.
- */
- writel(0xFFFFBE32, &macstat->carry_reg1_mask);
- writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
-}
-
-/* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
- * @adapter: pointer to our private adapter structure
- * @addr: the address of the transceiver
- * @reg: the register to read
- * @value: pointer to a 16-bit value in which the value will be stored
- */
-static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
- u8 reg, u16 *value)
-{
- struct mac_regs __iomem *mac = &adapter->regs->mac;
- int status = 0;
- u32 delay = 0;
- u32 mii_addr;
- u32 mii_cmd;
- u32 mii_indicator;
-
- /* Save a local copy of the registers we are dealing with so we can
- * set them back
- */
- mii_addr = readl(&mac->mii_mgmt_addr);
- mii_cmd = readl(&mac->mii_mgmt_cmd);
-
- /* Stop the current operation */
- writel(0, &mac->mii_mgmt_cmd);
-
- /* Set up the register we need to read from on the correct PHY */
- writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
-
- writel(0x1, &mac->mii_mgmt_cmd);
-
- do {
- udelay(50);
- delay++;
- mii_indicator = readl(&mac->mii_mgmt_indicator);
- } while ((mii_indicator & ET_MAC_MGMT_WAIT) && delay < 50);
-
- /* If we hit the max delay, we could not read the register */
- if (delay == 50) {
- dev_warn(&adapter->pdev->dev,
- "reg 0x%08x could not be read\n", reg);
- dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
- mii_indicator);
-
- status = -EIO;
- goto out;
- }
-
- /* If we hit here we were able to read the register and we need to
- * return the value to the caller
- */
- *value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK;
-
-out:
- /* Stop the read operation */
- writel(0, &mac->mii_mgmt_cmd);
-
- /* set the registers we touched back to the state at which we entered
- * this function
- */
- writel(mii_addr, &mac->mii_mgmt_addr);
- writel(mii_cmd, &mac->mii_mgmt_cmd);
-
- return status;
-}
-
-static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
-{
- struct phy_device *phydev = adapter->phydev;
-
- if (!phydev)
- return -EIO;
-
- return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
-}
-
-/* et131x_mii_write - Write to a PHY reg through the MII interface of the MAC
- * @adapter: pointer to our private adapter structure
- * @reg: the register to read
- * @value: 16-bit value to write
- */
-static int et131x_mii_write(struct et131x_adapter *adapter, u8 addr, u8 reg,
- u16 value)
-{
- struct mac_regs __iomem *mac = &adapter->regs->mac;
- int status = 0;
- u32 delay = 0;
- u32 mii_addr;
- u32 mii_cmd;
- u32 mii_indicator;
-
- /* Save a local copy of the registers we are dealing with so we can
- * set them back
- */
- mii_addr = readl(&mac->mii_mgmt_addr);
- mii_cmd = readl(&mac->mii_mgmt_cmd);
-
- /* Stop the current operation */
- writel(0, &mac->mii_mgmt_cmd);
-
- /* Set up the register we need to write to on the correct PHY */
- writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
-
- /* Add the value to write to the registers to the mac */
- writel(value, &mac->mii_mgmt_ctrl);
-
- do {
- udelay(50);
- delay++;
- mii_indicator = readl(&mac->mii_mgmt_indicator);
- } while ((mii_indicator & ET_MAC_MGMT_BUSY) && delay < 100);
-
- /* If we hit the max delay, we could not write the register */
- if (delay == 100) {
- u16 tmp;
-
- dev_warn(&adapter->pdev->dev,
- "reg 0x%08x could not be written", reg);
- dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
- mii_indicator);
- dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
- readl(&mac->mii_mgmt_cmd));
-
- et131x_mii_read(adapter, reg, &tmp);
-
- status = -EIO;
- }
- /* Stop the write operation */
- writel(0, &mac->mii_mgmt_cmd);
-
- /* set the registers we touched back to the state at which we entered
- * this function
- */
- writel(mii_addr, &mac->mii_mgmt_addr);
- writel(mii_cmd, &mac->mii_mgmt_cmd);
-
- return status;
-}
-
-static void et1310_phy_read_mii_bit(struct et131x_adapter *adapter,
- u16 regnum,
- u16 bitnum,
- u8 *value)
-{
- u16 reg;
- u16 mask = 1 << bitnum;
-
- /* Read the requested register */
- et131x_mii_read(adapter, regnum, ®);
-
- *value = (reg & mask) >> bitnum;
-}
-
-static void et1310_config_flow_control(struct et131x_adapter *adapter)
-{
- struct phy_device *phydev = adapter->phydev;
-
- if (phydev->duplex == DUPLEX_HALF) {
- adapter->flow = FLOW_NONE;
- } else {
- char remote_pause, remote_async_pause;
-
- et1310_phy_read_mii_bit(adapter, 5, 10, &remote_pause);
- et1310_phy_read_mii_bit(adapter, 5, 11, &remote_async_pause);
-
- if (remote_pause && remote_async_pause) {
- adapter->flow = adapter->wanted_flow;
- } else if (remote_pause && !remote_async_pause) {
- if (adapter->wanted_flow == FLOW_BOTH)
- adapter->flow = FLOW_BOTH;
- else
- adapter->flow = FLOW_NONE;
- } else if (!remote_pause && !remote_async_pause) {
- adapter->flow = FLOW_NONE;
- } else {
- if (adapter->wanted_flow == FLOW_BOTH)
- adapter->flow = FLOW_RXONLY;
- else
- adapter->flow = FLOW_NONE;
- }
- }
-}
-
-/* et1310_update_macstat_host_counters - Update local copy of the statistics */
-static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
-{
- struct ce_stats *stats = &adapter->stats;
- struct macstat_regs __iomem *macstat =
- &adapter->regs->macstat;
-
- stats->tx_collisions += readl(&macstat->tx_total_collisions);
- stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
- stats->tx_deferred += readl(&macstat->tx_deferred);
- stats->tx_excessive_collisions +=
- readl(&macstat->tx_multiple_collisions);
- stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
- stats->tx_underflows += readl(&macstat->tx_undersize_frames);
- stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
-
- stats->rx_align_errs += readl(&macstat->rx_align_errs);
- stats->rx_crc_errs += readl(&macstat->rx_code_errs);
- stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
- stats->rx_overflows += readl(&macstat->rx_oversize_packets);
- stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
- stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
- stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
-}
-
-/* et1310_handle_macstat_interrupt
- *
- * One of the MACSTAT counters has wrapped. Update the local copy of
- * the statistics held in the adapter structure, checking the "wrap"
- * bit for each counter.
- */
-static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
-{
- u32 carry_reg1;
- u32 carry_reg2;
-
- /* Read the interrupt bits from the register(s). These are Clear On
- * Write.
- */
- carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
- carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
-
- writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
- writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
-
- /* We need to do update the host copy of all the MAC_STAT counters.
- * For each counter, check it's overflow bit. If the overflow bit is
- * set, then increment the host version of the count by one complete
- * revolution of the counter. This routine is called when the counter
- * block indicates that one of the counters has wrapped.
- */
- if (carry_reg1 & (1 << 14))
- adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
- if (carry_reg1 & (1 << 8))
- adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
- if (carry_reg1 & (1 << 7))
- adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
- if (carry_reg1 & (1 << 2))
- adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
- if (carry_reg1 & (1 << 6))
- adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
- if (carry_reg1 & (1 << 3))
- adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
- if (carry_reg1 & (1 << 0))
- adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
- if (carry_reg2 & (1 << 16))
- adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
- if (carry_reg2 & (1 << 15))
- adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
- if (carry_reg2 & (1 << 6))
- adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
- if (carry_reg2 & (1 << 8))
- adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
- if (carry_reg2 & (1 << 5))
- adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
- if (carry_reg2 & (1 << 4))
- adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
- if (carry_reg2 & (1 << 2))
- adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
-}
-
-static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
-{
- struct net_device *netdev = bus->priv;
- struct et131x_adapter *adapter = netdev_priv(netdev);
- u16 value;
- int ret;
-
- ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
-
- if (ret < 0)
- return ret;
-
- return value;
-}
-
-static int et131x_mdio_write(struct mii_bus *bus, int phy_addr,
- int reg, u16 value)
-{
- struct net_device *netdev = bus->priv;
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- return et131x_mii_write(adapter, phy_addr, reg, value);
-}
-
-/* et1310_phy_power_switch - PHY power control
- * @adapter: device to control
- * @down: true for off/false for back on
- *
- * one hundred, ten, one thousand megs
- * How would you like to have your LAN accessed
- * Can't you see that this code processed
- * Phy power, phy power..
- */
-static void et1310_phy_power_switch(struct et131x_adapter *adapter, bool down)
-{
- u16 data;
- struct phy_device *phydev = adapter->phydev;
-
- et131x_mii_read(adapter, MII_BMCR, &data);
- data &= ~BMCR_PDOWN;
- if (down)
- data |= BMCR_PDOWN;
- et131x_mii_write(adapter, phydev->addr, MII_BMCR, data);
-}
-
-/* et131x_xcvr_init - Init the phy if we are setting it into force mode */
-static void et131x_xcvr_init(struct et131x_adapter *adapter)
-{
- u16 lcr2;
- struct phy_device *phydev = adapter->phydev;
-
- /* Set the LED behavior such that LED 1 indicates speed (off =
- * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
- * link and activity (on for link, blink off for activity).
- *
- * NOTE: Some customizations have been added here for specific
- * vendors; The LED behavior is now determined by vendor data in the
- * EEPROM. However, the above description is the default.
- */
- if ((adapter->eeprom_data[1] & 0x4) == 0) {
- et131x_mii_read(adapter, PHY_LED_2, &lcr2);
-
- lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T);
- lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
-
- if ((adapter->eeprom_data[1] & 0x8) == 0)
- lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
- else
- lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
-
- et131x_mii_write(adapter, phydev->addr, PHY_LED_2, lcr2);
- }
-}
-
-/* et131x_configure_global_regs - configure JAGCore global regs
- *
- * Used to configure the global registers on the JAGCore
- */
-static void et131x_configure_global_regs(struct et131x_adapter *adapter)
-{
- struct global_regs __iomem *regs = &adapter->regs->global;
-
- writel(0, ®s->rxq_start_addr);
- writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
-
- if (adapter->registry_jumbo_packet < 2048) {
- /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
- * block of RAM that the driver can split between Tx
- * and Rx as it desires. Our default is to split it
- * 50/50:
- */
- writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
- writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
- } else if (adapter->registry_jumbo_packet < 8192) {
- /* For jumbo packets > 2k but < 8k, split 50-50. */
- writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
- writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
- } else {
- /* 9216 is the only packet size greater than 8k that
- * is available. The Tx buffer has to be big enough
- * for one whole packet on the Tx side. We'll make
- * the Tx 9408, and give the rest to Rx
- */
- writel(0x01b3, ®s->rxq_end_addr);
- writel(0x01b4, ®s->txq_start_addr);
- }
-
- /* Initialize the loopback register. Disable all loopbacks. */
- writel(0, ®s->loopback);
-
- /* MSI Register */
- writel(0, ®s->msi_config);
-
- /* By default, disable the watchdog timer. It will be enabled when
- * a packet is queued.
- */
- writel(0, ®s->watchdog_timer);
-}
-
-/* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */
-static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
-{
- struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
- struct rx_ring *rx_local = &adapter->rx_ring;
- struct fbr_desc *fbr_entry;
- u32 entry;
- u32 psr_num_des;
- unsigned long flags;
- u8 id;
-
- /* Halt RXDMA to perform the reconfigure. */
- et131x_rx_dma_disable(adapter);
-
- /* Load the completion writeback physical address */
- writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
- writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
-
- memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
-
- /* Set the address and parameters of the packet status ring into the
- * 1310's registers
- */
- writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
- writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
- writel(rx_local->psr_entries - 1, &rx_dma->psr_num_des);
- writel(0, &rx_dma->psr_full_offset);
-
- psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK;
- writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
- &rx_dma->psr_min_des);
-
- spin_lock_irqsave(&adapter->rcv_lock, flags);
-
- /* These local variables track the PSR in the adapter structure */
- rx_local->local_psr_full = 0;
-
- for (id = 0; id < NUM_FBRS; id++) {
- u32 __iomem *num_des;
- u32 __iomem *full_offset;
- u32 __iomem *min_des;
- u32 __iomem *base_hi;
- u32 __iomem *base_lo;
- struct fbr_lookup *fbr = rx_local->fbr[id];
-
- if (id == 0) {
- num_des = &rx_dma->fbr0_num_des;
- full_offset = &rx_dma->fbr0_full_offset;
- min_des = &rx_dma->fbr0_min_des;
- base_hi = &rx_dma->fbr0_base_hi;
- base_lo = &rx_dma->fbr0_base_lo;
- } else {
- num_des = &rx_dma->fbr1_num_des;
- full_offset = &rx_dma->fbr1_full_offset;
- min_des = &rx_dma->fbr1_min_des;
- base_hi = &rx_dma->fbr1_base_hi;
- base_lo = &rx_dma->fbr1_base_lo;
- }
-
- /* Now's the best time to initialize FBR contents */
- fbr_entry = fbr->ring_virtaddr;
- for (entry = 0; entry < fbr->num_entries; entry++) {
- fbr_entry->addr_hi = fbr->bus_high[entry];
- fbr_entry->addr_lo = fbr->bus_low[entry];
- fbr_entry->word2 = entry;
- fbr_entry++;
- }
-
- /* Set the address and parameters of Free buffer ring 1 and 0
- * into the 1310's registers
- */
- writel(upper_32_bits(fbr->ring_physaddr), base_hi);
- writel(lower_32_bits(fbr->ring_physaddr), base_lo);
- writel(fbr->num_entries - 1, num_des);
- writel(ET_DMA10_WRAP, full_offset);
-
- /* This variable tracks the free buffer ring 1 full position,
- * so it has to match the above.
- */
- fbr->local_full = ET_DMA10_WRAP;
- writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
- min_des);
- }
-
- /* Program the number of packets we will receive before generating an
- * interrupt.
- * For version B silicon, this value gets updated once autoneg is
- *complete.
- */
- writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
-
- /* The "time_done" is not working correctly to coalesce interrupts
- * after a given time period, but rather is giving us an interrupt
- * regardless of whether we have received packets.
- * This value gets updated once autoneg is complete.
- */
- writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
-
- spin_unlock_irqrestore(&adapter->rcv_lock, flags);
-}
-
-/* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
- *
- * Configure the transmit engine with the ring buffers we have created
- * and prepare it for use.
- */
-static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
-{
- struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
- struct tx_ring *tx_ring = &adapter->tx_ring;
-
- /* Load the hardware with the start of the transmit descriptor ring. */
- writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi);
- writel(lower_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_lo);
-
- /* Initialise the transmit DMA engine */
- writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
-
- /* Load the completion writeback physical address */
- writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi);
- writel(lower_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_lo);
-
- *tx_ring->tx_status = 0;
-
- writel(0, &txdma->service_request);
- tx_ring->send_idx = 0;
-}
-
-/* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */
-static void et131x_adapter_setup(struct et131x_adapter *adapter)
-{
- /* Configure the JAGCore */
- et131x_configure_global_regs(adapter);
-
- et1310_config_mac_regs1(adapter);
-
- /* Configure the MMC registers */
- /* All we need to do is initialize the Memory Control Register */
- writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
-
- et1310_config_rxmac_regs(adapter);
- et1310_config_txmac_regs(adapter);
-
- et131x_config_rx_dma_regs(adapter);
- et131x_config_tx_dma_regs(adapter);
-
- et1310_config_macstat_regs(adapter);
-
- et1310_phy_power_switch(adapter, 0);
- et131x_xcvr_init(adapter);
-}
-
-/* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */
-static void et131x_soft_reset(struct et131x_adapter *adapter)
-{
- u32 reg;
-
- /* Disable MAC Core */
- reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
- ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
- ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
- writel(reg, &adapter->regs->mac.cfg1);
-
- reg = ET_RESET_ALL;
- writel(reg, &adapter->regs->global.sw_reset);
-
- reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
- ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
- writel(reg, &adapter->regs->mac.cfg1);
- writel(0, &adapter->regs->mac.cfg1);
-}
-
-/* et131x_enable_interrupts - enable interrupt
- *
- * Enable the appropriate interrupts on the ET131x according to our
- * configuration
- */
-static void et131x_enable_interrupts(struct et131x_adapter *adapter)
-{
- u32 mask;
-
- /* Enable all global interrupts */
- if (adapter->flow == FLOW_TXONLY || adapter->flow == FLOW_BOTH)
- mask = INT_MASK_ENABLE;
- else
- mask = INT_MASK_ENABLE_NO_FLOW;
-
- writel(mask, &adapter->regs->global.int_mask);
-}
-
-/* et131x_disable_interrupts - interrupt disable
- *
- * Block all interrupts from the et131x device at the device itself
- */
-static void et131x_disable_interrupts(struct et131x_adapter *adapter)
-{
- /* Disable all global interrupts */
- writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
-}
-
-/* et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 */
-static void et131x_tx_dma_disable(struct et131x_adapter *adapter)
-{
- /* Setup the transmit dma configuration register */
- writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,
- &adapter->regs->txdma.csr);
-}
-
-/* et131x_enable_txrx - Enable tx/rx queues */
-static void et131x_enable_txrx(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- /* Enable the Tx and Rx DMA engines (if not already enabled) */
- et131x_rx_dma_enable(adapter);
- et131x_tx_dma_enable(adapter);
-
- /* Enable device interrupts */
- if (adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE)
- et131x_enable_interrupts(adapter);
-
- /* We're ready to move some data, so start the queue */
- netif_start_queue(netdev);
-}
-
-/* et131x_disable_txrx - Disable tx/rx queues */
-static void et131x_disable_txrx(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- /* First thing is to stop the queue */
- netif_stop_queue(netdev);
-
- /* Stop the Tx and Rx DMA engines */
- et131x_rx_dma_disable(adapter);
- et131x_tx_dma_disable(adapter);
-
- /* Disable device interrupts */
- et131x_disable_interrupts(adapter);
-}
-
-/* et131x_init_send - Initialize send data structures */
-static void et131x_init_send(struct et131x_adapter *adapter)
-{
- u32 ct;
- struct tx_ring *tx_ring = &adapter->tx_ring;
- struct tcb *tcb = tx_ring->tcb_ring;
-
- tx_ring->tcb_qhead = tcb;
-
- memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
-
- /* Go through and set up each TCB */
- for (ct = 0; ct++ < NUM_TCB; tcb++)
- /* Set the link pointer in HW TCB to the next TCB in the
- * chain
- */
- tcb->next = tcb + 1;
-
- /* Set the tail pointer */
- tcb--;
- tx_ring->tcb_qtail = tcb;
- tcb->next = NULL;
- /* Curr send queue should now be empty */
- tx_ring->send_head = NULL;
- tx_ring->send_tail = NULL;
-}
-
-/* et1310_enable_phy_coma - called when network cable is unplugged
- *
- * driver receive an phy status change interrupt while in D0 and check that
- * phy_status is down.
- *
- * -- gate off JAGCore;
- * -- set gigE PHY in Coma mode
- * -- wake on phy_interrupt; Perform software reset JAGCore,
- * re-initialize jagcore and gigE PHY
- *
- * Add D0-ASPM-PhyLinkDown Support:
- * -- while in D0, when there is a phy_interrupt indicating phy link
- * down status, call the MPSetPhyComa routine to enter this active
- * state power saving mode
- * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
- * indicating linkup status, call the MPDisablePhyComa routine to
- * restore JAGCore and gigE PHY
- */
-static void et1310_enable_phy_coma(struct et131x_adapter *adapter)
-{
- u32 pmcsr = readl(&adapter->regs->global.pm_csr);
-
- /* Save the GbE PHY speed and duplex modes. Need to restore this
- * when cable is plugged back in
- */
-
- /* Stop sending packets. */
- adapter->flags |= FMP_ADAPTER_LOWER_POWER;
-
- /* Wait for outstanding Receive packets */
- et131x_disable_txrx(adapter->netdev);
-
- /* Gate off JAGCore 3 clock domains */
- pmcsr &= ~ET_PMCSR_INIT;
- writel(pmcsr, &adapter->regs->global.pm_csr);
-
- /* Program gigE PHY in to Coma mode */
- pmcsr |= ET_PM_PHY_SW_COMA;
- writel(pmcsr, &adapter->regs->global.pm_csr);
-}
-
-/* et1310_disable_phy_coma - Disable the Phy Coma Mode */
-static void et1310_disable_phy_coma(struct et131x_adapter *adapter)
-{
- u32 pmcsr;
-
- pmcsr = readl(&adapter->regs->global.pm_csr);
-
- /* Disable phy_sw_coma register and re-enable JAGCore clocks */
- pmcsr |= ET_PMCSR_INIT;
- pmcsr &= ~ET_PM_PHY_SW_COMA;
- writel(pmcsr, &adapter->regs->global.pm_csr);
-
- /* Restore the GbE PHY speed and duplex modes;
- * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
- */
-
- /* Re-initialize the send structures */
- et131x_init_send(adapter);
-
- /* Bring the device back to the state it was during init prior to
- * autonegotiation being complete. This way, when we get the auto-neg
- * complete interrupt, we can complete init by calling ConfigMacREGS2.
- */
- et131x_soft_reset(adapter);
-
- /* setup et1310 as per the documentation ?? */
- et131x_adapter_setup(adapter);
-
- /* Allow Tx to restart */
- adapter->flags &= ~FMP_ADAPTER_LOWER_POWER;
-
- et131x_enable_txrx(adapter->netdev);
-}
-
-static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
-{
- u32 tmp_free_buff_ring = *free_buff_ring;
-
- tmp_free_buff_ring++;
- /* This works for all cases where limit < 1024. The 1023 case
- * works because 1023++ is 1024 which means the if condition is not
- * taken but the carry of the bit into the wrap bit toggles the wrap
- * value correctly
- */
- if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
- tmp_free_buff_ring &= ~ET_DMA10_MASK;
- tmp_free_buff_ring ^= ET_DMA10_WRAP;
- }
- /* For the 1023 case */
- tmp_free_buff_ring &= (ET_DMA10_MASK | ET_DMA10_WRAP);
- *free_buff_ring = tmp_free_buff_ring;
- return tmp_free_buff_ring;
-}
-
-/* et131x_rx_dma_memory_alloc
- *
- * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
- * and the Packet Status Ring.
- */
-static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
-{
- u8 id;
- u32 i, j;
- u32 bufsize;
- u32 psr_size;
- u32 fbr_chunksize;
- struct rx_ring *rx_ring = &adapter->rx_ring;
- struct fbr_lookup *fbr;
-
- /* Alloc memory for the lookup table */
- rx_ring->fbr[0] = kmalloc(sizeof(*fbr), GFP_KERNEL);
- if (rx_ring->fbr[0] == NULL)
- return -ENOMEM;
- rx_ring->fbr[1] = kmalloc(sizeof(*fbr), GFP_KERNEL);
- if (rx_ring->fbr[1] == NULL)
- return -ENOMEM;
-
- /* The first thing we will do is configure the sizes of the buffer
- * rings. These will change based on jumbo packet support. Larger
- * jumbo packets increases the size of each entry in FBR0, and the
- * number of entries in FBR0, while at the same time decreasing the
- * number of entries in FBR1.
- *
- * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
- * entries are huge in order to accommodate a "jumbo" frame, then it
- * will have less entries. Conversely, FBR1 will now be relied upon
- * to carry more "normal" frames, thus it's entry size also increases
- * and the number of entries goes up too (since it now carries
- * "small" + "regular" packets.
- *
- * In this scheme, we try to maintain 512 entries between the two
- * rings. Also, FBR1 remains a constant size - when it's size doubles
- * the number of entries halves. FBR0 increases in size, however.
- */
- if (adapter->registry_jumbo_packet < 2048) {
- rx_ring->fbr[0]->buffsize = 256;
- rx_ring->fbr[0]->num_entries = 512;
- rx_ring->fbr[1]->buffsize = 2048;
- rx_ring->fbr[1]->num_entries = 512;
- } else if (adapter->registry_jumbo_packet < 4096) {
- rx_ring->fbr[0]->buffsize = 512;
- rx_ring->fbr[0]->num_entries = 1024;
- rx_ring->fbr[1]->buffsize = 4096;
- rx_ring->fbr[1]->num_entries = 512;
- } else {
- rx_ring->fbr[0]->buffsize = 1024;
- rx_ring->fbr[0]->num_entries = 768;
- rx_ring->fbr[1]->buffsize = 16384;
- rx_ring->fbr[1]->num_entries = 128;
- }
-
- rx_ring->psr_entries = rx_ring->fbr[0]->num_entries +
- rx_ring->fbr[1]->num_entries;
-
- for (id = 0; id < NUM_FBRS; id++) {
- fbr = rx_ring->fbr[id];
- /* Allocate an area of memory for Free Buffer Ring */
- bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
- fbr->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
- bufsize,
- &fbr->ring_physaddr,
- GFP_KERNEL);
- if (!fbr->ring_virtaddr) {
- dev_err(&adapter->pdev->dev,
- "Cannot alloc memory for Free Buffer Ring %d\n",
- id);
- return -ENOMEM;
- }
- }
-
- for (id = 0; id < NUM_FBRS; id++) {
- fbr = rx_ring->fbr[id];
- fbr_chunksize = (FBR_CHUNKS * fbr->buffsize);
-
- for (i = 0; i < fbr->num_entries / FBR_CHUNKS; i++) {
- dma_addr_t fbr_physaddr;
-
- fbr->mem_virtaddrs[i] = dma_alloc_coherent(
- &adapter->pdev->dev, fbr_chunksize,
- &fbr->mem_physaddrs[i],
- GFP_KERNEL);
-
- if (!fbr->mem_virtaddrs[i]) {
- dev_err(&adapter->pdev->dev,
- "Could not alloc memory\n");
- return -ENOMEM;
- }
-
- /* See NOTE in "Save Physical Address" comment above */
- fbr_physaddr = fbr->mem_physaddrs[i];
-
- for (j = 0; j < FBR_CHUNKS; j++) {
- u32 k = (i * FBR_CHUNKS) + j;
-
- /* Save the Virtual address of this index for
- * quick access later
- */
- fbr->virt[k] = (u8 *)fbr->mem_virtaddrs[i] +
- (j * fbr->buffsize);
-
- /* now store the physical address in the
- * descriptor so the device can access it
- */
- fbr->bus_high[k] = upper_32_bits(fbr_physaddr);
- fbr->bus_low[k] = lower_32_bits(fbr_physaddr);
- fbr_physaddr += fbr->buffsize;
- }
- }
- }
-
- /* Allocate an area of memory for FIFO of Packet Status ring entries */
- psr_size = sizeof(struct pkt_stat_desc) * rx_ring->psr_entries;
-
- rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
- psr_size,
- &rx_ring->ps_ring_physaddr,
- GFP_KERNEL);
-
- if (!rx_ring->ps_ring_virtaddr) {
- dev_err(&adapter->pdev->dev,
- "Cannot alloc memory for Packet Status Ring\n");
- return -ENOMEM;
- }
-
- /* NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
- * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
- * are ever returned, make sure the high part is retrieved here before
- * storing the adjusted address.
- */
-
- /* Allocate an area of memory for writeback of status information */
- rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
- sizeof(struct rx_status_block),
- &rx_ring->rx_status_bus,
- GFP_KERNEL);
- if (!rx_ring->rx_status_block) {
- dev_err(&adapter->pdev->dev,
- "Cannot alloc memory for Status Block\n");
- return -ENOMEM;
- }
- rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
-
- /* The RFDs are going to be put on lists later on, so initialize the
- * lists now.
- */
- INIT_LIST_HEAD(&rx_ring->recv_list);
- return 0;
-}
-
-/* et131x_rx_dma_memory_free - Free all memory allocated within this module */
-static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
-{
- u8 id;
- u32 ii;
- u32 bufsize;
- u32 psr_size;
- struct rfd *rfd;
- struct rx_ring *rx_ring = &adapter->rx_ring;
- struct fbr_lookup *fbr;
-
- /* Free RFDs and associated packet descriptors */
- WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
-
- while (!list_empty(&rx_ring->recv_list)) {
- rfd = list_entry(rx_ring->recv_list.next,
- struct rfd, list_node);
-
- list_del(&rfd->list_node);
- rfd->skb = NULL;
- kfree(rfd);
- }
-
- /* Free Free Buffer Rings */
- for (id = 0; id < NUM_FBRS; id++) {
- fbr = rx_ring->fbr[id];
-
- if (!fbr || !fbr->ring_virtaddr)
- continue;
-
- /* First the packet memory */
- for (ii = 0; ii < fbr->num_entries / FBR_CHUNKS; ii++) {
- if (fbr->mem_virtaddrs[ii]) {
- bufsize = fbr->buffsize * FBR_CHUNKS;
-
- dma_free_coherent(&adapter->pdev->dev,
- bufsize,
- fbr->mem_virtaddrs[ii],
- fbr->mem_physaddrs[ii]);
-
- fbr->mem_virtaddrs[ii] = NULL;
- }
- }
-
- bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
-
- dma_free_coherent(&adapter->pdev->dev,
- bufsize,
- fbr->ring_virtaddr,
- fbr->ring_physaddr);
-
- fbr->ring_virtaddr = NULL;
- }
-
- /* Free Packet Status Ring */
- if (rx_ring->ps_ring_virtaddr) {
- psr_size = sizeof(struct pkt_stat_desc) * rx_ring->psr_entries;
-
- dma_free_coherent(&adapter->pdev->dev, psr_size,
- rx_ring->ps_ring_virtaddr,
- rx_ring->ps_ring_physaddr);
-
- rx_ring->ps_ring_virtaddr = NULL;
- }
-
- /* Free area of memory for the writeback of status information */
- if (rx_ring->rx_status_block) {
- dma_free_coherent(&adapter->pdev->dev,
- sizeof(struct rx_status_block),
- rx_ring->rx_status_block,
- rx_ring->rx_status_bus);
- rx_ring->rx_status_block = NULL;
- }
-
- /* Free the FBR Lookup Table */
- kfree(rx_ring->fbr[0]);
- kfree(rx_ring->fbr[1]);
-
- /* Reset Counters */
- rx_ring->num_ready_recv = 0;
-}
-
-/* et131x_init_recv - Initialize receive data structures */
-static int et131x_init_recv(struct et131x_adapter *adapter)
-{
- struct rfd *rfd;
- u32 rfdct;
- struct rx_ring *rx_ring = &adapter->rx_ring;
-
- /* Setup each RFD */
- for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
- rfd = kzalloc(sizeof(*rfd), GFP_ATOMIC | GFP_DMA);
- if (!rfd)
- return -ENOMEM;
-
- rfd->skb = NULL;
-
- /* Add this RFD to the recv_list */
- list_add_tail(&rfd->list_node, &rx_ring->recv_list);
-
- /* Increment the available RFD's */
- rx_ring->num_ready_recv++;
- }
-
- return 0;
-}
-
-/* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */
-static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
-{
- struct phy_device *phydev = adapter->phydev;
-
- /* For version B silicon, we do not use the RxDMA timer for 10 and 100
- * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
- */
- if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
- writel(0, &adapter->regs->rxdma.max_pkt_time);
- writel(1, &adapter->regs->rxdma.num_pkt_done);
- }
-}
-
-/* NICReturnRFD - Recycle a RFD and put it back onto the receive list
- * @adapter: pointer to our adapter
- * @rfd: pointer to the RFD
- */
-static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
-{
- struct rx_ring *rx_local = &adapter->rx_ring;
- struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
- u16 buff_index = rfd->bufferindex;
- u8 ring_index = rfd->ringindex;
- unsigned long flags;
- struct fbr_lookup *fbr = rx_local->fbr[ring_index];
-
- /* We don't use any of the OOB data besides status. Otherwise, we
- * need to clean up OOB data
- */
- if (buff_index < fbr->num_entries) {
- u32 free_buff_ring;
- u32 __iomem *offset;
- struct fbr_desc *next;
-
- if (ring_index == 0)
- offset = &rx_dma->fbr0_full_offset;
- else
- offset = &rx_dma->fbr1_full_offset;
-
- next = (struct fbr_desc *)(fbr->ring_virtaddr) +
- INDEX10(fbr->local_full);
-
- /* Handle the Free Buffer Ring advancement here. Write
- * the PA / Buffer Index for the returned buffer into
- * the oldest (next to be freed)FBR entry
- */
- next->addr_hi = fbr->bus_high[buff_index];
- next->addr_lo = fbr->bus_low[buff_index];
- next->word2 = buff_index;
-
- free_buff_ring = bump_free_buff_ring(&fbr->local_full,
- fbr->num_entries - 1);
- writel(free_buff_ring, offset);
- } else {
- dev_err(&adapter->pdev->dev,
- "%s illegal Buffer Index returned\n", __func__);
- }
-
- /* The processing on this RFD is done, so put it back on the tail of
- * our list
- */
- spin_lock_irqsave(&adapter->rcv_lock, flags);
- list_add_tail(&rfd->list_node, &rx_local->recv_list);
- rx_local->num_ready_recv++;
- spin_unlock_irqrestore(&adapter->rcv_lock, flags);
-
- WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
-}
-
-/* nic_rx_pkts - Checks the hardware for available packets
- *
- * Returns rfd, a pointer to our MPRFD.
- *
- * Checks the hardware for available packets, using completion ring
- * If packets are available, it gets an RFD from the recv_list, attaches
- * the packet to it, puts the RFD in the RecvPendList, and also returns
- * the pointer to the RFD.
- */
-static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
-{
- struct rx_ring *rx_local = &adapter->rx_ring;
- struct rx_status_block *status;
- struct pkt_stat_desc *psr;
- struct rfd *rfd;
- unsigned long flags;
- struct list_head *element;
- u8 ring_index;
- u16 buff_index;
- u32 len;
- u32 word0;
- u32 word1;
- struct sk_buff *skb;
- struct fbr_lookup *fbr;
-
- /* RX Status block is written by the DMA engine prior to every
- * interrupt. It contains the next to be used entry in the Packet
- * Status Ring, and also the two Free Buffer rings.
- */
- status = rx_local->rx_status_block;
- word1 = status->word1 >> 16; /* Get the useful bits */
-
- /* Check the PSR and wrap bits do not match */
- if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
- return NULL; /* Looks like this ring is not updated yet */
-
- /* The packet status ring indicates that data is available. */
- psr = (struct pkt_stat_desc *)(rx_local->ps_ring_virtaddr) +
- (rx_local->local_psr_full & 0xFFF);
-
- /* Grab any information that is required once the PSR is advanced,
- * since we can no longer rely on the memory being accurate
- */
- len = psr->word1 & 0xFFFF;
- ring_index = (psr->word1 >> 26) & 0x03;
- fbr = rx_local->fbr[ring_index];
- buff_index = (psr->word1 >> 16) & 0x3FF;
- word0 = psr->word0;
-
- /* Indicate that we have used this PSR entry. */
- /* FIXME wrap 12 */
- add_12bit(&rx_local->local_psr_full, 1);
- if ((rx_local->local_psr_full & 0xFFF) > rx_local->psr_entries - 1) {
- /* Clear psr full and toggle the wrap bit */
- rx_local->local_psr_full &= ~0xFFF;
- rx_local->local_psr_full ^= 0x1000;
- }
-
- writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);
-
- if (ring_index > 1 || buff_index > fbr->num_entries - 1) {
- /* Illegal buffer or ring index cannot be used by S/W*/
- dev_err(&adapter->pdev->dev,
- "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
- rx_local->local_psr_full & 0xFFF, len, buff_index);
- return NULL;
- }
-
- /* Get and fill the RFD. */
- spin_lock_irqsave(&adapter->rcv_lock, flags);
-
- element = rx_local->recv_list.next;
- rfd = list_entry(element, struct rfd, list_node);
-
- if (!rfd) {
- spin_unlock_irqrestore(&adapter->rcv_lock, flags);
- return NULL;
- }
-
- list_del(&rfd->list_node);
- rx_local->num_ready_recv--;
-
- spin_unlock_irqrestore(&adapter->rcv_lock, flags);
-
- rfd->bufferindex = buff_index;
- rfd->ringindex = ring_index;
-
- /* In V1 silicon, there is a bug which screws up filtering of runt
- * packets. Therefore runt packet filtering is disabled in the MAC and
- * the packets are dropped here. They are also counted here.
- */
- if (len < (NIC_MIN_PACKET_SIZE + 4)) {
- adapter->stats.rx_other_errs++;
- rfd->len = 0;
- goto out;
- }
-
- if ((word0 & ALCATEL_MULTICAST_PKT) && !(word0 & ALCATEL_BROADCAST_PKT))
- adapter->stats.multicast_pkts_rcvd++;
-
- rfd->len = len;
-
- skb = dev_alloc_skb(rfd->len + 2);
- if (!skb) {
- dev_err(&adapter->pdev->dev, "Couldn't alloc an SKB for Rx\n");
- return NULL;
- }
-
- adapter->netdev->stats.rx_bytes += rfd->len;
-
- memcpy(skb_put(skb, rfd->len), fbr->virt[buff_index], rfd->len);
-
- skb->protocol = eth_type_trans(skb, adapter->netdev);
- skb->ip_summed = CHECKSUM_NONE;
- netif_receive_skb(skb);
-
-out:
- nic_return_rfd(adapter, rfd);
- return rfd;
-}
-
-/* et131x_handle_recv_pkts - Interrupt handler for receive processing
- *
- * Assumption, Rcv spinlock has been acquired.
- */
-static int et131x_handle_recv_pkts(struct et131x_adapter *adapter, int budget)
-{
- struct rfd *rfd = NULL;
- int count = 0;
- int limit = budget;
- bool done = true;
- struct rx_ring *rx_ring = &adapter->rx_ring;
-
- if (budget > MAX_PACKETS_HANDLED)
- limit = MAX_PACKETS_HANDLED;
-
- /* Process up to available RFD's */
- while (count < limit) {
- if (list_empty(&rx_ring->recv_list)) {
- WARN_ON(rx_ring->num_ready_recv != 0);
- done = false;
- break;
- }
-
- rfd = nic_rx_pkts(adapter);
-
- if (rfd == NULL)
- break;
-
- /* Do not receive any packets until a filter has been set.
- * Do not receive any packets until we have link.
- * If length is zero, return the RFD in order to advance the
- * Free buffer ring.
- */
- if (!adapter->packet_filter ||
- !netif_carrier_ok(adapter->netdev) ||
- rfd->len == 0)
- continue;
-
- /* Increment the number of packets we received */
- adapter->netdev->stats.rx_packets++;
-
- /* Set the status on the packet, either resources or success */
- if (rx_ring->num_ready_recv < RFD_LOW_WATER_MARK)
- dev_warn(&adapter->pdev->dev, "RFD's are running out\n");
-
- count++;
- }
-
- if (count == limit || !done) {
- rx_ring->unfinished_receives = true;
- writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
- &adapter->regs->global.watchdog_timer);
- } else {
- /* Watchdog timer will disable itself if appropriate. */
- rx_ring->unfinished_receives = false;
- }
-
- return count;
-}
-
-/* et131x_tx_dma_memory_alloc
- *
- * Allocates memory that will be visible both to the device and to the CPU.
- * The OS will pass us packets, pointers to which we will insert in the Tx
- * Descriptor queue. The device will read this queue to find the packets in
- * memory. The device will update the "status" in memory each time it xmits a
- * packet.
- */
-static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
-{
- int desc_size = 0;
- struct tx_ring *tx_ring = &adapter->tx_ring;
-
- /* Allocate memory for the TCB's (Transmit Control Block) */
- tx_ring->tcb_ring = kcalloc(NUM_TCB, sizeof(struct tcb),
- GFP_ATOMIC | GFP_DMA);
- if (!tx_ring->tcb_ring)
- return -ENOMEM;
-
- desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
- tx_ring->tx_desc_ring = dma_alloc_coherent(&adapter->pdev->dev,
- desc_size,
- &tx_ring->tx_desc_ring_pa,
- GFP_KERNEL);
- if (!tx_ring->tx_desc_ring) {
- dev_err(&adapter->pdev->dev,
- "Cannot alloc memory for Tx Ring\n");
- return -ENOMEM;
- }
-
- /* Save physical address
- *
- * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
- * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
- * are ever returned, make sure the high part is retrieved here before
- * storing the adjusted address.
- */
- /* Allocate memory for the Tx status block */
- tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
- sizeof(u32),
- &tx_ring->tx_status_pa,
- GFP_KERNEL);
- if (!tx_ring->tx_status_pa) {
- dev_err(&adapter->pdev->dev,
- "Cannot alloc memory for Tx status block\n");
- return -ENOMEM;
- }
- return 0;
-}
-
-/* et131x_tx_dma_memory_free - Free all memory allocated within this module */
-static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
-{
- int desc_size = 0;
- struct tx_ring *tx_ring = &adapter->tx_ring;
-
- if (tx_ring->tx_desc_ring) {
- /* Free memory relating to Tx rings here */
- desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
- dma_free_coherent(&adapter->pdev->dev,
- desc_size,
- tx_ring->tx_desc_ring,
- tx_ring->tx_desc_ring_pa);
- tx_ring->tx_desc_ring = NULL;
- }
-
- /* Free memory for the Tx status block */
- if (tx_ring->tx_status) {
- dma_free_coherent(&adapter->pdev->dev,
- sizeof(u32),
- tx_ring->tx_status,
- tx_ring->tx_status_pa);
-
- tx_ring->tx_status = NULL;
- }
- /* Free the memory for the tcb structures */
- kfree(tx_ring->tcb_ring);
-}
-
-/* nic_send_packet - NIC specific send handler for version B silicon.
- * @adapter: pointer to our adapter
- * @tcb: pointer to struct tcb
- */
-static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
-{
- u32 i;
- struct tx_desc desc[24]; /* 24 x 16 byte */
- u32 frag = 0;
- u32 thiscopy, remainder;
- struct sk_buff *skb = tcb->skb;
- u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
- struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
- struct phy_device *phydev = adapter->phydev;
- dma_addr_t dma_addr;
- struct tx_ring *tx_ring = &adapter->tx_ring;
-
- /* Part of the optimizations of this send routine restrict us to
- * sending 24 fragments at a pass. In practice we should never see
- * more than 5 fragments.
- *
- * NOTE: The older version of this function (below) can handle any
- * number of fragments. If needed, we can call this function,
- * although it is less efficient.
- */
-
- /* nr_frags should be no more than 18. */
- BUILD_BUG_ON(MAX_SKB_FRAGS + 1 > 23);
-
- memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
-
- for (i = 0; i < nr_frags; i++) {
- /* If there is something in this element, lets get a
- * descriptor from the ring and get the necessary data
- */
- if (i == 0) {
- /* If the fragments are smaller than a standard MTU,
- * then map them to a single descriptor in the Tx
- * Desc ring. However, if they're larger, as is
- * possible with support for jumbo packets, then
- * split them each across 2 descriptors.
- *
- * This will work until we determine why the hardware
- * doesn't seem to like large fragments.
- */
- if (skb_headlen(skb) <= 1514) {
- /* Low 16bits are length, high is vlan and
- * unused currently so zero
- */
- desc[frag].len_vlan = skb_headlen(skb);
- dma_addr = dma_map_single(&adapter->pdev->dev,
- skb->data,
- skb_headlen(skb),
- DMA_TO_DEVICE);
- desc[frag].addr_lo = lower_32_bits(dma_addr);
- desc[frag].addr_hi = upper_32_bits(dma_addr);
- frag++;
- } else {
- desc[frag].len_vlan = skb_headlen(skb) / 2;
- dma_addr = dma_map_single(&adapter->pdev->dev,
- skb->data,
- (skb_headlen(skb) / 2),
- DMA_TO_DEVICE);
- desc[frag].addr_lo = lower_32_bits(dma_addr);
- desc[frag].addr_hi = upper_32_bits(dma_addr);
- frag++;
-
- desc[frag].len_vlan = skb_headlen(skb) / 2;
- dma_addr = dma_map_single(&adapter->pdev->dev,
- skb->data +
- (skb_headlen(skb) / 2),
- (skb_headlen(skb) / 2),
- DMA_TO_DEVICE);
- desc[frag].addr_lo = lower_32_bits(dma_addr);
- desc[frag].addr_hi = upper_32_bits(dma_addr);
- frag++;
- }
- } else {
- desc[frag].len_vlan = frags[i - 1].size;
- dma_addr = skb_frag_dma_map(&adapter->pdev->dev,
- &frags[i - 1],
- 0,
- frags[i - 1].size,
- DMA_TO_DEVICE);
- desc[frag].addr_lo = lower_32_bits(dma_addr);
- desc[frag].addr_hi = upper_32_bits(dma_addr);
- frag++;
- }
- }
-
- if (phydev && phydev->speed == SPEED_1000) {
- if (++tx_ring->since_irq == PARM_TX_NUM_BUFS_DEF) {
- /* Last element & Interrupt flag */
- desc[frag - 1].flags =
- TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
- tx_ring->since_irq = 0;
- } else { /* Last element */
- desc[frag - 1].flags = TXDESC_FLAG_LASTPKT;
- }
- } else {
- desc[frag - 1].flags =
- TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
- }
-
- desc[0].flags |= TXDESC_FLAG_FIRSTPKT;
-
- tcb->index_start = tx_ring->send_idx;
- tcb->stale = 0;
-
- thiscopy = NUM_DESC_PER_RING_TX - INDEX10(tx_ring->send_idx);
-
- if (thiscopy >= frag) {
- remainder = 0;
- thiscopy = frag;
- } else {
- remainder = frag - thiscopy;
- }
-
- memcpy(tx_ring->tx_desc_ring + INDEX10(tx_ring->send_idx),
- desc,
- sizeof(struct tx_desc) * thiscopy);
-
- add_10bit(&tx_ring->send_idx, thiscopy);
-
- if (INDEX10(tx_ring->send_idx) == 0 ||
- INDEX10(tx_ring->send_idx) == NUM_DESC_PER_RING_TX) {
- tx_ring->send_idx &= ~ET_DMA10_MASK;
- tx_ring->send_idx ^= ET_DMA10_WRAP;
- }
-
- if (remainder) {
- memcpy(tx_ring->tx_desc_ring,
- desc + thiscopy,
- sizeof(struct tx_desc) * remainder);
-
- add_10bit(&tx_ring->send_idx, remainder);
- }
-
- if (INDEX10(tx_ring->send_idx) == 0) {
- if (tx_ring->send_idx)
- tcb->index = NUM_DESC_PER_RING_TX - 1;
- else
- tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
- } else {
- tcb->index = tx_ring->send_idx - 1;
- }
-
- spin_lock(&adapter->tcb_send_qlock);
-
- if (tx_ring->send_tail)
- tx_ring->send_tail->next = tcb;
- else
- tx_ring->send_head = tcb;
-
- tx_ring->send_tail = tcb;
-
- WARN_ON(tcb->next != NULL);
-
- tx_ring->used++;
-
- spin_unlock(&adapter->tcb_send_qlock);
-
- /* Write the new write pointer back to the device. */
- writel(tx_ring->send_idx, &adapter->regs->txdma.service_request);
-
- /* For Gig only, we use Tx Interrupt coalescing. Enable the software
- * timer to wake us up if this packet isn't followed by N more.
- */
- if (phydev && phydev->speed == SPEED_1000) {
- writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
- &adapter->regs->global.watchdog_timer);
- }
- return 0;
-}
-
-/* send_packet - Do the work to send a packet
- *
- * Assumption: Send spinlock has been acquired
- */
-static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
-{
- int status;
- struct tcb *tcb;
- unsigned long flags;
- struct tx_ring *tx_ring = &adapter->tx_ring;
-
- /* All packets must have at least a MAC address and a protocol type */
- if (skb->len < ETH_HLEN)
- return -EIO;
-
- /* Get a TCB for this packet */
- spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
-
- tcb = tx_ring->tcb_qhead;
-
- if (tcb == NULL) {
- spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
- return -ENOMEM;
- }
-
- tx_ring->tcb_qhead = tcb->next;
-
- if (tx_ring->tcb_qhead == NULL)
- tx_ring->tcb_qtail = NULL;
-
- spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
-
- tcb->skb = skb;
- tcb->next = NULL;
-
- /* Call the NIC specific send handler. */
- status = nic_send_packet(adapter, tcb);
-
- if (status != 0) {
- spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
-
- if (tx_ring->tcb_qtail)
- tx_ring->tcb_qtail->next = tcb;
- else
- /* Apparently ready Q is empty. */
- tx_ring->tcb_qhead = tcb;
-
- tx_ring->tcb_qtail = tcb;
- spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
- return status;
- }
- WARN_ON(tx_ring->used > NUM_TCB);
- return 0;
-}
-
-/* free_send_packet - Recycle a struct tcb
- * @adapter: pointer to our adapter
- * @tcb: pointer to struct tcb
- *
- * Complete the packet if necessary
- * Assumption - Send spinlock has been acquired
- */
-static inline void free_send_packet(struct et131x_adapter *adapter,
- struct tcb *tcb)
-{
- unsigned long flags;
- struct tx_desc *desc = NULL;
- struct net_device_stats *stats = &adapter->netdev->stats;
- struct tx_ring *tx_ring = &adapter->tx_ring;
- u64 dma_addr;
-
- if (tcb->skb) {
- stats->tx_bytes += tcb->skb->len;
-
- /* Iterate through the TX descriptors on the ring
- * corresponding to this packet and umap the fragments
- * they point to
- */
- do {
- desc = tx_ring->tx_desc_ring +
- INDEX10(tcb->index_start);
-
- dma_addr = desc->addr_lo;
- dma_addr |= (u64)desc->addr_hi << 32;
-
- dma_unmap_single(&adapter->pdev->dev,
- dma_addr,
- desc->len_vlan, DMA_TO_DEVICE);
-
- add_10bit(&tcb->index_start, 1);
- if (INDEX10(tcb->index_start) >=
- NUM_DESC_PER_RING_TX) {
- tcb->index_start &= ~ET_DMA10_MASK;
- tcb->index_start ^= ET_DMA10_WRAP;
- }
- } while (desc != tx_ring->tx_desc_ring + INDEX10(tcb->index));
-
- dev_kfree_skb_any(tcb->skb);
- }
-
- memset(tcb, 0, sizeof(struct tcb));
-
- /* Add the TCB to the Ready Q */
- spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
-
- stats->tx_packets++;
-
- if (tx_ring->tcb_qtail)
- tx_ring->tcb_qtail->next = tcb;
- else
- /* Apparently ready Q is empty. */
- tx_ring->tcb_qhead = tcb;
-
- tx_ring->tcb_qtail = tcb;
-
- spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
- WARN_ON(tx_ring->used < 0);
-}
-
-/* et131x_free_busy_send_packets - Free and complete the stopped active sends
- *
- * Assumption - Send spinlock has been acquired
- */
-static void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
-{
- struct tcb *tcb;
- unsigned long flags;
- u32 freed = 0;
- struct tx_ring *tx_ring = &adapter->tx_ring;
-
- /* Any packets being sent? Check the first TCB on the send list */
- spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
-
- tcb = tx_ring->send_head;
-
- while (tcb != NULL && freed < NUM_TCB) {
- struct tcb *next = tcb->next;
-
- tx_ring->send_head = next;
-
- if (next == NULL)
- tx_ring->send_tail = NULL;
-
- tx_ring->used--;
-
- spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
-
- freed++;
- free_send_packet(adapter, tcb);
-
- spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
-
- tcb = tx_ring->send_head;
- }
-
- WARN_ON(freed == NUM_TCB);
-
- spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
-
- tx_ring->used = 0;
-}
-
-/* et131x_handle_send_pkts - Interrupt handler for sending processing
- *
- * Re-claim the send resources, complete sends and get more to send from
- * the send wait queue.
- *
- * Assumption - Send spinlock has been acquired
- */
-static void et131x_handle_send_pkts(struct et131x_adapter *adapter)
-{
- unsigned long flags;
- u32 serviced;
- struct tcb *tcb;
- u32 index;
- struct tx_ring *tx_ring = &adapter->tx_ring;
-
- serviced = readl(&adapter->regs->txdma.new_service_complete);
- index = INDEX10(serviced);
-
- /* Has the ring wrapped? Process any descriptors that do not have
- * the same "wrap" indicator as the current completion indicator
- */
- spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
-
- tcb = tx_ring->send_head;
-
- while (tcb &&
- ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
- index < INDEX10(tcb->index)) {
- tx_ring->used--;
- tx_ring->send_head = tcb->next;
- if (tcb->next == NULL)
- tx_ring->send_tail = NULL;
-
- spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
- free_send_packet(adapter, tcb);
- spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
-
- /* Goto the next packet */
- tcb = tx_ring->send_head;
- }
- while (tcb &&
- !((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
- index > (tcb->index & ET_DMA10_MASK)) {
- tx_ring->used--;
- tx_ring->send_head = tcb->next;
- if (tcb->next == NULL)
- tx_ring->send_tail = NULL;
-
- spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
- free_send_packet(adapter, tcb);
- spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
-
- /* Goto the next packet */
- tcb = tx_ring->send_head;
- }
-
- /* Wake up the queue when we hit a low-water mark */
- if (tx_ring->used <= NUM_TCB / 3)
- netif_wake_queue(adapter->netdev);
-
- spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
-}
-
-static int et131x_get_settings(struct net_device *netdev,
- struct ethtool_cmd *cmd)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- return phy_ethtool_gset(adapter->phydev, cmd);
-}
-
-static int et131x_set_settings(struct net_device *netdev,
- struct ethtool_cmd *cmd)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- return phy_ethtool_sset(adapter->phydev, cmd);
-}
-
-static int et131x_get_regs_len(struct net_device *netdev)
-{
-#define ET131X_REGS_LEN 256
- return ET131X_REGS_LEN * sizeof(u32);
-}
-
-static void et131x_get_regs(struct net_device *netdev,
- struct ethtool_regs *regs, void *regs_data)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
- struct address_map __iomem *aregs = adapter->regs;
- u32 *regs_buff = regs_data;
- u32 num = 0;
- u16 tmp;
-
- memset(regs_data, 0, et131x_get_regs_len(netdev));
-
- regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
- adapter->pdev->device;
-
- /* PHY regs */
- et131x_mii_read(adapter, MII_BMCR, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_BMSR, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_PHYSID1, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_PHYSID2, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_ADVERTISE, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_LPA, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_EXPANSION, &tmp);
- regs_buff[num++] = tmp;
- /* Autoneg next page transmit reg */
- et131x_mii_read(adapter, 0x07, &tmp);
- regs_buff[num++] = tmp;
- /* Link partner next page reg */
- et131x_mii_read(adapter, 0x08, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_CTRL1000, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_STAT1000, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, 0x0b, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, 0x0c, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_MMD_CTRL, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_MMD_DATA, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, MII_ESTATUS, &tmp);
- regs_buff[num++] = tmp;
-
- et131x_mii_read(adapter, PHY_INDEX_REG, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_DATA_REG, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL + 1, &tmp);
- regs_buff[num++] = tmp;
-
- et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_CONFIG, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_PHY_CONTROL, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_PHY_STATUS, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_LED_1, &tmp);
- regs_buff[num++] = tmp;
- et131x_mii_read(adapter, PHY_LED_2, &tmp);
- regs_buff[num++] = tmp;
-
- /* Global regs */
- regs_buff[num++] = readl(&aregs->global.txq_start_addr);
- regs_buff[num++] = readl(&aregs->global.txq_end_addr);
- regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
- regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
- regs_buff[num++] = readl(&aregs->global.pm_csr);
- regs_buff[num++] = adapter->stats.interrupt_status;
- regs_buff[num++] = readl(&aregs->global.int_mask);
- regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
- regs_buff[num++] = readl(&aregs->global.int_status_alias);
- regs_buff[num++] = readl(&aregs->global.sw_reset);
- regs_buff[num++] = readl(&aregs->global.slv_timer);
- regs_buff[num++] = readl(&aregs->global.msi_config);
- regs_buff[num++] = readl(&aregs->global.loopback);
- regs_buff[num++] = readl(&aregs->global.watchdog_timer);
-
- /* TXDMA regs */
- regs_buff[num++] = readl(&aregs->txdma.csr);
- regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
- regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
- regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
- regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
- regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
- regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
- regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
- regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
- regs_buff[num++] = readl(&aregs->txdma.service_request);
- regs_buff[num++] = readl(&aregs->txdma.service_complete);
- regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
- regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
- regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
- regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
- regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
- regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
- regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
- regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
- regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
- regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
- regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
- regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
- regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
- regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
- regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
-
- /* RXDMA regs */
- regs_buff[num++] = readl(&aregs->rxdma.csr);
- regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
- regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
- regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
- regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
- regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
- regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
- regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
- regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
- regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
- regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
- regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
- regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
- regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
- regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
- regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
- regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
- regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
- regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
- regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
- regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
- regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
- regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
- regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
- regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
- regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
- regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
- regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
- regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
-}
-
-static void et131x_get_drvinfo(struct net_device *netdev,
- struct ethtool_drvinfo *info)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
- strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
- strlcpy(info->bus_info, pci_name(adapter->pdev),
- sizeof(info->bus_info));
-}
-
-static struct ethtool_ops et131x_ethtool_ops = {
- .get_settings = et131x_get_settings,
- .set_settings = et131x_set_settings,
- .get_drvinfo = et131x_get_drvinfo,
- .get_regs_len = et131x_get_regs_len,
- .get_regs = et131x_get_regs,
- .get_link = ethtool_op_get_link,
-};
-
-/* et131x_hwaddr_init - set up the MAC Address on the ET1310 */
-static void et131x_hwaddr_init(struct et131x_adapter *adapter)
-{
- /* If have our default mac from init and no mac address from
- * EEPROM then we need to generate the last octet and set it on the
- * device
- */
- if (is_zero_ether_addr(adapter->rom_addr)) {
- /* We need to randomly generate the last octet so we
- * decrease our chances of setting the mac address to
- * same as another one of our cards in the system
- */
- get_random_bytes(&adapter->addr[5], 1);
- /* We have the default value in the register we are
- * working with so we need to copy the current
- * address into the permanent address
- */
- memcpy(adapter->rom_addr,
- adapter->addr, ETH_ALEN);
- } else {
- /* We do not have an override address, so set the
- * current address to the permanent address and add
- * it to the device
- */
- memcpy(adapter->addr,
- adapter->rom_addr, ETH_ALEN);
- }
-}
-
-/* et131x_pci_init - initial PCI setup
- *
- * Perform the initial setup of PCI registers and if possible initialise
- * the MAC address. At this point the I/O registers have yet to be mapped
- */
-static int et131x_pci_init(struct et131x_adapter *adapter,
- struct pci_dev *pdev)
-{
- u16 max_payload;
- int i, rc;
-
- rc = et131x_init_eeprom(adapter);
- if (rc < 0)
- goto out;
-
- if (!pci_is_pcie(pdev)) {
- dev_err(&pdev->dev, "Missing PCIe capabilities\n");
- goto err_out;
- }
-
- /* Let's set up the PORT LOGIC Register. */
-
- /* Program the Ack/Nak latency and replay timers */
- max_payload = pdev->pcie_mpss;
-
- if (max_payload < 2) {
- static const u16 acknak[2] = { 0x76, 0xD0 };
- static const u16 replay[2] = { 0x1E0, 0x2ED };
-
- if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
- acknak[max_payload])) {
- dev_err(&pdev->dev,
- "Could not write PCI config space for ACK/NAK\n");
- goto err_out;
- }
- if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
- replay[max_payload])) {
- dev_err(&pdev->dev,
- "Could not write PCI config space for Replay Timer\n");
- goto err_out;
- }
- }
-
- /* l0s and l1 latency timers. We are using default values.
- * Representing 001 for L0s and 010 for L1
- */
- if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
- dev_err(&pdev->dev,
- "Could not write PCI config space for Latency Timers\n");
- goto err_out;
- }
-
- /* Change the max read size to 2k */
- if (pcie_set_readrq(pdev, 2048)) {
- dev_err(&pdev->dev,
- "Couldn't change PCI config space for Max read size\n");
- goto err_out;
- }
-
- /* Get MAC address from config space if an eeprom exists, otherwise
- * the MAC address there will not be valid
- */
- if (!adapter->has_eeprom) {
- et131x_hwaddr_init(adapter);
- return 0;
- }
-
- for (i = 0; i < ETH_ALEN; i++) {
- if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
- adapter->rom_addr + i)) {
- dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
- goto err_out;
- }
- }
- ether_addr_copy(adapter->addr, adapter->rom_addr);
-out:
- return rc;
-err_out:
- rc = -EIO;
- goto out;
-}
-
-/* et131x_error_timer_handler
- * @data: timer-specific variable; here a pointer to our adapter structure
- *
- * The routine called when the error timer expires, to track the number of
- * recurring errors.
- */
-static void et131x_error_timer_handler(unsigned long data)
-{
- struct et131x_adapter *adapter = (struct et131x_adapter *)data;
- struct phy_device *phydev = adapter->phydev;
-
- if (et1310_in_phy_coma(adapter)) {
- /* Bring the device immediately out of coma, to
- * prevent it from sleeping indefinitely, this
- * mechanism could be improved!
- */
- et1310_disable_phy_coma(adapter);
- adapter->boot_coma = 20;
- } else {
- et1310_update_macstat_host_counters(adapter);
- }
-
- if (!phydev->link && adapter->boot_coma < 11)
- adapter->boot_coma++;
-
- if (adapter->boot_coma == 10) {
- if (!phydev->link) {
- if (!et1310_in_phy_coma(adapter)) {
- /* NOTE - This was originally a 'sync with
- * interrupt'. How to do that under Linux?
- */
- et131x_enable_interrupts(adapter);
- et1310_enable_phy_coma(adapter);
- }
- }
- }
-
- /* This is a periodic timer, so reschedule */
- mod_timer(&adapter->error_timer, jiffies + TX_ERROR_PERIOD * HZ / 1000);
-}
-
-/* et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx */
-static void et131x_adapter_memory_free(struct et131x_adapter *adapter)
-{
- et131x_tx_dma_memory_free(adapter);
- et131x_rx_dma_memory_free(adapter);
-}
-
-/* et131x_adapter_memory_alloc
- * Allocate all the memory blocks for send, receive and others.
- */
-static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
-{
- int status;
-
- /* Allocate memory for the Tx Ring */
- status = et131x_tx_dma_memory_alloc(adapter);
- if (status) {
- dev_err(&adapter->pdev->dev,
- "et131x_tx_dma_memory_alloc FAILED\n");
- et131x_tx_dma_memory_free(adapter);
- return status;
- }
- /* Receive buffer memory allocation */
- status = et131x_rx_dma_memory_alloc(adapter);
- if (status) {
- dev_err(&adapter->pdev->dev,
- "et131x_rx_dma_memory_alloc FAILED\n");
- et131x_adapter_memory_free(adapter);
- return status;
- }
-
- /* Init receive data structures */
- status = et131x_init_recv(adapter);
- if (status) {
- dev_err(&adapter->pdev->dev, "et131x_init_recv FAILED\n");
- et131x_adapter_memory_free(adapter);
- }
- return status;
-}
-
-static void et131x_adjust_link(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
- struct phy_device *phydev = adapter->phydev;
-
- if (!phydev)
- return;
- if (phydev->link == adapter->link)
- return;
-
- /* Check to see if we are in coma mode and if
- * so, disable it because we will not be able
- * to read PHY values until we are out.
- */
- if (et1310_in_phy_coma(adapter))
- et1310_disable_phy_coma(adapter);
-
- adapter->link = phydev->link;
- phy_print_status(phydev);
-
- if (phydev->link) {
- adapter->boot_coma = 20;
- if (phydev->speed == SPEED_10) {
- u16 register18;
-
- et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
- ®ister18);
- et131x_mii_write(adapter, phydev->addr,
- PHY_MPHY_CONTROL_REG, register18 | 0x4);
- et131x_mii_write(adapter, phydev->addr, PHY_INDEX_REG,
- register18 | 0x8402);
- et131x_mii_write(adapter, phydev->addr, PHY_DATA_REG,
- register18 | 511);
- et131x_mii_write(adapter, phydev->addr,
- PHY_MPHY_CONTROL_REG, register18);
- }
-
- et1310_config_flow_control(adapter);
-
- if (phydev->speed == SPEED_1000 &&
- adapter->registry_jumbo_packet > 2048) {
- u16 reg;
-
- et131x_mii_read(adapter, PHY_CONFIG, ®);
- reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
- reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
- et131x_mii_write(adapter, phydev->addr, PHY_CONFIG,
- reg);
- }
-
- et131x_set_rx_dma_timer(adapter);
- et1310_config_mac_regs2(adapter);
- } else {
- adapter->boot_coma = 0;
-
- if (phydev->speed == SPEED_10) {
- u16 register18;
-
- et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
- ®ister18);
- et131x_mii_write(adapter, phydev->addr,
- PHY_MPHY_CONTROL_REG, register18 | 0x4);
- et131x_mii_write(adapter, phydev->addr,
- PHY_INDEX_REG, register18 | 0x8402);
- et131x_mii_write(adapter, phydev->addr,
- PHY_DATA_REG, register18 | 511);
- et131x_mii_write(adapter, phydev->addr,
- PHY_MPHY_CONTROL_REG, register18);
- }
-
- /* Free the packets being actively sent & stopped */
- et131x_free_busy_send_packets(adapter);
-
- /* Re-initialize the send structures */
- et131x_init_send(adapter);
-
- /* Bring the device back to the state it was during
- * init prior to autonegotiation being complete. This
- * way, when we get the auto-neg complete interrupt,
- * we can complete init by calling config_mac_regs2.
- */
- et131x_soft_reset(adapter);
-
- /* Setup ET1310 as per the documentation */
- et131x_adapter_setup(adapter);
-
- /* perform reset of tx/rx */
- et131x_disable_txrx(netdev);
- et131x_enable_txrx(netdev);
- }
-}
-
-static int et131x_mii_probe(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
- struct phy_device *phydev = NULL;
-
- phydev = phy_find_first(adapter->mii_bus);
- if (!phydev) {
- dev_err(&adapter->pdev->dev, "no PHY found\n");
- return -ENODEV;
- }
-
- phydev = phy_connect(netdev, dev_name(&phydev->dev),
- &et131x_adjust_link, PHY_INTERFACE_MODE_MII);
-
- if (IS_ERR(phydev)) {
- dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
- return PTR_ERR(phydev);
- }
-
- phydev->supported &= (SUPPORTED_10baseT_Half |
- SUPPORTED_10baseT_Full |
- SUPPORTED_100baseT_Half |
- SUPPORTED_100baseT_Full |
- SUPPORTED_Autoneg |
- SUPPORTED_MII |
- SUPPORTED_TP);
-
- if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
- phydev->supported |= SUPPORTED_1000baseT_Half |
- SUPPORTED_1000baseT_Full;
-
- phydev->advertising = phydev->supported;
- phydev->autoneg = AUTONEG_ENABLE;
- adapter->phydev = phydev;
-
- dev_info(&adapter->pdev->dev,
- "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
- phydev->drv->name, dev_name(&phydev->dev));
-
- return 0;
-}
-
-/* et131x_adapter_init
- *
- * Initialize the data structures for the et131x_adapter object and link
- * them together with the platform provided device structures.
- */
-static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
- struct pci_dev *pdev)
-{
- static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
-
- struct et131x_adapter *adapter;
-
- /* Allocate private adapter struct and copy in relevant information */
- adapter = netdev_priv(netdev);
- adapter->pdev = pci_dev_get(pdev);
- adapter->netdev = netdev;
-
- /* Initialize spinlocks here */
- spin_lock_init(&adapter->tcb_send_qlock);
- spin_lock_init(&adapter->tcb_ready_qlock);
- spin_lock_init(&adapter->rcv_lock);
-
- adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
-
- /* Set the MAC address to a default */
- ether_addr_copy(adapter->addr, default_mac);
-
- return adapter;
-}
-
-/* et131x_pci_remove
- *
- * Registered in the pci_driver structure, this function is called when the
- * PCI subsystem detects that a PCI device which matches the information
- * contained in the pci_device_id table has been removed.
- */
-static void et131x_pci_remove(struct pci_dev *pdev)
-{
- struct net_device *netdev = pci_get_drvdata(pdev);
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- unregister_netdev(netdev);
- netif_napi_del(&adapter->napi);
- phy_disconnect(adapter->phydev);
- mdiobus_unregister(adapter->mii_bus);
- kfree(adapter->mii_bus->irq);
- mdiobus_free(adapter->mii_bus);
-
- et131x_adapter_memory_free(adapter);
- iounmap(adapter->regs);
- pci_dev_put(pdev);
-
- free_netdev(netdev);
- pci_release_regions(pdev);
- pci_disable_device(pdev);
-}
-
-/* et131x_up - Bring up a device for use. */
-static void et131x_up(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- et131x_enable_txrx(netdev);
- phy_start(adapter->phydev);
-}
-
-/* et131x_down - Bring down the device */
-static void et131x_down(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- /* Save the timestamp for the TX watchdog, prevent a timeout */
- netdev->trans_start = jiffies;
-
- phy_stop(adapter->phydev);
- et131x_disable_txrx(netdev);
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int et131x_suspend(struct device *dev)
-{
- struct pci_dev *pdev = to_pci_dev(dev);
- struct net_device *netdev = pci_get_drvdata(pdev);
-
- if (netif_running(netdev)) {
- netif_device_detach(netdev);
- et131x_down(netdev);
- pci_save_state(pdev);
- }
-
- return 0;
-}
-
-static int et131x_resume(struct device *dev)
-{
- struct pci_dev *pdev = to_pci_dev(dev);
- struct net_device *netdev = pci_get_drvdata(pdev);
-
- if (netif_running(netdev)) {
- pci_restore_state(pdev);
- et131x_up(netdev);
- netif_device_attach(netdev);
- }
-
- return 0;
-}
-
-static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
-#define ET131X_PM_OPS (&et131x_pm_ops)
-#else
-#define ET131X_PM_OPS NULL
-#endif
-
-/* et131x_isr - The Interrupt Service Routine for the driver.
- * @irq: the IRQ on which the interrupt was received.
- * @dev_id: device-specific info (here a pointer to a net_device struct)
- *
- * Returns a value indicating if the interrupt was handled.
- */
-static irqreturn_t et131x_isr(int irq, void *dev_id)
-{
- bool handled = true;
- bool enable_interrupts = true;
- struct net_device *netdev = (struct net_device *)dev_id;
- struct et131x_adapter *adapter = netdev_priv(netdev);
- struct address_map __iomem *iomem = adapter->regs;
- struct rx_ring *rx_ring = &adapter->rx_ring;
- struct tx_ring *tx_ring = &adapter->tx_ring;
- u32 status;
-
- if (!netif_device_present(netdev)) {
- handled = false;
- enable_interrupts = false;
- goto out;
- }
-
- /* If the adapter is in low power state, then it should not
- * recognize any interrupt
- */
-
- /* Disable Device Interrupts */
- et131x_disable_interrupts(adapter);
-
- /* Get a copy of the value in the interrupt status register
- * so we can process the interrupting section
- */
- status = readl(&adapter->regs->global.int_status);
-
- if (adapter->flow == FLOW_TXONLY || adapter->flow == FLOW_BOTH)
- status &= ~INT_MASK_ENABLE;
- else
- status &= ~INT_MASK_ENABLE_NO_FLOW;
-
- /* Make sure this is our interrupt */
- if (!status) {
- handled = false;
- et131x_enable_interrupts(adapter);
- goto out;
- }
-
- /* This is our interrupt, so process accordingly */
- if (status & ET_INTR_WATCHDOG) {
- struct tcb *tcb = tx_ring->send_head;
-
- if (tcb)
- if (++tcb->stale > 1)
- status |= ET_INTR_TXDMA_ISR;
-
- if (rx_ring->unfinished_receives)
- status |= ET_INTR_RXDMA_XFR_DONE;
- else if (tcb == NULL)
- writel(0, &adapter->regs->global.watchdog_timer);
-
- status &= ~ET_INTR_WATCHDOG;
- }
-
- if (status & (ET_INTR_RXDMA_XFR_DONE | ET_INTR_TXDMA_ISR)) {
- enable_interrupts = false;
- napi_schedule(&adapter->napi);
- }
-
- status &= ~(ET_INTR_TXDMA_ISR | ET_INTR_RXDMA_XFR_DONE);
-
- if (!status)
- goto out;
-
- /* Handle the TXDMA Error interrupt */
- if (status & ET_INTR_TXDMA_ERR) {
- /* Following read also clears the register (COR) */
- u32 txdma_err = readl(&iomem->txdma.tx_dma_error);
-
- dev_warn(&adapter->pdev->dev,
- "TXDMA_ERR interrupt, error = %d\n",
- txdma_err);
- }
-
- /* Handle Free Buffer Ring 0 and 1 Low interrupt */
- if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
- /* This indicates the number of unused buffers in RXDMA free
- * buffer ring 0 is <= the limit you programmed. Free buffer
- * resources need to be returned. Free buffers are consumed as
- * packets are passed from the network to the host. The host
- * becomes aware of the packets from the contents of the packet
- * status ring. This ring is queried when the packet done
- * interrupt occurs. Packets are then passed to the OS. When
- * the OS is done with the packets the resources can be
- * returned to the ET1310 for re-use. This interrupt is one
- * method of returning resources.
- */
-
- /* If the user has flow control on, then we will
- * send a pause packet, otherwise just exit
- */
- if (adapter->flow == FLOW_TXONLY || adapter->flow == FLOW_BOTH) {
- u32 pm_csr;
-
- /* Tell the device to send a pause packet via the back
- * pressure register (bp req and bp xon/xoff)
- */
- pm_csr = readl(&iomem->global.pm_csr);
- if (!et1310_in_phy_coma(adapter))
- writel(3, &iomem->txmac.bp_ctrl);
- }
- }
-
- /* Handle Packet Status Ring Low Interrupt */
- if (status & ET_INTR_RXDMA_STAT_LOW) {
- /* Same idea as with the two Free Buffer Rings. Packets going
- * from the network to the host each consume a free buffer
- * resource and a packet status resource. These resources are
- * passed to the OS. When the OS is done with the resources,
- * they need to be returned to the ET1310. This is one method
- * of returning the resources.
- */
- }
-
- /* Handle RXDMA Error Interrupt */
- if (status & ET_INTR_RXDMA_ERR) {
- /* The rxdma_error interrupt is sent when a time-out on a
- * request issued by the JAGCore has occurred or a completion is
- * returned with an un-successful status. In both cases the
- * request is considered complete. The JAGCore will
- * automatically re-try the request in question. Normally
- * information on events like these are sent to the host using
- * the "Advanced Error Reporting" capability. This interrupt is
- * another way of getting similar information. The only thing
- * required is to clear the interrupt by reading the ISR in the
- * global resources. The JAGCore will do a re-try on the
- * request. Normally you should never see this interrupt. If
- * you start to see this interrupt occurring frequently then
- * something bad has occurred. A reset might be the thing to do.
- */
- /* TRAP();*/
-
- dev_warn(&adapter->pdev->dev,
- "RxDMA_ERR interrupt, error %x\n",
- readl(&iomem->txmac.tx_test));
- }
-
- /* Handle the Wake on LAN Event */
- if (status & ET_INTR_WOL) {
- /* This is a secondary interrupt for wake on LAN. The driver
- * should never see this, if it does, something serious is
- * wrong. We will TRAP the message when we are in DBG mode,
- * otherwise we will ignore it.
- */
- dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
- }
-
- /* Let's move on to the TxMac */
- if (status & ET_INTR_TXMAC) {
- u32 err = readl(&iomem->txmac.err);
-
- /* When any of the errors occur and TXMAC generates an
- * interrupt to report these errors, it usually means that
- * TXMAC has detected an error in the data stream retrieved
- * from the on-chip Tx Q. All of these errors are catastrophic
- * and TXMAC won't be able to recover data when these errors
- * occur. In a nutshell, the whole Tx path will have to be reset
- * and re-configured afterwards.
- */
- dev_warn(&adapter->pdev->dev,
- "TXMAC interrupt, error 0x%08x\n",
- err);
-
- /* If we are debugging, we want to see this error, otherwise we
- * just want the device to be reset and continue
- */
- }
-
- /* Handle RXMAC Interrupt */
- if (status & ET_INTR_RXMAC) {
- /* These interrupts are catastrophic to the device, what we need
- * to do is disable the interrupts and set the flag to cause us
- * to reset so we can solve this issue.
- */
- /* MP_SET_FLAG( adapter, FMP_ADAPTER_HARDWARE_ERROR); */
-
- dev_warn(&adapter->pdev->dev,
- "RXMAC interrupt, error 0x%08x. Requesting reset\n",
- readl(&iomem->rxmac.err_reg));
-
- dev_warn(&adapter->pdev->dev,
- "Enable 0x%08x, Diag 0x%08x\n",
- readl(&iomem->rxmac.ctrl),
- readl(&iomem->rxmac.rxq_diag));
-
- /* If we are debugging, we want to see this error, otherwise we
- * just want the device to be reset and continue
- */
- }
-
- /* Handle MAC_STAT Interrupt */
- if (status & ET_INTR_MAC_STAT) {
- /* This means at least one of the un-masked counters in the
- * MAC_STAT block has rolled over. Use this to maintain the top,
- * software managed bits of the counter(s).
- */
- et1310_handle_macstat_interrupt(adapter);
- }
-
- /* Handle SLV Timeout Interrupt */
- if (status & ET_INTR_SLV_TIMEOUT) {
- /* This means a timeout has occurred on a read or write request
- * to one of the JAGCore registers. The Global Resources block
- * has terminated the request and on a read request, returned a
- * "fake" value. The most likely reasons are: Bad Address or the
- * addressed module is in a power-down state and can't respond.
- */
- }
-
-out:
- if (enable_interrupts)
- et131x_enable_interrupts(adapter);
-
- return IRQ_RETVAL(handled);
-}
-
-static int et131x_poll(struct napi_struct *napi, int budget)
-{
- struct et131x_adapter *adapter =
- container_of(napi, struct et131x_adapter, napi);
- int work_done = et131x_handle_recv_pkts(adapter, budget);
-
- et131x_handle_send_pkts(adapter);
-
- if (work_done < budget) {
- napi_complete(&adapter->napi);
- et131x_enable_interrupts(adapter);
- }
-
- return work_done;
-}
-
-/* et131x_stats - Return the current device statistics */
-static struct net_device_stats *et131x_stats(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
- struct net_device_stats *stats = &adapter->netdev->stats;
- struct ce_stats *devstat = &adapter->stats;
-
- stats->rx_errors = devstat->rx_length_errs +
- devstat->rx_align_errs +
- devstat->rx_crc_errs +
- devstat->rx_code_violations +
- devstat->rx_other_errs;
- stats->tx_errors = devstat->tx_max_pkt_errs;
- stats->multicast = devstat->multicast_pkts_rcvd;
- stats->collisions = devstat->tx_collisions;
-
- stats->rx_length_errors = devstat->rx_length_errs;
- stats->rx_over_errors = devstat->rx_overflows;
- stats->rx_crc_errors = devstat->rx_crc_errs;
- stats->rx_dropped = devstat->rcvd_pkts_dropped;
-
- /* NOTE: Not used, can't find analogous statistics */
- /* stats->rx_frame_errors = devstat->; */
- /* stats->rx_fifo_errors = devstat->; */
- /* stats->rx_missed_errors = devstat->; */
-
- /* stats->tx_aborted_errors = devstat->; */
- /* stats->tx_carrier_errors = devstat->; */
- /* stats->tx_fifo_errors = devstat->; */
- /* stats->tx_heartbeat_errors = devstat->; */
- /* stats->tx_window_errors = devstat->; */
- return stats;
-}
-
-/* et131x_open - Open the device for use. */
-static int et131x_open(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
- struct pci_dev *pdev = adapter->pdev;
- unsigned int irq = pdev->irq;
- int result;
-
- /* Start the timer to track NIC errors */
- init_timer(&adapter->error_timer);
- adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
- adapter->error_timer.function = et131x_error_timer_handler;
- adapter->error_timer.data = (unsigned long)adapter;
- add_timer(&adapter->error_timer);
-
- result = request_irq(irq, et131x_isr,
- IRQF_SHARED, netdev->name, netdev);
- if (result) {
- dev_err(&pdev->dev, "could not register IRQ %d\n", irq);
- return result;
- }
-
- adapter->flags |= FMP_ADAPTER_INTERRUPT_IN_USE;
-
- napi_enable(&adapter->napi);
-
- et131x_up(netdev);
-
- return result;
-}
-
-/* et131x_close - Close the device */
-static int et131x_close(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- et131x_down(netdev);
- napi_disable(&adapter->napi);
-
- adapter->flags &= ~FMP_ADAPTER_INTERRUPT_IN_USE;
- free_irq(adapter->pdev->irq, netdev);
-
- /* Stop the error timer */
- return del_timer_sync(&adapter->error_timer);
-}
-
-/* et131x_ioctl - The I/O Control handler for the driver
- * @netdev: device on which the control request is being made
- * @reqbuf: a pointer to the IOCTL request buffer
- * @cmd: the IOCTL command code
- */
-static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf,
- int cmd)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- if (!adapter->phydev)
- return -EINVAL;
-
- return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
-}
-
-/* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
- * @adapter: pointer to our private adapter structure
- *
- * FIXME: lot of dups with MAC code
- */
-static int et131x_set_packet_filter(struct et131x_adapter *adapter)
-{
- int filter = adapter->packet_filter;
- u32 ctrl;
- u32 pf_ctrl;
-
- ctrl = readl(&adapter->regs->rxmac.ctrl);
- pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
-
- /* Default to disabled packet filtering. Enable it in the individual
- * case statements that require the device to filter something
- */
- ctrl |= 0x04;
-
- /* Set us to be in promiscuous mode so we receive everything, this
- * is also true when we get a packet filter of 0
- */
- if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
- pf_ctrl &= ~7; /* Clear filter bits */
- else {
- /* Set us up with Multicast packet filtering. Three cases are
- * possible - (1) we have a multi-cast list, (2) we receive ALL
- * multicast entries or (3) we receive none.
- */
- if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
- pf_ctrl &= ~2; /* Multicast filter bit */
- else {
- et1310_setup_device_for_multicast(adapter);
- pf_ctrl |= 2;
- ctrl &= ~0x04;
- }
-
- /* Set us up with Unicast packet filtering */
- if (filter & ET131X_PACKET_TYPE_DIRECTED) {
- et1310_setup_device_for_unicast(adapter);
- pf_ctrl |= 4;
- ctrl &= ~0x04;
- }
-
- /* Set us up with Broadcast packet filtering */
- if (filter & ET131X_PACKET_TYPE_BROADCAST) {
- pf_ctrl |= 1; /* Broadcast filter bit */
- ctrl &= ~0x04;
- } else {
- pf_ctrl &= ~1;
- }
-
- /* Setup the receive mac configuration registers - Packet
- * Filter control + the enable / disable for packet filter
- * in the control reg.
- */
- writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
- writel(ctrl, &adapter->regs->rxmac.ctrl);
- }
- return 0;
-}
-
-/* et131x_multicast - The handler to configure multicasting on the interface */
-static void et131x_multicast(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
- int packet_filter;
- struct netdev_hw_addr *ha;
- int i;
-
- /* Before we modify the platform-independent filter flags, store them
- * locally. This allows us to determine if anything's changed and if
- * we even need to bother the hardware
- */
- packet_filter = adapter->packet_filter;
-
- /* Clear the 'multicast' flag locally; because we only have a single
- * flag to check multicast, and multiple multicast addresses can be
- * set, this is the easiest way to determine if more than one
- * multicast address is being set.
- */
- packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
-
- /* Check the net_device flags and set the device independent flags
- * accordingly
- */
- if (netdev->flags & IFF_PROMISC)
- adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
- else
- adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
-
- if ((netdev->flags & IFF_ALLMULTI) ||
- (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST))
- adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
-
- if (netdev_mc_count(netdev) < 1) {
- adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
- adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
- } else {
- adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
- }
-
- /* Set values in the private adapter struct */
- i = 0;
- netdev_for_each_mc_addr(ha, netdev) {
- if (i == NIC_MAX_MCAST_LIST)
- break;
- memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
- }
- adapter->multicast_addr_count = i;
-
- /* Are the new flags different from the previous ones? If not, then no
- * action is required
- *
- * NOTE - This block will always update the multicast_list with the
- * hardware, even if the addresses aren't the same.
- */
- if (packet_filter != adapter->packet_filter)
- et131x_set_packet_filter(adapter);
-}
-
-/* et131x_tx - The handler to tx a packet on the device */
-static netdev_tx_t et131x_tx(struct sk_buff *skb, struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
- struct tx_ring *tx_ring = &adapter->tx_ring;
-
- /* stop the queue if it's getting full */
- if (tx_ring->used >= NUM_TCB - 1 && !netif_queue_stopped(netdev))
- netif_stop_queue(netdev);
-
- /* Save the timestamp for the TX timeout watchdog */
- netdev->trans_start = jiffies;
-
- /* TCB is not available */
- if (tx_ring->used >= NUM_TCB)
- goto drop_err;
-
- if ((adapter->flags & FMP_ADAPTER_FAIL_SEND_MASK) ||
- !netif_carrier_ok(netdev))
- goto drop_err;
-
- if (send_packet(skb, adapter))
- goto drop_err;
-
- return NETDEV_TX_OK;
-
-drop_err:
- dev_kfree_skb_any(skb);
- adapter->netdev->stats.tx_dropped++;
- return NETDEV_TX_OK;
-}
-
-/* et131x_tx_timeout - Timeout handler
- *
- * The handler called when a Tx request times out. The timeout period is
- * specified by the 'tx_timeo" element in the net_device structure (see
- * et131x_alloc_device() to see how this value is set).
- */
-static void et131x_tx_timeout(struct net_device *netdev)
-{
- struct et131x_adapter *adapter = netdev_priv(netdev);
- struct tx_ring *tx_ring = &adapter->tx_ring;
- struct tcb *tcb;
- unsigned long flags;
-
- /* If the device is closed, ignore the timeout */
- if (~(adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE))
- return;
-
- /* Any nonrecoverable hardware error?
- * Checks adapter->flags for any failure in phy reading
- */
- if (adapter->flags & FMP_ADAPTER_NON_RECOVER_ERROR)
- return;
-
- /* Hardware failure? */
- if (adapter->flags & FMP_ADAPTER_HARDWARE_ERROR) {
- dev_err(&adapter->pdev->dev, "hardware error - reset\n");
- return;
- }
-
- /* Is send stuck? */
- spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
- tcb = tx_ring->send_head;
- spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
-
- if (tcb) {
- tcb->count++;
-
- if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
- dev_warn(&adapter->pdev->dev,
- "Send stuck - reset. tcb->WrIndex %x\n",
- tcb->index);
-
- adapter->netdev->stats.tx_errors++;
-
- /* perform reset of tx/rx */
- et131x_disable_txrx(netdev);
- et131x_enable_txrx(netdev);
- }
- }
-}
-
-/* et131x_change_mtu - The handler called to change the MTU for the device */
-static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
-{
- int result = 0;
- struct et131x_adapter *adapter = netdev_priv(netdev);
-
- /* Make sure the requested MTU is valid */
- if (new_mtu < 64 || new_mtu > 9216)
- return -EINVAL;
-
- et131x_disable_txrx(netdev);
-
- /* Set the new MTU */
- netdev->mtu = new_mtu;
-
- /* Free Rx DMA memory */
- et131x_adapter_memory_free(adapter);
-
- /* Set the config parameter for Jumbo Packet support */
- adapter->registry_jumbo_packet = new_mtu + 14;
- et131x_soft_reset(adapter);
-
- /* Alloc and init Rx DMA memory */
- result = et131x_adapter_memory_alloc(adapter);
- if (result != 0) {
- dev_warn(&adapter->pdev->dev,
- "Change MTU failed; couldn't re-alloc DMA memory\n");
- return result;
- }
-
- et131x_init_send(adapter);
-
- et131x_hwaddr_init(adapter);
- memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
-
- /* Init the device with the new settings */
- et131x_adapter_setup(adapter);
- et131x_enable_txrx(netdev);
-
- return result;
-}
-
-static const struct net_device_ops et131x_netdev_ops = {
- .ndo_open = et131x_open,
- .ndo_stop = et131x_close,
- .ndo_start_xmit = et131x_tx,
- .ndo_set_rx_mode = et131x_multicast,
- .ndo_tx_timeout = et131x_tx_timeout,
- .ndo_change_mtu = et131x_change_mtu,
- .ndo_set_mac_address = eth_mac_addr,
- .ndo_validate_addr = eth_validate_addr,
- .ndo_get_stats = et131x_stats,
- .ndo_do_ioctl = et131x_ioctl,
-};
-
-/* et131x_pci_setup - Perform device initialization
- * @pdev: a pointer to the device's pci_dev structure
- * @ent: this device's entry in the pci_device_id table
- *
- * Registered in the pci_driver structure, this function is called when the
- * PCI subsystem finds a new PCI device which matches the information
- * contained in the pci_device_id table. This routine is the equivalent to
- * a device insertion routine.
- */
-static int et131x_pci_setup(struct pci_dev *pdev,
- const struct pci_device_id *ent)
-{
- struct net_device *netdev;
- struct et131x_adapter *adapter;
- int rc;
- int ii;
-
- rc = pci_enable_device(pdev);
- if (rc < 0) {
- dev_err(&pdev->dev, "pci_enable_device() failed\n");
- goto out;
- }
-
- /* Perform some basic PCI checks */
- if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
- dev_err(&pdev->dev, "Can't find PCI device's base address\n");
- rc = -ENODEV;
- goto err_disable;
- }
-
- rc = pci_request_regions(pdev, DRIVER_NAME);
- if (rc < 0) {
- dev_err(&pdev->dev, "Can't get PCI resources\n");
- goto err_disable;
- }
-
- pci_set_master(pdev);
-
- /* Check the DMA addressing support of this device */
- if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
- dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
- dev_err(&pdev->dev, "No usable DMA addressing method\n");
- rc = -EIO;
- goto err_release_res;
- }
-
- /* Allocate netdev and private adapter structs */
- netdev = alloc_etherdev(sizeof(struct et131x_adapter));
- if (!netdev) {
- dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
- rc = -ENOMEM;
- goto err_release_res;
- }
-
- netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
- netdev->netdev_ops = &et131x_netdev_ops;
-
- SET_NETDEV_DEV(netdev, &pdev->dev);
- netdev->ethtool_ops = &et131x_ethtool_ops;
-
- adapter = et131x_adapter_init(netdev, pdev);
-
- rc = et131x_pci_init(adapter, pdev);
- if (rc < 0)
- goto err_free_dev;
-
- /* Map the bus-relative registers to system virtual memory */
- adapter->regs = pci_ioremap_bar(pdev, 0);
- if (!adapter->regs) {
- dev_err(&pdev->dev, "Cannot map device registers\n");
- rc = -ENOMEM;
- goto err_free_dev;
- }
-
- /* If Phy COMA mode was enabled when we went down, disable it here. */
- writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
-
- /* Issue a global reset to the et1310 */
- et131x_soft_reset(adapter);
-
- /* Disable all interrupts (paranoid) */
- et131x_disable_interrupts(adapter);
-
- /* Allocate DMA memory */
- rc = et131x_adapter_memory_alloc(adapter);
- if (rc < 0) {
- dev_err(&pdev->dev, "Could not alloc adapter memory (DMA)\n");
- goto err_iounmap;
- }
-
- /* Init send data structures */
- et131x_init_send(adapter);
-
- netif_napi_add(netdev, &adapter->napi, et131x_poll, 64);
-
- /* Copy address into the net_device struct */
- memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
-
- rc = -ENOMEM;
-
- /* Setup the mii_bus struct */
- adapter->mii_bus = mdiobus_alloc();
- if (!adapter->mii_bus) {
- dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
- goto err_mem_free;
- }
-
- adapter->mii_bus->name = "et131x_eth_mii";
- snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
- (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
- adapter->mii_bus->priv = netdev;
- adapter->mii_bus->read = et131x_mdio_read;
- adapter->mii_bus->write = et131x_mdio_write;
- adapter->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int),
- GFP_KERNEL);
- if (!adapter->mii_bus->irq)
- goto err_mdio_free;
-
- for (ii = 0; ii < PHY_MAX_ADDR; ii++)
- adapter->mii_bus->irq[ii] = PHY_POLL;
-
- rc = mdiobus_register(adapter->mii_bus);
- if (rc < 0) {
- dev_err(&pdev->dev, "failed to register MII bus\n");
- goto err_mdio_free_irq;
- }
-
- rc = et131x_mii_probe(netdev);
- if (rc < 0) {
- dev_err(&pdev->dev, "failed to probe MII bus\n");
- goto err_mdio_unregister;
- }
-
- /* Setup et1310 as per the documentation */
- et131x_adapter_setup(adapter);
-
- /* Init variable for counting how long we do not have link status */
- adapter->boot_coma = 0;
- et1310_disable_phy_coma(adapter);
-
- /* We can enable interrupts now
- *
- * NOTE - Because registration of interrupt handler is done in the
- * device's open(), defer enabling device interrupts to that
- * point
- */
-
- /* Register the net_device struct with the Linux network layer */
- rc = register_netdev(netdev);
- if (rc < 0) {
- dev_err(&pdev->dev, "register_netdev() failed\n");
- goto err_phy_disconnect;
- }
-
- /* Register the net_device struct with the PCI subsystem. Save a copy
- * of the PCI config space for this device now that the device has
- * been initialized, just in case it needs to be quickly restored.
- */
- pci_set_drvdata(pdev, netdev);
-out:
- return rc;
-
-err_phy_disconnect:
- phy_disconnect(adapter->phydev);
-err_mdio_unregister:
- mdiobus_unregister(adapter->mii_bus);
-err_mdio_free_irq:
- kfree(adapter->mii_bus->irq);
-err_mdio_free:
- mdiobus_free(adapter->mii_bus);
-err_mem_free:
- et131x_adapter_memory_free(adapter);
-err_iounmap:
- iounmap(adapter->regs);
-err_free_dev:
- pci_dev_put(pdev);
- free_netdev(netdev);
-err_release_res:
- pci_release_regions(pdev);
-err_disable:
- pci_disable_device(pdev);
- goto out;
-}
-
-static const struct pci_device_id et131x_pci_table[] = {
- { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
- { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
- {0,}
-};
-MODULE_DEVICE_TABLE(pci, et131x_pci_table);
-
-static struct pci_driver et131x_driver = {
- .name = DRIVER_NAME,
- .id_table = et131x_pci_table,
- .probe = et131x_pci_setup,
- .remove = et131x_pci_remove,
- .driver.pm = ET131X_PM_OPS,
-};
-
-module_pci_driver(et131x_driver);
diff --git a/drivers/staging/et131x/et131x.h b/drivers/staging/et131x/et131x.h
deleted file mode 100644
index 0727523..0000000
--- a/drivers/staging/et131x/et131x.h
+++ /dev/null
@@ -1,1533 +0,0 @@
-/*
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- * http://www.agere.com
- *
- * SOFTWARE LICENSE
- *
- * This software is provided subject to the following terms and conditions,
- * which you should read carefully before using the software. Using this
- * software indicates your acceptance of these terms and conditions. If you do
- * not agree with these terms and conditions, do not use the software.
- *
- * Copyright © 2005 Agere Systems Inc.
- * All rights reserved.
- *
- * Redistribution and use in source or binary forms, with or without
- * modifications, are permitted provided that the following conditions are met:
- *
- * . Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following Disclaimer as comments in the code as
- * well as in the documentation and/or other materials provided with the
- * distribution.
- *
- * . Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following Disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * . Neither the name of Agere Systems Inc. nor the names of the contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * Disclaimer
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
- * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
- * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGE.
- *
- */
-
-#define DRIVER_NAME "et131x"
-#define DRIVER_VERSION "v2.0"
-
-/* EEPROM registers */
-
-/* LBCIF Register Groups (addressed via 32-bit offsets) */
-#define LBCIF_DWORD0_GROUP 0xAC
-#define LBCIF_DWORD1_GROUP 0xB0
-
-/* LBCIF Registers (addressed via 8-bit offsets) */
-#define LBCIF_ADDRESS_REGISTER 0xAC
-#define LBCIF_DATA_REGISTER 0xB0
-#define LBCIF_CONTROL_REGISTER 0xB1
-#define LBCIF_STATUS_REGISTER 0xB2
-
-/* LBCIF Control Register Bits */
-#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
-#define LBCIF_CONTROL_PAGE_WRITE 0x02
-#define LBCIF_CONTROL_EEPROM_RELOAD 0x08
-#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
-#define LBCIF_CONTROL_I2C_WRITE 0x40
-#define LBCIF_CONTROL_LBCIF_ENABLE 0x80
-
-/* LBCIF Status Register Bits */
-#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
-#define LBCIF_STATUS_I2C_IDLE 0x02
-#define LBCIF_STATUS_ACK_ERROR 0x04
-#define LBCIF_STATUS_GENERAL_ERROR 0x08
-#define LBCIF_STATUS_CHECKSUM_ERROR 0x40
-#define LBCIF_STATUS_EEPROM_PRESENT 0x80
-
-/* START OF GLOBAL REGISTER ADDRESS MAP */
-/*
- * 10bit registers
- *
- * Tx queue start address reg in global address map at address 0x0000
- * tx queue end address reg in global address map at address 0x0004
- * rx queue start address reg in global address map at address 0x0008
- * rx queue end address reg in global address map at address 0x000C
- */
-
-/*
- * structure for power management control status reg in global address map
- * located at address 0x0010
- * jagcore_rx_rdy bit 9
- * jagcore_tx_rdy bit 8
- * phy_lped_en bit 7
- * phy_sw_coma bit 6
- * rxclk_gate bit 5
- * txclk_gate bit 4
- * sysclk_gate bit 3
- * jagcore_rx_en bit 2
- * jagcore_tx_en bit 1
- * gigephy_en bit 0
- */
-#define ET_PM_PHY_SW_COMA 0x40
-#define ET_PMCSR_INIT 0x38
-
-/*
- * Interrupt status reg at address 0x0018
- */
-#define ET_INTR_TXDMA_ISR 0x00000008
-#define ET_INTR_TXDMA_ERR 0x00000010
-#define ET_INTR_RXDMA_XFR_DONE 0x00000020
-#define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
-#define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
-#define ET_INTR_RXDMA_STAT_LOW 0x00000100
-#define ET_INTR_RXDMA_ERR 0x00000200
-#define ET_INTR_WATCHDOG 0x00004000
-#define ET_INTR_WOL 0x00008000
-#define ET_INTR_PHY 0x00010000
-#define ET_INTR_TXMAC 0x00020000
-#define ET_INTR_RXMAC 0x00040000
-#define ET_INTR_MAC_STAT 0x00080000
-#define ET_INTR_SLV_TIMEOUT 0x00100000
-
-/*
- * Interrupt mask register at address 0x001C
- * Interrupt alias clear mask reg at address 0x0020
- * Interrupt status alias reg at address 0x0024
- *
- * Same masks as above
- */
-
-/*
- * Software reset reg at address 0x0028
- * 0: txdma_sw_reset
- * 1: rxdma_sw_reset
- * 2: txmac_sw_reset
- * 3: rxmac_sw_reset
- * 4: mac_sw_reset
- * 5: mac_stat_sw_reset
- * 6: mmc_sw_reset
- *31: selfclr_disable
- */
-#define ET_RESET_ALL 0x007F
-
-/*
- * SLV Timer reg at address 0x002C (low 24 bits)
- */
-
-/*
- * MSI Configuration reg at address 0x0030
- */
-#define ET_MSI_VECTOR 0x0000001F
-#define ET_MSI_TC 0x00070000
-
-/*
- * Loopback reg located at address 0x0034
- */
-#define ET_LOOP_MAC 0x00000001
-#define ET_LOOP_DMA 0x00000002
-
-/*
- * GLOBAL Module of JAGCore Address Mapping
- * Located at address 0x0000
- */
-struct global_regs { /* Location: */
- u32 txq_start_addr; /* 0x0000 */
- u32 txq_end_addr; /* 0x0004 */
- u32 rxq_start_addr; /* 0x0008 */
- u32 rxq_end_addr; /* 0x000C */
- u32 pm_csr; /* 0x0010 */
- u32 unused; /* 0x0014 */
- u32 int_status; /* 0x0018 */
- u32 int_mask; /* 0x001C */
- u32 int_alias_clr_en; /* 0x0020 */
- u32 int_status_alias; /* 0x0024 */
- u32 sw_reset; /* 0x0028 */
- u32 slv_timer; /* 0x002C */
- u32 msi_config; /* 0x0030 */
- u32 loopback; /* 0x0034 */
- u32 watchdog_timer; /* 0x0038 */
-};
-
-/* START OF TXDMA REGISTER ADDRESS MAP */
-/*
- * txdma control status reg at address 0x1000
- */
-#define ET_TXDMA_CSR_HALT 0x00000001
-#define ET_TXDMA_DROP_TLP 0x00000002
-#define ET_TXDMA_CACHE_THRS 0x000000F0
-#define ET_TXDMA_CACHE_SHIFT 4
-#define ET_TXDMA_SNGL_EPKT 0x00000100
-#define ET_TXDMA_CLASS 0x00001E00
-
-/*
- * structure for txdma packet ring base address hi reg in txdma address map
- * located at address 0x1004
- * Defined earlier (u32)
- */
-
-/*
- * structure for txdma packet ring base address low reg in txdma address map
- * located at address 0x1008
- * Defined earlier (u32)
- */
-
-/*
- * structure for txdma packet ring number of descriptor reg in txdma address
- * map. Located at address 0x100C
- *
- * 31-10: unused
- * 9-0: pr ndes
- */
-#define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
-#define ET_DMA12_WRAP 0x1000
-#define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
-#define ET_DMA10_WRAP 0x0400
-#define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
-#define ET_DMA4_WRAP 0x0010
-
-#define INDEX12(x) ((x) & ET_DMA12_MASK)
-#define INDEX10(x) ((x) & ET_DMA10_MASK)
-#define INDEX4(x) ((x) & ET_DMA4_MASK)
-
-/*
- * 10bit DMA with wrap
- * txdma tx queue write address reg in txdma address map at 0x1010
- * txdma tx queue write address external reg in txdma address map at 0x1014
- * txdma tx queue read address reg in txdma address map at 0x1018
- *
- * u32
- * txdma status writeback address hi reg in txdma address map at0x101C
- * txdma status writeback address lo reg in txdma address map at 0x1020
- *
- * 10bit DMA with wrap
- * txdma service request reg in txdma address map at 0x1024
- * structure for txdma service complete reg in txdma address map at 0x1028
- *
- * 4bit DMA with wrap
- * txdma tx descriptor cache read index reg in txdma address map at 0x102C
- * txdma tx descriptor cache write index reg in txdma address map at 0x1030
- *
- * txdma error reg in txdma address map at address 0x1034
- * 0: PyldResend
- * 1: PyldRewind
- * 4: DescrResend
- * 5: DescrRewind
- * 8: WrbkResend
- * 9: WrbkRewind
- */
-
-/*
- * Tx DMA Module of JAGCore Address Mapping
- * Located at address 0x1000
- */
-struct txdma_regs { /* Location: */
- u32 csr; /* 0x1000 */
- u32 pr_base_hi; /* 0x1004 */
- u32 pr_base_lo; /* 0x1008 */
- u32 pr_num_des; /* 0x100C */
- u32 txq_wr_addr; /* 0x1010 */
- u32 txq_wr_addr_ext; /* 0x1014 */
- u32 txq_rd_addr; /* 0x1018 */
- u32 dma_wb_base_hi; /* 0x101C */
- u32 dma_wb_base_lo; /* 0x1020 */
- u32 service_request; /* 0x1024 */
- u32 service_complete; /* 0x1028 */
- u32 cache_rd_index; /* 0x102C */
- u32 cache_wr_index; /* 0x1030 */
- u32 tx_dma_error; /* 0x1034 */
- u32 desc_abort_cnt; /* 0x1038 */
- u32 payload_abort_cnt; /* 0x103c */
- u32 writeback_abort_cnt; /* 0x1040 */
- u32 desc_timeout_cnt; /* 0x1044 */
- u32 payload_timeout_cnt; /* 0x1048 */
- u32 writeback_timeout_cnt; /* 0x104c */
- u32 desc_error_cnt; /* 0x1050 */
- u32 payload_error_cnt; /* 0x1054 */
- u32 writeback_error_cnt; /* 0x1058 */
- u32 dropped_tlp_cnt; /* 0x105c */
- u32 new_service_complete; /* 0x1060 */
- u32 ethernet_packet_cnt; /* 0x1064 */
-};
-
-/* END OF TXDMA REGISTER ADDRESS MAP */
-
-/* START OF RXDMA REGISTER ADDRESS MAP */
-/*
- * structure for control status reg in rxdma address map
- * Located at address 0x2000
- *
- * CSR
- * 0: halt
- * 1-3: tc
- * 4: fbr_big_endian
- * 5: psr_big_endian
- * 6: pkt_big_endian
- * 7: dma_big_endian
- * 8-9: fbr0_size
- * 10: fbr0_enable
- * 11-12: fbr1_size
- * 13: fbr1_enable
- * 14: unused
- * 15: pkt_drop_disable
- * 16: pkt_done_flush
- * 17: halt_status
- * 18-31: unused
- */
-#define ET_RXDMA_CSR_HALT 0x0001
-#define ET_RXDMA_CSR_FBR0_SIZE_LO 0x0100
-#define ET_RXDMA_CSR_FBR0_SIZE_HI 0x0200
-#define ET_RXDMA_CSR_FBR0_ENABLE 0x0400
-#define ET_RXDMA_CSR_FBR1_SIZE_LO 0x0800
-#define ET_RXDMA_CSR_FBR1_SIZE_HI 0x1000
-#define ET_RXDMA_CSR_FBR1_ENABLE 0x2000
-#define ET_RXDMA_CSR_HALT_STATUS 0x00020000
-
-/*
- * structure for dma writeback lo reg in rxdma address map
- * located at address 0x2004
- * Defined earlier (u32)
- */
-
-/*
- * structure for dma writeback hi reg in rxdma address map
- * located at address 0x2008
- * Defined earlier (u32)
- */
-
-/*
- * structure for number of packets done reg in rxdma address map
- * located at address 0x200C
- *
- * 31-8: unused
- * 7-0: num done
- */
-
-/*
- * structure for max packet time reg in rxdma address map
- * located at address 0x2010
- *
- * 31-18: unused
- * 17-0: time done
- */
-
-/*
- * structure for rx queue read address reg in rxdma address map
- * located at address 0x2014
- * Defined earlier (u32)
- */
-
-/*
- * structure for rx queue read address external reg in rxdma address map
- * located at address 0x2018
- * Defined earlier (u32)
- */
-
-/*
- * structure for rx queue write address reg in rxdma address map
- * located at address 0x201C
- * Defined earlier (u32)
- */
-
-/*
- * structure for packet status ring base address lo reg in rxdma address map
- * located at address 0x2020
- * Defined earlier (u32)
- */
-
-/*
- * structure for packet status ring base address hi reg in rxdma address map
- * located at address 0x2024
- * Defined earlier (u32)
- */
-
-/*
- * structure for packet status ring number of descriptors reg in rxdma address
- * map. Located at address 0x2028
- *
- * 31-12: unused
- * 11-0: psr ndes
- */
-#define ET_RXDMA_PSR_NUM_DES_MASK 0xFFF
-
-/*
- * structure for packet status ring available offset reg in rxdma address map
- * located at address 0x202C
- *
- * 31-13: unused
- * 12: psr avail wrap
- * 11-0: psr avail
- */
-
-/*
- * structure for packet status ring full offset reg in rxdma address map
- * located at address 0x2030
- *
- * 31-13: unused
- * 12: psr full wrap
- * 11-0: psr full
- */
-
-/*
- * structure for packet status ring access index reg in rxdma address map
- * located at address 0x2034
- *
- * 31-5: unused
- * 4-0: psr_ai
- */
-
-/*
- * structure for packet status ring minimum descriptors reg in rxdma address
- * map. Located at address 0x2038
- *
- * 31-12: unused
- * 11-0: psr_min
- */
-
-/*
- * structure for free buffer ring base lo address reg in rxdma address map
- * located at address 0x203C
- * Defined earlier (u32)
- */
-
-/*
- * structure for free buffer ring base hi address reg in rxdma address map
- * located at address 0x2040
- * Defined earlier (u32)
- */
-
-/*
- * structure for free buffer ring number of descriptors reg in rxdma address
- * map. Located at address 0x2044
- *
- * 31-10: unused
- * 9-0: fbr ndesc
- */
-
-/*
- * structure for free buffer ring 0 available offset reg in rxdma address map
- * located at address 0x2048
- * Defined earlier (u32)
- */
-
-/*
- * structure for free buffer ring 0 full offset reg in rxdma address map
- * located at address 0x204C
- * Defined earlier (u32)
- */
-
-/*
- * structure for free buffer cache 0 full offset reg in rxdma address map
- * located at address 0x2050
- *
- * 31-5: unused
- * 4-0: fbc rdi
- */
-
-/*
- * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
- * located at address 0x2054
- *
- * 31-10: unused
- * 9-0: fbr min
- */
-
-/*
- * structure for free buffer ring 1 base address lo reg in rxdma address map
- * located at address 0x2058 - 0x205C
- * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
- */
-
-/*
- * structure for free buffer ring 1 number of descriptors reg in rxdma address
- * map. Located at address 0x2060
- * Defined earlier (RXDMA_FBR_NUM_DES_t)
- */
-
-/*
- * structure for free buffer ring 1 available offset reg in rxdma address map
- * located at address 0x2064
- * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
- */
-
-/*
- * structure for free buffer ring 1 full offset reg in rxdma address map
- * located at address 0x2068
- * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
- */
-
-/*
- * structure for free buffer cache 1 read index reg in rxdma address map
- * located at address 0x206C
- * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
- */
-
-/*
- * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
- * located at address 0x2070
- * Defined Earlier (RXDMA_FBR_MIN_DES_t)
- */
-
-/*
- * Rx DMA Module of JAGCore Address Mapping
- * Located at address 0x2000
- */
-struct rxdma_regs { /* Location: */
- u32 csr; /* 0x2000 */
- u32 dma_wb_base_lo; /* 0x2004 */
- u32 dma_wb_base_hi; /* 0x2008 */
- u32 num_pkt_done; /* 0x200C */
- u32 max_pkt_time; /* 0x2010 */
- u32 rxq_rd_addr; /* 0x2014 */
- u32 rxq_rd_addr_ext; /* 0x2018 */
- u32 rxq_wr_addr; /* 0x201C */
- u32 psr_base_lo; /* 0x2020 */
- u32 psr_base_hi; /* 0x2024 */
- u32 psr_num_des; /* 0x2028 */
- u32 psr_avail_offset; /* 0x202C */
- u32 psr_full_offset; /* 0x2030 */
- u32 psr_access_index; /* 0x2034 */
- u32 psr_min_des; /* 0x2038 */
- u32 fbr0_base_lo; /* 0x203C */
- u32 fbr0_base_hi; /* 0x2040 */
- u32 fbr0_num_des; /* 0x2044 */
- u32 fbr0_avail_offset; /* 0x2048 */
- u32 fbr0_full_offset; /* 0x204C */
- u32 fbr0_rd_index; /* 0x2050 */
- u32 fbr0_min_des; /* 0x2054 */
- u32 fbr1_base_lo; /* 0x2058 */
- u32 fbr1_base_hi; /* 0x205C */
- u32 fbr1_num_des; /* 0x2060 */
- u32 fbr1_avail_offset; /* 0x2064 */
- u32 fbr1_full_offset; /* 0x2068 */
- u32 fbr1_rd_index; /* 0x206C */
- u32 fbr1_min_des; /* 0x2070 */
-};
-
-/* END OF RXDMA REGISTER ADDRESS MAP */
-
-/* START OF TXMAC REGISTER ADDRESS MAP */
-/*
- * structure for control reg in txmac address map
- * located at address 0x3000
- *
- * bits
- * 31-8: unused
- * 7: cklseg_disable
- * 6: ckbcnt_disable
- * 5: cksegnum
- * 4: async_disable
- * 3: fc_disable
- * 2: mcif_disable
- * 1: mif_disable
- * 0: txmac_en
- */
-#define ET_TX_CTRL_FC_DISABLE 0x0008
-#define ET_TX_CTRL_TXMAC_ENABLE 0x0001
-
-/*
- * structure for shadow pointer reg in txmac address map
- * located at address 0x3004
- * 31-27: reserved
- * 26-16: txq rd ptr
- * 15-11: reserved
- * 10-0: txq wr ptr
- */
-
-/*
- * structure for error count reg in txmac address map
- * located at address 0x3008
- *
- * 31-12: unused
- * 11-8: reserved
- * 7-4: txq_underrun
- * 3-0: fifo_underrun
- */
-
-/*
- * structure for max fill reg in txmac address map
- * located at address 0x300C
- * 31-12: unused
- * 11-0: max fill
- */
-
-/*
- * structure for cf parameter reg in txmac address map
- * located at address 0x3010
- * 31-16: cfep
- * 15-0: cfpt
- */
-
-/*
- * structure for tx test reg in txmac address map
- * located at address 0x3014
- * 31-17: unused
- * 16: reserved
- * 15: txtest_en
- * 14-11: unused
- * 10-0: txq test pointer
- */
-
-/*
- * structure for error reg in txmac address map
- * located at address 0x3018
- *
- * 31-9: unused
- * 8: fifo_underrun
- * 7-6: unused
- * 5: ctrl2_err
- * 4: txq_underrun
- * 3: bcnt_err
- * 2: lseg_err
- * 1: segnum_err
- * 0: seg0_err
- */
-
-/*
- * structure for error interrupt reg in txmac address map
- * located at address 0x301C
- *
- * 31-9: unused
- * 8: fifo_underrun
- * 7-6: unused
- * 5: ctrl2_err
- * 4: txq_underrun
- * 3: bcnt_err
- * 2: lseg_err
- * 1: segnum_err
- * 0: seg0_err
- */
-
-/*
- * structure for error interrupt reg in txmac address map
- * located at address 0x3020
- *
- * 31-2: unused
- * 1: bp_req
- * 0: bp_xonxoff
- */
-
-/*
- * Tx MAC Module of JAGCore Address Mapping
- */
-struct txmac_regs { /* Location: */
- u32 ctl; /* 0x3000 */
- u32 shadow_ptr; /* 0x3004 */
- u32 err_cnt; /* 0x3008 */
- u32 max_fill; /* 0x300C */
- u32 cf_param; /* 0x3010 */
- u32 tx_test; /* 0x3014 */
- u32 err; /* 0x3018 */
- u32 err_int; /* 0x301C */
- u32 bp_ctrl; /* 0x3020 */
-};
-
-/* END OF TXMAC REGISTER ADDRESS MAP */
-
-/* START OF RXMAC REGISTER ADDRESS MAP */
-
-/*
- * structure for rxmac control reg in rxmac address map
- * located at address 0x4000
- *
- * 31-7: reserved
- * 6: rxmac_int_disable
- * 5: async_disable
- * 4: mif_disable
- * 3: wol_disable
- * 2: pkt_filter_disable
- * 1: mcif_disable
- * 0: rxmac_en
- */
-#define ET_RX_CTRL_WOL_DISABLE 0x0008
-#define ET_RX_CTRL_RXMAC_ENABLE 0x0001
-
-/*
- * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
- * located at address 0x4004
- * 31-16: crc
- * 15-12: reserved
- * 11: ignore_pp
- * 10: ignore_mp
- * 9: clr_intr
- * 8: ignore_link_chg
- * 7: ignore_uni
- * 6: ignore_multi
- * 5: ignore_broad
- * 4-0: valid_crc 4-0
- */
-
-/*
- * structure for CRC 1 and CRC 2 reg in rxmac address map
- * located at address 0x4008
- *
- * 31-16: crc2
- * 15-0: crc1
- */
-
-/*
- * structure for CRC 3 and CRC 4 reg in rxmac address map
- * located at address 0x400C
- *
- * 31-16: crc4
- * 15-0: crc3
- */
-
-/*
- * structure for Wake On Lan Source Address Lo reg in rxmac address map
- * located at address 0x4010
- *
- * 31-24: sa3
- * 23-16: sa4
- * 15-8: sa5
- * 7-0: sa6
- */
-#define ET_RX_WOL_LO_SA3_SHIFT 24
-#define ET_RX_WOL_LO_SA4_SHIFT 16
-#define ET_RX_WOL_LO_SA5_SHIFT 8
-
-/*
- * structure for Wake On Lan Source Address Hi reg in rxmac address map
- * located at address 0x4014
- *
- * 31-16: reserved
- * 15-8: sa1
- * 7-0: sa2
- */
-#define ET_RX_WOL_HI_SA1_SHIFT 8
-
-/*
- * structure for Wake On Lan mask reg in rxmac address map
- * located at address 0x4018 - 0x4064
- * Defined earlier (u32)
- */
-
-/*
- * structure for Unicast Packet Filter Address 1 reg in rxmac address map
- * located at address 0x4068
- *
- * 31-24: addr1_3
- * 23-16: addr1_4
- * 15-8: addr1_5
- * 7-0: addr1_6
- */
-#define ET_RX_UNI_PF_ADDR1_3_SHIFT 24
-#define ET_RX_UNI_PF_ADDR1_4_SHIFT 16
-#define ET_RX_UNI_PF_ADDR1_5_SHIFT 8
-
-/*
- * structure for Unicast Packet Filter Address 2 reg in rxmac address map
- * located at address 0x406C
- *
- * 31-24: addr2_3
- * 23-16: addr2_4
- * 15-8: addr2_5
- * 7-0: addr2_6
- */
-#define ET_RX_UNI_PF_ADDR2_3_SHIFT 24
-#define ET_RX_UNI_PF_ADDR2_4_SHIFT 16
-#define ET_RX_UNI_PF_ADDR2_5_SHIFT 8
-
-/*
- * structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map
- * located at address 0x4070
- *
- * 31-24: addr2_1
- * 23-16: addr2_2
- * 15-8: addr1_1
- * 7-0: addr1_2
- */
-#define ET_RX_UNI_PF_ADDR2_1_SHIFT 24
-#define ET_RX_UNI_PF_ADDR2_2_SHIFT 16
-#define ET_RX_UNI_PF_ADDR1_1_SHIFT 8
-
-/*
- * structure for Multicast Hash reg in rxmac address map
- * located at address 0x4074 - 0x4080
- * Defined earlier (u32)
- */
-
-/*
- * structure for Packet Filter Control reg in rxmac address map
- * located at address 0x4084
- *
- * 31-23: unused
- * 22-16: min_pkt_size
- * 15-4: unused
- * 3: filter_frag_en
- * 2: filter_uni_en
- * 1: filter_multi_en
- * 0: filter_broad_en
- */
-#define ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT 16
-#define ET_RX_PFCTRL_FRAG_FILTER_ENABLE 0x0008
-#define ET_RX_PFCTRL_UNICST_FILTER_ENABLE 0x0004
-#define ET_RX_PFCTRL_MLTCST_FILTER_ENABLE 0x0002
-#define ET_RX_PFCTRL_BRDCST_FILTER_ENABLE 0x0001
-
-/*
- * structure for Memory Controller Interface Control Max Segment reg in rxmac
- * address map. Located at address 0x4088
- *
- * 31-10: reserved
- * 9-2: max_size
- * 1: fc_en
- * 0: seg_en
- */
-#define ET_RX_MCIF_CTRL_MAX_SEG_SIZE_SHIFT 2
-#define ET_RX_MCIF_CTRL_MAX_SEG_FC_ENABLE 0x0002
-#define ET_RX_MCIF_CTRL_MAX_SEG_ENABLE 0x0001
-
-/*
- * structure for Memory Controller Interface Water Mark reg in rxmac address
- * map. Located at address 0x408C
- *
- * 31-26: unused
- * 25-16: mark_hi
- * 15-10: unused
- * 9-0: mark_lo
- */
-
-/*
- * structure for Rx Queue Dialog reg in rxmac address map.
- * located at address 0x4090
- *
- * 31-26: reserved
- * 25-16: rd_ptr
- * 15-10: reserved
- * 9-0: wr_ptr
- */
-
-/*
- * structure for space available reg in rxmac address map.
- * located at address 0x4094
- *
- * 31-17: reserved
- * 16: space_avail_en
- * 15-10: reserved
- * 9-0: space_avail
- */
-
-/*
- * structure for management interface reg in rxmac address map.
- * located at address 0x4098
- *
- * 31-18: reserved
- * 17: drop_pkt_en
- * 16-0: drop_pkt_mask
- */
-
-/*
- * structure for Error reg in rxmac address map.
- * located at address 0x409C
- *
- * 31-4: unused
- * 3: mif
- * 2: async
- * 1: pkt_filter
- * 0: mcif
- */
-
-/*
- * Rx MAC Module of JAGCore Address Mapping
- */
-struct rxmac_regs { /* Location: */
- u32 ctrl; /* 0x4000 */
- u32 crc0; /* 0x4004 */
- u32 crc12; /* 0x4008 */
- u32 crc34; /* 0x400C */
- u32 sa_lo; /* 0x4010 */
- u32 sa_hi; /* 0x4014 */
- u32 mask0_word0; /* 0x4018 */
- u32 mask0_word1; /* 0x401C */
- u32 mask0_word2; /* 0x4020 */
- u32 mask0_word3; /* 0x4024 */
- u32 mask1_word0; /* 0x4028 */
- u32 mask1_word1; /* 0x402C */
- u32 mask1_word2; /* 0x4030 */
- u32 mask1_word3; /* 0x4034 */
- u32 mask2_word0; /* 0x4038 */
- u32 mask2_word1; /* 0x403C */
- u32 mask2_word2; /* 0x4040 */
- u32 mask2_word3; /* 0x4044 */
- u32 mask3_word0; /* 0x4048 */
- u32 mask3_word1; /* 0x404C */
- u32 mask3_word2; /* 0x4050 */
- u32 mask3_word3; /* 0x4054 */
- u32 mask4_word0; /* 0x4058 */
- u32 mask4_word1; /* 0x405C */
- u32 mask4_word2; /* 0x4060 */
- u32 mask4_word3; /* 0x4064 */
- u32 uni_pf_addr1; /* 0x4068 */
- u32 uni_pf_addr2; /* 0x406C */
- u32 uni_pf_addr3; /* 0x4070 */
- u32 multi_hash1; /* 0x4074 */
- u32 multi_hash2; /* 0x4078 */
- u32 multi_hash3; /* 0x407C */
- u32 multi_hash4; /* 0x4080 */
- u32 pf_ctrl; /* 0x4084 */
- u32 mcif_ctrl_max_seg; /* 0x4088 */
- u32 mcif_water_mark; /* 0x408C */
- u32 rxq_diag; /* 0x4090 */
- u32 space_avail; /* 0x4094 */
-
- u32 mif_ctrl; /* 0x4098 */
- u32 err_reg; /* 0x409C */
-};
-
-/* END OF RXMAC REGISTER ADDRESS MAP */
-
-/* START OF MAC REGISTER ADDRESS MAP */
-/*
- * structure for configuration #1 reg in mac address map.
- * located at address 0x5000
- *
- * 31: soft reset
- * 30: sim reset
- * 29-20: reserved
- * 19: reset rx mc
- * 18: reset tx mc
- * 17: reset rx func
- * 16: reset tx fnc
- * 15-9: reserved
- * 8: loopback
- * 7-6: reserved
- * 5: rx flow
- * 4: tx flow
- * 3: syncd rx en
- * 2: rx enable
- * 1: syncd tx en
- * 0: tx enable
- */
-#define ET_MAC_CFG1_SOFT_RESET 0x80000000
-#define ET_MAC_CFG1_SIM_RESET 0x40000000
-#define ET_MAC_CFG1_RESET_RXMC 0x00080000
-#define ET_MAC_CFG1_RESET_TXMC 0x00040000
-#define ET_MAC_CFG1_RESET_RXFUNC 0x00020000
-#define ET_MAC_CFG1_RESET_TXFUNC 0x00010000
-#define ET_MAC_CFG1_LOOPBACK 0x00000100
-#define ET_MAC_CFG1_RX_FLOW 0x00000020
-#define ET_MAC_CFG1_TX_FLOW 0x00000010
-#define ET_MAC_CFG1_RX_ENABLE 0x00000004
-#define ET_MAC_CFG1_TX_ENABLE 0x00000001
-#define ET_MAC_CFG1_WAIT 0x0000000A /* RX & TX syncd */
-
-/*
- * structure for configuration #2 reg in mac address map.
- * located at address 0x5004
- * 31-16: reserved
- * 15-12: preamble
- * 11-10: reserved
- * 9-8: if mode
- * 7-6: reserved
- * 5: huge frame
- * 4: length check
- * 3: undefined
- * 2: pad crc
- * 1: crc enable
- * 0: full duplex
- */
-#define ET_MAC_CFG2_PREAMBLE_SHIFT 12
-#define ET_MAC_CFG2_IFMODE_MASK 0x0300
-#define ET_MAC_CFG2_IFMODE_1000 0x0200
-#define ET_MAC_CFG2_IFMODE_100 0x0100
-#define ET_MAC_CFG2_IFMODE_HUGE_FRAME 0x0020
-#define ET_MAC_CFG2_IFMODE_LEN_CHECK 0x0010
-#define ET_MAC_CFG2_IFMODE_PAD_CRC 0x0004
-#define ET_MAC_CFG2_IFMODE_CRC_ENABLE 0x0002
-#define ET_MAC_CFG2_IFMODE_FULL_DPLX 0x0001
-
-/*
- * structure for Interpacket gap reg in mac address map.
- * located at address 0x5008
- *
- * 31: reserved
- * 30-24: non B2B ipg 1
- * 23: undefined
- * 22-16: non B2B ipg 2
- * 15-8: Min ifg enforce
- * 7-0: B2B ipg
- *
- * structure for half duplex reg in mac address map.
- * located at address 0x500C
- * 31-24: reserved
- * 23-20: Alt BEB trunc
- * 19: Alt BEB enable
- * 18: BP no backoff
- * 17: no backoff
- * 16: excess defer
- * 15-12: re-xmit max
- * 11-10: reserved
- * 9-0: collision window
- */
-
-/*
- * structure for Maximum Frame Length reg in mac address map.
- * located at address 0x5010: bits 0-15 hold the length.
- */
-
-/*
- * structure for Reserve 1 reg in mac address map.
- * located at address 0x5014 - 0x5018
- * Defined earlier (u32)
- */
-
-/*
- * structure for Test reg in mac address map.
- * located at address 0x501C
- * test: bits 0-2, rest unused
- */
-
-/*
- * structure for MII Management Configuration reg in mac address map.
- * located at address 0x5020
- *
- * 31: reset MII mgmt
- * 30-6: unused
- * 5: scan auto increment
- * 4: preamble suppress
- * 3: undefined
- * 2-0: mgmt clock reset
- */
-#define ET_MAC_MIIMGMT_CLK_RST 0x0007
-
-/*
- * structure for MII Management Command reg in mac address map.
- * located at address 0x5024
- * bit 1: scan cycle
- * bit 0: read cycle
- */
-
-/*
- * structure for MII Management Address reg in mac address map.
- * located at address 0x5028
- * 31-13: reserved
- * 12-8: phy addr
- * 7-5: reserved
- * 4-0: register
- */
-#define ET_MAC_MII_ADDR(phy, reg) ((phy) << 8 | (reg))
-
-/*
- * structure for MII Management Control reg in mac address map.
- * located at address 0x502C
- * 31-16: reserved
- * 15-0: phy control
- */
-
-/*
- * structure for MII Management Status reg in mac address map.
- * located at address 0x5030
- * 31-16: reserved
- * 15-0: phy control
- */
-#define ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK 0xFFFF
-
-/*
- * structure for MII Management Indicators reg in mac address map.
- * located at address 0x5034
- * 31-3: reserved
- * 2: not valid
- * 1: scanning
- * 0: busy
- */
-#define ET_MAC_MGMT_BUSY 0x00000001 /* busy */
-#define ET_MAC_MGMT_WAIT 0x00000005 /* busy | not valid */
-
-/*
- * structure for Interface Control reg in mac address map.
- * located at address 0x5038
- *
- * 31: reset if module
- * 30-28: reserved
- * 27: tbi mode
- * 26: ghd mode
- * 25: lhd mode
- * 24: phy mode
- * 23: reset per mii
- * 22-17: reserved
- * 16: speed
- * 15: reset pe100x
- * 14-11: reserved
- * 10: force quiet
- * 9: no cipher
- * 8: disable link fail
- * 7: reset gpsi
- * 6-1: reserved
- * 0: enable jabber protection
- */
-#define ET_MAC_IFCTRL_GHDMODE (1 << 26)
-#define ET_MAC_IFCTRL_PHYMODE (1 << 24)
-
-/*
- * structure for Interface Status reg in mac address map.
- * located at address 0x503C
- *
- * 31-10: reserved
- * 9: excess_defer
- * 8: clash
- * 7: phy_jabber
- * 6: phy_link_ok
- * 5: phy_full_duplex
- * 4: phy_speed
- * 3: pe100x_link_fail
- * 2: pe10t_loss_carrier
- * 1: pe10t_sqe_error
- * 0: pe10t_jabber
- */
-
-/*
- * structure for Mac Station Address, Part 1 reg in mac address map.
- * located at address 0x5040
- *
- * 31-24: Octet6
- * 23-16: Octet5
- * 15-8: Octet4
- * 7-0: Octet3
- */
-#define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
-#define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
-#define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
-
-/*
- * structure for Mac Station Address, Part 2 reg in mac address map.
- * located at address 0x5044
- *
- * 31-24: Octet2
- * 23-16: Octet1
- * 15-0: reserved
- */
-#define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
-#define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
-
-/*
- * MAC Module of JAGCore Address Mapping
- */
-struct mac_regs { /* Location: */
- u32 cfg1; /* 0x5000 */
- u32 cfg2; /* 0x5004 */
- u32 ipg; /* 0x5008 */
- u32 hfdp; /* 0x500C */
- u32 max_fm_len; /* 0x5010 */
- u32 rsv1; /* 0x5014 */
- u32 rsv2; /* 0x5018 */
- u32 mac_test; /* 0x501C */
- u32 mii_mgmt_cfg; /* 0x5020 */
- u32 mii_mgmt_cmd; /* 0x5024 */
- u32 mii_mgmt_addr; /* 0x5028 */
- u32 mii_mgmt_ctrl; /* 0x502C */
- u32 mii_mgmt_stat; /* 0x5030 */
- u32 mii_mgmt_indicator; /* 0x5034 */
- u32 if_ctrl; /* 0x5038 */
- u32 if_stat; /* 0x503C */
- u32 station_addr_1; /* 0x5040 */
- u32 station_addr_2; /* 0x5044 */
-};
-
-/* END OF MAC REGISTER ADDRESS MAP */
-
-/* START OF MAC STAT REGISTER ADDRESS MAP */
-/*
- * structure for Carry Register One and it's Mask Register reg located in mac
- * stat address map address 0x6130 and 0x6138.
- *
- * 31: tr64
- * 30: tr127
- * 29: tr255
- * 28: tr511
- * 27: tr1k
- * 26: trmax
- * 25: trmgv
- * 24-17: unused
- * 16: rbyt
- * 15: rpkt
- * 14: rfcs
- * 13: rmca
- * 12: rbca
- * 11: rxcf
- * 10: rxpf
- * 9: rxuo
- * 8: raln
- * 7: rflr
- * 6: rcde
- * 5: rcse
- * 4: rund
- * 3: rovr
- * 2: rfrg
- * 1: rjbr
- * 0: rdrp
- */
-
-/*
- * structure for Carry Register Two Mask Register reg in mac stat address map.
- * located at address 0x613C
- *
- * 31-20: unused
- * 19: tjbr
- * 18: tfcs
- * 17: txcf
- * 16: tovr
- * 15: tund
- * 14: trfg
- * 13: tbyt
- * 12: tpkt
- * 11: tmca
- * 10: tbca
- * 9: txpf
- * 8: tdfr
- * 7: tedf
- * 6: tscl
- * 5: tmcl
- * 4: tlcl
- * 3: txcl
- * 2: tncl
- * 1: tpfh
- * 0: tdrp
- */
-
-/*
- * MAC STATS Module of JAGCore Address Mapping
- */
-struct macstat_regs { /* Location: */
- u32 pad[32]; /* 0x6000 - 607C */
-
- /* counters */
- u32 txrx_0_64_byte_frames; /* 0x6080 */
- u32 txrx_65_127_byte_frames; /* 0x6084 */
- u32 txrx_128_255_byte_frames; /* 0x6088 */
- u32 txrx_256_511_byte_frames; /* 0x608C */
- u32 txrx_512_1023_byte_frames; /* 0x6090 */
- u32 txrx_1024_1518_byte_frames; /* 0x6094 */
- u32 txrx_1519_1522_gvln_frames; /* 0x6098 */
- u32 rx_bytes; /* 0x609C */
- u32 rx_packets; /* 0x60A0 */
- u32 rx_fcs_errs; /* 0x60A4 */
- u32 rx_multicast_packets; /* 0x60A8 */
- u32 rx_broadcast_packets; /* 0x60AC */
- u32 rx_control_frames; /* 0x60B0 */
- u32 rx_pause_frames; /* 0x60B4 */
- u32 rx_unknown_opcodes; /* 0x60B8 */
- u32 rx_align_errs; /* 0x60BC */
- u32 rx_frame_len_errs; /* 0x60C0 */
- u32 rx_code_errs; /* 0x60C4 */
- u32 rx_carrier_sense_errs; /* 0x60C8 */
- u32 rx_undersize_packets; /* 0x60CC */
- u32 rx_oversize_packets; /* 0x60D0 */
- u32 rx_fragment_packets; /* 0x60D4 */
- u32 rx_jabbers; /* 0x60D8 */
- u32 rx_drops; /* 0x60DC */
- u32 tx_bytes; /* 0x60E0 */
- u32 tx_packets; /* 0x60E4 */
- u32 tx_multicast_packets; /* 0x60E8 */
- u32 tx_broadcast_packets; /* 0x60EC */
- u32 tx_pause_frames; /* 0x60F0 */
- u32 tx_deferred; /* 0x60F4 */
- u32 tx_excessive_deferred; /* 0x60F8 */
- u32 tx_single_collisions; /* 0x60FC */
- u32 tx_multiple_collisions; /* 0x6100 */
- u32 tx_late_collisions; /* 0x6104 */
- u32 tx_excessive_collisions; /* 0x6108 */
- u32 tx_total_collisions; /* 0x610C */
- u32 tx_pause_honored_frames; /* 0x6110 */
- u32 tx_drops; /* 0x6114 */
- u32 tx_jabbers; /* 0x6118 */
- u32 tx_fcs_errs; /* 0x611C */
- u32 tx_control_frames; /* 0x6120 */
- u32 tx_oversize_frames; /* 0x6124 */
- u32 tx_undersize_frames; /* 0x6128 */
- u32 tx_fragments; /* 0x612C */
- u32 carry_reg1; /* 0x6130 */
- u32 carry_reg2; /* 0x6134 */
- u32 carry_reg1_mask; /* 0x6138 */
- u32 carry_reg2_mask; /* 0x613C */
-};
-
-/* END OF MAC STAT REGISTER ADDRESS MAP */
-
-/* START OF MMC REGISTER ADDRESS MAP */
-/*
- * Main Memory Controller Control reg in mmc address map.
- * located at address 0x7000
- */
-#define ET_MMC_ENABLE 1
-#define ET_MMC_ARB_DISABLE 2
-#define ET_MMC_RXMAC_DISABLE 4
-#define ET_MMC_TXMAC_DISABLE 8
-#define ET_MMC_TXDMA_DISABLE 16
-#define ET_MMC_RXDMA_DISABLE 32
-#define ET_MMC_FORCE_CE 64
-
-/*
- * Main Memory Controller Host Memory Access Address reg in mmc
- * address map. Located at address 0x7004. Top 16 bits hold the address bits
- */
-#define ET_SRAM_REQ_ACCESS 1
-#define ET_SRAM_WR_ACCESS 2
-#define ET_SRAM_IS_CTRL 4
-
-/*
- * structure for Main Memory Controller Host Memory Access Data reg in mmc
- * address map. Located at address 0x7008 - 0x7014
- * Defined earlier (u32)
- */
-
-/*
- * Memory Control Module of JAGCore Address Mapping
- */
-struct mmc_regs { /* Location: */
- u32 mmc_ctrl; /* 0x7000 */
- u32 sram_access; /* 0x7004 */
- u32 sram_word1; /* 0x7008 */
- u32 sram_word2; /* 0x700C */
- u32 sram_word3; /* 0x7010 */
- u32 sram_word4; /* 0x7014 */
-};
-
-/* END OF MMC REGISTER ADDRESS MAP */
-
-/*
- * JAGCore Address Mapping
- */
-struct address_map {
- struct global_regs global;
- /* unused section of global address map */
- u8 unused_global[4096 - sizeof(struct global_regs)];
- struct txdma_regs txdma;
- /* unused section of txdma address map */
- u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
- struct rxdma_regs rxdma;
- /* unused section of rxdma address map */
- u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
- struct txmac_regs txmac;
- /* unused section of txmac address map */
- u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
- struct rxmac_regs rxmac;
- /* unused section of rxmac address map */
- u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
- struct mac_regs mac;
- /* unused section of mac address map */
- u8 unused_mac[4096 - sizeof(struct mac_regs)];
- struct macstat_regs macstat;
- /* unused section of mac stat address map */
- u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
- struct mmc_regs mmc;
- /* unused section of mmc address map */
- u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
- /* unused section of address map */
- u8 unused_[1015808];
- u8 unused_exp_rom[4096]; /* MGS-size TBD */
- u8 unused__[524288]; /* unused section of address map */
-};
-
-/*
- * Defines for generic MII registers 0x00 -> 0x0F can be found in
- * include/linux/mii.h
- */
-/* some defines for modem registers that seem to be 'reserved' */
-#define PHY_INDEX_REG 0x10
-#define PHY_DATA_REG 0x11
-#define PHY_MPHY_CONTROL_REG 0x12
-
-/* defines for specified registers */
-#define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
- /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
-#define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
-#define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
-#define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
-#define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
-#define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
-#define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
-#define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
-#define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
- /* TRU_VMI_LINK_CONTROL_REG 29 */
- /* TRU_VMI_TIMING_CONTROL_REG */
-
-/* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
-#define ET_1000BT_MSTR_SLV 0x4000
-
-/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
-
-/* MI Register 19: Loopback Control Reg(0x13)
- * 15: mii_en
- * 14: pcs_en
- * 13: pmd_en
- * 12: all_digital_en
- * 11: replica_en
- * 10: line_driver_en
- * 9-0: reserved
- */
-
-/* MI Register 20: Reserved Reg(0x14) */
-
-/* MI Register 21: Management Interface Control Reg(0x15)
- * 15-11: reserved
- * 10-4: mi_error_count
- * 3: reserved
- * 2: ignore_10g_fr
- * 1: reserved
- * 0: preamble_suppress_en
- */
-
-/* MI Register 22: PHY Configuration Reg(0x16)
- * 15: crs_tx_en
- * 14: reserved
- * 13-12: tx_fifo_depth
- * 11-10: speed_downshift
- * 9: pbi_detect
- * 8: tbi_rate
- * 7: alternate_np
- * 6: group_mdio_en
- * 5: tx_clock_en
- * 4: sys_clock_en
- * 3: reserved
- * 2-0: mac_if_mode
- */
-#define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
-
-#define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
-#define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
-#define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
-#define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
-
-/* MI Register 23: PHY CONTROL Reg(0x17)
- * 15: reserved
- * 14: tdr_en
- * 13: reserved
- * 12-11: downshift_attempts
- * 10-6: reserved
- * 5: jabber_10baseT
- * 4: sqe_10baseT
- * 3: tp_loopback_10baseT
- * 2: preamble_gen_en
- * 1: reserved
- * 0: force_int
- */
-
-/* MI Register 24: Interrupt Mask Reg(0x18)
- * 15-10: reserved
- * 9: mdio_sync_lost
- * 8: autoneg_status
- * 7: hi_bit_err
- * 6: np_rx
- * 5: err_counter_full
- * 4: fifo_over_underflow
- * 3: rx_status
- * 2: link_status
- * 1: automatic_speed
- * 0: int_en
- */
-
-/* MI Register 25: Interrupt Status Reg(0x19)
- * 15-10: reserved
- * 9: mdio_sync_lost
- * 8: autoneg_status
- * 7: hi_bit_err
- * 6: np_rx
- * 5: err_counter_full
- * 4: fifo_over_underflow
- * 3: rx_status
- * 2: link_status
- * 1: automatic_speed
- * 0: int_en
- */
-
-/* MI Register 26: PHY Status Reg(0x1A)
- * 15: reserved
- * 14-13: autoneg_fault
- * 12: autoneg_status
- * 11: mdi_x_status
- * 10: polarity_status
- * 9-8: speed_status
- * 7: duplex_status
- * 6: link_status
- * 5: tx_status
- * 4: rx_status
- * 3: collision_status
- * 2: autoneg_en
- * 1: pause_en
- * 0: asymmetric_dir
- */
-#define ET_PHY_AUTONEG_STATUS 0x1000
-#define ET_PHY_POLARITY_STATUS 0x0400
-#define ET_PHY_SPEED_STATUS 0x0300
-#define ET_PHY_DUPLEX_STATUS 0x0080
-#define ET_PHY_LSTATUS 0x0040
-#define ET_PHY_AUTONEG_ENABLE 0x0020
-
-/* MI Register 27: LED Control Reg 1(0x1B)
- * 15-14: reserved
- * 13-12: led_dup_indicate
- * 11-10: led_10baseT
- * 9-8: led_collision
- * 7-4: reserved
- * 3-2: pulse_dur
- * 1: pulse_stretch1
- * 0: pulse_stretch0
- */
-
-/* MI Register 28: LED Control Reg 2(0x1C)
- * 15-12: led_link
- * 11-8: led_tx_rx
- * 7-4: led_100BaseTX
- * 3-0: led_1000BaseT
- */
-#define ET_LED2_LED_LINK 0xF000
-#define ET_LED2_LED_TXRX 0x0F00
-#define ET_LED2_LED_100TX 0x00F0
-#define ET_LED2_LED_1000T 0x000F
-
-/* defines for LED control reg 2 values */
-#define LED_VAL_1000BT 0x0
-#define LED_VAL_100BTX 0x1
-#define LED_VAL_10BT 0x2
-#define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
-#define LED_VAL_LINKON 0x4
-#define LED_VAL_TX 0x5
-#define LED_VAL_RX 0x6
-#define LED_VAL_TXRX 0x7 /* TX or RX */
-#define LED_VAL_DUPLEXFULL 0x8
-#define LED_VAL_COLLISION 0x9
-#define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
-#define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
-#define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
-#define LED_VAL_BLINK 0xD
-#define LED_VAL_ON 0xE
-#define LED_VAL_OFF 0xF
-
-#define LED_LINK_SHIFT 12
-#define LED_TXRX_SHIFT 8
-#define LED_100TX_SHIFT 4
-
-/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
--
2.1.0
^ permalink raw reply related
* Re: [patch net-next v2 8/9] switchdev: introduce Netlink API
From: Thomas Graf @ 2014-09-22 22:17 UTC (permalink / raw)
To: Tom Herbert
Cc: Alexei Starovoitov, Jiri Pirko, John Fastabend, Jamal Hadi Salim,
netdev@vger.kernel.org, David S. Miller, Neil Horman,
Andy Gospodarek, Daniel Borkmann, Or Gerlitz, Jesse Gross,
Pravin Shelar, Andy Zhou, Ben Hutchings, Stephen Hemminger,
Jeff Kirsher, Vladislav Yasevich, Cong Wang, Eric Dumazet,
Scott Feldman, Florian Fainelli, Roopa Prabhu
In-Reply-To: <CA+mtBx-ZvkZ2ALGLsLEN7Cgn9gN_rY36ZhuqYC3mZ9WVxjFDaQ@mail.gmail.com>
On 09/22/14 at 08:10am, Tom Herbert wrote:
> Thomas, can you (or someone else) quantify what the host case is. I
> suppose there may be merit in using a switch on NIC for kernel bypass
> scenarios, but I'm still having a hard time understanding how this
> could be integrated into the host stack with benefits that outweigh
Personally my primary interest is on lxc and vm based workloads w/
end to end encryption, encap, distributed L3 and NAT, and policy
enforcement including service graphs which imply both east-west
and north-south traffic patterns on a host. The usual I guess ;-)
> complexity. The history of stateful offloads in NICs is not great, and
> encapsulation (stuffing a few bytes of header into a packet) is in
> itself not nearly an expensive enough operation to warrant offloading
No argument here. The direct benchmark comparisons I've measured showed
only around 2% improvement.
What makes stateful offload interesting to me is that the final
desintation of a packet is known at RX and can be redirected to a
queue or VF. This allows to build packet batches on shared pages
while preserving the securiy model.
Will the gains outweigh complexity? I hope so but I don't know for
sure. If you have insights, let me know. What I know for sure is that
I don't want to rely on a kernel bypass for the above.
> to the NIC. Personally, I wish if NIC vendors are going to focus on
> stateful offload I rather see it be for encryption which I believe
> currently does warrant offload at 40G and higher speeds.
Agreed. I would like to be see a focus on both.
^ permalink raw reply
* Re: [PATCH] brcmfmac: Fix off by one bug in brcmf_count_20mhz_channels()
From: Emil Goode @ 2014-09-22 22:38 UTC (permalink / raw)
To: Arend van Spriel
Cc: Brett Rudley, Franky (Zhenhui) Lin, Hante Meuleman,
John W. Linville, Pieter-Paul Giesberts, Daniel Kim,
linux-wireless, brcm80211-dev-list, netdev, linux-kernel,
kernel-janitors
In-Reply-To: <541FF0C4.9020805@broadcom.com>
Hello Arend,
Ok I will resend with your ack.
Best regards,
Emil
On Mon, Sep 22, 2014 at 11:49:56AM +0200, Arend van Spriel wrote:
> On 09/21/14 00:58, Emil Goode wrote:
> >In the brcmf_count_20mhz_channels function we are looping through a list
> >of channels received from firmware. Since the index of the first channel
> >is 0 the condition leads to an off by one bug. This is causing us to hit
> >the WARN_ON_ONCE(1) calls in the brcmu_d11n_decchspec function, which is
> >how I discovered the bug.
> >
> >Introduced by:
> >commit b48d891676f756d48b4d0ee131e4a7a5d43ca417
> >("brcmfmac: rework wiphy structure setup")
>
> My bad :-(. You can add:
>
> Acked-by: Arend van Spriel <arend@broadcom.com>
> >Signed-off-by: Emil Goode<emilgoode@gmail.com>
> >---
> > drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
> >index 02fe706..93b5dd9 100644
> >--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
> >+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
> >@@ -4918,7 +4918,7 @@ static void brcmf_count_20mhz_channels(struct brcmf_cfg80211_info *cfg,
> > struct brcmu_chan ch;
> > int i;
> >
> >- for (i = 0; i<= total; i++) {
> >+ for (i = 0; i< total; i++) {
> > ch.chspec = (u16)le32_to_cpu(chlist->element[i]);
> > cfg->d11inf.decchspec(&ch);
> >
>
^ permalink raw reply
* Re: [PATCH net 0/2 v2] net: bcmgenet: TX reclaim and DMA fixes
From: David Miller @ 2014-09-22 22:39 UTC (permalink / raw)
To: f.fainelli; +Cc: netdev
In-Reply-To: <1411412083-9370-1-git-send-email-f.fainelli@gmail.com>
From: Florian Fainelli <f.fainelli@gmail.com>
Date: Mon, 22 Sep 2014 11:54:41 -0700
> This patch set contains one fix for an accounting problem while reclaiming
> transmitted buffers having fragments, and the second fix is to make sure
> that the DMA shutdown is properly controlled.
Series applied, but I can't see how you could have possibly
functionally tested the original patch series if it didn't
even compile :-/
^ permalink raw reply
* Re: [patch net-next v2 8/9] switchdev: introduce Netlink API
From: Tom Herbert @ 2014-09-22 22:40 UTC (permalink / raw)
To: Thomas Graf
Cc: ryazanov.s.a-Re5JQEeQqe8AvxtiuMwx3w, Jason Wang, John Fastabend,
Neil Jerram, Eric Dumazet, Andy Gospodarek,
dev-yBygre7rU0TnMu66kgdUjQ@public.gmane.org, Felix Fietkau,
Florian Fainelli, ronye-VPRAkNaXOzVWk0Htik3J/w, Jeff Kirsher,
Or Gerlitz, Ben Hutchings, Lennert Buytenhek, Alexander Duyck,
Jiri Pirko, simon.horman-wFxRvT7yatFl57MIdRCFDg, Roopa Prabhu,
Jamal Hadi Salim, aviadr-VPRAkNaXOzVWk0Htik3J/w, Nicolas Dichtel,
Vladislav Yasevich, Neil Horman,
"netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <netdev@
In-Reply-To: <20140922221727.GA4708-FZi0V3Vbi30CUdFEqe4BF2D2FQJk+8+b@public.gmane.org>
On Mon, Sep 22, 2014 at 3:17 PM, Thomas Graf <tgraf-G/eBtMaohhA@public.gmane.org> wrote:
> On 09/22/14 at 08:10am, Tom Herbert wrote:
>> Thomas, can you (or someone else) quantify what the host case is. I
>> suppose there may be merit in using a switch on NIC for kernel bypass
>> scenarios, but I'm still having a hard time understanding how this
>> could be integrated into the host stack with benefits that outweigh
>
> Personally my primary interest is on lxc and vm based workloads w/
> end to end encryption, encap, distributed L3 and NAT, and policy
> enforcement including service graphs which imply both east-west
> and north-south traffic patterns on a host. The usual I guess ;-)
>
>> complexity. The history of stateful offloads in NICs is not great, and
>> encapsulation (stuffing a few bytes of header into a packet) is in
>> itself not nearly an expensive enough operation to warrant offloading
>
> No argument here. The direct benchmark comparisons I've measured showed
> only around 2% improvement.
>
> What makes stateful offload interesting to me is that the final
> desintation of a packet is known at RX and can be redirected to a
> queue or VF. This allows to build packet batches on shared pages
> while preserving the securiy model.
>
How is this different from what rx-filtering already does?
> Will the gains outweigh complexity? I hope so but I don't know for
> sure. If you have insights, let me know. What I know for sure is that
> I don't want to rely on a kernel bypass for the above.
>
>> to the NIC. Personally, I wish if NIC vendors are going to focus on
>> stateful offload I rather see it be for encryption which I believe
>> currently does warrant offload at 40G and higher speeds.
>
> Agreed. I would like to be see a focus on both.
^ permalink raw reply
* Re: [PATCH net 0/2 v2] net: bcmgenet: TX reclaim and DMA fixes
From: Florian Fainelli @ 2014-09-22 22:43 UTC (permalink / raw)
To: David Miller; +Cc: netdev
In-Reply-To: <20140922.183943.104495150444696692.davem@davemloft.net>
On 09/22/2014 03:39 PM, David Miller wrote:
> From: Florian Fainelli <f.fainelli@gmail.com>
> Date: Mon, 22 Sep 2014 11:54:41 -0700
>
>> This patch set contains one fix for an accounting problem while reclaiming
>> transmitted buffers having fragments, and the second fix is to make sure
>> that the DMA shutdown is properly controlled.
>
> Series applied, but I can't see how you could have possibly
> functionally tested the original patch series if it didn't
> even compile :-/
I cherry picked the second patch from my downstream tree which had a
different function re-arrangement, and I must admit I thought I also had
compiled the second patch, while I did not...
--
Florian
^ permalink raw reply
* [PATCH v2] brcmfmac: Fix off by one bug in brcmf_count_20mhz_channels()
From: Emil Goode @ 2014-09-22 22:49 UTC (permalink / raw)
To: Arend van Spriel, Brett Rudley, Franky (Zhenhui) Lin,
Hante Meuleman, John W. Linville, Pieter-Paul Giesberts,
Daniel Kim
Cc: linux-wireless, brcm80211-dev-list, netdev, linux-kernel,
kernel-janitors, Emil Goode
In the brcmf_count_20mhz_channels function we are looping through a list
of channels received from firmware. Since the index of the first channel
is 0 the condition leads to an off by one bug. This is causing us to hit
the WARN_ON_ONCE(1) calls in the brcmu_d11n_decchspec function, which is
how I discovered the bug.
Introduced by:
commit b48d891676f756d48b4d0ee131e4a7a5d43ca417
("brcmfmac: rework wiphy structure setup")
Acked-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Emil Goode <emilgoode@gmail.com>
---
v2: Added Arends "Acked-by" tag.
drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
index 12a60ca..0517687 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
@@ -4924,7 +4924,7 @@ static void brcmf_count_20mhz_channels(struct brcmf_cfg80211_info *cfg,
struct brcmu_chan ch;
int i;
- for (i = 0; i <= total; i++) {
+ for (i = 0; i < total; i++) {
ch.chspec = (u16)le32_to_cpu(chlist->element[i]);
cfg->d11inf.decchspec(&ch);
--
2.1.0
^ permalink raw reply related
* Re: [patch net-next v2 8/9] switchdev: introduce Netlink API
From: Thomas Graf @ 2014-09-22 22:53 UTC (permalink / raw)
To: Tom Herbert
Cc: Alexei Starovoitov, Jiri Pirko, John Fastabend, Jamal Hadi Salim,
netdev@vger.kernel.org, David S. Miller, Neil Horman,
Andy Gospodarek, Daniel Borkmann, Or Gerlitz, Jesse Gross,
Pravin Shelar, Andy Zhou, Ben Hutchings, Stephen Hemminger,
Jeff Kirsher, Vladislav Yasevich, Cong Wang, Eric Dumazet,
Scott Feldman, Florian Fainelli, Roopa Prabhu
In-Reply-To: <CA+mtBx9ZVQ5r5Hzy9-uEnk+iu+HKkOP4+VANC06Xf8VvTxktwQ@mail.gmail.com>
On 09/22/14 at 03:40pm, Tom Herbert wrote:
> On Mon, Sep 22, 2014 at 3:17 PM, Thomas Graf <tgraf@suug.ch> wrote:
> > What makes stateful offload interesting to me is that the final
> > desintation of a packet is known at RX and can be redirected to a
> > queue or VF. This allows to build packet batches on shared pages
> > while preserving the securiy model.
> >
> How is this different from what rx-filtering already does?
Without stateful offload I can't know where the packet is destined
to until after I've allocated an skb and parsed the packet in
software. I might be missing what you refer to here specifically.
^ permalink raw reply
* [GIT] Networking
From: David Miller @ 2014-09-22 22:54 UTC (permalink / raw)
To: torvalds; +Cc: akpm, netdev, linux-kernel
1) If the user gives us a msg_namelen of 0, don't try to interpret anything
pointed to by msg_name. From Ani Sinha.
2) Fix some bnx2i/bnx2fc randconfig compilation errors.
The gist of the issue is that we firstly have drivers that span
both SCSI and networking. And at the top of that chain of
dependencies we have things like SCSI_FC_ATTRS and SCSI_NETLINK
which are selected.
But since select is a sledgehammer and ignores dependencies,
everything to select's SCSI_FC_ATTRS and/or SCSI_NETLINK has
to also explicitly select their dependencies and so on and so
forth.
Generally speaking 'select' is supposed to only be used for child
nodes, those which have no dependencies of their own. And this
whole chain of dependencies in the scsi layer violates that rather
strongly.
So just make SCSI_NETLINK depend upon it's dependencies, and so
on and so forth for the things selecting it (either directly or
indirectly).
From Anish Bhatt and Randy Dunlap.
3) Fix generation of blackhole routes in IPSEC, from Steffen Klassert.
4) Actually notice netdev feature changes in rtl_open() code, from
Hayes Wang.
5) Fix divide by zero in bond enslaving, from Nikolay Aleksandrov.
6) Missing memory barrier in sunvnet driver, from David Stevens.
7) Don't leave anycast addresses around when ipv6 interface is
destroyed, from Sabrina Dubroca.
8) Don't call efx_{arch}_filter_sync_rx_mode before addr_list_lock
is initialized in SFC driver, from Edward Cree.
9) Fix missing DMA error checking in 3c59x, from Neal Horman.
10) Openvswitch doesn't emit OVS_FLOW_CMD_NEW notifications accidently,
fix from Samuel Gauthier.
11) pch_gbe needs to select NET_PTP_CLASSIFY otherwise we can get
a build error.
12) Fix macvlan regression wherein we stopped emitting
broadcast/multicast frames over software devices. From Nicolas
Dichtel.
13) Fix infiniband bug due to unintended overflow of skb->cb[], from
Eric Dumazet. And add an assertion so this doesn't happen again.
14) dm9000_parse_dt() should return error pointers, not NULL. From
Tobias Klauser.
15) IP tunneling code uses this_cpu_ptr() in preemptible contexts, fix
from Eric Dumazet.
Please pull, thanks a lot!
The following changes since commit 35af25616c6c0c42416545f732d36b2ba7199519:
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux (2014-09-08 08:27:00 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git master
for you to fetch changes up to e18b7faae15dbd47e5811ed748bd5b500dcfaa2d:
Merge branch 'bcmgenet' (2014-09-22 18:38:53 -0400)
----------------------------------------------------------------
Aaro Koskinen (1):
drivers: net: ethernet: octeon_mgmt: fix a compiler warning
Alexander Y. Fomichev (1):
net: fix creation adjacent device symlinks
Alexei Starovoitov (1):
sparc: bpf_jit: fix support for ldx/stx mem and SKF_AD_VLAN_TAG
Ani Sinha (1):
net:socket: set msg_namelen to 0 if msg_name is passed as NULL in msghdr struct from userland.
Anish Bhatt (2):
scsi_netlink : Make SCSI_NETLINK dependent on NET instead of selecting NET
bnx2i/bnx2fc : fix randconfig error in next-20140909
Arend van Spriel (3):
brcmfmac: conditionally compile firmware protocol source code
brcmfmac: obtain ifp through wdev structure
brcmfmac: handle IF event for P2P_DEVICE interface
Beniamino Galvani (2):
net: arc_emac: enable tx interrupts
net: arc_emac: prevent reuse of unreclaimed tx descriptors
Dan Carpenter (1):
r8169: fix an if condition
David Dueck (1):
can: at91_can: add missing prepare and unprepare of the clock
David Howells (1):
RxRPC: Fix missing __user annotation
David Jander (3):
can: flexcan: avoid calling usleep_range from interrupt context
can: flexcan: correctly initialize mailboxes
can: flexcan: implement workaround for errata ERR005829
David L Stevens (1):
sunvnet - add missing rmb() for sunvnet driver
David S. Miller (14):
Merge branch 'oom_fixes'
Merge branch 'mlx4'
Merge branch 'arc_emac'
Merge tag 'linux-can-fixes-for-3.17-20140911' of git://gitorious.org/linux-can/linux-can
Merge tag 'master-2014-09-11' of git://git.kernel.org/.../linville/wireless
Merge branch 'r8169-net'
Merge branch 'bridge_vlan_filtering'
Merge branch 'bnx2-deps'
Merge tag 'master-2014-09-16' of git://git.kernel.org/.../linville/wireless
Merge tag 'linux-can-fixes-for-3.17-20140918' of git://gitorious.org/linux-can/linux-can
scsi: Use 'depends' with LIBFC instead of 'select'.
pch_gbe: 'select' NET_PTP_CLASSIFY.
Merge branch 'master' of git://git.kernel.org/.../klassert/ipsec
Merge branch 'bcmgenet'
Edward Cree (1):
sfc: fix addr_list_lock spinlock use before init
Eliad Peller (1):
iwlwifi: increase DEFAULT_MAX_TX_POWER
Emmanuel Grumbach (5):
iwlwifi: mvm: enable scheduled scan on newest firmware
mac80211: use bss_conf->dtim_period instead of conf.ps_dtim_period
iwlwifi: mvm: fix endianity issues with Smart Fifo commands
iwlwiwi: mvm: use bss_conf->dtim_period instead of conf.ps_dtim_period
iwlwifi: dvm: disable power save by default
Eric Dumazet (4):
net: fix skb_page_frag_refill() kerneldoc
net: sched: shrink struct qdisc_skb_cb to 28 bytes
ipoib: validate struct ipoib_cb size
ipv4: do not use this_cpu_ptr() in preemptible context
Eyal Shapira (2):
iwlwifi: mvm: treat EAPOLs like mgmt frames wrt rate
iwlwifi: mvm: fix an overflow in iwl_mvm_get_signal_strength
Fabian Frederick (1):
lib: rhashtable: remove second linux/log2.h inclusion
Florian Fainelli (4):
net: systemport: check harder for out of memory conditions
net: bcmgenet: check harder for out of memory conditions
net: bcmgenet: fix TX reclaim accounting for fragments
net: bcmgenet: call bcmgenet_dma_teardown in bcmgenet_fini_dma
Francesco Ruggeri (1):
net: allow macvlans to move to net namespace
Hante Meuleman (1):
brcmfmac: Fix memory leak and missing assignment.
Hariprasad Shenai (1):
cxgb4: Don't allocate adapter structure for all PF's
Ivan Vecera (1):
net/mlx4_en: do not ignore autoneg in mlx4_en_set_pauseparam()
Johannes Berg (4):
nl80211: clear skb cb before passing to netlink
iwlwifi: mvm: BT Coex - remove shadowing variable
iwlwifi: mvm: correctly handle PM/QoS changes from mac80211
iwlwifi: mvm: BT Coex - always initialize smps_mode
Johannes Stezenbach (1):
ath9k_htc: fix random decryption failure
John W. Linville (2):
Merge tag 'mac80211-for-john-2014-09-08' of git://git.kernel.org/.../jberg/mac80211
Merge branch 'for-john' of git://git.kernel.org/.../iwlwifi/iwlwifi-fixes
Luciano Coelho (1):
iwlwifi: mvm: set MAC_FILTER_IN_BEACON correctly for STA/P2P client
Marc Kleine-Budde (3):
can: flexcan: mark TX mailbox as TX_INACTIVE
can: flexcan: put TX mailbox into TX_INACTIVE mode after tx-complete
can: flexcan: increase FLEXCAN_MCR_MAXMB() macro to 7 bits
Marcel Holtmann (1):
net: rfkill: gpio: Enable module auto-loading for ACPI based switches
Mark Einon (1):
drivers: net: b44: Fix typo in returning multicast stats
Markos Chandras (1):
Documentation: filter: Add MIPS to architectures with BPF JIT
Masanari Iida (1):
net:bonding: Add missing space in bonding driver parameter description
Matan Barak (4):
net/mlx4: Correctly configure single ported VFs from the host
net/mlx4: Use the correct VSD mask in UPDATE_QP
net/mlx4: Avoid dealing with MAC index in UPDATE_QP wrapper if not needed
net/mlx4: Set vlan stripping policy by the right command
Mike Looijmans (1):
net/phy: micrel: Disable asymmetric pause for KSZ9031
Mugunthan V N (2):
drivers: net: cpsw: dual_emac: fix reducing of rx descriptor during ifdown
drivers: net: cpsw: dual_emac: in suspend/resume bring down/up all the netdev
Neil Horman (2):
3c59x: Add dma error checking and recovery
3c59x: Fix bad offset spec in skb_frag_dma_map
Nicolas Dichtel (2):
genetlink: add function genl_has_listeners()
macvlan: allow to enqueue broadcast pkt on virtual device
Nikolay Aleksandrov (1):
bonding: fix div by zero while enslaving and transmitting
Oliver Hartkopp (1):
can: peak_pci: add PCI ID definition pcie card variant
Or Gerlitz (1):
mlx4: Fix wrong endianess access with QP context flags
Oren Givon (1):
iwlwifi: add PCI IDs and add then new 3165 series
Randy Dunlap (2):
scsi: fix build errors, SCSI_FC_ATTRS needs to depend on SCSI && NET
scsi: use 'depends' instead of 'select' for SCSI_FC_ATTRS
Roger Quadros (1):
can: c_can_platform: fix parameters of c_can_hw_raminit_ti()
Sabrina Dubroca (1):
ipv6: clean up anycast when an interface is destroyed
Samuel Gauthier (1):
openvswitch: restore OVS_FLOW_CMD_NEW notifications
Steffen Klassert (2):
xfrm: Generate blackhole routes only from route lookup functions
xfrm: Generate queueing routes only from route lookup functions
Sujith Manoharan (1):
Revert "ath9k: Calculate sleep duration"
Tobias Klauser (1):
dm9000: Return an ERR_PTR() in all error conditions of dm9000_parse_dt()
Vlad Yasevich (4):
bridge: Check if vlan filtering is enabled only once.
bridge: Allow clearing of pvid and untagged bitmap
bridge: Fix br_should_learn to check vlan_enabled
tg3: Work around HW/FW limitations with vlan encapsulated frames
hayeswang (4):
r8169: fix the default setting of rx vlan
r8169: fix setting rx vlan
r8169: adjust __rtl8169_set_features
r8152: disable ALDPS
Documentation/networking/filter.txt | 6 +--
arch/sparc/net/bpf_jit_comp.c | 25 +++++++---
drivers/infiniband/hw/mlx4/main.c | 2 +-
drivers/infiniband/hw/mlx4/qp.c | 2 +-
drivers/infiniband/ulp/ipoib/ipoib.h | 6 +++
drivers/infiniband/ulp/ipoib/ipoib_main.c | 4 +-
drivers/message/fusion/Kconfig | 2 +-
drivers/net/bonding/bond_main.c | 19 ++++++--
drivers/net/can/at91_can.c | 8 +--
drivers/net/can/c_can/c_can_platform.c | 4 +-
drivers/net/can/flexcan.c | 53 ++++++++++++++++----
drivers/net/can/sja1000/peak_pci.c | 6 ++-
drivers/net/ethernet/3com/3c59x.c | 50 +++++++++++++++----
drivers/net/ethernet/arc/emac_main.c | 53 ++++++++++++++------
drivers/net/ethernet/broadcom/b44.c | 2 +-
drivers/net/ethernet/broadcom/bcmsysport.c | 31 +++++++-----
drivers/net/ethernet/broadcom/genet/bcmgenet.c | 143 ++++++++++++++++++++++++++++--------------------------
drivers/net/ethernet/broadcom/tg3.c | 20 +++++++-
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 49 ++++++++++---------
drivers/net/ethernet/davicom/dm9000.c | 2 +-
drivers/net/ethernet/mellanox/mlx4/cmd.c | 21 ++++++++
drivers/net/ethernet/mellanox/mlx4/en_ethtool.c | 3 ++
drivers/net/ethernet/mellanox/mlx4/qp.c | 12 ++++-
drivers/net/ethernet/mellanox/mlx4/resource_tracker.c | 38 +++++++++++----
drivers/net/ethernet/octeon/octeon_mgmt.c | 4 +-
drivers/net/ethernet/oki-semi/pch_gbe/Kconfig | 1 +
drivers/net/ethernet/realtek/r8169.c | 67 +++++++++++++------------
drivers/net/ethernet/sfc/farch.c | 3 ++
drivers/net/ethernet/sun/sunvnet.c | 7 ++-
drivers/net/ethernet/ti/cpsw.c | 52 ++++++++++++++++++--
drivers/net/macvlan.c | 4 +-
drivers/net/phy/micrel.c | 3 +-
drivers/net/usb/r8152.c | 62 ++++++++++++++++-------
drivers/net/wireless/ath/ath9k/common-beacon.c | 5 +-
drivers/net/wireless/ath/ath9k/htc_drv_txrx.c | 2 +-
drivers/net/wireless/brcm80211/Kconfig | 10 ++++
drivers/net/wireless/brcm80211/brcmfmac/Makefile | 10 ++--
drivers/net/wireless/brcm80211/brcmfmac/bcdc.h | 7 ++-
drivers/net/wireless/brcm80211/brcmfmac/fweh.c | 12 +++--
drivers/net/wireless/brcm80211/brcmfmac/fweh.h | 2 +
drivers/net/wireless/brcm80211/brcmfmac/msgbuf.h | 11 ++++-
drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c | 9 +++-
drivers/net/wireless/iwlwifi/dvm/power.c | 2 +-
drivers/net/wireless/iwlwifi/iwl-7000.c | 16 ++++++
drivers/net/wireless/iwlwifi/iwl-config.h | 3 ++
drivers/net/wireless/iwlwifi/iwl-nvm-parse.c | 4 +-
drivers/net/wireless/iwlwifi/mvm/coex.c | 9 ++--
drivers/net/wireless/iwlwifi/mvm/debugfs-vif.c | 3 +-
drivers/net/wireless/iwlwifi/mvm/fw-api.h | 4 +-
drivers/net/wireless/iwlwifi/mvm/mac-ctxt.c | 10 ++--
drivers/net/wireless/iwlwifi/mvm/mac80211.c | 25 +++++-----
drivers/net/wireless/iwlwifi/mvm/power.c | 5 +-
drivers/net/wireless/iwlwifi/mvm/rx.c | 6 +--
drivers/net/wireless/iwlwifi/mvm/sf.c | 2 +-
drivers/net/wireless/iwlwifi/mvm/tx.c | 8 ++-
drivers/net/wireless/iwlwifi/pcie/drv.c | 7 +++
drivers/scsi/Kconfig | 20 ++++----
drivers/scsi/bnx2fc/Kconfig | 5 +-
drivers/scsi/bnx2i/Kconfig | 1 +
drivers/scsi/csiostor/Kconfig | 2 +-
drivers/scsi/qla2xxx/Kconfig | 4 +-
include/linux/mlx4/device.h | 1 +
include/linux/mlx4/qp.h | 12 ++++-
include/net/addrconf.h | 1 +
include/net/dst.h | 16 +++++-
include/net/genetlink.h | 8 +++
include/net/sch_generic.h | 3 +-
lib/rhashtable.c | 1 -
net/bridge/br_private.h | 3 ++
net/bridge/br_vlan.c | 16 ++++--
net/core/dev.c | 18 ++++---
net/core/sock.c | 2 +-
net/ipv4/ip_tunnel.c | 6 +--
net/ipv4/route.c | 6 +--
net/ipv6/addrconf.c | 8 +--
net/ipv6/anycast.c | 21 ++++++++
net/ipv6/ip6_output.c | 4 +-
net/mac80211/sta_info.c | 2 +-
net/openvswitch/datapath.c | 9 ++--
net/rfkill/rfkill-gpio.c | 1 +
net/rxrpc/ar-key.c | 2 +-
net/sched/sch_choke.c | 18 +++++--
net/socket.c | 3 ++
net/wireless/nl80211.c | 6 +++
net/xfrm/xfrm_policy.c | 48 +++++++++++++++---
85 files changed, 828 insertions(+), 355 deletions(-)
^ permalink raw reply
* Re: [patch net-next v2 8/9] switchdev: introduce Netlink API
From: Tom Herbert @ 2014-09-22 23:07 UTC (permalink / raw)
To: Thomas Graf
Cc: Alexei Starovoitov, Jiri Pirko, John Fastabend, Jamal Hadi Salim,
netdev@vger.kernel.org, David S. Miller, Neil Horman,
Andy Gospodarek, Daniel Borkmann, Or Gerlitz, Jesse Gross,
Pravin Shelar, Andy Zhou, Ben Hutchings, Stephen Hemminger,
Jeff Kirsher, Vladislav Yasevich, Cong Wang, Eric Dumazet,
Scott Feldman, Florian Fainelli, Roopa Prabhu
In-Reply-To: <20140922225305.GB4708@casper.infradead.org>
On Mon, Sep 22, 2014 at 3:53 PM, Thomas Graf <tgraf@suug.ch> wrote:
> On 09/22/14 at 03:40pm, Tom Herbert wrote:
>> On Mon, Sep 22, 2014 at 3:17 PM, Thomas Graf <tgraf@suug.ch> wrote:
>> > What makes stateful offload interesting to me is that the final
>> > desintation of a packet is known at RX and can be redirected to a
>> > queue or VF. This allows to build packet batches on shared pages
>> > while preserving the securiy model.
>> >
>> How is this different from what rx-filtering already does?
>
> Without stateful offload I can't know where the packet is destined
> to until after I've allocated an skb and parsed the packet in
> software. I might be missing what you refer to here specifically.
n-tuple filtering in as exposed by ethtool.
^ permalink raw reply
* Gneneric Netlink: can two kernel modules register under one family?
From: Sergiy Lozovsky @ 2014-09-22 23:08 UTC (permalink / raw)
To: netdev
Hi,
I plan to use Gneneric Netlink as a messaging bus for endpoints of my
system. Endpoints are kernel modules and user space daemons. Generic
Netlink is designed to accommodate multiple user space processes under
one family, but what if I need multiple kernel modules, too? Is it
feasible? Will genl_register_family() work if called for the same
family from two different kernel modules?
Thanks,
Sergiy.
^ permalink raw reply
* Re: [PATCH] brcmfmac: Fix off by one bug in brcmf_count_20mhz_channels()
From: Emil Goode @ 2014-09-22 23:08 UTC (permalink / raw)
To: Arend van Spriel
Cc: Brett Rudley, Franky (Zhenhui) Lin, Hante Meuleman,
John W. Linville, Pieter-Paul Giesberts, Daniel Kim,
linux-wireless, brcm80211-dev-list, netdev, linux-kernel,
kernel-janitors
In-Reply-To: <541FF25B.9000404@broadcom.com>
[-- Attachment #1: Type: text/plain, Size: 1739 bytes --]
Hello Arend,
Sorry for the late reply. I have attached a kernel log with brcmfmac
debugging enabled (without my patch applied).
Let me know if I can provide any other useful information.
Best regards,
Emil
On Mon, Sep 22, 2014 at 11:56:43AM +0200, Arend van Spriel wrote:
> On 09/21/14 00:58, Emil Goode wrote:
> >In the brcmf_count_20mhz_channels function we are looping through a list
> >of channels received from firmware. Since the index of the first channel
> >is 0 the condition leads to an off by one bug. This is causing us to hit
> >the WARN_ON_ONCE(1) calls in the brcmu_d11n_decchspec function, which is
> >how I discovered the bug.
>
> The fix is fine. Would like to know what exactly is going wrong. Can you
> provide a kernel log with brcmfmac debugging enabled, ie. insmod brcmfmac.ko
> debug=0x1416
>
> Regards,
> Arend
>
> >Introduced by:
> >commit b48d891676f756d48b4d0ee131e4a7a5d43ca417
> >("brcmfmac: rework wiphy structure setup")
> >
> >Signed-off-by: Emil Goode<emilgoode@gmail.com>
> >---
> > drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
> >index 02fe706..93b5dd9 100644
> >--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
> >+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
> >@@ -4918,7 +4918,7 @@ static void brcmf_count_20mhz_channels(struct brcmf_cfg80211_info *cfg,
> > struct brcmu_chan ch;
> > int i;
> >
> >- for (i = 0; i<= total; i++) {
> >+ for (i = 0; i< total; i++) {
> > ch.chspec = (u16)le32_to_cpu(chlist->element[i]);
> > cfg->d11inf.decchspec(&ch);
> >
>
[-- Attachment #2: dmesg_brcmfmac_debug.out --]
[-- Type: text/plain, Size: 87640 bytes --]
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Initializing cgroup subsys cpuacct
[ 0.000000] Linux version 3.17.0-rc6-armv7-x2 (emil@lianli) (gcc version 4.8.3 20140401 (prerelease) (crosstool-NG linaro-1.13.1-4.8-2014.04 - Linaro GCC 4.8-2014.04) ) #3 SMP Mon Sep 22 21:25:25 CEST 2014
[ 0.000000] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine model: Wandboard i.MX6 Quad Board
[ 0.000000] cma: Reserved 16 MiB at 3e800000
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] On node 0 totalpages: 524288
[ 0.000000] free_area_init_node: node 0, pgdat c0f66b40, node_mem_map ed7f0000
[ 0.000000] Normal zone: 1520 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 194560 pages, LIFO batch:31
[ 0.000000] HighMem zone: 2576 pages used for memmap
[ 0.000000] HighMem zone: 329728 pages, LIFO batch:31
[ 0.000000] PERCPU: Embedded 9 pages/cpu @ed7ab000 s14336 r8192 d14336 u36864
[ 0.000000] pcpu-alloc: s14336 r8192 d14336 u36864 alloc=9*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 522768
[ 0.000000] Kernel command line: console=ttymxc0,115200 console=tty0 brcmfmac.debug=0x1416 root=/dev/mmcblk0p5 ro rootfstype=ext4 rootwait video=HDMI-A-1:1024x768@60e
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] allocated 4194304 bytes of page_cgroup
[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
[ 0.000000] Memory: 2042336K/2097152K available (10309K kernel code, 926K rwdata, 3788K rodata, 830K init, 922K bss, 54816K reserved, 1318912K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xffe00000 (2048 kB)
[ 0.000000] vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xef800000 ( 760 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0dcca40 (14099 kB)
[ 0.000000] .init : 0xc0dcd000 - 0xc0e9c800 ( 830 kB)
[ 0.000000] .data : 0xc0e9e000 - 0xc0f859b8 ( 927 kB)
[ 0.000000] .bss : 0xc0f859b8 - 0xc106c51c ( 923 kB)
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU dyntick-idle grace-period acceleration is enabled.
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] L2C-310 erratum 769419 enabled
[ 0.000000] L2C-310 enabling early BRESP for Cortex-A9
[ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[ 0.000000] L2C-310 ID prefetch enabled, offset 1 lines
[ 0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[ 0.000000] L2C-310 cache controller enabled, 16 ways, 1024 kB
[ 0.000000] L2C-310: CACHE_ID 0x410000c7, AUX_CTRL 0x76070001
[ 0.000000] Switching to timer-based delay loop, resolution 15ns
[ 0.000008] sched_clock: 32 bits at 66MHz, resolution 15ns, wraps every 65075262448ns
[ 0.001524] Console: colour dummy device 80x30
[ 0.002213] console [tty0] enabled
[ 0.002248] Calibrating delay loop (skipped), value calculated using timer frequency.. 132.00 BogoMIPS (lpj=660000)
[ 0.002287] pid_max: default: 32768 minimum: 301
[ 0.002430] Security Framework initialized
[ 0.002474] AppArmor: AppArmor disabled by boot time parameter
[ 0.002496] Yama: becoming mindful.
[ 0.002693] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.002726] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.003442] Initializing cgroup subsys memory
[ 0.003492] Initializing cgroup subsys devices
[ 0.003523] Initializing cgroup subsys freezer
[ 0.003554] Initializing cgroup subsys net_cls
[ 0.003587] Initializing cgroup subsys blkio
[ 0.003612] Initializing cgroup subsys perf_event
[ 0.003638] Initializing cgroup subsys net_prio
[ 0.003703] CPU: Testing write buffer coherency: ok
[ 0.003748] ftrace: allocating 34038 entries in 100 pages
[ 0.060864] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.061007] Setting up static identity map for 0x10955578 - 0x10955610
[ 0.069916] CPU1: Booted secondary processor
[ 0.069949] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.071003] CPU2: Booted secondary processor
[ 0.071028] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
[ 0.072065] CPU3: Booted secondary processor
[ 0.072090] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
[ 0.072180] Brought up 4 CPUs
[ 0.072265] SMP: Total of 4 processors activated.
[ 0.072279] CPU: All CPU(s) started in SVC mode.
[ 0.072969] devtmpfs: initialized
[ 0.077467] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[ 0.084771] xor: measuring software checksum speed
[ 0.179596] arm4regs : 1363.200 MB/sec
[ 0.279593] 8regs : 821.200 MB/sec
[ 0.379596] 32regs : 769.200 MB/sec
[ 0.479596] neon : 888.800 MB/sec
[ 0.479611] xor: using function: arm4regs (1363.200 MB/sec)
[ 0.479658] pinctrl core: initialized pinctrl subsystem
[ 0.480118] regulator-dummy: no parameters
[ 0.487918] NET: Registered protocol family 16
[ 0.491141] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.492158] cpuidle: using governor ladder
[ 0.492185] cpuidle: using governor menu
[ 0.492551] CPU identified as i.MX6Q, silicon rev 1.2
[ 0.501208] vdd1p1: 800 <--> 1375 mV at 1100 mV
[ 0.501691] vdd3p0: 2800 <--> 3150 mV at 3000 mV
[ 0.502148] vdd2p5: 2000 <--> 2750 mV at 2400 mV
[ 0.502604] vddarm: 725 <--> 1450 mV at 1150 mV
[ 0.503099] vddpu: 725 <--> 1450 mV at 1150 mV
[ 0.503569] vddsoc: 725 <--> 1450 mV at 1175 mV
[ 0.511979] No ATAGs?
[ 0.512025] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
[ 0.512057] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.513440] imx6q-pinctrl 20e0000.iomuxc: initialized IMX pinctrl driver
[ 0.719826] raid6: int32x1 115 MB/s
[ 0.889868] raid6: int32x2 144 MB/s
[ 1.059773] raid6: int32x4 166 MB/s
[ 1.229753] raid6: int32x8 192 MB/s
[ 1.399641] raid6: neonx1 591 MB/s
[ 1.569643] raid6: neonx2 655 MB/s
[ 1.739665] raid6: neonx4 653 MB/s
[ 1.909671] raid6: neonx8 506 MB/s
[ 1.909688] raid6: using algorithm neonx2 (655 MB/s)
[ 1.909704] raid6: using intx1 recovery algorithm
[ 1.913666] mxs-dma 110000.dma-apbh: initialized
[ 1.914243] edma-dma-engine edma-dma-engine.0: Can't allocate PaRAM dummy slot
[ 1.914284] edma-dma-engine: probe of edma-dma-engine.0 failed with error -22
[ 1.915034] 2P5V: 2500 mV
[ 1.915307] 3P3V: 3300 mV
[ 1.918426] SCSI subsystem initialized
[ 1.918678] libata version 3.00 loaded.
[ 1.918995] usbcore: registered new interface driver usbfs
[ 1.919077] usbcore: registered new interface driver hub
[ 1.919211] usbcore: registered new device driver usb
[ 1.920512] i2c i2c-0: IMX I2C adapter registered
[ 1.921426] i2c i2c-1: IMX I2C adapter registered
[ 1.922000] media: Linux media interface: v0.10
[ 1.922084] Linux video capture interface: v2.00
[ 1.922195] pps_core: LinuxPPS API ver. 1 registered
[ 1.922212] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 1.922256] PTP clock support registered
[ 1.924088] NetLabel: Initializing
[ 1.924112] NetLabel: domain hash size = 128
[ 1.924124] NetLabel: protocols = UNLABELED CIPSOv4
[ 1.924190] NetLabel: unlabeled traffic allowed by default
[ 1.924754] Switched to clocksource mxc_timer1
[ 2.011235] NET: Registered protocol family 2
[ 2.012117] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 2.012227] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[ 2.012364] TCP: Hash tables configured (established 8192 bind 8192)
[ 2.012463] TCP: reno registered
[ 2.012487] UDP hash table entries: 512 (order: 2, 16384 bytes)
[ 2.012553] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[ 2.012878] NET: Registered protocol family 1
[ 2.013390] RPC: Registered named UNIX socket transport module.
[ 2.013413] RPC: Registered udp transport module.
[ 2.013428] RPC: Registered tcp transport module.
[ 2.013443] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 2.014319] hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
[ 2.016732] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 2.016947] audit: initializing netlink subsys (disabled)
[ 2.017005] audit: type=2000 audit(1.989:1): initialized
[ 2.018432] zpool: loaded
[ 2.018462] zbud: loaded
[ 2.018835] VFS: Disk quotas dquot_6.5.2
[ 2.018909] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[ 2.019706] NFS: Registering the id_resolver key type
[ 2.019767] Key type id_resolver registered
[ 2.019782] Key type id_legacy registered
[ 2.019826] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 2.020098] fuse init (API version 7.23)
[ 2.020328] SGI XFS with ACLs, security attributes, realtime, no debug enabled
[ 2.021201] msgmni has been set to 1444
[ 2.022517] bounce: pool size: 64 pages
[ 2.022593] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
[ 2.022779] io scheduler noop registered
[ 2.022808] io scheduler deadline registered
[ 2.022870] io scheduler cfq registered (default)
[ 2.029919] imx-sdma 20ec000.sdma: Direct firmware load for imx/sdma/sdma-imx6q.bin failed with error -2
[ 2.029957] imx-sdma 20ec000.sdma: firmware not found
[ 2.033582] imx-sdma 20ec000.sdma: initialized
[ 2.035822] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.037519] Serial: IMX driver
[ 2.037853] 2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 58, base_baud = 5000000) is a IMX
[ 2.920692] console [ttymxc0] enabled
[ 2.925253] 21ec000.serial: ttymxc2 at MMIO 0x21ec000 (irq = 60, base_baud = 5000000) is a IMX
[ 2.935201] serial: Freescale lpuart driver
[ 2.940292] [drm] Initialized drm 1.1.0 20060810
[ 2.945043] usbcore: registered new interface driver udl
[ 2.950397] Error: Driver 'tfp410' is already registered, aborting...
[ 2.957914] ipu_smfc_init: ioremap 0x02650000 -> f00de000
[ 2.958649] imx-ipuv3 2400000.ipu: IPUv3H probed
[ 2.963613] ipu_smfc_init: ioremap 0x02a50000 -> f012e000
[ 2.964317] imx-ipuv3 2800000.ipu: IPUv3H probed
[ 2.971162] ahci-imx 2200000.sata: fsl,transmit-level-mV not specified, using 00000024
[ 2.979138] ahci-imx 2200000.sata: fsl,transmit-boost-mdB not specified, using 00000480
[ 2.987185] ahci-imx 2200000.sata: fsl,transmit-atten-16ths not specified, using 00002000
[ 2.995401] ahci-imx 2200000.sata: fsl,receive-eq-mdB not specified, using 05000000
[ 3.006413] ahci-imx 2200000.sata: SSS flag set, parallel bus scan disabled
[ 3.013427] ahci-imx 2200000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
[ 3.022269] ahci-imx 2200000.sata: flags: ncq sntf stag pm led clo only pmp pio slum part ccc apst
[ 3.032847] scsi host0: ahci_platform
[ 3.037052] ata1: SATA max UDMA/133 mmio [mem 0x02200000-0x02203fff] port 0x100 irq 71
[ 3.048923] 2188000.ethernet supply phy not found, using dummy regulator
[ 3.079889] libphy: fec_enet_mii_bus: probed
[ 3.084938] fec 2188000.ethernet eth0: registered PHC device 0
[ 3.092045] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 3.098645] ehci-platform: EHCI generic platform driver
[ 3.104132] ehci-omap: OMAP-EHCI Host Controller driver
[ 3.109558] tegra-ehci: Tegra EHCI driver
[ 3.113863] usbcore: registered new interface driver usb-storage
[ 3.125348] 2184200.usb supply vbus not found, using dummy regulator
[ 3.135534] ci_hdrc ci_hdrc.1: doesn't support gadget
[ 3.140617] ci_hdrc ci_hdrc.1: EHCI Host Controller
[ 3.145803] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1
[ 3.164796] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
[ 3.170462] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[ 3.177302] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.184547] usb usb1: Product: EHCI Host Controller
[ 3.189456] usb usb1: Manufacturer: Linux 3.17.0-rc6-armv7-x2 ehci_hcd
[ 3.196017] usb usb1: SerialNumber: ci_hdrc.1
[ 3.201091] hub 1-0:1.0: USB hub found
[ 3.204946] hub 1-0:1.0: 1 port detected
[ 3.209614] using random self ethernet address
[ 3.214084] using random host ethernet address
[ 3.219173] usb0: HOST MAC 7e:c2:60:98:c7:5c
[ 3.223522] usb0: MAC ae:68:07:e8:cf:a2
[ 3.227444] using random self ethernet address
[ 3.231908] using random host ethernet address
[ 3.236427] g_ether gadget: Ethernet Gadget, version: Memorial Day 2008
[ 3.243060] g_ether gadget: g_ether ready
[ 3.247564] mousedev: PS/2 mouse device common for all mice
[ 3.253753] i2c /dev entries driver
[ 3.258260] IR XMP protocol handler initialized
[ 3.265990] imx2-wdt 20bc000.wdog: timeout 60 sec (nowayout=1)
[ 3.272628] sdhci: Secure Digital Host Controller Interface driver
[ 3.278868] sdhci: Copyright(c) Pierre Ossman
[ 3.283914] sdhci-pltfm: SDHCI platform and OF driver helper
[ 3.290507] sdhci-esdhc-imx 2190000.usdhc: could not get ultra high speed state, work on normal mode
[ 3.300855] sdhci-esdhc-imx 2190000.usdhc: No vmmc regulator found
[ 3.307096] sdhci-esdhc-imx 2190000.usdhc: No vqmmc regulator found
[ 3.354799] mmc0: SDHCI controller on 2190000.usdhc [2190000.usdhc] using ADMA
[ 3.362393] sdhci-esdhc-imx 2194000.usdhc: could not get ultra high speed state, work on normal mode
[ 3.372669] sdhci-esdhc-imx 2194000.usdhc: No vmmc regulator found
[ 3.378904] sdhci-esdhc-imx 2194000.usdhc: No vqmmc regulator found
[ 3.385254] ata1: SATA link down (SStatus 0 SControl 300)
[ 3.390717] ahci-imx 2200000.sata: no device found, disabling link.
[ 3.397030] ahci-imx 2200000.sata: pass ahci_imx..hotplug=1 to enable hotplug
[ 3.444785] mmc1: SDHCI controller on 2194000.usdhc [2194000.usdhc] using ADMA
[ 3.453278] sdhci-esdhc-imx 2198000.usdhc: could not get ultra high speed state, work on normal mode
[ 3.462587] sdhci-esdhc-imx 2198000.usdhc: No vmmc regulator found
[ 3.463805] mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
[ 3.465540] mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
[ 3.467273] mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
[ 3.470382] mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
[ 3.474857] mmc1: queuing unknown CIS tuple 0x80 (11 bytes)
[ 3.496401] sdhci-esdhc-imx 2198000.usdhc: No vqmmc regulator found
[ 3.524828] usb 1-1: new high-speed USB device number 2 using ci_hdrc
[ 3.525468] mmc1: new high speed SDIO card at address 0001
[ 3.544792] mmc2: SDHCI controller on 2198000.usdhc [2198000.usdhc] using ADMA
[ 3.552740] ledtrig-cpu: registered to indicate activity on CPUs
[ 3.558889] hidraw: raw HID events driver (C) Jiri Kosina
[ 3.565255] usbcore: registered new interface driver usbhid
[ 3.570850] usbhid: USB HID core driver
[ 3.575518] ashmem: initialized
[ 3.580904] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 3.587582] [drm] No driver support for vblank timestamp query.
[ 3.593661] imx-drm display-subsystem: bound imx-ipuv3-crtc.0 (ops ipu_crtc_ops)
[ 3.601223] imx-drm display-subsystem: bound imx-ipuv3-crtc.1 (ops ipu_crtc_ops)
[ 3.608785] imx-drm display-subsystem: bound imx-ipuv3-crtc.4 (ops ipu_crtc_ops)
[ 3.616319] imx-drm display-subsystem: bound imx-ipuv3-crtc.5 (ops ipu_crtc_ops)
[ 3.623958] imx-hdmi 120000.hdmi: Detected HDMI controller 0x13:0xa:0xa0:0xc1
[ 3.631237] imx-drm display-subsystem: bound 120000.hdmi (ops hdmi_ops)
[ 3.638088] [drm] forcing HDMI-A-1 connector ON
[ 3.649405] mmc2: host does not support reading read-only switch. assuming write-enable.
[ 3.665380] mmc2: new high speed SDHC card at address aaaa
[ 3.671344] mmcblk0: mmc2:aaaa SU16G 14.8 GiB
[ 3.678042] mmcblk0: p1 p2 < p5 >
[ 3.685299] usb 1-1: New USB device found, idVendor=0409, idProduct=005a
[ 3.692027] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 3.700010] hub 1-1:1.0: USB hub found
[ 3.703916] hub 1-1:1.0: 4 ports detected
[ 3.985047] usb 1-1.1: new low-speed USB device number 3 using ci_hdrc
[ 4.117542] usb 1-1.1: New USB device found, idVendor=0461, idProduct=4d03
[ 4.124441] usb 1-1.1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 4.136260] input: HID 0461:4d03 as /devices/soc0/soc/2100000.aips-bus/2184200.usb/ci_hdrc.1/usb1/1-1/1-1.1/1-1.1:1.0/0003:0461:4D03.0001/input/input0
[ 4.150241] hid-generic 0003:0461:4D03.0001: input,hidraw0: USB HID v1.00 Mouse [HID 0461:4d03] on usb-ci_hdrc.1-1.1/input0
[ 4.255041] usb 1-1.3: new low-speed USB device number 4 using ci_hdrc
[ 4.392168] usb 1-1.3: New USB device found, idVendor=04b4, idProduct=0101
[ 4.399088] usb 1-1.3: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 4.406434] usb 1-1.3: Product: SteelS\xffffffec\xffffff80\xffffff81\xffffff80\xffffff81\xffffffcc\xffffff84\xffffff84\xffffffd0\xffffff89\xffffff89\xffffffcc\xffffff92\xffffff92DATA
[ 4.411330] usb 1-1.3: Manufacturer: DATACOMP
[ 4.438206] input: DATACOMP SteelS\xffffffec\xffffff80\xffffff81\xffffff80\xffffff81\xffffffcc\xffffff84\xffffff84\xffffffd0\xffffff89\xffffff89\xffffffcc\xffffff92\xffffff92DATA as /devices/soc0/soc/2100000.aips-bus/2184200.usb/ci_hdrc.1/usb1/1-1/1-1.3/1-1.3:1.0/0003:04B4:0101.0002/input/input1
[ 4.453337] hid-generic 0003:04B4:0101.0002: input,hidraw1: USB HID v1.00 Keyboard [DATACOMP SteelS\xffffffec\xffffff80\xffffff81\xffffff80\xffffff81\xffffffcc\xffffff84\xffffff84\xffffffd0\xffffff89\xffffff89\xffffffcc\xffffff92\xffffff92DATA] on usb-ci_hdrc.1-1.3/input0
[ 4.478521] input: DATACOMP SteelS\xffffffec\xffffff80\xffffff81\xffffff80\xffffff81\xffffffcc\xffffff84\xffffff84\xffffffd0\xffffff89\xffffff89\xffffffcc\xffffff92\xffffff92DATA as /devices/soc0/soc/2100000.aips-bus/2184200.usb/ci_hdrc.1/usb1/1-1/1-1.3/1-1.3:1.1/0003:04B4:0101.0003/input/input2
[ 4.493623] hid-generic 0003:04B4:0101.0003: input,hidraw2: USB HID v1.00 Device [DATACOMP SteelS\xffffffec\xffffff80\xffffff81\xffffff80\xffffff81\xffffffcc\xffffff84\xffffff84\xffffffd0\xffffff89\xffffff89\xffffffcc\xffffff92\xffffff92DATA] on usb-ci_hdrc.1-1.3/input1
[ 4.585051] usb 1-1.4: new low-speed USB device number 5 using ci_hdrc
[ 4.720917] usb 1-1.4: New USB device found, idVendor=0603, idProduct=0002
[ 4.727837] usb 1-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 4.735182] usb 1-1.4: Product: USB Composite Device
[ 4.740164] usb 1-1.4: Manufacturer: SINO WEALTH
[ 4.749184] input: SINO WEALTH USB Composite Device as /devices/soc0/soc/2100000.aips-bus/2184200.usb/ci_hdrc.1/usb1/1-1/1-1.4/1-1.4:1.0/0003:0603:0002.0004/input/input3
[ 4.764626] hid-generic 0003:0603:0002.0004: input,hidraw3: USB HID v1.10 Keyboard [SINO WEALTH USB Composite Device] on usb-ci_hdrc.1-1.4/input0
[ 4.785351] input: SINO WEALTH USB Composite Device as /devices/soc0/soc/2100000.aips-bus/2184200.usb/ci_hdrc.1/usb1/1-1/1-1.4/1-1.4:1.1/0003:0603:0002.0005/input/input4
[ 4.801193] hid-generic 0003:0603:0002.0005: input,hiddev0,hidraw4: USB HID v1.10 Mouse [SINO WEALTH USB Composite Device] on usb-ci_hdrc.1-1.4/input1
[ 6.234418] Console: switching to colour frame buffer device 128x48
[ 6.246062] imx-drm display-subsystem: fb0: frame buffer device
[ 6.252150] imx-drm display-subsystem: registered panic notifier
[ 6.324791] [drm] Initialized imx-drm 1.0.0 20120507 on minor 0
[ 6.332822] oprofile: using arm/armv7-ca9
[ 6.337152] TCP: cubic registered
[ 6.340627] NET: Registered protocol family 10
[ 6.346212] mip6: Mobile IPv6
[ 6.349250] NET: Registered protocol family 17
[ 6.353850] Key type dns_resolver registered
[ 6.358214] mpls_gso: MPLS GSO support
[ 6.364172] ThumbEE CPU extension supported.
[ 6.368564] Registering SWP/SWPB emulation handler
[ 6.373936] registered taskstats version 1
[ 6.380867] Btrfs loaded
[ 6.386419] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 6.394862] sr_init: No PMIC hook to init smartreflex
[ 6.402113] sr_init: platform driver register failed for SR
[ 6.417198] PM: Hibernation image not present or could not be loaded.
[ 6.439362] EXT4-fs (mmcblk0p5): mounted filesystem with ordered data mode. Opts: (null)
[ 6.449628] VFS: Mounted root (ext4 filesystem) readonly on device 179:5.
[ 6.463357] devtmpfs: mounted
[ 6.469707] Freeing unused kernel memory: 828K (c0dcd000 - c0e9c000)
[ 7.240832] udevd[199]: starting version 175
[ 7.884268] snvs_rtc 20cc034.snvs-rtc-lp: rtc core: registered 20cc034.snvs-rtc-lp as rtc0
[ 8.151673] sgtl5000 1-000a: sgtl5000 revision 0x11
[ 8.164962] imx-sgtl5000 sound: ASoC: CODEC (null) not registered
[ 8.186470] imx-sgtl5000 sound: snd_soc_register_card failed (-517)
[ 8.201157] platform sound: Driver imx-sgtl5000 requests probe deferral
[ 8.214101] imx-spdif sound-spdif: snd-soc-dummy-dai <-> 2004000.spdif mapping ok
[ 8.219468] 1-000a: 1200 mV normal
[ 8.219541] sgtl5000 1-000a: Using internal LDO instead of VDDD
[ 8.237027] cfg80211: Calling CRDA to update world regulatory domain
[ 8.269419] imx-sgtl5000 sound: sgtl5000 <-> 2028000.ssi mapping ok
[ 8.288297] brcmfmac: brcmf_sdiod_sgtable_alloc nents=35
[ 8.288317] brcmfmac: brcmf_sdio_probe Enter
[ 8.293231] brcmfmac: F1 signature read @0x18000000=0x16044330
[ 8.293341] brcmfmac: brcmf_bus_change_state 0 -> 2
[ 8.293695] brcmfmac: brcmf_chip_recognition found AXI chip: BCM4330, rev=4
[ 8.298171] brcmfmac: brcmf_chip_cores_check [1 ] core 0x800:39 base 0x18000000 wrap 0x18100000
[ 8.298201] brcmfmac: brcmf_chip_cores_check [2 ] core 0x812:25 base 0x18001000 wrap 0x18101000
[ 8.298214] brcmfmac: brcmf_chip_cores_check [3 ] core 0x829:7 base 0x18002000 wrap 0x18102000
[ 8.298222] brcmfmac: brcmf_chip_cores_check [4 ] core 0x82a:3 base 0x18003000 wrap 0x18103000
[ 8.298230] brcmfmac: brcmf_chip_cores_check [5 ] core 0x80e:13 base 0x18004000 wrap 0x18104000
[ 8.298237] brcmfmac: brcmf_chip_cores_check [6 ] core 0x81a:11 base 0x18005000 wrap 0x18105000
[ 8.298245] brcmfmac: brcmf_chip_cores_check [7 ] core 0x135:0 base 0x18108000 wrap 0x18106000
[ 8.298493] brcmfmac: brcmf_chip_setup ccrev=39, pmurev=12, pmucaps=0x19583c0c
[ 8.298834] brcmfmac: brcmf_sdio_kso_init Enter
[ 8.299106] brcmfmac: brcmf_sdio_drivestrengthinit SDIO: 4 mA (req=6 mA) drive strength selected, set to 0x00000001
[ 8.302079] brcmfmac: brcmf_attach Enter
[ 8.302174] brcmfmac: brcmf_proto_attach Enter
[ 8.302518] brcmfmac: brcmf_sdio_probe completed!!
[ 8.302538] brcmfmac: brcmf_fw_get_firmwares enter: dev=mmc1:0001:1
[ 8.328297] brcmfmac: brcmf_fw_request_code_done enter: dev=mmc1:0001:1
[ 8.336630] brcmfmac: brcmf_fw_request_nvram_done enter: dev=mmc1:0001:1
[ 8.336742] brcmfmac: brcmf_nvram_handle_key warning: ln=117:col=37: '=' expected, skip invalid key entry
[ 8.336756] brcmfmac: brcmf_nvram_handle_key warning: ln=118:col=37: '=' expected, skip invalid key entry
[ 8.336793] brcmfmac: brcmf_sdio_firmware_callback Enter: dev=mmc1:0001:1
[ 8.336916] brcmfmac: brcmf_chip_enter_download Enter
[ 8.339765] brcmfmac: brcmf_sdio_download_code_file Enter
[ 8.355128] brcmfmac: brcmf_sdio_verifymemory Compare RAM dl & ul at 0x00000000; size=222126
[ 8.394467] brcmfmac: brcmf_sdio_download_nvram Enter
[ 8.394846] brcmfmac: brcmf_sdio_verifymemory Compare RAM dl & ul at 0x00047b18; size=1256
[ 8.395209] brcmfmac: brcmf_chip_exit_download Enter
[ 8.395933] brcmfmac: brcmf_bus_change_state 2 -> 3
[ 8.505174] random: nonblocking pool is initialized
[ 8.630982] cfg80211: World regulatory domain updated:
[ 8.639267] cfg80211: DFS Master region: unset
[ 8.643726] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp), (dfs_cac_time)
[ 8.650197] brcmfmac: brcmf_sdio_firmware_callback enable F2: err=0
[ 8.650292] brcmfmac: brcmf_chip_sr_capable Enter
[ 8.650473] brcmfmac: brcmf_bus_start
[ 8.650480] brcmfmac: brcmf_add_if Enter, idx=0, ifidx=0
[ 8.650483] brcmfmac: brcmf_add_if allocate netdev interface
[ 8.650515] brcmfmac: brcmf_add_if ==== pid:26, if:wlan%d (00:00:00:00:00:00) created ===
[ 8.650518] brcmfmac: brcmf_bus_change_state 3 -> 4
[ 8.650532] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.650573] brcmfmac: brcmf_sdio_isr Enter
[ 8.650703] brcmfmac: brcmf_sdio_dpc Enter
[ 8.650707] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.650784] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.651604] brcmfmac: brcmf_sdio_dpc Dongle reports CHIPACTIVE
[ 8.651608] brcmfmac: brcmf_sdio_readframes Enter
[ 8.651644] brcmfmac: brcmf_sdio_isr Enter
[ 8.651885] brcmfmac: brcmf_sdio_read_control Enter
[ 8.651953] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 36 expected 36
[ 8.651963] brcmfmac: brcmf_fil_iovar_data_get name=cur_etheraddr, len=6
[ 8.651966] brcmutil: data
[ 8.651972] 00000000: fc 4d d4 c5 2b 66 .M..+f
[ 8.651979] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.651995] brcmfmac: brcmf_sdio_dpc Enter
[ 8.652518] brcmfmac: brcmf_sdio_readframes Enter
[ 8.652588] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.652661] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.652809] brcmfmac: brcmf_sdio_isr Enter
[ 8.652964] brcmfmac: brcmf_sdio_dpc Enter
[ 8.652970] brcmfmac: brcmf_sdio_readframes Enter
[ 8.653060] brcmfmac: brcmf_sdio_read_control Enter
[ 8.653200] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 276 expected 276
[ 8.653207] brcmfmac: brcmf_fil_iovar_data_get name=ver, len=256
[ 8.653211] brcmutil: data
[ 8.653216] 00000000: 77 6c 30 3a 20 4f 63 74 20 32 35 20 32 30 31 31 wl0: Oct 25 2011
[ 8.653220] 00000010: 20 31 39 3a 33 34 3a 31 32 20 76 65 72 73 69 6f 19:34:12 versio
[ 8.653223] 00000020: 6e 20 35 2e 39 30 2e 31 32 35 2e 31 30 34 0a 00 n 5.90.125.104..
[ 8.653226] 00000030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[ 8.653230] brcmfmac: brcmf_c_preinit_dcmds: Firmware version = wl0: Oct 25 2011 19:34:12 version 5.90.125.104
[ 8.653236] brcmfmac: brcmf_fil_iovar_data_set name=mpc, len=4
[ 8.653238] brcmutil: data
[ 8.653241] 00000000: 01 00 00 00 ....
[ 8.653245] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.653250] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.653316] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.653423] brcmfmac: brcmf_sdio_isr Enter
[ 8.653544] brcmfmac: brcmf_sdio_dpc Enter
[ 8.653552] brcmfmac: brcmf_sdio_readframes Enter
[ 8.653614] brcmfmac: brcmf_sdio_read_control Enter
[ 8.653666] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 24 expected 24
[ 8.653675] brcmfmac: brcmf_fil_iovar_data_set name=bcn_timeout, len=4
[ 8.653678] brcmutil: data
[ 8.653682] 00000000: 03 00 00 00 ....
[ 8.653687] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.653712] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.653784] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.653913] brcmfmac: brcmf_sdio_isr Enter
[ 8.654033] brcmfmac: brcmf_sdio_dpc Enter
[ 8.654040] brcmfmac: brcmf_sdio_readframes Enter
[ 8.654103] brcmfmac: brcmf_sdio_read_control Enter
[ 8.654158] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 32 expected 32
[ 8.654167] brcmfmac: brcmf_fil_iovar_data_set name=roam_off, len=4
[ 8.654169] brcmutil: data
[ 8.654174] 00000000: 01 00 00 00 ....
[ 8.654178] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.654202] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.654267] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.654413] brcmfmac: brcmf_sdio_isr Enter
[ 8.654529] brcmfmac: brcmf_sdio_dpc Enter
[ 8.654535] brcmfmac: brcmf_sdio_readframes Enter
[ 8.654598] brcmfmac: brcmf_sdio_read_control Enter
[ 8.654644] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 29 expected 29
[ 8.654651] brcmfmac: brcmf_fil_iovar_data_set name=join_pref, len=8
[ 8.654654] brcmutil: data
[ 8.654659] 00000000: 04 02 08 01 01 02 00 00 ........
[ 8.654663] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.654692] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.654813] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.654860] brcmfmac: brcmf_sdio_isr Enter
[ 8.654976] brcmfmac: brcmf_sdio_dpc Enter
[ 8.654986] brcmfmac: brcmf_sdio_readframes Enter
[ 8.655049] brcmfmac: brcmf_sdio_read_control Enter
[ 8.655093] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.655099] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.655148] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.655213] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.655325] brcmfmac: brcmf_sdio_isr Enter
[ 8.655445] brcmfmac: brcmf_sdio_dpc Enter
[ 8.655452] brcmfmac: brcmf_sdio_readframes Enter
[ 8.655515] brcmfmac: brcmf_sdio_read_control Enter
[ 8.655569] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 44 expected 44
[ 8.655577] brcmfmac: brcmf_fil_iovar_data_get name=event_msgs, len=17
[ 8.655580] brcmutil: data
[ 8.655585] 00000000: 00 00 00 00 00 00 60 00 00 04 00 00 00 00 00 00 ......`.........
[ 8.655588] 00000010: 00 .
[ 8.655593] brcmfmac: brcmf_fil_iovar_data_set name=event_msgs, len=17
[ 8.655596] brcmutil: data
[ 8.655599] 00000000: 00 00 00 00 00 00 60 00 00 04 00 00 00 00 00 00 ......`.........
[ 8.655602] 00000010: 00 .
[ 8.655606] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.655611] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.655681] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.655795] brcmfmac: brcmf_sdio_isr Enter
[ 8.655914] brcmfmac: brcmf_sdio_dpc Enter
[ 8.655921] brcmfmac: brcmf_sdio_readframes Enter
[ 8.655982] brcmfmac: brcmf_sdio_read_control Enter
[ 8.656045] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 44 expected 44
[ 8.656054] brcmfmac: brcmf_fil_cmd_int_set cmd=185, value=40
[ 8.656058] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.656084] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.656149] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.656226] brcmfmac: brcmf_sdio_isr Enter
[ 8.656339] brcmfmac: brcmf_sdio_dpc Enter
[ 8.656346] brcmfmac: brcmf_sdio_readframes Enter
[ 8.656411] brcmfmac: brcmf_sdio_read_control Enter
[ 8.656462] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 8.656469] brcmfmac: brcmf_fil_cmd_int_set cmd=187, value=40
[ 8.656473] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.656503] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.656562] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.656647] brcmfmac: brcmf_sdio_isr Enter
[ 8.656762] brcmfmac: brcmf_sdio_dpc Enter
[ 8.656769] brcmfmac: brcmf_sdio_readframes Enter
[ 8.656831] brcmfmac: brcmf_sdio_read_control Enter
[ 8.656883] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 8.656898] brcmfmac: brcmf_fil_iovar_data_set name=pkt_filter_add, len=22
[ 8.656901] brcmutil: data
[ 8.656907] 00000000: 64 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d...............
[ 8.656911] 00000010: 01 00 00 00 01 00 ......
[ 8.656915] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.656921] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.656986] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.657282] brcmfmac: brcmf_sdio_isr Enter
[ 8.657400] brcmfmac: brcmf_sdio_dpc Enter
[ 8.657407] brcmfmac: brcmf_sdio_readframes Enter
[ 8.657464] brcmfmac: brcmf_sdio_read_control Enter
[ 8.657562] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 53 expected 53
[ 8.657573] brcmfmac: brcmf_fil_iovar_data_set name=pkt_filter_enable, len=8
[ 8.657575] brcmutil: data
[ 8.657580] 00000000: 64 00 00 00 00 00 00 00 d.......
[ 8.657585] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.657591] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.657668] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.657955] brcmfmac: brcmf_sdio_isr Enter
[ 8.658083] brcmfmac: brcmf_sdio_dpc Enter
[ 8.658090] brcmfmac: brcmf_sdio_readframes Enter
[ 8.658161] brcmfmac: brcmf_sdio_read_control Enter
[ 8.658211] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 42 expected 42
[ 8.658218] brcmfmac: brcmf_fil_iovar_data_set name=pkt_filter_mode, len=4
[ 8.658221] brcmutil: data
[ 8.658225] 00000000: 01 00 00 00 ....
[ 8.658230] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.658291] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.658362] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.658656] brcmfmac: brcmf_sdio_isr Enter
[ 8.658792] brcmfmac: brcmf_sdio_dpc Enter
[ 8.658801] brcmfmac: brcmf_sdio_readframes Enter
[ 8.658869] brcmfmac: brcmf_sdio_read_control Enter
[ 8.658924] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 36 expected 36
[ 8.658934] brcmfmac: brcmf_fil_iovar_data_set name=bus:txglom, len=4
[ 8.658937] brcmutil: data
[ 8.658942] 00000000: 00 00 00 00 ....
[ 8.658946] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.658969] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.659029] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.659114] brcmfmac: brcmf_sdio_isr Enter
[ 8.659237] brcmfmac: brcmf_sdio_dpc Enter
[ 8.659243] brcmfmac: brcmf_sdio_readframes Enter
[ 8.659305] brcmfmac: brcmf_sdio_read_control Enter
[ 8.659357] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 31 expected 31
[ 8.659365] brcmfmac: brcmf_fil_iovar_data_set name=bus:rxglom, len=4
[ 8.659368] brcmutil: data
[ 8.659373] 00000000: 01 00 00 00 ....
[ 8.659379] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.659384] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.659445] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.659503] brcmfmac: brcmf_sdio_isr Enter
[ 8.659625] brcmfmac: brcmf_sdio_dpc Enter
[ 8.659632] brcmfmac: brcmf_sdio_readframes Enter
[ 8.659692] brcmfmac: brcmf_sdio_read_control Enter
[ 8.659743] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 31 expected 31
[ 8.659751] brcmfmac: brcmf_fil_cmd_data Failed err=-23
[ 8.659758] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.659796] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.659854] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.660114] brcmfmac: brcmf_sdio_isr Enter
[ 8.660244] brcmfmac: brcmf_sdio_dpc Enter
[ 8.660251] brcmfmac: brcmf_sdio_readframes Enter
[ 8.660314] brcmfmac: brcmf_sdio_read_control Enter
[ 8.660364] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 26 expected 26
[ 8.660370] brcmfmac: brcmf_fil_cmd_data Failed err=-23
[ 8.660374] brcmfmac: brcmf_fil_iovar_data_get name=mchan, len=4
[ 8.660376] brcmutil: data
[ 8.660383] 00000000: 80 5d be eb .]..
[ 8.660388] brcmfmac: brcmf_feat_iovar_int_get MCHAN feature check failed: -23
[ 8.660452] brcmfmac: brcmf_fws_init FWS queueing will be avoided
[ 8.660460] brcmfmac: brcmf_fws_macdesc_init enter: desc ebe15030 ea=fc:4d:d4:c5:2b:66, ifidx=0
[ 8.660466] brcmfmac: brcmf_fws_add_interface added MACIF:0
[ 8.660670] brcmfmac: brcmf_alloc_vif allocating virtual interface (size=2700)
[ 8.660699] brcmfmac: brcmf_fweh_register event handler registered for LINK
[ 8.660703] brcmfmac: brcmf_fweh_register event handler registered for DEAUTH_IND
[ 8.660707] brcmfmac: brcmf_fweh_register event handler registered for DEAUTH
[ 8.660710] brcmfmac: brcmf_fweh_register event handler registered for DISASSOC_IND
[ 8.660713] brcmfmac: brcmf_fweh_register event handler registered for ASSOC_IND
[ 8.660719] brcmfmac: brcmf_fweh_register event handler registered for REASSOC_IND
[ 8.660722] brcmfmac: brcmf_fweh_register event handler registered for ROAM
[ 8.660725] brcmfmac: brcmf_fweh_register event handler registered for MIC_ERROR
[ 8.660728] brcmfmac: brcmf_fweh_register event handler registered for SET_SSID
[ 8.660733] brcmfmac: brcmf_fweh_register event handler registered for PFN_NET_FOUND
[ 8.660737] brcmfmac: brcmf_fweh_register event handler registered for IF
[ 8.660741] brcmfmac: brcmf_fweh_register event handler registered for P2P_PROBEREQ_MSG
[ 8.660745] brcmfmac: brcmf_fweh_register event handler registered for P2P_DISC_LISTEN_COMPLETE
[ 8.660758] brcmfmac: brcmf_fweh_register event handler registered for ACTION_FRAME_RX
[ 8.660767] brcmfmac: brcmf_fweh_register event handler registered for ACTION_FRAME_COMPLETE
[ 8.660772] brcmfmac: brcmf_fweh_register event handler registered for ACTION_FRAME_OFF_CHAN_COMPLETE
[ 8.660776] brcmfmac: brcmf_fweh_register event handler registered for ESCAN_RESULT
[ 8.660783] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.660789] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.660872] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.660941] brcmfmac: brcmf_sdio_isr Enter
[ 8.661072] brcmfmac: brcmf_sdio_dpc Enter
[ 8.661080] brcmfmac: brcmf_sdio_readframes Enter
[ 8.661147] brcmfmac: brcmf_sdio_read_control Enter
[ 8.661222] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 8.661229] brcmfmac: brcmf_fil_cmd_int_get cmd=1, value=1
[ 8.661237] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.661266] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.661340] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.661605] brcmfmac: brcmf_sdio_isr Enter
[ 8.661773] brcmfmac: brcmf_sdio_dpc Enter
[ 8.661782] brcmfmac: brcmf_sdio_readframes Enter
[ 8.661872] brcmfmac: brcmf_sdio_read_control Enter
[ 8.661947] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 28 expected 28
[ 8.661954] brcmfmac: brcmf_fil_cmd_data Failed err=-23
[ 8.661958] brcmfmac: brcmf_fil_iovar_data_get name=vhtmode, len=4
[ 8.661961] brcmutil: data
[ 8.661967] 00000000: 00 00 00 00 ....
[ 8.661974] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.662004] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.662069] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.662196] brcmfmac: brcmf_sdio_isr Enter
[ 8.662317] brcmfmac: brcmf_sdio_dpc Enter
[ 8.662324] brcmfmac: brcmf_sdio_readframes Enter
[ 8.662389] brcmfmac: brcmf_sdio_read_control Enter
[ 8.662440] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 26 expected 26
[ 8.662448] brcmfmac: brcmf_fil_iovar_data_get name=nmode, len=4
[ 8.662451] brcmutil: data
[ 8.662455] 00000000: 01 00 00 00 ....
[ 8.662461] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.662483] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.662546] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.662840] brcmfmac: brcmf_sdio_isr Enter
[ 8.662971] brcmfmac: brcmf_sdio_dpc Enter
[ 8.662978] brcmfmac: brcmf_sdio_readframes Enter
[ 8.663045] brcmfmac: brcmf_sdio_read_control Enter
[ 8.663095] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 27 expected 27
[ 8.663104] brcmfmac: brcmf_fil_cmd_data Failed err=-23
[ 8.663109] brcmfmac: brcmf_fil_iovar_data_get name=bw_cap, len=4
[ 8.663111] brcmutil: data
[ 8.663116] 00000000: 02 00 00 00 ....
[ 8.663119] brcmfmac: brcmf_get_bwcap fallback to mimo_bw_cap info
[ 8.663124] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.663146] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.663214] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.663378] brcmfmac: brcmf_sdio_isr Enter
[ 8.663502] brcmfmac: brcmf_sdio_dpc Enter
[ 8.663509] brcmfmac: brcmf_sdio_readframes Enter
[ 8.663581] brcmfmac: brcmf_sdio_read_control Enter
[ 8.663638] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 32 expected 32
[ 8.663645] brcmfmac: brcmf_fil_iovar_data_get name=mimo_bw_cap, len=4
[ 8.663650] brcmutil: data
[ 8.663654] 00000000: 00 00 00 00 ....
[ 8.663660] brcmfmac: brcmf_setup_wiphybands nmode=1, vhtmode=0, bw_cap=(1, 1)
[ 8.663664] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.663686] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.663758] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.663879] brcmfmac: brcmf_sdio_isr Enter
[ 8.664073] brcmfmac: brcmf_sdio_dpc Enter
[ 8.664082] brcmfmac: brcmf_sdio_readframes Enter
[ 8.664342] brcmfmac: brcmf_sdio_read_control Enter
[ 8.664409] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 28 expected 28
[ 8.664417] brcmfmac: brcmf_fil_iovar_data_get name=rxchain, len=4
[ 8.664419] brcmutil: data
[ 8.664424] 00000000: 01 00 00 00 ....
[ 8.664429] brcmfmac: brcmf_setup_wiphybands nchain=1
[ 8.664439] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.664446] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.664596] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.666618] brcmfmac: brcmf_sdio_isr Enter
[ 8.666812] brcmfmac: brcmf_sdio_dpc Enter
[ 8.666822] brcmfmac: brcmf_sdio_readframes Enter
[ 8.666889] brcmfmac: brcmf_sdio_read_control Enter
[ 8.667104] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 1562 expected 1562
[ 8.667114] brcmfmac: brcmf_fil_iovar_data_get name=chanspecs, len=1536
[ 8.667117] brcmutil: data
[ 8.667122] 00000000: 11 00 00 00 01 2b 00 00 02 2b 00 00 03 2b 00 00 .....+...+...+..
[ 8.667127] 00000010: 04 2b 00 00 05 2b 00 00 06 2b 00 00 07 2b 00 00 .+...+...+...+..
[ 8.667130] 00000020: 08 2b 00 00 09 2b 00 00 0a 2b 00 00 0b 2b 00 00 .+...+...+...+..
[ 8.667133] 00000030: 0c 2b 00 00 0d 2b 00 00 24 1b 00 00 28 1b 00 00 .+...+..$...(...
[ 8.667138] ------------[ cut here ]------------
[ 8.667158] WARNING: CPU: 1 PID: 38 at drivers/net/wireless/brcm80211/brcmutil/d11.c:128 brcmu_d11n_decchspec+0xfc/0x10c [brcmutil]()
[ 8.667194] Modules linked in: brcmfmac brcmutil cfg80211 snd_soc_imx_spdif snd_soc_imx_sgtl5000 snd_soc_imx_audmux snd_soc_sgtl5000 snd_soc_fsl_ssi snd_soc_fsl_spdif imx_pcm_fiq imx_pcm_dma snd_soc_core snd_compress snd_pcm_dmaengine snd_pcm snd_seq snd_seq_device snd_timer snd soundcore rtc_snvs
[ 8.667202] CPU: 1 PID: 38 Comm: kworker/1:1 Not tainted 3.17.0-rc6-armv7-x2 #3
[ 8.667222] Workqueue: events request_firmware_work_func
[ 8.667246] [<c0018e78>] (unwind_backtrace) from [<c0013978>] (show_stack+0x20/0x24)
[ 8.667261] [<c0013978>] (show_stack) from [<c094cd68>] (dump_stack+0x8c/0x9c)
[ 8.667284] [<c094cd68>] (dump_stack) from [<c0053f48>] (warn_slowpath_common+0x80/0x9c)
[ 8.667295] [<c0053f48>] (warn_slowpath_common) from [<c0054020>] (warn_slowpath_null+0x2c/0x34)
[ 8.667308] [<c0054020>] (warn_slowpath_null) from [<bf305b58>] (brcmu_d11n_decchspec+0xfc/0x10c [brcmutil])
[ 8.667473] [<bf305b58>] (brcmu_d11n_decchspec [brcmutil]) from [<bf31b798>] (brcmf_cfg80211_attach+0x6e8/0x118c [brcmfmac])
[ 8.667628] [<bf31b798>] (brcmf_cfg80211_attach [brcmfmac]) from [<bf32a408>] (brcmf_bus_start+0xe0/0x298 [brcmfmac])
[ 8.667798] [<bf32a408>] (brcmf_bus_start [brcmfmac]) from [<bf32f0bc>] (brcmf_sdio_firmware_callback+0x48c/0x628 [brcmfmac])
[ 8.667965] [<bf32f0bc>] (brcmf_sdio_firmware_callback [brcmfmac]) from [<bf32acb0>] (brcmf_fw_request_nvram_done+0x144/0x1dc [brcmfmac])
[ 8.668060] [<bf32acb0>] (brcmf_fw_request_nvram_done [brcmfmac]) from [<c0603f08>] (request_firmware_work_func+0x40/0x60)
[ 8.668083] [<c0603f08>] (request_firmware_work_func) from [<c006b2c0>] (process_one_work+0x158/0x3c4)
[ 8.668105] [<c006b2c0>] (process_one_work) from [<c006bc44>] (worker_thread+0x68/0x534)
[ 8.668122] [<c006bc44>] (worker_thread) from [<c00705bc>] (kthread+0xe8/0x100)
[ 8.668140] [<c00705bc>] (kthread) from [<c000f858>] (ret_from_fork+0x14/0x20)
[ 8.668145] ---[ end trace dfea49328ba94d5f ]---
[ 8.668148] ------------[ cut here ]------------
[ 8.668162] WARNING: CPU: 1 PID: 38 at drivers/net/wireless/brcm80211/brcmutil/d11.c:140 brcmu_d11n_decchspec+0x8c/0x10c [brcmutil]()
[ 8.668196] Modules linked in: brcmfmac brcmutil cfg80211 snd_soc_imx_spdif snd_soc_imx_sgtl5000 snd_soc_imx_audmux snd_soc_sgtl5000 snd_soc_fsl_ssi snd_soc_fsl_spdif imx_pcm_fiq imx_pcm_dma snd_soc_core snd_compress snd_pcm_dmaengine snd_pcm snd_seq snd_seq_device snd_timer snd soundcore rtc_snvs
[ 8.668202] CPU: 1 PID: 38 Comm: kworker/1:1 Tainted: G W 3.17.0-rc6-armv7-x2 #3
[ 8.668212] Workqueue: events request_firmware_work_func
[ 8.668228] [<c0018e78>] (unwind_backtrace) from [<c0013978>] (show_stack+0x20/0x24)
[ 8.668239] [<c0013978>] (show_stack) from [<c094cd68>] (dump_stack+0x8c/0x9c)
[ 8.668267] [<c094cd68>] (dump_stack) from [<c0053f48>] (warn_slowpath_common+0x80/0x9c)
[ 8.668277] [<c0053f48>] (warn_slowpath_common) from [<c0054020>] (warn_slowpath_null+0x2c/0x34)
[ 8.668290] [<c0054020>] (warn_slowpath_null) from [<bf305ae8>] (brcmu_d11n_decchspec+0x8c/0x10c [brcmutil])
[ 8.668390] [<bf305ae8>] (brcmu_d11n_decchspec [brcmutil]) from [<bf31b798>] (brcmf_cfg80211_attach+0x6e8/0x118c [brcmfmac])
[ 8.668543] [<bf31b798>] (brcmf_cfg80211_attach [brcmfmac]) from [<bf32a408>] (brcmf_bus_start+0xe0/0x298 [brcmfmac])
[ 8.668726] [<bf32a408>] (brcmf_bus_start [brcmfmac]) from [<bf32f0bc>] (brcmf_sdio_firmware_callback+0x48c/0x628 [brcmfmac])
[ 8.668883] [<bf32f0bc>] (brcmf_sdio_firmware_callback [brcmfmac]) from [<bf32acb0>] (brcmf_fw_request_nvram_done+0x144/0x1dc [brcmfmac])
[ 8.668967] [<bf32acb0>] (brcmf_fw_request_nvram_done [brcmfmac]) from [<c0603f08>] (request_firmware_work_func+0x40/0x60)
[ 8.668982] [<c0603f08>] (request_firmware_work_func) from [<c006b2c0>] (process_one_work+0x158/0x3c4)
[ 8.668993] [<c006b2c0>] (process_one_work) from [<c006bc44>] (worker_thread+0x68/0x534)
[ 8.669002] [<c006bc44>] (worker_thread) from [<c00705bc>] (kthread+0xe8/0x100)
[ 8.669013] [<c00705bc>] (kthread) from [<c000f858>] (ret_from_fork+0x14/0x20)
[ 8.669019] ---[ end trace dfea49328ba94d60 ]---
[ 8.669034] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.669042] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.669141] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.669237] brcmfmac: brcmf_sdio_isr Enter
[ 8.669375] brcmfmac: brcmf_sdio_dpc Enter
[ 8.669383] brcmfmac: brcmf_sdio_readframes Enter
[ 8.669456] brcmfmac: brcmf_sdio_read_control Enter
[ 8.669517] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.669525] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.669528] brcmutil: data
[ 8.669533] 00000000: 03 00 00 00 ....
[ 8.669543] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.669548] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.669616] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.669744] brcmfmac: brcmf_sdio_isr Enter
[ 8.669892] brcmfmac: brcmf_sdio_dpc Enter
[ 8.669900] brcmfmac: brcmf_sdio_readframes Enter
[ 8.669989] brcmfmac: brcmf_sdio_read_control Enter
[ 8.670051] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.670058] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.670060] brcmutil: data
[ 8.670065] 00000000: 03 00 00 00 ....
[ 8.670073] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.670102] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.670174] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.670280] brcmfmac: brcmf_sdio_isr Enter
[ 8.670412] brcmfmac: brcmf_sdio_dpc Enter
[ 8.670419] brcmfmac: brcmf_sdio_readframes Enter
[ 8.670491] brcmfmac: brcmf_sdio_read_control Enter
[ 8.670545] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.670553] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.670556] brcmutil: data
[ 8.670561] 00000000: 03 00 00 00 ....
[ 8.670567] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.670591] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.670657] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.670763] brcmfmac: brcmf_sdio_isr Enter
[ 8.670892] brcmfmac: brcmf_sdio_dpc Enter
[ 8.670899] brcmfmac: brcmf_sdio_readframes Enter
[ 8.671887] brcmfmac: brcmf_sdio_read_control Enter
[ 8.671939] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.671950] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.671954] brcmutil: data
[ 8.671959] 00000000: 03 00 00 00 ....
[ 8.671966] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.672028] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.672108] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.672217] brcmfmac: brcmf_sdio_isr Enter
[ 8.672340] brcmfmac: brcmf_sdio_dpc Enter
[ 8.672351] brcmfmac: brcmf_sdio_readframes Enter
[ 8.672409] brcmfmac: brcmf_sdio_read_control Enter
[ 8.672463] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.672471] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.672475] brcmutil: data
[ 8.672480] 00000000: 03 00 00 00 ....
[ 8.672489] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.672496] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.672554] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.672668] brcmfmac: brcmf_sdio_isr Enter
[ 8.672794] brcmfmac: brcmf_sdio_dpc Enter
[ 8.672803] brcmfmac: brcmf_sdio_readframes Enter
[ 8.672899] brcmfmac: brcmf_sdio_read_control Enter
[ 8.672971] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.672979] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.672982] brcmutil: data
[ 8.672988] 00000000: 03 00 00 00 ....
[ 8.672996] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.673030] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.673114] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.673226] brcmfmac: brcmf_sdio_isr Enter
[ 8.673370] brcmfmac: brcmf_sdio_dpc Enter
[ 8.673378] brcmfmac: brcmf_sdio_readframes Enter
[ 8.673457] brcmfmac: brcmf_sdio_read_control Enter
[ 8.673536] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.673543] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.673546] brcmutil: data
[ 8.673551] 00000000: 03 00 00 00 ....
[ 8.673559] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.673596] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.673667] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.673783] brcmfmac: brcmf_sdio_isr Enter
[ 8.673916] brcmfmac: brcmf_sdio_dpc Enter
[ 8.673924] brcmfmac: brcmf_sdio_readframes Enter
[ 8.674031] brcmfmac: brcmf_sdio_read_control Enter
[ 8.674091] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.674098] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.674101] brcmutil: data
[ 8.674106] 00000000: 03 00 00 00 ....
[ 8.674115] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.674153] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.674220] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.674338] brcmfmac: brcmf_sdio_isr Enter
[ 8.674470] brcmfmac: brcmf_sdio_dpc Enter
[ 8.674477] brcmfmac: brcmf_sdio_readframes Enter
[ 8.674546] brcmfmac: brcmf_sdio_read_control Enter
[ 8.674599] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.674609] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.674612] brcmutil: data
[ 8.674617] 00000000: 03 00 00 00 ....
[ 8.674624] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.674654] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.674721] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.674848] brcmfmac: brcmf_sdio_isr Enter
[ 8.674962] brcmfmac: brcmf_sdio_dpc Enter
[ 8.674970] brcmfmac: brcmf_sdio_readframes Enter
[ 8.675031] brcmfmac: brcmf_sdio_read_control Enter
[ 8.675098] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.675106] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.675108] brcmutil: data
[ 8.675113] 00000000: 03 00 00 00 ....
[ 8.675122] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.675128] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.675197] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.675312] brcmfmac: brcmf_sdio_isr Enter
[ 8.675582] brcmfmac: brcmf_sdio_dpc Enter
[ 8.675590] brcmfmac: brcmf_sdio_readframes Enter
[ 8.675671] brcmfmac: brcmf_sdio_read_control Enter
[ 8.675730] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.675740] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.675743] brcmutil: data
[ 8.675749] 00000000: 03 00 00 00 ....
[ 8.675757] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.675766] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.675831] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.675941] brcmfmac: brcmf_sdio_isr Enter
[ 8.676073] brcmfmac: brcmf_sdio_dpc Enter
[ 8.676080] brcmfmac: brcmf_sdio_readframes Enter
[ 8.676145] brcmfmac: brcmf_sdio_read_control Enter
[ 8.676200] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.676208] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.676211] brcmutil: data
[ 8.676215] 00000000: 03 00 00 00 ....
[ 8.676224] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.676252] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.676320] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.676434] brcmfmac: brcmf_sdio_isr Enter
[ 8.676572] brcmfmac: brcmf_sdio_dpc Enter
[ 8.676579] brcmfmac: brcmf_sdio_readframes Enter
[ 8.676658] brcmfmac: brcmf_sdio_read_control Enter
[ 8.676721] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.676728] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.676731] brcmutil: data
[ 8.676735] 00000000: 03 00 00 00 ....
[ 8.676746] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.676775] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.676840] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.676972] brcmfmac: brcmf_sdio_isr Enter
[ 8.677152] brcmfmac: brcmf_sdio_dpc Enter
[ 8.677185] brcmfmac: brcmf_sdio_readframes Enter
[ 8.677343] brcmfmac: brcmf_sdio_read_control Enter
[ 8.677424] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.677431] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.677434] brcmutil: data
[ 8.677439] 00000000: 07 00 00 00 ....
[ 8.677452] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.677545] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.677623] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.677732] brcmfmac: brcmf_sdio_isr Enter
[ 8.677858] brcmfmac: brcmf_sdio_dpc Enter
[ 8.677865] brcmfmac: brcmf_sdio_readframes Enter
[ 8.677936] brcmfmac: brcmf_sdio_read_control Enter
[ 8.677984] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.677992] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.677996] brcmutil: data
[ 8.678000] 00000000: 07 00 00 00 ....
[ 8.678007] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.678036] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.678102] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.678221] brcmfmac: brcmf_sdio_isr Enter
[ 8.678541] brcmfmac: brcmf_sdio_dpc Enter
[ 8.678548] brcmfmac: brcmf_sdio_readframes Enter
[ 8.678626] brcmfmac: brcmf_sdio_read_control Enter
[ 8.678683] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.678693] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.678696] brcmutil: data
[ 8.678700] 00000000: 07 00 00 00 ....
[ 8.678708] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 8.678734] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 8.678804] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 8.678943] brcmfmac: brcmf_sdio_isr Enter
[ 8.680229] brcmfmac: brcmf_sdio_dpc Enter
[ 8.680237] brcmfmac: brcmf_sdio_readframes Enter
[ 8.680328] brcmfmac: brcmf_sdio_read_control Enter
[ 8.680388] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 34 expected 34
[ 8.680397] brcmfmac: brcmf_fil_bsscfg_data_get bssidx=0, name=per_chan_info, len=4
[ 8.680401] brcmutil: data
[ 8.680407] 00000000: 07 00 00 00 ....
[ 8.680419] brcmfmac: brcmf_cfg80211_attach Registering custom regulatory
[ 9.202144] cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A)
[ 9.213039] cfg80211: (2457000 KHz - 2482000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A)
[ 9.223880] cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (N/A, 2000 mBm), (N/A)
[ 9.234696] cfg80211: (5170000 KHz - 5250000 KHz @ 80000 KHz), (N/A, 2000 mBm), (N/A)
[ 9.245458] cfg80211: (5735000 KHz - 5835000 KHz @ 80000 KHz), (N/A, 2000 mBm), (N/A)
[ 9.256214] cfg80211: (57240000 KHz - 63720000 KHz @ 2160000 KHz), (N/A, 0 mBm), (N/A)
[ 9.267520] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 9.295616] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 9.295714] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 9.295772] brcmfmac: brcmf_sdio_isr Enter
[ 9.295900] brcmfmac: brcmf_sdio_dpc Enter
[ 9.295953] brcmfmac: brcmf_sdio_isr Enter
[ 9.296086] brcmfmac: brcmf_sdio_dpc Dongle reports CHIPACTIVE
[ 9.296098] brcmfmac: brcmf_sdio_readframes Enter
[ 9.296162] brcmfmac: brcmf_sdio_read_control Enter
[ 9.296237] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 27 expected 27
[ 9.296252] brcmfmac: brcmf_fil_cmd_data Failed err=-23
[ 9.296260] brcmfmac: brcmf_fil_iovar_data_get name=bw_cap, len=4
[ 9.296266] brcmutil: data
[ 9.296274] 00000000: 01 00 00 00 ....
[ 9.296281] brcmfmac: brcmf_enable_bw40_2g fallback to mimo_bw_cap
[ 9.296289] brcmfmac: brcmf_fil_iovar_data_set name=mimo_bw_cap, len=4
[ 9.296294] brcmutil: data
[ 9.296302] 00000000: 01 00 00 00 ....
[ 9.296311] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 9.296332] brcmfmac: brcmf_sdio_dpc Enter
[ 9.296351] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 9.296409] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 9.296534] brcmfmac: brcmf_sdio_isr Enter
[ 9.296633] brcmfmac: brcmf_sdio_dpc Enter
[ 9.296643] brcmfmac: brcmf_sdio_readframes Enter
[ 9.296698] brcmfmac: brcmf_sdio_read_control Enter
[ 9.296753] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 32 expected 32
[ 9.296769] brcmfmac: brcmf_fil_cmd_data Failed err=-23
[ 9.296777] brcmfmac: brcmf_btcoex_attach enter
[ 9.296785] brcmfmac: brcmf_fil_iovar_data_set name=tdls_enable, len=4
[ 9.296790] brcmutil: data
[ 9.296797] 00000000: 01 00 00 00 ....
[ 9.296804] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 9.296831] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 9.296883] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 9.297134] brcmfmac: brcmf_sdio_isr Enter
[ 9.297230] brcmfmac: brcmf_sdio_dpc Enter
[ 9.297240] brcmfmac: brcmf_sdio_readframes Enter
[ 9.297294] brcmfmac: brcmf_sdio_read_control Enter
[ 9.297349] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 32 expected 32
[ 9.297363] brcmfmac: brcmf_fil_cmd_data Failed err=-23
[ 9.297370] brcmfmac: brcmf_cfg80211_attach TDLS not enabled (-23)
[ 9.297380] brcmfmac: brcmf_fweh_activate_events enable event SET_SSID
[ 9.297387] brcmfmac: brcmf_fweh_activate_events enable event DEAUTH
[ 9.297393] brcmfmac: brcmf_fweh_activate_events enable event DEAUTH_IND
[ 9.297399] brcmfmac: brcmf_fweh_activate_events enable event ASSOC_IND
[ 9.297406] brcmfmac: brcmf_fweh_activate_events enable event REASSOC_IND
[ 9.297412] brcmfmac: brcmf_fweh_activate_events enable event DISASSOC_IND
[ 9.297418] brcmfmac: brcmf_fweh_activate_events enable event LINK
[ 9.297424] brcmfmac: brcmf_fweh_activate_events enable event MIC_ERROR
[ 9.297430] brcmfmac: brcmf_fweh_activate_events enable event ROAM
[ 9.297438] brcmfmac: brcmf_fweh_activate_events enable event PFN_NET_FOUND
[ 9.297445] brcmfmac: brcmf_fweh_activate_events enable event IF
[ 9.297451] brcmfmac: brcmf_fweh_activate_events enable event P2P_DISC_LISTEN_COMPLETE
[ 9.297457] brcmfmac: brcmf_fweh_activate_events enable event ACTION_FRAME_COMPLETE
[ 9.297464] brcmfmac: brcmf_fweh_activate_events enable event ESCAN_RESULT
[ 9.297470] brcmfmac: brcmf_fweh_activate_events enable event ACTION_FRAME_OFF_CHAN_COMPLETE
[ 9.297476] brcmfmac: brcmf_fweh_activate_events enable event P2P_PROBEREQ_MSG
[ 9.297483] brcmfmac: brcmf_fweh_activate_events enable event ACTION_FRAME_RX
[ 9.297489] brcmfmac: brcmf_fweh_activate_events enable event IF
[ 9.297495] brcmfmac: brcmf_fil_iovar_data_set name=event_msgs, len=17
[ 9.297500] brcmutil: data
[ 9.297507] 00000000: ff 15 0b 00 02 03 c0 13 60 09 00 00 00 ec 9d b3 ........`.......
[ 9.297514] 00000010: ec .
[ 9.297520] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 9.297548] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 9.297604] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 9.297714] brcmfmac: brcmf_sdio_isr Enter
[ 9.297813] brcmfmac: brcmf_sdio_dpc Enter
[ 9.297823] brcmfmac: brcmf_sdio_readframes Enter
[ 9.297876] brcmfmac: brcmf_sdio_read_control Enter
[ 9.297930] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 44 expected 44
[ 9.297946] brcmfmac: brcmf_net_attach Enter, idx=0 mac=fc:4d:d4:c5:2b:66
[ 9.298620] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 9.298655] brcmfmac: brcmf_net_attach wlan0: Broadcom Dongle Host Driver
[ 10.309372] EXT4-fs (mmcblk0p5): re-mounted. Opts: (null)
[ 10.471555] EXT4-fs (mmcblk0p5): re-mounted. Opts: errors=remount-ro
[ 10.750107] loop: module loaded
[ 12.198301] EXT4-fs (mmcblk0p1): mounting ext2 file system using the ext4 subsystem
[ 12.214301] EXT4-fs (mmcblk0p1): mounted filesystem without journal. Opts: (null)
[ 13.016438] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 14.208955] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 14.209007] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 14.584652] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
[ 18.384229] zram: Created 4 device(s) ...
[ 18.602185] zram0: detected capacity change from 0 to 527245312
[ 18.605456] zram1: detected capacity change from 0 to 527245312
[ 18.608619] zram2: detected capacity change from 0 to 527245312
[ 18.613187] zram3: detected capacity change from 0 to 527245312
[ 19.273758] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 19.273856] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 19.345217] Bluetooth: Core ver 2.19
[ 19.352959] NET: Registered protocol family 31
[ 19.361112] Bluetooth: HCI device and connection manager initialized
[ 19.371102] Bluetooth: HCI socket layer initialized
[ 19.380603] Bluetooth: L2CAP socket layer initialized
[ 19.389801] Bluetooth: SCO socket layer initialized
[ 19.423502] Bluetooth: RFCOMM TTY layer initialized
[ 19.423538] Bluetooth: RFCOMM socket layer initialized
[ 19.423566] Bluetooth: RFCOMM ver 1.11
[ 19.455197] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[ 19.455202] Bluetooth: BNEP filters: protocol multicast
[ 19.455235] Bluetooth: BNEP socket layer initialized
[ 19.578975] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 19.579163] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 19.621390] Adding 514884k swap on /dev/zram0. Priority:100 extents:1 across:514884k SSFS
[ 19.789953] Adding 514884k swap on /dev/zram1. Priority:100 extents:1 across:514884k SSFS
[ 19.905471] Adding 514884k swap on /dev/zram2. Priority:100 extents:1 across:514884k SSFS
[ 20.021249] Adding 514884k swap on /dev/zram3. Priority:100 extents:1 across:514884k SSFS
[ 20.318397] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.318486] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.319478] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.319550] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.319837] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.319890] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.425200] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.425326] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.426980] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.427048] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.427358] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.427416] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.427760] IPv6: ADDRCONF(NETDEV_UP): usb0: link is not ready
[ 20.435745] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.435803] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.436012] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.436054] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.436264] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.436307] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.436502] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.436544] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.436741] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.436782] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.437268] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.437319] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.437568] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.437612] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.438087] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.438131] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.506082] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.506138] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.506701] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.506754] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.506950] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.506992] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.575185] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.575296] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.594413] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.594538] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.595062] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.595131] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.675333] fec 2188000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=2188000.ethernet:01, irq=-1)
[ 20.689292] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 20.698255] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.698353] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.698702] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.698760] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.698993] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.699059] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.699268] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.699315] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.699543] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.699590] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.700136] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.700199] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.700435] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.700486] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.700823] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.700865] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.703195] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.703279] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.706078] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.706142] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.706414] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.706464] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.706627] brcmfmac: brcmf_netdev_open Enter, idx=0
[ 20.706641] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.734998] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.735089] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.735146] brcmfmac: brcmf_sdio_isr Enter
[ 20.735259] brcmfmac: brcmf_sdio_dpc Enter
[ 20.735317] brcmfmac: brcmf_sdio_isr Enter
[ 20.735426] brcmfmac: brcmf_sdio_dpc Dongle reports CHIPACTIVE
[ 20.735435] brcmfmac: brcmf_sdio_readframes Enter
[ 20.735493] brcmfmac: brcmf_sdio_read_control Enter
[ 20.735572] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 27 expected 27
[ 20.735583] brcmfmac: brcmf_sdio_dpc Enter
[ 20.735588] brcmfmac: brcmf_fil_iovar_data_get name=toe_ol, len=4
[ 20.735595] brcmutil: data
[ 20.735600] 00000000: 00 00 00 00 ....
[ 20.735608] brcmfmac: brcmf_fil_cmd_int_set cmd=2, value=0
[ 20.735613] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.735618] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.735695] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.820144] brcmfmac: brcmf_sdio_isr Enter
[ 20.820328] brcmfmac: brcmf_sdio_dpc Enter
[ 20.820462] brcmfmac: brcmf_sdio_readframes Enter
[ 20.820546] brcmfmac: brcmf_sdio_read_control Enter
[ 20.820734] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 20.820749] brcmfmac: brcmf_fil_cmd_int_set cmd=185, value=40
[ 20.820757] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.820803] brcmfmac: brcmf_fweh_event_worker event IF (54) ifidx 0 bsscfg 0 addr fc:4d:d4:c5:2b:66
[ 20.820823] brcmfmac: brcmf_fweh_event_worker version 2 flags 0 status 0 reason 0
[ 20.820832] brcmutil: event payload, len=5
[ 20.820845] 00000000: 00 01 00 00 00 .....
[ 20.820857] brcmfmac: brcmf_fweh_handle_if_event action: 1 idx: 0 bsscfg: 0 flags: 0 role: 0
[ 20.820869] brcmfmac: brcmf_fweh_handle_if_event adding wl0 (fc:4d:d4:c5:2b:66)
[ 20.820879] brcmfmac: brcmf_add_if Enter, idx=0, ifidx=0
[ 20.820888] brcmfmac: brcmf_add_if: ERROR: netdev:wlan0 already exists
[ 20.829489] brcmfmac: brcmf_add_if: ignore IF event
[ 20.831147] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.831232] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.831307] brcmfmac: brcmf_sdio_isr Enter
[ 20.831420] brcmfmac: brcmf_sdio_dpc Enter
[ 20.831427] brcmfmac: brcmf_sdio_readframes Enter
[ 20.831489] brcmfmac: brcmf_sdio_read_control Enter
[ 20.831562] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 20.831574] brcmfmac: brcmf_fil_cmd_int_set cmd=187, value=40
[ 20.831578] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.831603] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.831665] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.831746] brcmfmac: brcmf_sdio_isr Enter
[ 20.831858] brcmfmac: brcmf_sdio_dpc Enter
[ 20.831864] brcmfmac: brcmf_sdio_readframes Enter
[ 20.831922] brcmfmac: brcmf_sdio_read_control Enter
[ 20.831983] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 20.831994] brcmfmac: brcmf_fil_cmd_int_set cmd=258, value=120
[ 20.831999] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.832022] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.832082] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.832165] brcmfmac: brcmf_sdio_isr Enter
[ 20.832279] brcmfmac: brcmf_sdio_dpc Enter
[ 20.832284] brcmfmac: brcmf_sdio_readframes Enter
[ 20.832345] brcmfmac: brcmf_sdio_read_control Enter
[ 20.832405] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 20.832416] brcmfmac: brcmf_fil_cmd_int_set cmd=86, value=2
[ 20.832420] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.832444] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.832504] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.832848] brcmfmac: brcmf_sdio_isr Enter
[ 20.832957] brcmfmac: brcmf_sdio_dpc Enter
[ 20.832963] brcmfmac: brcmf_sdio_readframes Enter
[ 20.833023] brcmfmac: brcmf_sdio_read_control Enter
[ 20.833084] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 20.833094] brcmfmac: brcmf_config_dongle power save set to enabled
[ 20.833098] brcmfmac: brcmf_dongle_roam Internal Roaming = On
[ 20.833105] brcmfmac: brcmf_fil_iovar_data_set name=roam_off, len=4
[ 20.833108] brcmutil: data
[ 20.833112] 00000000: 00 00 00 00 ....
[ 20.833117] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.833142] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.833205] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.833345] brcmfmac: brcmf_sdio_isr Enter
[ 20.833460] brcmfmac: brcmf_sdio_dpc Enter
[ 20.833467] brcmfmac: brcmf_sdio_readframes Enter
[ 20.833527] brcmfmac: brcmf_sdio_read_control Enter
[ 20.833587] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 29 expected 29
[ 20.833598] brcmfmac: brcmf_fil_cmd_data_set cmd=55, len=8
[ 20.833600] brcmutil: data
[ 20.833605] 00000000: b5 ff ff ff 03 00 00 00 ........
[ 20.833608] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.833633] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.833695] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.833754] brcmfmac: brcmf_sdio_isr Enter
[ 20.833866] brcmfmac: brcmf_sdio_dpc Enter
[ 20.833872] brcmfmac: brcmf_sdio_readframes Enter
[ 20.833930] brcmfmac: brcmf_sdio_read_control Enter
[ 20.833991] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 24 expected 24
[ 20.834001] brcmfmac: brcmf_fil_cmd_data_set cmd=57, len=8
[ 20.834003] brcmutil: data
[ 20.834007] 00000000: 14 00 00 00 03 00 00 00 ........
[ 20.834011] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.834038] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.834098] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.834158] brcmfmac: brcmf_sdio_isr Enter
[ 20.834269] brcmfmac: brcmf_sdio_dpc Enter
[ 20.834276] brcmfmac: brcmf_sdio_readframes Enter
[ 20.834335] brcmfmac: brcmf_sdio_read_control Enter
[ 20.834396] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 24 expected 24
[ 20.834408] brcmfmac: brcmf_cfg80211_change_iface Enter, ndev=ebbe5800, type=2
[ 20.834413] brcmfmac: brcmf_fil_cmd_int_set cmd=20, value=1
[ 20.834417] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.834441] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.834504] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.834564] brcmfmac: brcmf_sdio_isr Enter
[ 20.834676] brcmfmac: brcmf_sdio_dpc Enter
[ 20.834682] brcmfmac: brcmf_sdio_readframes Enter
[ 20.834786] brcmfmac: brcmf_sdio_read_control Enter
[ 20.834858] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 20.834863] brcmfmac: brcmf_cfg80211_change_iface IF Type = Infra
[ 20.834872] brcmfmac: brcmf_cfg80211_change_iface Exit
[ 20.834879] brcmfmac: brcmf_fil_iovar_data_set name=arp_ol, len=4
[ 20.834882] brcmutil: data
[ 20.834886] 00000000: 09 00 00 00 ....
[ 20.834892] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.834927] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.835401] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.835444] brcmfmac: brcmf_sdio_isr Enter
[ 20.835561] brcmfmac: brcmf_sdio_dpc Enter
[ 20.835567] brcmfmac: brcmf_sdio_readframes Enter
[ 20.835627] brcmfmac: brcmf_sdio_read_control Enter
[ 20.835690] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 27 expected 27
[ 20.835701] brcmfmac: brcmf_fil_iovar_data_set name=arpoe, len=4
[ 20.835704] brcmutil: data
[ 20.835707] 00000000: 01 00 00 00 ....
[ 20.835711] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.835736] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.835797] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.835975] brcmfmac: brcmf_sdio_isr Enter
[ 20.836088] brcmfmac: brcmf_sdio_dpc Enter
[ 20.836095] brcmfmac: brcmf_sdio_readframes Enter
[ 20.836158] brcmfmac: brcmf_sdio_read_control Enter
[ 20.836221] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 26 expected 26
[ 20.836231] brcmfmac: brcmf_configure_arp_offload successfully configured (1) ARP offload to 0x9
[ 20.836269] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.836411] brcmfmac: brcmf_cfg80211_set_power_mgmt Enter
[ 20.836416] brcmfmac: brcmf_cfg80211_set_power_mgmt power save enabled
[ 20.836422] brcmfmac: brcmf_fil_cmd_int_set cmd=86, value=2
[ 20.836427] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.836459] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.836499] brcmfmac: _brcmf_set_multicast_list Enter, idx=0
[ 20.836517] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.836594] brcmfmac: brcmf_sdio_isr Enter
[ 20.836718] brcmfmac: brcmf_sdio_dpc Enter
[ 20.836726] brcmfmac: brcmf_sdio_readframes Enter
[ 20.836792] brcmfmac: brcmf_sdio_read_control Enter
[ 20.836862] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 20.836881] brcmfmac: brcmf_cfg80211_set_power_mgmt Exit
[ 20.837081] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.837133] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.837353] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.837392] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.838034] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.838087] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.838302] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.838342] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.838710] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.838746] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.843452] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.844885] brcmfmac: brcmf_fil_iovar_data_set name=mcast_list, len=16
[ 20.844890] brcmutil: data
[ 20.844897] 00000000: 02 00 00 00 33 33 00 00 00 01 01 00 5e 00 00 01 ....33......^...
[ 20.844907] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.844917] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.845150] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.845206] brcmfmac: brcmf_sdio_isr Enter
[ 20.845481] brcmfmac: brcmf_sdio_dpc Enter
[ 20.845499] brcmfmac: brcmf_sdio_readframes Enter
[ 20.846627] brcmfmac: brcmf_sdio_read_control Enter
[ 20.854868] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 43 expected 43
[ 20.854890] brcmfmac: brcmf_fil_iovar_data_set name=allmulti, len=4
[ 20.854900] brcmutil: data
[ 20.854911] 00000000: 00 00 00 00 ....
[ 20.854920] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.855155] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.855245] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.855410] brcmfmac: brcmf_sdio_isr Enter
[ 20.855581] brcmfmac: brcmf_sdio_dpc Enter
[ 20.855595] brcmfmac: brcmf_sdio_readframes Enter
[ 20.855662] brcmfmac: brcmf_sdio_read_control Enter
[ 20.855732] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 29 expected 29
[ 20.855751] brcmfmac: brcmf_fil_cmd_int_set cmd=10, value=0
[ 20.855758] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.855789] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.855853] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.855922] brcmfmac: brcmf_sdio_isr Enter
[ 20.856040] brcmfmac: brcmf_sdio_dpc Enter
[ 20.856055] brcmfmac: brcmf_sdio_readframes Enter
[ 20.856119] brcmfmac: brcmf_sdio_read_control Enter
[ 20.856176] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 20.856190] brcmfmac: _brcmf_set_multicast_list Enter, idx=0
[ 20.856196] brcmfmac: brcmf_fil_iovar_data_set name=mcast_list, len=22
[ 20.856200] brcmutil: data
[ 20.856208] 00000000: 03 00 00 00 33 33 00 00 00 01 01 00 5e 00 00 01 ....33......^...
[ 20.856226] 00000010: 33 33 ff c5 2b 66 33..+f
[ 20.856231] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.856257] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.856328] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.856455] brcmfmac: brcmf_sdio_isr Enter
[ 20.856578] brcmfmac: brcmf_sdio_dpc Enter
[ 20.856586] brcmfmac: brcmf_sdio_readframes Enter
[ 20.856651] brcmfmac: brcmf_sdio_read_control Enter
[ 20.856715] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 49 expected 49
[ 20.856729] brcmfmac: brcmf_fil_iovar_data_set name=allmulti, len=4
[ 20.856732] brcmutil: data
[ 20.856737] 00000000: 00 00 00 00 ....
[ 20.856742] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.856769] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.856834] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.856987] brcmfmac: brcmf_sdio_isr Enter
[ 20.857115] brcmfmac: brcmf_sdio_dpc Enter
[ 20.857122] brcmfmac: brcmf_sdio_readframes Enter
[ 20.857189] brcmfmac: brcmf_sdio_read_control Enter
[ 20.857254] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 29 expected 29
[ 20.857266] brcmfmac: brcmf_fil_cmd_int_set cmd=10, value=0
[ 20.857270] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 20.857296] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 20.857359] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 20.857420] brcmfmac: brcmf_sdio_isr Enter
[ 20.857541] brcmfmac: brcmf_sdio_dpc Enter
[ 20.857548] brcmfmac: brcmf_sdio_readframes Enter
[ 20.857605] brcmfmac: brcmf_sdio_read_control Enter
[ 20.857670] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 20.858106] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.858179] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.864867] brcmfmac: brcmf_sdio_bus_txdata Enter: pkt: data ebcca01e len 94
[ 20.864874] brcmfmac: brcmf_sdio_bus_txdata deferring pktq len 0
[ 20.864985] brcmfmac: brcmf_sdio_dpc Enter
[ 20.865002] brcmfmac: brcmf_sdio_sendfromq Enter
[ 20.865009] brcmfmac: brcmf_sdio_txpkt Enter
[ 20.947407] brcmfmac: brcmf_netdev_get_stats Enter, idx=0
[ 20.947972] brcmfmac: brcmf_cfg80211_mgmt_frame_register Enter, frame_type 00d0, reg=1
[ 20.948022] brcmfmac: brcmf_cfg80211_mgmt_frame_register Enter, frame_type 00d0, reg=1
[ 20.948068] brcmfmac: brcmf_cfg80211_mgmt_frame_register Enter, frame_type 00d0, reg=1
[ 20.948110] brcmfmac: brcmf_cfg80211_mgmt_frame_register Enter, frame_type 00d0, reg=1
[ 20.948151] brcmfmac: brcmf_cfg80211_mgmt_frame_register Enter, frame_type 00d0, reg=1
[ 20.948194] brcmfmac: brcmf_cfg80211_mgmt_frame_register Enter, frame_type 00d0, reg=1
[ 20.948236] brcmfmac: brcmf_cfg80211_mgmt_frame_register Enter, frame_type 00d0, reg=1
[ 21.025308] brcmfmac: brcmf_cfg80211_flush_pmksa Enter
[ 21.025326] brcmfmac: brcmf_fil_iovar_data_set name=pmkid_info, len=360
[ 21.025333] brcmutil: data
[ 21.025342] 00000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[ 21.025349] 00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[ 21.025356] 00000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[ 21.025362] 00000030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[ 21.025372] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 21.033023] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 21.033114] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 21.033246] brcmfmac: brcmf_sdio_isr Enter
[ 21.033366] brcmfmac: brcmf_sdio_dpc Enter
[ 21.033378] brcmfmac: brcmf_sdio_readframes Enter
[ 21.033447] brcmfmac: brcmf_sdio_read_control Enter
[ 21.033572] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 387 expected 387
[ 21.033582] brcmfmac: brcmf_cfg80211_flush_pmksa Exit
[ 21.046802] brcmfmac: brcmf_cfg80211_scan Enter
[ 21.046824] brcmfmac: brcmf_vif_set_mgmt_ie bssidx 0, pktflag : 0x10
[ 21.046836] brcmfmac: brcmf_fil_cmd_int_set cmd=49, value=0
[ 21.046844] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 21.047064] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 21.047147] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 21.047208] brcmfmac: brcmf_sdio_isr Enter
[ 21.047349] brcmfmac: brcmf_sdio_dpc Enter
[ 21.047363] brcmfmac: brcmf_sdio_readframes Enter
[ 21.047575] brcmfmac: brcmf_sdio_read_control Enter
[ 21.047656] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 20 expected 20
[ 21.047678] brcmfmac: brcmf_fil_iovar_data_set name=escan, len=144
[ 21.047685] brcmutil: data
[ 21.047696] 00000000: 01 00 00 00 01 00 34 12 00 00 00 00 00 00 00 00 ......4.........
[ 21.047703] 00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[ 21.047710] 00000020: 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff ff ................
[ 21.047716] 00000030: ff ff 02 00 ff ff ff ff ff ff ff ff ff ff ff ff ................
[ 21.047726] brcmfmac: brcmf_sdio_bus_txctl Enter
[ 21.047803] brcmfmac: brcmf_sdio_tx_ctrlframe Enter
[ 21.047868] brcmfmac: brcmf_sdio_bus_rxctl Enter
[ 21.048708] brcmfmac: brcmf_sdio_isr Enter
[ 21.048814] brcmfmac: brcmf_sdio_dpc Enter
[ 21.048826] brcmfmac: brcmf_sdio_readframes Enter
[ 21.048881] brcmfmac: brcmf_sdio_read_control Enter
[ 21.048976] brcmfmac: brcmf_sdio_bus_rxctl resumed on rxctl frame, got 166 expected 166
[ 21.048987] brcmfmac: brcmf_cfg80211_scan Exit
[ 21.064809] brcmfmac: brcmf_sdio_bus_txdata Enter: pkt: data ebcca01e len 94
[ 21.064822] brcmfmac: brcmf_sdio_bus_txdata deferring pktq len 0
[ 21.064861] brcmfmac: brcmf_sdio_dpc Enter
[ 21.064940] brcmfmac: brcmf_sdio_sendfromq Enter
[ 21.064952] brcmfmac: brcmf_sdio_txpkt Enter
[ 21.279155] brcmfmac: brcmf_sdio_isr Enter
[ 21.279282] brcmfmac: brcmf_sdio_dpc Enter
[ 21.279379] brcmfmac: brcmf_sdio_readframes Enter
[ 21.279557] brcmfmac: brcmf_fweh_event_worker event ESCAN_RESULT (69) ifidx 0 bsscfg 0 addr 00:00:00:00:00:00
[ 21.279574] brcmfmac: brcmf_fweh_event_worker version 2 flags 0 status 8 reason 0
[ 21.279581] brcmutil: event payload, len=280
^ permalink raw reply
* [PATCH net-next] net: introduce __skb_header_release()
From: Eric Dumazet @ 2014-09-22 23:29 UTC (permalink / raw)
To: David Miller; +Cc: netdev
From: Eric Dumazet <edumazet@google.com>
While profiling TCP stack, I noticed one useless atomic operation
in tcp_sendmsg(), caused by skb_header_release().
It turns out all current skb_header_release() users have a fresh skb,
that no other user can see, so we can avoid one atomic operation.
Introduce __skb_header_release() to clearly document this.
This gave me a 1.5 % improvement on TCP_RR workload.
Signed-off-by: Eric Dumazet <edumazet@google.com>
---
include/linux/skbuff.h | 15 +++++++++++++++
net/core/skbuff.c | 4 ++--
net/ipv4/tcp.c | 4 ++--
net/ipv4/tcp_output.c | 10 +++++-----
4 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index f1bfa3781c75..8eaa62400fca 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -1083,6 +1083,7 @@ static inline int skb_header_cloned(const struct sk_buff *skb)
* Drop a reference to the header part of the buffer. This is done
* by acquiring a payload reference. You must not read from the header
* part of skb->data after this.
+ * Note : Check if you can use __skb_header_release() instead.
*/
static inline void skb_header_release(struct sk_buff *skb)
{
@@ -1092,6 +1093,20 @@ static inline void skb_header_release(struct sk_buff *skb)
}
/**
+ * __skb_header_release - release reference to header
+ * @skb: buffer to operate on
+ *
+ * Variant of skb_header_release() assuming skb is private to caller.
+ * We can avoid one atomic operation.
+ */
+static inline void __skb_header_release(struct sk_buff *skb)
+{
+ skb->nohdr = 1;
+ atomic_set(&skb_shinfo(skb)->dataref, 1 + (1 << SKB_DATAREF_SHIFT));
+}
+
+
+/**
* skb_shared - is the buffer shared
* @skb: buffer to check
*
diff --git a/net/core/skbuff.c b/net/core/skbuff.c
index 06a8feb10099..512dc7dcbc32 100644
--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
@@ -3179,7 +3179,7 @@ int skb_gro_receive(struct sk_buff **head, struct sk_buff *skb)
skb_shinfo(nskb)->frag_list = p;
skb_shinfo(nskb)->gso_size = pinfo->gso_size;
pinfo->gso_size = 0;
- skb_header_release(p);
+ __skb_header_release(p);
NAPI_GRO_CB(nskb)->last = p;
nskb->data_len += p->len;
@@ -3211,7 +3211,7 @@ merge:
else
NAPI_GRO_CB(p)->last->next = skb;
NAPI_GRO_CB(p)->last = skb;
- skb_header_release(skb);
+ __skb_header_release(skb);
lp = p;
done:
diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
index 070aeff1b131..553b01f52f71 100644
--- a/net/ipv4/tcp.c
+++ b/net/ipv4/tcp.c
@@ -609,7 +609,7 @@ static inline bool forced_push(const struct tcp_sock *tp)
return after(tp->write_seq, tp->pushed_seq + (tp->max_window >> 1));
}
-static inline void skb_entail(struct sock *sk, struct sk_buff *skb)
+static void skb_entail(struct sock *sk, struct sk_buff *skb)
{
struct tcp_sock *tp = tcp_sk(sk);
struct tcp_skb_cb *tcb = TCP_SKB_CB(skb);
@@ -618,7 +618,7 @@ static inline void skb_entail(struct sock *sk, struct sk_buff *skb)
tcb->seq = tcb->end_seq = tp->write_seq;
tcb->tcp_flags = TCPHDR_ACK;
tcb->sacked = 0;
- skb_header_release(skb);
+ __skb_header_release(skb);
tcp_add_write_queue_tail(sk, skb);
sk->sk_wmem_queued += skb->truesize;
sk_mem_charge(sk, skb->truesize);
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 8c61a7c0c889..f173b1c4f815 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -995,7 +995,7 @@ static void tcp_queue_skb(struct sock *sk, struct sk_buff *skb)
/* Advance write_seq and place onto the write_queue. */
tp->write_seq = TCP_SKB_CB(skb)->end_seq;
- skb_header_release(skb);
+ __skb_header_release(skb);
tcp_add_write_queue_tail(sk, skb);
sk->sk_wmem_queued += skb->truesize;
sk_mem_charge(sk, skb->truesize);
@@ -1167,7 +1167,7 @@ int tcp_fragment(struct sock *sk, struct sk_buff *skb, u32 len,
}
/* Link BUFF into the send queue. */
- skb_header_release(buff);
+ __skb_header_release(buff);
tcp_insert_write_queue_after(skb, buff, sk);
return 0;
@@ -1671,7 +1671,7 @@ static int tso_fragment(struct sock *sk, struct sk_buff *skb, unsigned int len,
tcp_set_skb_tso_segs(sk, buff, mss_now);
/* Link BUFF into the send queue. */
- skb_header_release(buff);
+ __skb_header_release(buff);
tcp_insert_write_queue_after(skb, buff, sk);
return 0;
@@ -2772,7 +2772,7 @@ int tcp_send_synack(struct sock *sk)
if (nskb == NULL)
return -ENOMEM;
tcp_unlink_write_queue(skb, sk);
- skb_header_release(nskb);
+ __skb_header_release(nskb);
__tcp_add_write_queue_head(sk, nskb);
sk_wmem_free_skb(sk, skb);
sk->sk_wmem_queued += nskb->truesize;
@@ -2947,7 +2947,7 @@ static void tcp_connect_queue_skb(struct sock *sk, struct sk_buff *skb)
struct tcp_skb_cb *tcb = TCP_SKB_CB(skb);
tcb->end_seq += skb->len;
- skb_header_release(skb);
+ __skb_header_release(skb);
__tcp_add_write_queue_tail(sk, skb);
sk->sk_wmem_queued += skb->truesize;
sk_mem_charge(sk, skb->truesize);
^ permalink raw reply related
* [PATCH] Revert "net/macb: add pinctrl consumer support"
From: Soren Brinkmann @ 2014-09-22 23:49 UTC (permalink / raw)
To: Nicolas Ferre; +Cc: linux-kernel, netdev, Soren Brinkmann
This reverts commit 8ef29f8aae524bd51298fb10ac6a5ce6c4c5a3d8.
The driver core already calls pinctrl_get() and claims the default
state. There is no need to replicate this in the driver.
---
Hi,
I might be mistaken, but I think the driver core does already take care of
calling into the pinctrl framework and the driver does not need to do it on its
own (drivers/base/dd.c:really_probe() calls 'pinctrl_bind_pins() which takes
care of the pinctrl setup).
Thanks,
Sören
drivers/net/ethernet/cadence/macb.c | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index ca5d7798b265..e1e02fba4fcc 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -30,7 +30,6 @@
#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
-#include <linux/pinctrl/consumer.h>
#include "macb.h"
@@ -2071,7 +2070,6 @@ static int __init macb_probe(struct platform_device *pdev)
struct phy_device *phydev;
u32 config;
int err = -ENXIO;
- struct pinctrl *pinctrl;
const char *mac;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -2080,15 +2078,6 @@ static int __init macb_probe(struct platform_device *pdev)
goto err_out;
}
- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
- if (IS_ERR(pinctrl)) {
- err = PTR_ERR(pinctrl);
- if (err == -EPROBE_DEFER)
- goto err_out;
-
- dev_warn(&pdev->dev, "No pinctrl provided\n");
- }
-
err = -ENOMEM;
dev = alloc_etherdev(sizeof(*bp));
if (!dev)
--
2.1.0.1.g27b9230
^ permalink raw reply related
* [PATCH net-next 0/3] tcp: better TCP_SKB_CB layout
From: Eric Dumazet @ 2014-09-22 23:50 UTC (permalink / raw)
To: David S. Miller; +Cc: netdev, Yuchung Cheng, Neal Cardwell, Eric Dumazet
TCP had the assumption that IPCB and IP6CB are first members of skb->cb[]
This is fine, except that IPCB/IP6CB are used for a very short time
in input path.
What really matters for TCP stack is to get skb->next,
TCP_SKB_CB(skb)->seq, and TCP_SKB_CB(skb)->end_seq in the same cache line.
skb that are immediately consumed do not care because whole skb->cb[] is
hot in cpu cache, while skb that sit in wocket write queue or receive queues
do not need TCP_SKB_CB(skb)->header at all.
This patch set implements the prereq for IPv4, IPv6, and TCP to make this
possible. This makes TCP more efficient.
Eric Dumazet (3):
ipv4: rename ip_options_echo to __ip_options_echo()
ipv6: add a struct inet6_skb_parm param to ipv6_opt_accepted()
tcp: better TCP_SKB_CB layout to reduce cache line misses
include/net/ip.h | 15 ++++++++++++---
include/net/ipv6.h | 3 ++-
include/net/tcp.h | 12 ++++++------
net/dccp/ipv6.c | 2 +-
net/ipv4/ip_options.c | 6 ++----
net/ipv4/ip_output.c | 8 +++++---
net/ipv4/tcp_ipv4.c | 17 +++++++++++++----
net/ipv6/af_inet6.c | 4 ++--
net/ipv6/syncookies.c | 2 +-
net/ipv6/tcp_ipv6.c | 12 ++++++++++--
10 files changed, 54 insertions(+), 27 deletions(-)
--
2.1.0.rc2.206.gedb03e5
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox