* pull-request: wireless-drivers-next 2018-05-17
From: Kalle Valo @ 2018-05-17 8:44 UTC (permalink / raw)
To: David Miller; +Cc: linux-wireless, netdev, linux-kernel
Hi Dave,
here's a pull request to net-next for 4.18. I forgot to mention in the
signed tag was that one id is added to include/linux/mmc/sdio_ids.h but
that was acked by Ulf.
I suspect hat because of my merge of wireless-drivers into
wireless-drivers-next the diffstat from request-pull was wrong again. I
manually replaced that with the diffstat from my test pull to net-next.
Please let me know if you have any problems.
Kalle
The following changes since commit af8a41cccf8f469165c6debc8fe07c5fd2ca501a:
rtlwifi: cleanup 8723be ant_sel definition (2018-04-24 13:15:08 +0300)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next.git tags/wireless-drivers-next-for-davem-2018-05-17
for you to fetch changes up to 763ece85f45a6b93268e25a0abf02922f911dab4:
brcmfmac: fix initialization of struct cfg80211_inform_bss variable (2018-05-15 18:03:35 +0300)
----------------------------------------------------------------
wireless-drivers-next patches for 4.18
The first pull request for 4.18. As usual new features and bug fixes
but nothing really special.
I also merged wireless-drivers due to an iwlwifi patch dependency.
Major changes:
iwlwifi
* implement Traffic Condition Monitor and use it for scan, BT coex and
to detect when the AP doesn't support UAPSD properly
* some more work for the 22000 family of devices;
* introduce AMSDU rate control offload
qtnfmac
* DFS offload support
rsi
* roaming enhancements
* increase max supported aggregation subframes
* don't advertise 5 GHz support if the device doesn't support it
brcmfmac
* add support for BCM4366E chipset
* add support for bcm43364 wireless chipset
ath10k
* enable temperature reads for QCA6174 and QCA9377
* add firmware memory dump support for QCA9984
* continue adding WCN3990 support via SNOC bus
----------------------------------------------------------------
Amitkumar Karwar (7):
rsi: disable fw watchdog timer during reset
rsi: device bootup parameter configuration
rsi: use appropriate interface for power save configuration
rsi: increase max supported aggregation subframes
rsi: parse TID from data frame correctly
rsi: enable power save by default for coex
rsi: advertise 5GHz support based on device capability
Arend Van Spriel (2):
brcmfmac: check p2pdev mac address uniqueness
brcmfmac: constify firmware mapping tables
Arnd Bergmann (1):
ath10k: avoid possible string overflow
Carl Huang (2):
ath10k: add WMI_SERVICE_AVAILABLE_EVENT support
ath10k: support MAC address randomization in scan
Colin Ian King (9):
wil6210: fix potential null dereference of ndev before null check
ath10k: fix spelling mistake: "tiggers" -> "triggers"
ath6kl: fix spelling mistake: "chache" -> "cache"
cw1200: fix spelling mistake: "Mailformed" -> "Malformed"
rt2x00: fix spelling mistake in various macros, UKNOWN -> UNKNOWN
ipw2100: fix spelling mistake: "decsribed" -> "described"
rtlwifi: fix spelling mistake: "dismatch" -> "mismatch"
ipw2200: fix spelling mistake: "functionalitis" -> "functionalities"
rsi: fix spelling mistake: "thead" -> "thread"
Dan Carpenter (2):
rsi: remove unecessary PTR_ALIGN()s
mwifiex: pcie: tighten a check in mwifiex_pcie_process_event_ready()
Dan Haab (1):
brcmfmac: add support for BCM4366E chipset
Daniel Mack (11):
wcn36xx: check for DMA mapping errors in wcn36xx_dxe_tx_frame()
wcn36xx: don't keep reference to skb if transmission failed
wcn36xx: don't delete invalid bss indices
wcn36xx: allocate skbs with GFP_KERNEL during init
wcn36xx: use READ_ONCE() to access desc->ctrl
wcn36xx: pass correct BSS index when deleting BSS keys
wcn36xx: abort scan request when 'dequeued' indicator is sent
wcn36xx: cancel pending scan request when interface goes down
wcn36xx: handle scan cancellation when firmware support is missing
wcn36xx: send bss_type in scan requests
wcn36xx: pass information elements in scan requests
Dmitry Lebed (1):
qtnfmac: add DFS offload support
Eliad Peller (2):
iwlwifi: pcie: allow sending pre-built A-MSDUs
iwlwifi: mvm: set wakeup filters for wowlan "any" configuration
Emmanuel Grumbach (3):
iwlwifi: mvm: BT Coex - make the primary / secondary pick traffic aware
iwlwifi: pcie: implement the overlow queue for Gen2 devices
iwlwifi: mvm: set the MFP flag for keys that are used by MFP stations
Erik Stromdahl (2):
ath10k: add inlined wrappers for htt tx ops
ath10k: add inlined wrappers for htt rx ops
Eyal Reizer (1):
wlcore: sdio: allow pm to handle sdio power
Felix Fietkau (11):
mt76: stop tx queues from the driver callback instead of common code
mt76: add missing VHT maximum A-MPDU length capability
mt76: toggle driver station powersave bit before notifying mac80211
mt76: rework tx power handling
mt76: fix potential sleep in atomic context
mt76: set RX_FLAG_DUP_VALIDATED for A-MPDU reordered packets
mt76: check qos ack policy before reordering packets
mt76: fix concurrent rx calls on A-MPDU release
mt76: add rcu locking in tid reorder function
mt76: add rcu locking around tx scheduling
mt76: check for pending reset before attempting to schedule tx
Franky Lin (5):
brcmfmac: reports boottime_ns while informing bss
brcmfmac: use nl80211_band directly to get ieee80211 channel
brcmfmac: add hostready indication
brcmfmac: coarse support for PCIe shared structure rev7
brcmfmac: fix initialization of struct cfg80211_inform_bss variable
Ganapathi Bhat (1):
mwifiex: increase TX threashold to avoid TX timeout during ED MAC test
Golan Ben Ami (2):
iwlwifi: allow different csr flags for different device families
iwlwifi: support new csr addresses for hw address
Golan Ben-Ami (1):
iwlwifi: introduce Image Loader (IML) - new firmware image
Govind Singh (15):
ath10k: build ce layer in ath10k core module
ath10k: platform driver for WCN3990 SNOC WLAN module
ath10k: add resource init and deinit for WCN3990
ath10k: add hif start/stop methods for wcn3990 snoc layer
ath10k: add HTC services for WCN3990
ath10k: map HTC services to tx/rx pipes for wcn3990
ath10k: add hif power-up/power-down methods
ath10k: add hif tx methods for wcn3990
ath10k: add hif rx methods for wcn3990
ath10k: modify hif tx paddr to dma_addr_t type
ath10k: vote for hardware resources for WCN3990
dt: bindings: add bindings for wcn3990 wifi block
ath10k: fix fw path name for WCN3990 target
ath10k: enable SRRI/DRRI support on ddr for WCN3990
ath10k: enable sta idle power save
Gregory Greenman (1):
iwlwifi: mvm: support offload of AMSDU rate control
Gustavo A. R. Silva (6):
ath9k: dfs: remove accidental use of stack VLA
mt7601u: phy: mark expected switch fall-through
brcmsmac: phy_lcn: remove duplicate code
qtnfmac: pearl: pcie: fix memory leak in qtnf_fw_work_handler
rsi_91x: fix structurally dead code
rsi_91x: fix uninitialized variable
Haim Dreyfuss (1):
iwlwifi: move timestamp functions from debugfs.h to dbg.h
Jia-Ju Bai (1):
net: wireless: b43legacy: Replace GFP_ATOMIC with GFP_KERNEL in dma_tx_fragment
Johannes Berg (3):
iwlwifi: mvm: detect U-APSD breaking aggregation
iwlwifi: mvm: clean up scan capability checks
iwlwifi: mvm: move skb padding reservation earlier
Julia Lawall (1):
mwifiex: delete unneeded include
Kalle Valo (4):
Merge tag 'iwlwifi-next-for-kalle-2018-04-20' of git://git.kernel.org/.../iwlwifi/iwlwifi-next
Merge ath-next from git://git.kernel.org/.../kvalo/ath.git
Merge git://git.kernel.org/.../kvalo/wireless-drivers.git
Merge tag 'iwlwifi-next-for-kalle-2018-04-26' of git://git.kernel.org/.../iwlwifi/iwlwifi-next
Liad Kaufman (2):
iwlwifi: support api ver2 of NVM_GET_INFO resp
iwlwifi: mvm: support 22000 HW opening agg before traffic
Loic Poulain (2):
wcn36xx: Add missing fall through comment in smd.c
wcn36xx: Remove useless skb spinlock
Lorenzo Bianconi (10):
mt76x2: fix tssi initialization for 5GHz band
mt76x2: make mt76x2_mac_reset routine static
mt76x2: remove unnecessary MT_TX_ALC_CFG_4 configuration
mt76x2: fix tx_alc_enabled check
mt76x2: set default values in TX_ALC_CFG_{1, 2} for tempetaure compensation
mt76x2: fix TXD_INFO bitmask definition
mt76x2: fix is_mt7612 routine
mt76x2: remove unnecessary break in mt76x2_mac_process_tx_rate()
mt76x2: fix avg_rssi estimation
mt76x2: add a polling delay in mt76x2_mac_stop routine
Luc Van Oostenryck (2):
mwifiex: fix mwifiex_hard_start_xmit()'s return type
qtnfmac: fix qtnf_netdev_hard_start_xmit()'s return type
Luca Coelho (10):
iwlwifi: mvm: add traffic condition monitoring (TCM)
iwlwifi: mvm: use TCM data to decide scan priority
iwlwifi: mvm: fix OOC priority in scans
iwlwifi: use flags to denote modifiers for the channel maps
iwlwifi: remove upper case letters in sku_capa_band_*_enable
iwlwifi: cfg: remove unnecessary cfg data in non-dvm devices
iwlwifi: fw: harden page loading code
iwlwifi: fw: combine loading of last page block into main copy loop
iwlwifi: pcie: remove non-responsive device
iwlwifi: make bitfield a u32 instead of u16
Maharaja Kennadyrajan (1):
ath10k: fix a typo in ath10k_wmi_set_wmm_param()
Manikanta Pubbisetty (1):
ath10k: correct target assert problem due to CE5 stuck
Marcus Folkesson (1):
ath10k: sdio: fix memory leak for probe allocations
Naftali Goldstein (1):
iwlwifi: mvm: update rs-fw API
Ping-Ke Shih (2):
rtlwifi: btcoex: remove identical statements within if-else branches
rtlwifi: remove duplicate definition of antenna number for btcoex
Prameela Rani Garnepudi (4):
rsi: move xtend_desc structure from rsi_main.h to rsi_mgmt.h
rsi: move descriptor preparation to core
rsi: enable 80MHz clock by default
rsi: roaming enhancements
Rafał Miłecki (1):
brcmfmac: set WIPHY_FLAG_HAVE_AP_SME flag
Rakesh Pillai (5):
ath10k: add support to get target info from hif ops
ath10k: check all CE for data if irq summary is not retained
ath10k: enable hw checksum for wcn3990
ath10k: add hw params for shadow register support
ath10k: add support for shadow register for WNC3990
Sanjay Kumar Konduri (1):
rsi: Add null check for virtual interfaces in wowlan config
Sara Sharon (8):
iwlwifi: mvm: detect low latency and traffic load per band
iwlwifi: pcie: allocate shorter TX queues for 22000 devices
iwlwifi: Revert "iwlwifi: pcie: dynamic Tx command queue size"
iwlwifi: add TX queue size parameter to TX queue allocation
iwlwifi: pcie: use the queue size as sent by opmode
iwlwifi: mvm: use shorter queues for mgmt and auxilary queues
iwlwifi: mvm: use the new get_tid function
iwlwifi: mvm: remove check for non low latency TIDs
Sean Lanigan (1):
brcmfmac: Add support for bcm43364 wireless chipset
Shaul Triebitz (3):
iwlwifi: move all NVM parsing code to the common files
iwlwifi: pcie: gen2: fix race in cmd fifo write ptr
iwlwifi: get rid of fw/nvm.c
Siva Rebbagondla (4):
rsi: fix nommu_map_sg overflow kernel panic
rsi: Fix 'invalid vdd' warning in mmc
rsi: reset hibernate_resume flag to work hibernate resume in coex mode.
rsi: Set wowlan flag while writing wowlan config parameters
Stanislaw Gruszka (4):
mt7601u: use EWMA to calculate avg_rssi
mt7601u: run calibration works after finishing scanning
rt2x00: call sta_add/remove directly in rt2800
rt2x00: check against flushing empty queue
Taketo Kabe (1):
b43: fix transmit failure when VT is switched
Thomas Hebb (1):
ath10k: search all IEs for variant before falling back
Toke Høiland-Jørgensen (1):
wireless-drivers: Dynamically allocate struct station_info
Venkateswara Naralasetty (1):
ath10k: Add tx ack signal support for management frames
Wen Gong (1):
ath10k: convert wow pattern from 802.3 to 802.11
Xinming Hu (5):
mwifiex: uap: filter duplicate ERP IE
mwifiex: uap: support cfg80211 ignore_broadcast_ssid=2
mwifiex: make firmware mac address consistent with host configuration
mwifiex: always configure firmware mac address during changing virtual interface
mwifiex: keep user configured mac address during changing virtual interface
Xose Vazquez Perez (1):
rt2x00: rt2800: add antenna diversity for RT5370G
drivers/net/wireless/ath/ath10k/Kconfig | 12 ++
drivers/net/wireless/ath/ath10k/Makefile | 7 +-
drivers/net/wireless/ath/ath10k/ce.c | 269 ++++++++++++++++++++++++++-
drivers/net/wireless/ath/ath10k/ce.h | 24 ++-
drivers/net/wireless/ath/ath10k/core.c | 183 +++++++++++-------
drivers/net/wireless/ath/ath10k/core.h | 2 +
drivers/net/wireless/ath/ath10k/hif.h | 15 +-
drivers/net/wireless/ath/ath10k/htc.c | 6 +
drivers/net/wireless/ath/ath10k/htc.h | 4 +
drivers/net/wireless/ath/ath10k/htt.c | 4 +-
drivers/net/wireless/ath/ath10k/htt.h | 111 ++++++++++-
drivers/net/wireless/ath/ath10k/htt_rx.c | 24 ++-
drivers/net/wireless/ath/ath10k/htt_tx.c | 19 +-
drivers/net/wireless/ath/ath10k/hw.c | 9 +-
drivers/net/wireless/ath/ath10k/hw.h | 22 ++-
drivers/net/wireless/ath/ath10k/mac.c | 26 ++-
drivers/net/wireless/ath/ath10k/pci.c | 8 +-
drivers/net/wireless/ath/ath10k/sdio.c | 24 +--
drivers/net/wireless/ath/ath10k/snoc.c | 1414 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/wireless/ath/ath10k/snoc.h | 95 ++++++++++
drivers/net/wireless/ath/ath10k/txrx.c | 8 +
drivers/net/wireless/ath/ath10k/wmi-ops.h | 46 +++++
drivers/net/wireless/ath/ath10k/wmi-tlv.c | 63 +++++++
drivers/net/wireless/ath/ath10k/wmi-tlv.h | 357 ++++++++++++++++++++++++++++++++++-
drivers/net/wireless/ath/ath10k/wmi.c | 34 +++-
drivers/net/wireless/ath/ath10k/wmi.h | 28 +++
drivers/net/wireless/ath/ath10k/wow.c | 138 +++++++++++++-
drivers/net/wireless/ath/ath6kl/debug.c | 2 +-
drivers/net/wireless/ath/ath6kl/main.c | 14 +-
drivers/net/wireless/ath/ath9k/dfs.c | 6 +-
drivers/net/wireless/ath/wcn36xx/dxe.c | 36 ++--
drivers/net/wireless/ath/wcn36xx/dxe.h | 1 -
drivers/net/wireless/ath/wcn36xx/hal.h | 8 +-
drivers/net/wireless/ath/wcn36xx/main.c | 40 +++-
drivers/net/wireless/ath/wcn36xx/smd.c | 33 +++-
drivers/net/wireless/ath/wcn36xx/smd.h | 2 +
drivers/net/wireless/ath/wcn36xx/txrx.c | 15 +-
drivers/net/wireless/ath/wcn36xx/wcn36xx.h | 7 +-
drivers/net/wireless/ath/wil6210/debugfs.c | 22 ++-
drivers/net/wireless/ath/wil6210/main.c | 3 +-
drivers/net/wireless/ath/wil6210/wmi.c | 19 +-
drivers/net/wireless/broadcom/b43/dma.c | 14 +-
drivers/net/wireless/broadcom/b43legacy/dma.c | 2 +-
drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c | 1 +
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c | 51 ++---
drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c | 1 +
drivers/net/wireless/broadcom/brcm80211/brcmfmac/firmware.c | 2 +-
drivers/net/wireless/broadcom/brcm80211/brcmfmac/firmware.h | 2 +-
drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.h | 6 +-
drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c | 7 +
drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c | 40 +++-
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 2 +-
drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c | 2 +-
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c | 9 +-
drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h | 1 +
drivers/net/wireless/intel/ipw2x00/ipw2100.c | 2 +-
drivers/net/wireless/intel/ipw2x00/ipw2100.h | 2 +-
drivers/net/wireless/intel/ipw2x00/ipw2200.c | 2 +-
drivers/net/wireless/intel/iwlwifi/Makefile | 2 +-
drivers/net/wireless/intel/iwlwifi/cfg/1000.c | 8 +-
drivers/net/wireless/intel/iwlwifi/cfg/2000.c | 13 +-
drivers/net/wireless/intel/iwlwifi/cfg/22000.c | 11 +-
drivers/net/wireless/intel/iwlwifi/cfg/5000.c | 8 +-
drivers/net/wireless/intel/iwlwifi/cfg/6000.c | 19 +-
drivers/net/wireless/intel/iwlwifi/cfg/7000.c | 12 +-
drivers/net/wireless/intel/iwlwifi/cfg/8000.c | 10 +-
drivers/net/wireless/intel/iwlwifi/cfg/9000.c | 6 +-
drivers/net/wireless/intel/iwlwifi/dvm/main.c | 8 +-
drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h | 5 -
drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h | 42 +++--
drivers/net/wireless/intel/iwlwifi/fw/api/rs.h | 156 ++++++----------
drivers/net/wireless/intel/iwlwifi/fw/api/txq.h | 2 +
drivers/net/wireless/intel/iwlwifi/fw/dbg.h | 36 ++++
drivers/net/wireless/intel/iwlwifi/fw/debugfs.c | 1 +
drivers/net/wireless/intel/iwlwifi/fw/debugfs.h | 31 ----
drivers/net/wireless/intel/iwlwifi/fw/file.h | 3 +
drivers/net/wireless/intel/iwlwifi/fw/img.h | 6 +
drivers/net/wireless/intel/iwlwifi/fw/nvm.c | 162 ----------------
drivers/net/wireless/intel/iwlwifi/fw/paging.c | 78 ++++----
drivers/net/wireless/intel/iwlwifi/fw/runtime.h | 1 -
drivers/net/wireless/intel/iwlwifi/iwl-config.h | 92 ++++++++-
drivers/net/wireless/intel/iwlwifi/iwl-csr.h | 28 +--
drivers/net/wireless/intel/iwlwifi/iwl-drv.c | 14 ++
drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.c | 4 +-
drivers/net/wireless/intel/iwlwifi/iwl-eeprom-parse.h | 5 +-
drivers/net/wireless/intel/iwlwifi/iwl-eeprom-read.c | 8 +-
drivers/net/wireless/intel/iwlwifi/iwl-modparams.h | 2 +
drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c | 353 ++++++++++++++++++++++++++++++++---
drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.h | 56 ++++--
drivers/net/wireless/intel/iwlwifi/iwl-trans.h | 13 +-
drivers/net/wireless/intel/iwlwifi/mvm/coex.c | 37 ++++
drivers/net/wireless/intel/iwlwifi/mvm/constants.h | 7 +
drivers/net/wireless/intel/iwlwifi/mvm/d3.c | 22 ++-
drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c | 2 +
drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c | 25 +++
drivers/net/wireless/intel/iwlwifi/mvm/fw.c | 10 +-
drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c | 33 ++++
drivers/net/wireless/intel/iwlwifi/mvm/mvm.h | 101 ++++++++--
drivers/net/wireless/intel/iwlwifi/mvm/nvm.c | 208 +--------------------
drivers/net/wireless/intel/iwlwifi/mvm/ops.c | 18 +-
drivers/net/wireless/intel/iwlwifi/mvm/rs-fw.c | 117 ++++++------
drivers/net/wireless/intel/iwlwifi/mvm/rs.c | 15 +-
drivers/net/wireless/intel/iwlwifi/mvm/rs.h | 3 +-
drivers/net/wireless/intel/iwlwifi/mvm/rx.c | 103 +++++++++-
drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c | 33 ++--
drivers/net/wireless/intel/iwlwifi/mvm/scan.c | 194 +++++++++++++------
drivers/net/wireless/intel/iwlwifi/mvm/sta.c | 28 ++-
drivers/net/wireless/intel/iwlwifi/mvm/sta.h | 7 +-
drivers/net/wireless/intel/iwlwifi/mvm/tx.c | 56 +++++-
drivers/net/wireless/intel/iwlwifi/mvm/utils.c | 438 +++++++++++++++++++++++++++++++++++++++++--
drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c | 2 +-
drivers/net/wireless/intel/iwlwifi/pcie/internal.h | 8 +-
drivers/net/wireless/intel/iwlwifi/pcie/rx.c | 3 +-
drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c | 15 +-
drivers/net/wireless/intel/iwlwifi/pcie/trans.c | 139 ++++++++++----
drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c | 55 ++++--
drivers/net/wireless/intel/iwlwifi/pcie/tx.c | 52 +++---
drivers/net/wireless/marvell/mwifiex/cfg80211.c | 7 +-
drivers/net/wireless/marvell/mwifiex/cmdevt.c | 1 -
drivers/net/wireless/marvell/mwifiex/ie.c | 1 +
drivers/net/wireless/marvell/mwifiex/main.c | 43 +++--
drivers/net/wireless/marvell/mwifiex/main.h | 7 +-
drivers/net/wireless/marvell/mwifiex/pcie.c | 3 +-
drivers/net/wireless/marvell/mwifiex/uap_event.c | 25 ++-
drivers/net/wireless/mediatek/mt76/agg-rx.c | 16 +-
drivers/net/wireless/mediatek/mt76/mac80211.c | 13 +-
drivers/net/wireless/mediatek/mt76/mt76.h | 1 +
drivers/net/wireless/mediatek/mt76/mt76x2.h | 3 +-
drivers/net/wireless/mediatek/mt76/mt76x2_dma.h | 7 +-
drivers/net/wireless/mediatek/mt76/mt76x2_eeprom.c | 6 +-
drivers/net/wireless/mediatek/mt76/mt76x2_eeprom.h | 6 +
drivers/net/wireless/mediatek/mt76/mt76x2_init.c | 13 +-
drivers/net/wireless/mediatek/mt76/mt76x2_mac.c | 1 -
drivers/net/wireless/mediatek/mt76/mt76x2_mac.h | 1 -
drivers/net/wireless/mediatek/mt76/mt76x2_main.c | 1 +
drivers/net/wireless/mediatek/mt76/mt76x2_phy.c | 84 ++++++---
drivers/net/wireless/mediatek/mt76/tx.c | 6 +
drivers/net/wireless/mediatek/mt7601u/mac.c | 4 +-
drivers/net/wireless/mediatek/mt7601u/main.c | 6 +
drivers/net/wireless/mediatek/mt7601u/mt7601u.h | 5 +-
drivers/net/wireless/mediatek/mt7601u/phy.c | 11 +-
drivers/net/wireless/quantenna/qtnfmac/cfg80211.c | 9 +
drivers/net/wireless/quantenna/qtnfmac/core.c | 2 +-
drivers/net/wireless/quantenna/qtnfmac/event.c | 52 ++++--
drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c | 4 +
drivers/net/wireless/quantenna/qtnfmac/qlink.h | 7 +-
drivers/net/wireless/ralink/rt2x00/rt2800.h | 17 +-
drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 20 +-
drivers/net/wireless/ralink/rt2x00/rt2800lib.h | 5 +-
drivers/net/wireless/ralink/rt2x00/rt2800mmio.c | 1 +
drivers/net/wireless/ralink/rt2x00/rt2800pci.c | 6 +-
drivers/net/wireless/ralink/rt2x00/rt2800soc.c | 6 +-
drivers/net/wireless/ralink/rt2x00/rt2800usb.c | 6 +-
drivers/net/wireless/ralink/rt2x00/rt2x00.h | 4 -
drivers/net/wireless/ralink/rt2x00/rt2x00mac.c | 3 +-
drivers/net/wireless/ralink/rt2x00/rt2x00queue.c | 2 +
drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c | 2 +-
drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.c | 2 +-
drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.c | 19 +-
drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.c | 2 +-
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c | 4 +-
drivers/net/wireless/realtek/rtlwifi/wifi.h | 5 -
drivers/net/wireless/rsi/rsi_91x_coex.c | 1 +
drivers/net/wireless/rsi/rsi_91x_core.c | 33 +++-
drivers/net/wireless/rsi/rsi_91x_hal.c | 108 +++++++----
drivers/net/wireless/rsi/rsi_91x_mac80211.c | 72 ++++---
drivers/net/wireless/rsi/rsi_91x_mgmt.c | 34 ++--
drivers/net/wireless/rsi/rsi_91x_sdio.c | 27 +--
drivers/net/wireless/rsi/rsi_91x_usb.c | 8 +
drivers/net/wireless/rsi/rsi_boot_params.h | 3 +-
drivers/net/wireless/rsi/rsi_hal.h | 3 +
drivers/net/wireless/rsi/rsi_main.h | 7 +-
drivers/net/wireless/rsi/rsi_mgmt.h | 19 +-
drivers/net/wireless/rsi/rsi_sdio.h | 2 +-
drivers/net/wireless/rsi/rsi_usb.h | 1 +
drivers/net/wireless/st/cw1200/txrx.c | 2 +-
drivers/net/wireless/ti/wlcore/sdio.c | 27 +--
include/linux/mmc/sdio_ids.h | 1 +
179 files changed, 5580 insertions(+), 1480 deletions(-)
create mode 100644 drivers/net/wireless/ath/ath10k/snoc.c
create mode 100644 drivers/net/wireless/ath/ath10k/snoc.h
delete mode 100644 drivers/net/wireless/intel/iwlwifi/fw/nvm.c
--
Kalle Valo
^ permalink raw reply
* [PATCH net-next 3/3] net: mvpp2: print rx error with rate-limit
From: Antoine Tenart @ 2018-05-17 8:34 UTC (permalink / raw)
To: davem
Cc: Yan Markman, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, gregory.clement, miquel.raynal, nadavh,
stefanc, mw, Antoine Tenart
In-Reply-To: <20180517083427.15793-1-antoine.tenart@bootlin.com>
From: Yan Markman <ymarkman@marvell.com>
Prevent flood of RX error prints during heavy traffic with weak signal
in link by checking net_ratelimit() before using netdev_err().
Signed-off-by: Yan Markman <ymarkman@marvell.com>
[Antoine: small rework, commit message]
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index a9483da18e00..f8ed983bc767 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -6382,21 +6382,23 @@ static void mvpp2_rx_error(struct mvpp2_port *port,
{
u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
+ char *err_str = NULL;
switch (status & MVPP2_RXD_ERR_CODE_MASK) {
case MVPP2_RXD_ERR_CRC:
- netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
- status, sz);
+ err_str = "crc";
break;
case MVPP2_RXD_ERR_OVERRUN:
- netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
- status, sz);
+ err_str = "overrun";
break;
case MVPP2_RXD_ERR_RESOURCE:
- netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
- status, sz);
+ err_str = "resource";
break;
}
+ if (err_str && net_ratelimit())
+ netdev_err(port->dev,
+ "bad rx status %08x (%s error), size=%zu\n",
+ status, err_str, sz);
}
/* Handle RX checksum offload */
--
2.17.0
^ permalink raw reply related
* [PATCH net-next 2/3] net: mvpp2: set mac address does not require the stop/start sequence
From: Antoine Tenart @ 2018-05-17 8:34 UTC (permalink / raw)
To: davem
Cc: Yan Markman, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, gregory.clement, miquel.raynal, nadavh,
stefanc, mw, Antoine Tenart
In-Reply-To: <20180517083427.15793-1-antoine.tenart@bootlin.com>
From: Yan Markman <ymarkman@marvell.com>
Remove special stop/start handling from the set_mac_address callback.
All this special care is not needed, and can be removed. It also
simplifies the up/down status in the driver and helps avoiding possible
link status mismatch issues.
Signed-off-by: Yan Markman <ymarkman@marvell.com>
[Antoine: commit message]
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 38 +++++-----------------------
1 file changed, 7 insertions(+), 31 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 73b2f2d331c5..a9483da18e00 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -7358,42 +7358,18 @@ static void mvpp2_set_rx_mode(struct net_device *dev)
static int mvpp2_set_mac_address(struct net_device *dev, void *p)
{
- struct mvpp2_port *port = netdev_priv(dev);
const struct sockaddr *addr = p;
int err;
- if (!is_valid_ether_addr(addr->sa_data)) {
- err = -EADDRNOTAVAIL;
- goto log_error;
- }
-
- if (!netif_running(dev)) {
- err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
- if (!err)
- return 0;
- /* Reconfigure parser to accept the original MAC address */
- err = mvpp2_prs_update_mac_da(dev, dev->dev_addr);
- if (err)
- goto log_error;
- }
-
- mvpp2_stop_dev(port);
+ if (!is_valid_ether_addr(addr->sa_data))
+ return -EADDRNOTAVAIL;
err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
- if (!err)
- goto out_start;
-
- /* Reconfigure parser accept the original MAC address */
- err = mvpp2_prs_update_mac_da(dev, dev->dev_addr);
- if (err)
- goto log_error;
-out_start:
- mvpp2_start_dev(port);
- mvpp2_egress_enable(port);
- mvpp2_ingress_enable(port);
- return 0;
-log_error:
- netdev_err(dev, "failed to change MAC address\n");
+ if (err) {
+ /* Reconfigure parser accept the original MAC address */
+ mvpp2_prs_update_mac_da(dev, dev->dev_addr);
+ netdev_err(dev, "failed to change MAC address\n");
+ }
return err;
}
--
2.17.0
^ permalink raw reply related
* [PATCH net-next 1/3] net: mvpp2: avoid checking for free aggregated descriptors twice
From: Antoine Tenart @ 2018-05-17 8:34 UTC (permalink / raw)
To: davem
Cc: Yan Markman, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, gregory.clement, miquel.raynal, nadavh,
stefanc, mw, Antoine Tenart
In-Reply-To: <20180517083427.15793-1-antoine.tenart@bootlin.com>
From: Yan Markman <ymarkman@marvell.com>
Avoid repeating the check for free aggregated descriptors when it
already failed at the beginning of the function.
Signed-off-by: Yan Markman <ymarkman@marvell.com>
[Antoine: commit message]
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index df59f0e0d33c..73b2f2d331c5 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -5488,11 +5488,10 @@ static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv,
MVPP2_AGGR_TXQ_STATUS_REG(cpu));
aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
- }
-
- if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
- return -ENOMEM;
+ if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
+ return -ENOMEM;
+ }
return 0;
}
--
2.17.0
^ permalink raw reply related
* [PATCH net-next 0/3] net: mvpp2: small improvements
From: Antoine Tenart @ 2018-05-17 8:34 UTC (permalink / raw)
To: davem
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, gregory.clement, miquel.raynal, nadavh,
stefanc, ymarkman, mw
Hi all,
Those 3 patches are small improvements to the Marvell PPv2 driver. The
series does not conflict with the one sent about phylink and
1000/2500baseX support, so the two series can live in parallel.
Thanks!
Antoine
Yan Markman (3):
net: mvpp2: avoid checking for free aggregated descriptors twice
net: mvpp2: set mac address does not require the stop/start sequence
net: mvpp2: print rx error with rate-limit
drivers/net/ethernet/marvell/mvpp2.c | 59 +++++++++-------------------
1 file changed, 18 insertions(+), 41 deletions(-)
--
2.17.0
^ permalink raw reply
* [PATCH net-next v3 10/10] arm64: dts: marvell: 7040-db: describe the 10G interface as fixed-link
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, miquel.raynal, nadavh, stefanc, ymarkman, mw,
linux-arm-kernel
In-Reply-To: <20180517082939.14598-1-antoine.tenart@bootlin.com>
This patch adds a fixed-link node to the 10G interface of the 7040-db
board. This is required as the mvpp2 driver now uses phylink. The best
solution would have been to describe the SFP cage but they are not
wired correctly, and thus unusable, so we chose to use fixed-link
instead.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index d6bec058a30a..412efdb46e7c 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -242,6 +242,11 @@
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cp0_comphy2 0>;
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
};
&cp0_eth1 {
--
2.17.0
^ permalink raw reply related
* [PATCH net-next v3 09/10] arm64: dts: marvell: 8040-db: describe the 10G interfaces as fixed-link
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, miquel.raynal, nadavh, stefanc, ymarkman, mw,
linux-arm-kernel
In-Reply-To: <20180517082939.14598-1-antoine.tenart@bootlin.com>
This patch adds a fixed-link node to both 10G interfaces of the 8040-db
board. This is required as the mvpp2 driver now uses phylink. The best
solution would have been to describe the SFP cages but they are not
wired correctly, and thus unusable, so we chose to use fixed-link
instead.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 5689fb23bbab..1bac437369a1 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -177,6 +177,11 @@
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
};
&cp0_eth2 {
@@ -303,6 +308,11 @@
&cp1_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
};
&cp1_eth1 {
--
2.17.0
^ permalink raw reply related
* [PATCH net-next v3 08/10] arm64: dts: marvell: mcbin: enable the fourth network interface
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, miquel.raynal, nadavh, stefanc, ymarkman, mw,
linux-arm-kernel
In-Reply-To: <20180517082939.14598-1-antoine.tenart@bootlin.com>
This patch enables the fourth network interface on the Marvell
Macchiatobin. It is configured in the 2500Base-X PHY mode. The SFP cage
is also described.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
.../boot/dts/marvell/armada-8040-mcbin.dts | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index eaa67de8c2bb..a66958ff4de6 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -27,6 +27,7 @@
ethernet0 = &cp0_eth0;
ethernet1 = &cp1_eth0;
ethernet2 = &cp1_eth1;
+ ethernet3 = &cp1_eth2;
};
/* Regulator labels correspond with schematics */
@@ -88,6 +89,18 @@
pinctrl-names = "default";
pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
};
+
+ sfp_eth3: sfp-eth3 {
+ /* CON3,4 - CPS lane 5 */
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_1g_i2c>;
+ los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
+ };
};
&uart0 {
@@ -195,6 +208,10 @@
marvell,pins = "mpp47";
marvell,function = "gpio";
};
+ cp0_sfp_1g_pins: sfp-1g-pins {
+ marvell,pins = "mpp51", "mpp53", "mpp54";
+ marvell,function = "gpio";
+ };
cp0_pcie_pins: pcie-pins {
marvell,pins = "mpp52";
marvell,function = "gpio";
@@ -287,6 +304,17 @@
phys = <&cp1_comphy0 1>;
};
+&cp1_eth2 {
+ /* CPS Lane 5 */
+ status = "okay";
+ /* Network PHY */
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy5 2>;
+ sfp = <&sfp_eth3>;
+};
+
&cp1_pinctrl {
cp1_sfpp1_pins: sfpp1-pins {
marvell,pins = "mpp8", "mpp10", "mpp11";
@@ -300,6 +328,10 @@
marvell,pins = "mpp6", "mpp7";
marvell,function = "uart0";
};
+ cp1_sfp_1g_pins: sfp-1g-pins {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
cp1_sfpp0_pins: sfpp0-pins {
marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
marvell,function = "gpio";
--
2.17.0
^ permalink raw reply related
* [PATCH net-next v3 07/10] arm64: dts: marvell: mcbin: add 10G SFP support
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: Russell King, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, miquel.raynal, nadavh, stefanc, ymarkman, mw,
linux-arm-kernel, Antoine Tenart
In-Reply-To: <20180517082939.14598-1-antoine.tenart@bootlin.com>
From: Russell King <rmk+kernel@armlinux.org.uk>
This patch adds the SFP cage description in the Marvell Armada 8040
mcbin, for both 10G interfaces.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
[Antoine: small reworks, commit message]
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
.../boot/dts/marvell/armada-8040-mcbin.dts | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index 81de03ef860d..eaa67de8c2bb 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -64,6 +64,30 @@
compatible = "usb-nop-xceiv";
vcc-supply = <&v_5v0_usb3_hst_vbus>;
};
+
+ sfp_eth0: sfp-eth0 {
+ /* CON15,16 - CPM lane 4 */
+ compatible = "sff,sfp";
+ i2c-bus = <&sfpp0_i2c>;
+ los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_sfpp0_pins>;
+ };
+
+ sfp_eth1: sfp-eth1 {
+ /* CON17,18 - CPS lane 4 */
+ compatible = "sff,sfp";
+ i2c-bus = <&sfpp1_i2c>;
+ los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
+ };
};
&uart0 {
@@ -180,6 +204,10 @@
"mpp60", "mpp61";
marvell,function = "sdio";
};
+ cp0_sfpp1_pins: sfpp1-pins {
+ marvell,pins = "mpp62";
+ marvell,function = "gpio";
+ };
};
&cp0_xmdio {
@@ -188,11 +216,13 @@
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
+ sfp = <&sfp_eth0>;
};
phy8: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
+ sfp = <&sfp_eth1>;
};
};
@@ -258,6 +288,10 @@
};
&cp1_pinctrl {
+ cp1_sfpp1_pins: sfpp1-pins {
+ marvell,pins = "mpp8", "mpp10", "mpp11";
+ marvell,function = "gpio";
+ };
cp1_spi1_pins: spi1-pins {
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
@@ -266,6 +300,10 @@
marvell,pins = "mpp6", "mpp7";
marvell,function = "uart0";
};
+ cp1_sfpp0_pins: sfpp0-pins {
+ marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
+ marvell,function = "gpio";
+ };
};
/* J27 UART header */
--
2.17.0
^ permalink raw reply related
* [PATCH net-next v3 06/10] net: mvpp2: 2500baseX support
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, miquel.raynal, nadavh, stefanc, ymarkman, mw,
linux-arm-kernel
In-Reply-To: <20180517082939.14598-1-antoine.tenart@bootlin.com>
This patch adds the 2500Base-X PHY mode support in the Marvell PPv2
driver. 2500Base-X is quite close to 1000Base-X and SGMII modes and uses
nearly the same code path.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 51 +++++++++++++++++++++-------
1 file changed, 39 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index ece61f1727e4..5e580482769e 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -4871,6 +4871,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
mvpp22_gop_init_sgmii(port);
break;
case PHY_INTERFACE_MODE_10GKR:
@@ -4909,7 +4910,8 @@ static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
/* Enable the GMAC link status irq for this port */
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
@@ -4940,7 +4942,8 @@ static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
@@ -4953,7 +4956,8 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_MASK);
val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_MASK);
@@ -4968,6 +4972,16 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
mvpp22_gop_unmask_irq(port);
}
+/* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
+ *
+ * The PHY mode used by the PPv2 driver comes from the network subsystem, while
+ * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
+ * differ.
+ *
+ * The COMPHY configures the serdes lanes regardless of the actual use of the
+ * lanes by the physical layer. This is why configurations like
+ * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
+ */
static int mvpp22_comphy_init(struct mvpp2_port *port)
{
enum phy_mode mode;
@@ -4981,6 +4995,9 @@ static int mvpp22_comphy_init(struct mvpp2_port *port)
case PHY_INTERFACE_MODE_1000BASEX:
mode = PHY_MODE_SGMII;
break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ mode = PHY_MODE_2500SGMII;
+ break;
case PHY_INTERFACE_MODE_10GKR:
mode = PHY_MODE_10GKR;
break;
@@ -5062,7 +5079,8 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port,
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
val |= MVPP2_GMAC_PCS_LB_EN_MASK;
else
val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -6273,7 +6291,8 @@ static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
}
} else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_STAT);
if (val & MVPP22_GMAC_INT_STAT_LINK) {
event = true;
@@ -8056,8 +8075,10 @@ static void mvpp2_phylink_validate(struct net_device *dev,
phylink_set(mask, 10000baseT_Full);
/* Fall-through */
case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
phylink_set(mask, 1000baseT_Full);
phylink_set(mask, 1000baseX_Full);
+ phylink_set(mask, 2500baseX_Full);
}
bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
@@ -8100,6 +8121,9 @@ static void mvpp2_gmac_link_state(struct mvpp2_port *port,
case PHY_INTERFACE_MODE_1000BASEX:
state->speed = SPEED_1000;
break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ state->speed = SPEED_2500;
+ break;
default:
if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
state->speed = SPEED_1000;
@@ -8199,11 +8223,12 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
- if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
- /* 1000BaseX port cannot negotiate speed nor can it negotiate
- * duplex: they are always operating with a fixed speed of
- * 1000Mbps in full duplex, so force 1000 speed and full duplex
- * here.
+ if (state->interface == PHY_INTERFACE_MODE_1000BASEX ||
+ state->interface == PHY_INTERFACE_MODE_2500BASEX) {
+ /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
+ * they negotiate duplex: they are always operating with a fixed
+ * speed of 1000/2500Mbps in full duplex, so force 1000/2500
+ * speed and full duplex here.
*/
ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
an |= MVPP2_GMAC_CONFIG_GMII_SPEED |
@@ -8220,7 +8245,8 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
an |= MVPP2_GMAC_FC_ADV_ASM_EN;
if (state->interface == PHY_INTERFACE_MODE_SGMII ||
- state->interface == PHY_INTERFACE_MODE_1000BASEX) {
+ state->interface == PHY_INTERFACE_MODE_1000BASEX ||
+ state->interface == PHY_INTERFACE_MODE_2500BASEX) {
an |= MVPP2_GMAC_IN_BAND_AUTONEG;
ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
@@ -8286,7 +8312,8 @@ static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
mvpp2_xlg_config(port, mode, state);
else if (phy_interface_mode_is_rgmii(state->interface) ||
state->interface == PHY_INTERFACE_MODE_SGMII ||
- state->interface == PHY_INTERFACE_MODE_1000BASEX)
+ state->interface == PHY_INTERFACE_MODE_1000BASEX ||
+ state->interface == PHY_INTERFACE_MODE_2500BASEX)
mvpp2_gmac_config(port, mode, state);
if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
--
2.17.0
^ permalink raw reply related
* [PATCH net-next v3 05/10] net: mvpp2: 1000baseX support
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: ymarkman, Antoine Tenart, netdev, linux-kernel, maxime.chevallier,
nadavh, thomas.petazzoni, miquel.raynal, stefanc, mw,
linux-arm-kernel
In-Reply-To: <20180517082939.14598-1-antoine.tenart@bootlin.com>
This patch adds the 1000Base-X PHY mode support in the Marvell PPv2
driver. 1000Base-X is quite close the SGMII and uses nearly the same
code path.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 72 ++++++++++++++++++++--------
1 file changed, 51 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 60093f1e6297..ece61f1727e4 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -4870,6 +4870,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
mvpp22_gop_init_rgmii(port);
break;
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
mvpp22_gop_init_sgmii(port);
break;
case PHY_INTERFACE_MODE_10GKR:
@@ -4907,7 +4908,8 @@ static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
u32 val;
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
/* Enable the GMAC link status irq for this port */
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
@@ -4937,7 +4939,8 @@ static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
}
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
@@ -4949,7 +4952,8 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
u32 val;
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_MASK);
val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_MASK);
@@ -4974,6 +4978,7 @@ static int mvpp22_comphy_init(struct mvpp2_port *port)
switch (port->phy_interface) {
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
mode = PHY_MODE_SGMII;
break;
case PHY_INTERFACE_MODE_10GKR:
@@ -5056,7 +5061,8 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port,
else
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
val |= MVPP2_GMAC_PCS_LB_EN_MASK;
else
val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -6266,7 +6272,8 @@ static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
link = true;
}
} else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_STAT);
if (val & MVPP22_GMAC_INT_STAT_LINK) {
event = true;
@@ -8032,20 +8039,25 @@ static void mvpp2_phylink_validate(struct net_device *dev,
phylink_set(mask, Pause);
phylink_set(mask, Asym_Pause);
- phylink_set(mask, 10baseT_Half);
- phylink_set(mask, 10baseT_Full);
- phylink_set(mask, 100baseT_Half);
- phylink_set(mask, 100baseT_Full);
- phylink_set(mask, 1000baseT_Full);
- phylink_set(mask, 10000baseT_Full);
-
- if (state->interface == PHY_INTERFACE_MODE_10GKR) {
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_10GKR:
phylink_set(mask, 10000baseCR_Full);
phylink_set(mask, 10000baseSR_Full);
phylink_set(mask, 10000baseLR_Full);
phylink_set(mask, 10000baseLRM_Full);
phylink_set(mask, 10000baseER_Full);
phylink_set(mask, 10000baseKR_Full);
+ /* Fall-through */
+ default:
+ phylink_set(mask, 10baseT_Half);
+ phylink_set(mask, 10baseT_Full);
+ phylink_set(mask, 100baseT_Half);
+ phylink_set(mask, 100baseT_Full);
+ phylink_set(mask, 10000baseT_Full);
+ /* Fall-through */
+ case PHY_INTERFACE_MODE_1000BASEX:
+ phylink_set(mask, 1000baseT_Full);
+ phylink_set(mask, 1000baseX_Full);
}
bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
@@ -8084,12 +8096,18 @@ static void mvpp2_gmac_link_state(struct mvpp2_port *port,
state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
- if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
+ switch (port->phy_interface) {
+ case PHY_INTERFACE_MODE_1000BASEX:
state->speed = SPEED_1000;
- else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
- state->speed = SPEED_100;
- else
- state->speed = SPEED_10;
+ break;
+ default:
+ if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
+ state->speed = SPEED_1000;
+ else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
+ state->speed = SPEED_100;
+ else
+ state->speed = SPEED_10;
+ }
state->pause = 0;
if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
@@ -8181,8 +8199,18 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
- if (!phy_interface_mode_is_rgmii(state->interface))
+ if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
+ /* 1000BaseX port cannot negotiate speed nor can it negotiate
+ * duplex: they are always operating with a fixed speed of
+ * 1000Mbps in full duplex, so force 1000 speed and full duplex
+ * here.
+ */
+ ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
+ an |= MVPP2_GMAC_CONFIG_GMII_SPEED |
+ MVPP2_GMAC_CONFIG_FULL_DUPLEX;
+ } else if (!phy_interface_mode_is_rgmii(state->interface)) {
an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG;
+ }
if (state->duplex)
an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
@@ -8191,7 +8219,8 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
if (phylink_test(state->advertising, Asym_Pause))
an |= MVPP2_GMAC_FC_ADV_ASM_EN;
- if (state->interface == PHY_INTERFACE_MODE_SGMII) {
+ if (state->interface == PHY_INTERFACE_MODE_SGMII ||
+ state->interface == PHY_INTERFACE_MODE_1000BASEX) {
an |= MVPP2_GMAC_IN_BAND_AUTONEG;
ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
@@ -8256,7 +8285,8 @@ static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
if (state->interface == PHY_INTERFACE_MODE_10GKR)
mvpp2_xlg_config(port, mode, state);
else if (phy_interface_mode_is_rgmii(state->interface) ||
- state->interface == PHY_INTERFACE_MODE_SGMII)
+ state->interface == PHY_INTERFACE_MODE_SGMII ||
+ state->interface == PHY_INTERFACE_MODE_1000BASEX)
mvpp2_gmac_config(port, mode, state);
if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
--
2.17.0
^ permalink raw reply related
* [PATCH net-next v3 04/10] phy: cp110-comphy: 2.5G SGMII mode
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, miquel.raynal, nadavh, stefanc, ymarkman, mw,
linux-arm-kernel
In-Reply-To: <20180517082939.14598-1-antoine.tenart@bootlin.com>
This patch allow the CP110 comphy to configure some lanes in the
2.5G SGMII mode. This mode is quite close to SGMII and uses nearly the
same code path.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index a0d522154cdf..4ef429250d7b 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -135,19 +135,25 @@ struct mvebu_comhy_conf {
static const struct mvebu_comhy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(0, 1, PHY_MODE_2500SGMII, 0x1),
/* lane 1 */
MVEBU_COMPHY_CONF(1, 2, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(1, 2, PHY_MODE_2500SGMII, 0x1),
/* lane 2 */
MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(2, 0, PHY_MODE_2500SGMII, 0x1),
MVEBU_COMPHY_CONF(2, 0, PHY_MODE_10GKR, 0x1),
/* lane 3 */
MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SGMII, 0x2),
+ MVEBU_COMPHY_CONF(3, 1, PHY_MODE_2500SGMII, 0x2),
/* lane 4 */
MVEBU_COMPHY_CONF(4, 0, PHY_MODE_SGMII, 0x2),
+ MVEBU_COMPHY_CONF(4, 0, PHY_MODE_2500SGMII, 0x2),
MVEBU_COMPHY_CONF(4, 0, PHY_MODE_10GKR, 0x2),
MVEBU_COMPHY_CONF(4, 1, PHY_MODE_SGMII, 0x1),
/* lane 5 */
MVEBU_COMPHY_CONF(5, 2, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(5, 2, PHY_MODE_2500SGMII, 0x1),
};
struct mvebu_comphy_priv {
@@ -206,6 +212,10 @@ static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane,
if (mode == PHY_MODE_10GKR)
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe);
+ else if (mode == PHY_MODE_2500SGMII)
+ val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) |
+ MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x8) |
+ MVEBU_COMPHY_SERDES_CFG0_HALF_BUS;
else if (mode == PHY_MODE_SGMII)
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) |
@@ -296,13 +306,13 @@ static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane,
return 0;
}
-static int mvebu_comphy_set_mode_sgmii(struct phy *phy)
+static int mvebu_comphy_set_mode_sgmii(struct phy *phy, enum phy_mode mode)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
u32 val;
- mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_SGMII);
+ mvebu_comphy_ethernet_init_reset(lane, mode);
val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
@@ -487,7 +497,8 @@ static int mvebu_comphy_power_on(struct phy *phy)
switch (lane->mode) {
case PHY_MODE_SGMII:
- ret = mvebu_comphy_set_mode_sgmii(phy);
+ case PHY_MODE_2500SGMII:
+ ret = mvebu_comphy_set_mode_sgmii(phy, lane->mode);
break;
case PHY_MODE_10GKR:
ret = mvebu_comphy_set_mode_10gkr(phy);
--
2.17.0
^ permalink raw reply related
* [PATCH net-next v3 03/10] phy: add 2.5G SGMII mode to the phy_mode enum
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: ymarkman, Antoine Tenart, netdev, linux-kernel, maxime.chevallier,
nadavh, thomas.petazzoni, miquel.raynal, stefanc, mw,
linux-arm-kernel
In-Reply-To: <20180517082939.14598-1-antoine.tenart@bootlin.com>
This patch adds one more generic PHY mode to the phy_mode enum, to allow
configuring generic PHYs to the 2.5G SGMII mode by using the set_mode
callback.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
---
include/linux/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index c9d14eeee7f5..9713aebdd348 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -36,6 +36,7 @@ enum phy_mode {
PHY_MODE_USB_DEVICE_SS,
PHY_MODE_USB_OTG,
PHY_MODE_SGMII,
+ PHY_MODE_2500SGMII,
PHY_MODE_10GKR,
PHY_MODE_UFS_HS_A,
PHY_MODE_UFS_HS_B,
--
2.17.0
^ permalink raw reply related
* [PATCH net-next v3 02/10] net: mvpp2: phylink support
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, miquel.raynal, nadavh, stefanc, ymarkman, mw,
linux-arm-kernel
In-Reply-To: <20180517082939.14598-1-antoine.tenart@bootlin.com>
Convert the PPv2 driver to implement phylink helpers, and use phylink in
DT mode. The other mode supported is ACPI, which will need further work
in order to be entirely compatible with phylink.
The MAC and GoP configuration functions were completely moved to fit
into the phylink helpers. When a PHY is always present between the MAC
and the physical port, phylink only is used, but when this is not the
case (the MAC directly is connected to the physical port) the link IRQ
is used to detect changes in the link state and call phylink_mac_change.
The ACPI mode do not uses phylink as of now, and the changes shouldn't
impact its use.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
drivers/net/ethernet/marvell/Kconfig | 1 +
drivers/net/ethernet/marvell/mvpp2.c | 846 ++++++++++++++++-----------
2 files changed, 509 insertions(+), 338 deletions(-)
diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig
index ebe5c9148935..cc2f7701e71e 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -86,6 +86,7 @@ config MVPP2
depends on ARCH_MVEBU || COMPILE_TEST
depends on HAS_DMA
select MVMDIO
+ select PHYLINK
---help---
This driver supports the network interface units in the
Marvell ARMADA 375, 7K and 8K SoCs.
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 77dd91e3d962..60093f1e6297 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -29,6 +29,7 @@
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/phy.h>
+#include <linux/phylink.h>
#include <linux/phy/phy.h>
#include <linux/clk.h>
#include <linux/hrtimer.h>
@@ -359,15 +360,23 @@
#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
#define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2)
#define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3)
+#define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4)
#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
#define MVPP2_GMAC_FC_ADV_EN BIT(9)
+#define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10)
#define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11)
#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
#define MVPP2_GMAC_STATUS0 0x10
#define MVPP2_GMAC_STATUS0_LINK_UP BIT(0)
+#define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1)
+#define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2)
+#define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3)
+#define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(6)
+#define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(7)
+#define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11)
#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
@@ -379,6 +388,8 @@
#define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1)
#define MVPP22_GMAC_CTRL_4_REG 0x90
#define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)
+#define MVPP22_CTRL4_RX_FC_EN BIT(3)
+#define MVPP22_CTRL4_TX_FC_EN BIT(4)
#define MVPP22_CTRL4_DP_CLK_SEL BIT(5)
#define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6)
#define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)
@@ -392,6 +403,7 @@
#define MVPP22_XLG_CTRL0_PORT_EN BIT(0)
#define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1)
#define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7)
+#define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8)
#define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14)
#define MVPP22_XLG_CTRL1_REG 0x104
#define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0
@@ -413,6 +425,7 @@
#define MVPP22_XLG_CTRL4_FWD_FC BIT(5)
#define MVPP22_XLG_CTRL4_FWD_PFC BIT(6)
#define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12)
+#define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14)
/* SMI registers. PPv2.2 only, relative to priv->iface_base. */
#define MVPP22_SMI_MISC_CFG_REG 0x1204
@@ -1017,6 +1030,9 @@ struct mvpp2_port {
/* Firmware node associated to the port */
struct fwnode_handle *fwnode;
+ /* Is a PHY always connected to the port */
+ bool has_phy;
+
/* Per-port registers' base address */
void __iomem *base;
void __iomem *stats_base;
@@ -1044,12 +1060,11 @@ struct mvpp2_port {
struct mutex gather_stats_lock;
struct delayed_work stats_work;
+ struct device_node *of_node;
+
phy_interface_t phy_interface;
- struct device_node *phy_node;
+ struct phylink *phylink;
struct phy *comphy;
- unsigned int link;
- unsigned int duplex;
- unsigned int speed;
struct mvpp2_bm_pool *pool_long;
struct mvpp2_bm_pool *pool_short;
@@ -1338,6 +1353,12 @@ struct mvpp2_bm_pool {
(addr) < (txq_pcpu)->tso_headers_dma + \
(txq_pcpu)->size * TSO_HEADER_SIZE)
+/* The prototype is added here to be used in start_dev when using ACPI. This
+ * will be removed once phylink is used for all modes (dt+ACPI).
+ */
+static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
+ const struct phylink_link_state *state);
+
/* Queue modes */
#define MVPP2_QDIST_SINGLE_MODE 0
#define MVPP2_QDIST_MULTI_MODE 1
@@ -4969,133 +4990,6 @@ static int mvpp22_comphy_init(struct mvpp2_port *port)
return phy_power_on(port->comphy);
}
-static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
-{
- u32 val;
-
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
- val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
- val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL |
- MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
- val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
- writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
- } else if (phy_interface_mode_is_rgmii(port->phy_interface)) {
- val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
- val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
- MVPP22_CTRL4_SYNC_BYPASS_DIS |
- MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
- val &= ~MVPP22_CTRL4_DP_CLK_SEL;
- writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
- }
-
- /* The port is connected to a copper PHY */
- val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
- val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
- writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
-
- val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
- val |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
- MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
- MVPP2_GMAC_AN_DUPLEX_EN;
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
- val |= MVPP2_GMAC_IN_BAND_AUTONEG;
- writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
-}
-
-static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port)
-{
- u32 val;
-
- /* Force link down */
- val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
- val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
- val |= MVPP2_GMAC_FORCE_LINK_DOWN;
- writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
-
- /* Set the GMAC in a reset state */
- val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
- val |= MVPP2_GMAC_PORT_RESET_MASK;
- writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
-
- /* Configure the PCS and in-band AN */
- val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
- val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
- } else if (phy_interface_mode_is_rgmii(port->phy_interface)) {
- val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
- }
- writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
-
- mvpp2_port_mii_gmac_configure_mode(port);
-
- /* Unset the GMAC reset state */
- val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
- val &= ~MVPP2_GMAC_PORT_RESET_MASK;
- writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
-
- /* Stop forcing link down */
- val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
- val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
- writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
-}
-
-static void mvpp2_port_mii_xlg_configure(struct mvpp2_port *port)
-{
- u32 val;
-
- if (port->gop_id != 0)
- return;
-
- val = readl(port->base + MVPP22_XLG_CTRL0_REG);
- val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
- writel(val, port->base + MVPP22_XLG_CTRL0_REG);
-
- val = readl(port->base + MVPP22_XLG_CTRL4_REG);
- val &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
- val |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC;
- writel(val, port->base + MVPP22_XLG_CTRL4_REG);
-}
-
-static void mvpp22_port_mii_set(struct mvpp2_port *port)
-{
- u32 val;
-
- /* Only GOP port 0 has an XLG MAC */
- if (port->gop_id == 0) {
- val = readl(port->base + MVPP22_XLG_CTRL3_REG);
- val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
-
- if (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
- port->phy_interface == PHY_INTERFACE_MODE_10GKR)
- val |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
- else
- val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
-
- writel(val, port->base + MVPP22_XLG_CTRL3_REG);
- }
-}
-
-static void mvpp2_port_mii_set(struct mvpp2_port *port)
-{
- if (port->priv->hw_version == MVPP22)
- mvpp22_port_mii_set(port);
-
- if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII)
- mvpp2_port_mii_gmac_configure(port);
- else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
- mvpp2_port_mii_xlg_configure(port);
-}
-
-static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
-{
- u32 val;
-
- val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
- val |= MVPP2_GMAC_FC_ADV_EN;
- writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
-}
-
static void mvpp2_port_enable(struct mvpp2_port *port)
{
u32 val;
@@ -5126,8 +5020,11 @@ static void mvpp2_port_disable(struct mvpp2_port *port)
(port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
val = readl(port->base + MVPP22_XLG_CTRL0_REG);
- val &= ~(MVPP22_XLG_CTRL0_PORT_EN |
- MVPP22_XLG_CTRL0_MAC_RESET_DIS);
+ val &= ~MVPP22_XLG_CTRL0_PORT_EN;
+ writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+
+ /* Disable & reset should be done separately */
+ val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
} else {
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
@@ -5147,13 +5044,14 @@ static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
}
/* Configure loopback port */
-static void mvpp2_port_loopback_set(struct mvpp2_port *port)
+static void mvpp2_port_loopback_set(struct mvpp2_port *port,
+ const struct phylink_link_state *state)
{
u32 val;
val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
- if (port->speed == 1000)
+ if (state->speed == 1000)
val |= MVPP2_GMAC_GMII_LB_EN_MASK;
else
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
@@ -5331,10 +5229,6 @@ static void mvpp2_defaults_set(struct mvpp2_port *port)
int tx_port_num, val, queue, ptxq, lrxq;
if (port->priv->hw_version == MVPP21) {
- /* Configure port to loopback if needed */
- if (port->flags & MVPP2_F_LOOPBACK)
- mvpp2_port_loopback_set(port);
-
/* Update TX FIFO MIN Threshold */
val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
@@ -6382,6 +6276,11 @@ static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
}
}
+ if (port->phylink) {
+ phylink_mac_change(port->phylink, link);
+ goto handled;
+ }
+
if (!netif_running(dev) || !event)
goto handled;
@@ -6406,111 +6305,6 @@ static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port,
- struct phy_device *phydev)
-{
- u32 val;
-
- if (port->phy_interface != PHY_INTERFACE_MODE_RGMII &&
- port->phy_interface != PHY_INTERFACE_MODE_RGMII_ID &&
- port->phy_interface != PHY_INTERFACE_MODE_RGMII_RXID &&
- port->phy_interface != PHY_INTERFACE_MODE_RGMII_TXID &&
- port->phy_interface != PHY_INTERFACE_MODE_SGMII)
- return;
-
- val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
- val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
- MVPP2_GMAC_CONFIG_GMII_SPEED |
- MVPP2_GMAC_CONFIG_FULL_DUPLEX |
- MVPP2_GMAC_AN_SPEED_EN |
- MVPP2_GMAC_AN_DUPLEX_EN);
-
- if (phydev->duplex)
- val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
-
- if (phydev->speed == SPEED_1000)
- val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
- else if (phydev->speed == SPEED_100)
- val |= MVPP2_GMAC_CONFIG_MII_SPEED;
-
- writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
-}
-
-/* Adjust link */
-static void mvpp2_link_event(struct net_device *dev)
-{
- struct mvpp2_port *port = netdev_priv(dev);
- struct phy_device *phydev = dev->phydev;
- bool link_reconfigured = false;
- u32 val;
-
- if (phydev->link) {
- if (port->phy_interface != phydev->interface && port->comphy) {
- /* disable current port for reconfiguration */
- mvpp2_interrupts_disable(port);
- netif_carrier_off(port->dev);
- mvpp2_port_disable(port);
- phy_power_off(port->comphy);
-
- /* comphy reconfiguration */
- port->phy_interface = phydev->interface;
- mvpp22_comphy_init(port);
-
- /* gop/mac reconfiguration */
- mvpp22_gop_init(port);
- mvpp2_port_mii_set(port);
-
- link_reconfigured = true;
- }
-
- if ((port->speed != phydev->speed) ||
- (port->duplex != phydev->duplex)) {
- mvpp2_gmac_set_autoneg(port, phydev);
-
- port->duplex = phydev->duplex;
- port->speed = phydev->speed;
- }
- }
-
- if (phydev->link != port->link || link_reconfigured) {
- port->link = phydev->link;
-
- if (phydev->link) {
- if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
- port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
- port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
- val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
- val |= (MVPP2_GMAC_FORCE_LINK_PASS |
- MVPP2_GMAC_FORCE_LINK_DOWN);
- writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
- }
-
- mvpp2_interrupts_enable(port);
- mvpp2_port_enable(port);
-
- mvpp2_egress_enable(port);
- mvpp2_ingress_enable(port);
- netif_carrier_on(dev);
- netif_tx_wake_all_queues(dev);
- } else {
- port->duplex = -1;
- port->speed = 0;
-
- netif_tx_stop_all_queues(dev);
- netif_carrier_off(dev);
- mvpp2_ingress_disable(port);
- mvpp2_egress_disable(port);
-
- mvpp2_port_disable(port);
- mvpp2_interrupts_disable(port);
- }
-
- phy_print_status(phydev);
- }
-}
-
static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
{
ktime_t interval;
@@ -7118,11 +6912,29 @@ static int mvpp2_poll(struct napi_struct *napi, int budget)
return rx_done;
}
-/* Set hw internals when starting port */
-static void mvpp2_start_dev(struct mvpp2_port *port)
+static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
{
- struct net_device *ndev = port->dev;
- int i;
+ u32 ctrl3;
+
+ /* comphy reconfiguration */
+ mvpp22_comphy_init(port);
+
+ /* gop reconfiguration */
+ mvpp22_gop_init(port);
+
+ /* Only GOP port 0 has an XLG MAC */
+ if (port->gop_id == 0) {
+ ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
+ ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+
+ if (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
+ port->phy_interface == PHY_INTERFACE_MODE_10GKR)
+ ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
+ else
+ ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
+
+ writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
+ }
if (port->gop_id == 0 &&
(port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
@@ -7130,6 +6942,12 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
mvpp2_xlg_max_rx_size_set(port);
else
mvpp2_gmac_max_rx_size_set(port);
+}
+
+/* Set hw internals when starting port */
+static void mvpp2_start_dev(struct mvpp2_port *port)
+{
+ int i;
mvpp2_txp_max_tx_size_set(port);
@@ -7139,42 +6957,39 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
/* Enable interrupts on all CPUs */
mvpp2_interrupts_enable(port);
- if (port->priv->hw_version == MVPP22) {
- mvpp22_comphy_init(port);
- mvpp22_gop_init(port);
+ if (port->priv->hw_version == MVPP22)
+ mvpp22_mode_reconfigure(port);
+
+ if (port->phylink) {
+ phylink_start(port->phylink);
+ } else {
+ /* Phylink isn't used as of now for ACPI, so the MAC has to be
+ * configured manually when the interface is started. This will
+ * be removed as soon as the phylink ACPI support lands in.
+ */
+ struct phylink_link_state state = {
+ .interface = port->phy_interface,
+ .link = 1,
+ };
+ mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state);
}
- mvpp2_port_mii_set(port);
- mvpp2_port_enable(port);
- if (ndev->phydev)
- phy_start(ndev->phydev);
netif_tx_start_all_queues(port->dev);
}
/* Set hw internals when stopping port */
static void mvpp2_stop_dev(struct mvpp2_port *port)
{
- struct net_device *ndev = port->dev;
int i;
- /* Stop new packets from arriving to RXQs */
- mvpp2_ingress_disable(port);
-
- mdelay(10);
-
/* Disable interrupts on all CPUs */
mvpp2_interrupts_disable(port);
for (i = 0; i < port->nqvecs; i++)
napi_disable(&port->qvecs[i].napi);
- netif_carrier_off(port->dev);
- netif_tx_stop_all_queues(port->dev);
-
- mvpp2_egress_disable(port);
- mvpp2_port_disable(port);
- if (ndev->phydev)
- phy_stop(ndev->phydev);
+ if (port->phylink)
+ phylink_stop(port->phylink);
phy_power_off(port->comphy);
}
@@ -7233,40 +7048,6 @@ static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
}
-static int mvpp2_phy_connect(struct mvpp2_port *port)
-{
- struct phy_device *phy_dev;
-
- /* No PHY is attached */
- if (!port->phy_node)
- return 0;
-
- phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0,
- port->phy_interface);
- if (!phy_dev) {
- netdev_err(port->dev, "cannot connect to phy\n");
- return -ENODEV;
- }
- phy_dev->supported &= PHY_GBIT_FEATURES;
- phy_dev->advertising = phy_dev->supported;
-
- port->link = 0;
- port->duplex = 0;
- port->speed = 0;
-
- return 0;
-}
-
-static void mvpp2_phy_disconnect(struct mvpp2_port *port)
-{
- struct net_device *ndev = port->dev;
-
- if (!ndev->phydev)
- return;
-
- phy_disconnect(ndev->phydev);
-}
-
static int mvpp2_irqs_init(struct mvpp2_port *port)
{
int err, i;
@@ -7350,6 +7131,7 @@ static int mvpp2_open(struct net_device *dev)
struct mvpp2 *priv = port->priv;
unsigned char mac_bcast[ETH_ALEN] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+ bool valid = false;
int err;
err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
@@ -7392,7 +7174,19 @@ static int mvpp2_open(struct net_device *dev)
goto err_cleanup_txqs;
}
- if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) {
+ /* Phylink isn't supported yet in ACPI mode */
+ if (port->of_node) {
+ err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
+ if (err) {
+ netdev_err(port->dev, "could not attach PHY (%d)\n",
+ err);
+ goto err_free_irq;
+ }
+
+ valid = true;
+ }
+
+ if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) {
err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
dev->name, port);
if (err) {
@@ -7402,14 +7196,20 @@ static int mvpp2_open(struct net_device *dev)
}
mvpp22_gop_setup_irq(port);
- }
- /* In default link is down */
- netif_carrier_off(port->dev);
+ /* In default link is down */
+ netif_carrier_off(port->dev);
- err = mvpp2_phy_connect(port);
- if (err < 0)
- goto err_free_link_irq;
+ valid = true;
+ } else {
+ port->link_irq = 0;
+ }
+
+ if (!valid) {
+ netdev_err(port->dev,
+ "invalid configuration: no dt or link IRQ");
+ goto err_free_irq;
+ }
/* Unmask interrupts on all CPUs */
on_each_cpu(mvpp2_interrupts_unmask, port, 1);
@@ -7426,9 +7226,6 @@ static int mvpp2_open(struct net_device *dev)
return 0;
-err_free_link_irq:
- if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq)
- free_irq(port->link_irq, port);
err_free_irq:
mvpp2_irqs_deinit(port);
err_cleanup_txqs:
@@ -7442,17 +7239,17 @@ static int mvpp2_stop(struct net_device *dev)
{
struct mvpp2_port *port = netdev_priv(dev);
struct mvpp2_port_pcpu *port_pcpu;
- struct mvpp2 *priv = port->priv;
int cpu;
mvpp2_stop_dev(port);
- mvpp2_phy_disconnect(port);
/* Mask interrupts on all CPUs */
on_each_cpu(mvpp2_interrupts_mask, port, 1);
mvpp2_shared_interrupt_mask_unmask(port, true);
- if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq)
+ if (port->phylink)
+ phylink_disconnect_phy(port->phylink);
+ if (port->link_irq)
free_irq(port->link_irq, port);
mvpp2_irqs_deinit(port);
@@ -7658,16 +7455,12 @@ mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
- int ret;
+ struct mvpp2_port *port = netdev_priv(dev);
- if (!dev->phydev)
+ if (!port->phylink)
return -ENOTSUPP;
- ret = phy_mii_ioctl(dev->phydev, ifr, cmd);
- if (!ret)
- mvpp2_link_event(dev);
-
- return ret;
+ return phylink_mii_ioctl(port->phylink, ifr, cmd);
}
static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
@@ -7714,6 +7507,16 @@ static int mvpp2_set_features(struct net_device *dev,
/* Ethtool methods */
+static int mvpp2_ethtool_nway_reset(struct net_device *dev)
+{
+ struct mvpp2_port *port = netdev_priv(dev);
+
+ if (!port->phylink)
+ return -ENOTSUPP;
+
+ return phylink_ethtool_nway_reset(port->phylink);
+}
+
/* Set interrupt coalescing for ethtools */
static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
struct ethtool_coalesce *c)
@@ -7842,6 +7645,50 @@ static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
return err;
}
+static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
+ struct ethtool_pauseparam *pause)
+{
+ struct mvpp2_port *port = netdev_priv(dev);
+
+ if (!port->phylink)
+ return;
+
+ phylink_ethtool_get_pauseparam(port->phylink, pause);
+}
+
+static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
+ struct ethtool_pauseparam *pause)
+{
+ struct mvpp2_port *port = netdev_priv(dev);
+
+ if (!port->phylink)
+ return -ENOTSUPP;
+
+ return phylink_ethtool_set_pauseparam(port->phylink, pause);
+}
+
+static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
+ struct ethtool_link_ksettings *cmd)
+{
+ struct mvpp2_port *port = netdev_priv(dev);
+
+ if (!port->phylink)
+ return -ENOTSUPP;
+
+ return phylink_ethtool_ksettings_get(port->phylink, cmd);
+}
+
+static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
+ const struct ethtool_link_ksettings *cmd)
+{
+ struct mvpp2_port *port = netdev_priv(dev);
+
+ if (!port->phylink)
+ return -ENOTSUPP;
+
+ return phylink_ethtool_ksettings_set(port->phylink, cmd);
+}
+
/* Device ops */
static const struct net_device_ops mvpp2_netdev_ops = {
@@ -7859,7 +7706,7 @@ static const struct net_device_ops mvpp2_netdev_ops = {
};
static const struct ethtool_ops mvpp2_eth_tool_ops = {
- .nway_reset = phy_ethtool_nway_reset,
+ .nway_reset = mvpp2_ethtool_nway_reset,
.get_link = ethtool_op_get_link,
.set_coalesce = mvpp2_ethtool_set_coalesce,
.get_coalesce = mvpp2_ethtool_get_coalesce,
@@ -7869,8 +7716,10 @@ static const struct ethtool_ops mvpp2_eth_tool_ops = {
.get_strings = mvpp2_ethtool_get_strings,
.get_ethtool_stats = mvpp2_ethtool_get_stats,
.get_sset_count = mvpp2_ethtool_get_sset_count,
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
- .set_link_ksettings = phy_ethtool_set_link_ksettings,
+ .get_pauseparam = mvpp2_ethtool_get_pause_param,
+ .set_pauseparam = mvpp2_ethtool_set_pause_param,
+ .get_link_ksettings = mvpp2_ethtool_get_link_ksettings,
+ .set_link_ksettings = mvpp2_ethtool_set_link_ksettings,
};
/* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
@@ -8172,18 +8021,330 @@ static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
eth_hw_addr_random(dev);
}
+static void mvpp2_phylink_validate(struct net_device *dev,
+ unsigned long *supported,
+ struct phylink_link_state *state)
+{
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+
+ phylink_set(mask, Autoneg);
+ phylink_set_port_modes(mask);
+ phylink_set(mask, Pause);
+ phylink_set(mask, Asym_Pause);
+
+ phylink_set(mask, 10baseT_Half);
+ phylink_set(mask, 10baseT_Full);
+ phylink_set(mask, 100baseT_Half);
+ phylink_set(mask, 100baseT_Full);
+ phylink_set(mask, 1000baseT_Full);
+ phylink_set(mask, 10000baseT_Full);
+
+ if (state->interface == PHY_INTERFACE_MODE_10GKR) {
+ phylink_set(mask, 10000baseCR_Full);
+ phylink_set(mask, 10000baseSR_Full);
+ phylink_set(mask, 10000baseLR_Full);
+ phylink_set(mask, 10000baseLRM_Full);
+ phylink_set(mask, 10000baseER_Full);
+ phylink_set(mask, 10000baseKR_Full);
+ }
+
+ bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
+ bitmap_and(state->advertising, state->advertising, mask,
+ __ETHTOOL_LINK_MODE_MASK_NBITS);
+}
+
+static void mvpp22_xlg_link_state(struct mvpp2_port *port,
+ struct phylink_link_state *state)
+{
+ u32 val;
+
+ state->speed = SPEED_10000;
+ state->duplex = 1;
+ state->an_complete = 1;
+
+ val = readl(port->base + MVPP22_XLG_STATUS);
+ state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
+
+ state->pause = 0;
+ val = readl(port->base + MVPP22_XLG_CTRL0_REG);
+ if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
+ state->pause |= MLO_PAUSE_TX;
+ if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
+ state->pause |= MLO_PAUSE_RX;
+}
+
+static void mvpp2_gmac_link_state(struct mvpp2_port *port,
+ struct phylink_link_state *state)
+{
+ u32 val;
+
+ val = readl(port->base + MVPP2_GMAC_STATUS0);
+
+ state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
+ state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
+ state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
+
+ if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
+ state->speed = SPEED_1000;
+ else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
+ state->speed = SPEED_100;
+ else
+ state->speed = SPEED_10;
+
+ state->pause = 0;
+ if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
+ state->pause |= MLO_PAUSE_RX;
+ if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
+ state->pause |= MLO_PAUSE_TX;
+}
+
+static int mvpp2_phylink_mac_link_state(struct net_device *dev,
+ struct phylink_link_state *state)
+{
+ struct mvpp2_port *port = netdev_priv(dev);
+
+ if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
+ u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
+ mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
+
+ if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
+ mvpp22_xlg_link_state(port, state);
+ return 1;
+ }
+ }
+
+ mvpp2_gmac_link_state(port, state);
+ return 1;
+}
+
+static void mvpp2_mac_an_restart(struct net_device *dev)
+{
+ struct mvpp2_port *port = netdev_priv(dev);
+ u32 val;
+
+ if (port->phy_interface != PHY_INTERFACE_MODE_SGMII)
+ return;
+
+ val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+ /* The RESTART_AN bit is cleared by the h/w after restarting the AN
+ * process.
+ */
+ val |= MVPP2_GMAC_IN_BAND_RESTART_AN | MVPP2_GMAC_IN_BAND_AUTONEG;
+ writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
+static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ u32 ctrl0, ctrl4;
+
+ ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG);
+ ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG);
+
+ if (state->pause & MLO_PAUSE_TX)
+ ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
+ if (state->pause & MLO_PAUSE_RX)
+ ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
+
+ ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
+ ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC |
+ MVPP22_XLG_CTRL4_EN_IDLE_CHECK;
+
+ writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG);
+ writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);
+}
+
+static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ u32 an, ctrl0, ctrl2, ctrl4;
+
+ an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+ ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+ ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
+ ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
+
+ /* Force link down */
+ an &= ~MVPP2_GMAC_FORCE_LINK_PASS;
+ an |= MVPP2_GMAC_FORCE_LINK_DOWN;
+ writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+
+ /* Set the GMAC in a reset state */
+ ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK;
+ writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+ an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED |
+ MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
+ MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
+ MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN |
+ MVPP2_GMAC_FORCE_LINK_DOWN);
+ ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
+ ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
+
+ if (!phy_interface_mode_is_rgmii(state->interface))
+ an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG;
+
+ if (state->duplex)
+ an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
+ if (phylink_test(state->advertising, Pause))
+ an |= MVPP2_GMAC_FC_ADV_EN;
+ if (phylink_test(state->advertising, Asym_Pause))
+ an |= MVPP2_GMAC_FC_ADV_ASM_EN;
+
+ if (state->interface == PHY_INTERFACE_MODE_SGMII) {
+ an |= MVPP2_GMAC_IN_BAND_AUTONEG;
+ ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
+
+ ctrl4 &= ~(MVPP22_CTRL4_EXT_PIN_GMII_SEL |
+ MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
+ ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
+ MVPP22_CTRL4_DP_CLK_SEL |
+ MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
+
+ if (state->pause & MLO_PAUSE_TX)
+ ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
+ if (state->pause & MLO_PAUSE_RX)
+ ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
+ } else if (phy_interface_mode_is_rgmii(state->interface)) {
+ an |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS;
+
+ if (state->speed == SPEED_1000)
+ an |= MVPP2_GMAC_CONFIG_GMII_SPEED;
+ else if (state->speed == SPEED_100)
+ an |= MVPP2_GMAC_CONFIG_MII_SPEED;
+
+ ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
+ ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
+ MVPP22_CTRL4_SYNC_BYPASS_DIS |
+ MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
+ }
+
+ writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
+ writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
+ writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
+ writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
+static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct mvpp2_port *port = netdev_priv(dev);
+
+ /* Check for invalid configuration */
+ if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) {
+ netdev_err(dev, "Invalid mode on %s\n", dev->name);
+ return;
+ }
+
+ netif_tx_stop_all_queues(port->dev);
+ if (!port->has_phy)
+ netif_carrier_off(port->dev);
+
+ /* Make sure the port is disabled when reconfiguring the mode */
+ mvpp2_port_disable(port);
+
+ if (port->priv->hw_version == MVPP22 &&
+ port->phy_interface != state->interface) {
+ port->phy_interface = state->interface;
+
+ /* Reconfigure the serdes lanes */
+ phy_power_off(port->comphy);
+ mvpp22_mode_reconfigure(port);
+ }
+
+ /* mac (re)configuration */
+ if (state->interface == PHY_INTERFACE_MODE_10GKR)
+ mvpp2_xlg_config(port, mode, state);
+ else if (phy_interface_mode_is_rgmii(state->interface) ||
+ state->interface == PHY_INTERFACE_MODE_SGMII)
+ mvpp2_gmac_config(port, mode, state);
+
+ if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
+ mvpp2_port_loopback_set(port, state);
+
+ /* If the port already was up, make sure it's still in the same state */
+ if (state->link || !port->has_phy) {
+ mvpp2_port_enable(port);
+
+ mvpp2_egress_enable(port);
+ mvpp2_ingress_enable(port);
+ if (!port->has_phy)
+ netif_carrier_on(dev);
+ netif_tx_wake_all_queues(dev);
+ }
+}
+
+static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
+ phy_interface_t interface, struct phy_device *phy)
+{
+ struct mvpp2_port *port = netdev_priv(dev);
+ u32 val;
+
+ if (!phylink_autoneg_inband(mode) &&
+ interface != PHY_INTERFACE_MODE_10GKR) {
+ val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+ val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
+ if (phy_interface_mode_is_rgmii(interface))
+ val |= MVPP2_GMAC_FORCE_LINK_PASS;
+ writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+ }
+
+ mvpp2_port_enable(port);
+
+ mvpp2_egress_enable(port);
+ mvpp2_ingress_enable(port);
+ netif_tx_wake_all_queues(dev);
+}
+
+static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode,
+ phy_interface_t interface)
+{
+ struct mvpp2_port *port = netdev_priv(dev);
+ u32 val;
+
+ if (!phylink_autoneg_inband(mode) &&
+ interface != PHY_INTERFACE_MODE_10GKR) {
+ val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+ val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
+ val |= MVPP2_GMAC_FORCE_LINK_DOWN;
+ writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+ }
+
+ netif_tx_stop_all_queues(dev);
+ mvpp2_egress_disable(port);
+ mvpp2_ingress_disable(port);
+
+ /* When using link interrupts to notify phylink of a MAC state change,
+ * we do not want the port to be disabled (we want to receive further
+ * interrupts, to be notified when the port will have a link later).
+ */
+ if (!port->has_phy)
+ return;
+
+ mvpp2_port_disable(port);
+}
+
+static const struct phylink_mac_ops mvpp2_phylink_ops = {
+ .validate = mvpp2_phylink_validate,
+ .mac_link_state = mvpp2_phylink_mac_link_state,
+ .mac_an_restart = mvpp2_mac_an_restart,
+ .mac_config = mvpp2_mac_config,
+ .mac_link_up = mvpp2_mac_link_up,
+ .mac_link_down = mvpp2_mac_link_down,
+};
+
/* Ports initialization */
static int mvpp2_port_probe(struct platform_device *pdev,
struct fwnode_handle *port_fwnode,
struct mvpp2 *priv)
{
- struct device_node *phy_node;
struct phy *comphy = NULL;
struct mvpp2_port *port;
struct mvpp2_port_pcpu *port_pcpu;
struct device_node *port_node = to_of_node(port_fwnode);
struct net_device *dev;
struct resource *res;
+ struct phylink *phylink;
char *mac_from = "";
unsigned int ntxqs, nrxqs;
bool has_tx_irqs;
@@ -8212,11 +8373,6 @@ static int mvpp2_port_probe(struct platform_device *pdev,
if (!dev)
return -ENOMEM;
- if (port_node)
- phy_node = of_parse_phandle(port_node, "phy", 0);
- else
- phy_node = NULL;
-
phy_mode = fwnode_get_phy_mode(port_fwnode);
if (phy_mode < 0) {
dev_err(&pdev->dev, "incorrect phy mode\n");
@@ -8249,6 +8405,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
port = netdev_priv(dev);
port->dev = dev;
port->fwnode = port_fwnode;
+ port->has_phy = !!of_find_property(port_node, "phy", NULL);
port->ntxqs = ntxqs;
port->nrxqs = nrxqs;
port->priv = priv;
@@ -8279,7 +8436,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
else
port->first_rxq = port->id * priv->max_port_rxqs;
- port->phy_node = phy_node;
+ port->of_node = port_node;
port->phy_interface = phy_mode;
port->comphy = comphy;
@@ -8340,9 +8497,6 @@ static int mvpp2_port_probe(struct platform_device *pdev,
mvpp2_port_periodic_xon_disable(port);
- if (priv->hw_version == MVPP21)
- mvpp2_port_fc_adv_enable(port);
-
mvpp2_port_reset(port);
port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
@@ -8386,10 +8540,23 @@ static int mvpp2_port_probe(struct platform_device *pdev,
/* 9704 == 9728 - 20 and rounding to 8 */
dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
+ /* Phylink isn't used w/ ACPI as of now */
+ if (port_node) {
+ phylink = phylink_create(dev, port_fwnode, phy_mode,
+ &mvpp2_phylink_ops);
+ if (IS_ERR(phylink)) {
+ err = PTR_ERR(phylink);
+ goto err_free_port_pcpu;
+ }
+ port->phylink = phylink;
+ } else {
+ port->phylink = NULL;
+ }
+
err = register_netdev(dev);
if (err < 0) {
dev_err(&pdev->dev, "failed to register netdev\n");
- goto err_free_port_pcpu;
+ goto err_phylink;
}
netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
@@ -8397,6 +8564,9 @@ static int mvpp2_port_probe(struct platform_device *pdev,
return 0;
+err_phylink:
+ if (port->phylink)
+ phylink_destroy(port->phylink);
err_free_port_pcpu:
free_percpu(port->pcpu);
err_free_txq_pcpu:
@@ -8410,7 +8580,6 @@ static int mvpp2_port_probe(struct platform_device *pdev,
err_deinit_qvecs:
mvpp2_queue_vectors_deinit(port);
err_free_netdev:
- of_node_put(phy_node);
free_netdev(dev);
return err;
}
@@ -8421,7 +8590,8 @@ static void mvpp2_port_remove(struct mvpp2_port *port)
int i;
unregister_netdev(port->dev);
- of_node_put(port->phy_node);
+ if (port->phylink)
+ phylink_destroy(port->phylink);
free_percpu(port->pcpu);
free_percpu(port->stats);
for (i = 0; i < port->ntxqs; i++)
--
2.17.0
^ permalink raw reply related
* [PATCH net-next v3 01/10] net: mvpp2: align the ethtool ops definition
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, miquel.raynal, nadavh, stefanc, ymarkman, mw,
linux-arm-kernel
In-Reply-To: <20180517082939.14598-1-antoine.tenart@bootlin.com>
Cosmetic patch to align the ethtool functions to ops definitions. This
patch does not change in any way the driver's behaviour.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 6f410235987c..77dd91e3d962 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -7859,18 +7859,18 @@ static const struct net_device_ops mvpp2_netdev_ops = {
};
static const struct ethtool_ops mvpp2_eth_tool_ops = {
- .nway_reset = phy_ethtool_nway_reset,
- .get_link = ethtool_op_get_link,
- .set_coalesce = mvpp2_ethtool_set_coalesce,
- .get_coalesce = mvpp2_ethtool_get_coalesce,
- .get_drvinfo = mvpp2_ethtool_get_drvinfo,
- .get_ringparam = mvpp2_ethtool_get_ringparam,
- .set_ringparam = mvpp2_ethtool_set_ringparam,
- .get_strings = mvpp2_ethtool_get_strings,
- .get_ethtool_stats = mvpp2_ethtool_get_stats,
- .get_sset_count = mvpp2_ethtool_get_sset_count,
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
- .set_link_ksettings = phy_ethtool_set_link_ksettings,
+ .nway_reset = phy_ethtool_nway_reset,
+ .get_link = ethtool_op_get_link,
+ .set_coalesce = mvpp2_ethtool_set_coalesce,
+ .get_coalesce = mvpp2_ethtool_get_coalesce,
+ .get_drvinfo = mvpp2_ethtool_get_drvinfo,
+ .get_ringparam = mvpp2_ethtool_get_ringparam,
+ .set_ringparam = mvpp2_ethtool_set_ringparam,
+ .get_strings = mvpp2_ethtool_get_strings,
+ .get_ethtool_stats = mvpp2_ethtool_get_stats,
+ .get_sset_count = mvpp2_ethtool_get_sset_count,
+ .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .set_link_ksettings = phy_ethtool_set_link_ksettings,
};
/* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
--
2.17.0
^ permalink raw reply related
* [PATCH net-next v3 00/10] net: mvpp2: phylink conversion
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, kishon, linux, gregory.clement, andrew, jason,
sebastian.hesselbarth
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, miquel.raynal, nadavh, stefanc, ymarkman, mw,
linux-arm-kernel
Hi Dave, Russell,
This series convert the Marvell PPv2 driver to phylink (models the MAC
to PHY link).
One important point is the PPv2 driver supports two probe modes: device
tree and ACPI. This series only brings phylink support for the device
tree mode, as the ACPI one will need further work. Still, the driver
should be working as before when using ACPI. This split should be
temporary, and was discussed with Marcin (in Cc.) who added ACPI support
to the driver.
Also as the SFP cages on both DB boards can be considered as non-wired.
We thus chose not to describe those SFP cages and we use fixed-link.
The rest of the series uses phylink to add support for 1000BaseX and
2500BaseX modes in the PPv2 driver. To do this, two patches are needed
in the common PHY framework (patches 3 and 4). The last 4 patches modify
the device tree to use the new PPv2 functionalities.
The series has been tested for the device tree mode on the 7040-db,
8040-db and 8040-mcbin boards, to ensure all the interface where working
as expected.
@Dave: patches 7 to 10 should go through the mvebu tree (Gregory in
Cc.) to avoid any conflict with the other mvebu dt patches taken during
this cycle.
The series is based on today's net-next.
Thanks!
Antoine
Since v2:
- Removed the SFP description from the DB boards, as their SFP cages
are wired properly. We now use fixed-link.
- Because of this rework, split the series in two, so that the SFP
part is reviewed separately.
- Small fixes in the phylink patch.
- Rebased on the latest net-next branch.
Since v1:
- Chose a different approach to the SFP changes, as the previous ones
weren't valid and reworked both BD boards device trees.
- Misc fixes.
- Added Kishon's acked-by on one patch.
- Rebaed on latest net-next branch.
Antoine Tenart (9):
net: mvpp2: align the ethtool ops definition
net: mvpp2: phylink support
phy: add 2.5G SGMII mode to the phy_mode enum
phy: cp110-comphy: 2.5G SGMII mode
net: mvpp2: 1000baseX support
net: mvpp2: 2500baseX support
arm64: dts: marvell: mcbin: enable the fourth network interface
arm64: dts: marvell: 8040-db: describe the 10G interfaces as
fixed-link
arm64: dts: marvell: 7040-db: describe the 10G interface as fixed-link
Russell King (1):
arm64: dts: marvell: mcbin: add 10G SFP support
.../arm64/boot/dts/marvell/armada-7040-db.dts | 5 +
.../arm64/boot/dts/marvell/armada-8040-db.dts | 10 +
.../boot/dts/marvell/armada-8040-mcbin.dts | 70 ++
drivers/net/ethernet/marvell/Kconfig | 1 +
drivers/net/ethernet/marvell/mvpp2.c | 931 +++++++++++-------
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 17 +-
include/linux/phy/phy.h | 1 +
7 files changed, 680 insertions(+), 355 deletions(-)
--
2.17.0
^ permalink raw reply
* [PATCH net-next 2/2] net: phy: sfp: warn the user when no tx_disable pin is available
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, linux
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, gregory.clement, miquel.raynal, nadavh,
stefanc, ymarkman, mw
In-Reply-To: <20180517082907.14420-1-antoine.tenart@bootlin.com>
In case no Tx disable pin is available the SFP modules will always be
emitting. This could be an issue when using modules using laser as their
light source as we would have no way to disable it when the fiber is
removed. This patch adds a warning when registering an SFP cage which do
not have its tx_disable pin wired or available.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
---
drivers/net/phy/sfp.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c
index 0fd2a92a6f7b..4e62769b3e00 100644
--- a/drivers/net/phy/sfp.c
+++ b/drivers/net/phy/sfp.c
@@ -1077,6 +1077,15 @@ static int sfp_probe(struct platform_device *pdev)
if (poll)
mod_delayed_work(system_wq, &sfp->poll, poll_jiffies);
+ /* We could have an issue in cases no Tx disable pin is available or
+ * wired as modules using a laser as their light source will continue to
+ * be active when the fiber is removed. This could be a safety issue and
+ * we should at least warn the user about that.
+ */
+ if (!sfp->gpio[GPIO_TX_DISABLE])
+ dev_warn(sfp->dev,
+ "No tx_disable pin: SFP modules will always be emitting.\n");
+
return 0;
}
--
2.17.0
^ permalink raw reply related
* [PATCH net-next 1/2] net: phy: sfp: make the i2c-bus property really optional
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, linux
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, gregory.clement, miquel.raynal, nadavh,
stefanc, ymarkman, mw
In-Reply-To: <20180517082907.14420-1-antoine.tenart@bootlin.com>
The SFF,SFP documentation is clear about making all the DT properties,
with the exception of the compatible, optional. In practice this is not
the case and without an i2c-bus property provided the SFP code will
throw NULL pointer exceptions.
This patch is an attempt to fix this.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
---
drivers/net/phy/sfp.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c
index 4ab6e9a50bbe..0fd2a92a6f7b 100644
--- a/drivers/net/phy/sfp.c
+++ b/drivers/net/phy/sfp.c
@@ -298,11 +298,17 @@ static void sfp_set_state(struct sfp *sfp, unsigned int state)
static int sfp_read(struct sfp *sfp, bool a2, u8 addr, void *buf, size_t len)
{
+ if (!sfp->read)
+ return -ENODEV;
+
return sfp->read(sfp, a2, addr, buf, len);
}
static int sfp_write(struct sfp *sfp, bool a2, u8 addr, void *buf, size_t len)
{
+ if (!sfp->write)
+ return -ENODEV;
+
return sfp->write(sfp, a2, addr, buf, len);
}
@@ -533,6 +539,8 @@ static int sfp_sm_mod_hpower(struct sfp *sfp)
return 0;
err = sfp_read(sfp, true, SFP_EXT_STATUS, &val, sizeof(val));
+ if (err == -ENODEV)
+ goto err;
if (err != sizeof(val)) {
dev_err(sfp->dev, "Failed to read EEPROM: %d\n", err);
err = -EAGAIN;
@@ -542,6 +550,8 @@ static int sfp_sm_mod_hpower(struct sfp *sfp)
val |= BIT(0);
err = sfp_write(sfp, true, SFP_EXT_STATUS, &val, sizeof(val));
+ if (err == -ENODEV)
+ goto err;
if (err != sizeof(val)) {
dev_err(sfp->dev, "Failed to write EEPROM: %d\n", err);
err = -EAGAIN;
@@ -565,6 +575,8 @@ static int sfp_sm_mod_probe(struct sfp *sfp)
int ret;
ret = sfp_read(sfp, false, 0, &id, sizeof(id));
+ if (ret == -ENODEV)
+ return ret;
if (ret < 0) {
dev_err(sfp->dev, "failed to read EEPROM: %d\n", ret);
return -EAGAIN;
--
2.17.0
^ permalink raw reply related
* [PATCH net-next 0/2] net: sfp: small improvements
From: Antoine Tenart @ 2018-05-17 8:29 UTC (permalink / raw)
To: davem, linux
Cc: Antoine Tenart, netdev, linux-kernel, thomas.petazzoni,
maxime.chevallier, gregory.clement, miquel.raynal, nadavh,
stefanc, ymarkman, mw
Hi Russell,
This series was part of the mvpp2 phylink one but as we reworked it to
use fixed-link on the DB boards, the SFP commits weren't needed
anymore for our use case. Two of the three patches still are needed I
believe (I ditched the one about non-wired SFP cages), so they are sent
here in a separate series.
Thanks!
Antoine
Since last time:
- s/-EOPNOTSUPP/-ENODEV/ in patch 1/2.
- I added the acked-by tag in patch 2/2.
Antoine Tenart (2):
net: phy: sfp: make the i2c-bus property really optional
net: phy: sfp: warn the user when no tx_disable pin is available
drivers/net/phy/sfp.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
--
2.17.0
^ permalink raw reply
* [PATCH] net: qcom/emac: Allocate buffers from local node
From: Hemanth Puranik @ 2018-05-17 8:28 UTC (permalink / raw)
To: netdev, linux-kernel; +Cc: Timur Tabi, Hemanth Puranik
Currently we use non-NUMA aware allocation for TPD and RRD buffers,
this patch modifies to use NUMA friendly allocation.
Signed-off-by: Hemanth Puranik <hpuranik@codeaurora.org>
---
drivers/net/ethernet/qualcomm/emac/emac-mac.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/qualcomm/emac/emac-mac.c b/drivers/net/ethernet/qualcomm/emac/emac-mac.c
index 092718a..c3df86a 100644
--- a/drivers/net/ethernet/qualcomm/emac/emac-mac.c
+++ b/drivers/net/ethernet/qualcomm/emac/emac-mac.c
@@ -684,9 +684,10 @@ static int emac_tx_q_desc_alloc(struct emac_adapter *adpt,
{
struct emac_ring_header *ring_header = &adpt->ring_header;
size_t size;
+ int node = dev_to_node(adpt->netdev->dev.parent);
size = sizeof(struct emac_buffer) * tx_q->tpd.count;
- tx_q->tpd.tpbuff = kzalloc(size, GFP_KERNEL);
+ tx_q->tpd.tpbuff = kzalloc_node(size, GFP_KERNEL, node);
if (!tx_q->tpd.tpbuff)
return -ENOMEM;
@@ -725,9 +726,10 @@ static int emac_rx_descs_alloc(struct emac_adapter *adpt)
struct emac_ring_header *ring_header = &adpt->ring_header;
struct emac_rx_queue *rx_q = &adpt->rx_q;
size_t size;
+ int node = dev_to_node(adpt->netdev->dev.parent);
size = sizeof(struct emac_buffer) * rx_q->rfd.count;
- rx_q->rfd.rfbuff = kzalloc(size, GFP_KERNEL);
+ rx_q->rfd.rfbuff = kzalloc_node(size, GFP_KERNEL, node);
if (!rx_q->rfd.rfbuff)
return -ENOMEM;
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
* Re: [PATCH 1/3] sh_eth: add RGMII support
From: Sergei Shtylyov @ 2018-05-17 8:15 UTC (permalink / raw)
To: Andrew Lunn; +Cc: netdev, David S. Miller, linux-renesas-soc
In-Reply-To: <20180516203724.GL26028@lunn.ch>
On 5/16/2018 11:37 PM, Andrew Lunn wrote:
>>> What about
>>> PHY_INTERFACE_MODE_RGMII_ID,
>>> PHY_INTERFACE_MODE_RGMII_RXID,
>>> PHY_INTERFACE_MODE_RGMII_TXID,
>>
>> Oops, totally forgot about those... :-/
>
> Everybody does. I keep intending to write a email template for
> this, and phy_interface_mode_is_rgmii() :-)
The latter doesn't fit for *switch*, anyway.
> Andrew
MBR, Sergei
^ permalink raw reply
* Re: [PATCH 2/3] sh_eth: add EDMR.NBST support
From: Simon Horman @ 2018-05-17 8:12 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: netdev, David S. Miller, linux-renesas-soc
In-Reply-To: <7e929d5a-e97d-7339-a089-2231c7a6a92c@cogentembedded.com>
On Wed, May 16, 2018 at 10:58:26PM +0300, Sergei Shtylyov wrote:
> The R-Car V3H (AKA R8A77980) GEther controller adds the DMA burst mode bit
> (NBST) in EDMR and the manual tells to always set it before doing any DMA.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
>
> ---
> drivers/net/ethernet/renesas/sh_eth.c | 4 ++++
> drivers/net/ethernet/renesas/sh_eth.h | 2 ++
> 2 files changed, 6 insertions(+)
>
> Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
> ===================================================================
> --- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
> +++ net-next/drivers/net/ethernet/renesas/sh_eth.c
> @@ -1434,6 +1434,10 @@ static int sh_eth_dev_init(struct net_de
>
> sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
>
> + /* DMA transfer burst mode */
> + if (mdp->cd->nbst)
> + sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
> +
> if (mdp->cd->bculr)
> sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
Not related to this patch, but: s/sycle/cycle/
>
> Index: net-next/drivers/net/ethernet/renesas/sh_eth.h
> ===================================================================
> --- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h
> +++ net-next/drivers/net/ethernet/renesas/sh_eth.h
> @@ -184,6 +184,7 @@ enum GECMR_BIT {
>
> /* EDMR */
> enum DMAC_M_BIT {
> + EDMR_NBST = 0x80,
It would be nice to start using BIT() in this file.
> EDMR_EL = 0x40, /* Litte endian */
> EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
> EDMR_SRST_GETHER = 0x03,
> @@ -505,6 +506,7 @@ struct sh_eth_cpu_data {
> unsigned bculr:1; /* EtherC have BCULR */
> unsigned tsu:1; /* EtherC have TSU */
> unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
> + unsigned nbst:1; /* E-DMAC has NBST bit in EDMR */
> unsigned rpadir:1; /* E-DMAC have RPADIR */
> unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
> unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
>
^ permalink raw reply
* Re: [RFC PATCH bpf-next 05/12] xdp: add MEM_TYPE_ZERO_COPY
From: Björn Töpel @ 2018-05-17 7:09 UTC (permalink / raw)
To: Jesper Dangaard Brouer
Cc: Magnus Karlsson, Karlsson, Magnus, Duyck, Alexander H,
Alexander Duyck, John Fastabend, Alexei Starovoitov,
Willem de Bruijn, Daniel Borkmann, Michael S. Tsirkin, Netdev,
Björn Töpel, michael.lundkvist, Brandeburg, Jesse,
Singhai, Anjali, Zhang, Qi Z, intel-wired-lan
In-Reply-To: <CAJ+HfNjwM4GeX2Zt9JuJz5Ld80QEzBZsFV+22E4cw3nmU6sJGA@mail.gmail.com>
2018-05-17 9:08 GMT+02:00 Björn Töpel <bjorn.topel@gmail.com>:
> 2018-05-17 7:57 GMT+02:00 Jesper Dangaard Brouer <brouer@redhat.com>:
>> On Tue, 15 May 2018 21:06:08 +0200
>> Björn Töpel <bjorn.topel@gmail.com> wrote:
>>
>>> @@ -82,6 +88,10 @@ struct xdp_frame *convert_to_xdp_frame(struct xdp_buff *xdp)
>>> int metasize;
>>> int headroom;
>>>
>>> + // XXX implement clone, copy, use "native" MEM_TYPE
>>> + if (xdp->rxq->mem.type == MEM_TYPE_ZERO_COPY)
>>> + return NULL;
>>> +
>>
>> There is going to be significant tradeoffs between AF_XDP zero-copy and
>> copy-variant. The copy-variant, still have very attractive
>> RX-performance, and other benefits like no exposing unrelated packets
>> to userspace (but limit these to the XDP filter).
>>
>> Thus, as a user I would like to choose between AF_XDP zero-copy and
>> copy-variant. Even if my NIC support zero-copy, I can be interested in
>> only enabling the copy-variant. This patchset doesn't let me choose.
>>
>> How do we expose this to userspace?
>> (Maybe as simple as an sockaddr_xdp->sxdp_flags flag?)
>>
>
> We planned to add these flags later, but I think you're right that
> it's better to do that right away.
>
> If we try to follow the behavior of the XDP netlink interface: Pick
> the "the best mode" when there are no flags. A user would like to
> "force" a mode -- meaning that you select, say copy, and getting an
> error if that's not supported. Four new flags?
>
> diff --git a/include/uapi/linux/if_xdp.h b/include/uapi/linux/if_xdp.h
> index 77b88c4efe98..ce1f710847b7 100644
> --- a/include/uapi/linux/if_xdp.h
> +++ b/include/uapi/linux/if_xdp.h
> @@ -22,7 +22,11 @@
> #include <linux/types.h>
>
> /* Options for the sxdp_flags field */
> -#define XDP_SHARED_UMEM 1
> +#define XDP_SHARED_UMEM (1U << 0)
> +#define XDP_COPY_TX_UMEM (1U << 1)
> +#define XDP_ZEROCOPY_TX_UMEM (1U << 2)
> +#define XDP_COPY_RX_UMEM (1U << 3)
> +#define XDP_ZEROCOPY_RX_UMEM (1U << 4)
>
> struct sockaddr_xdp {
> __u16 sxdp_family;
>
> A better way?
>
...but without the _UMEM suffix obviously.
>
>
>
>> --
>> Best regards,
>> Jesper Dangaard Brouer
>> MSc.CS, Principal Kernel Engineer at Red Hat
>> LinkedIn: http://www.linkedin.com/in/brouer
^ permalink raw reply
* Re: [RFC PATCH bpf-next 05/12] xdp: add MEM_TYPE_ZERO_COPY
From: Björn Töpel @ 2018-05-17 7:08 UTC (permalink / raw)
To: Jesper Dangaard Brouer
Cc: Magnus Karlsson, Karlsson, Magnus, Duyck, Alexander H,
Alexander Duyck, John Fastabend, Alexei Starovoitov,
Willem de Bruijn, Daniel Borkmann, Michael S. Tsirkin, Netdev,
Björn Töpel, michael.lundkvist, Brandeburg, Jesse,
Singhai, Anjali, Zhang, Qi Z, intel-wired-lan
In-Reply-To: <20180517075756.52e7f82a@redhat.com>
2018-05-17 7:57 GMT+02:00 Jesper Dangaard Brouer <brouer@redhat.com>:
> On Tue, 15 May 2018 21:06:08 +0200
> Björn Töpel <bjorn.topel@gmail.com> wrote:
>
>> @@ -82,6 +88,10 @@ struct xdp_frame *convert_to_xdp_frame(struct xdp_buff *xdp)
>> int metasize;
>> int headroom;
>>
>> + // XXX implement clone, copy, use "native" MEM_TYPE
>> + if (xdp->rxq->mem.type == MEM_TYPE_ZERO_COPY)
>> + return NULL;
>> +
>
> There is going to be significant tradeoffs between AF_XDP zero-copy and
> copy-variant. The copy-variant, still have very attractive
> RX-performance, and other benefits like no exposing unrelated packets
> to userspace (but limit these to the XDP filter).
>
> Thus, as a user I would like to choose between AF_XDP zero-copy and
> copy-variant. Even if my NIC support zero-copy, I can be interested in
> only enabling the copy-variant. This patchset doesn't let me choose.
>
> How do we expose this to userspace?
> (Maybe as simple as an sockaddr_xdp->sxdp_flags flag?)
>
We planned to add these flags later, but I think you're right that
it's better to do that right away.
If we try to follow the behavior of the XDP netlink interface: Pick
the "the best mode" when there are no flags. A user would like to
"force" a mode -- meaning that you select, say copy, and getting an
error if that's not supported. Four new flags?
diff --git a/include/uapi/linux/if_xdp.h b/include/uapi/linux/if_xdp.h
index 77b88c4efe98..ce1f710847b7 100644
--- a/include/uapi/linux/if_xdp.h
+++ b/include/uapi/linux/if_xdp.h
@@ -22,7 +22,11 @@
#include <linux/types.h>
/* Options for the sxdp_flags field */
-#define XDP_SHARED_UMEM 1
+#define XDP_SHARED_UMEM (1U << 0)
+#define XDP_COPY_TX_UMEM (1U << 1)
+#define XDP_ZEROCOPY_TX_UMEM (1U << 2)
+#define XDP_COPY_RX_UMEM (1U << 3)
+#define XDP_ZEROCOPY_RX_UMEM (1U << 4)
struct sockaddr_xdp {
__u16 sxdp_family;
A better way?
> --
> Best regards,
> Jesper Dangaard Brouer
> MSc.CS, Principal Kernel Engineer at Red Hat
> LinkedIn: http://www.linkedin.com/in/brouer
^ permalink raw reply related
* Re: linux-next: manual merge of the net-next tree with the vfs tree
From: Christoph Hellwig @ 2018-05-17 6:47 UTC (permalink / raw)
To: Stephen Rothwell
Cc: David Miller, Networking, Al Viro, Linux-Next Mailing List,
Linux Kernel Mailing List, Christoph Hellwig, Chris Novakovic
In-Reply-To: <20180517113450.182c8259@canb.auug.org.au>
> + /* Create a new file under /proc/net/ipconfig */
> + static int ipconfig_proc_net_create(const char *name,
> + const struct file_operations *fops)
> + {
> + char *pname;
> + struct proc_dir_entry *p;
> +
> + if (!ipconfig_dir)
> + return -ENOMEM;
> +
> + pname = kasprintf(GFP_KERNEL, "%s%s", "ipconfig/", name);
> + if (!pname)
> + return -ENOMEM;
> +
> + p = proc_create(pname, 0444, init_net.proc_net, fops);
> + kfree(pname);
> + if (!p)
> + return -ENOMEM;
> +
> + return 0;
This code doesn't exist in the above mentioned commit. But event
without knowing the details of the /proc/net code this looks somewhat
bogus. For one I thought all the /proc/net files should be per-net
namespace. Second the ntp file really should be using proc_create_net,
to handle all that under the hood - with the merge of the VFS
tree it will take a seq_ops, which is what this code really wants
anyway.
^ permalink raw reply
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