* [PATCH v5 2/5] net: macb: add support for sgmii MAC-PHY interface
From: Parshuram Thombare @ 2019-06-24 12:11 UTC (permalink / raw)
To: andrew, nicolas.ferre, davem, f.fainelli
Cc: linux, netdev, hkallweit1, linux-kernel, rafalc, aniljoy, piotrs,
pthombar
In-Reply-To: <1561378210-11033-1-git-send-email-pthombar@cadence.com>
This patch add support for SGMII interface) and
2.5Gbps MAC in Cadence ethernet controller driver.
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
---
drivers/net/ethernet/cadence/macb.h | 54 +++++++++++++-----
drivers/net/ethernet/cadence/macb_main.c | 72 ++++++++++++++++++++++--
2 files changed, 109 insertions(+), 17 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 8629d345af31..6d268283c318 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -77,6 +77,7 @@
#define MACB_RBQPH 0x04D4
/* GEM register offsets. */
+#define GEM_NCR 0x0000 /* Network Control */
#define GEM_NCFGR 0x0004 /* Network Config */
#define GEM_USRIO 0x000c /* User IO */
#define GEM_DMACFG 0x0010 /* DMA Configuration */
@@ -156,6 +157,7 @@
#define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
#define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
#define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
+#define GEM_PCS_CTRL 0x0200 /* PCS Control */
#define GEM_DCFG1 0x0280 /* Design Config 1 */
#define GEM_DCFG2 0x0284 /* Design Config 2 */
#define GEM_DCFG3 0x0288 /* Design Config 3 */
@@ -271,6 +273,10 @@
#define MACB_IRXFCS_OFFSET 19
#define MACB_IRXFCS_SIZE 1
+/* GEM specific NCR bitfields. */
+#define GEM_TWO_PT_FIVE_GIG_OFFSET 29
+#define GEM_TWO_PT_FIVE_GIG_SIZE 1
+
/* GEM specific NCFGR bitfields. */
#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
#define GEM_GBE_SIZE 1
@@ -323,6 +329,9 @@
#define MACB_MDIO_SIZE 1
#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
#define MACB_IDLE_SIZE 1
+#define MACB_DUPLEX_OFFSET 3
+#define MACB_DUPLEX_SIZE 1
+
/* Bitfields in TSR */
#define MACB_UBR_OFFSET 0 /* Used bit read */
@@ -456,11 +465,17 @@
#define MACB_REV_OFFSET 0
#define MACB_REV_SIZE 16
+/* Bitfields in PCS_CONTROL. */
+#define GEM_PCS_CTRL_RST_OFFSET 15
+#define GEM_PCS_CTRL_RST_SIZE 1
+
/* Bitfields in DCFG1. */
#define GEM_IRQCOR_OFFSET 23
#define GEM_IRQCOR_SIZE 1
#define GEM_DBWDEF_OFFSET 25
#define GEM_DBWDEF_SIZE 3
+#define GEM_NO_PCS_OFFSET 0
+#define GEM_NO_PCS_SIZE 1
/* Bitfields in DCFG2. */
#define GEM_RX_PKT_BUFF_OFFSET 20
@@ -633,19 +648,32 @@
#define MACB_MAN_CODE 2
/* Capability mask bits */
-#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
-#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
-#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
-#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
-#define MACB_CAPS_USRIO_DISABLED 0x00000010
-#define MACB_CAPS_JUMBO 0x00000020
-#define MACB_CAPS_GEM_HAS_PTP 0x00000040
-#define MACB_CAPS_BD_RD_PREFETCH 0x00000080
-#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
-#define MACB_CAPS_FIFO_MODE 0x10000000
-#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
-#define MACB_CAPS_SG_DISABLED 0x40000000
-#define MACB_CAPS_MACB_IS_GEM 0x80000000
+#define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0)
+#define MACB_CAPS_USRIO_HAS_CLKEN BIT(1)
+#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII BIT(2)
+#define MACB_CAPS_NO_GIGABIT_HALF BIT(3)
+#define MACB_CAPS_USRIO_DISABLED BIT(4)
+#define MACB_CAPS_JUMBO BIT(5)
+#define MACB_CAPS_GEM_HAS_PTP BIT(6)
+#define MACB_CAPS_BD_RD_PREFETCH BIT(7)
+#define MACB_CAPS_NEEDS_RSTONUBR BIT(8)
+#define MACB_CAPS_FIFO_MODE BIT(28)
+#define MACB_CAPS_GIGABIT_MODE_AVAILABLE BIT(29)
+#define MACB_CAPS_SG_DISABLED BIT(30)
+#define MACB_CAPS_MACB_IS_GEM BIT(31)
+#define MACB_CAPS_PCS BIT(24)
+#define MACB_CAPS_MACB_IS_GEM_GXL BIT(25)
+
+#define MACB_GEM7010_IDNUM 0x009
+#define MACB_GEM7014_IDNU 0x107
+#define MACB_GEM7014A_IDNUM 0x207
+#define MACB_GEM7016_IDNUM 0x10a
+#define MACB_GEM7017_IDNUM 0x00a
+#define MACB_GEM7017A_IDNUM 0x20a
+#define MACB_GEM7020_IDNUM 0x003
+#define MACB_GEM7021_IDNUM 0x00c
+#define MACB_GEM7021A_IDNUM 0x20c
+#define MACB_GEM7022_IDNUM 0x00b
/* LSO settings */
#define MACB_LSO_UFO_ENABLE 0x01
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index ac5b233cd2e5..572691d948e9 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -445,6 +445,8 @@ static void gem_phylink_validate(struct phylink_config *pl_config,
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
switch (state->interface) {
+ case PHY_INTERFACE_MODE_NA:
+ case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_GMII:
case PHY_INTERFACE_MODE_RGMII:
if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) {
@@ -480,10 +482,31 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
{
struct net_device *netdev = to_net_dev(pl_config->dev);
struct macb *bp = netdev_priv(netdev);
+ bool change_interface = bp->phy_interface != state->interface;
unsigned long flags;
spin_lock_irqsave(&bp->lock, flags);
+ if (change_interface) {
+ bp->phy_interface = state->interface;
+ gem_writel(bp, NCR, ~GEM_BIT(TWO_PT_FIVE_GIG) &
+ gem_readl(bp, NCR));
+
+ if (state->interface == PHY_INTERFACE_MODE_SGMII) {
+ gem_writel(bp, NCFGR, GEM_BIT(SGMIIEN) |
+ GEM_BIT(PCSSEL) |
+ gem_readl(bp, NCFGR));
+ } else {
+ /* Disable SGMII mode and PCS */
+ gem_writel(bp, NCFGR, ~(GEM_BIT(SGMIIEN) |
+ GEM_BIT(PCSSEL)) &
+ gem_readl(bp, NCFGR));
+ /* Reset PCS */
+ gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) |
+ GEM_BIT(PCS_CTRL_RST));
+ }
+ }
+
if (!phylink_autoneg_inband(mode) &&
(bp->speed != state->speed ||
bp->duplex != state->duplex)) {
@@ -493,6 +516,7 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
if (macb_is_gem(bp))
reg &= ~GEM_BIT(GBE);
+
if (state->duplex)
reg |= MACB_BIT(FD);
@@ -587,8 +611,8 @@ static int macb_mii_probe(struct net_device *dev)
}
bp->link = 0;
- bp->speed = 0;
- bp->duplex = -1;
+ bp->speed = SPEED_UNKNOWN;
+ bp->duplex = DUPLEX_UNKNOWN;
return ret;
}
@@ -3337,6 +3361,22 @@ static void macb_configure_caps(struct macb *bp,
dcfg = gem_readl(bp, DCFG1);
if (GEM_BFEXT(IRQCOR, dcfg) == 0)
bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
+ if (GEM_BFEXT(NO_PCS, dcfg) == 0)
+ bp->caps |= MACB_CAPS_PCS;
+ switch (MACB_BFEXT(IDNUM, macb_readl(bp, MID))) {
+ case MACB_GEM7016_IDNUM:
+ case MACB_GEM7017_IDNUM:
+ case MACB_GEM7017A_IDNUM:
+ case MACB_GEM7020_IDNUM:
+ case MACB_GEM7021_IDNUM:
+ case MACB_GEM7021A_IDNUM:
+ case MACB_GEM7022_IDNUM:
+ bp->caps |= MACB_CAPS_USRIO_DISABLED;
+ bp->caps |= MACB_CAPS_MACB_IS_GEM_GXL;
+ break;
+ default:
+ break;
+ }
dcfg = gem_readl(bp, DCFG2);
if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
bp->caps |= MACB_CAPS_FIFO_MODE;
@@ -4319,11 +4359,35 @@ static int macb_probe(struct platform_device *pdev)
}
phy_mode = of_get_phy_mode(np);
- if (phy_mode < 0)
+ if (phy_mode < 0) {
/* not found in DT, MII by default */
bp->phy_interface = PHY_INTERFACE_MODE_MII;
- else
+ } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) {
+ u32 interface_supported = 1;
+
+ if (phy_mode == PHY_INTERFACE_MODE_SGMII) {
+ if (!(bp->caps & MACB_CAPS_PCS))
+ interface_supported = 0;
+ } else if (phy_mode == PHY_INTERFACE_MODE_GMII ||
+ phy_mode == PHY_INTERFACE_MODE_RGMII) {
+ if (!macb_is_gem(bp))
+ interface_supported = 0;
+ } else if (phy_mode != PHY_INTERFACE_MODE_RMII &&
+ phy_mode != PHY_INTERFACE_MODE_MII) {
+ /* Add new mode before this */
+ interface_supported = 0;
+ }
+
+ if (!interface_supported) {
+ netdev_err(dev, "Phy mode %s not supported",
+ phy_modes(phy_mode));
+ goto err_out_free_netdev;
+ }
+
+ bp->phy_interface = phy_mode;
+ } else {
bp->phy_interface = phy_mode;
+ }
/* IP specific init */
err = init(pdev);
--
2.17.1
^ permalink raw reply related
* [PATCH v5 3/5] net: macb: add support for c45 PHY
From: Parshuram Thombare @ 2019-06-24 12:11 UTC (permalink / raw)
To: andrew, nicolas.ferre, davem, f.fainelli
Cc: linux, netdev, hkallweit1, linux-kernel, rafalc, aniljoy, piotrs,
pthombar
In-Reply-To: <1561378210-11033-1-git-send-email-pthombar@cadence.com>
This patch modify MDIO read/write functions to support
communication with C45 PHY.
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/ethernet/cadence/macb.h | 15 ++++--
drivers/net/ethernet/cadence/macb_main.c | 61 +++++++++++++++++++-----
2 files changed, 61 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 6d268283c318..330da702b946 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -642,10 +642,17 @@
#define GEM_CLK_DIV96 5
/* Constants for MAN register */
-#define MACB_MAN_SOF 1
-#define MACB_MAN_WRITE 1
-#define MACB_MAN_READ 2
-#define MACB_MAN_CODE 2
+#define MACB_MAN_C22_SOF 1
+#define MACB_MAN_C22_WRITE 1
+#define MACB_MAN_C22_READ 2
+#define MACB_MAN_C22_CODE 2
+
+#define MACB_MAN_C45_SOF 0
+#define MACB_MAN_C45_ADDR 0
+#define MACB_MAN_C45_WRITE 1
+#define MACB_MAN_C45_POST_READ_INCR 2
+#define MACB_MAN_C45_READ 3
+#define MACB_MAN_C45_CODE 2
/* Capability mask bits */
#define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0)
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 572691d948e9..1323f9b4d3b8 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -341,11 +341,30 @@ static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
if (status < 0)
goto mdio_read_exit;
- macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
- | MACB_BF(RW, MACB_MAN_READ)
- | MACB_BF(PHYA, mii_id)
- | MACB_BF(REGA, regnum)
- | MACB_BF(CODE, MACB_MAN_CODE)));
+ if (regnum & MII_ADDR_C45) {
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
+ | MACB_BF(RW, MACB_MAN_C45_ADDR)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, (regnum >> 16) & 0x1F)
+ | MACB_BF(DATA, regnum & 0xFFFF)
+ | MACB_BF(CODE, MACB_MAN_C45_CODE)));
+
+ status = macb_mdio_wait_for_idle(bp);
+ if (status < 0)
+ goto mdio_read_exit;
+
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
+ | MACB_BF(RW, MACB_MAN_C45_READ)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, (regnum >> 16) & 0x1F)
+ | MACB_BF(CODE, MACB_MAN_C45_CODE)));
+ } else {
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
+ | MACB_BF(RW, MACB_MAN_C22_READ)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, regnum)
+ | MACB_BF(CODE, MACB_MAN_C22_CODE)));
+ }
status = macb_mdio_wait_for_idle(bp);
if (status < 0)
@@ -374,12 +393,32 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
if (status < 0)
goto mdio_write_exit;
- macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
- | MACB_BF(RW, MACB_MAN_WRITE)
- | MACB_BF(PHYA, mii_id)
- | MACB_BF(REGA, regnum)
- | MACB_BF(CODE, MACB_MAN_CODE)
- | MACB_BF(DATA, value)));
+ if (regnum & MII_ADDR_C45) {
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
+ | MACB_BF(RW, MACB_MAN_C45_ADDR)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, (regnum >> 16) & 0x1F)
+ | MACB_BF(DATA, regnum & 0xFFFF)
+ | MACB_BF(CODE, MACB_MAN_C45_CODE)));
+
+ status = macb_mdio_wait_for_idle(bp);
+ if (status < 0)
+ goto mdio_write_exit;
+
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
+ | MACB_BF(RW, MACB_MAN_C45_WRITE)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, (regnum >> 16) & 0x1F)
+ | MACB_BF(CODE, MACB_MAN_C45_CODE)
+ | MACB_BF(DATA, value)));
+ } else {
+ macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
+ | MACB_BF(RW, MACB_MAN_C22_WRITE)
+ | MACB_BF(PHYA, mii_id)
+ | MACB_BF(REGA, regnum)
+ | MACB_BF(CODE, MACB_MAN_C22_CODE)
+ | MACB_BF(DATA, value)));
+ }
status = macb_mdio_wait_for_idle(bp);
if (status < 0)
--
2.17.1
^ permalink raw reply related
* [PATCH v5 4/5] net: macb: add support for high speed interface
From: Parshuram Thombare @ 2019-06-24 12:12 UTC (permalink / raw)
To: andrew, nicolas.ferre, davem, f.fainelli
Cc: linux, netdev, hkallweit1, linux-kernel, rafalc, aniljoy, piotrs,
pthombar
In-Reply-To: <1561378210-11033-1-git-send-email-pthombar@cadence.com>
This patch add support for high speed USXGMII PCS and 10G
speed in Cadence ethernet controller driver.
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
---
drivers/net/ethernet/cadence/macb.h | 41 +++++
drivers/net/ethernet/cadence/macb_main.c | 189 ++++++++++++++++++++---
2 files changed, 207 insertions(+), 23 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 330da702b946..809acff19be9 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -82,6 +82,7 @@
#define GEM_USRIO 0x000c /* User IO */
#define GEM_DMACFG 0x0010 /* DMA Configuration */
#define GEM_JML 0x0048 /* Jumbo Max Length */
+#define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
#define GEM_HRB 0x0080 /* Hash Bottom */
#define GEM_HRT 0x0084 /* Hash Top */
#define GEM_SA1B 0x0088 /* Specific1 Bottom */
@@ -167,6 +168,9 @@
#define GEM_DCFG7 0x0298 /* Design Config 7 */
#define GEM_DCFG8 0x029C /* Design Config 8 */
#define GEM_DCFG10 0x02A4 /* Design Config 10 */
+#define GEM_DCFG12 0x02AC /* Design Config 12 */
+#define GEM_USX_CONTROL 0x0A80 /* USXGMII control register */
+#define GEM_USX_STATUS 0x0A88 /* USXGMII status register */
#define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
#define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
@@ -274,6 +278,8 @@
#define MACB_IRXFCS_SIZE 1
/* GEM specific NCR bitfields. */
+#define GEM_ENABLE_HS_MAC_OFFSET 31
+#define GEM_ENABLE_HS_MAC_SIZE 1
#define GEM_TWO_PT_FIVE_GIG_OFFSET 29
#define GEM_TWO_PT_FIVE_GIG_SIZE 1
@@ -465,6 +471,10 @@
#define MACB_REV_OFFSET 0
#define MACB_REV_SIZE 16
+/* Bitfield in HS_MAC_CONFIG */
+#define GEM_HS_MAC_SPEED_OFFSET 0
+#define GEM_HS_MAC_SPEED_SIZE 3
+
/* Bitfields in PCS_CONTROL. */
#define GEM_PCS_CTRL_RST_OFFSET 15
#define GEM_PCS_CTRL_RST_SIZE 1
@@ -510,6 +520,34 @@
#define GEM_RXBD_RDBUFF_OFFSET 8
#define GEM_RXBD_RDBUFF_SIZE 4
+/* Bitfields in DCFG12. */
+#define GEM_HIGH_SPEED_OFFSET 26
+#define GEM_HIGH_SPEED_SIZE 1
+
+/* Bitfields in USX_CONTROL. */
+#define GEM_USX_CTRL_SPEED_OFFSET 14
+#define GEM_USX_CTRL_SPEED_SIZE 3
+#define GEM_SERDES_RATE_OFFSET 12
+#define GEM_SERDES_RATE_SIZE 2
+#define GEM_RX_SCR_BYPASS_OFFSET 9
+#define GEM_RX_SCR_BYPASS_SIZE 1
+#define GEM_TX_SCR_BYPASS_OFFSET 8
+#define GEM_TX_SCR_BYPASS_SIZE 1
+#define GEM_RX_SYNC_RESET_OFFSET 2
+#define GEM_RX_SYNC_RESET_SIZE 1
+#define GEM_TX_EN_OFFSET 1
+#define GEM_TX_EN_SIZE 1
+#define GEM_SIGNAL_OK_OFFSET 0
+#define GEM_SIGNAL_OK_SIZE 1
+
+/* Bitfields in USX_STATUS. */
+#define GEM_USX_TX_FAULT_OFFSET 28
+#define GEM_USX_TX_FAULT_SIZE 1
+#define GEM_USX_RX_FAULT_OFFSET 27
+#define GEM_USX_RX_FAULT_SIZE 1
+#define GEM_USX_BLOCK_LOCK_OFFSET 0
+#define GEM_USX_BLOCK_LOCK_SIZE 1
+
/* Bitfields in TISUBN */
#define GEM_SUBNSINCR_OFFSET 0
#define GEM_SUBNSINCR_SIZE 16
@@ -670,6 +708,7 @@
#define MACB_CAPS_MACB_IS_GEM BIT(31)
#define MACB_CAPS_PCS BIT(24)
#define MACB_CAPS_MACB_IS_GEM_GXL BIT(25)
+#define MACB_CAPS_HIGH_SPEED BIT(26)
#define MACB_GEM7010_IDNUM 0x009
#define MACB_GEM7014_IDNU 0x107
@@ -749,6 +788,7 @@
})
#define MACB_READ_NSR(bp) macb_readl(bp, NSR)
+#define GEM_READ_USX_STATUS(bp) gem_readl(bp, USX_STATUS)
/* struct macb_dma_desc - Hardware DMA descriptor
* @addr: DMA address of data buffer
@@ -1262,6 +1302,7 @@ struct macb {
struct macb_pm_data pm_data;
struct phylink *pl;
struct phylink_config pl_config;
+ u32 serdes_rate;
};
#ifdef CONFIG_MACB_USE_HWSTAMP
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 1323f9b4d3b8..5afc03299bee 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -84,6 +84,20 @@ static struct sifive_fu540_macb_mgmt *mgmt;
#define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
#define MACB_WOL_ENABLED (0x1 << 1)
+enum {
+ HS_MAC_SPEED_100M,
+ HS_MAC_SPEED_1000M,
+ HS_MAC_SPEED_2500M,
+ HS_MAC_SPEED_5000M,
+ HS_MAC_SPEED_10000M,
+ HS_MAC_SPEED_25000M,
+};
+
+enum {
+ MACB_SERDES_RATE_5Gbps = 5,
+ MACB_SERDES_RATE_10Gbps = 10,
+};
+
/* Graceful stop timeouts in us. We should allow up to
* 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
*/
@@ -93,6 +107,8 @@ static struct sifive_fu540_macb_mgmt *mgmt;
#define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
+#define MACB_USX_BLOCK_LOCK_TIMEOUT 1000000 /* in usecs */
+
/* DMA buffer descriptor might be different size
* depends on hardware configuration:
*
@@ -439,23 +455,37 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
*/
static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
{
+ struct macb *bp = netdev_priv(dev);
long ferr, rate, rate_rounded;
if (!clk)
return;
- switch (speed) {
- case SPEED_10:
- rate = 2500000;
- break;
- case SPEED_100:
- rate = 25000000;
- break;
- case SPEED_1000:
- rate = 125000000;
- break;
- default:
- return;
+ if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
+ switch (bp->serdes_rate) {
+ case MACB_SERDES_RATE_5Gbps:
+ rate = 78125000;
+ break;
+ case MACB_SERDES_RATE_10Gbps:
+ rate = 156250000;
+ break;
+ default:
+ return;
+ }
+ } else {
+ switch (speed) {
+ case SPEED_10:
+ rate = 2500000;
+ break;
+ case SPEED_100:
+ rate = 25000000;
+ break;
+ case SPEED_1000:
+ rate = 125000000;
+ break;
+ default:
+ return;
+ }
}
rate_rounded = clk_round_rate(clk, rate);
@@ -485,6 +515,21 @@ static void gem_phylink_validate(struct phylink_config *pl_config,
switch (state->interface) {
case PHY_INTERFACE_MODE_NA:
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GKR:
+ if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) {
+ phylink_set(mask, 10000baseCR_Full);
+ phylink_set(mask, 10000baseER_Full);
+ phylink_set(mask, 10000baseKR_Full);
+ phylink_set(mask, 10000baseLR_Full);
+ phylink_set(mask, 10000baseLRM_Full);
+ phylink_set(mask, 10000baseSR_Full);
+ phylink_set(mask, 10000baseT_Full);
+ phylink_set(mask, 5000baseT_Full);
+ phylink_set(mask, 2500baseX_Full);
+ phylink_set(mask, 1000baseX_Full);
+ }
+ /* fallthrough */
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_GMII:
case PHY_INTERFACE_MODE_RGMII:
@@ -516,6 +561,91 @@ static int gem_phylink_mac_link_state(struct phylink_config *pl_config,
return -EOPNOTSUPP;
}
+static int macb_wait_for_usx_block_lock(struct macb *bp)
+{
+ u32 val;
+
+ return readx_poll_timeout(GEM_READ_USX_STATUS, bp, val,
+ val & GEM_BIT(USX_BLOCK_LOCK),
+ 1, MACB_USX_BLOCK_LOCK_TIMEOUT);
+}
+
+static inline int gem_mac_usx_configure(struct macb *bp, int spd)
+{
+ u32 speed, config;
+
+ gem_writel(bp, NCFGR, GEM_BIT(PCSSEL) |
+ (~GEM_BIT(SGMIIEN) & gem_readl(bp, NCFGR)));
+ gem_writel(bp, NCR, gem_readl(bp, NCR) |
+ GEM_BIT(ENABLE_HS_MAC));
+ gem_writel(bp, NCFGR, gem_readl(bp, NCFGR) |
+ MACB_BIT(FD));
+ config = gem_readl(bp, USX_CONTROL);
+ config = GEM_BFINS(SERDES_RATE, bp->serdes_rate, config);
+ config &= ~GEM_BIT(TX_SCR_BYPASS);
+ config &= ~GEM_BIT(RX_SCR_BYPASS);
+ gem_writel(bp, USX_CONTROL, config |
+ GEM_BIT(TX_EN));
+ config = gem_readl(bp, USX_CONTROL);
+ gem_writel(bp, USX_CONTROL, config | GEM_BIT(SIGNAL_OK));
+ if (macb_wait_for_usx_block_lock(bp) < 0) {
+ netdev_warn(bp->dev, "USXGMII block lock failed");
+ return -ETIMEDOUT;
+ }
+
+ switch (spd) {
+ case SPEED_10000:
+ if (bp->serdes_rate >= MACB_SERDES_RATE_10Gbps) {
+ speed = HS_MAC_SPEED_10000M;
+ } else {
+ netdev_warn(bp->dev, "10G speed isn't supported by HW");
+ netdev_warn(bp->dev, "Setting speed to 1G");
+ speed = HS_MAC_SPEED_1000M;
+ }
+ break;
+ case SPEED_5000:
+ speed = HS_MAC_SPEED_5000M;
+ break;
+ case SPEED_2500:
+ speed = HS_MAC_SPEED_2500M;
+ break;
+ case SPEED_1000:
+ speed = HS_MAC_SPEED_1000M;
+ break;
+ default:
+ case SPEED_100:
+ speed = HS_MAC_SPEED_100M;
+ break;
+ }
+
+ gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, speed,
+ gem_readl(bp, HS_MAC_CONFIG)));
+ gem_writel(bp, USX_CONTROL, GEM_BFINS(USX_CTRL_SPEED, speed,
+ gem_readl(bp, USX_CONTROL)));
+ return 0;
+}
+
+static inline void gem_mac_configure(struct macb *bp, int speed)
+{
+ if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ gem_writel(bp, NCFGR, GEM_BIT(SGMIIEN) |
+ GEM_BIT(PCSSEL) |
+ gem_readl(bp, NCFGR));
+
+ switch (speed) {
+ case SPEED_1000:
+ gem_writel(bp, NCFGR, GEM_BIT(GBE) |
+ gem_readl(bp, NCFGR));
+ break;
+ case SPEED_100:
+ macb_writel(bp, NCFGR, MACB_BIT(SPD) |
+ macb_readl(bp, NCFGR));
+ break;
+ default:
+ break;
+ }
+}
+
static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
const struct phylink_link_state *state)
{
@@ -558,18 +688,17 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
if (state->duplex)
reg |= MACB_BIT(FD);
+ macb_or_gem_writel(bp, NCFGR, reg);
- switch (state->speed) {
- case SPEED_1000:
- reg |= GEM_BIT(GBE);
- break;
- case SPEED_100:
- reg |= MACB_BIT(SPD);
- break;
- default:
- break;
+ if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
+ if (gem_mac_usx_configure(bp, state->speed) < 0) {
+ spin_unlock_irqrestore(&bp->lock, flags);
+ phylink_mac_change(bp->pl, false);
+ return;
+ }
+ } else {
+ gem_mac_configure(bp, state->speed);
}
- macb_or_gem_writel(bp, NCFGR, reg);
bp->speed = state->speed;
bp->duplex = state->duplex;
@@ -3416,6 +3545,9 @@ static void macb_configure_caps(struct macb *bp,
default:
break;
}
+ dcfg = gem_readl(bp, DCFG12);
+ if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
+ bp->caps |= MACB_CAPS_HIGH_SPEED;
dcfg = gem_readl(bp, DCFG2);
if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
bp->caps |= MACB_CAPS_FIFO_MODE;
@@ -4404,7 +4536,18 @@ static int macb_probe(struct platform_device *pdev)
} else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) {
u32 interface_supported = 1;
- if (phy_mode == PHY_INTERFACE_MODE_SGMII) {
+ if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
+ if (!(bp->caps & MACB_CAPS_HIGH_SPEED &&
+ bp->caps & MACB_CAPS_PCS))
+ interface_supported = 0;
+
+ if (of_property_read_u32(np, "serdes-rate-gbps",
+ &bp->serdes_rate)) {
+ netdev_err(dev,
+ "GEM serdes_rate not specified");
+ interface_supported = 0;
+ }
+ } else if (phy_mode == PHY_INTERFACE_MODE_SGMII) {
if (!(bp->caps & MACB_CAPS_PCS))
interface_supported = 0;
} else if (phy_mode == PHY_INTERFACE_MODE_GMII ||
--
2.17.1
^ permalink raw reply related
* [PATCH v5 5/5] net: macb: parameter added to cadence ethernet controller DT binding
From: Parshuram Thombare @ 2019-06-24 12:12 UTC (permalink / raw)
To: andrew, nicolas.ferre, davem, f.fainelli
Cc: linux, netdev, hkallweit1, linux-kernel, rafalc, aniljoy, piotrs,
pthombar
In-Reply-To: <1561378210-11033-1-git-send-email-pthombar@cadence.com>
New parameters added to Cadence ethernet controller DT binding
for USXGMII interface.
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
---
Documentation/devicetree/bindings/net/macb.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
index 63c73fafe26d..dabdf9d3b574 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -28,6 +28,9 @@ Required properties:
Optional elements: 'rx_clk' applies to cdns,zynqmp-gem
Optional elements: 'tsu_clk'
- clocks: Phandles to input clocks.
+- serdes-rate-gbps External serdes rate.Mandatory for USXGMII mode.
+ 5 - 5G
+ 10 - 10G
The MAC address will be determined using the optional properties
defined in ethernet.txt.
--
2.17.1
^ permalink raw reply related
* Re: WARNING: ODEBUG bug in netdev_freemem (2)
From: Dmitry Vyukov @ 2019-06-24 12:22 UTC (permalink / raw)
To: Eric Dumazet
Cc: Thomas Gleixner, syzbot, Alexander Duyck, amritha.nambiar,
Andy Shevchenko, David Miller, Dmitry Torokhov, Florian Fainelli,
Greg Kroah-Hartman, Ido Schimmel, LKML, netdev, syzkaller-bugs,
tyhicks, wanghai26, yuehaibing
In-Reply-To: <da83da44-0088-3056-6bba-d028b6cbb218@gmail.com>
On Mon, Jun 24, 2019 at 2:08 PM Eric Dumazet <eric.dumazet@gmail.com> wrote:
> On 6/24/19 3:54 AM, Dmitry Vyukov wrote:
> > On Mon, Jun 24, 2019 at 11:34 AM Thomas Gleixner <tglx@linutronix.de> wrote:
> >>
> >> On Mon, 24 Jun 2019, syzbot wrote:
> >>
> >>> Hello,
> >>>
> >>> syzbot found the following crash on:
> >>>
> >>> HEAD commit: fd6b99fa Merge branch 'akpm' (patches from Andrew)
> >>> git tree: upstream
> >>> console output: https://syzkaller.appspot.com/x/log.txt?x=144de256a00000
> >>> kernel config: https://syzkaller.appspot.com/x/.config?x=fa9f7e1b6a8bb586
> >>> dashboard link: https://syzkaller.appspot.com/bug?extid=c4521ac872a4ccc3afec
> >>> compiler: gcc (GCC) 9.0.0 20181231 (experimental)
> >>>
> >>> Unfortunately, I don't have any reproducer for this crash yet.
> >>>
> >>> IMPORTANT: if you fix the bug, please add the following tag to the commit:
> >>> Reported-by: syzbot+c4521ac872a4ccc3afec@syzkaller.appspotmail.com
> >>>
> >>> device hsr_slave_0 left promiscuous mode
> >>> team0 (unregistering): Port device team_slave_1 removed
> >>> team0 (unregistering): Port device team_slave_0 removed
> >>> bond0 (unregistering): Releasing backup interface bond_slave_1
> >>> bond0 (unregistering): Releasing backup interface bond_slave_0
> >>> bond0 (unregistering): Released>
>
> all slaves
> >>> ------------[ cut here ]------------
> >>> ODEBUG: free active (active state 0) object type: timer_list hint:
> >>> delayed_work_timer_fn+0x0/0x90 arch/x86/include/asm/paravirt.h:767
> >>
> >> One of the cleaned up devices has left an active timer which belongs to a
> >> delayed work. That's all I can decode out of that splat. :(
> >
> > Hi Thomas,
> >
> > If ODEBUG would memorize full stack traces for object allocation
> > (using lib/stackdepot.c), it would make this splat actionable, right?
> > I've fixed https://bugzilla.kernel.org/show_bug.cgi?id=203969 for this.
> >
>
> Not sure this would help in this case as some netdev are allocated through a generic helper.
>
> The driver specific portion might not show up in the stack trace.
>
> It would be nice here to get the work queue function pointer,
> so that it gives us a clue which driver needs a fix.
I see. But isn't the workqueue callback is cleanup_net in this case
and is in the stack?
cleanup_net+0x3fb/0x960 net/core/net_namespace.c:553
process_one_work+0x989/0x1790 kernel/workqueue.c:2269
^ permalink raw reply
* Re: KASAN: global-out-of-bounds Read in qmi_wwan_probe
From: Bjørn Mork @ 2019-06-24 12:59 UTC (permalink / raw)
To: Kristian Evensen
Cc: syzbot, andreyknvl, davem, linux-kernel, linux-usb, netdev,
syzkaller-bugs
In-Reply-To: <0000000000008f19f7058c10a633@google.com>
syzbot <syzbot+b68605d7fadd21510de1@syzkaller.appspotmail.com> writes:
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit: 9939f56e usb-fuzzer: main usb gadget fuzzer driver
> git tree: https://github.com/google/kasan.git usb-fuzzer
> console output: https://syzkaller.appspot.com/x/log.txt?x=1615a669a00000
> kernel config: https://syzkaller.appspot.com/x/.config?x=df134eda130bb43a
> dashboard link: https://syzkaller.appspot.com/bug?extid=b68605d7fadd21510de1
> compiler: gcc (GCC) 9.0.0 20181231 (experimental)
> syz repro: https://syzkaller.appspot.com/x/repro.syz?x=10630af6a00000
> C reproducer: https://syzkaller.appspot.com/x/repro.c?x=1127da69a00000
>
> IMPORTANT: if you fix the bug, please add the following tag to the commit:
> Reported-by: syzbot+b68605d7fadd21510de1@syzkaller.appspotmail.com
>
> usb 1-1: new high-speed USB device number 2 using dummy_hcd
> usb 1-1: Using ep0 maxpacket: 8
> usb 1-1: New USB device found, idVendor=12d1, idProduct=14f1,
> bcdDevice=d4.d9
> usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
> usb 1-1: config 0 descriptor??
> ==================================================================
> BUG: KASAN: global-out-of-bounds in qmi_wwan_probe+0x342/0x360
> drivers/net/usb/qmi_wwan.c:1417
> Read of size 8 at addr ffffffff8618c140 by task kworker/1:1/22
>
> CPU: 1 PID: 22 Comm: kworker/1:1 Not tainted 5.2.0-rc5+ #11
> Hardware name: Google Google Compute Engine/Google Compute Engine,
> BIOS Google 01/01/2011
> Workqueue: usb_hub_wq hub_event
> Call Trace:
> __dump_stack lib/dump_stack.c:77 [inline]
> dump_stack+0xca/0x13e lib/dump_stack.c:113
> print_address_description+0x67/0x231 mm/kasan/report.c:188
> __kasan_report.cold+0x1a/0x32 mm/kasan/report.c:317
> kasan_report+0xe/0x20 mm/kasan/common.c:614
> qmi_wwan_probe+0x342/0x360 drivers/net/usb/qmi_wwan.c:1417
> usb_probe_interface+0x305/0x7a0 drivers/usb/core/driver.c:361
> really_probe+0x281/0x660 drivers/base/dd.c:509
> driver_probe_device+0x104/0x210 drivers/base/dd.c:670
> __device_attach_driver+0x1c2/0x220 drivers/base/dd.c:777
> bus_for_each_drv+0x15c/0x1e0 drivers/base/bus.c:454
>
Hello Kristian!
I need some help understanding this... IIUC syzbot is claiming an
out-of-bounds access at line 1417 in v5.2-rc5. Or whatever - I'm having
a hard time deciphering what kernel version the bot is actually
testing. The claimed HEAD is not a kernel commit. At least not in my
kernel...
But if this is correct, then it points to the info->data access you
recently added:
822e44b45eb99 (Kristian Evensen 2019-03-02 13:32:26 +0100 1409) /* Several Quectel modems supports dynamic interface configuration, so
7c5cca3588545 (Kristian Evensen 2018-09-08 13:50:48 +0200 1410) * we need to match on class/subclass/protocol. These values are
7c5cca3588545 (Kristian Evensen 2018-09-08 13:50:48 +0200 1411) * identical for the diagnostic- and QMI-interface, but bNumEndpoints is
7c5cca3588545 (Kristian Evensen 2018-09-08 13:50:48 +0200 1412) * different. Ignore the current interface if the number of endpoints
e4bf63482c309 (Kristian Evensen 2019-04-07 15:39:09 +0200 1413) * equals the number for the diag interface (two).
7c5cca3588545 (Kristian Evensen 2018-09-08 13:50:48 +0200 1414) */
e4bf63482c309 (Kristian Evensen 2019-04-07 15:39:09 +0200 1415) info = (void *)&id->driver_info;
e4bf63482c309 (Kristian Evensen 2019-04-07 15:39:09 +0200 1416)
e4bf63482c309 (Kristian Evensen 2019-04-07 15:39:09 +0200 1417) if (info->data & QMI_WWAN_QUIRK_QUECTEL_DYNCFG) {
e4bf63482c309 (Kristian Evensen 2019-04-07 15:39:09 +0200 1418) if (desc->bNumEndpoints == 2)
e4bf63482c309 (Kristian Evensen 2019-04-07 15:39:09 +0200 1419) return -ENODEV;
e4bf63482c309 (Kristian Evensen 2019-04-07 15:39:09 +0200 1420) }
I must be blind. I cannot see how this could end up failing.
id->driver_info is always set to one of qmi_wwan_info,
qmi_wwan_info_quirk_dtr or qmi_wwan_info_quirk_quectel_dyncfg at this
point. How does that end up out-of-bounds?
Bjørn
^ permalink raw reply
* Re: memory leak in sctp_v4_create_accept_sk
From: Xin Long @ 2019-06-24 13:11 UTC (permalink / raw)
To: syzbot
Cc: davem, LKML, linux-sctp, Marcelo Ricardo Leitner, network dev,
Neil Horman, syzkaller-bugs, Vlad Yasevich
In-Reply-To: <00000000000064c849058c0cbdc9@google.com>
On Mon, Jun 24, 2019 at 3:28 PM syzbot
<syzbot+afabda3890cc2f765041@syzkaller.appspotmail.com> wrote:
>
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit: abf02e29 Merge tag 'pm-5.2-rc6' of git://git.kernel.org/pu..
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=13470eb2a00000
> kernel config: https://syzkaller.appspot.com/x/.config?x=56f1da14935c3cce
> dashboard link: https://syzkaller.appspot.com/bug?extid=afabda3890cc2f765041
> compiler: gcc (GCC) 9.0.0 20181231 (experimental)
> syz repro: https://syzkaller.appspot.com/x/repro.syz?x=15100a91a00000
> C reproducer: https://syzkaller.appspot.com/x/repro.c?x=10c46026a00000
>
> IMPORTANT: if you fix the bug, please add the following tag to the commit:
> Reported-by: syzbot+afabda3890cc2f765041@syzkaller.appspotmail.com
>
> ffffffffda RBX: 00000000006fbc38 RCX: 0000000000446a79
> BUG: memory leak
> unreferenced object 0xffff888118137680 (size 1352):
> comm "syz-executor360", pid 7164, jiffies 4294941839 (age 13.960s)
> hex dump (first 32 bytes):
> ac 14 ff aa 0a 80 01 1a 00 00 00 00 00 00 00 00 ................
> 02 00 07 40 00 00 00 00 00 00 00 00 00 00 00 00 ...@............
> backtrace:
> [<000000006c358063>] kmemleak_alloc_recursive
> include/linux/kmemleak.h:43 [inline]
> [<000000006c358063>] slab_post_alloc_hook mm/slab.h:439 [inline]
> [<000000006c358063>] slab_alloc mm/slab.c:3326 [inline]
> [<000000006c358063>] kmem_cache_alloc+0x134/0x270 mm/slab.c:3488
> [<00000000f2fb26e7>] sk_prot_alloc+0x41/0x170 net/core/sock.c:1596
> [<000000003c036edc>] sk_alloc+0x35/0x2f0 net/core/sock.c:1656
> [<00000000c25725a4>] sctp_v4_create_accept_sk+0x32/0xb0
> net/sctp/protocol.c:556
> [<0000000049bd7e55>] sctp_accept+0x1df/0x290 net/sctp/socket.c:4913
> [<00000000d287a63e>] inet_accept+0x4e/0x1d0 net/ipv4/af_inet.c:734
> [<00000000acb0fc20>] __sys_accept4+0x12a/0x280 net/socket.c:1760
> [<00000000bbdaf60b>] __do_sys_accept4 net/socket.c:1795 [inline]
> [<00000000bbdaf60b>] __se_sys_accept4 net/socket.c:1792 [inline]
> [<00000000bbdaf60b>] __x64_sys_accept4+0x22/0x30 net/socket.c:1792
> [<000000006da547ee>] do_syscall_64+0x76/0x1a0
> arch/x86/entry/common.c:301
> [<00000000025f5c93>] entry_SYSCALL_64_after_hwframe+0x44/0xa9
The same issue as "memory leak in sctp_v6_create_accept_sk" one.
Fix:
diff --git a/net/sctp/endpointola.c b/net/sctp/endpointola.c
index e358437..69cebb2 100644
--- a/net/sctp/endpointola.c
+++ b/net/sctp/endpointola.c
@@ -118,10 +118,6 @@ static struct sctp_endpoint
*sctp_endpoint_init(struct sctp_endpoint *ep,
/* Initialize the bind addr area */
sctp_bind_addr_init(&ep->base.bind_addr, 0);
- /* Remember who we are attached to. */
- ep->base.sk = sk;
- sock_hold(ep->base.sk);
-
/* Create the lists of associations. */
INIT_LIST_HEAD(&ep->asocs);
@@ -154,6 +150,10 @@ static struct sctp_endpoint
*sctp_endpoint_init(struct sctp_endpoint *ep,
ep->prsctp_enable = net->sctp.prsctp_enable;
ep->reconf_enable = net->sctp.reconf_enable;
+ /* Remember who we are attached to. */
+ ep->base.sk = sk;
+ sock_hold(ep->base.sk);
+
return ep;
nomem_shkey:
>
>
>
> ---
> This bug is generated by a bot. It may contain errors.
> See https://goo.gl/tpsmEJ for more information about syzbot.
> syzbot engineers can be reached at syzkaller@googlegroups.com.
>
> syzbot will keep track of this bug report. See:
> https://goo.gl/tpsmEJ#status for how to communicate with syzbot.
> syzbot can test patches for this bug, for details see:
> https://goo.gl/tpsmEJ#testing-patches
^ permalink raw reply related
* Re: [PATCH v4 4/5] net: macb: add support for high speed interface
From: Andrew Lunn @ 2019-06-24 13:13 UTC (permalink / raw)
To: Parshuram Raju Thombare
Cc: nicolas.ferre@microchip.com, davem@davemloft.net,
f.fainelli@gmail.com, linux@armlinux.org.uk,
netdev@vger.kernel.org, hkallweit1@gmail.com,
linux-kernel@vger.kernel.org, Rafal Ciepiela, Anil Joy Varughese,
Piotr Sroka
In-Reply-To: <CO2PR07MB2469FDA06C3F8848290013B8C1E00@CO2PR07MB2469.namprd07.prod.outlook.com>
On Mon, Jun 24, 2019 at 06:52:51AM +0000, Parshuram Raju Thombare wrote:
> Hi Andrew,
>
> >> +enum {
> >> + MACB_SERDES_RATE_5_PT_15625Gbps = 5,
> >> + MACB_SERDES_RATE_10_PT_3125Gbps = 10,
> >> +};
> >What do the units mean here? Why would you clock the SERDES at 15Tbps,
> >or 3Tbps? 3.125Mbps would give you 2.5Gbps when using 8b/10b encoding.
> >
> MACB_SERDES_RATE_5_PT_15625Gbps is for 5.15625Gbps, I think this should be just
> MACB_SERDES_RATE_5_Gbps and MACB_SERDES_RATE_10_Gbps. I will do it in next patch set.
OK.
> >Xilinx documentation:
> >https://urldefense.proofpoint.com/v2/url?u=https-
> >3A__www.xilinx.com_support_documentation_ip-5Fdocumentation_usxgmii_v1-
> >5F1_pg251-
> >2Dusxgmii.pdf&d=DwIBAg&c=aUq983L2pue2FqKFoP6PGHMJQyoJ7kl3s3GZ-
> >_haXqY&r=GTefrem3hiBCnsjCOqAuapQHRN8-rKC1FRbk0it-
> >LDs&m=6V8fNIg49czRjfvVtDJ5BbR28p9UPlLLyB7fah7ypcw&s=LsDphgLBe1VDpM
> >_K9pkuyal873WeKqHDv64NDRUWy1Q&e=
> >seems to suggest USXGMII uses a fixed rate of 10.3125Gb/s. So why do
> >you need to change the rate?
> For USXGMII, Cadence MAC need to be correctly programmed for external serdes rate.
What i'm saying is that the USXGMII rate is fixed. So why do you need
a device tree property for the SERDES rate?
Andrew
^ permalink raw reply
* Re: WARNING: ODEBUG bug in netdev_freemem (2)
From: Thomas Gleixner @ 2019-06-24 13:18 UTC (permalink / raw)
To: Dmitry Vyukov
Cc: Eric Dumazet, syzbot, Alexander Duyck, amritha.nambiar,
Andy Shevchenko, David Miller, Dmitry Torokhov, Florian Fainelli,
Greg Kroah-Hartman, Ido Schimmel, LKML, netdev, syzkaller-bugs,
tyhicks, wanghai26, yuehaibing
In-Reply-To: <CACT4Y+bk1h+CFVdbbKau490Wjis8zt_ia8gVctGZ+bs=7qPk=Q@mail.gmail.com>
On Mon, 24 Jun 2019, Dmitry Vyukov wrote:
> On Mon, Jun 24, 2019 at 2:08 PM Eric Dumazet <eric.dumazet@gmail.com> wrote:
> > >>> ------------[ cut here ]------------
> > >>> ODEBUG: free active (active state 0) object type: timer_list hint:
> > >>> delayed_work_timer_fn+0x0/0x90 arch/x86/include/asm/paravirt.h:767
> > >>
> > >> One of the cleaned up devices has left an active timer which belongs to a
> > >> delayed work. That's all I can decode out of that splat. :(
> > >
> > > Hi Thomas,
> > >
> > > If ODEBUG would memorize full stack traces for object allocation
> > > (using lib/stackdepot.c), it would make this splat actionable, right?
> > > I've fixed https://bugzilla.kernel.org/show_bug.cgi?id=203969 for this.
> > >
> >
> > Not sure this would help in this case as some netdev are allocated through a generic helper.
> >
> > The driver specific portion might not show up in the stack trace.
> >
> > It would be nice here to get the work queue function pointer,
> > so that it gives us a clue which driver needs a fix.
Hrm. Let me think about a way to achieve that after I handled that
regression which is on my desk.
> I see. But isn't the workqueue callback is cleanup_net in this case
> and is in the stack?
>
> cleanup_net+0x3fb/0x960 net/core/net_namespace.c:553
> process_one_work+0x989/0x1790 kernel/workqueue.c:2269
That's the work which does the cleanup, but I doubt that this is part of
the offending net_device.
Thanks,
tglx
^ permalink raw reply
* RE: [PATCH net-next 6/6] net/mssc/ocelot: Add basic Felix switch driver
From: Claudiu Manoil @ 2019-06-24 13:19 UTC (permalink / raw)
To: Andrew Lunn
Cc: David S . Miller, devicetree@vger.kernel.org, Alexandre Belloni,
netdev@vger.kernel.org, Alexandru Marginean,
linux-kernel@vger.kernel.org, UNGLinuxDriver@microchip.com,
Allan Nielsen, Rob Herring, Catalin Horghidan,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190622205720.GK8497@lunn.ch>
>-----Original Message-----
>From: Andrew Lunn <andrew@lunn.ch>
>Sent: Saturday, June 22, 2019 11:57 PM
>To: Claudiu Manoil <claudiu.manoil@nxp.com>
[...]
Ok for all, I can work more on refactoring if we agree on the basics.
For instance I can change the driver to use reg-names, same as
mscc-ocelot, and factor out the common code.
So far my intention was to change the ocelot part as little as possible,
only where necessary.
Thanks,
Claudiu
^ permalink raw reply
* Re: [PATCH] wl18xx: Fix Wunused-const-variable
From: Kalle Valo @ 2019-06-24 13:22 UTC (permalink / raw)
To: Nathan Huckleberry
Cc: davem, linux-wireless, netdev, linux-kernel, Nathan Huckleberry,
clang-built-linux
In-Reply-To: <20190614171713.89262-1-nhuck@google.com>
Nathan Huckleberry <nhuck@google.com> wrote:
> Clang produces the following warning
>
> drivers/net/wireless/ti/wl18xx/main.c:1850:43: warning: unused variable
> 'wl18xx_iface_ap_cl_limits' [-Wunused-const-variable] static const struct
> ieee80211_iface_limit wl18xx_iface_ap_cl_limits[] = { ^
> drivers/net/wireless/ti/wl18xx/main.c:1869:43: warning: unused variable
> 'wl18xx_iface_ap_go_limits' [-Wunused-const-variable] static const struct
> ieee80211_iface_limit wl18xx_iface_ap_go_limits[] = { ^
>
> The commit that added these variables never used them. Removing them.
>
> Cc: clang-built-linux@googlegroups.com
> Link: https://github.com/ClangBuiltLinux/linux/issues/530
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Patch applied to wireless-drivers.git, thanks.
608fd7214323 wl18xx: Fix Wunused-const-variable
--
https://patchwork.kernel.org/patch/10996073/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: KASAN: slab-out-of-bounds Read in p54u_load_firmware_cb
From: Kalle Valo @ 2019-06-24 13:24 UTC (permalink / raw)
To: Andrey Konovalov
Cc: Christian Lamparter, Alan Stern, syzbot, Christian Lamparter,
David S. Miller, Kernel development list, USB list,
linux-wireless, netdev, syzkaller-bugs
In-Reply-To: <CAAeHK+zhcgmBQT=rdHaCMu7XWPz4o1gwzCJQEXiTEW9_iUUauA@mail.gmail.com>
Andrey Konovalov <andreyknvl@google.com> writes:
> On Thu, Jun 20, 2019 at 9:56 PM Christian Lamparter <chunkeey@gmail.com> wrote:
>>
>> On Thursday, June 20, 2019 9:46:32 PM CEST Alan Stern wrote:
>> > On Wed, 19 Jun 2019, syzbot wrote:
>> >
>> > > syzbot has found a reproducer for the following crash on:
>> > >
>> > > HEAD commit: 9939f56e usb-fuzzer: main usb gadget fuzzer driver
>> > > git tree: https://github.com/google/kasan.git usb-fuzzer
>> > > console output: https://syzkaller.appspot.com/x/log.txt?x=135e29faa00000
>> > > kernel config: https://syzkaller.appspot.com/x/.config?x=df134eda130bb43a
>> > > dashboard link: https://syzkaller.appspot.com/bug?extid=6d237e74cdc13f036473
>> > > compiler: gcc (GCC) 9.0.0 20181231 (experimental)
>> > > syz repro: https://syzkaller.appspot.com/x/repro.syz?x=175d946ea00000
>> > >
>> > > IMPORTANT: if you fix the bug, please add the following tag to the commit:
>> > > Reported-by: syzbot+6d237e74cdc13f036473@syzkaller.appspotmail.com
>> > >
>> > > usb 3-1: Direct firmware load for isl3887usb failed with error -2
>> > > usb 3-1: Firmware not found.
>> > > ==================================================================
>> > > BUG: KASAN: slab-out-of-bounds in p54u_load_firmware_cb.cold+0x97/0x13d
>> > > drivers/net/wireless/intersil/p54/p54usb.c:936
>> > > Read of size 8 at addr ffff8881c9cf7588 by task kworker/1:5/2759
>> > >
>> > > CPU: 1 PID: 2759 Comm: kworker/1:5 Not tainted 5.2.0-rc5+ #11
>> > > Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS
>> > > Google 01/01/2011
>> > > Workqueue: events request_firmware_work_func
>> > > Call Trace:
>> > > __dump_stack lib/dump_stack.c:77 [inline]
>> > > dump_stack+0xca/0x13e lib/dump_stack.c:113
>> > > print_address_description+0x67/0x231 mm/kasan/report.c:188
>> > > __kasan_report.cold+0x1a/0x32 mm/kasan/report.c:317
>> > > kasan_report+0xe/0x20 mm/kasan/common.c:614
>> > > p54u_load_firmware_cb.cold+0x97/0x13d
>> > > drivers/net/wireless/intersil/p54/p54usb.c:936
>> > > request_firmware_work_func+0x126/0x242
>> > > drivers/base/firmware_loader/main.c:785
>> > > process_one_work+0x905/0x1570 kernel/workqueue.c:2269
>> > > worker_thread+0x96/0xe20 kernel/workqueue.c:2415
>> > > kthread+0x30b/0x410 kernel/kthread.c:255
>> > > ret_from_fork+0x24/0x30 arch/x86/entry/entry_64.S:352
>> > >
>> > > Allocated by task 1612:
>> > > save_stack+0x1b/0x80 mm/kasan/common.c:71
>> > > set_track mm/kasan/common.c:79 [inline]
>> > > __kasan_kmalloc mm/kasan/common.c:489 [inline]
>> > > __kasan_kmalloc.constprop.0+0xbf/0xd0 mm/kasan/common.c:462
>> > > kmalloc include/linux/slab.h:547 [inline]
>> > > syslog_print kernel/printk/printk.c:1346 [inline]
>> > > do_syslog kernel/printk/printk.c:1519 [inline]
>> > > do_syslog+0x4f4/0x12e0 kernel/printk/printk.c:1493
>> > > kmsg_read+0x8a/0xb0 fs/proc/kmsg.c:40
>> > > proc_reg_read+0x1c1/0x280 fs/proc/inode.c:221
>> > > __vfs_read+0x76/0x100 fs/read_write.c:425
>> > > vfs_read+0x18e/0x3d0 fs/read_write.c:461
>> > > ksys_read+0x127/0x250 fs/read_write.c:587
>> > > do_syscall_64+0xb7/0x560 arch/x86/entry/common.c:301
>> > > entry_SYSCALL_64_after_hwframe+0x49/0xbe
>> > >
>> > > Freed by task 1612:
>> > > save_stack+0x1b/0x80 mm/kasan/common.c:71
>> > > set_track mm/kasan/common.c:79 [inline]
>> > > __kasan_slab_free+0x130/0x180 mm/kasan/common.c:451
>> > > slab_free_hook mm/slub.c:1421 [inline]
>> > > slab_free_freelist_hook mm/slub.c:1448 [inline]
>> > > slab_free mm/slub.c:2994 [inline]
>> > > kfree+0xd7/0x280 mm/slub.c:3949
>> > > syslog_print kernel/printk/printk.c:1405 [inline]
>> > > do_syslog kernel/printk/printk.c:1519 [inline]
>> > > do_syslog+0xff3/0x12e0 kernel/printk/printk.c:1493
>> > > kmsg_read+0x8a/0xb0 fs/proc/kmsg.c:40
>> > > proc_reg_read+0x1c1/0x280 fs/proc/inode.c:221
>> > > __vfs_read+0x76/0x100 fs/read_write.c:425
>> > > vfs_read+0x18e/0x3d0 fs/read_write.c:461
>> > > ksys_read+0x127/0x250 fs/read_write.c:587
>> > > do_syscall_64+0xb7/0x560 arch/x86/entry/common.c:301
>> > > entry_SYSCALL_64_after_hwframe+0x49/0xbe
>> > >
>> > > The buggy address belongs to the object at ffff8881c9cf7180
>> > > which belongs to the cache kmalloc-1k of size 1024
>> > > The buggy address is located 8 bytes to the right of
>> > > 1024-byte region [ffff8881c9cf7180, ffff8881c9cf7580)
>> > > The buggy address belongs to the page:
>> > > page:ffffea0007273d00 refcount:1 mapcount:0 mapping:ffff8881dac02a00
>> > > index:0x0 compound_mapcount: 0
>> > > flags: 0x200000000010200(slab|head)
>> > > raw: 0200000000010200 dead000000000100 dead000000000200 ffff8881dac02a00
>> > > raw: 0000000000000000 00000000000e000e 00000001ffffffff 0000000000000000
>> > > page dumped because: kasan: bad access detected
>> > >
>> > > Memory state around the buggy address:
>> > > ffff8881c9cf7480: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
>> > > ffff8881c9cf7500: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
>> > > > ffff8881c9cf7580: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
>> > > ^
>> > > ffff8881c9cf7600: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
>> > > ffff8881c9cf7680: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
>> > > ==================================================================
>> >
>> > Isn't this the same as syzkaller bug 200d4bb11b23d929335f ? Doesn't
>> > the same patch fix it?
>> >
>> I think Kalle hasn't applied it yet? It's still sitting on the patchwork queue:
>> <https://patchwork.kernel.org/patch/10951527/>
>
> Yes, until this patch is in the tree that is being tested (which is
> based on the usb-linus branch; I update it every few weeks), syzbot
> considers this bug as open.
I'm hoping to apply this today or tomorrow.
--
Kalle Valo
^ permalink raw reply
* Re: [PATCH rdma-next v1 08/12] IB/mlx5: Introduce MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD
From: Yishai Hadas @ 2019-06-24 13:25 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Doug Ledford, Leon Romanovsky, RDMA mailing list, Yishai Hadas,
Saeed Mahameed, linux-netdev
In-Reply-To: <20190624115059.GA5479@mellanox.com>
On 6/24/2019 2:51 PM, Jason Gunthorpe wrote:
> On Tue, Jun 18, 2019 at 08:15:36PM +0300, Leon Romanovsky wrote:
>> From: Yishai Hadas <yishaih@mellanox.com>
>>
>> Introduce MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD and its initial
>> implementation.
>>
>> This object is from type class FD and will be used to read DEVX
>> async events.
>>
>> Signed-off-by: Yishai Hadas <yishaih@mellanox.com>
>> Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
>> drivers/infiniband/hw/mlx5/devx.c | 112 ++++++++++++++++++++--
>> include/uapi/rdma/mlx5_user_ioctl_cmds.h | 10 ++
>> include/uapi/rdma/mlx5_user_ioctl_verbs.h | 4 +
>> 3 files changed, 116 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/infiniband/hw/mlx5/devx.c b/drivers/infiniband/hw/mlx5/devx.c
>> index 80b42d069328..1815ce0f8daf 100644
>> +++ b/drivers/infiniband/hw/mlx5/devx.c
>> @@ -33,6 +33,24 @@ struct devx_async_data {
>> struct mlx5_ib_uapi_devx_async_cmd_hdr hdr;
>> };
>>
>> +struct devx_async_event_queue {
>
> It seems to be a mistake to try and re-use the async_event_queue for
> both cmd and event, as they use it very differently and don't even
> store the same things in the event_list. I think it is bettter to just
> inline this into devx_async_event_file (and inline the old struct in
> the cmd file
>
How about having another struct with all the event's queue fields
together ? this has the benefit of having all those related fields in
one place and leave the cmd as is.
Alternatively,
We can inline the event stuff under devx_async_event_file and leave the
cmd for now under a struct as it's not directly related to this series.
What do you think ?
>> + spinlock_t lock;
>> + wait_queue_head_t poll_wait;
>> + struct list_head event_list;
>> + atomic_t bytes_in_use;
>> + u8 is_destroyed:1;
>> + u32 flags;
>> +};
>
> All the flags testing is ugly, why not just add another bitfield?
The flags are coming from user space and have their different name
space, I prefer to not mix with kernel ones. (i.e. is_destroyed).
Makes sense ?
>
>> +
>> +struct devx_async_event_file {
>> + struct ib_uobject uobj;
>> + struct list_head subscribed_events_list; /* Head of events that are
>> + * subscribed to this FD
>> + */
>> + struct devx_async_event_queue ev_queue;
>> + struct mlx5_ib_dev *dev;
>> +};
>> +
>
> Crazy indenting
>
OK, will handle.
>> diff --git a/include/uapi/rdma/mlx5_user_ioctl_verbs.h b/include/uapi/rdma/mlx5_user_ioctl_verbs.h
>> index a8f34c237458..57beea4589e4 100644
>> +++ b/include/uapi/rdma/mlx5_user_ioctl_verbs.h
>> @@ -63,5 +63,9 @@ enum mlx5_ib_uapi_dm_type {
>> MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM,
>> };
>>
>> +enum mlx5_ib_uapi_devx_create_event_channel_flags {
>> + MLX5_IB_UAPI_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA = 1
>> << 0,
>
> Maybe this name is too long
Quite long but follows the name scheme having the UAPI prefix.
Any shorter suggestion ?
^ permalink raw reply
* [PATCH net-next] ipv4: enable route flushing in network namespaces
From: Christian Brauner @ 2019-06-24 13:29 UTC (permalink / raw)
To: davem, kuznet, yoshfuji, netdev; +Cc: linux-kernel, Christian Brauner
Tools such as vpnc try to flush routes when run inside network
namespaces by writing 1 into /proc/sys/net/ipv4/route/flush. This
currently does not work because flush is not enabled in non-initial
network namespaces.
Since routes are per network namespace it is safe to enable
/proc/sys/net/ipv4/route/flush in there.
Link: https://github.com/lxc/lxd/issues/4257
Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com>
---
net/ipv4/route.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/net/ipv4/route.c b/net/ipv4/route.c
index 6cb7cff22db9..41726e26cd5f 100644
--- a/net/ipv4/route.c
+++ b/net/ipv4/route.c
@@ -3197,9 +3197,11 @@ static struct ctl_table ipv4_route_table[] = {
{ }
};
+static const char ipv4_route_flush_procname[] = "flush";
+
static struct ctl_table ipv4_route_flush_table[] = {
{
- .procname = "flush",
+ .procname = ipv4_route_flush_procname,
.maxlen = sizeof(int),
.mode = 0200,
.proc_handler = ipv4_sysctl_rtcache_flush,
@@ -3217,9 +3219,11 @@ static __net_init int sysctl_route_net_init(struct net *net)
if (!tbl)
goto err_dup;
- /* Don't export sysctls to unprivileged users */
- if (net->user_ns != &init_user_ns)
- tbl[0].procname = NULL;
+ /* Don't export non-whitelisted sysctls to unprivileged users */
+ if (net->user_ns != &init_user_ns) {
+ if (tbl[0].procname != ipv4_route_flush_procname)
+ tbl[0].procname = NULL;
+ }
}
tbl[0].extra1 = net;
--
2.22.0
^ permalink raw reply related
* Re: [PATCH rdma-next v1 09/12] IB/mlx5: Register DEVX with mlx5_core to get async events
From: Yishai Hadas @ 2019-06-24 13:36 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Leon Romanovsky, Doug Ledford, Leon Romanovsky, RDMA mailing list,
Yishai Hadas, Saeed Mahameed, linux-netdev
In-Reply-To: <20190624115206.GB5479@mellanox.com>
On 6/24/2019 2:52 PM, Jason Gunthorpe wrote:
> On Tue, Jun 18, 2019 at 08:15:37PM +0300, Leon Romanovsky wrote:
>> void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
>> diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h
>> index 9cf23ae6324e..556af34b788b 100644
>> +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h
>> @@ -944,6 +944,13 @@ struct mlx5_ib_pf_eq {
>> mempool_t *pool;
>> };
>>
>> +struct mlx5_devx_event_table {
>> + struct mlx5_nb devx_nb;
>> + /* serialize updating the event_xa */
>> + struct mutex event_xa_lock;
>> + struct xarray event_xa;
>> +};
>> +
>> struct mlx5_ib_dev {
>> struct ib_device ib_dev;
>> struct mlx5_core_dev *mdev;
>> @@ -994,6 +1001,7 @@ struct mlx5_ib_dev {
>> struct mlx5_srq_table srq_table;
>> struct mlx5_async_ctx async_ctx;
>> int free_port;
>> + struct mlx5_devx_event_table devx_event_table;
>
> I really question if adding all these structs really does anything for
> readability..
>
I would prefer this option to add only one structure (i.e.
mlx5_devx_event_table) on ib_dev, it will hold internally the other
related stuff.
^ permalink raw reply
* Re: [PATCH v5 2/5] net: macb: add support for sgmii MAC-PHY interface
From: Russell King - ARM Linux admin @ 2019-06-24 13:42 UTC (permalink / raw)
To: Parshuram Thombare
Cc: andrew, nicolas.ferre, davem, f.fainelli, netdev, hkallweit1,
linux-kernel, rafalc, aniljoy, piotrs
In-Reply-To: <1561378274-12357-1-git-send-email-pthombar@cadence.com>
On Mon, Jun 24, 2019 at 01:11:14PM +0100, Parshuram Thombare wrote:
> This patch add support for SGMII interface) and
> 2.5Gbps MAC in Cadence ethernet controller driver.
>
> Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
> ---
> drivers/net/ethernet/cadence/macb.h | 54 +++++++++++++-----
> drivers/net/ethernet/cadence/macb_main.c | 72 ++++++++++++++++++++++--
> 2 files changed, 109 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 8629d345af31..6d268283c318 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -77,6 +77,7 @@
> #define MACB_RBQPH 0x04D4
>
> /* GEM register offsets. */
> +#define GEM_NCR 0x0000 /* Network Control */
> #define GEM_NCFGR 0x0004 /* Network Config */
> #define GEM_USRIO 0x000c /* User IO */
> #define GEM_DMACFG 0x0010 /* DMA Configuration */
> @@ -156,6 +157,7 @@
> #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
> #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
> #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
> +#define GEM_PCS_CTRL 0x0200 /* PCS Control */
> #define GEM_DCFG1 0x0280 /* Design Config 1 */
> #define GEM_DCFG2 0x0284 /* Design Config 2 */
> #define GEM_DCFG3 0x0288 /* Design Config 3 */
> @@ -271,6 +273,10 @@
> #define MACB_IRXFCS_OFFSET 19
> #define MACB_IRXFCS_SIZE 1
>
> +/* GEM specific NCR bitfields. */
> +#define GEM_TWO_PT_FIVE_GIG_OFFSET 29
> +#define GEM_TWO_PT_FIVE_GIG_SIZE 1
> +
> /* GEM specific NCFGR bitfields. */
> #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
> #define GEM_GBE_SIZE 1
> @@ -323,6 +329,9 @@
> #define MACB_MDIO_SIZE 1
> #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
> #define MACB_IDLE_SIZE 1
> +#define MACB_DUPLEX_OFFSET 3
> +#define MACB_DUPLEX_SIZE 1
> +
>
> /* Bitfields in TSR */
> #define MACB_UBR_OFFSET 0 /* Used bit read */
> @@ -456,11 +465,17 @@
> #define MACB_REV_OFFSET 0
> #define MACB_REV_SIZE 16
>
> +/* Bitfields in PCS_CONTROL. */
> +#define GEM_PCS_CTRL_RST_OFFSET 15
> +#define GEM_PCS_CTRL_RST_SIZE 1
> +
> /* Bitfields in DCFG1. */
> #define GEM_IRQCOR_OFFSET 23
> #define GEM_IRQCOR_SIZE 1
> #define GEM_DBWDEF_OFFSET 25
> #define GEM_DBWDEF_SIZE 3
> +#define GEM_NO_PCS_OFFSET 0
> +#define GEM_NO_PCS_SIZE 1
>
> /* Bitfields in DCFG2. */
> #define GEM_RX_PKT_BUFF_OFFSET 20
> @@ -633,19 +648,32 @@
> #define MACB_MAN_CODE 2
>
> /* Capability mask bits */
> -#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
> -#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
> -#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
> -#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
> -#define MACB_CAPS_USRIO_DISABLED 0x00000010
> -#define MACB_CAPS_JUMBO 0x00000020
> -#define MACB_CAPS_GEM_HAS_PTP 0x00000040
> -#define MACB_CAPS_BD_RD_PREFETCH 0x00000080
> -#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
> -#define MACB_CAPS_FIFO_MODE 0x10000000
> -#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
> -#define MACB_CAPS_SG_DISABLED 0x40000000
> -#define MACB_CAPS_MACB_IS_GEM 0x80000000
> +#define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0)
> +#define MACB_CAPS_USRIO_HAS_CLKEN BIT(1)
> +#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII BIT(2)
> +#define MACB_CAPS_NO_GIGABIT_HALF BIT(3)
> +#define MACB_CAPS_USRIO_DISABLED BIT(4)
> +#define MACB_CAPS_JUMBO BIT(5)
> +#define MACB_CAPS_GEM_HAS_PTP BIT(6)
> +#define MACB_CAPS_BD_RD_PREFETCH BIT(7)
> +#define MACB_CAPS_NEEDS_RSTONUBR BIT(8)
> +#define MACB_CAPS_FIFO_MODE BIT(28)
> +#define MACB_CAPS_GIGABIT_MODE_AVAILABLE BIT(29)
> +#define MACB_CAPS_SG_DISABLED BIT(30)
> +#define MACB_CAPS_MACB_IS_GEM BIT(31)
> +#define MACB_CAPS_PCS BIT(24)
> +#define MACB_CAPS_MACB_IS_GEM_GXL BIT(25)
> +
> +#define MACB_GEM7010_IDNUM 0x009
> +#define MACB_GEM7014_IDNU 0x107
> +#define MACB_GEM7014A_IDNUM 0x207
> +#define MACB_GEM7016_IDNUM 0x10a
> +#define MACB_GEM7017_IDNUM 0x00a
> +#define MACB_GEM7017A_IDNUM 0x20a
> +#define MACB_GEM7020_IDNUM 0x003
> +#define MACB_GEM7021_IDNUM 0x00c
> +#define MACB_GEM7021A_IDNUM 0x20c
> +#define MACB_GEM7022_IDNUM 0x00b
>
> /* LSO settings */
> #define MACB_LSO_UFO_ENABLE 0x01
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index ac5b233cd2e5..572691d948e9 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -445,6 +445,8 @@ static void gem_phylink_validate(struct phylink_config *pl_config,
> __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
>
> switch (state->interface) {
> + case PHY_INTERFACE_MODE_NA:
> + case PHY_INTERFACE_MODE_SGMII:
> case PHY_INTERFACE_MODE_GMII:
> case PHY_INTERFACE_MODE_RGMII:
> if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) {
> @@ -480,10 +482,31 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
> {
> struct net_device *netdev = to_net_dev(pl_config->dev);
> struct macb *bp = netdev_priv(netdev);
> + bool change_interface = bp->phy_interface != state->interface;
> unsigned long flags;
>
> spin_lock_irqsave(&bp->lock, flags);
>
> + if (change_interface) {
> + bp->phy_interface = state->interface;
> + gem_writel(bp, NCR, ~GEM_BIT(TWO_PT_FIVE_GIG) &
> + gem_readl(bp, NCR));
This could do with a comment, such as the one I gave in my example.
> +
> + if (state->interface == PHY_INTERFACE_MODE_SGMII) {
> + gem_writel(bp, NCFGR, GEM_BIT(SGMIIEN) |
> + GEM_BIT(PCSSEL) |
> + gem_readl(bp, NCFGR));
> + } else {
> + /* Disable SGMII mode and PCS */
> + gem_writel(bp, NCFGR, ~(GEM_BIT(SGMIIEN) |
> + GEM_BIT(PCSSEL)) &
> + gem_readl(bp, NCFGR));
> + /* Reset PCS */
> + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) |
> + GEM_BIT(PCS_CTRL_RST));
> + }
> + }
Good.
> +
> if (!phylink_autoneg_inband(mode) &&
> (bp->speed != state->speed ||
> bp->duplex != state->duplex)) {
> @@ -493,6 +516,7 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
> reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
> if (macb_is_gem(bp))
> reg &= ~GEM_BIT(GBE);
> +
Useless change.
> if (state->duplex)
> reg |= MACB_BIT(FD);
>
> @@ -587,8 +611,8 @@ static int macb_mii_probe(struct net_device *dev)
> }
>
> bp->link = 0;
> - bp->speed = 0;
> - bp->duplex = -1;
> + bp->speed = SPEED_UNKNOWN;
> + bp->duplex = DUPLEX_UNKNOWN;
>
> return ret;
> }
> @@ -3337,6 +3361,22 @@ static void macb_configure_caps(struct macb *bp,
> dcfg = gem_readl(bp, DCFG1);
> if (GEM_BFEXT(IRQCOR, dcfg) == 0)
> bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
> + if (GEM_BFEXT(NO_PCS, dcfg) == 0)
> + bp->caps |= MACB_CAPS_PCS;
> + switch (MACB_BFEXT(IDNUM, macb_readl(bp, MID))) {
> + case MACB_GEM7016_IDNUM:
> + case MACB_GEM7017_IDNUM:
> + case MACB_GEM7017A_IDNUM:
> + case MACB_GEM7020_IDNUM:
> + case MACB_GEM7021_IDNUM:
> + case MACB_GEM7021A_IDNUM:
> + case MACB_GEM7022_IDNUM:
> + bp->caps |= MACB_CAPS_USRIO_DISABLED;
> + bp->caps |= MACB_CAPS_MACB_IS_GEM_GXL;
> + break;
> + default:
> + break;
> + }
> dcfg = gem_readl(bp, DCFG2);
> if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
> bp->caps |= MACB_CAPS_FIFO_MODE;
> @@ -4319,11 +4359,35 @@ static int macb_probe(struct platform_device *pdev)
> }
>
> phy_mode = of_get_phy_mode(np);
> - if (phy_mode < 0)
> + if (phy_mode < 0) {
> /* not found in DT, MII by default */
> bp->phy_interface = PHY_INTERFACE_MODE_MII;
> - else
> + } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) {
> + u32 interface_supported = 1;
> +
> + if (phy_mode == PHY_INTERFACE_MODE_SGMII) {
> + if (!(bp->caps & MACB_CAPS_PCS))
> + interface_supported = 0;
So if bp->caps does not have MACB_CAPS_PCS set, then SGMII mode is not
supported?
In which case, gem_phylink_validate() must clear the support mask when
SGMII mode is requested to indicate that the interface mode is not
supported.
The same goes for _all_ other PHY link modes that the hardware does not
actually support, such as PHY_INTERFACE_MODE_10GKR...
> + } else if (phy_mode == PHY_INTERFACE_MODE_GMII ||
> + phy_mode == PHY_INTERFACE_MODE_RGMII) {
> + if (!macb_is_gem(bp))
> + interface_supported = 0;
> + } else if (phy_mode != PHY_INTERFACE_MODE_RMII &&
> + phy_mode != PHY_INTERFACE_MODE_MII) {
> + /* Add new mode before this */
> + interface_supported = 0;
> + }
... and the same goes for these too.
> +
> + if (!interface_supported) {
> + netdev_err(dev, "Phy mode %s not supported",
> + phy_modes(phy_mode));
> + goto err_out_free_netdev;
> + }
> +
> + bp->phy_interface = phy_mode;
> + } else {
> bp->phy_interface = phy_mode;
> + }
>
> /* IP specific init */
> err = init(pdev);
> --
> 2.17.1
>
>
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
^ permalink raw reply
* Re: [PATCH v5 4/5] net: macb: add support for high speed interface
From: Russell King - ARM Linux admin @ 2019-06-24 13:47 UTC (permalink / raw)
To: Parshuram Thombare
Cc: andrew, nicolas.ferre, davem, f.fainelli, netdev, hkallweit1,
linux-kernel, rafalc, aniljoy, piotrs
In-Reply-To: <1561378355-14048-1-git-send-email-pthombar@cadence.com>
On Mon, Jun 24, 2019 at 01:12:35PM +0100, Parshuram Thombare wrote:
> This patch add support for high speed USXGMII PCS and 10G
> speed in Cadence ethernet controller driver.
>
> Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
> ---
> drivers/net/ethernet/cadence/macb.h | 41 +++++
> drivers/net/ethernet/cadence/macb_main.c | 189 ++++++++++++++++++++---
> 2 files changed, 207 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index 330da702b946..809acff19be9 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -82,6 +82,7 @@
> #define GEM_USRIO 0x000c /* User IO */
> #define GEM_DMACFG 0x0010 /* DMA Configuration */
> #define GEM_JML 0x0048 /* Jumbo Max Length */
> +#define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
> #define GEM_HRB 0x0080 /* Hash Bottom */
> #define GEM_HRT 0x0084 /* Hash Top */
> #define GEM_SA1B 0x0088 /* Specific1 Bottom */
> @@ -167,6 +168,9 @@
> #define GEM_DCFG7 0x0298 /* Design Config 7 */
> #define GEM_DCFG8 0x029C /* Design Config 8 */
> #define GEM_DCFG10 0x02A4 /* Design Config 10 */
> +#define GEM_DCFG12 0x02AC /* Design Config 12 */
> +#define GEM_USX_CONTROL 0x0A80 /* USXGMII control register */
> +#define GEM_USX_STATUS 0x0A88 /* USXGMII status register */
>
> #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
> #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
> @@ -274,6 +278,8 @@
> #define MACB_IRXFCS_SIZE 1
>
> /* GEM specific NCR bitfields. */
> +#define GEM_ENABLE_HS_MAC_OFFSET 31
> +#define GEM_ENABLE_HS_MAC_SIZE 1
> #define GEM_TWO_PT_FIVE_GIG_OFFSET 29
> #define GEM_TWO_PT_FIVE_GIG_SIZE 1
>
> @@ -465,6 +471,10 @@
> #define MACB_REV_OFFSET 0
> #define MACB_REV_SIZE 16
>
> +/* Bitfield in HS_MAC_CONFIG */
> +#define GEM_HS_MAC_SPEED_OFFSET 0
> +#define GEM_HS_MAC_SPEED_SIZE 3
> +
> /* Bitfields in PCS_CONTROL. */
> #define GEM_PCS_CTRL_RST_OFFSET 15
> #define GEM_PCS_CTRL_RST_SIZE 1
> @@ -510,6 +520,34 @@
> #define GEM_RXBD_RDBUFF_OFFSET 8
> #define GEM_RXBD_RDBUFF_SIZE 4
>
> +/* Bitfields in DCFG12. */
> +#define GEM_HIGH_SPEED_OFFSET 26
> +#define GEM_HIGH_SPEED_SIZE 1
> +
> +/* Bitfields in USX_CONTROL. */
> +#define GEM_USX_CTRL_SPEED_OFFSET 14
> +#define GEM_USX_CTRL_SPEED_SIZE 3
> +#define GEM_SERDES_RATE_OFFSET 12
> +#define GEM_SERDES_RATE_SIZE 2
> +#define GEM_RX_SCR_BYPASS_OFFSET 9
> +#define GEM_RX_SCR_BYPASS_SIZE 1
> +#define GEM_TX_SCR_BYPASS_OFFSET 8
> +#define GEM_TX_SCR_BYPASS_SIZE 1
> +#define GEM_RX_SYNC_RESET_OFFSET 2
> +#define GEM_RX_SYNC_RESET_SIZE 1
> +#define GEM_TX_EN_OFFSET 1
> +#define GEM_TX_EN_SIZE 1
> +#define GEM_SIGNAL_OK_OFFSET 0
> +#define GEM_SIGNAL_OK_SIZE 1
> +
> +/* Bitfields in USX_STATUS. */
> +#define GEM_USX_TX_FAULT_OFFSET 28
> +#define GEM_USX_TX_FAULT_SIZE 1
> +#define GEM_USX_RX_FAULT_OFFSET 27
> +#define GEM_USX_RX_FAULT_SIZE 1
> +#define GEM_USX_BLOCK_LOCK_OFFSET 0
> +#define GEM_USX_BLOCK_LOCK_SIZE 1
> +
> /* Bitfields in TISUBN */
> #define GEM_SUBNSINCR_OFFSET 0
> #define GEM_SUBNSINCR_SIZE 16
> @@ -670,6 +708,7 @@
> #define MACB_CAPS_MACB_IS_GEM BIT(31)
> #define MACB_CAPS_PCS BIT(24)
> #define MACB_CAPS_MACB_IS_GEM_GXL BIT(25)
> +#define MACB_CAPS_HIGH_SPEED BIT(26)
>
> #define MACB_GEM7010_IDNUM 0x009
> #define MACB_GEM7014_IDNU 0x107
> @@ -749,6 +788,7 @@
> })
>
> #define MACB_READ_NSR(bp) macb_readl(bp, NSR)
> +#define GEM_READ_USX_STATUS(bp) gem_readl(bp, USX_STATUS)
>
> /* struct macb_dma_desc - Hardware DMA descriptor
> * @addr: DMA address of data buffer
> @@ -1262,6 +1302,7 @@ struct macb {
> struct macb_pm_data pm_data;
> struct phylink *pl;
> struct phylink_config pl_config;
> + u32 serdes_rate;
> };
>
> #ifdef CONFIG_MACB_USE_HWSTAMP
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index 1323f9b4d3b8..5afc03299bee 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -84,6 +84,20 @@ static struct sifive_fu540_macb_mgmt *mgmt;
> #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
> #define MACB_WOL_ENABLED (0x1 << 1)
>
> +enum {
> + HS_MAC_SPEED_100M,
> + HS_MAC_SPEED_1000M,
> + HS_MAC_SPEED_2500M,
> + HS_MAC_SPEED_5000M,
> + HS_MAC_SPEED_10000M,
> + HS_MAC_SPEED_25000M,
> +};
> +
> +enum {
> + MACB_SERDES_RATE_5Gbps = 5,
> + MACB_SERDES_RATE_10Gbps = 10,
> +};
> +
> /* Graceful stop timeouts in us. We should allow up to
> * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
> */
> @@ -93,6 +107,8 @@ static struct sifive_fu540_macb_mgmt *mgmt;
>
> #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
>
> +#define MACB_USX_BLOCK_LOCK_TIMEOUT 1000000 /* in usecs */
> +
> /* DMA buffer descriptor might be different size
> * depends on hardware configuration:
> *
> @@ -439,23 +455,37 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
> */
> static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
> {
> + struct macb *bp = netdev_priv(dev);
> long ferr, rate, rate_rounded;
>
> if (!clk)
> return;
>
> - switch (speed) {
> - case SPEED_10:
> - rate = 2500000;
> - break;
> - case SPEED_100:
> - rate = 25000000;
> - break;
> - case SPEED_1000:
> - rate = 125000000;
> - break;
> - default:
> - return;
> + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
> + switch (bp->serdes_rate) {
> + case MACB_SERDES_RATE_5Gbps:
> + rate = 78125000;
> + break;
> + case MACB_SERDES_RATE_10Gbps:
> + rate = 156250000;
> + break;
> + default:
> + return;
> + }
> + } else {
> + switch (speed) {
> + case SPEED_10:
> + rate = 2500000;
> + break;
> + case SPEED_100:
> + rate = 25000000;
> + break;
> + case SPEED_1000:
> + rate = 125000000;
> + break;
> + default:
> + return;
> + }
> }
>
> rate_rounded = clk_round_rate(clk, rate);
> @@ -485,6 +515,21 @@ static void gem_phylink_validate(struct phylink_config *pl_config,
>
> switch (state->interface) {
> case PHY_INTERFACE_MODE_NA:
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_10GKR:
> + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) {
> + phylink_set(mask, 10000baseCR_Full);
> + phylink_set(mask, 10000baseER_Full);
> + phylink_set(mask, 10000baseKR_Full);
> + phylink_set(mask, 10000baseLR_Full);
> + phylink_set(mask, 10000baseLRM_Full);
> + phylink_set(mask, 10000baseSR_Full);
> + phylink_set(mask, 10000baseT_Full);
> + phylink_set(mask, 5000baseT_Full);
> + phylink_set(mask, 2500baseX_Full);
> + phylink_set(mask, 1000baseX_Full);
> + }
If MACB_CAPS_GIGABIT_MODE_AVAILABLE is not set, are these interface
modes supported by the hardware? If the PHY interface mode is not
supported, then the returned support mask must be cleared.
> + /* fallthrough */
> case PHY_INTERFACE_MODE_SGMII:
> case PHY_INTERFACE_MODE_GMII:
> case PHY_INTERFACE_MODE_RGMII:
> @@ -516,6 +561,91 @@ static int gem_phylink_mac_link_state(struct phylink_config *pl_config,
> return -EOPNOTSUPP;
> }
>
> +static int macb_wait_for_usx_block_lock(struct macb *bp)
> +{
> + u32 val;
> +
> + return readx_poll_timeout(GEM_READ_USX_STATUS, bp, val,
> + val & GEM_BIT(USX_BLOCK_LOCK),
> + 1, MACB_USX_BLOCK_LOCK_TIMEOUT);
> +}
> +
> +static inline int gem_mac_usx_configure(struct macb *bp, int spd)
> +{
> + u32 speed, config;
> +
> + gem_writel(bp, NCFGR, GEM_BIT(PCSSEL) |
> + (~GEM_BIT(SGMIIEN) & gem_readl(bp, NCFGR)));
> + gem_writel(bp, NCR, gem_readl(bp, NCR) |
> + GEM_BIT(ENABLE_HS_MAC));
> + gem_writel(bp, NCFGR, gem_readl(bp, NCFGR) |
> + MACB_BIT(FD));
> + config = gem_readl(bp, USX_CONTROL);
> + config = GEM_BFINS(SERDES_RATE, bp->serdes_rate, config);
> + config &= ~GEM_BIT(TX_SCR_BYPASS);
> + config &= ~GEM_BIT(RX_SCR_BYPASS);
> + gem_writel(bp, USX_CONTROL, config |
> + GEM_BIT(TX_EN));
> + config = gem_readl(bp, USX_CONTROL);
> + gem_writel(bp, USX_CONTROL, config | GEM_BIT(SIGNAL_OK));
> + if (macb_wait_for_usx_block_lock(bp) < 0) {
> + netdev_warn(bp->dev, "USXGMII block lock failed");
> + return -ETIMEDOUT;
> + }
> +
> + switch (spd) {
> + case SPEED_10000:
> + if (bp->serdes_rate >= MACB_SERDES_RATE_10Gbps) {
> + speed = HS_MAC_SPEED_10000M;
> + } else {
> + netdev_warn(bp->dev, "10G speed isn't supported by HW");
> + netdev_warn(bp->dev, "Setting speed to 1G");
> + speed = HS_MAC_SPEED_1000M;
> + }
> + break;
> + case SPEED_5000:
> + speed = HS_MAC_SPEED_5000M;
> + break;
> + case SPEED_2500:
> + speed = HS_MAC_SPEED_2500M;
> + break;
> + case SPEED_1000:
> + speed = HS_MAC_SPEED_1000M;
> + break;
> + default:
> + case SPEED_100:
> + speed = HS_MAC_SPEED_100M;
> + break;
> + }
> +
> + gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, speed,
> + gem_readl(bp, HS_MAC_CONFIG)));
> + gem_writel(bp, USX_CONTROL, GEM_BFINS(USX_CTRL_SPEED, speed,
> + gem_readl(bp, USX_CONTROL)));
> + return 0;
> +}
> +
> +static inline void gem_mac_configure(struct macb *bp, int speed)
> +{
> + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
> + gem_writel(bp, NCFGR, GEM_BIT(SGMIIEN) |
> + GEM_BIT(PCSSEL) |
> + gem_readl(bp, NCFGR));
Is this still necessary?
> +
> + switch (speed) {
> + case SPEED_1000:
> + gem_writel(bp, NCFGR, GEM_BIT(GBE) |
> + gem_readl(bp, NCFGR));
> + break;
> + case SPEED_100:
> + macb_writel(bp, NCFGR, MACB_BIT(SPD) |
> + macb_readl(bp, NCFGR));
What happens to the NCFGR register if we call mac_config() first for
a 1G speed, then 100M and finally 10M - what value does the NCFGR
register end up with?
I suspect it ends up with both the GBE and SPD bits set, and that is
probably not what you want.
> + break;
> + default:
> + break;
> + }
> +}
> +
> static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
> const struct phylink_link_state *state)
> {
> @@ -558,18 +688,17 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode,
>
> if (state->duplex)
> reg |= MACB_BIT(FD);
> + macb_or_gem_writel(bp, NCFGR, reg);
>
> - switch (state->speed) {
> - case SPEED_1000:
> - reg |= GEM_BIT(GBE);
> - break;
> - case SPEED_100:
> - reg |= MACB_BIT(SPD);
> - break;
> - default:
> - break;
> + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) {
> + if (gem_mac_usx_configure(bp, state->speed) < 0) {
> + spin_unlock_irqrestore(&bp->lock, flags);
> + phylink_mac_change(bp->pl, false);
> + return;
> + }
> + } else {
> + gem_mac_configure(bp, state->speed);
> }
> - macb_or_gem_writel(bp, NCFGR, reg);
>
> bp->speed = state->speed;
> bp->duplex = state->duplex;
> @@ -3416,6 +3545,9 @@ static void macb_configure_caps(struct macb *bp,
> default:
> break;
> }
> + dcfg = gem_readl(bp, DCFG12);
> + if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
> + bp->caps |= MACB_CAPS_HIGH_SPEED;
> dcfg = gem_readl(bp, DCFG2);
> if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
> bp->caps |= MACB_CAPS_FIFO_MODE;
> @@ -4404,7 +4536,18 @@ static int macb_probe(struct platform_device *pdev)
> } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) {
> u32 interface_supported = 1;
>
> - if (phy_mode == PHY_INTERFACE_MODE_SGMII) {
> + if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
> + if (!(bp->caps & MACB_CAPS_HIGH_SPEED &&
> + bp->caps & MACB_CAPS_PCS))
> + interface_supported = 0;
> +
> + if (of_property_read_u32(np, "serdes-rate-gbps",
> + &bp->serdes_rate)) {
> + netdev_err(dev,
> + "GEM serdes_rate not specified");
> + interface_supported = 0;
> + }
> + } else if (phy_mode == PHY_INTERFACE_MODE_SGMII) {
> if (!(bp->caps & MACB_CAPS_PCS))
> interface_supported = 0;
> } else if (phy_mode == PHY_INTERFACE_MODE_GMII ||
> --
> 2.17.1
>
>
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
^ permalink raw reply
* Re: [PATCH] flow_dissector: Fix vlan header offset in __skb_flow_dissect
From: Jiri Pirko @ 2019-06-24 13:50 UTC (permalink / raw)
To: Stanislav Fomichev
Cc: Yuehaibing, davem, sdf, jianbol, jiri, mirq-linux, willemb,
linux-kernel, netdev
In-Reply-To: <20190621003317.GE1383@mini-arch>
Fri, Jun 21, 2019 at 02:33:17AM CEST, sdf@fomichev.me wrote:
>On 06/20, Yuehaibing wrote:
>> On 2019/6/20 2:39, Stanislav Fomichev wrote:
>> > On 06/20, YueHaibing wrote:
>> >> We build vlan on top of bonding interface, which vlan offload
>> >> is off, bond mode is 802.3ad (LACP) and xmit_hash_policy is
>> >> BOND_XMIT_POLICY_ENCAP34.
>> >>
>> >> __skb_flow_dissect() fails to get information from protocol headers
>> >> encapsulated within vlan, because 'nhoff' is points to IP header,
>> >> so bond hashing is based on layer 2 info, which fails to distribute
>> >> packets across slaves.
>> >>
>> >> Fixes: d5709f7ab776 ("flow_dissector: For stripped vlan, get vlan info from skb->vlan_tci")
>> >> Signed-off-by: YueHaibing <yuehaibing@huawei.com>
>> >> ---
>> >> net/core/flow_dissector.c | 3 +++
>> >> 1 file changed, 3 insertions(+)
>> >>
>> >> diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c
>> >> index 415b95f..2a52abb 100644
>> >> --- a/net/core/flow_dissector.c
>> >> +++ b/net/core/flow_dissector.c
>> >> @@ -785,6 +785,9 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
>> >> skb && skb_vlan_tag_present(skb)) {
>> >> proto = skb->protocol;
>> >> } else {
>> >> + if (dissector_vlan == FLOW_DISSECTOR_KEY_MAX)
>> >> + nhoff -= sizeof(*vlan);
>> >> +
>> > Should we instead fix the place where the skb is allocated to properly
>> > pull vlan (skb_vlan_untag)? I'm not sure this particular place is
>> > supposed to work with an skb. Having an skb with nhoff pointing to
>> > IP header but missing skb_vlan_tag_present() when with
>> > proto==ETH_P_8021xx seems weird.
>>
>> The skb is a forwarded vxlan packet, it send through vlan interface like this:
>>
>> vlan_dev_hard_start_xmit
>> --> __vlan_hwaccel_put_tag //vlan_tci and VLAN_TAG_PRESENT is set
>> --> dev_queue_xmit
>> --> validate_xmit_skb
>> --> validate_xmit_vlan // vlan_hw_offload_capable is false
>> --> __vlan_hwaccel_push_inside //here skb_push vlan_hlen, then clear skb->tci
>>
>> --> bond_start_xmit
>> --> bond_xmit_hash
>> --> __skb_flow_dissect // nhoff point to IP header
>> --> case htons(ETH_P_8021Q)
>> // skb_vlan_tag_present is false, so
>> vlan = __skb_header_pointer(skb, nhoff, sizeof(_vlan), //vlan point to ip header wrongly
>I see, so bonding device propagates hw VLAN support from the slaves.
>If one of the slaves doesn't have it, its disabled for the bond device.
>Any idea why we do that? Why not pass skbs to the slave devices
>instead and let them handle the hw/sw vlan implementation?
Probably due to historical reasons. It is indeed not needed to push the
vlan header. We should rather have the vlan_tci filled all the way down
to the transmitting netdevice. So the bonding/team should have the
NETIF_F_HW_VLAN_CTAG_TX and NETIF_F_HW_VLAN_STAG_TX flags always on.
That seems to be the correct fix to me.
>I see the propagation was added in 278339a42a1b 10 years ago and
>I don't see any rationale in the commit description.
>Somebody with more context should probably chime in :-)
^ permalink raw reply
* [PATCH V2 00/15] cleanup cppcheck signed shifting errors
From: Phong Tran @ 2019-06-24 13:50 UTC (permalink / raw)
To: tranmanphong
Cc: acme, alexander.shishkin, alexander.sverdlin, allison, andrew,
ast, bgolaszewski, bpf, daniel, daniel, dmg, festevam, gerg,
gregkh, gregory.clement, haojian.zhuang, hsweeten,
illusionist.neo, info, jason, jolsa, kafai, kernel, kgene, krzk,
kstewart, linux-arm-kernel, linux-imx, linux-kernel, linux-omap,
linux-samsung-soc, linux, liviu.dudau, lkundrak,
lorenzo.pieralisi, mark.rutland, mingo, namhyung, netdev, nsekhar,
peterz, robert.jarzmik, s.hauer, sebastian.hesselbarth, shawnguo,
songliubraving, sudeep.holla, swinslow, tglx, tony, will, yhs
In-Reply-To: <20190623151313.970-1-tranmanphong@gmail.com>
There are errors with cppcheck
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
This is just a mirror changing.
V2: Using BIT() macro instead of (1UL << nr)
Phong Tran (15):
arm: perf: cleanup cppcheck shifting error
ARM: davinci: cleanup cppcheck shifting errors
ARM: ep93xx: cleanup cppcheck shifting errors
ARM: exynos: cleanup cppcheck shifting error
ARM: footbridge: cleanup cppcheck shifting error
ARM: imx: cleanup cppcheck shifting errors
ARM: ks8695: cleanup cppcheck shifting error
ARM: mmp: cleanup cppcheck shifting errors
ARM: omap2: cleanup cppcheck shifting error
ARM: orion5x: cleanup cppcheck shifting errors
ARM: pxa: cleanup cppcheck shifting errors
ARM: vexpress: cleanup cppcheck shifting error
ARM: mm: cleanup cppcheck shifting errors
ARM: bpf: cleanup cppcheck shifting error
ARM: vfp: cleanup cppcheck shifting errors
arch/arm/kernel/perf_event_v7.c | 6 +-
arch/arm/mach-davinci/ddr2.h | 6 +-
arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++-------------------
arch/arm/mach-exynos/suspend.c | 2 +-
arch/arm/mach-footbridge/dc21285.c | 2 +-
arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++---------
arch/arm/mach-ks8695/regs-pci.h | 4 +-
arch/arm/mach-mmp/pm-mmp2.h | 40 +++++------
arch/arm/mach-mmp/pm-pxa910.h | 76 ++++++++++-----------
arch/arm/mach-omap2/powerdomain.c | 2 +-
arch/arm/mach-orion5x/pci.c | 8 +--
arch/arm/mach-pxa/irq.c | 4 +-
arch/arm/mach-vexpress/spc.c | 12 ++--
arch/arm/mm/fault.h | 6 +-
arch/arm/net/bpf_jit_32.c | 2 +-
arch/arm/vfp/vfpinstr.h | 8 +--
16 files changed, 187 insertions(+), 187 deletions(-)
--
2.11.0
^ permalink raw reply
* [PATCH V2 01/15] arm: perf: cleanup cppcheck shifting error
From: Phong Tran @ 2019-06-24 13:50 UTC (permalink / raw)
To: tranmanphong
Cc: acme, alexander.shishkin, alexander.sverdlin, allison, andrew,
ast, bgolaszewski, bpf, daniel, daniel, dmg, festevam, gerg,
gregkh, gregory.clement, haojian.zhuang, hsweeten,
illusionist.neo, info, jason, jolsa, kafai, kernel, kgene, krzk,
kstewart, linux-arm-kernel, linux-imx, linux-kernel, linux-omap,
linux-samsung-soc, linux, liviu.dudau, lkundrak,
lorenzo.pieralisi, mark.rutland, mingo, namhyung, netdev, nsekhar,
peterz, robert.jarzmik, s.hauer, sebastian.hesselbarth, shawnguo,
songliubraving, sudeep.holla, swinslow, tglx, tony, will, yhs
In-Reply-To: <20190624135105.15579-1-tranmanphong@gmail.com>
fix "Shifting signed 32-bit value by 31 bits is undefined behaviour
errors"
[arch/arm/kernel/perf_event_v7.c:1080]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/kernel/perf_event_v7.c:1436]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/kernel/perf_event_v7.c:1783]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/kernel/perf_event_v7.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index a4fb0f8b8f84..2924d7910b10 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -697,9 +697,9 @@ static struct attribute_group armv7_pmuv2_events_attr_group = {
/*
* Event filters for PMUv2
*/
-#define ARMV7_EXCLUDE_PL1 (1 << 31)
-#define ARMV7_EXCLUDE_USER (1 << 30)
-#define ARMV7_INCLUDE_HYP (1 << 27)
+#define ARMV7_EXCLUDE_PL1 BIT(31)
+#define ARMV7_EXCLUDE_USER BIT(30)
+#define ARMV7_INCLUDE_HYP BIT(27)
/*
* Secure debug enable reg
--
2.11.0
^ permalink raw reply related
* [PATCH V2 02/15] ARM: davinci: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-24 13:50 UTC (permalink / raw)
To: tranmanphong
Cc: acme, alexander.shishkin, alexander.sverdlin, allison, andrew,
ast, bgolaszewski, bpf, daniel, daniel, dmg, festevam, gerg,
gregkh, gregory.clement, haojian.zhuang, hsweeten,
illusionist.neo, info, jason, jolsa, kafai, kernel, kgene, krzk,
kstewart, linux-arm-kernel, linux-imx, linux-kernel, linux-omap,
linux-samsung-soc, linux, liviu.dudau, lkundrak,
lorenzo.pieralisi, mark.rutland, mingo, namhyung, netdev, nsekhar,
peterz, robert.jarzmik, s.hauer, sebastian.hesselbarth, shawnguo,
songliubraving, sudeep.holla, swinslow, tglx, tony, will, yhs
In-Reply-To: <20190624135105.15579-1-tranmanphong@gmail.com>
[arch/arm/mach-davinci/cpuidle.c:41]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/mach-davinci/cpuidle.c:43]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-davinci/ddr2.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-davinci/ddr2.h b/arch/arm/mach-davinci/ddr2.h
index 4f7d7824b0c9..f2f56d16d7d5 100644
--- a/arch/arm/mach-davinci/ddr2.h
+++ b/arch/arm/mach-davinci/ddr2.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
#define DDR2_SDRCR_OFFSET 0xc
-#define DDR2_SRPD_BIT (1 << 23)
-#define DDR2_MCLKSTOPEN_BIT (1 << 30)
-#define DDR2_LPMODEN_BIT (1 << 31)
+#define DDR2_SRPD_BIT BIT(23)
+#define DDR2_MCLKSTOPEN_BIT BIT(30)
+#define DDR2_LPMODEN_BIT BIT(31)
--
2.11.0
^ permalink raw reply related
* [PATCH V2 03/15] ARM: ep93xx: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-24 13:50 UTC (permalink / raw)
To: tranmanphong
Cc: acme, alexander.shishkin, alexander.sverdlin, allison, andrew,
ast, bgolaszewski, bpf, daniel, daniel, dmg, festevam, gerg,
gregkh, gregory.clement, haojian.zhuang, hsweeten,
illusionist.neo, info, jason, jolsa, kafai, kernel, kgene, krzk,
kstewart, linux-arm-kernel, linux-imx, linux-kernel, linux-omap,
linux-samsung-soc, linux, liviu.dudau, lkundrak,
lorenzo.pieralisi, mark.rutland, mingo, namhyung, netdev, nsekhar,
peterz, robert.jarzmik, s.hauer, sebastian.hesselbarth, shawnguo,
songliubraving, sudeep.holla, swinslow, tglx, tony, will, yhs
In-Reply-To: <20190624135105.15579-1-tranmanphong@gmail.com>
[arch/arm/mach-ep93xx/clock.c:102]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/clock.c:132]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/clock.c:140]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/core.c:1001]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/core.c:1002]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++++++-----------------------
1 file changed, 66 insertions(+), 66 deletions(-)
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index f2dace1c9154..250c82f8b0a1 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -109,89 +109,89 @@
#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
-#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
-#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
-#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
+#define EP93XX_SYSCON_PWRCNT_FIR_EN BIT(31)
+#define EP93XX_SYSCON_PWRCNT_UARTBAUD BIT(29)
+#define EP93XX_SYSCON_PWRCNT_USH_EN BIT(28)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 BIT(27)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 BIT(26)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 BIT(25)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 BIT(24)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 BIT(23)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 BIT(22)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 BIT(21)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 BIT(20)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 BIT(19)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 BIT(18)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 BIT(17)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 BIT(16)
#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
+#define EP93XX_SYSCON_CLKSET1_NBYP1 BIT(23)
#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
-#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
-#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
+#define EP93XX_SYSCON_CLKSET2_NBYP2 BIT(19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN BIT(18)
#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
-#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
-#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
-#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
-#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
-#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
-#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
-#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
-#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
-#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
-#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
-#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
-#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
-#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
-#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
-#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
-#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
-#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
-#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
-#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
-#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
-#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
-#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
-#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
-#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
-#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
-#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
-#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
-#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
-#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
+#define EP93XX_SYSCON_DEVCFG_SWRST BIT(31)
+#define EP93XX_SYSCON_DEVCFG_D1ONG BIT(30)
+#define EP93XX_SYSCON_DEVCFG_D0ONG BIT(29)
+#define EP93XX_SYSCON_DEVCFG_IONU2 BIT(28)
+#define EP93XX_SYSCON_DEVCFG_GONK BIT(27)
+#define EP93XX_SYSCON_DEVCFG_TONG BIT(26)
+#define EP93XX_SYSCON_DEVCFG_MONG BIT(25)
+#define EP93XX_SYSCON_DEVCFG_U3EN BIT(24)
+#define EP93XX_SYSCON_DEVCFG_CPENA BIT(23)
+#define EP93XX_SYSCON_DEVCFG_A2ONG BIT(22)
+#define EP93XX_SYSCON_DEVCFG_A1ONG BIT(21)
+#define EP93XX_SYSCON_DEVCFG_U2EN BIT(20)
+#define EP93XX_SYSCON_DEVCFG_EXVC BIT(19)
+#define EP93XX_SYSCON_DEVCFG_U1EN BIT(18)
+#define EP93XX_SYSCON_DEVCFG_TIN BIT(17)
+#define EP93XX_SYSCON_DEVCFG_HC3IN BIT(15)
+#define EP93XX_SYSCON_DEVCFG_HC3EN BIT(14)
+#define EP93XX_SYSCON_DEVCFG_HC1IN BIT(13)
+#define EP93XX_SYSCON_DEVCFG_HC1EN BIT(12)
+#define EP93XX_SYSCON_DEVCFG_HONIDE BIT(11)
+#define EP93XX_SYSCON_DEVCFG_GONIDE BIT(10)
+#define EP93XX_SYSCON_DEVCFG_PONG BIT(9)
+#define EP93XX_SYSCON_DEVCFG_EONIDE BIT(8)
+#define EP93XX_SYSCON_DEVCFG_I2SONSSP BIT(7)
+#define EP93XX_SYSCON_DEVCFG_I2SONAC97 BIT(6)
+#define EP93XX_SYSCON_DEVCFG_RASONP3 BIT(4)
+#define EP93XX_SYSCON_DEVCFG_RAS BIT(3)
+#define EP93XX_SYSCON_DEVCFG_ADCPD BIT(2)
+#define EP93XX_SYSCON_DEVCFG_KEYS BIT(1)
+#define EP93XX_SYSCON_DEVCFG_SHENA BIT(0)
#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
-#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
-#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
-#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
+#define EP93XX_SYSCON_CLKDIV_ENABLE BIT(15)
+#define EP93XX_SYSCON_CLKDIV_ESEL BIT(14)
+#define EP93XX_SYSCON_CLKDIV_PSEL BIT(13)
#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
-#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
-#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
-#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
+#define EP93XX_SYSCON_I2SCLKDIV_SENA BIT(31)
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE BIT(29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL BIT(19)
#define EP93XX_I2SCLKDIV_SDIV (1 << 16)
#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN BIT(31)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV BIT(16)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN BIT(15)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV BIT(0)
#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
-#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
-#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
-#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
-#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
-#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
-#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
-#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
-#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
+#define EP93XX_SYSCON_SYSCFG_SBOOT BIT(8)
+#define EP93XX_SYSCON_SYSCFG_LCSN7 BIT(7)
+#define EP93XX_SYSCON_SYSCFG_LCSN6 BIT(6)
+#define EP93XX_SYSCON_SYSCFG_LASDO BIT(5)
+#define EP93XX_SYSCON_SYSCFG_LEEDA BIT(4)
+#define EP93XX_SYSCON_SYSCFG_LEECLK BIT(3)
+#define EP93XX_SYSCON_SYSCFG_LCSN2 BIT(1)
+#define EP93XX_SYSCON_SYSCFG_LCSN1 BIT(0)
#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
/* EP93xx System Controller software locked register write */
--
2.11.0
^ permalink raw reply related
* [PATCH V2 04/15] ARM: exynos: cleanup cppcheck shifting error
From: Phong Tran @ 2019-06-24 13:50 UTC (permalink / raw)
To: tranmanphong
Cc: acme, alexander.shishkin, alexander.sverdlin, allison, andrew,
ast, bgolaszewski, bpf, daniel, daniel, dmg, festevam, gerg,
gregkh, gregory.clement, haojian.zhuang, hsweeten,
illusionist.neo, info, jason, jolsa, kafai, kernel, kgene, krzk,
kstewart, linux-arm-kernel, linux-imx, linux-kernel, linux-omap,
linux-samsung-soc, linux, liviu.dudau, lkundrak,
lorenzo.pieralisi, mark.rutland, mingo, namhyung, netdev, nsekhar,
peterz, robert.jarzmik, s.hauer, sebastian.hesselbarth, shawnguo,
songliubraving, sudeep.holla, swinslow, tglx, tony, will, yhs
In-Reply-To: <20190624135105.15579-1-tranmanphong@gmail.com>
[arch/arm/mach-exynos/suspend.c:288]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-exynos/suspend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index be122af0de8f..b6a73dc5bde4 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -285,7 +285,7 @@ static void exynos_pm_set_wakeup_mask(void)
* Set wake-up mask registers
* EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
*/
- pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+ pmu_raw_writel(exynos_irqwake_intmask & ~(BIT(31)), S5P_WAKEUP_MASK);
}
static void exynos_pm_enter_sleep_mode(void)
--
2.11.0
^ permalink raw reply related
* [PATCH V2 05/15] ARM: footbridge: cleanup cppcheck shifting error
From: Phong Tran @ 2019-06-24 13:50 UTC (permalink / raw)
To: tranmanphong
Cc: acme, alexander.shishkin, alexander.sverdlin, allison, andrew,
ast, bgolaszewski, bpf, daniel, daniel, dmg, festevam, gerg,
gregkh, gregory.clement, haojian.zhuang, hsweeten,
illusionist.neo, info, jason, jolsa, kafai, kernel, kgene, krzk,
kstewart, linux-arm-kernel, linux-imx, linux-kernel, linux-omap,
linux-samsung-soc, linux, liviu.dudau, lkundrak,
lorenzo.pieralisi, mark.rutland, mingo, namhyung, netdev, nsekhar,
peterz, robert.jarzmik, s.hauer, sebastian.hesselbarth, shawnguo,
songliubraving, sudeep.holla, swinslow, tglx, tony, will, yhs
In-Reply-To: <20190624135105.15579-1-tranmanphong@gmail.com>
[arch/arm/mach-footbridge/dc21285.c:236]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 8b81a17f675d..edea41e0256f 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -230,7 +230,7 @@ static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
printk("\n");
cmd = *CSR_PCICMD & 0xffff;
- *CSR_PCICMD = cmd | 1 << 31;
+ *CSR_PCICMD = cmd | BIT(31);
/*
* back off this interrupt
--
2.11.0
^ permalink raw reply related
* [PATCH V2 06/15] ARM: imx: cleanup cppcheck shifting errors
From: Phong Tran @ 2019-06-24 13:50 UTC (permalink / raw)
To: tranmanphong
Cc: acme, alexander.shishkin, alexander.sverdlin, allison, andrew,
ast, bgolaszewski, bpf, daniel, daniel, dmg, festevam, gerg,
gregkh, gregory.clement, haojian.zhuang, hsweeten,
illusionist.neo, info, jason, jolsa, kafai, kernel, kgene, krzk,
kstewart, linux-arm-kernel, linux-imx, linux-kernel, linux-omap,
linux-samsung-soc, linux, liviu.dudau, lkundrak,
lorenzo.pieralisi, mark.rutland, mingo, namhyung, netdev, nsekhar,
peterz, robert.jarzmik, s.hauer, sebastian.hesselbarth, shawnguo,
songliubraving, sudeep.holla, swinslow, tglx, tony, will, yhs
In-Reply-To: <20190624135105.15579-1-tranmanphong@gmail.com>
[arch/arm/mach-imx/iomux-mx3.h:93]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <tranmanphong@gmail.com>
---
arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++++++++++++++----------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index 99270a183d47..028b683866c3 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -59,38 +59,38 @@ enum iomux_pad_config {
* various IOMUX general purpose functions
*/
enum iomux_gp_func {
- MUX_PGP_FIRI = 1 << 0,
- MUX_DDR_MODE = 1 << 1,
- MUX_PGP_CSPI_BB = 1 << 2,
- MUX_PGP_ATA_1 = 1 << 3,
- MUX_PGP_ATA_2 = 1 << 4,
- MUX_PGP_ATA_3 = 1 << 5,
- MUX_PGP_ATA_4 = 1 << 6,
- MUX_PGP_ATA_5 = 1 << 7,
- MUX_PGP_ATA_6 = 1 << 8,
- MUX_PGP_ATA_7 = 1 << 9,
- MUX_PGP_ATA_8 = 1 << 10,
- MUX_PGP_UH2 = 1 << 11,
- MUX_SDCTL_CSD0_SEL = 1 << 12,
- MUX_SDCTL_CSD1_SEL = 1 << 13,
- MUX_CSPI1_UART3 = 1 << 14,
- MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
- MUX_TAMPER_DETECT_EN = 1 << 16,
- MUX_PGP_USB_4WIRE = 1 << 17,
- MUX_PGP_USB_COMMON = 1 << 18,
- MUX_SDHC_MEMSTICK1 = 1 << 19,
- MUX_SDHC_MEMSTICK2 = 1 << 20,
- MUX_PGP_SPLL_BYP = 1 << 21,
- MUX_PGP_UPLL_BYP = 1 << 22,
- MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
- MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
- MUX_CSPI3_UART5_SEL = 1 << 25,
- MUX_PGP_ATA_9 = 1 << 26,
- MUX_PGP_USB_SUSPEND = 1 << 27,
- MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
- MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
- MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
- MUX_CLKO_DDR_MODE = 1 << 31,
+ MUX_PGP_FIRI = BIT(0),
+ MUX_DDR_MODE = BIT(1),
+ MUX_PGP_CSPI_BB = BIT(2),
+ MUX_PGP_ATA_1 = BIT(3),
+ MUX_PGP_ATA_2 = BIT(4),
+ MUX_PGP_ATA_3 = BIT(5),
+ MUX_PGP_ATA_4 = BIT(6),
+ MUX_PGP_ATA_5 = BIT(7),
+ MUX_PGP_ATA_6 = BIT(8),
+ MUX_PGP_ATA_7 = BIT(9),
+ MUX_PGP_ATA_8 = BIT(10),
+ MUX_PGP_UH2 = BIT(11),
+ MUX_SDCTL_CSD0_SEL = BIT(12),
+ MUX_SDCTL_CSD1_SEL = BIT(13),
+ MUX_CSPI1_UART3 = BIT(14),
+ MUX_EXTDMAREQ2_MBX_SEL = BIT(15),
+ MUX_TAMPER_DETECT_EN = BIT(16),
+ MUX_PGP_USB_4WIRE = BIT(17),
+ MUX_PGP_USB_COMMON = BIT(18),
+ MUX_SDHC_MEMSTICK1 = BIT(19),
+ MUX_SDHC_MEMSTICK2 = BIT(20),
+ MUX_PGP_SPLL_BYP = BIT(21),
+ MUX_PGP_UPLL_BYP = BIT(22),
+ MUX_PGP_MSHC1_CLK_SEL = BIT(23),
+ MUX_PGP_MSHC2_CLK_SEL = BIT(24),
+ MUX_CSPI3_UART5_SEL = BIT(25),
+ MUX_PGP_ATA_9 = BIT(26),
+ MUX_PGP_USB_SUSPEND = BIT(27),
+ MUX_PGP_USB_OTG_LOOPBACK = BIT(28),
+ MUX_PGP_USB_HS1_LOOPBACK = BIT(29),
+ MUX_PGP_USB_HS2_LOOPBACK = BIT(30),
+ MUX_CLKO_DDR_MODE = BIT(31),
};
/*
--
2.11.0
^ permalink raw reply related
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