* Re: [net-next v5 09/12] net: bnxt: Add SW GSO completion and teardown support
From: Paolo Abeni @ 2026-03-26 12:39 UTC (permalink / raw)
To: Joe Damato, netdev, Michael Chan, Pavan Chebbi, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski
Cc: horms, linux-kernel, leon
In-Reply-To: <20260323183844.3146982-10-joe@dama.to>
On 3/23/26 7:38 PM, Joe Damato wrote:
> Update __bnxt_tx_int and bnxt_free_one_tx_ring_skbs to handle SW GSO
> segments:
>
> - MID segments: adjust tx_pkts/tx_bytes accounting and skip skb free
> (the skb is shared across all segments and freed only once)
>
> - LAST segments: if the DMA IOVA path was used, use dma_iova_destroy to
> tear down the contiguous mapping. On the fallback path, payload DMA
> unmapping is handled by the existing per-BD dma_unmap_len walk.
>
> Both MID and LAST completions advance tx_inline_cons to release the
> segment's inline header slot back to the ring.
>
> is_sw_gso is initialized to zero, so the new code paths are not run.
>
> Suggested-by: Jakub Kicinski <kuba@kernel.org>
> Reviewed-by: Pavan Chebbi <pavan.chebbi@broadcom.com>
> Signed-off-by: Joe Damato <joe@dama.to>
> ---
> v5:
> - Added Pavan's Reviewed-by. No functional changes.
>
> v3:
> - completion paths updated to use DMA IOVA APIs to teardown mappings.
>
> rfcv2:
> - Update the shared header buffer consumer on TX completion.
>
> drivers/net/ethernet/broadcom/bnxt/bnxt.c | 82 +++++++++++++++++--
> .../net/ethernet/broadcom/bnxt/bnxt_ethtool.c | 19 ++++-
> 2 files changed, 91 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> index 2759a4e2b148..40a16f96feba 100644
> --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
> @@ -74,6 +74,8 @@
> #include "bnxt_debugfs.h"
> #include "bnxt_coredump.h"
> #include "bnxt_hwmon.h"
> +#include "bnxt_gso.h"
> +#include <net/tso.h>
>
> #define BNXT_TX_TIMEOUT (5 * HZ)
> #define BNXT_DEF_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_HW | \
> @@ -817,12 +819,13 @@ static bool __bnxt_tx_int(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
> bool rc = false;
>
> while (RING_TX(bp, cons) != hw_cons) {
> - struct bnxt_sw_tx_bd *tx_buf;
> + struct bnxt_sw_tx_bd *tx_buf, *head_buf;
> struct sk_buff *skb;
> bool is_ts_pkt;
> int j, last;
>
> tx_buf = &txr->tx_buf_ring[RING_TX(bp, cons)];
> + head_buf = tx_buf;
> skb = tx_buf->skb;
>
> if (unlikely(!skb)) {
> @@ -869,6 +872,23 @@ static bool __bnxt_tx_int(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
> DMA_TO_DEVICE, 0);
> }
> }
> +
> + if (unlikely(head_buf->is_sw_gso)) {
> + txr->tx_inline_cons++;
> + if (head_buf->is_sw_gso == BNXT_SW_GSO_LAST) {
> + if (dma_use_iova(&head_buf->iova_state))
I'm likely lost, but AFAICS the previous patch/bnxt_sw_udp_gso_xmit()
initialize head_buf->iova_state only when
`dma_use_iova(&head_buf->iova_state) == true`. I.e. in fallback scenario
the previous iova_state is maintained.
Additionally AFAICS dma_iova_destroy does not clear `head_buf->iova_state`.
It looks like that 2 consecutive skb hitting the same slot use a
different dma mapping strategy (fallback vs iova) bat things will
happen?!? should the previous patch always initializing
head_buf->iova_state?
/P
^ permalink raw reply
* Re: [PATCH 3/3] net: dsa: microchip: implement KSZ87xx Module 3 low-loss cable errata
From: Marek Vasut @ 2026-03-26 12:38 UTC (permalink / raw)
To: Fidelio Lawson, Woojung Huh, UNGLinuxDriver, Andrew Lunn,
Vladimir Oltean, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Chevallier
Cc: netdev, devicetree, linux-kernel, Fidelio Lawson
In-Reply-To: <20260326-ksz87xx_errata_low_loss_connections-v1-3-79a698f43626@exotec.com>
[-- Attachment #1: Type: text/plain, Size: 5627 bytes --]
On 3/26/26 10:10 AM, Fidelio Lawson wrote:
> +static int ksz8_handle_module3_errata(struct ksz_device *dev)
> +{
> + int ret = 0;
> + const u16 *regs = dev->info->regs;
> + u16 indir_reg = 0x0000;
> + u8 indir_val = 0x00;
> +
> + switch (dev->low_loss_wa_mode) {
> + case KSZ_LOW_LOSS_WA_1:
> + indir_reg = 0x3C;
> + indir_val = 0x15;
> + break;
> + case KSZ_LOW_LOSS_WA_2:
> + indir_reg = 0x4C;
> + indir_val = 0x40;
> + break;
> + default:
> + break;
> + }
> +
> + mutex_lock(&dev->alu_mutex);
> +
> + ret = ksz_write8(dev, regs[REG_IND_CTRL_0], 0xA0);
> +
> + if (!ret)
> + ret = ksz_write8(dev, 0x6F, indir_reg);
> +
> + if (!ret)
> + ret = ksz_write8(dev, regs[REG_IND_BYTE], indir_val);
> +
> + mutex_unlock(&dev->alu_mutex);
> +
> + return ret;
> +}
Since this is configurable from DT, please adjust the bindings and make
the low pass filter bandwidth actually configurable according to the
values supported by the hardware, see this article:
https://microchip.my.site.com/s/article/Solution-for-Using-CAT-5E-or-CAT-6-Short-Cable-with-a-Link-Issue-for-the-KSZ8795-Family
The indirect register (0x4C) is an 8-bit register. The bits [7:6] are
described in the table below.
Low pass filter bandwidth
00 = 90MHz
01 = 62MHz
10 = 55MHz
11 = 44MHz
...
I had this attached patch in my tree for a while, I just never got
around to finishing it, because even with this in place, there was some
packet loss with short cables at low temperatures. Maybe it can help:
From 937278ee6dc0aa46797cc4b2d53078f95b6557a9 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@nabladev.com>
Date: Mon, 2 Jun 2025 01:42:17 +0200
Subject: [PATCH] net: dsa: microchip: Fix KSZ87xx high quality cable errata
module 3
KSZ87xx may fail to establish link, or may take long time to
establish link, when using high quality > CAT-5 ethernet cables.
This is described in KSZ87xx Errata DS80000687C Module 3:
Module 3: Establishing a link through low loss connections.
The receiver of the embedded PHYs is tuned by default to
support long cable length applications. This was developed
using low quality, high loss cables. Because of this, the
equalizer in the PHY may amplify high amplitude receiver
signals to the point that the signal is distorted internally,
preventing a link from being established.
More detailed description and a more advanced fix is described in
"
Solution for Using CAT-5E or CAT-6 Short Cable with a Link Issue
for the KSZ8795 Family
"
https://microchip.my.site.com/s/article/Solution-for-Using-CAT-5E-or-CAT-6-Short-Cable-with-a-Link-Issue-for-the-KSZ8795-Family
The fix reduces low pass filter bandwidth from 90 MHz to 62 MHz
to block higher frequency components which make it through the
higher quality cables and saturate the receiver amplifier. In
case of even shorter cables, the link equalizer function has to
start from position 0 instead of the default position 0xf to
cater for those cables, configure the equalizer position as well.
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
drivers/net/dsa/microchip/ksz8.c | 33 ++++++++++++++++++++++++++--
drivers/net/dsa/microchip/ksz8_reg.h | 2 +-
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/microchip/ksz8.c
b/drivers/net/dsa/microchip/ksz8.c
index 3309c2c172f02..f8716c8d0d375 100644
--- a/drivers/net/dsa/microchip/ksz8.c
+++ b/drivers/net/dsa/microchip/ksz8.c
@@ -1891,10 +1891,39 @@ static int ksz8_handle_global_errata(struct
dsa_switch *ds)
* KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in
* the link dropping.
*/
- if (dev->info->ksz87xx_eee_link_erratum)
+ if (dev->info->ksz87xx_eee_link_erratum) {
ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0);
+ if (ret)
+ return ret;
+ }
- return ret;
+ /*
+ * Module 3: Establishing a link through low loss connections.
+ * The receiver of the embedded PHYs is tuned by default to
+ * support long cable length applications. This was developed
+ * using low quality, high loss cables. Because of this, the
+ * equalizer in the PHY may amplify high amplitude receiver
+ * signals to the point that the signal is distorted internally,
+ * preventing a link from being established.
+ *
+ * More detailed description and a more advanced fix is described in
+ * "
+ * Solution for Using CAT-5E or CAT-6 Short Cable with a Link Issue
+ * for the KSZ8795 Family
+ * "
+ *
https://microchip.my.site.com/s/article/Solution-for-Using-CAT-5E-or-CAT-6-Short-Cable-with-a-Link-Issue-for-the-KSZ8795-Family
+ *
+ * The following two magic writes are the implementation of the
+ * aforementioned workaround.
+ */
+
+ /* Force low pass filter bandwidth from 90 MHz to 62 MHz */
+ ret = ksz8_ind_write8(dev, TABLE_LINK_MD, 0x4c, 0x40);
+ if (ret)
+ return ret;
+
+ /* Force DSP EQ initial value to 0 */
+ return ksz8_ind_write8(dev, TABLE_LINK_MD, 0x08, 0);
}
int ksz8_enable_stp_addr(struct ksz_device *dev)
diff --git a/drivers/net/dsa/microchip/ksz8_reg.h
b/drivers/net/dsa/microchip/ksz8_reg.h
index 329688603a582..c4897f27c6d1c 100644
--- a/drivers/net/dsa/microchip/ksz8_reg.h
+++ b/drivers/net/dsa/microchip/ksz8_reg.h
@@ -342,7 +342,7 @@
#define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S)
#define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S)
#define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S)
-#define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S)
+#define TABLE_LINK_MD (TABLE_LINK_MD_V << TABLE_EXT_SELECT_S)
#define TABLE_READ BIT(4)
#define TABLE_SELECT_S 2
#define TABLE_STATIC_MAC_V 0
--
2.53.0
[-- Attachment #2: 0001-net-dsa-microchip-Fix-KSZ87xx-high-quality-cable-err.patch --]
[-- Type: text/x-patch, Size: 4121 bytes --]
From 937278ee6dc0aa46797cc4b2d53078f95b6557a9 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@nabladev.com>
Date: Mon, 2 Jun 2025 01:42:17 +0200
Subject: [PATCH] net: dsa: microchip: Fix KSZ87xx high quality cable errata
module 3
KSZ87xx may fail to establish link, or may take long time to
establish link, when using high quality > CAT-5 ethernet cables.
This is described in KSZ87xx Errata DS80000687C Module 3:
Module 3: Establishing a link through low loss connections.
The receiver of the embedded PHYs is tuned by default to
support long cable length applications. This was developed
using low quality, high loss cables. Because of this, the
equalizer in the PHY may amplify high amplitude receiver
signals to the point that the signal is distorted internally,
preventing a link from being established.
More detailed description and a more advanced fix is described in
"
Solution for Using CAT-5E or CAT-6 Short Cable with a Link Issue
for the KSZ8795 Family
"
https://microchip.my.site.com/s/article/Solution-for-Using-CAT-5E-or-CAT-6-Short-Cable-with-a-Link-Issue-for-the-KSZ8795-Family
The fix reduces low pass filter bandwidth from 90 MHz to 62 MHz
to block higher frequency components which make it through the
higher quality cables and saturate the receiver amplifier. In
case of even shorter cables, the link equalizer function has to
start from position 0 instead of the default position 0xf to
cater for those cables, configure the equalizer position as well.
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
drivers/net/dsa/microchip/ksz8.c | 33 ++++++++++++++++++++++++++--
drivers/net/dsa/microchip/ksz8_reg.h | 2 +-
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/microchip/ksz8.c b/drivers/net/dsa/microchip/ksz8.c
index 3309c2c172f02..f8716c8d0d375 100644
--- a/drivers/net/dsa/microchip/ksz8.c
+++ b/drivers/net/dsa/microchip/ksz8.c
@@ -1891,10 +1891,39 @@ static int ksz8_handle_global_errata(struct dsa_switch *ds)
* KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in
* the link dropping.
*/
- if (dev->info->ksz87xx_eee_link_erratum)
+ if (dev->info->ksz87xx_eee_link_erratum) {
ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0);
+ if (ret)
+ return ret;
+ }
- return ret;
+ /*
+ * Module 3: Establishing a link through low loss connections.
+ * The receiver of the embedded PHYs is tuned by default to
+ * support long cable length applications. This was developed
+ * using low quality, high loss cables. Because of this, the
+ * equalizer in the PHY may amplify high amplitude receiver
+ * signals to the point that the signal is distorted internally,
+ * preventing a link from being established.
+ *
+ * More detailed description and a more advanced fix is described in
+ * "
+ * Solution for Using CAT-5E or CAT-6 Short Cable with a Link Issue
+ * for the KSZ8795 Family
+ * "
+ * https://microchip.my.site.com/s/article/Solution-for-Using-CAT-5E-or-CAT-6-Short-Cable-with-a-Link-Issue-for-the-KSZ8795-Family
+ *
+ * The following two magic writes are the implementation of the
+ * aforementioned workaround.
+ */
+
+ /* Force low pass filter bandwidth from 90 MHz to 62 MHz */
+ ret = ksz8_ind_write8(dev, TABLE_LINK_MD, 0x4c, 0x40);
+ if (ret)
+ return ret;
+
+ /* Force DSP EQ initial value to 0 */
+ return ksz8_ind_write8(dev, TABLE_LINK_MD, 0x08, 0);
}
int ksz8_enable_stp_addr(struct ksz_device *dev)
diff --git a/drivers/net/dsa/microchip/ksz8_reg.h b/drivers/net/dsa/microchip/ksz8_reg.h
index 329688603a582..c4897f27c6d1c 100644
--- a/drivers/net/dsa/microchip/ksz8_reg.h
+++ b/drivers/net/dsa/microchip/ksz8_reg.h
@@ -342,7 +342,7 @@
#define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S)
#define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S)
#define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S)
-#define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S)
+#define TABLE_LINK_MD (TABLE_LINK_MD_V << TABLE_EXT_SELECT_S)
#define TABLE_READ BIT(4)
#define TABLE_SELECT_S 2
#define TABLE_STATIC_MAC_V 0
--
2.53.0
^ permalink raw reply related
* [PATCH net] xfrm: account XFRMA_IF_ID in aevent size calculation
From: Keenan Dong @ 2026-03-26 12:36 UTC (permalink / raw)
To: steffen.klassert, netdev
Cc: keenanat2000, herbert, davem, edumazet, kuba, pabeni, horms,
linux-kernel
xfrm_get_ae() allocates the reply skb with xfrm_aevent_msgsize(), then
build_aevent() appends attributes including XFRMA_IF_ID when x->if_id is
set.
xfrm_aevent_msgsize() does not include space for XFRMA_IF_ID. For states
with if_id, build_aevent() can fail with -EMSGSIZE and hit BUG_ON(err < 0)
in xfrm_get_ae(), turning a malformed netlink interaction into a kernel
panic.
Account XFRMA_IF_ID in the size calculation unconditionally and replace
the BUG_ON with normal error unwinding.
Fixes: 7e6526404ade ("xfrm: Add a new lookup key to match xfrm interfaces.")
Reported-by: Keenan Dong <keenanat2000@gmail.com>
Signed-off-by: Keenan Dong <keenanat2000@gmail.com>
---
net/xfrm/xfrm_user.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c
index 1656b487f..d79240a1c 100644
--- a/net/xfrm/xfrm_user.c
+++ b/net/xfrm/xfrm_user.c
@@ -2677,7 +2677,8 @@ static inline unsigned int xfrm_aevent_msgsize(struct xfrm_state *x)
+ nla_total_size(4) /* XFRM_AE_RTHR */
+ nla_total_size(4) /* XFRM_AE_ETHR */
+ nla_total_size(sizeof(x->dir)) /* XFRMA_SA_DIR */
- + nla_total_size(4); /* XFRMA_SA_PCPU */
+ + nla_total_size(4) /* XFRMA_SA_PCPU */
+ + nla_total_size(sizeof(x->if_id)); /* XFRMA_IF_ID */
}
static int build_aevent(struct sk_buff *skb, struct xfrm_state *x, const struct km_event *c)
@@ -2789,7 +2790,12 @@ static int xfrm_get_ae(struct sk_buff *skb, struct nlmsghdr *nlh,
c.portid = nlh->nlmsg_pid;
err = build_aevent(r_skb, x, &c);
- BUG_ON(err < 0);
+ if (err < 0) {
+ spin_unlock_bh(&x->lock);
+ xfrm_state_put(x);
+ kfree_skb(r_skb);
+ return err;
+ }
err = nlmsg_unicast(xfrm_net_nlsk(net, skb), r_skb, NETLINK_CB(skb).portid);
spin_unlock_bh(&x->lock);
--
2.43.0
^ permalink raw reply related
* [PATCH v2 4/4] net/rds: Use special gfp_t format specifier
From: Brendan Jackman @ 2026-03-26 12:32 UTC (permalink / raw)
To: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Stanislaw Gruszka, Alexander Potapenko,
Marco Elver, Dmitry Vyukov, Andrew Morton, Allison Henderson,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman
Cc: dri-devel, linux-kernel, linux-wireless, kasan-dev, linux-mm,
netdev, linux-rdma, rds-devel, Brendan Jackman
In-Reply-To: <20260326-gfp64-v2-0-d916021cecdf@google.com>
%pGg produces nice readable output and decouples the format string from
the size of gfp_t.
Signed-off-by: Brendan Jackman <jackmanb@google.com>
---
net/rds/tcp_recv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/rds/tcp_recv.c b/net/rds/tcp_recv.c
index 49f96ee0c40f6..ffe843ca219c7 100644
--- a/net/rds/tcp_recv.c
+++ b/net/rds/tcp_recv.c
@@ -275,7 +275,7 @@ static int rds_tcp_read_sock(struct rds_conn_path *cp, gfp_t gfp)
desc.count = 1; /* give more than one skb per call */
tcp_read_sock(sock->sk, &desc, rds_tcp_data_recv);
- rdsdebug("tcp_read_sock for tc %p gfp 0x%x returned %d\n", tc, gfp,
+ rdsdebug("tcp_read_sock for tc %p gfp %pGg returned %d\n", tc, &gfp,
desc.error);
if (skb_queue_empty_lockless(&sock->sk->sk_receive_queue) &&
--
2.51.2
^ permalink raw reply related
* [PATCH v2 3/4] mm/kfence: Use special gfp_t format specifier
From: Brendan Jackman @ 2026-03-26 12:31 UTC (permalink / raw)
To: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Stanislaw Gruszka, Alexander Potapenko,
Marco Elver, Dmitry Vyukov, Andrew Morton, Allison Henderson,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman
Cc: dri-devel, linux-kernel, linux-wireless, kasan-dev, linux-mm,
netdev, linux-rdma, rds-devel, Brendan Jackman
In-Reply-To: <20260326-gfp64-v2-0-d916021cecdf@google.com>
%pGg produces nice readable output and decouples the format string from
the size of gfp_t.
Signed-off-by: Brendan Jackman <jackmanb@google.com>
---
mm/kfence/kfence_test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mm/kfence/kfence_test.c b/mm/kfence/kfence_test.c
index 5725a367246d9..10424cd25e5a6 100644
--- a/mm/kfence/kfence_test.c
+++ b/mm/kfence/kfence_test.c
@@ -263,7 +263,7 @@ static void *test_alloc(struct kunit *test, size_t size, gfp_t gfp, enum allocat
break;
}
- kunit_info(test, "%s: size=%zu, gfp=%x, policy=%s, cache=%i\n", __func__, size, gfp,
+ kunit_info(test, "%s: size=%zu, gfp=%pGg, policy=%s, cache=%i\n", __func__, size, &gfp,
policy_name, !!test_cache);
/*
--
2.51.2
^ permalink raw reply related
* [PATCH v2 2/4] iwlegacy: 3945-mac: Fixup allocation failure log
From: Brendan Jackman @ 2026-03-26 12:31 UTC (permalink / raw)
To: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Stanislaw Gruszka, Alexander Potapenko,
Marco Elver, Dmitry Vyukov, Andrew Morton, Allison Henderson,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman
Cc: dri-devel, linux-kernel, linux-wireless, kasan-dev, linux-mm,
netdev, linux-rdma, rds-devel, Brendan Jackman
In-Reply-To: <20260326-gfp64-v2-0-d916021cecdf@google.com>
Fix 2 issues spotted by AI[0]:
1. Missing space after the full stop.
2. Wrong GFP flags are printed.
And also switch to %pGg for the GFP flags. This produces nice readable
output and decouples the format string from the size of gfp_t.
[0] https://sashiko.dev/#/patchset/20260319-gfp64-v1-0-2c73b8d42b7f%40google.com
Signed-off-by: Brendan Jackman <jackmanb@google.com>
---
drivers/net/wireless/intel/iwlegacy/3945-mac.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/wireless/intel/iwlegacy/3945-mac.c b/drivers/net/wireless/intel/iwlegacy/3945-mac.c
index c148654aa9533..88b31e0b9568c 100644
--- a/drivers/net/wireless/intel/iwlegacy/3945-mac.c
+++ b/drivers/net/wireless/intel/iwlegacy/3945-mac.c
@@ -1002,9 +1002,9 @@ il3945_rx_allocate(struct il_priv *il, gfp_t priority)
D_INFO("Failed to allocate SKB buffer.\n");
if (rxq->free_count <= RX_LOW_WATERMARK &&
net_ratelimit())
- IL_ERR("Failed to allocate SKB buffer with %0x."
+ IL_ERR("Failed to allocate SKB buffer with %pGg. "
"Only %u free buffers remaining.\n",
- priority, rxq->free_count);
+ &gfp_mask, rxq->free_count);
/* We don't reschedule replenish work here -- we will
* call the restock method and if it still needs
* more buffers it will schedule replenish */
--
2.51.2
^ permalink raw reply related
* [PATCH v2 1/4] drm/managed: Use special gfp_t format specifier
From: Brendan Jackman @ 2026-03-26 12:31 UTC (permalink / raw)
To: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Stanislaw Gruszka, Alexander Potapenko,
Marco Elver, Dmitry Vyukov, Andrew Morton, Allison Henderson,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman
Cc: dri-devel, linux-kernel, linux-wireless, kasan-dev, linux-mm,
netdev, linux-rdma, rds-devel, Brendan Jackman
In-Reply-To: <20260326-gfp64-v2-0-d916021cecdf@google.com>
%pGg produces nice readable output and decouples the format string from
the size of gfp_t.
Signed-off-by: Brendan Jackman <jackmanb@google.com>
---
drivers/gpu/drm/drm_managed.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_managed.c b/drivers/gpu/drm/drm_managed.c
index 247f468731de0..a9da94319b052 100644
--- a/drivers/gpu/drm/drm_managed.c
+++ b/drivers/gpu/drm/drm_managed.c
@@ -232,8 +232,8 @@ void *drmm_kmalloc(struct drm_device *dev, size_t size, gfp_t gfp)
dr = alloc_dr(NULL, size, gfp, dev_to_node(dev->dev));
if (!dr) {
- drm_dbg_drmres(dev, "failed to allocate %zu bytes, %u flags\n",
- size, gfp);
+ drm_dbg_drmres(dev, "failed to allocate %zu bytes, %pGg\n",
+ size, &gfp);
return NULL;
}
dr->node.name = kstrdup_const("kmalloc", gfp);
--
2.51.2
^ permalink raw reply related
* [PATCH v2 0/4] treewide: fixup gfp_t printks
From: Brendan Jackman @ 2026-03-26 12:31 UTC (permalink / raw)
To: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Stanislaw Gruszka, Alexander Potapenko,
Marco Elver, Dmitry Vyukov, Andrew Morton, Allison Henderson,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman
Cc: dri-devel, linux-kernel, linux-wireless, kasan-dev, linux-mm,
netdev, linux-rdma, rds-devel, Brendan Jackman
This patchset used to be about switching gfp_t to unsigned long. That is
probably not gonna happen any more but while writing it I found these
cleanups that seem worthwhile regardless.
Signed-off-by: Brendan Jackman <jackmanb@google.com>
---
Changes in v2:
- Drop gfp_t changes
- Add correct CCs
- Add minor fixups to preexisting code spotted by AI review
- Link to v1: https://lore.kernel.org/r/20260319-gfp64-v1-0-2c73b8d42b7f@google.com
---
Brendan Jackman (4):
drm/managed: Use special gfp_t format specifier
iwlegacy: 3945-mac: Fixup allocation failure log
mm/kfence: Use special gfp_t format specifier
net/rds: Use special gfp_t format specifier
drivers/gpu/drm/drm_managed.c | 4 ++--
drivers/net/wireless/intel/iwlegacy/3945-mac.c | 4 ++--
mm/kfence/kfence_test.c | 2 +-
net/rds/tcp_recv.c | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
---
base-commit: c369299895a591d96745d6492d4888259b004a9e
change-id: 20260319-gfp64-7a970a80ba4e
Best regards,
--
Brendan Jackman <jackmanb@google.com>
^ permalink raw reply
* Re: [PATCH net-next v2 3/4] net: phy: air_phy_lib: Factorize BuckPBus register accessors
From: Andrew Lunn @ 2026-03-26 12:30 UTC (permalink / raw)
To: Louis-Alexis Eyraud
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Heiner Kallweit, Russell King,
kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
In-Reply-To: <20260326-add-airoha-an8801-support-v2-3-1a42d6b6050f@collabora.com>
> @@ -480,8 +287,8 @@ static int en8811h_wait_mcu_ready(struct phy_device *phydev)
> {
> int ret, reg_value;
>
> - ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
> - EN8811H_FW_CTRL_1_FINISH);
> + ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
> + EN8811H_FW_CTRL_1_FINISH);
Is a rename required? Is the namespace air_buckpbus_ used somewhere
else?
Andrew
^ permalink raw reply
* [PATCH net] net: sfp: Fix Ubiquiti U-Fiber Instant SFP module on mvneta
From: Marek Behún @ 2026-03-26 12:20 UTC (permalink / raw)
To: netdev, Russell King
Cc: Paolo Abeni, Jakub Kicinski, Eric Dumazet, David S. Miller,
Heiner Kallweit, Andrew Lunn, Maxime Chevallier, Marek Behún
In commit 8110633db49d7de2 ("net: sfp-bus: allow SFP quirks to override
Autoneg and pause bits") we moved the setting of Autoneg and pause bits
before the call to SFP quirk when parsing SFP module support.
Since the quirk for Ubiquiti U-Fiber Instant SFP module zeroes the
support bits and sets 1000baseX_Full only, the above mentioned commit
changed the overall computed support from
1000baseX_Full, Autoneg, Pause, Asym_Pause
to just
1000baseX_Full.
This broke the SFP module for mvneta, which requires Autoneg for
1000baseX since commit c762b7fac1b249a9 ("net: mvneta: deny disabling
autoneg for 802.3z modes").
Fix this by setting back the Autoneg, Pause and Asym_Pause bits in the
quirk.
Fixes: 8110633db49d7de2 ("net: sfp-bus: allow SFP quirks to override Autoneg and pause bits")
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/net/phy/sfp.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c
index 5db841377199..ce8924613363 100644
--- a/drivers/net/phy/sfp.c
+++ b/drivers/net/phy/sfp.c
@@ -480,11 +480,16 @@ static void sfp_quirk_ubnt_uf_instant(const struct sfp_eeprom_id *id,
{
/* Ubiquiti U-Fiber Instant module claims that support all transceiver
* types including 10G Ethernet which is not truth. So clear all claimed
- * modes and set only one mode which module supports: 1000baseX_Full.
+ * modes and set only one mode which module supports: 1000baseX_Full,
+ * along with the Autoneg and pause bits.
*/
linkmode_zero(caps->link_modes);
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
caps->link_modes);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, caps->link_modes);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, caps->link_modes);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, caps->link_modes);
+
phy_interface_zero(caps->interfaces);
__set_bit(PHY_INTERFACE_MODE_1000BASEX, caps->interfaces);
}
--
2.52.0
^ permalink raw reply related
* Re: [PATCH net-next 5/5] selftests: net: add veth BQL stress test
From: Jesper Dangaard Brouer @ 2026-03-26 12:19 UTC (permalink / raw)
To: netdev
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, horms, jhs, jiri,
j.koeppeler, kernel-team
In-Reply-To: <20260324174719.1224337-7-hawk@kernel.org>
On 24/03/2026 18.47, hawk@kernel.org wrote:
> From: Jesper Dangaard Brouer<hawk@kernel.org>
>
> Add a selftest that exercises veth's BQL (Byte Queue Limits) code path
> under sustained UDP load. The test creates a veth pair with GRO enabled
> (activating the NAPI path and BQL), attaches a qdisc, optionally loads
> iptables rules in the consumer namespace to slow NAPI processing, and
> floods UDP packets for a configurable duration.
>
[...]
>
> Signed-off-by: Jesper Dangaard Brouer<hawk@kernel.org>
> Tested-by: Jonas Köppeler<j.koeppeler@tu-berlin.de>
> ---
> tools/testing/selftests/net/veth_bql_test.sh | 784 ++++++++++++++++++
> .../selftests/net/veth_bql_test_virtme.sh | 124 +++
> 2 files changed, 908 insertions(+)
> create mode 100755 tools/testing/selftests/net/veth_bql_test.sh
> create mode 100755 tools/testing/selftests/net/veth_bql_test_virtme.sh
>
> diff --git a/tools/testing/selftests/net/veth_bql_test.sh b/tools/testing/selftests/net/veth_bql_test.sh
> new file mode 100755
> index 000000000000..9b5923341040
> --- /dev/null
> +++ b/tools/testing/selftests/net/veth_bql_test.sh
The netdev/shellcheck [0][1] had some review comments.
I will work on addressing these.
[0]
https://netdev-ctrl.bots.linux.dev/logs/build/1071815/14493217/shellcheck/stdout
[1] https://www.shellcheck.net/
pw-bot: changes-requested
--Jesper
^ permalink raw reply
* [PATCH net v6] net: use skb_header_pointer() for TCPv4 GSO frag_off
From: Guoyu Su @ 2026-03-26 12:18 UTC (permalink / raw)
To: edumazet, davem, kuba, pabeni
Cc: willemdebruijn.kernel, netdev, horms, linux-kernel,
syzkaller-bugs, syzbot+1543a7d954d9c6d00407, Guoyu Su
In-Reply-To: <willemdebruijn.kernel.1a9f35039caab@gmail.com>
Syzbot reported a KMSAN uninit-value warning in gso_features_check()
called from netif_skb_features() [1].
gso_features_check() reads iph->frag_off to decide whether to clear
mangleid_features. Accessing the IPv4 header via ip_hdr()/inner_ip_hdr()
can rely on skb header offsets that are not always safe for direct
dereference on packets injected from PF_PACKET paths.
Use skb_header_pointer() for the TCPv4 frag_off check so the header read
is robust whether data is already linear or needs copying.
This also removes the SKB_GSO_DODGY special casing: skb_header_pointer()
already fast-paths linear data, so a separate direct-access path is not
needed.
[1] https://syzkaller.appspot.com/bug?extid=1543a7d954d9c6d00407
Link: https://lore.kernel.org/netdev/willemdebruijn.kernel.1a9f35039caab@gmail.com/
Fixes: cbc53e08a793 ("GSO: Add GSO type for fixed IPv4 ID")
Reported-by: syzbot+1543a7d954d9c6d00407@syzkaller.appspotmail.com
Closes: https://syzkaller.appspot.com/bug?extid=1543a7d954d9c6d00407
Tested-by: syzbot+1543a7d954d9c6d00407@syzkaller.appspotmail.com
Signed-off-by: Guoyu Su <yss2813483011xxl@gmail.com>
---
v6:
- Use skb_header_pointer() for both DODGY and non-DODGY TCPv4 GSO
packets in gso_features_check().
- Drop the SKB_GSO_DODGY special-casing for IPv4 header access.
v5: https://lore.kernel.org/netdev/20260320141459.9691-1-yss2813483011xxl@gmail.com/
v4: https://lore.kernel.org/netdev/20260319005421.14908-1-yss2813483011xxl@gmail.com/
v3: https://lore.kernel.org/netdev/20260312104351.185370-1-yss2813483011xxl@gmail.com/
v2: https://lore.kernel.org/netdev/20260308083319.1255118-1-yss2813483011xxl@gmail.com/
v1: https://lore.kernel.org/netdev/20260307162905.3697050-1-yss2813483011xxl@gmail.com/
net/core/dev.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/net/core/dev.c b/net/core/dev.c
index 14a83f2035b9..8a15ca67cfed 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -3805,10 +3805,16 @@ static netdev_features_t gso_features_check(const struct sk_buff *skb,
* segmentation-offloads.rst).
*/
if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
- struct iphdr *iph = skb->encapsulation ?
- inner_ip_hdr(skb) : ip_hdr(skb);
+ const struct iphdr *iph;
+ struct iphdr _iph;
- if (!(iph->frag_off & htons(IP_DF)))
+ int nhoff = skb->encapsulation ?
+ skb_inner_network_offset(skb) :
+ skb_network_offset(skb);
+
+ iph = skb_header_pointer(skb, nhoff, sizeof(_iph), &_iph);
+
+ if (!iph || !(iph->frag_off & htons(IP_DF)))
features &= ~dev->mangleid_features;
}
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 3/3] net: dsa: microchip: implement KSZ87xx Module 3 low-loss cable errata
From: Andrew Lunn @ 2026-03-26 12:18 UTC (permalink / raw)
To: Fidelio Lawson
Cc: Woojung Huh, UNGLinuxDriver, Vladimir Oltean, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Marek Vasut, Maxime Chevallier,
netdev, devicetree, linux-kernel, Fidelio Lawson
In-Reply-To: <20260326-ksz87xx_errata_low_loss_connections-v1-3-79a698f43626@exotec.com>
> + mutex_lock(&dev->alu_mutex);
> +
> + ret = ksz_write8(dev, regs[REG_IND_CTRL_0], 0xA0);
> +
> + if (!ret)
> + ret = ksz_write8(dev, 0x6F, indir_reg);
> +
> + if (!ret)
> + ret = ksz_write8(dev, regs[REG_IND_BYTE], indir_val);
> +
> + mutex_unlock(&dev->alu_mutex);
What address space are these registers in? Normally workarounds for a
PHY would be in the PHY driver. But that assumes the registers are
accessible from the PHY driver.
Andrew
^ permalink raw reply
* Re: [PATCH] net: wan/fsl_ucc_hdlc: cleanup ucc_hdlc_poll
From: Christophe Leroy (CS GROUP) @ 2026-03-26 12:17 UTC (permalink / raw)
To: Tomas Alvarez Vanoli, netdev, linuxppc-dev; +Cc: qiang.zhao, andrew+netdev
In-Reply-To: <20260326100232.904289-1-tomas.alvarez-vanoli@hitachienergy.com>
Le 26/03/2026 à 11:02, Tomas Alvarez Vanoli a écrit :
> Immediately after setting to 0 we are adding to it, and subtracting 0
> from budget. Replace with just assignment and no subtraction.
>
> Signed-off-by: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com>
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
> ---
> drivers/net/wan/fsl_ucc_hdlc.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
> index b72ab9951875e..3bd57527b1be6 100644
> --- a/drivers/net/wan/fsl_ucc_hdlc.c
> +++ b/drivers/net/wan/fsl_ucc_hdlc.c
> @@ -628,8 +628,7 @@ static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
> hdlc_tx_done(priv);
> spin_unlock(&priv->lock);
>
> - howmany = 0;
> - howmany += hdlc_rx_done(priv, budget - howmany);
> + howmany = hdlc_rx_done(priv, budget);
>
> if (howmany < budget) {
> napi_complete_done(napi, howmany);
> --
> 2.47.3
>
>
^ permalink raw reply
* Re: [PATCH net-next v35 0/8] eea: Add basic driver framework for Alibaba Elastic Ethernet Adaptor
From: Xuan Zhuo @ 2026-03-26 12:11 UTC (permalink / raw)
To: Paolo Abeni
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Wen Gu, Philo Lu, Vadim Fedorenko, Dong Yibo, Ethan Nelson-Moore,
Heiner Kallweit, Vivian Wang, Dust Li, netdev
In-Reply-To: <cddbd5e9-6df0-40df-9ae1-6a6f296b4061@redhat.com>
On Thu, 26 Mar 2026 13:06:14 +0100, Paolo Abeni <pabeni@redhat.com> wrote:
> On 3/26/26 12:38 PM, Xuan Zhuo wrote:
> > On Thu, 26 Mar 2026 12:26:33 +0100, Paolo Abeni <pabeni@redhat.com> wrote:
> >> On 3/23/26 8:44 AM, Xuan Zhuo wrote:
> >>> Add a driver framework for EEA that will be available in the future.
> >>>
> >>> This driver is currently quite minimal, implementing only fundamental
> >>> core functionalities. Key features include: I/O queue management via
> >>> adminq, basic PCI-layer operations, and essential RX/TX data
> >>> communication capabilities. It also supports the creation,
> >>> initialization, and management of network devices (netdev). Furthermore,
> >>> the ring structures for both I/O queues and adminq have been abstracted
> >>> into a simple, unified, and reusable library implementation,
> >>> facilitating future extension and maintenance.
> >>
> >> Unfortunately sashiko fund more stuff:
> >>
> >> https://sashiko.dev/#/patchset/20260323074441.91691-1-xuanzhuo%40linux.alibaba.com
> >>
> >> AFAIK checks vs malicious values from the H/W are not due, but stats
> >> endianness, 32-bits, truesize related concerns looks real.
> >
> > I've looked at this, and I think most of it is meaningless. For example, since
> > we have the following options,
> >
> > + depends on 64BIT
> >
> > there's no need to consider some 32-bit related issues. Many other points are
> > also unnecessary.
> >
> > I will go through these comments again. I'll try to fix them.
> > I might introduce some defensive programming. ^_^ Just to make the
> > AI happy. However, I can't make all these comments disappear.
> Please, don't add defensive programming for AI's sake. AI reviews are
> threaded alike other reviews: if there are valid argument to counter
> them, should be ignored. Please instead mention on the ML why specific
> comments are not relevant.
>
> Note that defensive checks vs rouge H/W are AFAIK not needed, no need to
> argument that.
Sashiko doesn't seem to check the discussions on lore, but
https://netdev-ai.bots.linux.dev/ should perform such checks.
So I'm not sure how to make Sashiko aware of the detailed context.
I will try to address the issues it currently reports. For the next version, I
hope to incorporate more manual review of Sashiko's reports.
Thanks.
>
> /P
>
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: dsa: microchip: add KSZ low-loss cable errata properties
From: Andrew Lunn @ 2026-03-26 12:14 UTC (permalink / raw)
To: Fidelio Lawson
Cc: Woojung Huh, UNGLinuxDriver, Vladimir Oltean, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Marek Vasut, Maxime Chevallier,
netdev, devicetree, linux-kernel, Fidelio Lawson
In-Reply-To: <20260326-ksz87xx_errata_low_loss_connections-v1-1-79a698f43626@exotec.com>
On Thu, Mar 26, 2026 at 10:10:21AM +0100, Fidelio Lawson wrote:
> Microchip KSZ87xx switches are affected by the "Module 3: Equalizer fix
> for short cables" erratum described in DS80000687C.
> The embedded PHY receivers are tuned for long, high-loss cables,
> which may cause signal distortion when operated with short or low-loss
> cabling such as CAT5e or CAT6. In these cases,
> the PHY may fail to establish a link due to internal over-amplification.
>
> Two workarounds are provided by Microchip, each configuring a different
> indirect register value to adjust the PHY equalizer settings.
>
> This patch introduces two new device tree properties to enable and
> select the appropriate workaround:
>
> - microchip,low-loss-errata-enable: boolean enabling the feature
> - microchip,low-loss-errata: selects workaround 1 or 2 (default: 1)
>
> These properties allow board designers to opt into the errata fix
> according to the targeted cable characteristics of their platform.
Does the errata give any indication how the two different workarounds
differ? How would a user decided which to use?
I also question if this should be a DT property. The length of the
cables is not a property of the board.
A PHY tunable would better reflect the same board can be used with
different cables, with different lengths/quality.
Andrew
^ permalink raw reply
* Re: [PATCH v3 4/4] rust: make `build_assert` module the home of related macros
From: FUJITA Tomonori @ 2026-03-26 12:09 UTC (permalink / raw)
To: miguel.ojeda.sandonis
Cc: gary, fujita.tomonori, acourbot, boqun.feng, tamird, a.hindborg,
ojeda, boqun, bjorn3_gh, lossin, aliceryhl, tmgross, dakr,
airlied, simona, abdiel.janulgue, daniel.almeida, robin.murphy,
yury.norov, will, peterz, mark.rutland, mingo, longman, ynorov,
rust-for-linux, nouveau, dri-devel, linux-kernel, driver-core,
netdev
In-Reply-To: <CANiq72kZH-AX=QQz2V+qCfVzMsUEAPan=o1E=OZOAnivj3L3HQ@mail.gmail.com>
On Mon, 23 Mar 2026 00:36:52 +0100
Miguel Ojeda <miguel.ojeda.sandonis@gmail.com> wrote:
> On Thu, Mar 19, 2026 at 1:17 PM Gary Guo <gary@kernel.org> wrote:
>>
>> rust/kernel/net/phy/reg.rs | 8 +++++---
>
> Tomonori: are you OK with these changes?
Acked-by: FUJITA Tomonori <fujita.tomonori@gmail.com>
^ permalink raw reply
* Re: [PATCH 2/2 net-next] ipv4: ipv4: handle devconf post-set actions on netlink updates
From: kernel test robot @ 2026-03-26 12:08 UTC (permalink / raw)
To: Fernando Fernandez Mancera, netdev
Cc: llvm, oe-kbuild-all, horms, pabeni, kuba, edumazet, dsahern,
davem, Fernando Fernandez Mancera
In-Reply-To: <20260325161020.3516-2-fmancera@suse.de>
Hi Fernando,
kernel test robot noticed the following build warnings:
[auto build test WARNING on net-next/main]
url: https://github.com/intel-lab-lkp/linux/commits/Fernando-Fernandez-Mancera/ipv4-ipv4-handle-devconf-post-set-actions-on-netlink-updates/20260326-020953
base: net-next/main
patch link: https://lore.kernel.org/r/20260325161020.3516-2-fmancera%40suse.de
patch subject: [PATCH 2/2 net-next] ipv4: ipv4: handle devconf post-set actions on netlink updates
config: x86_64-buildonly-randconfig-003-20260326 (https://download.01.org/0day-ci/archive/20260326/202603261933.hgl2CPHS-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260326/202603261933.hgl2CPHS-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603261933.hgl2CPHS-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> net/ipv4/devinet.c:2131:13: warning: function 'devinet_conf_post_set' has internal linkage but is not defined [-Wundefined-internal]
2131 | static bool devinet_conf_post_set(struct net *net, struct ipv4_devconf *cnf,
| ^
net/ipv4/devinet.c:2155:8: note: used here
2155 | if (devinet_conf_post_set(net, &in_dev->cnf, nla_type(a), new_value,
| ^
1 warning generated.
vim +/devinet_conf_post_set +2131 net/ipv4/devinet.c
2130
> 2131 static bool devinet_conf_post_set(struct net *net, struct ipv4_devconf *cnf,
2132 int attr, int new, int old, int index);
2133
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH net-next v35 0/8] eea: Add basic driver framework for Alibaba Elastic Ethernet Adaptor
From: Paolo Abeni @ 2026-03-26 12:06 UTC (permalink / raw)
To: Xuan Zhuo
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Wen Gu, Philo Lu, Vadim Fedorenko, Dong Yibo, Ethan Nelson-Moore,
Heiner Kallweit, Vivian Wang, Dust Li, netdev
In-Reply-To: <1774525085.4029815-1-xuanzhuo@linux.alibaba.com>
On 3/26/26 12:38 PM, Xuan Zhuo wrote:
> On Thu, 26 Mar 2026 12:26:33 +0100, Paolo Abeni <pabeni@redhat.com> wrote:
>> On 3/23/26 8:44 AM, Xuan Zhuo wrote:
>>> Add a driver framework for EEA that will be available in the future.
>>>
>>> This driver is currently quite minimal, implementing only fundamental
>>> core functionalities. Key features include: I/O queue management via
>>> adminq, basic PCI-layer operations, and essential RX/TX data
>>> communication capabilities. It also supports the creation,
>>> initialization, and management of network devices (netdev). Furthermore,
>>> the ring structures for both I/O queues and adminq have been abstracted
>>> into a simple, unified, and reusable library implementation,
>>> facilitating future extension and maintenance.
>>
>> Unfortunately sashiko fund more stuff:
>>
>> https://sashiko.dev/#/patchset/20260323074441.91691-1-xuanzhuo%40linux.alibaba.com
>>
>> AFAIK checks vs malicious values from the H/W are not due, but stats
>> endianness, 32-bits, truesize related concerns looks real.
>
> I've looked at this, and I think most of it is meaningless. For example, since
> we have the following options,
>
> + depends on 64BIT
>
> there's no need to consider some 32-bit related issues. Many other points are
> also unnecessary.
>
> I will go through these comments again. I'll try to fix them.
> I might introduce some defensive programming. ^_^ Just to make the
> AI happy. However, I can't make all these comments disappear.
Please, don't add defensive programming for AI's sake. AI reviews are
threaded alike other reviews: if there are valid argument to counter
them, should be ignored. Please instead mention on the ML why specific
comments are not relevant.
Note that defensive checks vs rouge H/W are AFAIK not needed, no need to
argument that.
/P
^ permalink raw reply
* Re: [PATCH net] ipv6: fix data race in fib6_metric_set() using cmpxchg
From: Eric Dumazet @ 2026-03-26 12:05 UTC (permalink / raw)
To: Hangbin Liu
Cc: David S. Miller, David Ahern, Jakub Kicinski, Paolo Abeni,
Simon Horman, David Ahern, netdev, linux-kernel, Fei Liu
In-Reply-To: <20260326-b4-fib6_metric_set-kmemleak-v1-1-c89fc1b312c0@gmail.com>
On Wed, Mar 25, 2026 at 9:22 PM Hangbin Liu <liuhangbin@gmail.com> wrote:
>
> fib6_metric_set() may be called concurrently from softirq context without
> holding the FIB table lock. A typical path is:
>
> ndisc_router_discovery()
> spin_unlock_bh(&table->tb6_lock) <- lock released
> fib6_metric_set(rt, RTAX_HOPLIMIT, ...) <- lockless call
>
> When two CPUs process Router Advertisement packets for the same router
> simultaneously, they can both arrive at fib6_metric_set() with the same
> fib6_info pointer whose fib6_metrics still points to dst_default_metrics.
>
> if (f6i->fib6_metrics == &dst_default_metrics) { /* both CPUs: true */
> struct dst_metrics *p = kzalloc_obj(*p, GFP_ATOMIC);
> refcount_set(&p->refcnt, 1);
> f6i->fib6_metrics = p; /* CPU1 overwrites CPU0's p -> p0 leaked */
> }
>
> The dst_metrics allocated by the losing CPU has refcnt=1 but no pointer
> to it anywhere in memory, producing a kmemleak report:
>
> unreferenced object 0xff1100025aca1400 (size 96):
> comm "softirq", pid 0, jiffies 4299271239
> backtrace:
> kmalloc_trace+0x28a/0x380
> fib6_metric_set+0xcd/0x180
> ndisc_router_discovery+0x12dc/0x24b0
> icmpv6_rcv+0xc16/0x1360
>
> Fix this by replacing the plain pointer store with cmpxchg() and free
> the allocation safely when competition failed.
>
> Fixes: d4ead6b34b67 ("net/ipv6: move metrics from dst to rt6_info")
> Reported-by: Fei Liu <feliu@redhat.com>
> Signed-off-by: Hangbin Liu <liuhangbin@gmail.com>
> ---
> net/ipv6/ip6_fib.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/net/ipv6/ip6_fib.c b/net/ipv6/ip6_fib.c
> index dd26657b6a4a..64de761f40d5 100644
> --- a/net/ipv6/ip6_fib.c
> +++ b/net/ipv6/ip6_fib.c
> @@ -730,14 +730,16 @@ void fib6_metric_set(struct fib6_info *f6i, int metric, u32 val)
> if (!f6i)
> return;
>
> - if (f6i->fib6_metrics == &dst_default_metrics) {
> + if (READ_ONCE(f6i->fib6_metrics) == &dst_default_metrics) {
> + struct dst_metrics *dflt = (struct dst_metrics *)&dst_default_metrics;
> struct dst_metrics *p = kzalloc_obj(*p, GFP_ATOMIC);
>
> if (!p)
> return;
>
> refcount_set(&p->refcnt, 1);
> - f6i->fib6_metrics = p;
> + if (cmpxchg(&f6i->fib6_metrics, dflt, p) != dflt)
> + kfree(p);
> }
>
The following line should happen before the cmpxchg(),
->metrics[X] accesses also need READ_ONCE()/WRITE_ONCE() annotations.
> f6i->fib6_metrics->metrics[metric - 1] = val;
>
> ---
> base-commit: c4ea7d8907cf72b259bf70bd8c2e791e1c4ff70f
> change-id: 20260326-b4-fib6_metric_set-kmemleak-7aa51978284a
>
> Best regards,
> --
> Hangbin Liu <liuhangbin@gmail.com>
>
^ permalink raw reply
* [PATCH net-next v2 4/4] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver
From: Louis-Alexis Eyraud @ 2026-03-26 12:04 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260326-add-airoha-an8801-support-v2-0-1a42d6b6050f@collabora.com>
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Introduce a driver for the Airoha AN8801R Series Gigabit Ethernet
PHY; this currently supports setting up PHY LEDs, 10/100M, 1000M
speeds, and Wake on LAN and PHY interrupts.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_an8801.c | 1115 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1122 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index b6b1cde7e51fa1e470bfe210c8764a193449acb5..4dd77ba487763eaf16c2b390feb237e667f76746 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -90,6 +90,12 @@ config AS21XXX_PHY
AS21210PB1 that all register with the PHY ID 0x7500 0x7500
before the firmware is loaded.
+config AIR_AN8801_PHY
+ tristate "Airoha AN8801 Gigabit PHY"
+ select AIR_NET_PHYLIB
+ help
+ Currently supports the Airoha AN8801R PHY.
+
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
select AIR_NET_PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 7cf1fa9e12cb6073a9e68c0ffa6284b361b80487..de660ae949453d99f8a383ca0c0e3cf3f1a14922 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -29,6 +29,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
+obj-$(CONFIG_AIR_AN8801_PHY) += air_an8801.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
diff --git a/drivers/net/phy/air_an8801.c b/drivers/net/phy/air_an8801.c
new file mode 100644
index 0000000000000000000000000000000000000000..53ade9665fe9e08010fe208f760051f1b621a128
--- /dev/null
+++ b/drivers/net/phy/air_an8801.c
@@ -0,0 +1,1115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for the Airoha AN8801 Gigabit PHY.
+ *
+ * Copyright (C) 2025 Airoha Technology Corp.
+ * Copyright (C) 2025 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/pm_wakeirq.h>
+
+#include "air_phy_lib.h"
+
+#define AN8801R_PHY_ID 0xc0ff0421
+
+/* MII Registers */
+
+/* MII Registers - Airoha Page 1 */
+#define AN8801_EXT_REG_PHY 0x14
+#define AN8801_EXT_PHY_STATUS0 GENMASK(1, 0)
+#define AN8801_EXT_PHY_DOWNSHIFT_CTL GENMASK(3, 2) /* 2 to 5 1G auto-neg attempts (0..3) */
+#define AN8801_EXT_PHY_DOWNSHIFT_EN BIT(4)
+#define AN8801_EXT_PHY_CTRL0 BIT(5)
+#define AN8801_EXT_PHY_STATUS1 GENMASK(8, 6)
+#define AN8801_EXT_PHY_CTRL1 GENMASK(14, 9)
+
+/* MII Registers - Airoha Page 4 */
+#define AN8801_PBUS_ACCESS BIT(28)
+#define AN8801_PBUS_EPHY_ACCESS BIT(24)
+#define AN8801_PBUS_CL22_ACCESS BIT(23)
+
+/* BPBUS Registers */
+#define AN8801_BPBUS_REG_LED_GPIO 0x54
+#define AN8801_BPBUS_REG_LED_ID_SEL 0x58
+#define LED_ID_GPIO_SEL(led, gpio) ((led) << ((gpio) * 3))
+#define AN8801_BPBUS_REG_GPIO_MODE 0x70
+#define AN8801_BPBUS_REG_PHY_IRQ_GPIO 0x7c
+#define AN8801_PHY_IRQ_GPIO_NUM_MASK GENMASK(19, 16)
+#define AN8801_PHY_IRQ_GPIO_NUM 1
+
+#define AN8801_BPBUS_REG_CKO 0x1a4
+#define AN8801_CKO_OUTPUT_MODE_AUTO 3
+
+#define AN8801_BPBUS_REG_LINK_MODE 0x5054
+#define AN8801_BPBUS_LINK_MODE_1000 BIT(0)
+
+#define AN8801_BPBUS_REG_BYPASS_PTP 0x21c004
+#define AN8801_BYP_PTP_SGMII_TO_GPHY BIT(8)
+#define AN8801_BYP_PTP_RGMII_TO_GPHY BIT(0)
+
+#define AN8801_BPBUS_REG_TXDLY_STEP 0x21c024
+#define RGMII_DELAY_STEP_MASK GENMASK(2, 0)
+#define RGMII_DELAY_NO_STEP 0
+#define RGMII_DELAY_STEP_1 1
+#define RGMII_DELAY_STEP_2 2
+#define RGMII_DELAY_STEP_3 3
+#define RGMII_DELAY_STEP_4 4
+#define RGMII_DELAY_STEP_5 5
+#define RGMII_DELAY_STEP_6 6
+#define RGMII_DELAY_STEP_7 7
+#define RGMII_TXDELAY_FORCE_MODE BIT(24)
+
+#define AN8801_RGMII_TXDELAY_DEFAULT RGMII_DELAY_STEP_4 /* 1.883ns delay */
+
+#define AN8801_BPBUS_REG_RXDLY_STEP 0x21c02c
+#define RGMII_RXDELAY_ALIGN BIT(4)
+#define RGMII_RXDELAY_FORCE_MODE BIT(24)
+
+#define AN8801_RGMII_RXDELAY_DEFAULT RGMII_DELAY_NO_STEP /* 1.992ns delay */
+
+#define AN8801_BPBUS_REG_EFIFO_CTL(x) (0x270004 + (0x100 * (x))) /* 0..2 */
+#define AN8801_EFIFO_ALL_EN GENMASK(7, 0)
+#define AN8801_EFIFO_RX_EN BIT(0)
+#define AN8801_EFIFO_TX_EN BIT(1)
+#define AN8801_EFIFO_RX_CLK_EN BIT(2)
+#define AN8801_EFIFO_TX_CLK_EN BIT(3)
+#define AN8801_EFIFO_RX_EEE_EN BIT(4)
+#define AN8801_EFIFO_TX_EEE_EN BIT(5)
+#define AN8801_EFIFO_RX_ODD_NIBBLE_EN BIT(6)
+#define AN8801_EFIFO_TX_ODD_NIBBLE_EN BIT(7)
+
+#define AN8801_BPBUS_REG_WOL_MAC_16_47 0x285114
+#define AN8801_BPBUS_REG_WOL_MAC_0_15 0x285118
+
+#define AN8801_BPBUS_REG_WAKEUP_CTL1 0x285400
+#define AN8801_WOL_WAKE_MAGIC_EN GENMASK(3, 1)
+#define AN8801_WOL_WAKE_LNKCHG_EN BIT(4)
+
+#define AN8801_BPBUS_REG_WAKEUP_CTL2 0x285404
+#define AN8801_WAKE_OUT_TYPE_PULSE BIT(0) /* Set/Unset: Pulse/Static */
+#define AN8801_WAKE_OUT_POLARITY_NEG BIT(1) /* Set/Unset: Negative/Positive */
+#define AN8801_WAKE_OUT_WIDTH GENMASK(2, 3)
+#define AN8801_WAKE_OUT_84MS 0
+#define AN8801_WAKE_OUT_168MS 1
+#define AN8801_WAKE_OUT_336MS 2
+#define AN8801_WAKE_OUT_672MS 3
+#define AN8801_WAKE_OUT_EN BIT(4)
+#define AN8801_PME_WAKEUP_CLR BIT(8)
+
+#define AN8801_BPBUS_REG_WAKE_IRQ_EN 0x285700
+#define AN8801_BPBUS_REG_WAKE_IRQ_STS 0x285704
+#define AN8801_IRQ_WAKE_LNKCHG BIT(0) /* Wake on link change */
+#define AN8801_IRQ_WAKE_UNIPKT BIT(1) /* Wake on unicast packet */
+#define AN8801_IRQ_WAKE_MULPKT BIT(2) /* Wake on multicast packet */
+#define AN8801_IRQ_WAKE_BCPKT BIT(3) /* Wake on broadcast packet */
+#define AN8801_IRQ_WAKE_MAGICPKT BIT(4) /* Wake on magic packet */
+#define AN8801_IRQ_WAKE_ALL GENMASK(4, 0)
+
+/* MDIO_MMD_VEND1 Registers */
+#define AN8801_PHY_TX_PAIR_DLY_SEL_GBE 0x13
+#define AN8801_PHY_PAIR_DLY_SEL_A_GBE GENMASK(14, 12)
+#define AN8801_PHY_PAIR_DLY_SEL_B_GBE GENMASK(10, 8)
+#define AN8801_PHY_PAIR_DLY_SEL_C_GBE GENMASK(6, 4)
+#define AN8801_PHY_PAIR_DLY_SEL_D_GBE GENMASK(2, 0)
+#define AN8801_PHY_RXADC_CTRL 0xd8
+#define AN8801_PHY_RXADC_SAMP_PHSEL_A BIT(12)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_B BIT(8)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_C BIT(4)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_D BIT(0)
+#define AN8801_PHY_RXADC_REV_0 0xd9
+#define AN8801_PHY_RXADC_REV_MASK_A GENMASK(15, 8)
+#define AN8801_PHY_RXADC_REV_MASK_B GENMASK(7, 0)
+#define AN8801_PHY_RXADC_REV_1 0xda
+#define AN8801_PHY_RXADC_REV_MASK_C GENMASK(15, 8)
+#define AN8801_PHY_RXADC_REV_MASK_D GENMASK(7, 0)
+
+/* MDIO_MMD_VEND2 Registers */
+#define LED_BCR 0x21
+#define LED_BCR_MODE_MASK GENMASK(1, 0)
+#define LED_BCR_TIME_TEST BIT(2)
+#define LED_BCR_CLK_EN BIT(3)
+#define LED_BCR_EVT_ALL BIT(4)
+#define LED_BCR_EXT_CTRL BIT(15)
+#define LED_BCR_MODE_DISABLE 0
+#define LED_BCR_MODE_2LED 1
+#define LED_BCR_MODE_3LED_1 2
+#define LED_BCR_MODE_3LED_2 3
+
+#define LED_ON_DUR 0x22
+#define LED_ON_DUR_MASK GENMASK(15, 0)
+
+#define LED_BLINK_DUR 0x23
+#define LED_BLINK_DUR_MASK GENMASK(15, 0)
+
+#define LED_ON_CTRL(i) (0x24 + ((i) * 2))
+#define LED_ON_EVT_MASK GENMASK(6, 0)
+#define LED_ON_EVT_LINK_1000M BIT(0)
+#define LED_ON_EVT_LINK_100M BIT(1)
+#define LED_ON_EVT_LINK_10M BIT(2)
+#define LED_ON_EVT_LINK_DN BIT(3)
+#define LED_ON_EVT_FDX BIT(4)
+#define LED_ON_EVT_HDX BIT(5)
+#define LED_ON_EVT_FORCE BIT(6)
+#define LED_ON_POL BIT(14)
+#define LED_ON_EN BIT(15)
+
+#define LED_BLINK_CTRL(i) (0x25 + ((i) * 2))
+#define LED_BLINK_EVT_MASK GENMASK(9, 0)
+#define LED_BLINK_EVT_1000M_TX BIT(0)
+#define LED_BLINK_EVT_1000M_RX BIT(1)
+#define LED_BLINK_EVT_100M_TX BIT(2)
+#define LED_BLINK_EVT_100M_RX BIT(3)
+#define LED_BLINK_EVT_10M_TX BIT(4)
+#define LED_BLINK_EVT_10M_RX BIT(5)
+#define LED_BLINK_EVT_COLLISION BIT(6)
+#define LED_BLINK_EVT_RX_CRC_ERR BIT(7)
+#define LED_BLINK_EVT_RX_IDLE_ERR BIT(8)
+#define LED_BLINK_EVT_FORCE BIT(9)
+
+#define AN8801R_NUM_LEDS 3
+#define AN8801_PERIOD_SHIFT 15
+#define AN8801_PERIOD_UNIT 32768 /* (1 << AN8801_PERIOD_SHIFT) */
+#define AN8801_MAX_PERIOD_MS 2147
+
+#define LED_BLINK_DURATION_UNIT 780
+#define LED_BLINK_DURATION(f) (LED_BLINK_DURATION_UNIT << (f))
+
+#define AN8801_LED_DURATION_UNIT_US 32768
+
+#define AN8801_REG_PHY_INTERNAL0 0x600
+#define AN8801_REG_PHY_INTERNAL1 0x601
+#define AN8801_PHY_INTFUNC_MASK GENMASK(15, 0) /* PHY internal functions */
+
+enum an8801r_led_fn {
+ AN8801R_LED_FN_NONE,
+ AN8801R_LED_FN_LINK,
+ AN8801R_LED_FN_ACTIVITY,
+ AN8801R_LED_FN_MAX,
+};
+
+struct an8801r_priv {
+ bool wake_magic_enabled;
+ bool wake_lnkchg_enabled;
+};
+
+static int an8801_buckpbus_reg_rmw(struct phy_device *phydev,
+ u32 addr, u32 mask, u32 set)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, set);
+}
+
+static int an8801_buckpbus_reg_set_bits(struct phy_device *phydev,
+ u32 addr, u32 mask)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, mask);
+}
+
+static int an8801_buckpbus_reg_clear_bits(struct phy_device *phydev,
+ u32 addr, u32 mask)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, 0);
+}
+
+static int an8801_buckpbus_reg_write(struct phy_device *phydev, u32 addr,
+ u32 data)
+{
+ return air_phy_buckpbus_reg_write(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ data);
+}
+
+static int an8801_buckpbus_reg_read(struct phy_device *phydev, u32 addr,
+ u32 *data)
+{
+ return air_phy_buckpbus_reg_read(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ data);
+}
+
+static u32 an8801r_led_blink_ms_to_hw(unsigned long req_ms)
+{
+ u32 req_ns, regval;
+
+ if (req_ms > AN8801_MAX_PERIOD_MS)
+ req_ms = AN8801_MAX_PERIOD_MS;
+
+ req_ns = req_ms * 1000000;
+
+ /* Round to the nearest period unit... */
+ regval = req_ns + (AN8801_PERIOD_UNIT / 2);
+
+ /* ...and now divide by the full period */
+ regval >>= AN8801_PERIOD_SHIFT;
+
+ return regval;
+}
+
+static int an8801r_led_blink_set(struct phy_device *phydev, u8 index,
+ unsigned long *delay_on,
+ unsigned long *delay_off)
+{
+ u32 hw_delay_on, hw_delay_off;
+ bool blink;
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ if (delay_on && delay_off) {
+ blink = true;
+
+ if (*delay_on == 0 || *delay_off == 0) {
+ *delay_on = 64;
+ *delay_off = 64;
+ }
+
+ hw_delay_on = an8801r_led_blink_ms_to_hw(*delay_on);
+ hw_delay_off = an8801r_led_blink_ms_to_hw(*delay_off);
+ } else {
+ blink = false;
+ }
+
+ if (blink) {
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_DUR,
+ LED_BLINK_DURATION(hw_delay_on));
+ if (ret)
+ goto error;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_DUR,
+ LED_BLINK_DURATION(hw_delay_off) >> 1);
+ if (ret)
+ goto error;
+ }
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, blink ? LED_ON_EN : 0);
+ if (ret)
+ return ret;
+
+ return 0;
+error:
+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, 0);
+ return ret;
+}
+
+static int an8801r_led_brightness_set(struct phy_device *phydev, u8 index,
+ enum led_brightness value)
+{
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK,
+ (value == LED_OFF) ? 0 : LED_ON_EVT_FORCE);
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, (value == LED_OFF) ? 0 : LED_ON_EN);
+}
+
+static int an8801r_led_hw_control_get(struct phy_device *phydev, u8 index,
+ unsigned long *rules)
+{
+ int on, blink;
+
+ on = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index));
+ if (on < 0)
+ return on;
+
+ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index));
+ if (blink < 0)
+ return blink;
+
+ if (FIELD_GET(LED_ON_EVT_LINK_10M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_10, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_100M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_100, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_1000M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_10M, on) &&
+ FIELD_GET(LED_ON_EVT_LINK_100M, on) &&
+ FIELD_GET(LED_ON_EVT_LINK_1000M, on))
+ __set_bit(TRIGGER_NETDEV_LINK, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_10M_RX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_100M_RX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_1000M_RX, blink))
+ __set_bit(TRIGGER_NETDEV_RX, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_10M_TX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_100M_TX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_1000M_TX, blink))
+ __set_bit(TRIGGER_NETDEV_TX, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_RX_CRC_ERR, blink))
+ __set_bit(TRIGGER_NETDEV_RX_ERR, rules);
+
+ return 0;
+}
+
+static int an8801r_led_trig_to_hw(unsigned long rules, u16 *on, u16 *blink)
+{
+ if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+ *on |= LED_ON_EVT_LINK_10M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
+ *on |= LED_ON_EVT_LINK_100M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
+ *on |= LED_ON_EVT_LINK_1000M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK, &rules)) {
+ *on |= LED_ON_EVT_LINK_10M;
+ *on |= LED_ON_EVT_LINK_100M;
+ *on |= LED_ON_EVT_LINK_1000M;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_RX, &rules)) {
+ *blink |= LED_BLINK_EVT_10M_RX;
+ *blink |= LED_BLINK_EVT_100M_RX;
+ *blink |= LED_BLINK_EVT_1000M_RX;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_TX, &rules)) {
+ *blink |= LED_BLINK_EVT_10M_TX;
+ *blink |= LED_BLINK_EVT_100M_TX;
+ *blink |= LED_BLINK_EVT_1000M_TX;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_RX_ERR, &rules))
+ *blink |= LED_BLINK_EVT_RX_CRC_ERR;
+
+ if (rules && !*on && !*blink)
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+
+static int an8801r_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+{
+ u16 on = 0, blink = 0;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ return an8801r_led_trig_to_hw(rules, &on, &blink);
+}
+
+static int an8801r_led_hw_control_set(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+{
+ u16 on = 0, blink = 0;
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ ret = an8801r_led_trig_to_hw(rules, &on, &blink);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK, on);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index),
+ LED_BLINK_EVT_MASK, blink);
+
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, on | blink ? LED_ON_EN : 0);
+}
+
+static int an8801r_led_polarity_set(struct phy_device *phydev, int index,
+ unsigned long modes)
+{
+ unsigned long mode;
+ bool active_high;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+ switch (mode) {
+ case PHY_LED_ACTIVE_HIGH:
+ active_high = true;
+ break;
+ case PHY_LED_ACTIVE_LOW:
+ active_high = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_POL, active_high ? LED_ON_POL : 0);
+}
+
+static int an8801r_led_init(struct phy_device *phydev, u8 *led_cfg)
+{
+ int led_id, ret;
+
+ /* Set LED BCR Enable */
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, LED_BCR,
+ LED_BCR_EXT_CTRL | LED_BCR_CLK_EN);
+ if (ret)
+ return ret;
+
+ for (led_id = 0; led_id < AN8801R_NUM_LEDS; led_id++) {
+ unsigned long led_trigger = 0;
+ u32 led_gpio = led_id + 1;
+
+ switch (led_cfg[led_id]) {
+ case AN8801R_LED_FN_LINK:
+ led_trigger = BIT(TRIGGER_NETDEV_LINK);
+ break;
+ case AN8801R_LED_FN_ACTIVITY:
+ led_trigger = BIT(TRIGGER_NETDEV_RX) |
+ BIT(TRIGGER_NETDEV_TX);
+ break;
+ default:
+ led_trigger = 0;
+ break;
+ }
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_LED_GPIO,
+ BIT(led_gpio));
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_LED_ID_SEL,
+ LED_ID_GPIO_SEL(led_id,
+ led_gpio));
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_GPIO_MODE,
+ BIT(led_gpio));
+ if (ret)
+ return ret;
+
+ if (!led_trigger)
+ continue;
+
+ ret = an8801r_led_hw_control_set(phydev, led_id, led_trigger);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+
+static int an8801r_reset_wake(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ u32 reg_val = 0;
+ int ret;
+
+ /* Enable wakeup clear and disable wake up output */
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2,
+ AN8801_PME_WAKEUP_CLR |
+ AN8801_WAKE_OUT_POLARITY_NEG);
+ if (ret)
+ return ret;
+
+ /* Clear WAKEUP_CTL1 register before enabling the wakeup events
+ * again
+ */
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ 0);
+ if (ret)
+ return ret;
+
+ if (priv->wake_magic_enabled)
+ reg_val |= AN8801_WOL_WAKE_MAGIC_EN;
+
+ if (priv->wake_lnkchg_enabled)
+ reg_val |= AN8801_WOL_WAKE_LNKCHG_EN;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ reg_val);
+ if (ret)
+ return ret;
+
+ /* Disable wake up clear and re-enable wake up output */
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2,
+ AN8801_WAKE_OUT_POLARITY_NEG |
+ AN8801_WAKE_OUT_EN);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int an8801r_ack_interrupt(struct phy_device *phydev)
+{
+ int ret;
+
+ /* Reset wake status */
+ ret = an8801r_reset_wake(phydev);
+ if (ret)
+ return ret;
+
+ /* Clear the interrupts by writing the reg */
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
+ AN8801_IRQ_WAKE_ALL);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int an8801r_config_intr(struct phy_device *phydev)
+{
+ int ret;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ u32 val = FIELD_PREP(AN8801_PHY_IRQ_GPIO_NUM_MASK,
+ AN8801_PHY_IRQ_GPIO_NUM);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_PHY_IRQ_GPIO,
+ val);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+
+ } else {
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_PHY_IRQ_GPIO,
+ 0);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+ }
+
+ ret = an8801r_ack_interrupt(phydev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static irqreturn_t an8801r_handle_interrupt(struct phy_device *phydev)
+{
+ u32 irq_status = 0;
+ int ret;
+
+ ret = an8801_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
+ &irq_status);
+ if (ret)
+ return ret;
+
+ ret = an8801r_ack_interrupt(phydev);
+ if (ret)
+ return IRQ_NONE;
+
+ if (irq_status & AN8801_IRQ_WAKE_MAGICPKT) {
+ pm_wakeup_event(&phydev->mdio.dev, 0);
+ return IRQ_HANDLED;
+ }
+
+ if (irq_status & AN8801_IRQ_WAKE_LNKCHG) {
+ phy_trigger_machine(phydev);
+ return IRQ_HANDLED;
+ }
+
+ return IRQ_NONE;
+}
+
+static void an8801r_get_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ u32 reg_val;
+
+ /* If the PHY is not capable of waking the system, then WoL can not
+ * be supported.
+ */
+ if (!device_can_wakeup(&phydev->mdio.dev)) {
+ wol->supported = 0;
+ return;
+ }
+
+ wol->supported = WAKE_MAGIC;
+
+ an8801_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ ®_val);
+
+ if (reg_val & AN8801_WOL_WAKE_MAGIC_EN)
+ wol->wolopts |= WAKE_MAGIC;
+ else
+ wol->wolopts &= ~WAKE_MAGIC;
+}
+
+static int an8801r_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct net_device *attach_dev = phydev->attached_dev;
+ const unsigned char *macaddr = attach_dev->dev_addr;
+ struct an8801r_priv *priv = phydev->priv;
+ u32 reg_val;
+ int ret;
+
+ if (!device_can_wakeup(&phydev->mdio.dev))
+ return -EOPNOTSUPP;
+
+ if (wol->wolopts & WAKE_MAGIC) {
+ /* MAC bits 16..47 */
+ reg_val = (macaddr[2] << 24) | (macaddr[3] << 16);
+ reg_val |= (macaddr[4] << 8) | (macaddr[5]);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_WOL_MAC_16_47,
+ reg_val);
+ if (ret)
+ return ret;
+
+ /* MAC bits 0..15 */
+ reg_val = (macaddr[0] << 8) | (macaddr[1]);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_WOL_MAC_0_15,
+ reg_val);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_MAGIC_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_MAGICPKT);
+ if (ret)
+ return ret;
+
+ } else {
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_MAGIC_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_MAGICPKT);
+ if (ret)
+ return ret;
+ }
+
+ priv->wake_magic_enabled = !!(wol->wolopts & WAKE_MAGIC);
+
+ device_set_wakeup_enable(&phydev->mdio.dev,
+ priv->wake_magic_enabled);
+
+ return 0;
+}
+
+static int an8801r_of_init_leds(struct phy_device *phydev, u8 *led_cfg)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *leds;
+ u32 function_enum_idx;
+ int ret;
+
+ if (!np)
+ return 0;
+
+ /* If devicetree is present, leds configuration is required */
+ leds = of_get_child_by_name(np, "leds");
+ if (!leds)
+ return 0;
+
+ for_each_available_child_of_node_scoped(leds, led) {
+ u32 led_idx;
+
+ ret = of_property_read_u32(led, "reg", &led_idx);
+ if (ret)
+ goto out;
+
+ if (led_idx >= AN8801R_NUM_LEDS) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = of_property_read_u32(led, "function-enumerator",
+ &function_enum_idx);
+ if (ret)
+ function_enum_idx = AN8801R_LED_FN_NONE;
+
+ if (function_enum_idx >= AN8801R_LED_FN_MAX) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ led_cfg[led_idx] = function_enum_idx;
+ }
+out:
+ of_node_put(leds);
+ return ret;
+}
+
+static int an8801r_rgmii_rxdelay(struct phy_device *phydev, bool enable,
+ u16 delay_steps)
+{
+ u32 reg_val;
+
+ if (delay_steps > RGMII_DELAY_STEP_MASK)
+ return -EINVAL;
+
+ if (enable) {
+ reg_val = delay_steps & RGMII_DELAY_STEP_MASK;
+
+ /* Set align bit to add extra offset for RX delay */
+ reg_val |= RGMII_RXDELAY_ALIGN;
+
+ /* Set force mode bit to enable RX delay insertion */
+ reg_val |= RGMII_RXDELAY_FORCE_MODE;
+ } else {
+ reg_val = 0;
+ }
+
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_RXDLY_STEP,
+ reg_val);
+}
+
+static int an8801r_rgmii_txdelay(struct phy_device *phydev, bool enable,
+ u16 delay_steps)
+{
+ u32 reg_val;
+
+ if (delay_steps > RGMII_DELAY_STEP_MASK)
+ return -EINVAL;
+
+ if (enable) {
+ reg_val = delay_steps & RGMII_DELAY_STEP_MASK;
+
+ /* Set force mode bit to enable TX delay insertion */
+ reg_val |= RGMII_TXDELAY_FORCE_MODE;
+ } else {
+ reg_val = 0;
+ }
+
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_TXDLY_STEP,
+ reg_val);
+}
+
+static int an8801r_rgmii_delay_config(struct phy_device *phydev)
+{
+ bool enable_delay;
+ u16 delay_step;
+ int ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ enable_delay = true;
+ delay_step = AN8801_RGMII_TXDELAY_DEFAULT;
+ } else {
+ enable_delay = false;
+ delay_step = RGMII_DELAY_NO_STEP;
+ }
+
+ ret = an8801r_rgmii_txdelay(phydev, enable_delay, delay_step);
+ if (ret)
+ return ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+ enable_delay = true;
+ delay_step = AN8801_RGMII_RXDELAY_DEFAULT;
+ } else {
+ enable_delay = false;
+ delay_step = RGMII_DELAY_NO_STEP;
+ }
+
+ ret = an8801r_rgmii_rxdelay(phydev, enable_delay, delay_step);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int an8801r_config_init(struct phy_device *phydev)
+{
+ u8 led_default_function[AN8801R_NUM_LEDS] = { 0 };
+ int ret;
+
+ ret = an8801r_of_init_leds(phydev, led_default_function);
+ if (ret)
+ return ret;
+
+ /* Disable Low Power Mode (LPM) */
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL0,
+ FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x1e));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL1,
+ FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x2));
+ if (ret)
+ return ret;
+
+ /* Set the PHY to perform auto-downshift after 3 auto-negotiation
+ * attempts
+ */
+ ret = phy_write_paged(phydev, AIR_PHY_PAGE_EXTENDED_1,
+ AN8801_EXT_REG_PHY,
+ FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d) |
+ FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
+ AN8801_EXT_PHY_DOWNSHIFT_EN);
+ if (ret < 0)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_BYPASS_PTP,
+ AN8801_BYP_PTP_RGMII_TO_GPHY);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(0),
+ AN8801_EFIFO_RX_EN |
+ AN8801_EFIFO_TX_EN |
+ AN8801_EFIFO_RX_CLK_EN |
+ AN8801_EFIFO_TX_CLK_EN |
+ AN8801_EFIFO_RX_EEE_EN |
+ AN8801_EFIFO_TX_EEE_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(1),
+ AN8801_EFIFO_ALL_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(2),
+ AN8801_EFIFO_ALL_EN);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ AN8801_PHY_TX_PAIR_DLY_SEL_GBE,
+ FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_A_GBE, 4) |
+ FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_C_GBE, 4));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_CTRL,
+ AN8801_PHY_RXADC_SAMP_PHSEL_A |
+ AN8801_PHY_RXADC_SAMP_PHSEL_C);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_0,
+ FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_A, 1));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_1,
+ FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_C, 1));
+ if (ret)
+ return ret;
+
+ ret = an8801r_rgmii_delay_config(phydev);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_CKO,
+ AN8801_CKO_OUTPUT_MODE_AUTO);
+ if (ret)
+ return ret;
+
+ ret = an8801r_led_init(phydev, led_default_function);
+ if (ret) {
+ phydev_err(phydev, "Cannot initialize LEDs: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int an8801r_read_status(struct phy_device *phydev)
+{
+ int prev_speed, ret;
+ u32 val;
+
+ prev_speed = phydev->speed;
+
+ ret = genphy_read_status(phydev);
+ if (ret)
+ return ret;
+
+ if (phydev->link && prev_speed != phydev->speed) {
+ val = phydev->speed == SPEED_1000 ?
+ AN8801_BPBUS_LINK_MODE_1000 : 0;
+
+ return an8801_buckpbus_reg_rmw(phydev,
+ AN8801_BPBUS_REG_LINK_MODE,
+ AN8801_BPBUS_LINK_MODE_1000,
+ val);
+ };
+
+ return 0;
+}
+
+static int an8801r_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct an8801r_priv *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->wake_lnkchg_enabled = true;
+
+ phydev->priv = priv;
+
+ /* Mark this PHY as wakeup capable and register the interrupt as a
+ * wakeup IRQ if the PHY is marked as a wakeup source in devicetree,
+ * and the interrupt is valid.
+ */
+ if (of_property_read_bool(dev->of_node, "wakeup-source") &&
+ phy_interrupt_is_valid(phydev)) {
+ device_set_wakeup_capable(dev, true);
+ devm_pm_set_wake_irq(dev, phydev->irq);
+ }
+
+ return 0;
+}
+
+static int an8801r_suspend(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ int ret;
+
+ /* If the PHY may wake up by a wake-on-line event, disable the link
+ * interrupt to only keep the WOL magic interrupt enabled
+ */
+ if (device_may_wakeup(&phydev->mdio.dev)) {
+ priv->wake_lnkchg_enabled = false;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+
+ /* Reset Wol status */
+ ret = an8801r_reset_wake(phydev);
+ if (ret)
+ return ret;
+ }
+
+ if (!phydev->wol_enabled)
+ return genphy_suspend(phydev);
+
+ return 0;
+}
+
+static int an8801r_resume(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ int ret;
+
+ ret = genphy_resume(phydev);
+ if (ret)
+ return ret;
+
+ /* Restore the interrupt enable so phylib can receive link
+ * state interrupts.
+ */
+ if (device_may_wakeup(&phydev->mdio.dev)) {
+ priv->wake_lnkchg_enabled = true;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_LNKCHG_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct phy_driver airoha_driver[] = {
+{
+ PHY_ID_MATCH_MODEL(AN8801R_PHY_ID),
+ .name = "Airoha AN8801R",
+ .probe = an8801r_probe,
+ .config_init = an8801r_config_init,
+ .suspend = an8801r_suspend,
+ .resume = an8801r_resume,
+ .config_aneg = genphy_config_aneg,
+ .read_status = an8801r_read_status,
+ .config_intr = an8801r_config_intr,
+ .handle_interrupt = an8801r_handle_interrupt,
+ .set_wol = an8801r_set_wol,
+ .get_wol = an8801r_get_wol,
+ .read_page = air_phy_read_page,
+ .write_page = air_phy_write_page,
+ .flags = PHY_ALWAYS_CALL_SUSPEND,
+ .led_brightness_set = an8801r_led_brightness_set,
+ .led_blink_set = an8801r_led_blink_set,
+ .led_hw_is_supported = an8801r_led_hw_is_supported,
+ .led_hw_control_set = an8801r_led_hw_control_set,
+ .led_hw_control_get = an8801r_led_hw_control_get,
+ .led_polarity_set = an8801r_led_polarity_set,
+} };
+module_phy_driver(airoha_driver);
+
+static struct mdio_device_id __maybe_unused an8801_tbl[] = {
+ { PHY_ID_MATCH_MODEL(AN8801R_PHY_ID) },
+ { }
+};
+MODULE_DEVICE_TABLE(mdio, an8801_tbl);
+
+MODULE_DESCRIPTION("Airoha AN8801 PHY driver");
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_LICENSE("GPL");
--
2.53.0
^ permalink raw reply related
* [PATCH net-next v2 3/4] net: phy: air_phy_lib: Factorize BuckPBus register accessors
From: Louis-Alexis Eyraud @ 2026-03-26 12:04 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260326-add-airoha-an8801-support-v2-0-1a42d6b6050f@collabora.com>
In preparation of Airoha AN8801R PHY support, move the BuckPBus
register accessors and definitions, present in air_en8811h driver,
into the Airoha PHY shared code (air_phy_lib), so they will be usable
by the new driver without duplicating them.
Also, update air_en8811h driver to use the new function names.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_en8811h.c | 303 ++++++++----------------------------------
drivers/net/phy/air_phy_lib.c | 180 +++++++++++++++++++++++++
drivers/net/phy/air_phy_lib.h | 23 ++++
3 files changed, 259 insertions(+), 247 deletions(-)
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index be7c3426182a26fe3799b875827750e7772caadd..a42898ae41358fe86072a55528a0ecff0eb5ec19 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -42,22 +42,6 @@
#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-#define AIR_PHY_PAGE_STANDARD 0x0000
-#define AIR_PHY_PAGE_EXTENDED_4 0x0004
-
-/* MII Registers Page 4*/
-#define AIR_BPBUS_MODE 0x10
-#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
-#define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
-#define AIR_BPBUS_WR_ADDR_HIGH 0x11
-#define AIR_BPBUS_WR_ADDR_LOW 0x12
-#define AIR_BPBUS_WR_DATA_HIGH 0x13
-#define AIR_BPBUS_WR_DATA_LOW 0x14
-#define AIR_BPBUS_RD_ADDR_HIGH 0x15
-#define AIR_BPBUS_RD_ADDR_LOW 0x16
-#define AIR_BPBUS_RD_DATA_HIGH 0x17
-#define AIR_BPBUS_RD_DATA_LOW 0x18
-
/* Registers on MDIO_MMD_VEND1 */
#define EN8811H_PHY_FW_STATUS 0x8009
#define EN8811H_PHY_READY 0x02
@@ -245,183 +229,6 @@ static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX);
-static int __air_buckpbus_reg_write(struct phy_device *phydev,
- u32 pbus_address, u32 pbus_data)
-{
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
- upper_16_bits(pbus_data));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
- lower_16_bits(pbus_data));
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-static int air_buckpbus_reg_write(struct phy_device *phydev,
- u32 pbus_address, u32 pbus_data)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_write(phydev, pbus_address,
- pbus_data);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
-static int __air_buckpbus_reg_read(struct phy_device *phydev,
- u32 pbus_address, u32 *pbus_data)
-{
- int pbus_data_low, pbus_data_high;
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
- if (pbus_data_high < 0)
- return pbus_data_high;
-
- pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
- if (pbus_data_low < 0)
- return pbus_data_low;
-
- *pbus_data = pbus_data_low | (pbus_data_high << 16);
- return 0;
-}
-
-static int air_buckpbus_reg_read(struct phy_device *phydev,
- u32 pbus_address, u32 *pbus_data)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
-static int __air_buckpbus_reg_modify(struct phy_device *phydev,
- u32 pbus_address, u32 mask, u32 set)
-{
- int pbus_data_low, pbus_data_high;
- u32 pbus_data_old, pbus_data_new;
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
- if (pbus_data_high < 0)
- return pbus_data_high;
-
- pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
- if (pbus_data_low < 0)
- return pbus_data_low;
-
- pbus_data_old = pbus_data_low | (pbus_data_high << 16);
- pbus_data_new = (pbus_data_old & ~mask) | set;
- if (pbus_data_new == pbus_data_old)
- return 0;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
- upper_16_bits(pbus_data_new));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
- lower_16_bits(pbus_data_new));
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-static int air_buckpbus_reg_modify(struct phy_device *phydev,
- u32 pbus_address, u32 mask, u32 set)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
- set);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
static int __air_write_buf(struct phy_device *phydev, u32 address,
const struct firmware *fw)
{
@@ -480,8 +287,8 @@ static int en8811h_wait_mcu_ready(struct phy_device *phydev)
{
int ret, reg_value;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_FINISH);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_FINISH);
if (ret)
return ret;
@@ -506,28 +313,29 @@ static int an8811hb_check_crc(struct phy_device *phydev, u32 set1,
int ret;
/* Configure CRC */
- ret = air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN,
- AN8811HB_CRC_RD_EN);
+ ret = air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ AN8811HB_CRC_RD_EN);
if (ret < 0)
return ret;
- air_buckpbus_reg_read(phydev, set1, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, set1, &pbus_value);
do {
msleep(300);
- air_buckpbus_reg_read(phydev, mon2, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon2, &pbus_value);
/* We do not know what errors this check is supposed
* catch or what to do about a failure. So print the
* result and continue like the vendor driver does.
*/
if (pbus_value & AN8811HB_CRC_ST) {
- air_buckpbus_reg_read(phydev, mon3, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon3, &pbus_value);
phydev_dbg(phydev, "CRC Check %s!\n",
pbus_value & AN8811HB_CRC_CHECK_PASS ?
"PASS" : "FAIL");
- return air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN, 0);
+ return air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ 0);
}
} while (--retry);
@@ -539,8 +347,8 @@ static void en8811h_print_fw_version(struct phy_device *phydev)
{
struct en8811h_priv *priv = phydev->priv;
- air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
- &priv->firmware_version);
+ air_phy_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
+ &priv->firmware_version);
phydev_info(phydev, "MD32 firmware version: %08x\n",
priv->firmware_version);
}
@@ -565,8 +373,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev)
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
@@ -607,14 +415,14 @@ static int en8811h_load_firmware(struct phy_device *phydev)
if (ret < 0)
goto en8811h_load_firmware_rel1;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING,
- EN8811H_FW_CTRL_2_LOADING);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING,
+ EN8811H_FW_CTRL_2_LOADING);
if (ret < 0)
goto en8811h_load_firmware_out;
@@ -626,8 +434,8 @@ static int en8811h_load_firmware(struct phy_device *phydev)
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING, 0);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING, 0);
if (ret < 0)
goto en8811h_load_firmware_out;
@@ -653,8 +461,8 @@ static int en8811h_restart_mcu(struct phy_device *phydev)
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
@@ -948,7 +756,7 @@ static unsigned long an8811hb_clk_recalc_rate(struct clk_hw *hw,
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
if (ret < 0)
return ret;
@@ -960,9 +768,9 @@ static int an8811hb_clk_enable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK,
- AN8811HB_CLK_DRV_CKO_MASK);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK,
+ AN8811HB_CLK_DRV_CKO_MASK);
}
static void an8811hb_clk_disable(struct clk_hw *hw)
@@ -970,8 +778,8 @@ static void an8811hb_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK, 0);
+ air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK, 0);
}
static int an8811hb_clk_is_enabled(struct clk_hw *hw)
@@ -981,7 +789,7 @@ static int an8811hb_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
if (ret < 0)
return ret;
@@ -1047,7 +855,7 @@ static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw,
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
if (ret < 0)
return ret;
@@ -1059,9 +867,9 @@ static int en8811h_clk_enable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO,
- EN8811H_CLK_CGM_CKO);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO,
+ EN8811H_CLK_CGM_CKO);
}
static void en8811h_clk_disable(struct clk_hw *hw)
@@ -1069,8 +877,8 @@ static void en8811h_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO, 0);
+ air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO, 0);
}
static int en8811h_clk_is_enabled(struct clk_hw *hw)
@@ -1080,7 +888,7 @@ static int en8811h_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
if (ret < 0)
return ret;
@@ -1191,9 +999,9 @@ static int an8811hb_probe(struct phy_device *phydev)
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
- AN8811HB_GPIO_OUTPUT_345,
- AN8811HB_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
+ AN8811HB_GPIO_OUTPUT_345,
+ AN8811HB_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
@@ -1232,9 +1040,9 @@ static int en8811h_probe(struct phy_device *phydev)
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
- EN8811H_GPIO_OUTPUT_345,
- EN8811H_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
+ EN8811H_GPIO_OUTPUT_345,
+ EN8811H_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
@@ -1254,9 +1062,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
return ret;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_RX_POLARITY_NORMAL;
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
- AN8811HB_RX_POLARITY_NORMAL,
- pbus_value);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
+ AN8811HB_RX_POLARITY_NORMAL,
+ pbus_value);
if (ret < 0)
return ret;
@@ -1267,9 +1075,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
pbus_value = 0;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_TX_POLARITY_NORMAL;
- return air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
- AN8811HB_TX_POLARITY_NORMAL,
- pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
+ AN8811HB_TX_POLARITY_NORMAL,
+ pbus_value);
}
static int en8811h_config_serdes_polarity(struct phy_device *phydev)
@@ -1303,9 +1111,10 @@ static int en8811h_config_serdes_polarity(struct phy_device *phydev)
if (pol == PHY_POL_NORMAL)
pbus_value |= EN8811H_POLARITY_TX_NORMAL;
- return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
- EN8811H_POLARITY_RX_REVERSE |
- EN8811H_POLARITY_TX_NORMAL, pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
+ EN8811H_POLARITY_RX_REVERSE |
+ EN8811H_POLARITY_TX_NORMAL,
+ pbus_value);
}
static int an8811hb_config_init(struct phy_device *phydev)
@@ -1457,8 +1266,8 @@ static int en8811h_read_status(struct phy_device *phydev)
val & MDIO_AN_10GBT_STAT_LP2_5G);
} else {
/* Get link partner 2.5GBASE-T ability from vendor register */
- ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
- &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
+ &pbus_value);
if (ret < 0)
return ret;
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
index 04c4719a073f98ef75eabd54c4851f6a16391350..780ce2a17d3a58d5e3105534e9fea71bf3097b36 100644
--- a/drivers/net/phy/air_phy_lib.c
+++ b/drivers/net/phy/air_phy_lib.c
@@ -13,6 +13,186 @@
#define AIR_EXT_PAGE_ACCESS 0x1f
+static int __air_buckpbus_reg_read(struct phy_device *phydev,
+ u32 pbus_address, u32 *pbus_data)
+{
+ int pbus_data_low, pbus_data_high;
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+ return pbus_data_low;
+
+ *pbus_data = pbus_data_low | (pbus_data_high << 16);
+ return 0;
+}
+
+static int __air_buckpbus_reg_write(struct phy_device *phydev,
+ u32 pbus_address, u32 pbus_data)
+{
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
+ upper_16_bits(pbus_data));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
+ lower_16_bits(pbus_data));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int __air_buckpbus_reg_modify(struct phy_device *phydev,
+ u32 pbus_address, u32 mask, u32 set)
+{
+ int pbus_data_low, pbus_data_high;
+ u32 pbus_data_old, pbus_data_new;
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+ return pbus_data_low;
+
+ pbus_data_old = pbus_data_low | (pbus_data_high << 16);
+ pbus_data_new = (pbus_data_old & ~mask) | set;
+ if (pbus_data_new == pbus_data_old)
+ return 0;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
+ upper_16_bits(pbus_data_new));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
+ lower_16_bits(pbus_data_new));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_read);
+
+int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_write(phydev, pbus_address,
+ pbus_data);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_write);
+
+int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
+ set);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_modify);
+
int air_phy_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
index dd501b175a3a38e57744f79571eb1bc4ef46fdf5..23d8e3e318398958f2bba297619f35a86f9871a9 100644
--- a/drivers/net/phy/air_phy_lib.h
+++ b/drivers/net/phy/air_phy_lib.h
@@ -8,6 +8,29 @@
#ifndef __AIR_PHY_LIB_H
#define __AIR_PHY_LIB_H
+#define AIR_PHY_PAGE_STANDARD 0x0000
+#define AIR_PHY_PAGE_EXTENDED_1 0x0001
+#define AIR_PHY_PAGE_EXTENDED_4 0x0004
+
+/* MII Registers Page 4*/
+#define AIR_BPBUS_MODE 0x10
+#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
+#define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
+#define AIR_BPBUS_WR_ADDR_HIGH 0x11
+#define AIR_BPBUS_WR_ADDR_LOW 0x12
+#define AIR_BPBUS_WR_DATA_HIGH 0x13
+#define AIR_BPBUS_WR_DATA_LOW 0x14
+#define AIR_BPBUS_RD_ADDR_HIGH 0x15
+#define AIR_BPBUS_RD_ADDR_LOW 0x16
+#define AIR_BPBUS_RD_DATA_HIGH 0x17
+#define AIR_BPBUS_RD_DATA_LOW 0x18
+
+int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set);
+int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data);
+int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data);
int air_phy_read_page(struct phy_device *phydev);
int air_phy_write_page(struct phy_device *phydev, int page);
--
2.53.0
^ permalink raw reply related
* [PATCH net-next v2 2/4] net: phy: Add Airoha phy library for shared code
From: Louis-Alexis Eyraud @ 2026-03-26 12:04 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260326-add-airoha-an8801-support-v2-0-1a42d6b6050f@collabora.com>
In preparation of Airoha AN8801R PHY support, split out the interface
functions that will be common between the already present air_en8811h
driver and the new one, and put them into a new library named
air_phy_lib.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/Kconfig | 6 ++++++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_en8811h.c | 13 ++-----------
drivers/net/phy/air_phy_lib.c | 30 ++++++++++++++++++++++++++++++
drivers/net/phy/air_phy_lib.h | 14 ++++++++++++++
5 files changed, 53 insertions(+), 11 deletions(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index b5ee338b620d53980fbec9e83ab0de3d96ab4cc9..b6b1cde7e51fa1e470bfe210c8764a193449acb5 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -92,10 +92,16 @@ config AS21XXX_PHY
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
+ select AIR_NET_PHYLIB
select PHY_COMMON_PROPS
help
Currently supports the Airoha EN8811H PHY.
+config AIR_NET_PHYLIB
+ tristate
+ help
+ Airoha Ethernet PHY common library
+
config AMD_PHY
tristate "AMD and Altima PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 05e4878af27abeae3dfd9ab18fd29f8bf788b2a4..7cf1fa9e12cb6073a9e68c0ffa6284b361b80487 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -30,6 +30,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
+obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o
obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index 29ae73e65caaa9cdebe2253b5349aa6c7478dc85..be7c3426182a26fe3799b875827750e7772caadd 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -21,6 +21,8 @@
#include <linux/wordpart.h>
#include <linux/unaligned.h>
+#include "air_phy_lib.h"
+
#define EN8811H_PHY_ID 0x03a2a411
#define AN8811HB_PHY_ID 0xc0ff04a0
@@ -40,7 +42,6 @@
#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-#define AIR_EXT_PAGE_ACCESS 0x1f
#define AIR_PHY_PAGE_STANDARD 0x0000
#define AIR_PHY_PAGE_EXTENDED_4 0x0004
@@ -244,16 +245,6 @@ static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX);
-static int air_phy_read_page(struct phy_device *phydev)
-{
- return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
-}
-
-static int air_phy_write_page(struct phy_device *phydev, int page)
-{
- return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
-}
-
static int __air_buckpbus_reg_write(struct phy_device *phydev,
u32 pbus_address, u32 pbus_data)
{
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
new file mode 100644
index 0000000000000000000000000000000000000000..04c4719a073f98ef75eabd54c4851f6a16391350
--- /dev/null
+++ b/drivers/net/phy/air_phy_lib.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Airoha Ethernet PHY common library
+ *
+ * Copyright (C) 2026 Airoha Technology Corp.
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/phy.h>
+
+#include "air_phy_lib.h"
+
+#define AIR_EXT_PAGE_ACCESS 0x1f
+
+int air_phy_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
+}
+EXPORT_SYMBOL_GPL(air_phy_read_page);
+
+int air_phy_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
+}
+EXPORT_SYMBOL_GPL(air_phy_write_page);
+
+MODULE_DESCRIPTION("Airoha PHY Library");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Louis-Alexis Eyraud");
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
new file mode 100644
index 0000000000000000000000000000000000000000..dd501b175a3a38e57744f79571eb1bc4ef46fdf5
--- /dev/null
+++ b/drivers/net/phy/air_phy_lib.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2026 Airoha Technology Corp.
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#ifndef __AIR_PHY_LIB_H
+#define __AIR_PHY_LIB_H
+
+int air_phy_read_page(struct phy_device *phydev);
+int air_phy_write_page(struct phy_device *phydev, int page);
+
+#endif /* __AIR_PHY_LIB_H */
--
2.53.0
^ permalink raw reply related
* [PATCH net-next v2 1/4] dt-bindings: net: Add support for Airoha AN8801/R GbE PHY
From: Louis-Alexis Eyraud @ 2026-03-26 12:04 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260326-add-airoha-an8801-support-v2-0-1a42d6b6050f@collabora.com>
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Add a new binding to support the Airoha AN8801R Series Gigabit
Ethernet PHY.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../devicetree/bindings/net/airoha,an8801.yaml | 85 ++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/airoha,an8801.yaml b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..b90b21b5505367309b5df8ece54ea38664f6b50f
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,an8801.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8801R Series PHY
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description:
+ The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
+ with Single-port serdes interface for 1000Base-X/RGMII; this chip is
+ compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE 802.3(u,ab)
+ and supports Energy Efficient Ethernet (802.3az), Full Duplex Control
+ Flow (802.3x), auto-negotiation, crossover detect and autocorrection,
+ Wake-on-LAN with Magic Packet, and Jumbo Frame up to 9 Kilobytes.
+ This PHY also supports up to three user-configurable LEDs, which are
+ usually used for LAN Activity, 100M, 1000M indication.
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ethernet-phy-idc0ff.0421
+
+ reg:
+ maxItems: 1
+
+ leds: true
+
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enable Wake-on-LAN support
+
+required:
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ compatible = "ethernet-phy-idc0ff.0421";
+ reg = <0>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ default-state = "keep";
+ };
+ };
+ };
+ };
--
2.53.0
^ permalink raw reply related
* [PATCH net-next v2 0/4] Introduce Airoha AN8801R series Gigabit Ethernet PHY driver
From: Louis-Alexis Eyraud @ 2026-03-26 12:04 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
This series introduces the Airoha AN8801R Gigabit Ethernet PHY initial
support.
The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
with Single-port serdes interface for 1000Base-X/RGMII.
This chip is compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE
802.3(u,ab) and supports:
- Energy Efficient Ethernet (802.3az)
- Full Duplex Control Flow (802.3x)
- auto-negotiation
- crossover detect and autocorrection,
- Wake-on-LAN with Magic Packet
- Jumbo Frame up to 9 Kilobytes.
This PHY also supports up to three user-configurable LEDs, which are
usually used for LAN Activity, 100M, 1000M indication.
The series provides the devicetree binding and the driver that have been
written by AngeloGioacchino Del Regno, based on downstream
implementation ([1]). The driver allows setting up PHY LEDs, 10/100M,
1000M speeds, and Wake on LAN and PHY interrupts.
Since v2, the series also adds the air_phy_lib library, which goal is to
share common code between air_en8811h and air_an8801 drivers, and its use
in them. The first shared functions are the existing BuckPbus register
accessors and air_phy_read/write_page functions coming from air_en8811h
driver.
The series is based on net-next kernel tree (sha1: d1e59a4697371) and
I have tested it on Mediatek Genio 720-EVK board (that integrates an
Airoha AN8801RIN/A Ethernet PHY) with early board hardware enablement
patches.
[1]: https://gitlab.com/mediatek/aiot/bsp/linux/-/blob/mtk-v6.6/drivers/net/phy/an8801.c
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Changes in v2:
- Rebased on net-next (d1e59a4697371)
- Fixed dt-bindings to remove the leds property from the required ones and
add wakeup-source as valid property
- Added new reviewed-by trailer for dt_bindings
- Added new patches (2 and 3) to create air_phy_lib, to share common code
between air_en8811h and air_an8801 drivers and use it in air_en8811h.
- Remove custom BuckPBus register accessor functions and definitions from
air_an8801 and use the ones from air_phy_lib. It also fixes a build
issue on v1 due to an uninitialized variable used in
__air_buckpbus_reg_read, that is now removed from driver code
- Added air_an8801_probe function to allocate the newly added private
data structure and detect if the PHY is wakeup capable and the interrupt
can be registered as a wakeup IRQ, and perform the needed actions
- Added an8801r_suspend and an8801r_resume functions to perform specific
actions when WoL is enabled (reset its status, enable/disable the Link
Changed interrupt) and call the genphy_suspend/resume functions if
needed
- Modified an8801r_get_wol to return WoL is not supported if the PHY
device is not wakeup capable
- Modified an8801r_set_wol to return EOPNOTSUPP error code if the PHY
device is not wakeup capable, and to update the wakeup flag according
to WoL mode
- Modified an8801r_config_init to remove EEE disabling and replace
__phy_write use by phy_write_paged
- Reworked an8801r_rgmii_delay_config and its subfunctions to fix a
double return use in PHY_INTERFACE_MODE_RGMII_ID case, replace the
magic value use for default TX and RX delay and handle better the
enable/disable the inserted delays for all RGMII modes
- Merged an8801r_did_interrupt function in an8801r_handle_interrupt
- Modified the an8801r_handle_interrupt processing to process differently
the Magic Packet (to notify system wakeup) and the Link Changed
interrupt (to notify PHY state machine)
- Splitted the reset WoL status part from an8801r_ack_interrupt and fix
an issue that in some random cases made WAKEUP_CTL1 register lose the
Magic Packet WoL settings
- Modified an8801r_of_init_leds function so it does not return an error
if the leds configuration is not present in devicetree
- Removed feature field and add PHY_ALWAYS_CALL_SUSPEND flag in
airoha_driver data structure
- Link to v1: https://lore.kernel.org/r/20260304-add-airoha-an8801-support-v1-0-0ae4ee5a2f9d@collabora.com
---
AngeloGioacchino Del Regno (2):
dt-bindings: net: Add support for Airoha AN8801/R GbE PHY
net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver
Louis-Alexis Eyraud (2):
net: phy: Add Airoha phy library for shared code
net: phy: air_phy_lib: Factorize BuckPBus register accessors
.../devicetree/bindings/net/airoha,an8801.yaml | 85 ++
drivers/net/phy/Kconfig | 12 +
drivers/net/phy/Makefile | 2 +
drivers/net/phy/air_an8801.c | 1115 ++++++++++++++++++++
drivers/net/phy/air_en8811h.c | 316 +-----
drivers/net/phy/air_phy_lib.c | 210 ++++
drivers/net/phy/air_phy_lib.h | 37 +
7 files changed, 1519 insertions(+), 258 deletions(-)
---
base-commit: d1e59a46973719e458bec78d00dd767d7a7ba71f
change-id: 20260303-add-airoha-an8801-support-57d544a4afed
Best regards,
--
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
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