* Re: [PATCH net-next v3 1/2] dpll: add fractional frequency offset to pin-parent-device
From: Ivan Vecera @ 2026-05-07 6:12 UTC (permalink / raw)
To: Jakub Kicinski, Jiri Pirko
Cc: netdev, Andrew Lunn, Arkadiusz Kubalewski, David S. Miller,
Donald Hunter, Eric Dumazet, Jonathan Corbet, Leon Romanovsky,
Mark Bloch, Michal Schmidt, Paolo Abeni, Pasi Vaananen, Petr Oros,
Prathosh Satish, Saeed Mahameed, Shuah Khan, Simon Horman,
Tariq Toukan, Vadim Fedorenko, linux-doc, linux-kernel,
linux-rdma
In-Reply-To: <20260506183342.767b5fbc@kernel.org>
On 5/7/26 3:33 AM, Jakub Kicinski wrote:
> On Mon, 4 May 2026 17:53:39 +0200 Ivan Vecera wrote:
>> + At top level this represents the RX vs TX symbol rate
>> + offset on the media associated with the pin.
>
> Isn't this a hacky hack? I'd think that pin is in or out.
> Having a freq offset between two pins or pin and parent's
> ref lock makes sense. This new interpretation sounds like
> we are trying to shove a difference between two pins into one?
The "RX vs TX symbol rate offset" description is not something I
introduced — it is the original documentation of the
fractional-frequency-offset attribute as defined by Jiri. The -ppt
variant was added later purely for higher precision. This patch just
unifies the documentation of both attributes.
I'm not sure I fully understand what the original "RX vs TX" semantics
were meant to capture. Jiri, could you clarify what you had in mind
and whether we should keep or change that description?
>> @@ -299,6 +299,10 @@ zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv,
>> {
>> struct zl3073x_dpll_pin *pin = pin_priv;
>>
>> + /* Only rx vs tx symbol rate FFO is supported */
>> + if (dpll)
>> + return -ENODATA;
>> +
>> *ffo = pin->freq_offset;
>
> It's easy for driver authors to forget this sort of validation.
> We should fail close, so it's better to have some "capability"
> bits or something for the driver to opt into getting given format
> of the call.
Regarding the fail-close concern — I agree that relying on drivers
to check dpll==NULL is fragile. A capability bit alone wouldn't help
though, since the driver still needs to distinguish which FFO context
is being requested.
I can think of two approaches:
1. An explicit bool parameter (e.g. `bool per_parent`) instead of
overloading the dpll pointer for context distinction.
2. Separate callbacks for each FFO context (e.g. ffo_get for the
top-level and ffo_parent_get for the per-parent).
Do you have a preference, or something else in mind?
Thanks,
Ivan
^ permalink raw reply
* [PATCH v3] net: dsa: realtek: rtl8365mb: add support for RTL8367SB
From: Mieczyslaw Nalewaj @ 2026-05-07 5:18 UTC (permalink / raw)
To: Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Alvin Šipraga,
Yury Norov, Rasmus Villemoes, Russell King, netdev
In-Reply-To: <2a52d7a8-3a39-4dd5-a0d5-c746122a9f73.ref@yahoo.com>
Add chip info entry for the Realtek RTL8367SB switch. This device has
chip ID 0x6367 and version 0x0010. It exposes two external interfaces:
port 6 supports MII, TMII, RMII, RGMII, SGMII and HSGMII, while port 7
supports MII, TMII, RMII and RGMII. Use the existing 8365MB-VC jam table
for initialization.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
---
drivers/net/dsa/realtek/rtl8365mb_main.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c
index 05412c4aa976..6451e8a31452 100644
+++ b/drivers/net/dsa/realtek/rtl8365mb.c
@@ -545,6 +545,20 @@ static const struct rtl8365mb_chip_info
.jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
},
{
+ .name = "RTL8367SB",
+ .chip_id = 0x6367,
+ .chip_ver = 0x0010,
+ .extints = {
+ { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
+ PHY_INTF(RMII) | PHY_INTF(RGMII) |
+ PHY_INTF(SGMII) | PHY_INTF(HSGMII) },
+ { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) |
+ PHY_INTF(RMII) | PHY_INTF(RGMII) },
+ },
+ .jam_table = rtl8365mb_init_jam_8365mb_vc,
+ .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
+ },
+ {
.name = "RTL8367RB-VB",
.chip_id = 0x6367,
.chip_ver = 0x0020,
--
2.53.0
^ permalink raw reply
* Re: [PATCH 4/8] tools/selftests: Add a VXLAN+IPsec traffic test
From: Steffen Klassert @ 2026-05-07 5:54 UTC (permalink / raw)
To: Jakub Kicinski; +Cc: David Miller, Herbert Xu, netdev
In-Reply-To: <20260506172310.64188c0e@kernel.org>
On Wed, May 06, 2026 at 05:23:10PM -0700, Jakub Kicinski wrote:
> On Wed, 6 May 2026 17:04:35 -0700 Jakub Kicinski wrote:
> > Oh, sorry, changed my mind we can't pull this:( both the Makefile and
> > config break alphabetic sort, our CI will flag every incoming as red
> > if we merge this as is, we need this on top:
>
> Eh, let me just commit this and move on..
Thanks!
^ permalink raw reply
* Re: [PATCH 0/8] pull request (net): ipsec 2026-05-05
From: Steffen Klassert @ 2026-05-07 5:54 UTC (permalink / raw)
To: Jakub Kicinski; +Cc: David Miller, Herbert Xu, netdev
In-Reply-To: <20260506165149.12e30102@kernel.org>
On Wed, May 06, 2026 at 04:51:49PM -0700, Jakub Kicinski wrote:
> On Wed, 6 May 2026 16:50:35 -0700 Jakub Kicinski wrote:
> > On Tue, 5 May 2026 15:22:56 +0200 Steffen Klassert wrote:
> > > 5. Harden __xfrm_state_delete() against repeated or inconsistent unhashing
> > > of state list nodes by keying the removal on actual list membership and
> > > using delete-and-init helpers. From Michal Kosiorek.
> >
> > Sashiko seems to have extra comments for this but I suspect follow up
> > is the way to go there.
>
> I should have made it clear - Claude-shiko:
>
> https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260505132326.1362733-4-steffen.klassert@secunet.com
I think the races Sashiko reveals here don't exist. __xfrm_state_delete()
is always called with the xfrm_state lock held, so there can't be a
second __xfrm_state_delete() on the same xfrm_state.
^ permalink raw reply
* Re: [PATCH net-next 2/3] ppp: unify two channel structs
From: Qingfang Deng @ 2026-05-07 5:53 UTC (permalink / raw)
To: Paolo Abeni, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Jiri Kosina, David Sterba, Greg Kroah-Hartman,
Jiri Slaby, Mitchell Blank Jr, Chas Williams, Simon Horman,
James Chapman, Kees Cook, Sebastian Andrzej Siewior, Taegu Ha,
Guillaume Nault, Eric Woudstra, Arnd Bergmann, Dawid Osuchowski,
Breno Leitao, linux-ppp, netdev, linux-kernel, linux-serial,
linux-atm-general
In-Reply-To: <590d7931-02b0-45d6-8f43-ef909c9bde89@redhat.com>
On 2026/5/5 19:16, Paolo Abeni wrote:
> On 4/30/26 11:05 AM, Qingfang Deng wrote:
>> Historically, PPP maintained two separate structures for a channel:
>> 'struct channel' was internal to ppp_generic.c, while 'struct ppp_channel'
>> was the public interface that drivers were required to embed. This
>> duplication was redundant and forced drivers to manage the lifecycle of
>> the public structure.
>>
>> Unify these two structures into a single 'struct ppp_channel', which is
>> now internal to ppp_generic.c. Drivers now use a 'ppp_channel_conf'
>> structure to specify registration parameters and receive an opaque
>> pointer to the allocated channel.
>>
>> Key changes:
>> - ppp_register_channel() and ppp_register_net_channel() now return
>> a 'struct ppp_channel *' instead of taking a pointer to a driver-
>> embedded structure.
>> - 'struct ppp_channel_ops' methods now take the driver's 'private'
>> pointer directly as their first argument, simplifying driver logic.
>> - ppp_unregister_channel() now takes the opaque pointer.
>> - Multilink-specific fields are unified and handled via the new
>> configuration structure.
>>
>> This cleanup simplifies the driver interface and makes the channel
>> lifecycle management more robust by centralizing allocation in the PPP
>> generic layer.
>>
>> Assisted-by: Gemini:gemini-3-flash
>> Signed-off-by: Qingfang Deng <qingfang.deng@linux.dev>
>> ---
>> drivers/net/ppp/ppp_async.c | 51 +++++-----
>> drivers/net/ppp/ppp_generic.c | 161 +++++++++++++++----------------
>> drivers/net/ppp/ppp_synctty.c | 51 +++++-----
>> drivers/net/ppp/pppoe.c | 34 ++++---
>> drivers/net/ppp/pppox.c | 4 +-
>> drivers/net/ppp/pptp.c | 40 ++++----
>> drivers/tty/ipwireless/network.c | 30 +++---
>> include/linux/if_pppox.h | 2 +-
>> include/linux/ppp_channel.h | 49 ++++++----
>> net/atm/pppoatm.c | 61 ++++++------
>> net/l2tp/l2tp_ppp.c | 34 ++++---
>> 11 files changed, 271 insertions(+), 246 deletions(-)
> This patch is IMHO a bit too big and should be split. Also this kind of
> refactor looks very invasive and potentially regression prone. I think
> it should include a signficant self-test coverage increase.
This is indeed too big. But how do I split it without breaking the build?
^ permalink raw reply
* Re: [PATCH net-next v3] net: stmmac: Add support for TX/RX channel interrupt
From: Nazle Asmade, Muhammad Nazim Amirul @ 2026-05-07 5:35 UTC (permalink / raw)
To: Jakub Kicinski
Cc: netdev@vger.kernel.org, davem@davemloft.net, pabeni@redhat.com,
edumazet@google.com, andrew+netdev@lunn.ch,
linux-kernel@vger.kernel.org
In-Reply-To: <20260506190703.5937aea9@kernel.org>
On 7/5/2026 10:07 am, Jakub Kicinski wrote:
> On Tue, 5 May 2026 19:00:18 -0700
> muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>> - Add net-next tree prefix to subject line.
>> - Fix variable declarations to follow Reverse Christmas Tree order.
>
> This patch does not apply to net-next, please rebase and repost.
sorry, I overlook this email, will repost again. Thanks Jakub!
^ permalink raw reply
* Re: [PATCH ipsec-next] xfrm: Use regular error handling instead of BUG_ON() in the netlink API.
From: Antony Antony @ 2026-05-07 5:21 UTC (permalink / raw)
To: Steffen Klassert; +Cc: netdev, devel
In-Reply-To: <aftnl6d59WUM_Dfm@secunet.com>
wHi Steffen,
Thanks Steffen, I was hit by this in the new XFRM_MIGRATE_STATE I am adding.
I am glad to see we are addressing this.
On Wed, May 06, 2026 at 06:08:55PM +0200, Steffen Klassert via Devel wrote:
> The xfrm netlink API uses BUG_ON() on failures since it exists.
> However all these error are uncritical and can be handled
> with regular error handling. This fixes machine crashes
> in situations where an emergency break is not needed.
While BUG_ON is an extreme measure for a recoverable netlink error, it does
have diagnostic value: it leaves a stack trace. The patch trades
a crash + stack trace for a silent error return, which loses observability.
Would you consider using WARN_ONCE instead of a bare if (err < 0)?
- BUG_ON(err < 0);
+ if (WARN_ONCE(err < 0, "xfrm: build_spdinfo failed: %d\n", err)) {
+ kfree_skb(r_skb);
+ return err;
+ }
Something like the above would preserve the "shouldn't happen" signal with a
stack trace on first occurrence, without panicking the machine.
Or are there better signaling styles in Kernel?
>
> Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
> ---
> net/xfrm/xfrm_user.c | 39 +++++++++++++++++++++++++++++++--------
> 1 file changed, 31 insertions(+), 8 deletions(-)
>
> diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c
> index d56450f61669..b24a0f9e91d5 100644
> --- a/net/xfrm/xfrm_user.c
> +++ b/net/xfrm/xfrm_user.c
> @@ -1734,7 +1734,10 @@ static int xfrm_get_spdinfo(struct sk_buff *skb, struct nlmsghdr *nlh,
> return -ENOMEM;
>
> err = build_spdinfo(r_skb, net, sportid, seq, *flags);
> - BUG_ON(err < 0);
> + if (err < 0) {
> + kfree_skb(r_skb);
> + return err;
> + }
>
> return nlmsg_unicast(xfrm_net_nlsk(net, skb), r_skb, sportid);
> }
> @@ -1794,7 +1797,11 @@ static int xfrm_get_sadinfo(struct sk_buff *skb, struct nlmsghdr *nlh,
> return -ENOMEM;
>
> err = build_sadinfo(r_skb, net, sportid, seq, *flags);
> - BUG_ON(err < 0);
> + if (err < 0) {
> + kfree_skb(r_skb);
> + return err;
> + }
> +
>
> return nlmsg_unicast(xfrm_net_nlsk(net, skb), r_skb, sportid);
> }
> @@ -3285,7 +3292,10 @@ static int xfrm_send_migrate(const struct xfrm_selector *sel, u8 dir, u8 type,
>
> /* build migrate */
> err = build_migrate(skb, m, num_migrate, k, sel, encap, dir, type);
> - BUG_ON(err < 0);
> + if (err < 0) {
> + kfree_skb(skb);
> + return err;
> + }
>
> return xfrm_nlmsg_multicast(net, skb, 0, XFRMNLGRP_MIGRATE);
> }
> @@ -3623,7 +3633,10 @@ static int xfrm_aevent_state_notify(struct xfrm_state *x, const struct km_event
> return -ENOMEM;
>
> err = build_aevent(skb, x, c);
> - BUG_ON(err < 0);
> + if (err < 0) {
> + kfree_skb(skb);
> + return err;
> + }
>
> return xfrm_nlmsg_multicast(net, skb, 0, XFRMNLGRP_AEVENTS);
> }
> @@ -3862,7 +3875,10 @@ static int xfrm_send_acquire(struct xfrm_state *x, struct xfrm_tmpl *xt,
> return -ENOMEM;
>
> err = build_acquire(skb, x, xt, xp);
> - BUG_ON(err < 0);
> + if (err < 0) {
> + kfree_skb(skb);
> + return err;
> + }
>
> return xfrm_nlmsg_multicast(net, skb, 0, XFRMNLGRP_ACQUIRE);
> }
> @@ -3984,7 +4000,10 @@ static int xfrm_exp_policy_notify(struct xfrm_policy *xp, int dir, const struct
> return -ENOMEM;
>
> err = build_polexpire(skb, xp, dir, c);
> - BUG_ON(err < 0);
> + if (err < 0) {
> + kfree_skb(skb);
> + return err;
> + }
>
> return xfrm_nlmsg_multicast(net, skb, 0, XFRMNLGRP_EXPIRE);
> }
> @@ -4151,7 +4170,8 @@ static int xfrm_send_report(struct net *net, u8 proto,
> return -ENOMEM;
>
> err = build_report(skb, proto, sel, addr);
> - BUG_ON(err < 0);
> + if (err < 0)
> + return err;
>
> return xfrm_nlmsg_multicast(net, skb, 0, XFRMNLGRP_REPORT);
> }
> @@ -4206,7 +4226,10 @@ static int xfrm_send_mapping(struct xfrm_state *x, xfrm_address_t *ipaddr,
> return -ENOMEM;
>
> err = build_mapping(skb, x, ipaddr, sport);
> - BUG_ON(err < 0);
> + if (err < 0) {
> + kfree_skb(skb);
> + return err;
> + }
>
> return xfrm_nlmsg_multicast(net, skb, 0, XFRMNLGRP_MAPPING);
> }
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH net] rds: filter RDS_INFO_* getsockopt by caller's netns
From: Allison Henderson @ 2026-05-07 5:17 UTC (permalink / raw)
To: Maoyi Xie
Cc: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman, netdev, linux-rdma, rds-devel, linux-kernel,
Maoyi Xie, Praveen Kakkolangara
In-Reply-To: <20260506075031.2238596-1-maoyixie.tju@gmail.com>
On Wed, 2026-05-06 at 15:50 +0800, Maoyi Xie wrote:
> From: Maoyi Xie <maoyi.xie@ntu.edu.sg>
>
> The RDS_INFO_* family of getsockopt(2) options reads several
> file-scope global lists that are not per-netns:
>
> rds_sock_info / rds6_sock_info,
> rds_sock_inc_info / rds6_sock_inc_info -> rds_sock_list
> rds_tcp_tc_info / rds6_tcp_tc_info -> rds_tcp_tc_list
> rds_conn_info / rds6_conn_info,
> rds_conn_message_info_cmn (for the *_SEND_MESSAGES and
> *_RETRANS_MESSAGES variants),
> rds_for_each_conn_info (for RDS_INFO_IB_CONNECTIONS)
> -> rds_conn_hash[]
>
> The handlers do not filter by the caller's network namespace.
> rds_info_getsockopt() has no netns or capable() check, and
> rds_create() has no capable() check, so AF_RDS is reachable from
> an unprivileged user namespace. As a result, an unprivileged
> caller in a fresh user_ns plus netns can read the bound address
> and sock inode of every RDS socket on the host, the peer address
> of incoming messages on every RDS socket on the host, the peer
> address and TCP sequence numbers of every rds-tcp connection on
> the host, and the peer address and RDS sequence numbers of every
> RDS connection on the host.
>
> The rds-tcp transport is reachable from a non-initial netns (see
> rds_set_transport()), so a one-shot init_net gate at
> rds_info_getsockopt() would deny legitimate per-netns visibility
> to rds-tcp callers. Instead, filter at each handler by comparing
> the netns of the caller's socket to the netns of the list entry,
> or to rds_conn_net(conn) for connection paths. Only copy entries
> whose netns matches the caller. Counters (RDS_INFO_COUNTERS) are
> aggregate statistics and remain global.
>
> Reproducer (KASAN VM, rds and rds_tcp loaded): an AF_RDS socket
> binds 127.0.0.1:4242 in init_net as root. A child process enters
> a fresh user_ns plus netns and opens AF_RDS there, then calls
> getsockopt(SOL_RDS, RDS_INFO_SOCKETS). Before this change, the
> child sees the init_net socket. After this change, the child
> sees zero entries.
>
> Suggested-by: Allison Henderson <achender@kernel.org>
> Co-developed-by: Praveen Kakkolangara <praveen.kakkolangara@aumovio.com>
> Signed-off-by: Praveen Kakkolangara <praveen.kakkolangara@aumovio.com>
> Signed-off-by: Maoyi Xie <maoyi.xie@ntu.edu.sg>
Thanks Xie. This looks good to me. I notice that patchwork failed to apply this patch though. So you may need to
rebase a v2 onto net/main. Other than that I think it looks good. Thank you!
Reviewed-by: Allison Henderson <achender@kernel.org>
> ---
> net/rds/af_rds.c | 24 ++++++++++++++++++++++--
> net/rds/connection.c | 13 +++++++++++++
> net/rds/tcp.c | 25 +++++++++++++++++++++----
> 3 files changed, 56 insertions(+), 6 deletions(-)
>
> diff --git a/net/rds/af_rds.c b/net/rds/af_rds.c
> index b396c673d..469891131 100644
> --- a/net/rds/af_rds.c
> +++ b/net/rds/af_rds.c
> @@ -729,6 +729,7 @@ static void rds_sock_inc_info(struct socket *sock, unsigned int len,
> struct rds_info_iterator *iter,
> struct rds_info_lengths *lens)
> {
> + struct net *net = sock_net(sock->sk);
> struct rds_sock *rs;
> struct rds_incoming *inc;
> unsigned int total = 0;
> @@ -738,6 +739,9 @@ static void rds_sock_inc_info(struct socket *sock, unsigned int len,
> spin_lock_bh(&rds_sock_lock);
>
> list_for_each_entry(rs, &rds_sock_list, rs_item) {
> + /* Only show sockets in the caller's netns. */
> + if (!net_eq(sock_net(rds_rs_to_sk(rs)), net))
> + continue;
> /* This option only supports IPv4 sockets. */
> if (!ipv6_addr_v4mapped(&rs->rs_bound_addr))
> continue;
> @@ -768,6 +772,7 @@ static void rds6_sock_inc_info(struct socket *sock, unsigned int len,
> struct rds_info_iterator *iter,
> struct rds_info_lengths *lens)
> {
> + struct net *net = sock_net(sock->sk);
> struct rds_incoming *inc;
> unsigned int total = 0;
> struct rds_sock *rs;
> @@ -777,6 +782,9 @@ static void rds6_sock_inc_info(struct socket *sock, unsigned int len,
> spin_lock_bh(&rds_sock_lock);
>
> list_for_each_entry(rs, &rds_sock_list, rs_item) {
> + /* Only show sockets in the caller's netns. */
> + if (!net_eq(sock_net(rds_rs_to_sk(rs)), net))
> + continue;
> read_lock(&rs->rs_recv_lock);
>
> list_for_each_entry(inc, &rs->rs_recv_queue, i_item) {
> @@ -800,6 +808,7 @@ static void rds_sock_info(struct socket *sock, unsigned int len,
> struct rds_info_iterator *iter,
> struct rds_info_lengths *lens)
> {
> + struct net *net = sock_net(sock->sk);
> struct rds_info_socket sinfo;
> unsigned int cnt = 0;
> struct rds_sock *rs;
> @@ -814,6 +823,9 @@ static void rds_sock_info(struct socket *sock, unsigned int len,
> }
>
> list_for_each_entry(rs, &rds_sock_list, rs_item) {
> + /* Only show sockets in the caller's netns. */
> + if (!net_eq(sock_net(rds_rs_to_sk(rs)), net))
> + continue;
> /* This option only supports IPv4 sockets. */
> if (!ipv6_addr_v4mapped(&rs->rs_bound_addr))
> continue;
> @@ -841,17 +853,24 @@ static void rds6_sock_info(struct socket *sock, unsigned int len,
> struct rds_info_iterator *iter,
> struct rds_info_lengths *lens)
> {
> + struct net *net = sock_net(sock->sk);
> struct rds6_info_socket sinfo6;
> + unsigned int cnt = 0;
> struct rds_sock *rs;
>
> len /= sizeof(struct rds6_info_socket);
>
> spin_lock_bh(&rds_sock_lock);
>
> - if (len < rds_sock_count)
> + if (len < rds_sock_count) {
> + cnt = rds_sock_count;
> goto out;
> + }
>
> list_for_each_entry(rs, &rds_sock_list, rs_item) {
> + /* Only show sockets in the caller's netns. */
> + if (!net_eq(sock_net(rds_rs_to_sk(rs)), net))
> + continue;
> sinfo6.sndbuf = rds_sk_sndbuf(rs);
> sinfo6.rcvbuf = rds_sk_rcvbuf(rs);
> sinfo6.bound_addr = rs->rs_bound_addr;
> @@ -861,10 +880,11 @@ static void rds6_sock_info(struct socket *sock, unsigned int len,
> sinfo6.inum = sock_i_ino(rds_rs_to_sk(rs));
>
> rds_info_copy(iter, &sinfo6, sizeof(sinfo6));
> + cnt++;
> }
>
> out:
> - lens->nr = rds_sock_count;
> + lens->nr = cnt;
> lens->each = sizeof(struct rds6_info_socket);
>
> spin_unlock_bh(&rds_sock_lock);
> diff --git a/net/rds/connection.c b/net/rds/connection.c
> index 412441aaa..a73554816 100644
> --- a/net/rds/connection.c
> +++ b/net/rds/connection.c
> @@ -568,6 +568,7 @@ static void rds_conn_message_info_cmn(struct socket *sock, unsigned int len,
> struct rds_info_lengths *lens,
> int want_send, bool isv6)
> {
> + struct net *net = sock_net(sock->sk);
> struct hlist_head *head;
> struct list_head *list;
> struct rds_connection *conn;
> @@ -590,6 +591,9 @@ static void rds_conn_message_info_cmn(struct socket *sock, unsigned int len,
> struct rds_conn_path *cp;
> int npaths;
>
> + /* Only show connections in the caller's netns. */
> + if (!net_eq(rds_conn_net(conn), net))
> + continue;
> if (!isv6 && conn->c_isv6)
> continue;
>
> @@ -688,6 +692,7 @@ void rds_for_each_conn_info(struct socket *sock, unsigned int len,
> u64 *buffer,
> size_t item_len)
> {
> + struct net *net = sock_net(sock->sk);
> struct hlist_head *head;
> struct rds_connection *conn;
> size_t i;
> @@ -700,6 +705,9 @@ void rds_for_each_conn_info(struct socket *sock, unsigned int len,
> for (i = 0, head = rds_conn_hash; i < ARRAY_SIZE(rds_conn_hash);
> i++, head++) {
> hlist_for_each_entry_rcu(conn, head, c_hash_node) {
> + /* Only show connections in the caller's netns. */
> + if (!net_eq(rds_conn_net(conn), net))
> + continue;
>
> /* XXX no c_lock usage.. */
> if (!visitor(conn, buffer))
> @@ -726,6 +734,7 @@ static void rds_walk_conn_path_info(struct socket *sock, unsigned int len,
> u64 *buffer,
> size_t item_len)
> {
> + struct net *net = sock_net(sock->sk);
> struct hlist_head *head;
> struct rds_connection *conn;
> size_t i;
> @@ -740,6 +749,10 @@ static void rds_walk_conn_path_info(struct socket *sock, unsigned int len,
> hlist_for_each_entry_rcu(conn, head, c_hash_node) {
> struct rds_conn_path *cp;
>
> + /* Only show connections in the caller's netns. */
> + if (!net_eq(rds_conn_net(conn), net))
> + continue;
> +
> /* XXX We only copy the information from the first
> * path for now. The problem is that if there are
> * more than one underlying paths, we cannot report
> diff --git a/net/rds/tcp.c b/net/rds/tcp.c
> index 654e23d13..ef9e958ca 100644
> --- a/net/rds/tcp.c
> +++ b/net/rds/tcp.c
> @@ -235,20 +235,27 @@ static void rds_tcp_tc_info(struct socket *rds_sock, unsigned int len,
> struct rds_info_iterator *iter,
> struct rds_info_lengths *lens)
> {
> + struct net *net = sock_net(rds_sock->sk);
> struct rds_info_tcp_socket tsinfo;
> struct rds_tcp_connection *tc;
> + unsigned int cnt = 0;
> unsigned long flags;
>
> spin_lock_irqsave(&rds_tcp_tc_list_lock, flags);
>
> - if (len / sizeof(tsinfo) < rds_tcp_tc_count)
> + if (len / sizeof(tsinfo) < rds_tcp_tc_count) {
> + cnt = rds_tcp_tc_count;
> goto out;
> + }
>
> list_for_each_entry(tc, &rds_tcp_tc_list, t_list_item) {
> struct inet_sock *inet = inet_sk(tc->t_sock->sk);
>
> if (tc->t_cpath->cp_conn->c_isv6)
> continue;
> + /* Only show connections in the caller's netns. */
> + if (!net_eq(rds_conn_net(tc->t_cpath->cp_conn), net))
> + continue;
>
> tsinfo.local_addr = inet->inet_saddr;
> tsinfo.local_port = inet->inet_sport;
> @@ -263,10 +270,11 @@ static void rds_tcp_tc_info(struct socket *rds_sock, unsigned int len,
> tsinfo.tos = tc->t_cpath->cp_conn->c_tos;
>
> rds_info_copy(iter, &tsinfo, sizeof(tsinfo));
> + cnt++;
> }
>
> out:
> - lens->nr = rds_tcp_tc_count;
> + lens->nr = cnt;
> lens->each = sizeof(tsinfo);
>
> spin_unlock_irqrestore(&rds_tcp_tc_list_lock, flags);
> @@ -281,19 +289,27 @@ static void rds6_tcp_tc_info(struct socket *sock, unsigned int len,
> struct rds_info_iterator *iter,
> struct rds_info_lengths *lens)
> {
> + struct net *net = sock_net(sock->sk);
> struct rds6_info_tcp_socket tsinfo6;
> struct rds_tcp_connection *tc;
> + unsigned int cnt = 0;
> unsigned long flags;
>
> spin_lock_irqsave(&rds_tcp_tc_list_lock, flags);
>
> - if (len / sizeof(tsinfo6) < rds6_tcp_tc_count)
> + if (len / sizeof(tsinfo6) < rds6_tcp_tc_count) {
> + cnt = rds6_tcp_tc_count;
> goto out;
> + }
>
> list_for_each_entry(tc, &rds_tcp_tc_list, t_list_item) {
> struct sock *sk = tc->t_sock->sk;
> struct inet_sock *inet = inet_sk(sk);
>
> + /* Only show connections in the caller's netns. */
> + if (!net_eq(rds_conn_net(tc->t_cpath->cp_conn), net))
> + continue;
> +
> tsinfo6.local_addr = sk->sk_v6_rcv_saddr;
> tsinfo6.local_port = inet->inet_sport;
> tsinfo6.peer_addr = sk->sk_v6_daddr;
> @@ -306,10 +322,11 @@ static void rds6_tcp_tc_info(struct socket *sock, unsigned int len,
> tsinfo6.last_seen_una = tc->t_last_seen_una;
>
> rds_info_copy(iter, &tsinfo6, sizeof(tsinfo6));
> + cnt++;
> }
>
> out:
> - lens->nr = rds6_tcp_tc_count;
> + lens->nr = cnt;
> lens->each = sizeof(tsinfo6);
>
> spin_unlock_irqrestore(&rds_tcp_tc_list_lock, flags);
>
> base-commit: 028ef9c96e96197026887c0f092424679298aae8
^ permalink raw reply
* Re: [PATCH v1 0/7] ARM: dts: stm32: Fix mecio1 hardware revisions and ADC/GPIO mappings
From: Oleksij Rempel @ 2026-05-07 5:14 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue
Cc: kernel, linux-kernel, netdev, devicetree, linux-stm32
In-Reply-To: <20260318105123.819807-1-o.rempel@pengutronix.de>
Hi Alexandre,
Can you please take a look at this patch stack :)
Best Regards,
Oleksij
On Wed, Mar 18, 2026 at 11:51:16AM +0100, Oleksij Rempel wrote:
> This series updates the STM32MP15x MECIO1 device trees to properly
> account for the physical hardware changes between the R0 and R1 board
> revisions.
>
> David Jander (7):
> ARM: dts: stm32: stm32mp15x-mecio1-io: Enable internal ADC reference
> ARM: dts: stm32: stm32mp15x-mecio1-io: Fix ADC sampling times
> ARM: dts: stm32: stm32mp15x-mecio1-io: Move divergent mecio1 ADC
> channels to board files
> ARM: dts: stm32: stm32mp15x-mecio1-io: Fix GPIO names typo
> ARM: dts: stm32: stm32mp15x-mecio1-io: Move gpio-line-names to board
> files
> ARM: dts: stm32: stm32mp15x-mecio1-io: Fix expander gpio line typo
> ARM: dts: stm32: stm32mp15x-mecio1-io: Move expander gpio-line-names
> to board files
>
> arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts | 128 +++++++++++++++
> arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts | 144 +++++++++++++++++
> .../arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 146 ++----------------
> 3 files changed, 288 insertions(+), 130 deletions(-)
>
> --
> 2.47.3
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* RE: [Patch net-next v1 1/7] r8169: add support for multi irqs
From: Javen @ 2026-05-07 4:23 UTC (permalink / raw)
To: Heiner Kallweit, nic_swsd@realtek.com, andrew+netdev@lunn.ch,
davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
pabeni@redhat.com, horms@kernel.org
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <bbbb2a7d-c6a3-4dcf-94f9-0e580d43897e@gmail.com>
>On 06.05.2026 10:13, javen wrote:
>> From: Javen Xu <javen_xu@realsil.com.cn>
>>
>> RSS uses multi rx queues to receive packets, and each rx queue needs
>> one irq and napi. So this patch adds support for multi irqs and napi here.
>>
>> Signed-off-by: Javen Xu <javen_xu@realsil.com.cn>
>> ---
>> drivers/net/ethernet/realtek/r8169_main.c | 199
>> ++++++++++++++++++++--
>> 1 file changed, 184 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/realtek/r8169_main.c
>> b/drivers/net/ethernet/realtek/r8169_main.c
>> index 791277e750ba..ef74ee02c117 100644
>> --- a/drivers/net/ethernet/realtek/r8169_main.c
>> +++ b/drivers/net/ethernet/realtek/r8169_main.c
>> @@ -77,6 +77,7 @@
>> #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
>> #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1)
>> #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS)
>> +#define R8169_MAX_MSIX_VEC 32
>>
>> #define OCP_STD_PHY_BASE 0xa400
>>
>> @@ -435,6 +436,8 @@ enum rtl8125_registers {
>> #define INT_CFG0_CLKREQEN BIT(3)
>> IntrMask_8125 = 0x38,
>> IntrStatus_8125 = 0x3c,
>> + INTR_VEC_MAP_MASK = 0x800,
>> + INTR_VEC_MAP_STATUS = 0x802,
>
>These register names don't have a chip version reference.
>Does this mean they can be used on other chip versions with RSS as well?
Yes, this can be reused on other chip versions.
>
>> INT_CFG1_8125 = 0x7a,
>> LEDSEL2 = 0x84,
>> LEDSEL1 = 0x86,
>> @@ -728,6 +731,19 @@ enum rtl_dash_type {
>> RTL_DASH_25_BP,
>> };
>>
>> +struct rtl8169_napi {
>> + struct napi_struct napi;
>> + void *priv;
>> + int index;
>
>It seems the index is never used in this patch.
This will be used in patch 5/7, when we enable rss. I will move it back.
>
>> +};
>> +
>> +struct rtl8169_irq {
>> + irq_handler_t handler;
>> + unsigned int vector;
>> + u8 requested;
>> + char name[IFNAMSIZ + 10];
>> +};
>> +
>> struct rtl8169_private {
>> void __iomem *mmio_addr; /* memory map physical address */
>> struct pci_dev *pci_dev;
>> @@ -745,9 +761,19 @@ struct rtl8169_private {
>> dma_addr_t RxPhyAddr;
>> struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
>> struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
>> + struct rtl8169_irq irq_tbl[R8169_MAX_MSIX_VEC];
>> + struct rtl8169_napi r8169napi[R8169_MAX_MSIX_VEC];
>> + u16 isr_reg[R8169_MAX_MSIX_VEC];
>> + u16 imr_reg[R8169_MAX_MSIX_VEC];
>
>These arrays result in unecessarily high memory consumption on all other
>chip versions. Can't they be dynamically allocated, only in case driver supports
>RSS for the respective chip version?
>
I will replace these arrays with pointers in v2.
During rtl_init_one, driver will dynamically allocate memory(e.g., via devm_kcalloc) based on the rx queue number that hardware supports. In this case, 8 for 8127 and 1 for other chips. So the init path will be the same for all the chips.
>> + unsigned int num_rx_rings;
>> u16 cp_cmd;
>> u16 tx_lpi_timer;
>> u32 irq_mask;
>> + u8 min_irq_nvecs;
>> + u8 max_irq_nvecs;
>
>It seems these values are actually constants.
>Can't we avoid these members?
These values are different for different chips (max_irq_nvecs 32 for 8127 and 1 for others. To avoid these members, I want know whether I should add a helper function to get the max_irq_nvecs/min_irq_nvecs number for different chips according to tp->mac_version or just use local variables in rtl_init_one?
>
>> + u8 hw_supp_isr_ver;
>> + u8 hw_curr_isr_ver;
>> + u8 irq_nvecs;
>> int irq;
>> struct clk *clk;
>>
>> @@ -763,6 +789,8 @@ struct rtl8169_private {
>> unsigned aspm_manageable:1;
>> unsigned dash_enabled:1;
>> bool sfp_mode:1;
>> + bool rss_support:1;
>> + bool rss_enable:1;
>> dma_addr_t counters_phys_addr;
>> struct rtl8169_counters *counters;
>> struct rtl8169_tc_offsets tc_offset; @@ -2680,6 +2708,44 @@
>> static void rtl_hw_reset(struct rtl8169_private *tp)
>> rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); }
>>
>> +static void rtl_setup_mqs_reg(struct rtl8169_private *tp) {
>> + if (tp->mac_version <= RTL_GIGA_MAC_VER_52) {
>> + tp->isr_reg[0] = IntrStatus;
>> + tp->imr_reg[0] = IntrMask;
>> + } else {
>> + tp->isr_reg[0] = IntrStatus_8125;
>> + tp->imr_reg[0] = IntrMask_8125;
>> + }
>> +
>> + for (int i = 1; i < tp->max_irq_nvecs; i++)
>> + tp->isr_reg[i] = (u16)(INTR_VEC_MAP_STATUS + (i - 1) *
>> + 4);
>> +
>> + for (int i = 1; i < tp->max_irq_nvecs; i++)
>> + tp->imr_reg[i] = (u16)(INTR_VEC_MAP_MASK + (i - 1) * 4);
>
>This populates the array with constant values. Therefore, can't you avoid
>using this array?
I review the code, I find these array are not used. So I will remove these code.
>
>> +}
>> +
>> +static void rtl_software_parameter_initialize(struct rtl8169_private
>> +*tp) {
>> + tp->num_rx_rings = 1;
>> +
>> + switch (tp->mac_version) {
>> + case RTL_GIGA_MAC_VER_80:
>> + tp->min_irq_nvecs = 1;
>> + tp->max_irq_nvecs = 1;
>> + tp->hw_supp_isr_ver = 6;
>
>Magic value 6 requires at least an explanation and a constant.
hw_supp_isr_ver means different intr status for different chips. For 8127, 6 means interrupt 0-7 is for rx, 8-16 is for tx. For 8125, if hw_supp_isr_ver is 5, this means 0-15 is for rx, 16 and 17 is for tx. The interrupt is distributed according to hw_supp_isr_ver.
>
>> + break;
>> + default:
>> + tp->min_irq_nvecs = 1;
>> + tp->max_irq_nvecs = 1;
>> + tp->hw_supp_isr_ver = 1;
>> + break;
>> + }
>> + tp->hw_curr_isr_ver = tp->hw_supp_isr_ver;
>
>This indicates that the current version can be set to a version which is not the
>supported one. This is misleading.
>- Is supp_isr_ver the highest supported isr version?
>- And does this mean that each chip is backwards-compatible and
> supports also all lower isr versions?
>
All the chips support hw_supp_isr_ver = 1. This means the old interrupt mapping. And the chips are not backwards-compatible and don’t support the lower isr version. hw_supp_isr_ver is the specific version the chip support.
>> +
>> + rtl_setup_mqs_reg(tp);
>> +}
>> +
>> static void rtl_request_firmware(struct rtl8169_private *tp) {
>> struct rtl_fw *rtl_fw;
>> @@ -4266,9 +4332,21 @@ static void rtl8169_tx_clear(struct rtl8169_private
>*tp)
>> netdev_reset_queue(tp->dev);
>> }
>>
>> +static void rtl8169_napi_disable(struct rtl8169_private *tp) {
>> + for (int i = 0; i < tp->irq_nvecs; i++)
>> + napi_disable(&tp->r8169napi[i].napi);
>> +}
>> +
>> +static void rtl8169_napi_enable(struct rtl8169_private *tp) {
>> + for (int i = 0; i < tp->irq_nvecs; i++)
>> + napi_enable(&tp->r8169napi[i].napi);
>> +}
>> +
>> static void rtl8169_cleanup(struct rtl8169_private *tp) {
>> - napi_disable(&tp->napi);
>> + rtl8169_napi_disable(tp);
>>
>> /* Give a racing hard_start_xmit a few cycles to complete. */
>> synchronize_net();
>> @@ -4313,8 +4391,8 @@ static void rtl_reset_work(struct rtl8169_private
>*tp)
>>
>> for (i = 0; i < NUM_RX_DESC; i++)
>> rtl8169_mark_to_asic(tp->RxDescArray + i);
>> + rtl8169_napi_enable(tp);
>>
>> - napi_enable(&tp->napi);
>
>This moves the empty line. It should remain where it is.
>
>> rtl_hw_start(tp);
>> }
>>
>> @@ -4820,7 +4898,7 @@ static int rtl_rx(struct net_device *dev, struct
>rtl8169_private *tp, int budget
>> goto release_descriptor;
>> }
>>
>> - skb = napi_alloc_skb(&tp->napi, pkt_size);
>> + skb = napi_alloc_skb(&tp->r8169napi[0].napi, pkt_size);
>> if (unlikely(!skb)) {
>> dev->stats.rx_dropped++;
>> goto release_descriptor;
>> @@ -4844,7 +4922,7 @@ static int rtl_rx(struct net_device *dev, struct
>rtl8169_private *tp, int budget
>> if (skb->pkt_type == PACKET_MULTICAST)
>> dev->stats.multicast++;
>>
>> - napi_gro_receive(&tp->napi, skb);
>> + napi_gro_receive(&tp->r8169napi[0].napi, skb);
>>
>> dev_sw_netstats_rx_add(dev, pkt_size);
>> release_descriptor:
>> @@ -4856,7 +4934,8 @@ static int rtl_rx(struct net_device *dev, struct
>rtl8169_private *tp, int budget
>>
>> static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
>> {
>> - struct rtl8169_private *tp = dev_instance;
>> + struct rtl8169_napi *napi = dev_instance;
>> + struct rtl8169_private *tp = napi->priv;
>> u32 status = rtl_get_events(tp);
>>
>> if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
>> @@ -4873,13 +4952,53 @@ static irqreturn_t rtl8169_interrupt(int irq, void
>*dev_instance)
>> phy_mac_interrupt(tp->phydev);
>>
>> rtl_irq_disable(tp);
>> - napi_schedule(&tp->napi);
>> + napi_schedule(&napi->napi);
>> out:
>> rtl_ack_events(tp, status);
>>
>> return IRQ_HANDLED;
>> }
>>
>> +static void rtl8169_free_irq(struct rtl8169_private *tp)
>> +{
>> + for (int i = 0; i < tp->irq_nvecs; i++) {
>> + struct rtl8169_irq *irq = &tp->irq_tbl[i];
>> + struct rtl8169_napi *napi = &tp->r8169napi[i];
>> +
>> + if (irq->requested) {
>
>Is this check actually needed? Wouldn't pci_free_irq()
>also be fine with irqs not having been requested?
It is not needed, I will remove it.
>
>> + irq->requested = 0;
>> + pci_free_irq(tp->pci_dev, i, napi);
>> + }
>> + }
>> +}
>> +
>> +static int rtl8169_request_irq(struct rtl8169_private *tp)
>> +{
>> + const int len = sizeof(tp->irq_tbl[0].name);
>> + struct net_device *dev = tp->dev;
>> + struct rtl8169_napi *napi;
>> + struct rtl8169_irq *irq;
>> + int rc = 0;
>> +
>> + for (int i = 0; i < tp->irq_nvecs; i++) {
>> + irq = &tp->irq_tbl[i];
>> +
>> + napi = &tp->r8169napi[i];
>> + snprintf(irq->name, len, "%s-%d", dev->name, i);
>
>I don't think this is needed. pci_request_irq() supports dynamic
>irq name generation.
>
I will remove it.
>> + irq->handler = rtl8169_interrupt;
>> + rc = pci_request_irq(tp->pci_dev, i, irq->handler, NULL, napi, irq-
>>name);
>> + if (rc)
>> + break;
>> +
>> + irq->vector = pci_irq_vector(tp->pci_dev, i);
>> + irq->requested = 1;
>> + }
>> +
>> + if (rc)
>> + rtl8169_free_irq(tp);
>> + return rc;
>> +}
>> +
>> static void rtl_task(struct work_struct *work)
>> {
>> struct rtl8169_private *tp =
>> @@ -4914,9 +5033,10 @@ static void rtl_task(struct work_struct *work)
>>
>> static int rtl8169_poll(struct napi_struct *napi, int budget)
>> {
>> - struct rtl8169_private *tp = container_of(napi, struct rtl8169_private,
>napi);
>> + struct rtl8169_napi *r8169_napi = container_of(napi, struct rtl8169_napi,
>napi);
>> + struct rtl8169_private *tp = r8169_napi->priv;
>> struct net_device *dev = tp->dev;
>> - int work_done;
>> + int work_done = 0;
>>
>> rtl_tx(dev, tp, budget);
>>
>> @@ -5035,7 +5155,7 @@ static void rtl8169_up(struct rtl8169_private *tp)
>> phy_init_hw(tp->phydev);
>> phy_resume(tp->phydev);
>> rtl8169_init_phy(tp);
>> - napi_enable(&tp->napi);
>> + rtl8169_napi_enable(tp);
>> enable_work(&tp->wk.work);
>> rtl_reset_work(tp);
>>
>> @@ -5053,7 +5173,7 @@ static int rtl8169_close(struct net_device *dev)
>> rtl8169_down(tp);
>> rtl8169_rx_clear(tp);
>>
>> - free_irq(tp->irq, tp);
>> + rtl8169_free_irq(tp);
>>
>> phy_disconnect(tp->phydev);
>>
>> @@ -5108,7 +5228,8 @@ static int rtl_open(struct net_device *dev)
>> rtl_request_firmware(tp);
>>
>> irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD :
>IRQF_SHARED;
>> - retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
>> +
>> + retval = rtl8169_request_irq(tp);
>> if (retval < 0)
>> goto err_release_fw_2;
>>
>> @@ -5125,7 +5246,7 @@ static int rtl_open(struct net_device *dev)
>> return retval;
>>
>> err_free_irq:
>> - free_irq(tp->irq, tp);
>> + rtl8169_free_irq(tp);
>> err_release_fw_2:
>> rtl_release_firmware(tp);
>> rtl8169_rx_clear(tp);
>> @@ -5328,7 +5449,9 @@ static void rtl_set_irq_mask(struct rtl8169_private
>*tp)
>>
>> static int rtl_alloc_irq(struct rtl8169_private *tp)
>> {
>> + struct pci_dev *pdev = tp->pci_dev;
>> unsigned int flags;
>> + int nvecs;
>>
>> switch (tp->mac_version) {
>> case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
>> @@ -5344,7 +5467,18 @@ static int rtl_alloc_irq(struct rtl8169_private *tp)
>> break;
>> }
>>
>> - return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
>> + nvecs = pci_alloc_irq_vectors(pdev, tp->min_irq_nvecs, tp-
>>max_irq_nvecs, flags);
>> +
>> + if (nvecs < 0)
>> + nvecs = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
>
>This may be dangerous. If the first allocation fails, you may here allocate an
>interrupt of a type not supported by the chip.
>
I will replace it with pci_alloc_irq_vectors(pdev, 1, 1, flags).
>> +
>> + if (nvecs < 0)
>> + return nvecs;
>> +
>> + tp->irq = pci_irq_vector(pdev, 0);
>> + tp->irq_nvecs = nvecs;
>> +
>> + return 0;
>> }
>>
>> static void rtl_read_mac_address(struct rtl8169_private *tp,
>> @@ -5539,6 +5673,17 @@ static void rtl_hw_initialize(struct rtl8169_private
>*tp)
>> }
>> }
>>
>> +static int rtl8169_set_real_num_queue(struct rtl8169_private *tp)
>> +{
>> + int retval;
>> +
>> + retval = netif_set_real_num_tx_queues(tp->dev, 1);
>> + if (retval < 0)
>> + return retval;
>> +
>> + return netif_set_real_num_rx_queues(tp->dev, tp->num_rx_rings);
>> +}
>> +
>> static int rtl_jumbo_max(struct rtl8169_private *tp)
>> {
>> /* Non-GBit versions don't support jumbo frames */
>> @@ -5599,6 +5744,19 @@ static bool rtl_aspm_is_safe(struct
>rtl8169_private *tp)
>> return false;
>> }
>>
>> +static void r8169_init_napi(struct rtl8169_private *tp)
>> +{
>> + for (int i = 0; i < tp->irq_nvecs; i++) {
>> + struct rtl8169_napi *r8169napi = &tp->r8169napi[i];
>> + int (*poll)(struct napi_struct *napi, int budget);
>> +
>> + poll = rtl8169_poll;
>> + netif_napi_add(tp->dev, &r8169napi->napi, poll);
>> + r8169napi->priv = tp;
>> + r8169napi->index = i;
>> + }
>> +}
>> +
>> static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
>> {
>> const struct rtl_chip_info *chip;
>> @@ -5703,11 +5861,12 @@ static int rtl_init_one(struct pci_dev *pdev,
>const struct pci_device_id *ent)
>>
>> rtl_hw_reset(tp);
>>
>> + rtl_software_parameter_initialize(tp);
>> +
>> rc = rtl_alloc_irq(tp);
>> if (rc < 0)
>> return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
>>
>> - tp->irq = pci_irq_vector(pdev, 0);
>>
>> INIT_WORK(&tp->wk.work, rtl_task);
>> disable_work(&tp->wk.work);
>> @@ -5716,7 +5875,13 @@ static int rtl_init_one(struct pci_dev *pdev, const
>struct pci_device_id *ent)
>>
>> dev->ethtool_ops = &rtl8169_ethtool_ops;
>>
>> - netif_napi_add(dev, &tp->napi, rtl8169_poll);
>> + if (!tp->rss_support) {
>> + netif_napi_add(dev, &tp->r8169napi[0].napi, rtl8169_poll);
>> + tp->r8169napi[0].priv = tp;
>> + tp->r8169napi[0].index = 0;
>> + } else {
>> + r8169_init_napi(tp);
>> + }
>>
>> dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
>> NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
>> @@ -5778,6 +5943,10 @@ static int rtl_init_one(struct pci_dev *pdev, const
>struct pci_device_id *ent)
>> if (jumbo_max)
>> dev->max_mtu = jumbo_max;
>>
>> + rc = rtl8169_set_real_num_queue(tp);
>> + if (rc < 0)
>> + return dev_err_probe(&pdev->dev, rc, "set tx/rx num failure\n");
>> +
>> rtl_set_irq_mask(tp);
>>
>> tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp-
>>counters),
^ permalink raw reply
* [PATCH net-next v3] net: stmmac: Add support for TX/RX channel interrupt
From: muhammad.nazim.amirul.nazle.asmade @ 2026-05-07 4:19 UTC (permalink / raw)
To: netdev; +Cc: davem, kuba, pabeni, edumazet, andrew+netdev, linux-kernel
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Enable TX/RX channel interrupt registration for MAC that interrupts CPU
through shared peripheral interrupt (SPI).
Per-channel interrupts and interrupt-names are registered as follows,
e.g. 4 TX and 4 RX channels:
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma_tx0",
"dma_tx1",
"dma_tx2",
"dma_tx3",
"dma_rx0",
"dma_rx1",
"dma_rx2",
"dma_rx3";
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
Changes in v3:
- Add net-next tree prefix to subject line.
- Fix variable declarations to follow Reverse Christmas Tree order.
Changes in v2:
- Use -ENXIO to detect when interrupt name is not present,
and return any other negative error code to the caller.
---
.../ethernet/stmicro/stmmac/stmmac_platform.c | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 5cae2aa72906..9039e207ddbd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -732,6 +732,9 @@ static int stmmac_pltfr_get_irq_array(struct platform_device *pdev,
int stmmac_get_platform_resources(struct platform_device *pdev,
struct stmmac_resources *stmmac_res)
{
+ char irq_name[9];
+ int ret;
+ int irq;
+ int i;
memset(stmmac_res, 0, sizeof(*stmmac_res));
@@ -767,6 +770,30 @@ int stmmac_get_platform_resources(struct platform_device *pdev,
dev_info(&pdev->dev, "IRQ sfty not found\n");
}
+ /* For RX Channel */
+ for (i = 0; i < MTL_MAX_RX_QUEUES; i++) {
+ snprintf(irq_name, sizeof(irq_name), "dma_rx%i", i);
+ irq = platform_get_irq_byname_optional(pdev, irq_name);
+ if (irq == -ENXIO)
+ break;
+ else if (irq < 0)
+ return irq;
+
+ stmmac_res->rx_irq[i] = irq;
+ }
+
+ /* For TX Channel */
+ for (i = 0; i < MTL_MAX_TX_QUEUES; i++) {
+ snprintf(irq_name, sizeof(irq_name), "dma_tx%i", i);
+ irq = platform_get_irq_byname_optional(pdev, irq_name);
+ if (irq == -ENXIO)
+ break;
+ else if (irq < 0)
+ return irq;
+
+ stmmac_res->tx_irq[i] = irq;
+ }
+
stmmac_res->addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(stmmac_res->addr))
--
2.43.7
^ permalink raw reply related
* [PATCH v2 2/2] docs: acpi: dsd: add Motorcomm yt8xxx PHY properties
From: chunzhi.lin @ 2026-05-07 4:02 UTC (permalink / raw)
To: netdev
Cc: Frank.Sae, andrew, hkallweit1, linux, kuba, pabeni, edumazet,
davem, linux-acpi, rafael, lenb, chunzhi.lin
In-Reply-To: <20260507040221.3679454-1-linchunzhi0@gmail.com>
Document Motorcomm yt8xxx PHY ACPI _DSD properties consumed by
the motorcomm PHY driver.
Describe property placement, UUID usage, and reference the DT binding
for value constraints and defaults.
Signed-off-by: chunzhi.lin <linchunzhi0@gmail.com>
Changes in v2:
- Keep dsd/ entries sorted in Documentation/firmware-guide/acpi/index.rst
---
.../acpi/dsd/motorcomm-yt8xxx-phy.rst | 107 ++++++++++++++++++
Documentation/firmware-guide/acpi/index.rst | 1 +
2 files changed, 108 insertions(+)
create mode 100644 Documentation/firmware-guide/acpi/dsd/motorcomm-yt8xxx-phy.rst
diff --git a/Documentation/firmware-guide/acpi/dsd/motorcomm-yt8xxx-phy.rst b/Documentation/firmware-guide/acpi/dsd/motorcomm-yt8xxx-phy.rst
new file mode 100644
index 000000000000..d64a396fac81
--- /dev/null
+++ b/Documentation/firmware-guide/acpi/dsd/motorcomm-yt8xxx-phy.rst
@@ -0,0 +1,107 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+======================================
+Motorcomm yt8xxx PHY properties (_DSD)
+======================================
+
+This document describes ACPI _DSD device properties for Motorcomm yt8xxx
+Ethernet PHYs supported by the in-kernel driver in
+``drivers/net/phy/motorcomm.c``.
+
+The properties are exposed on the PHY device object under the MDIO bus ACPI
+device (the same objects that are registered via
+``fwnode_mdiobus_register_phy()``). MAC-side connection properties such as
+``phy-handle`` and ``phy-mode`` are documented in [acpi-mdio-phy]_.
+
+Property names and semantics are intentionally aligned with the Devicetree
+binding [motorcomm-yt8xxx]_ so that the same driver code path
+(``device_property_*`` on ``&phydev->mdio.dev``) can consume firmware
+described either as Devicetree or ACPI _DSD.
+
+UUID and placement
+==================
+
+Per [acpi-dsd-properties-rules]_ and [acpi-mdio-phy]_, properties must be
+placed in an _DSD package using the standard Device Properties UUID::
+
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
+
+Properties
+==========
+
+Unless noted otherwise, integer properties use the same allowed values and
+defaults as [motorcomm-yt8xxx]_.
+
+``rx-internal-delay-ps`` (u32, optional)
+ RGMII RX internal delay in picoseconds. Only meaningful when the link is
+ using RGMII modes with RX internal delay; see [motorcomm-yt8xxx]_.
+
+``tx-internal-delay-ps`` (u32, optional)
+ RGMII TX internal delay in picoseconds. Only meaningful when the link is
+ using RGMII modes with TX internal delay; see [motorcomm-yt8xxx]_.
+
+``motorcomm,clk-out-frequency-hz`` (u32, optional)
+ Clock output frequency on the PHY clock output pin. Allowed values and
+ default are defined in [motorcomm-yt8xxx]_.
+
+``motorcomm,keep-pll-enabled`` (boolean, optional)
+ If true, keep the PLL enabled even when there is no link (useful for using
+ the clock output without an Ethernet link). See [motorcomm-yt8xxx]_.
+
+``motorcomm,auto-sleep-disabled`` (boolean, optional)
+ If true, disable the PHY auto-sleep behavior described in
+ [motorcomm-yt8xxx]_.
+
+``motorcomm,rx-clk-drv-microamp`` (u32, optional)
+ Drive strength for the ``rx_clk`` RGMII pad in microamps. Allowed values
+ depend on the configured RGMII LDO voltage; see [motorcomm-yt8xxx]_.
+
+``motorcomm,rx-data-drv-microamp`` (u32, optional)
+ Drive strength for the ``rx_data`` and ``rx_ctl`` RGMII pads in microamps.
+ See [motorcomm-yt8xxx]_.
+
+``motorcomm,tx-clk-adj-enabled`` (boolean, optional)
+ Enables adjustments related to ``motorcomm,tx-clk-*-inverted`` usage; see
+ [motorcomm-yt8xxx]_.
+
+``motorcomm,tx-clk-10-inverted`` (boolean, optional)
+``motorcomm,tx-clk-100-inverted`` (boolean, optional)
+``motorcomm,tx-clk-1000-inverted`` (boolean, optional)
+ Per-speed TX clock inversion options; see [motorcomm-yt8xxx]_.
+
+ASL example (illustrative)
+==========================
+
+The example below only shows PHY-local _DSD properties. A real platform
+still needs a MAC ``phy-handle`` and ``phy-mode`` package as in
+[acpi-mdio-phy]_.
+
+.. code-block:: none
+
+ Scope (\_SB.MDI0)
+ {
+ Device (PHY4)
+ {
+ Name (_ADR, 0x4)
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package (2) { "rx-internal-delay-ps", 2100 },
+ Package (2) { "tx-internal-delay-ps", 150 },
+ Package (2) { "motorcomm,clk-out-frequency-hz", 0 },
+ Package (2) { "motorcomm,keep-pll-enabled", 1 },
+ Package (2) { "motorcomm,auto-sleep-disabled", 1 },
+ }
+ })
+ }
+ }
+
+References
+==========
+
+.. [acpi-mdio-phy] Documentation/firmware-guide/acpi/dsd/phy.rst
+.. [acpi-dsd-properties-rules]
+ Documentation/firmware-guide/acpi/DSD-properties-rules.rst
+.. [motorcomm-yt8xxx]
+ Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
diff --git a/Documentation/firmware-guide/acpi/index.rst b/Documentation/firmware-guide/acpi/index.rst
index b246902f523f..db9eb7229948 100644
--- a/Documentation/firmware-guide/acpi/index.rst
+++ b/Documentation/firmware-guide/acpi/index.rst
@@ -11,6 +11,7 @@ ACPI Support
dsd/graph
dsd/data-node-references
dsd/leds
+ dsd/motorcomm-yt8xxx-phy
dsd/phy
enumeration
osi
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/2] net: phy: motorcomm: use device properties for firmware tuning
From: chunzhi.lin @ 2026-05-07 4:02 UTC (permalink / raw)
To: netdev
Cc: Frank.Sae, andrew, hkallweit1, linux, kuba, pabeni, edumazet,
davem, linux-acpi, rafael, lenb, chunzhi.lin
In-Reply-To: <20260507040221.3679454-1-linchunzhi0@gmail.com>
The Motorcomm PHY driver reads optional firmware properties via
of_property_read_*() from phydev->mdio.dev.of_node. This works for
Device Tree based systems, but causes ACPI platforms to ignore the same
properties when they are supplied through _DSD.
As a result, ACPI-described Motorcomm PHY devices fall back to default
settings instead of applying firmware-provided tuning such as
rx/tx internal delay, drive strength, clock output frequency, and
optional boolean controls like auto-sleep-disabled,
keep-pll-enabled, and tx clock inversion.
Switch these lookups to device_property_read_*() so the driver uses the
generic firmware node interface and can consume the same property names
from either Device Tree or ACPI.
This keeps the existing DT behavior unchanged while allowing ACPI
platforms to honor PHY configuration from firmware.
We have completed testing on Sophgo RISC-V architecture server SD3-10.
This server has a 64-core Thead C920 CPU whose DWMAC is connected to
Motorcomm's PHY YT8531. This server supports UEFI boot and it would like
to use the ACPI table.
Signed-off-by: chunzhi.lin <linchunzhi0@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/phy/motorcomm.c | 41 ++++++++++++++++++-------------------
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index 4d62f7b36212..708491bc198a 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c
@@ -10,7 +10,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/phy.h>
-#include <linux/of.h>
+#include <linux/property.h>
#define PHY_ID_YT8511 0x0000010a
#define PHY_ID_YT8521 0x0000011a
@@ -843,12 +843,12 @@ static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
u16 *rxc_dly_en,
u32 dflt)
{
- struct device_node *node = phydev->mdio.dev.of_node;
+ struct device *dev = &phydev->mdio.dev;
int tb_size_half = tb_size / 2;
u32 val;
int i;
- if (of_property_read_u32(node, prop_name, &val))
+ if (device_property_read_u32(dev, prop_name, &val))
goto err_dts_val;
/* when rxc_dly_en is NULL, it is get the delay for tx, only half of
@@ -996,12 +996,12 @@ static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur)
static int yt8531_set_ds(struct phy_device *phydev)
{
- struct device_node *node = phydev->mdio.dev.of_node;
+ struct device *dev = &phydev->mdio.dev;
u32 ds_field_low, ds_field_hi, val;
int ret, ds;
/* set rgmii rx clk driver strength */
- if (!of_property_read_u32(node, "motorcomm,rx-clk-drv-microamp", &val)) {
+ if (!device_property_read_u32(dev, "motorcomm,rx-clk-drv-microamp", &val)) {
ds = yt8531_get_ds_map(phydev, val);
if (ds < 0)
return dev_err_probe(&phydev->mdio.dev, ds,
@@ -1018,7 +1018,7 @@ static int yt8531_set_ds(struct phy_device *phydev)
return ret;
/* set rgmii rx data driver strength */
- if (!of_property_read_u32(node, "motorcomm,rx-data-drv-microamp", &val)) {
+ if (!device_property_read_u32(dev, "motorcomm,rx-data-drv-microamp", &val)) {
ds = yt8531_get_ds_map(phydev, val);
if (ds < 0)
return dev_err_probe(&phydev->mdio.dev, ds,
@@ -1051,7 +1051,6 @@ static int yt8531_set_ds(struct phy_device *phydev)
*/
static int yt8521_probe(struct phy_device *phydev)
{
- struct device_node *node = phydev->mdio.dev.of_node;
struct device *dev = &phydev->mdio.dev;
struct yt8521_priv *priv;
int chip_config;
@@ -1101,7 +1100,7 @@ static int yt8521_probe(struct phy_device *phydev)
return ret;
}
- if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq))
+ if (device_property_read_u32(dev, "motorcomm,clk-out-frequency-hz", &freq))
freq = YTPHY_DTS_OUTPUT_CLK_DIS;
if (phydev->drv->phy_id == PHY_ID_YT8521) {
@@ -1169,11 +1168,11 @@ static int yt8521_probe(struct phy_device *phydev)
static int yt8531_probe(struct phy_device *phydev)
{
- struct device_node *node = phydev->mdio.dev.of_node;
+ struct device *dev = &phydev->mdio.dev;
u16 mask, val;
u32 freq;
- if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq))
+ if (device_property_read_u32(dev, "motorcomm,clk-out-frequency-hz", &freq))
freq = YTPHY_DTS_OUTPUT_CLK_DIS;
switch (freq) {
@@ -1665,7 +1664,7 @@ static int yt8521_resume(struct phy_device *phydev)
*/
static int yt8521_config_init(struct phy_device *phydev)
{
- struct device_node *node = phydev->mdio.dev.of_node;
+ struct device *dev = &phydev->mdio.dev;
int old_page;
int ret = 0;
@@ -1680,7 +1679,7 @@ static int yt8521_config_init(struct phy_device *phydev)
goto err_restore_page;
}
- if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
+ if (device_property_read_bool(dev, "motorcomm,auto-sleep-disabled")) {
/* disable auto sleep */
ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG,
YT8521_ESC1R_SLEEP_SW, 0);
@@ -1688,7 +1687,7 @@ static int yt8521_config_init(struct phy_device *phydev)
goto err_restore_page;
}
- if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) {
+ if (device_property_read_bool(dev, "motorcomm,keep-pll-enabled")) {
/* enable RXC clock when no wire plug */
ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
YT8521_CGR_RX_CLK_EN, 0);
@@ -1801,14 +1800,14 @@ static int yt8521_led_hw_control_get(struct phy_device *phydev, u8 index,
static int yt8531_config_init(struct phy_device *phydev)
{
- struct device_node *node = phydev->mdio.dev.of_node;
+ struct device *dev = &phydev->mdio.dev;
int ret;
ret = ytphy_rgmii_clk_delay_config_with_lock(phydev);
if (ret < 0)
return ret;
- if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
+ if (device_property_read_bool(dev, "motorcomm,auto-sleep-disabled")) {
/* disable auto sleep */
ret = ytphy_modify_ext_with_lock(phydev,
YT8521_EXTREG_SLEEP_CONTROL1_REG,
@@ -1817,7 +1816,7 @@ static int yt8531_config_init(struct phy_device *phydev)
return ret;
}
- if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) {
+ if (device_property_read_bool(dev, "motorcomm,keep-pll-enabled")) {
/* enable RXC clock when no wire plug */
ret = ytphy_modify_ext_with_lock(phydev,
YT8521_CLOCK_GATING_REG,
@@ -1844,7 +1843,7 @@ static int yt8531_config_init(struct phy_device *phydev)
*/
static void yt8531_link_change_notify(struct phy_device *phydev)
{
- struct device_node *node = phydev->mdio.dev.of_node;
+ struct device *dev = &phydev->mdio.dev;
bool tx_clk_1000_inverted = false;
bool tx_clk_100_inverted = false;
bool tx_clk_10_inverted = false;
@@ -1852,17 +1851,17 @@ static void yt8531_link_change_notify(struct phy_device *phydev)
u16 val = 0;
int ret;
- if (of_property_read_bool(node, "motorcomm,tx-clk-adj-enabled"))
+ if (device_property_read_bool(dev, "motorcomm,tx-clk-adj-enabled"))
tx_clk_adj_enabled = true;
if (!tx_clk_adj_enabled)
return;
- if (of_property_read_bool(node, "motorcomm,tx-clk-10-inverted"))
+ if (device_property_read_bool(dev, "motorcomm,tx-clk-10-inverted"))
tx_clk_10_inverted = true;
- if (of_property_read_bool(node, "motorcomm,tx-clk-100-inverted"))
+ if (device_property_read_bool(dev, "motorcomm,tx-clk-100-inverted"))
tx_clk_100_inverted = true;
- if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted"))
+ if (device_property_read_bool(dev, "motorcomm,tx-clk-1000-inverted"))
tx_clk_1000_inverted = true;
if (phydev->speed < 0)
--
2.34.1
^ permalink raw reply related
* [PATCH net-next v2 0/2] net: phy: motorcomm: add ACPI _DSD property support
From: chunzhi.lin @ 2026-05-07 4:02 UTC (permalink / raw)
To: netdev
Cc: Frank.Sae, andrew, hkallweit1, linux, kuba, pabeni, edumazet,
davem, linux-acpi, rafael, lenb
Hi,
This series makes the Motorcomm PHY driver parse firmware properties via
device_property_*() so the same property set can be provided by either
Devicetree or ACPI _DSD.
Patch 1 switches drivers/net/phy/motorcomm.c from of_property_*() to
device_property_*() on &phydev->mdio.dev.
Patch 2 documents Motorcomm yt8xxx PHY ACPI _DSD properties under
Documentation/firmware-guide/acpi/dsd and links the new document from
the ACPI index.
Changes in v2:
- docs: sort dsd/motorcomm-yt8xxx-phy within dsd/ entries in
Documentation/firmware-guide/acpi/index.rst
Thanks,
chunzhi.lin
chunzhi.lin (2):
net: phy: motorcomm: use device properties for firmware tuning
docs: acpi: dsd: add Motorcomm yt8xxx PHY properties
Documentation/firmware-guide/acpi/dsd/motorcomm-yt8xxx-phy.rst | 107 +++++++++++++
Documentation/firmware-guide/acpi/index.rst | 1 +
drivers/net/phy/motorcomm.c | 41 +++--
3 files changed, 128 insertions(+), 21 deletions(-)
create mode 100644 Documentation/firmware-guide/acpi/dsd/motorcomm-yt8xxx-phy.rst
^ permalink raw reply
* Re: [syzbot] [rdma] general protection fault in kernel_sock_shutdown (4)
From: syzbot @ 2026-05-07 3:52 UTC (permalink / raw)
To: akpm, arjan, davem, dsahern, edumazet, hdanton, horms, jgg, kuba,
kuni1840, kuniyu, leon, linux-kernel, linux-rdma, netdev, pabeni,
syzkaller-bugs, yanjun.zhu, zyjzyj2000
In-Reply-To: <69ea344f.a00a0220.17a17.0040.GAE@google.com>
syzbot has found a reproducer for the following issue on:
HEAD commit: 735d2f48cada Add linux-next specific files for 20260506
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=14f0e56a580000
kernel config: https://syzkaller.appspot.com/x/.config?x=a88880f0f312e277
dashboard link: https://syzkaller.appspot.com/bug?extid=d8f76778263ab65c2b21
compiler: Debian clang version 21.1.8 (++20251221033036+2078da43e25a-1~exp1~20251221153213.50), Debian LLD 21.1.8
syz repro: https://syzkaller.appspot.com/x/repro.syz?x=125c9f6c580000
C reproducer: https://syzkaller.appspot.com/x/repro.c?x=166580ec580000
Downloadable assets:
disk image: https://storage.googleapis.com/syzbot-assets/e65b731bdb98/disk-735d2f48.raw.xz
vmlinux: https://storage.googleapis.com/syzbot-assets/60db2f3d3f2f/vmlinux-735d2f48.xz
kernel image: https://storage.googleapis.com/syzbot-assets/55da282f7ab4/bzImage-735d2f48.xz
IMPORTANT: if you fix the issue, please add the following tag to the commit:
Reported-by: syzbot+d8f76778263ab65c2b21@syzkaller.appspotmail.com
rdma_rxe: rxe_newlink: failed to add lo
Oops: gen[ 127.022080][ T5982] Oops: general protection fault, probably for non-canonical address 0xdffffc0000000004: 0000 [#1] SMP KASAN PTI
KASAN: null-ptr-deref in range [0x0000000000000020-0x0000000000000027]
CPU: 1 UID: 0 PID: 5982 Comm: syz.3.20 Not tainted syzkaller #0 PREEMPT_{RT,(full)}
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 04/18/2026
RIP: 0010:kernel_sock_shutdown+0x2a/0x70 net/socket.c:3803
Code: f3 0f 1e fa 41 57 41 56 41 54 53 89 f3 49 89 fe 49 bc 00 00 00 00 00 fc ff df e8 e1 25 c5 f8 4d 8d 7e 20 4c 89 f8 48 c1 e8 03 <42> 80 3c 20 00 74 08 4c 89 ff e8 27 bf 2e f9 4d 8b 3f 49 83 c7 68
RSP: 0018:ffffc900015ef090 EFLAGS: 00010202
RAX: 0000000000000004 RBX: 0000000000000002 RCX: ffff88802dd89ec0
RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000
RBP: 0000000000000001 R08: 0000000000000000 R09: 0000000000000000
R10: dffffc0000000000 R11: ffffed1007cc8979 R12: dffffc0000000000
R13: dffffc0000000000 R14: 0000000000000000 R15: 0000000000000020
FS: 000055556d432500(0000) GS:ffff888125dca000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000001b34563fff CR3: 0000000042b1c000 CR4: 00000000003526f0
Call Trace:
<TASK>
udp_tunnel_sock_release+0x6d/0x80 net/ipv4/udp_tunnel_core.c:197
rxe_release_udp_tunnel drivers/infiniband/sw/rxe/rxe_net.c:294 [inline]
rxe_sock_put drivers/infiniband/sw/rxe/rxe_net.c:639 [inline]
rxe_net_del+0xfb/0x290 drivers/infiniband/sw/rxe/rxe_net.c:660
rxe_dellink+0x15/0x20 drivers/infiniband/sw/rxe/rxe.c:254
nldev_dellink+0x304/0x3d0 drivers/infiniband/core/nldev.c:1849
rdma_nl_rcv_msg drivers/infiniband/core/netlink.c:-1 [inline]
rdma_nl_rcv_skb drivers/infiniband/core/netlink.c:239 [inline]
rdma_nl_rcv+0x6d7/0xa10 drivers/infiniband/core/netlink.c:259
netlink_unicast_kernel net/netlink/af_netlink.c:1319 [inline]
netlink_unicast+0x780/0x920 net/netlink/af_netlink.c:1345
netlink_sendmsg+0x813/0xb40 net/netlink/af_netlink.c:1895
sock_sendmsg_nosec+0x112/0x150 net/socket.c:797
__sock_sendmsg net/socket.c:812 [inline]
____sys_sendmsg+0x55c/0x870 net/socket.c:2716
___sys_sendmsg+0x2a5/0x360 net/socket.c:2770
__sys_sendmsg net/socket.c:2802 [inline]
__do_sys_sendmsg net/socket.c:2807 [inline]
__se_sys_sendmsg net/socket.c:2805 [inline]
__x64_sys_sendmsg+0x1c3/0x2a0 net/socket.c:2805
do_syscall_x64 arch/x86/entry/syscall_64.c:63 [inline]
do_syscall_64+0x15f/0xf80 arch/x86/entry/syscall_64.c:94
entry_SYSCALL_64_after_hwframe+0x77/0x7f
RIP: 0033:0x7f89172fcdd9
Code: ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 e8 ff ff ff f7 d8 64 89 01 48
RSP: 002b:00007ffe8bf8c018 EFLAGS: 00000246 ORIG_RAX: 000000000000002e
RAX: ffffffffffffffda RBX: 00007f8917575fa0 RCX: 00007f89172fcdd9
RDX: 0000000000000000 RSI: 00002000000002c0 RDI: 0000000000000006
RBP: 00007f8917392d69 R08: 0000000000000000 R09: 0000000000000000
R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000
R13: 00007f8917575fac R14: 00007f8917575fa0 R15: 00007f8917575fa0
</TASK>
Modules linked in:
---[ end trace 0000000000000000 ]---
RIP: 0010:kernel_sock_shutdown+0x2a/0x70 net/socket.c:3803
Code: f3 0f 1e fa 41 57 41 56 41 54 53 89 f3 49 89 fe 49 bc 00 00 00 00 00 fc ff df e8 e1 25 c5 f8 4d 8d 7e 20 4c 89 f8 48 c1 e8 03 <42> 80 3c 20 00 74 08 4c 89 ff e8 27 bf 2e f9 4d 8b 3f 49 83 c7 68
RSP: 0018:ffffc900015ef090 EFLAGS: 00010202
RAX: 0000000000000004 RBX: 0000000000000002 RCX: ffff88802dd89ec0
RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000
RBP: 0000000000000001 R08: 0000000000000000 R09: 0000000000000000
R10: dffffc0000000000 R11: ffffed1007cc8979 R12: dffffc0000000000
R13: dffffc0000000000 R14: 0000000000000000 R15: 0000000000000020
FS: 000055556d432500(0000) GS:ffff888125dca000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000000000008 CR3: 0000000042b1c000 CR4: 00000000003526f0
----------------
Code disassembly (best guess):
0: f3 0f 1e fa endbr64
4: 41 57 push %r15
6: 41 56 push %r14
8: 41 54 push %r12
a: 53 push %rbx
b: 89 f3 mov %esi,%ebx
d: 49 89 fe mov %rdi,%r14
10: 49 bc 00 00 00 00 00 movabs $0xdffffc0000000000,%r12
17: fc ff df
1a: e8 e1 25 c5 f8 call 0xf8c52600
1f: 4d 8d 7e 20 lea 0x20(%r14),%r15
23: 4c 89 f8 mov %r15,%rax
26: 48 c1 e8 03 shr $0x3,%rax
* 2a: 42 80 3c 20 00 cmpb $0x0,(%rax,%r12,1) <-- trapping instruction
2f: 74 08 je 0x39
31: 4c 89 ff mov %r15,%rdi
34: e8 27 bf 2e f9 call 0xf92ebf60
39: 4d 8b 3f mov (%r15),%r15
3c: 49 83 c7 68 add $0x68,%r15
---
If you want syzbot to run the reproducer, reply with:
#syz test: git://repo/address.git branch-or-commit-hash
If you attach or paste a git patch, syzbot will apply it before testing.
^ permalink raw reply
* Re: [PATCH net-next v2 3/3] net: dsa: yt921x: Add port qdisc tbf support
From: David Yang @ 2026-05-07 3:42 UTC (permalink / raw)
To: Jakub Kicinski
Cc: netdev, andrew, olteanv, davem, edumazet, pabeni, jhs, jiri,
horms, linux-kernel
In-Reply-To: <20260507012311.2187979-1-kuba@kernel.org>
On Thu, May 7, 2026 at 9:23 AM Jakub Kicinski <kuba@kernel.org> wrote:
> > + NL_SET_ERR_MSG_MOD(extack,
> > + "Offload not supported when mtu/peakrate is configured");
> > + return -EOPNOTSUPP;
> > + }
> > +
> > + if (!p->rate.mpu) {
>
> Does this code miss validation for p->rate.overhead?
>
> The TC TBF layer allows configuring overhead to account for additional
> headers. If the hardware relies on fixed wire frame sizes and the driver
> ignores p->rate.overhead, could this lead to a silent misconfiguration
> where the hardware shapes traffic at a different effective rate than
> requested?
I didn't see it can be non-zero while testing with tc-tbf(8).
> > @@ -1378,6 +1390,112 @@ yt921x_dsa_port_policer_add(struct dsa_switch *ds, int port,
> > return res;
> > }
> >
> > +static int
> > +yt921x_tbf_validate(struct yt921x_priv *priv,
> > + const struct tc_tbf_qopt_offload *qopt)
> > +{
> > + struct netlink_ext_ack *extack = qopt->extack;
> > +
> > + if (qopt->parent != TC_H_ROOT) {
> > + NL_SET_ERR_MSG_MOD(extack, "Parent should be \"root\"");
> > + return -EOPNOTSUPP;
> > + }
> > +
> > + switch (qopt->command) {
> > + case TC_TBF_REPLACE: {
> > + const struct tc_tbf_qopt_offload_replace_params *p;
> > +
> > + p = &qopt->replace_params;
> > +
> > + if (p->mtu || p->peak.rate_bytes_ps) {
> > + NL_SET_ERR_MSG_MOD(extack,
> > + "Offload not supported when mtu/peakrate is configured");
> > + return -EOPNOTSUPP;
> > + }
>
> Is the p->mtu check overly broad here? tbf_change() in
> net/sched/sch_tbf.c sets q->mtu from the user-supplied qopt->mtu whenever
> TCA_TBF_PBURST is absent, so p->mtu can be non-zero even when no peakrate
> has been requested. A user that explicitly passes the mtu parameter to
> tc would then be denied offload with an error that attributes the failure
> to mtu/peakrate together.
>
> Would gating only on p->peak.rate_bytes_ps better reflect what the
> hardware cannot do?
IIRC I have checked that with tc-tbf(8) (or I used the wrong series);
will check that later.
> > +
> > + if (!p->rate.mpu) {
> > + NL_SET_ERR_MSG_MOD(extack, "Assuming mpu = 64");
> > + } else if (p->rate.mpu != 64) {
> > + NL_SET_ERR_MSG_MOD(extack,
> > + "Offload not supported when mpu is other than 64");
> > + return -EOPNOTSUPP;
> > + }
>
> Is setting an extack message on the success path intentional?
> psched_ratecfg_precompute() leaves mpu at 0 by default, so the common
> tc qdisc add ... tbf rate X burst Y invocation will hit the first branch,
> return 0, and iproute2 will then print:
>
> Warning: yt921x: Assuming mpu = 64.
>
> on every TBF replace.
https://lore.kernel.org/all/20260413153248.0588690b@kernel.org/
...BTW we can use extack for "warnings" like this, too
> Also, is the assumption actually enforced anywhere? yt921x_marker_tfm_shape()
> and yt921x_marker_tfm() do not appear to compensate the rate computation
> for a 64-byte MPU, so the message seems to document an assumption that is
> not modelled by the transform.
tc-tbf(8): "For ethernet, no packet uses less than 64 bytes." I don't
see a need for rate computation unless I get it wrong.
> > +
> > + break;
> > + }
> > + default:
> > + break;
> > + }
> > +
> > + return 0;
> > +}
>
> Would it be clearer to have yt921x_tbf_validate() return -EOPNOTSUPP for
> commands the handler cannot service, so the supported command set is
> stated once? The default arm here returns 0 for every command other than
> TC_TBF_REPLACE (including TC_TBF_STATS and TC_TBF_GRAFT) while
> yt921x_dsa_port_setup_tc_tbf_port() below returns -EOPNOTSUPP for those
> same commands. There is no observable bug today, but if the validator is
> ever used on its own the two lists can drift.
>
> > +
> > +static int
> > +yt921x_dsa_port_setup_tc_tbf_port(struct dsa_switch *ds, int port,
> > + const struct tc_tbf_qopt_offload *qopt)
> > +{
> > + struct yt921x_priv *priv = to_yt921x_priv(ds);
> > + struct netlink_ext_ack *extack = qopt->extack;
> > + u32 ctrls[2];
> > + int res;
> > +
> > + switch (qopt->command) {
> > + case TC_TBF_DESTROY:
> > + ctrls[0] = 0;
> > + ctrls[1] = 0;
> > + break;
>
> Is there a concern about the write ordering on teardown?
> yt921x_reg64_write() -> yt921x_regs_write() performs two independent
> register writes (reg+0 then reg+4). On TC_TBF_DESTROY the first write
> sets CIR=0 and CBS=0 while the previously programmed EN bit in ctrls[1]
> is still set; only the second write clears EN. The REPLACE path writes
> configuration before arming EN, but the inverse is not followed here.
>
> Would writing ctrls[1]=0 first (or clearing EN via a read-modify-write
> before zeroing CIR/CBS) be safer for the hardware state machine?
The AI got confused on register operations; see comment for multi-word
registers.
> > + case TC_TBF_REPLACE: {
> [ ... ]
> > + ctrls[0] = YT921X_PORT_SHAPE_CTRLa_CIR(marker.cir) |
> > + YT921X_PORT_SHAPE_CTRLa_CBS(marker.cbs);
> > + ctrls[1] = YT921X_PORT_SHAPE_CTRLb_UNIT(marker.unit) |
> > + YT921X_PORT_SHAPE_CTRLb_EN;
> > + break;
> > + }
> > + default:
> > + return -EOPNOTSUPP;
> > + }
>
> Does returning -EOPNOTSUPP for TC_TBF_STATS defeat the hw offload
> indicator? qdisc_offload_dump_helper() in net/sched/sch_api.c first
> clears TCQ_F_OFFLOADED, then calls into the driver, and only re-sets the
> flag on a zero return:
No one else did that; mt753x_tc_setup_qdisc_tbf().
^ permalink raw reply
* Re: [PATCH net-next v8 1/2] net: pppoe: implement GRO/GSO support
From: Qingfang Deng @ 2026-05-07 3:36 UTC (permalink / raw)
To: Simon Horman
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, shuah, willemb,
petrm, anubhavsinggh, richardbgobert, netdev, linux-kselftest,
linux-kernel, linux-ppp, Pablo Neira Ayuso
In-Reply-To: <20260506121401.651540-1-horms@kernel.org>
On 2026/5/6 20:14, Simon Horman wrote:
> From: 'Simon Horman' <horms@kernel.org>
>
> This is an AI-generated review of your patch. The human sending this
> email has considered the AI review valid, or at least plausible.
> Full review at: https://sashiko.dev
> ---
> net: pppoe: implement GRO/GSO support
>
> This commit adds GRO and GSO support for PPPoE, which improves rx throughput
> significantly by handling packets where the pppoe header length field matches
> the exact packet length.
>
>> diff --git a/drivers/net/ppp/pppoe.c b/drivers/net/ppp/pppoe.c
>> index bdd61c504a1c4..363204e0c49a1 100644
>> --- a/drivers/net/ppp/pppoe.c
>> +++ b/drivers/net/ppp/pppoe.c
> [ ... ]
>> @@ -1103,6 +1104,164 @@ static struct pernet_operations pppoe_net_ops = {
>> .size = sizeof(struct pppoe_net),
>> };
>>
>> +static u16
>> +compare_pppoe_header(const struct pppoe_hdr *phdr,
>> + const struct pppoe_hdr *phdr2)
>> +{
>> + __be16 proto = *(const __be16 *)(phdr + 1);
> Because struct pppoe_hdr is packed, the compiler assigns it 1-byte alignment
> semantics, which phdr + 1 inherits.
>
> Does explicitly casting this to __be16 * bypass the compiler's unaligned access
> protections?
>
> If skb->data has an odd alignment from the NIC, this could trigger a fatal
> unaligned memory access exception on strict-alignment architectures. Would it
> be safer to use get_unaligned() here?
You can disregard all the alignment warnings. On those architectures,
drivers are required to 4-byte align the network header, so the PPPoE
header will also be aligned.
>> + __be16 proto2 = *(const __be16 *)(phdr2 + 1);
>> +
>> + return (__force u16)((phdr->sid ^ phdr2->sid) | (proto ^ proto2));
>> +}
>> +
>> +static __be16 pppoe_hdr_proto(const struct pppoe_hdr *phdr)
>> +{
>> + __be16 proto = *(const __be16 *)(phdr + 1);
> Could this also result in an unaligned access regression for the same reason?
>
> [ ... ]
>> +static struct sk_buff *pppoe_gro_receive(struct list_head *head,
>> + struct sk_buff *skb)
>> +{
> [ ... ]
>> + off_pppoe = skb_gro_offset(skb);
>> + hlen = off_pppoe + PPPOE_SES_HLEN;
>> + phdr = skb_gro_header(skb, hlen, off_pppoe);
>> + if (unlikely(!phdr))
>> + goto out;
>> +
>> + /* filter for session packets (type:1, ver:1, code:0) */
>> + if (*(const __be16 *)phdr != cpu_to_be16(0x1100))
> Is it possible this cast could similarly trigger an unaligned access exception
> if the header offset is oddly aligned?
>
> [ ... ]
>> +static struct sk_buff *pppoe_gso_segment(struct sk_buff *skb,
>> + netdev_features_t features)
>> +{
> [ ... ]
>> + segs = ptype->callbacks.gso_segment(skb, features);
>> + if (IS_ERR_OR_NULL(segs)) {
>> + skb_gso_error_unwind(skb, orig_type, PPPOE_SES_HLEN, mac_offset,
>> + mac_len);
> If the inner protocol's gso_segment callback returns NULL (indicating the
> hardware can natively offload the segmentation), skb_gso_error_unwind() will
> be called.
>
> skb_gso_error_unwind() unconditionally sets skb->encapsulation = 1. However,
> PPPoE does not configure the inner header offsets (such as
> skb->inner_network_header).
>
> When the driver sees skb->encapsulation == 1, could it attempt to read the
> uninitialized inner header offsets, parsing the outer MAC header as an inner
> IP header and misprogramming the hardware TSO context?
>
> Does PPPoE need to explicitly clear TSO features before calling the inner
> segmentation to force software segmentation, avoiding the need for
> skb_gso_error_unwind() here entirely?
I'm not sure how to test this. Is this what happens when the underlying
interface supports TSO?
+Cc: Pablo
^ permalink raw reply
* Re: [PATCH v2] net: dsa: realtek: rtl8365mb: add support for RTL8367SB
From: Luiz Angelo Daros de Luca @ 2026-05-07 3:24 UTC (permalink / raw)
To: Mieczyslaw Nalewaj
Cc: Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Alvin Šipraga,
Yury Norov, Rasmus Villemoes, Russell King, netdev
In-Reply-To: <05921e1f-693b-4322-a762-c8f03c386a78@yahoo.com>
Hi Mieczyslaw,
Thanks for the patch.
> Add chip info entry for the Realtek RTL8367SB switch. This device has
> chip ID 0x6367 and version 0x0010. It exposes two external interfaces:
> port 6 supports SGMII and HSGMII, while port 7 supports MII, TMII,
> RMII and RGMII. Use the existing 8365MB-VC jam table for initialization.
>
> Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
> ---
> drivers/net/dsa/realtek/rtl8365mb.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c
> index 073f12ca8028..84d6fdb94a96 100644
> --- a/drivers/net/dsa/realtek/rtl8365mb.c
> +++ b/drivers/net/dsa/realtek/rtl8365mb.c
> @@ -545,6 +545,18 @@ static const struct rtl8365mb_chip_info
> .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
> },
> {
> + .name = "RTL8367SB",
> + .chip_id = 0x6367,
> + .chip_ver = 0x0010,
> + .extints = {
> + { 6, 1, PHY_INTF(SGMII) | PHY_INTF(HSGMII) },
While reviewing the port capabilities, I noticed the description for
the RTL8367SB is identical to the RTL8367S (which does not make
sense). Documentation suggests the SB variant is more versatile. The
RTL8367SB appears to be a functional union of the RTL8367RB-VB and the
RTL8367S regarding its external interfaces:
+----------------+--------------------------+--------------------------+
| Port ID in API | EXT_PORT0(GMAC1) | EXT_PORT1(GMAC2) |
+----------------+--------------------------+--------------------------+
| RTL8367RB-VB | MII/TMII/RMII/RGMII | MII/TMII/RMII/RGMII |
+----------------+--------------------------+--------------------------+
| RTL8367SB | MII/TMII/RMII/RGMII | MII/TMII/RMII/RGMII |
| | SGMII / High-SGMII | |
+----------------+--------------------------+--------------------------+
| RTL8367S | SGMII / High-SGMII | MII/TMII/RMII/RGMII |
+----------------+--------------------------+--------------------------+
Source: https://cdn.jsdelivr.net/gh/libc0607/Realtek_switch_hacking@files/Realtek_Unmanaged_Switch_ProgrammingGuide.pdf
(last page)
It seems GMAC1 (Port 6) on the RTL8367SB actually supports the
standard (T)MII/RMII/RGMII modes in addition to the SGMII/HSGMII
modes.
Could you please double-check the datasheet?
Regards,
Luiz
^ permalink raw reply
* Re: [PATCH net-next v2 2/3] net: sched: tbf: pass all params to offload users
From: David Yang @ 2026-05-07 3:11 UTC (permalink / raw)
To: Jakub Kicinski
Cc: netdev, andrew, olteanv, davem, edumazet, pabeni, jhs, jiri,
horms, linux-kernel
In-Reply-To: <20260507012306.2187935-1-kuba@kernel.org>
On Thu, May 7, 2026 at 9:23 AM Jakub Kicinski <kuba@kernel.org> wrote:
> > qopt.command = TC_TBF_REPLACE;
> > qopt.handle = sch->handle;
> > qopt.parent = sch->parent;
> > - qopt.replace_params.rate = q->rate;
> > + qopt.replace_params.limit = q->limit;
> > qopt.replace_params.max_size = q->max_size;
>
> Does passing q->max_size here provide the driver with the original burst size?
>
> The software TBF overwrites q->max_size with min(burst, pburst) when a peak
> rate is configured. As a result, the offload API only passes this overwritten
> value, meaning a driver attempting to offload a dual-rate TBF is not given
> the original burst size in bytes and would have to reverse-engineer it from
> the nanosecond buffer value.
I'm not an expert on TBF so I don't know if it's fine to expose the
internal of schedulers to the drivers, also this would require changes
on struct tbf_sched_data.
> > struct tc_tbf_qopt_offload_replace_params {
> > + u32 limit;
> > + u32 max_size;
> > + s64 buffer;
> > + s64 mtu;
>
> The buffer and mtu fields are stored in tbf_sched_data in nanoseconds
> (see tbf_change() in net/sched/sch_tbf.c where they are derived via
> PSCHED_TICKS2NS(qopt->buffer) and psched_l2t_ns()), but they are
> exposed here as bare s64 buffer / s64 mtu right next to max_size
> which is a byte count.
>
> Would it be worth renaming these to buffer_ns / mtu_ns, or adding
> kerneldoc to describe their unit?
>
> A driver author reading this struct and seeing mtu adjacent to
> max_size might reasonably assume mtu is a byte MTU and program
> hardware accordingly.
These are carbon copies of struct tbf_sched_data, I see no reason to
rename just here.
> > struct psched_ratecfg rate;
> > - u32 max_size;
> > + struct psched_ratecfg peak;
>
> tbf_change() does memset(&peak, 0, sizeof(peak)) when no peakrate is
> configured, and the qdisc internally uses tbf_peak_present(q) which
> checks q->peak.rate_bytes_ps != 0 to distinguish absent from present.
>
> With peak exposed to offload drivers, every driver now has to
> reproduce this convention implicitly (e.g. by checking
> p->peak.rate_bytes_ps).
>
> Would an explicit indicator such as a bool peak_present field, or at
> least kerneldoc spelling out the rate_bytes_ps == 0 means absent
> contract, make this safer for future offload consumers?
No similar logic is found for struct flow_action_police.
^ permalink raw reply
* Re: [net-next v39] mctp pcc: Implement MCTP over PCC Transport
From: Jeremy Kerr @ 2026-05-07 3:02 UTC (permalink / raw)
To: Adam Young, Matt Johnston, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni
Cc: netdev, linux-kernel, Sudeep Holla, Jonathan Cameron, Huisong Li
In-Reply-To: <20260506214327.276069-1-admiyo@os.amperecomputing.com>
Hi Adam,
> +static void mctp_pcc_client_rx_callback(struct mbox_client *cl, void *mssg)
> +{
> + struct acpi_pcct_ext_pcc_shared_memory pcc_header;
> + struct mctp_pcc_ndev *mctp_pcc_ndev;
> + struct mctp_pcc_mailbox *inbox;
> + struct mctp_skb_cb *cb;
> + struct sk_buff *skb;
> + u32 header_length;
> + int size;
> +
> + mctp_pcc_ndev = container_of(cl, struct mctp_pcc_ndev, inbox.client);
> + inbox = &mctp_pcc_ndev->inbox;
> + memcpy_fromio(&pcc_header, inbox->chan->shmem, sizeof(pcc_header));
> +
> + // The message must at least have the PCC command indicating it is an MCTP
> + // message followed by the MCTP header, or we have a malformed message.
> + // This may be run on big endian system, but the data in the buffer is
> + // explicitly little endian.
> + header_length = le32_to_cpu(pcc_header.length);
> + if (header_length < sizeof(pcc_header.command) + sizeof(struct mctp_hdr)) {
> + dev_dstats_rx_dropped(mctp_pcc_ndev->ndev);
> + return;
> + }
> + // If the reported size is larger than the shared memory minus headers,
> + // something is wrong and treat the buffer as corrupted data.
> + if (header_length > inbox->chan->shmem_size - PCC_EXTRA_LEN) {
> + dev_dstats_rx_dropped(mctp_pcc_ndev->ndev);
> + return;
> + }
> + if (memcmp(&pcc_header.command, MCTP_SIGNATURE, MCTP_SIGNATURE_LENGTH) != 0) {
> + dev_dstats_rx_dropped(mctp_pcc_ndev->ndev);
> + return;
> + }
> +
> + size = header_length + PCC_EXTRA_LEN;
> + skb = netdev_alloc_skb(mctp_pcc_ndev->ndev, size);
> + if (!skb) {
> + dev_dstats_rx_dropped(mctp_pcc_ndev->ndev);
> + return;
> + }
Minor, but you have four instances of the dstats_rx_dropped call, that
may work as a shared error path.
> + skb_put(skb, size);
> + skb->protocol = htons(ETH_P_MCTP);
> + memcpy_fromio(skb->data, inbox->chan->shmem, size);
> + dev_dstats_rx_add(mctp_pcc_ndev->ndev, size);
> + skb_pull(skb, sizeof(pcc_header));
> + skb_reset_mac_header(skb);
> + skb_reset_network_header(skb);
> + cb = __mctp_cb(skb);
> + cb->halen = 0;
> + netif_rx(skb);
> +}
> +
> +static netdev_tx_t mctp_pcc_tx(struct sk_buff *skb, struct net_device *ndev)
> +{
> + struct acpi_pcct_ext_pcc_shared_memory *pcc_header;
> + struct mctp_pcc_ndev *mpnd = netdev_priv(ndev);
> + int len = skb->len;
> +
> + /* Consolidated a fragmented packet into contiguous memory */
> + if (skb_is_nonlinear(skb)) {
> + if (skb_linearize(skb))
> + goto error;
> + }
skb_linearize() already has the skb_is_nonlinear() check.
However, you don't need to call skb_linearize() anyway, as that will
happen for you in validate_xmit_skb(), since the driver does not
advertise support for nonlinear skbs.
> +
> + if (skb_cow_head(skb, sizeof(*pcc_header)))
> + goto error;
> +
> + /**
> + * This code could potentially be run on A Big Endian
> + * System. The ACPI specification requires that values
> + * in the shared buffer be little endian.
> + */
Minor, but I don't think this comment is necessary.
More importantly though, you're getting a bunch of warnings from the use
of these endian helpers:
drivers/net/mctp/mctp-pcc.c:70:25: warning: cast to restricted __le32
drivers/net/mctp/mctp-pcc.c:125:31: warning: incorrect type in assignment (different base types)
drivers/net/mctp/mctp-pcc.c:125:31: expected unsigned int [usertype] signature
drivers/net/mctp/mctp-pcc.c:125:31: got restricted __le32 [usertype]
drivers/net/mctp/mctp-pcc.c:126:27: warning: incorrect type in assignment (different base types)
drivers/net/mctp/mctp-pcc.c:126:27: expected unsigned int [usertype] flags
drivers/net/mctp/mctp-pcc.c:126:27: got restricted __le32 [usertype]
drivers/net/mctp/mctp-pcc.c:128:28: warning: incorrect type in assignment (different base types)
drivers/net/mctp/mctp-pcc.c:128:28: expected unsigned int [usertype] length
drivers/net/mctp/mctp-pcc.c:128:28: got restricted __le32 [usertype]
Looks like struct acpi_pcct_ext_pcc_shared_memory does not specify
fields as little endian, but host endian.
You could change to endian-annotated types to those ACPI structs, but
there are probably reasons why that's not already done. This might be an
indication that there are no big-endian ACPI platforms, so you don't
need the endian conversions?
> + pcc_header = skb_push(skb, sizeof(*pcc_header));
> + pcc_header->signature = cpu_to_le32(PCC_SIGNATURE | mpnd->outbox.index);
> + pcc_header->flags = cpu_to_le32(PCC_CMD_COMPLETION_NOTIFY);
> + memcpy(&pcc_header->command, MCTP_SIGNATURE, MCTP_SIGNATURE_LENGTH);
> + pcc_header->length = cpu_to_le32(len + MCTP_SIGNATURE_LENGTH);
> +
> + if (mbox_send_message(mpnd->outbox.chan->mchan, skb) < 0) {
> + // Remove the header in case it gets sent again
> + skb_pull(skb, sizeof(*pcc_header));
> + netif_stop_queue(ndev);
> + return NETDEV_TX_BUSY;
> + }
> +
> + return NETDEV_TX_OK;
> +error:
> + dev_dstats_tx_dropped(ndev);
> + kfree_skb(skb);
> + return NETDEV_TX_OK;
> +}
> +
> +static void mctp_pcc_tx_prepare(struct mbox_client *cl, void *mssg)
> +{
> + struct mctp_pcc_ndev *mctp_pcc_ndev;
> + struct mctp_pcc_mailbox *outbox;
> + struct sk_buff *skb = mssg;
> +
> + mctp_pcc_ndev = container_of(cl, struct mctp_pcc_ndev, outbox.client);
> + outbox = &mctp_pcc_ndev->outbox;
> +
> + /* The PCC Mailbox typically does not make use of the mssg pointer
> + * The mctp-over pcc driver is the only client that uses it.
> + * This value should always be non-null; it is possible
> + * that a change in the Mailbox level will break that assumption.
> + */
> + if (!skb) {
> + WARN_ONCE(!skb, "%s called with null message.\n", __func__);
> + return;
> + }
I'd suggest netdev_warn_once(), so we know which device is causing this.
> +
> + if (skb->len > outbox->chan->shmem_size) {
> + dev_dstats_tx_dropped(mctp_pcc_ndev->ndev);
> + return;
> + }
> + memcpy_toio(outbox->chan->shmem, skb->data, skb->len);
Super minor: double space before skb->data there.
> + dev_dstats_tx_add(mctp_pcc_ndev->ndev, skb->len);
> +}
> +
> +static void mctp_pcc_tx_done(struct mbox_client *c, void *mssg, int r)
> +{
> + struct mctp_pcc_ndev *mctp_pcc_ndev;
> + struct sk_buff *skb = mssg;
> +
> + /*
> + * If there is a packet in flight during driver cleanup
> + * It may have been freed already.
> + */
> + if (!mssg)
> + return;
> + /*
> + * If the return code is non-zero, we should not report the packet
> + * as transmitted. However, we are in IRQ context right now, and we
> + * cannot safely write transmission statistics.
> + */
This reads as if you're not updating stats at all, but you do so in
mctp_pcc_tx_prepare(). I don't think this comment is necessary - if
you really want to mention this, add a comment on the
dev_dstats_tx_add() to indicate why you're calling it early.
> + mctp_pcc_ndev = container_of(c, struct mctp_pcc_ndev, outbox.client);
> + dev_consume_skb_any(skb);
> + netif_wake_queue(mctp_pcc_ndev->ndev);
> +}
> +
> +static int mctp_pcc_open(struct net_device *ndev)
> +{
> + struct mctp_pcc_ndev *mctp_pcc_ndev = netdev_priv(ndev);
> + struct mctp_pcc_mailbox *outbox, *inbox;
> +
> + outbox = &mctp_pcc_ndev->outbox;
> + inbox = &mctp_pcc_ndev->inbox;
> +
> + outbox->chan = pcc_mbox_request_channel(&outbox->client, outbox->index);
> + if (IS_ERR(outbox->chan))
> + return PTR_ERR(outbox->chan);
> +
> + if (outbox->chan->shmem_size < MCTP_PCC_MIN_SIZE) {
Minor: odd spacing here.
> + pcc_mbox_free_channel(outbox->chan);
> + return -EINVAL;
> + }
> +
> + inbox->client.rx_callback = mctp_pcc_client_rx_callback;
> + inbox->chan = pcc_mbox_request_channel(&inbox->client, inbox->index);
> + if (IS_ERR(inbox->chan)) {
> + pcc_mbox_free_channel(outbox->chan);
> + return PTR_ERR(inbox->chan);
> + }
> + if (inbox->chan->shmem_size < MCTP_PCC_MIN_SIZE) {
> + pcc_mbox_free_channel(outbox->chan);
> + pcc_mbox_free_channel(inbox->chan);
> + return -EINVAL;
> + }
> + return 0;
> +}
> +
> +static int mctp_pcc_stop(struct net_device *ndev)
> +{
> + struct mctp_pcc_ndev *mctp_pcc_ndev;
> + unsigned int count, idx;
> + struct mbox_chan *chan;
> + struct sk_buff *skb;
> +
> + mctp_pcc_ndev = netdev_priv(ndev);
> + chan = mctp_pcc_ndev->outbox.chan->mchan;
> + pcc_mbox_free_channel(mctp_pcc_ndev->inbox.chan);
> + scoped_guard(spinlock_irqsave, &chan->lock) {
> + skb = chan->active_req;
> + chan->active_req = NULL;
> + if (skb) {
> + dev_dstats_tx_dropped(ndev);
> + dev_consume_skb_any(skb);
> + }
> + while (chan->msg_count > 0) {
> + count = chan->msg_count;
> + idx = chan->msg_free;
> + if (idx >= count)
> + idx -= count;
> + else
> + idx += MBOX_TX_QUEUE_LEN - count;
> + skb = chan->msg_data[idx];
> + dev_dstats_tx_dropped(ndev);
> + dev_consume_skb_any(skb);
> + chan->msg_count--;
> + }
> + }
I'm going to assume this is all OK with respect to PCC channel activity.
> + pcc_mbox_free_channel(mctp_pcc_ndev->outbox.chan);
> + return 0;
> +}
> +
> +static int mctp_pcc_change_mtu(struct net_device *dev, int new_mtu)
> +{
> + if (new_mtu > dev->max_mtu)
> + return -EINVAL;
> + if (new_mtu < MCTP_MIN_MTU)
> + return -EINVAL;
> + return 0;
> +}
The core already does these checks, I don't think you need a
ndo_change_mtu callback at all.
Cheers,
Jeremy
^ permalink raw reply
* [net-next PATCH v3 8/8] net: dsa: realtek: rtl8365mb: add bridge port flags
From: Luiz Angelo Daros de Luca @ 2026-05-07 2:58 UTC (permalink / raw)
To: Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Linus Walleij,
Alvin Šipraga, Yury Norov, Rasmus Villemoes, Russell King
Cc: netdev, linux-kernel, Luiz Angelo Daros de Luca
In-Reply-To: <20260506-realtek_forward-v3-0-1d87c5f85a3b@gmail.com>
From: Alvin Šipraga <alsi@bang-olufsen.dk>
Implement support for bridge port flags to control learning and flooding
behavior. This patch maps hardware functionalities to the following
bridge flags:
- BR_LEARNING
- BR_FLOOD
- BR_MCAST_FLOOD
- BR_BCAST_FLOOD
By default, all flooding types are enabled during port setup to ensure
standard bridge behavior.
Co-developed-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
drivers/net/dsa/realtek/realtek.h | 8 +++
drivers/net/dsa/realtek/rtl8365mb_main.c | 69 +++++++++++++++++++++
drivers/net/dsa/realtek/rtl83xx.c | 100 +++++++++++++++++++++++++++++++
drivers/net/dsa/realtek/rtl83xx.h | 4 ++
4 files changed, 181 insertions(+)
diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/realtek.h
index ef2d3ddfef60..e78113f050dc 100644
--- a/drivers/net/dsa/realtek/realtek.h
+++ b/drivers/net/dsa/realtek/realtek.h
@@ -140,6 +140,14 @@ struct realtek_ops {
int (*l2_del_mc)(struct realtek_priv *priv, int port,
const unsigned char addr[ETH_ALEN], u16 vid);
int (*l2_flush)(struct realtek_priv *priv, int port, u16 vid);
+ int (*port_set_learning)(struct realtek_priv *priv, int port,
+ bool enable);
+ int (*port_set_ucast_flood)(struct realtek_priv *priv, int port,
+ bool enable);
+ int (*port_set_mcast_flood)(struct realtek_priv *priv, int port,
+ bool enable);
+ int (*port_set_bcast_flood)(struct realtek_priv *priv, int port,
+ bool enable);
int (*phy_read)(struct realtek_priv *priv, int phy, int regnum);
int (*phy_write)(struct realtek_priv *priv, int phy, int regnum,
u16 val);
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index 1b8034311b17..7c296f6a0a05 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -304,6 +304,21 @@
#define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \
(0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport)))
+/* Unknown unicast DA flooding port mask */
+#define RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_REG 0x0890
+#define RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_MASK 0x07FF
+
+/* Unknown multicast DA flooding port mask */
+#define RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_REG 0x0891
+#define RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_MASK 0x07FF
+
+/* Broadcast flooding port mask */
+#define RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_REG 0x0892
+#define RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_MASK 0x07FF
+
+#define RTL8365MB_SUPPORTED_BRIDGE_FLAGS \
+ (BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD)
+
/* Miscellaneous port configuration register, incl. VLAN egress mode */
#define RTL8365MB_PORT_MISC_CFG_REG_BASE 0x000E
#define RTL8365MB_PORT_MISC_CFG_REG(_p) \
@@ -1450,6 +1465,49 @@ static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port,
enable ? RTL8365MB_LEARN_LIMIT_MAX : 0);
}
+static int rtl8365mb_port_set_ucast_flood(struct realtek_priv *priv, int port,
+ bool enable)
+{
+ /* Frames with unknown unicast DA will be flooded to a programmable
+ * port mask that by default includes all ports. Add or remove
+ * the specified port from this port mask accordingly.
+ */
+ return regmap_update_bits(priv->map,
+ RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_REG,
+ BIT(port), enable ? BIT(port) : 0);
+}
+
+static int rtl8365mb_port_set_mcast_flood(struct realtek_priv *priv, int port,
+ bool enable)
+{
+ return regmap_update_bits(priv->map,
+ RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_REG,
+ BIT(port), enable ? BIT(port) : 0);
+}
+
+static int rtl8365mb_port_set_bcast_flood(struct realtek_priv *priv, int port,
+ bool enable)
+{
+ return regmap_update_bits(priv->map,
+ RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_REG,
+ BIT(port), enable ? BIT(port) : 0);
+}
+
+static int rtl8365mb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ struct realtek_priv *priv = ds->priv;
+
+ dev_dbg(priv->dev, "pre_bridge_flags port:%d flags:%lx supported:%lx",
+ port, flags.mask, RTL8365MB_SUPPORTED_BRIDGE_FLAGS);
+
+ if (flags.mask & ~RTL8365MB_SUPPORTED_BRIDGE_FLAGS)
+ return -EINVAL;
+
+ return 0;
+}
+
static int rtl8365mb_port_set_efid(struct realtek_priv *priv, int port,
u32 efid)
{
@@ -2280,6 +2338,11 @@ static int rtl8365mb_setup(struct dsa_switch *ds)
if (ret)
goto out_teardown_irq;
+ /* Enable all types of flooding */
+ ret = rtl83xx_setup_port_flood_control(priv, dp->index);
+ if (ret)
+ goto out_teardown_irq;
+
/* Set up per-port private data */
p->priv = priv;
p->index = dp->index;
@@ -2447,6 +2510,8 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops = {
.phylink_get_caps = rtl8365mb_phylink_get_caps,
.port_bridge_join = rtl83xx_port_bridge_join,
.port_bridge_leave = rtl83xx_port_bridge_leave,
+ .port_pre_bridge_flags = rtl8365mb_port_pre_bridge_flags,
+ .port_bridge_flags = rtl83xx_port_bridge_flags,
.port_stp_state_set = rtl8365mb_port_stp_state_set,
.port_fast_age = rtl83xx_port_fast_age,
.port_fdb_add = rtl83xx_port_fdb_add,
@@ -2481,6 +2546,10 @@ static const struct realtek_ops rtl8365mb_ops = {
.l2_add_mc = rtl8365mb_l2_add_mc,
.l2_del_mc = rtl8365mb_l2_del_mc,
.l2_flush = rtl8365mb_l2_flush,
+ .port_set_learning = rtl8365mb_port_set_learning,
+ .port_set_ucast_flood = rtl8365mb_port_set_ucast_flood,
+ .port_set_mcast_flood = rtl8365mb_port_set_mcast_flood,
+ .port_set_bcast_flood = rtl8365mb_port_set_bcast_flood,
.phy_read = rtl8365mb_phy_read,
.phy_write = rtl8365mb_phy_write,
};
diff --git a/drivers/net/dsa/realtek/rtl83xx.c b/drivers/net/dsa/realtek/rtl83xx.c
index 36158209a192..fc01eb262fcf 100644
--- a/drivers/net/dsa/realtek/rtl83xx.c
+++ b/drivers/net/dsa/realtek/rtl83xx.c
@@ -3,6 +3,7 @@
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/of_mdio.h>
+#include <linux/if_bridge.h>
#include "realtek.h"
#include "rtl83xx.h"
@@ -707,6 +708,105 @@ int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
}
EXPORT_SYMBOL_NS_GPL(rtl83xx_port_mdb_del, "REALTEK_DSA");
+/**
+ * rtl83xx_port_bridge_flags() - set port bridge flags
+ * @ds: DSA switch instance
+ * @port: port index
+ * @flags: bridge port flags
+ * @extack: netlink extended ack for reporting errors
+ *
+ * This function handles setting bridge port flags like learning and flooding.
+ *
+ * Context: Can sleep.
+ * Return: 0 on success, negative value for failure.
+ */
+int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ struct realtek_priv *priv = ds->priv;
+ int ret;
+
+ if (flags.mask & BR_LEARNING) {
+ if (!priv->ops->port_set_learning)
+ return -EOPNOTSUPP;
+
+ ret = priv->ops->port_set_learning(priv, port,
+ !!(flags.val & BR_LEARNING));
+ if (ret)
+ return ret;
+ }
+
+ if (flags.mask & BR_FLOOD) {
+ if (!priv->ops->port_set_ucast_flood)
+ return -EOPNOTSUPP;
+
+ ret = priv->ops->port_set_ucast_flood(priv, port,
+ !!(flags.val & BR_FLOOD));
+ if (ret)
+ return ret;
+ }
+
+ if (flags.mask & BR_MCAST_FLOOD) {
+ if (!priv->ops->port_set_mcast_flood)
+ return -EOPNOTSUPP;
+
+ ret = priv->ops->port_set_mcast_flood(priv, port,
+ !!(flags.val & BR_MCAST_FLOOD));
+ if (ret)
+ return ret;
+ }
+
+ if (flags.mask & BR_BCAST_FLOOD) {
+ if (!priv->ops->port_set_bcast_flood)
+ return -EOPNOTSUPP;
+
+ ret = priv->ops->port_set_bcast_flood(priv, port,
+ !!(flags.val & BR_BCAST_FLOOD));
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(rtl83xx_port_bridge_flags, "REALTEK_DSA");
+
+/**
+ * rtl83xx_setup_port_flood_control() - setup default flood control for a port
+ * @priv: realtek_priv pointer
+ * @port: port index
+ *
+ * This function enables flooding for a given port.
+ *
+ * Context: Can sleep.
+ * Return: 0 on success, negative value for failure.
+ */
+int rtl83xx_setup_port_flood_control(struct realtek_priv *priv, int port)
+{
+ int ret;
+
+ if (priv->ops->port_set_ucast_flood) {
+ ret = priv->ops->port_set_ucast_flood(priv, port, true);
+ if (ret)
+ return ret;
+ }
+
+ if (priv->ops->port_set_mcast_flood) {
+ ret = priv->ops->port_set_mcast_flood(priv, port, true);
+ if (ret)
+ return ret;
+ }
+
+ if (priv->ops->port_set_bcast_flood) {
+ ret = priv->ops->port_set_bcast_flood(priv, port, true);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(rtl83xx_setup_port_flood_control, "REALTEK_DSA");
+
MODULE_AUTHOR("Luiz Angelo Daros de Luca <luizluca@gmail.com>");
MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
MODULE_DESCRIPTION("Realtek DSA switches common module");
diff --git a/drivers/net/dsa/realtek/rtl83xx.h b/drivers/net/dsa/realtek/rtl83xx.h
index dcb819fe567f..d86447121276 100644
--- a/drivers/net/dsa/realtek/rtl83xx.h
+++ b/drivers/net/dsa/realtek/rtl83xx.h
@@ -27,6 +27,10 @@ int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
struct netlink_ext_ack *extack);
void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
struct dsa_bridge bridge);
+int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack);
+int rtl83xx_setup_port_flood_control(struct realtek_priv *priv, int port);
void rtl83xx_port_fast_age(struct dsa_switch *ds, int port);
int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
--
2.54.0
^ permalink raw reply related
* [net-next PATCH v3 7/8] net: dsa: realtek: rtl8365mb: add FDB support
From: Luiz Angelo Daros de Luca @ 2026-05-07 2:58 UTC (permalink / raw)
To: Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Linus Walleij,
Alvin Šipraga, Yury Norov, Rasmus Villemoes, Russell King
Cc: netdev, linux-kernel, Luiz Angelo Daros de Luca
In-Reply-To: <20260506-realtek_forward-v3-0-1d87c5f85a3b@gmail.com>
From: Alvin Šipraga <alsi@bang-olufsen.dk>
Implement support for FDB and MDB management for the RTL8365MB series
switches.
The hardware supports IVL by keying the forwarding database with the
{VID, MAC, EFID} tuple. The Extended Filtering ID (EFID) is 3 bits
wide, providing 8 unique filtering domains. This driver reserves EFID 0
for standalone ports, effectively limiting the hardware offload to a
maximum of 7 bridges.
Introduce a mutex lock (l2_lock) to protect concurrent L2 table updates.
Add support for forwarding database operations, including unicast and
multicast entry handling as well as fast aging support.
Co-developed-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
drivers/net/dsa/realtek/Makefile | 1 +
drivers/net/dsa/realtek/realtek.h | 29 ++
drivers/net/dsa/realtek/rtl8365mb_l2.c | 493 +++++++++++++++++++++++++++++++
drivers/net/dsa/realtek/rtl8365mb_l2.h | 32 ++
drivers/net/dsa/realtek/rtl8365mb_main.c | 21 +-
drivers/net/dsa/realtek/rtl83xx.c | 268 +++++++++++++++++
drivers/net/dsa/realtek/rtl83xx.h | 16 +
7 files changed, 859 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Makefile
index b7fc4e852fd8..6c329e046d0b 100644
--- a/drivers/net/dsa/realtek/Makefile
+++ b/drivers/net/dsa/realtek/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8365mb.o
rtl8365mb-objs := rtl8365mb_main.o \
rtl8365mb_table.o \
rtl8365mb_vlan.o \
+ rtl8365mb_l2.o \
diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/realtek.h
index 0942f534834d..ef2d3ddfef60 100644
--- a/drivers/net/dsa/realtek/realtek.h
+++ b/drivers/net/dsa/realtek/realtek.h
@@ -45,6 +45,12 @@ struct rtl8366_vlan_4k {
u8 fid;
};
+struct realtek_fdb_entry {
+ u8 mac_addr[ETH_ALEN];
+ u16 vid;
+ bool is_static;
+};
+
struct realtek_priv {
struct device *dev;
struct reset_control *reset_ctl;
@@ -54,6 +60,15 @@ struct realtek_priv {
struct regmap *map;
struct regmap *map_nolock;
struct mutex map_lock;
+ /* l2_lock is used to prevent concurrent modifications of L2 table
+ * entries while another function is reading it. l2_(add,del)_mc
+ * is an example that first read current table entry and then
+ * create/update it. l2_(add|del)_uc uses a single table op and,
+ * internally, it might not need this lock. However, altering FDB
+ * may still collide, as well as l2_flush, with fdb_dump iterating
+ * over FDB.
+ */
+ struct mutex l2_lock;
struct mii_bus *user_mii_bus;
struct mii_bus *bus;
int mdio_addr;
@@ -112,6 +127,19 @@ struct realtek_ops {
int (*port_remove_isolation)(struct realtek_priv *priv, int port,
u32 mask);
int (*port_set_efid)(struct realtek_priv *priv, int port, u32 efid);
+ int (*l2_add_uc)(struct realtek_priv *priv, int port,
+ const unsigned char addr[ETH_ALEN],
+ u16 efid, u16 vid);
+ int (*l2_del_uc)(struct realtek_priv *priv, int port,
+ const unsigned char addr[ETH_ALEN],
+ u16 efid, u16 vid);
+ int (*l2_get_next_uc)(struct realtek_priv *priv, u16 *addr, int port,
+ struct realtek_fdb_entry *entry);
+ int (*l2_add_mc)(struct realtek_priv *priv, int port,
+ const unsigned char addr[ETH_ALEN], u16 vid);
+ int (*l2_del_mc)(struct realtek_priv *priv, int port,
+ const unsigned char addr[ETH_ALEN], u16 vid);
+ int (*l2_flush)(struct realtek_priv *priv, int port, u16 vid);
int (*phy_read)(struct realtek_priv *priv, int phy, int regnum);
int (*phy_write)(struct realtek_priv *priv, int phy, int regnum,
u16 val);
@@ -124,6 +152,7 @@ struct realtek_variant {
unsigned int clk_delay;
u8 cmd_read;
u8 cmd_write;
+ u16 l2_table_size;
size_t chip_data_sz;
};
diff --git a/drivers/net/dsa/realtek/rtl8365mb_l2.c b/drivers/net/dsa/realtek/rtl8365mb_l2.c
new file mode 100644
index 000000000000..400e21dd4d03
--- /dev/null
+++ b/drivers/net/dsa/realtek/rtl8365mb_l2.c
@@ -0,0 +1,493 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Forwarding and multicast database interface for the rtl8365mb switch family
+ *
+ * Copyright (C) 2022 Alvin Šipraga <alsi@bang-olufsen.dk>
+ */
+
+#include <linux/etherdevice.h>
+
+#include "rtl8365mb_l2.h"
+#include "rtl8365mb_table.h"
+#include <linux/regmap.h>
+
+#define RTL8365MB_L2_ENTRY_SIZE 6
+
+#define RTL8365MB_L2_UC_D0_MAC5_MASK GENMASK(7, 0)
+#define RTL8365MB_L2_UC_D0_MAC4_MASK GENMASK(15, 8)
+#define RTL8365MB_L2_UC_D1_MAC3_MASK GENMASK(7, 0)
+#define RTL8365MB_L2_UC_D1_MAC2_MASK GENMASK(15, 8)
+#define RTL8365MB_L2_UC_D2_MAC1_MASK GENMASK(7, 0)
+#define RTL8365MB_L2_UC_D2_MAC0_MASK GENMASK(15, 8)
+#define RTL8365MB_L2_UC_D3_VID_MASK GENMASK(11, 0)
+#define RTL8365MB_L2_UC_D3_IVL_MASK GENMASK(13, 13)
+#define RTL8365MB_L2_UC_D3_PORT_EXT_MASK GENMASK(15, 15)
+#define RTL8365MB_L2_UC_D4_EFID_MASK GENMASK(2, 0)
+#define RTL8365MB_L2_UC_D4_FID_MASK GENMASK(6, 3)
+#define RTL8365MB_L2_UC_D4_SA_PRI_MASK GENMASK(7, 7)
+#define RTL8365MB_L2_UC_D4_PORT_MASK GENMASK(10, 8)
+#define RTL8365MB_L2_UC_D4_AGE_MASK GENMASK(13, 11)
+#define RTL8365MB_L2_UC_D4_AUTH_MASK GENMASK(14, 14)
+#define RTL8365MB_L2_UC_D4_SA_BLOCK_MASK GENMASK(15, 15)
+#define RTL8365MB_L2_UC_D5_DA_BLOCK_MASK GENMASK(0, 0)
+#define RTL8365MB_L2_UC_D5_PRIORITY_MASK GENMASK(3, 1)
+#define RTL8365MB_L2_UC_D5_FWD_PRI_MASK GENMASK(4, 4)
+#define RTL8365MB_L2_UC_D5_STATIC_MASK GENMASK(5, 5)
+
+#define RTL8365MB_L2_MC_MAC5_MASK GENMASK(7, 0) /* D0 */
+#define RTL8365MB_L2_MC_MAC4_MASK GENMASK(15, 8) /* D0 */
+#define RTL8365MB_L2_MC_MAC3_MASK GENMASK(7, 0) /* D1 */
+#define RTL8365MB_L2_MC_MAC2_MASK GENMASK(15, 8) /* D1 */
+#define RTL8365MB_L2_MC_MAC1_MASK GENMASK(7, 0) /* D2 */
+#define RTL8365MB_L2_MC_MAC0_MASK GENMASK(15, 8) /* D2 */
+#define RTL8365MB_L2_MC_VID_MASK GENMASK(11, 0) /* D3 */
+#define RTL8365MB_L2_MC_IVL_MASK GENMASK(13, 13) /* D3 */
+#define RTL8365MB_L2_MC_MBR_EXT1_MASK GENMASK(15, 14) /* D3 */
+
+#define RTL8365MB_L2_MC_MBR_MASK GENMASK(7, 0) /* D4 */
+#define RTL8365MB_L2_MC_IGMPIDX_MASK GENMASK(15, 8) /* D4 */
+
+#define RTL8365MB_L2_MC_IGMP_ASIC_MASK GENMASK(0, 0) /* D5 */
+#define RTL8365MB_L2_MC_PRIORITY_MASK GENMASK(3, 1) /* D5 */
+#define RTL8365MB_L2_MC_FWD_PRI_MASK GENMASK(4, 4) /* D5 */
+#define RTL8365MB_L2_MC_STATIC_MASK GENMASK(5, 5) /* D5 */
+#define RTL8365MB_L2_MC_MBR_EXT2_MASK GENMASK(7, 7) /* D5 */
+
+/* Port flush command registers - writing a 1 to the port's MASK bit will
+ * initiate the flush procedure. Completion is signalled when the corresponding
+ * BUSY bit is 0.
+ */
+#define RTL8365MB_L2_FLUSH_PORT_REG 0x0A36
+#define RTL8365MB_L2_FLUSH_PORT_MASK_MASK GENMASK(7, 0)
+#define RTL8365MB_L2_FLUSH_PORT_BUSY_MASK GENMASK(15, 8)
+
+#define RTL8365MB_L2_FLUSH_PORT_EXT_REG 0x0A35
+#define RTL8365MB_L2_FLUSH_PORT_EXT_MASK_MASK GENMASK(2, 0)
+#define RTL8365MB_L2_FLUSH_PORT_EXT_BUSY_MASK GENMASK(5, 3)
+
+#define RTL8365MB_L2_FLUSH_CTRL1_REG 0x0A37
+#define RTL8365MB_L2_FLUSH_CTRL1_VID_MASK GENMASK(11, 0)
+#define RTL8365MB_L2_FLUSH_CTRL1_FID_MASK GENMASK(15, 12)
+
+#define RTL8365MB_L2_FLUSH_CTRL2_REG 0x0A38
+#define RTL8365MB_L2_FLUSH_CTRL2_MODE_MASK GENMASK(1, 0)
+#define RTL8365MB_L2_FLUSH_CTRL2_MODE_PORT 0
+#define RTL8365MB_L2_FLUSH_CTRL2_MODE_PORT_VID 1
+#define RTL8365MB_L2_FLUSH_CTRL2_MODE_PORT_FID 2
+#define RTL8365MB_L2_FLUSH_CTRL2_TYPE_MASK GENMASK(2, 2)
+#define RTL8365MB_L2_FLUSH_CTRL2_TYPE_DYNAMIC 0
+#define RTL8365MB_L2_FLUSH_CTRL2_TYPE_BOTH 0
+
+/* This flushes the entire LUT, reading it back it will turn 0 when the
+ * operation is complete
+ */
+#define RTL8365MB_L2_FLUSH_CTRL3_REG 0x0A39
+#define RTL8365MB_L2_FLUSH_CTRL3_MASK GENMASK(0, 0)
+
+struct rtl8365mb_l2_uc_key {
+ u8 mac_addr[ETH_ALEN];
+ union {
+ u16 vid; /* IVL */
+ u16 fid; /* SVL */
+ };
+ bool ivl;
+ u16 efid;
+};
+
+struct rtl8365mb_l2_uc {
+ struct rtl8365mb_l2_uc_key key;
+ u8 port;
+ u8 age;
+ u8 priority;
+
+ bool sa_block;
+ bool da_block;
+ bool auth;
+ bool is_static;
+ bool sa_pri;
+ bool fwd_pri;
+};
+
+struct rtl8365mb_l2_mc_key {
+ u8 mac_addr[ETH_ALEN];
+ union {
+ u16 vid; /* IVL */
+ u16 fid; /* SVL */
+ };
+ bool ivl;
+};
+
+struct rtl8365mb_l2_mc {
+ struct rtl8365mb_l2_mc_key key;
+ u16 member;
+ u8 priority;
+ u8 igmpidx;
+
+ bool is_static;
+ bool fwd_pri;
+ bool igmp_asic;
+};
+
+static void rtl8365mb_l2_data_to_uc(const u16 *data, struct rtl8365mb_l2_uc *uc)
+{
+ uc->key.mac_addr[5] = FIELD_GET(RTL8365MB_L2_UC_D0_MAC5_MASK, data[0]);
+ uc->key.mac_addr[4] = FIELD_GET(RTL8365MB_L2_UC_D0_MAC4_MASK, data[0]);
+ uc->key.mac_addr[3] = FIELD_GET(RTL8365MB_L2_UC_D1_MAC3_MASK, data[1]);
+ uc->key.mac_addr[2] = FIELD_GET(RTL8365MB_L2_UC_D1_MAC2_MASK, data[1]);
+ uc->key.mac_addr[1] = FIELD_GET(RTL8365MB_L2_UC_D2_MAC1_MASK, data[2]);
+ uc->key.mac_addr[0] = FIELD_GET(RTL8365MB_L2_UC_D2_MAC0_MASK, data[2]);
+ uc->key.efid = FIELD_GET(RTL8365MB_L2_UC_D4_EFID_MASK, data[4]);
+ uc->key.vid = FIELD_GET(RTL8365MB_L2_UC_D3_VID_MASK, data[3]);
+ uc->key.ivl = FIELD_GET(RTL8365MB_L2_UC_D3_IVL_MASK, data[3]);
+ uc->key.fid = FIELD_GET(RTL8365MB_L2_UC_D4_FID_MASK, data[4]);
+ uc->age = FIELD_GET(RTL8365MB_L2_UC_D4_AGE_MASK, data[4]);
+ uc->auth = FIELD_GET(RTL8365MB_L2_UC_D4_AUTH_MASK, data[4]);
+ uc->port = FIELD_GET(RTL8365MB_L2_UC_D4_PORT_MASK, data[4]) |
+ (FIELD_GET(RTL8365MB_L2_UC_D3_PORT_EXT_MASK, data[3]) << 3);
+ uc->sa_pri = FIELD_GET(RTL8365MB_L2_UC_D4_SA_PRI_MASK, data[4]);
+ uc->fwd_pri = FIELD_GET(RTL8365MB_L2_UC_D5_FWD_PRI_MASK, data[5]);
+ uc->sa_block = FIELD_GET(RTL8365MB_L2_UC_D4_SA_BLOCK_MASK, data[4]);
+ uc->da_block = FIELD_GET(RTL8365MB_L2_UC_D5_DA_BLOCK_MASK, data[5]);
+ uc->priority = FIELD_GET(RTL8365MB_L2_UC_D5_PRIORITY_MASK, data[5]);
+ uc->is_static = FIELD_GET(RTL8365MB_L2_UC_D5_STATIC_MASK, data[5]);
+}
+
+static void rtl8365mb_l2_uc_to_data(const struct rtl8365mb_l2_uc *uc, u16 *data)
+{
+ memset(data, 0, RTL8365MB_L2_ENTRY_SIZE * 2);
+ data[0] |=
+ FIELD_PREP(RTL8365MB_L2_UC_D0_MAC5_MASK, uc->key.mac_addr[5]);
+ data[0] |=
+ FIELD_PREP(RTL8365MB_L2_UC_D0_MAC4_MASK, uc->key.mac_addr[4]);
+ data[1] |=
+ FIELD_PREP(RTL8365MB_L2_UC_D1_MAC3_MASK, uc->key.mac_addr[3]);
+ data[1] |=
+ FIELD_PREP(RTL8365MB_L2_UC_D1_MAC2_MASK, uc->key.mac_addr[2]);
+ data[2] |=
+ FIELD_PREP(RTL8365MB_L2_UC_D2_MAC1_MASK, uc->key.mac_addr[1]);
+ data[2] |=
+ FIELD_PREP(RTL8365MB_L2_UC_D2_MAC0_MASK, uc->key.mac_addr[0]);
+ data[3] |= FIELD_PREP(RTL8365MB_L2_UC_D3_VID_MASK, uc->key.vid);
+ data[3] |= FIELD_PREP(RTL8365MB_L2_UC_D3_IVL_MASK, uc->key.ivl);
+ data[3] |= FIELD_PREP(RTL8365MB_L2_UC_D3_PORT_EXT_MASK, uc->port >> 3);
+ data[4] |= FIELD_PREP(RTL8365MB_L2_UC_D4_FID_MASK, uc->key.fid);
+ data[4] |= FIELD_PREP(RTL8365MB_L2_UC_D4_EFID_MASK, uc->key.efid);
+ data[4] |= FIELD_PREP(RTL8365MB_L2_UC_D4_AGE_MASK, uc->age);
+ data[4] |= FIELD_PREP(RTL8365MB_L2_UC_D4_AUTH_MASK, uc->auth);
+ data[4] |= FIELD_PREP(RTL8365MB_L2_UC_D4_PORT_MASK, uc->port);
+ data[4] |= FIELD_PREP(RTL8365MB_L2_UC_D4_SA_PRI_MASK, uc->sa_pri);
+ data[4] |= FIELD_PREP(RTL8365MB_L2_UC_D4_SA_BLOCK_MASK, uc->sa_block);
+ data[5] |= FIELD_PREP(RTL8365MB_L2_UC_D5_FWD_PRI_MASK, uc->fwd_pri);
+ data[5] |= FIELD_PREP(RTL8365MB_L2_UC_D5_DA_BLOCK_MASK, uc->da_block);
+ data[5] |= FIELD_PREP(RTL8365MB_L2_UC_D5_PRIORITY_MASK, uc->priority);
+ data[5] |= FIELD_PREP(RTL8365MB_L2_UC_D5_STATIC_MASK, uc->is_static);
+}
+
+static void rtl8365mb_l2_data_to_mc(const u16 *data, struct rtl8365mb_l2_mc *mc)
+{
+ mc->key.mac_addr[5] = FIELD_GET(RTL8365MB_L2_MC_MAC5_MASK, data[0]);
+ mc->key.mac_addr[4] = FIELD_GET(RTL8365MB_L2_MC_MAC4_MASK, data[0]);
+ mc->key.mac_addr[3] = FIELD_GET(RTL8365MB_L2_MC_MAC3_MASK, data[1]);
+ mc->key.mac_addr[2] = FIELD_GET(RTL8365MB_L2_MC_MAC2_MASK, data[1]);
+ mc->key.mac_addr[1] = FIELD_GET(RTL8365MB_L2_MC_MAC1_MASK, data[2]);
+ mc->key.mac_addr[0] = FIELD_GET(RTL8365MB_L2_MC_MAC0_MASK, data[2]);
+ mc->key.vid = FIELD_GET(RTL8365MB_L2_MC_VID_MASK, data[3]);
+ mc->key.ivl = FIELD_GET(RTL8365MB_L2_MC_IVL_MASK, data[3]);
+ mc->priority = FIELD_GET(RTL8365MB_L2_MC_PRIORITY_MASK, data[5]);
+ mc->fwd_pri = FIELD_GET(RTL8365MB_L2_MC_FWD_PRI_MASK, data[5]);
+ mc->is_static = FIELD_GET(RTL8365MB_L2_MC_STATIC_MASK, data[5]);
+ mc->member = FIELD_GET(RTL8365MB_L2_MC_MBR_MASK, data[4]) |
+ (FIELD_GET(RTL8365MB_L2_MC_MBR_EXT1_MASK, data[3]) << 8) |
+ (FIELD_GET(RTL8365MB_L2_MC_MBR_EXT2_MASK, data[5]) << 8);
+ mc->igmpidx = FIELD_GET(RTL8365MB_L2_MC_IGMPIDX_MASK, data[4]);
+ mc->igmp_asic = FIELD_GET(RTL8365MB_L2_MC_IGMP_ASIC_MASK, data[5]);
+}
+
+static void rtl8365mb_l2_mc_to_data(const struct rtl8365mb_l2_mc *mc, u16 *data)
+{
+ memset(data, 0, 12);
+ data[0] |= FIELD_PREP(RTL8365MB_L2_MC_MAC5_MASK, mc->key.mac_addr[5]);
+ data[0] |= FIELD_PREP(RTL8365MB_L2_MC_MAC4_MASK, mc->key.mac_addr[4]);
+ data[1] |= FIELD_PREP(RTL8365MB_L2_MC_MAC3_MASK, mc->key.mac_addr[3]);
+ data[1] |= FIELD_PREP(RTL8365MB_L2_MC_MAC2_MASK, mc->key.mac_addr[2]);
+ data[2] |= FIELD_PREP(RTL8365MB_L2_MC_MAC1_MASK, mc->key.mac_addr[1]);
+ data[2] |= FIELD_PREP(RTL8365MB_L2_MC_MAC0_MASK, mc->key.mac_addr[0]);
+ data[3] |= FIELD_PREP(RTL8365MB_L2_MC_VID_MASK, mc->key.vid);
+ data[3] |= FIELD_PREP(RTL8365MB_L2_MC_IVL_MASK, mc->key.ivl);
+ data[3] |= FIELD_PREP(RTL8365MB_L2_MC_MBR_EXT1_MASK, mc->member >> 8);
+ data[4] |= FIELD_PREP(RTL8365MB_L2_MC_MBR_MASK, mc->member);
+ data[4] |= FIELD_PREP(RTL8365MB_L2_MC_IGMPIDX_MASK, mc->igmpidx);
+ data[5] |= FIELD_PREP(RTL8365MB_L2_MC_IGMP_ASIC_MASK, mc->igmp_asic);
+ data[5] |= FIELD_PREP(RTL8365MB_L2_MC_PRIORITY_MASK, mc->priority);
+ data[5] |= FIELD_PREP(RTL8365MB_L2_MC_FWD_PRI_MASK, mc->fwd_pri);
+ data[5] |= FIELD_PREP(RTL8365MB_L2_MC_STATIC_MASK, mc->is_static);
+ data[5] |= FIELD_PREP(RTL8365MB_L2_MC_MBR_EXT2_MASK, mc->member >> 10);
+}
+
+/**
+ * rtl8365mb_l2_get_next_uc() - get the next Unicast L2 entry
+ * @priv: realtek_priv pointer
+ * @addr: as input, the table index to start the walk
+ * as output, the found table index
+ * @port: restrict the walk on entries related to port
+ * @entry: returned L2 Unicast table entry
+ *
+ * This function get the next unicast L2 table entry starting from @addr
+ * and checking exclusively entries related to @port. If no more entries
+ * were found, the output @addr will be lower than the input @addr and @entry
+ * will not be overwritten.
+ *
+ * Return: Returns 0 on success, a negative error on failure.
+ **/
+int rtl8365mb_l2_get_next_uc(struct realtek_priv *priv, u16 *addr, int port,
+ struct realtek_fdb_entry *entry)
+{
+ u16 data[RTL8365MB_L2_ENTRY_SIZE] = { 0 };
+ struct rtl8365mb_l2_uc uc;
+ int ret;
+
+ ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
+ RTL8365MB_TABLE_OP_READ, addr,
+ RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT,
+ port, data, RTL8365MB_L2_ENTRY_SIZE);
+ if (ret)
+ return ret;
+
+ rtl8365mb_l2_data_to_uc(data, &uc);
+
+ ether_addr_copy(entry->mac_addr, uc.key.mac_addr);
+ entry->vid = uc.key.vid;
+ entry->is_static = uc.is_static;
+
+ return 0;
+}
+
+int rtl8365mb_l2_add_uc(struct realtek_priv *priv, int port,
+ const unsigned char mac_addr[static ETH_ALEN],
+ u16 efid, u16 vid)
+{
+ u16 data[RTL8365MB_L2_ENTRY_SIZE] = { 0 };
+ struct rtl8365mb_l2_uc uc = { 0 };
+ u16 addr;
+ int ret;
+
+ memcpy(uc.key.mac_addr, mac_addr, ETH_ALEN);
+ uc.key.efid = efid;
+ uc.key.ivl = true;
+ uc.key.vid = vid;
+ uc.port = port;
+ /* do not let HW decrease age */
+ uc.is_static = true;
+ /* age greater than 0 adds/updates entries */
+ uc.age = 1;
+ rtl8365mb_l2_uc_to_data(&uc, data);
+
+ /* add the new entry or update an existing one */
+ ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
+ RTL8365MB_TABLE_OP_WRITE, &addr,
+ 0, 0,
+ data, RTL8365MB_L2_ENTRY_SIZE);
+ /* addr will hold the table index, but it is not used here */
+ if (ret == -ENOENT) {
+ /* -ENOENT means the just added entry was not found (and @addr
+ * does not hold the table index. Although any error will be
+ * treated equally by the caller, assume that the missing entry
+ * means the table is full (tested in real HW).
+ */
+ return -ENOSPC;
+ }
+ return ret;
+}
+
+int rtl8365mb_l2_del_uc(struct realtek_priv *priv, int port,
+ const unsigned char mac_addr[static ETH_ALEN],
+ u16 efid, u16 vid)
+{
+ u16 data[RTL8365MB_L2_ENTRY_SIZE] = { 0 };
+ struct rtl8365mb_l2_uc uc = { 0 };
+ u16 addr;
+ int ret;
+
+ memcpy(uc.key.mac_addr, mac_addr, ETH_ALEN);
+ uc.key.efid = efid;
+ uc.key.ivl = true;
+ uc.key.vid = vid;
+ /* age 0 deletes the entry */
+ uc.age = 0;
+ rtl8365mb_l2_uc_to_data(&uc, data);
+
+ /* it looks like the switch will always add/update the entry,
+ * even when age is 0 or uc.key did not match an existing entry,
+ * just to immediately drop it because age is zero. You can still
+ * get the added/updated address from @addr
+ */
+ ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
+ RTL8365MB_TABLE_OP_WRITE, &addr,
+ 0, 0,
+ data, RTL8365MB_L2_ENTRY_SIZE);
+ /* addr will hold the table index, but it is not used here */
+ return ret;
+}
+
+int rtl8365mb_l2_flush(struct realtek_priv *priv, int port, u16 vid)
+{
+ int mode = vid ? RTL8365MB_L2_FLUSH_CTRL2_MODE_PORT_VID :
+ RTL8365MB_L2_FLUSH_CTRL2_MODE_PORT;
+ u32 val, mask;
+ int ret;
+
+ mutex_lock(&priv->map_lock);
+
+ /* Configure flushing mode; only flush dynamic entries */
+ ret = regmap_write(priv->map_nolock, RTL8365MB_L2_FLUSH_CTRL2_REG,
+ FIELD_PREP(RTL8365MB_L2_FLUSH_CTRL2_MODE_MASK,
+ mode) |
+ FIELD_PREP(RTL8365MB_L2_FLUSH_CTRL2_TYPE_MASK,
+ RTL8365MB_L2_FLUSH_CTRL2_TYPE_DYNAMIC));
+ if (ret)
+ goto out;
+
+ ret = regmap_write(priv->map_nolock, RTL8365MB_L2_FLUSH_CTRL1_REG,
+ FIELD_PREP(RTL8365MB_L2_FLUSH_CTRL1_VID_MASK, vid));
+
+ if (ret)
+ goto out;
+ /* Now issue the flush command and wait for its completion. There are
+ * two registers for this purpose, and which one to use depends on the
+ * port number. The _EXT register is for ports 8 or higher.
+ */
+ if (port < 8) {
+ val = FIELD_PREP(RTL8365MB_L2_FLUSH_PORT_MASK_MASK,
+ BIT(port) & 0xFF);
+ ret = regmap_write(priv->map_nolock,
+ RTL8365MB_L2_FLUSH_PORT_REG, val);
+ if (ret)
+ goto out;
+
+ mask = FIELD_PREP(RTL8365MB_L2_FLUSH_PORT_BUSY_MASK,
+ BIT(port) & 0xFF);
+ ret = regmap_read_poll_timeout(priv->map_nolock,
+ RTL8365MB_L2_FLUSH_PORT_REG,
+ val, !(val & mask), 10, 100);
+ if (ret)
+ goto out;
+ } else {
+ val = FIELD_PREP(RTL8365MB_L2_FLUSH_PORT_EXT_MASK_MASK,
+ BIT(port) >> 8);
+ ret = regmap_write(priv->map_nolock,
+ RTL8365MB_L2_FLUSH_PORT_EXT_REG, val);
+ if (ret)
+ goto out;
+
+ mask = FIELD_PREP(RTL8365MB_L2_FLUSH_PORT_EXT_BUSY_MASK,
+ BIT(port) >> 8);
+ ret = regmap_read_poll_timeout(priv->map_nolock,
+ RTL8365MB_L2_FLUSH_PORT_EXT_REG,
+ val, !(val & mask), 10, 100);
+ if (ret)
+ goto out;
+ }
+
+out:
+ mutex_unlock(&priv->map_lock);
+
+ return ret;
+}
+
+int rtl8365mb_l2_add_mc(struct realtek_priv *priv, int port,
+ const unsigned char mac_addr[static ETH_ALEN],
+ u16 vid)
+{
+ u16 data[RTL8365MB_L2_ENTRY_SIZE] = { 0 };
+ struct rtl8365mb_l2_mc mc = { 0 };
+ u16 addr;
+ int ret;
+
+ memcpy(mc.key.mac_addr, mac_addr, ETH_ALEN);
+ mc.key.vid = vid;
+ mc.key.ivl = true;
+ /* Already set the port and is_static, although not used in OP_READ,
+ * data will be ready for OP_WRITE if it is a new entry.
+ */
+ mc.member |= BIT(port);
+ mc.is_static = 1;
+ rtl8365mb_l2_mc_to_data(&mc, data);
+
+ /* First look for an existing entry (to get existing port members) */
+ ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
+ RTL8365MB_TABLE_OP_READ, &addr,
+ RTL8365MB_TABLE_L2_METHOD_MAC, 0,
+ data, RTL8365MB_L2_ENTRY_SIZE);
+ if (!ret) {
+ /* There is already an entry... */
+ rtl8365mb_l2_data_to_mc(data, &mc);
+ /* the port must be added as a member */
+ mc.member |= BIT(port);
+ rtl8365mb_l2_mc_to_data(&mc, data);
+ } else if (ret == -ENOENT) {
+ /* New entry, no need to update data again as it already
+ * includes the member
+ */
+ } else {
+ return ret;
+ }
+
+ /* add the new entry or update an existing one */
+ ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
+ RTL8365MB_TABLE_OP_WRITE, &addr,
+ 0, 0,
+ data, RTL8365MB_L2_ENTRY_SIZE);
+ /* addr will hold the table index, but it is not used here */
+ if (ret == -ENOENT) {
+ /* -ENOENT means the just added entry was not found (and @addr
+ * does not hold the table index. Although any error will be
+ * treated equally by the caller, assume that the missing entry
+ * means the table is full (tested in real HW).
+ */
+ return -ENOSPC;
+ }
+
+ return ret;
+}
+
+int rtl8365mb_l2_del_mc(struct realtek_priv *priv, int port,
+ const unsigned char mac_addr[static ETH_ALEN],
+ u16 vid)
+{
+ u16 data[RTL8365MB_L2_ENTRY_SIZE] = { 0 };
+ struct rtl8365mb_l2_mc mc = { 0 };
+ u16 addr;
+ int ret;
+
+ memcpy(mc.key.mac_addr, mac_addr, ETH_ALEN);
+ mc.key.vid = vid;
+ mc.key.ivl = true;
+ rtl8365mb_l2_mc_to_data(&mc, data);
+
+ /* First look for an existing entry (to get existing port members) */
+ ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
+ RTL8365MB_TABLE_OP_READ, &addr,
+ RTL8365MB_TABLE_L2_METHOD_MAC, 0,
+ data, RTL8365MB_L2_ENTRY_SIZE);
+ if (ret)
+ /* Any error, including -ENOENT is unexpected */
+ return ret;
+
+ rtl8365mb_l2_data_to_mc(data, &mc);
+ /* the port must be removed as a member */
+ mc.member &= ~BIT(port);
+ if (!mc.member) {
+ /* With no members, zero all non-key fields to delete the
+ * entry. However is_static is everything else we wrote.
+ * (and probably all that is needed by the HW)
+ */
+ mc.is_static = 0;
+ }
+ rtl8365mb_l2_mc_to_data(&mc, data);
+
+ /* update the existing entry. */
+ ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_L2,
+ RTL8365MB_TABLE_OP_WRITE, &addr,
+ 0, 0,
+ data, RTL8365MB_L2_ENTRY_SIZE);
+ return ret;
+}
diff --git a/drivers/net/dsa/realtek/rtl8365mb_l2.h b/drivers/net/dsa/realtek/rtl8365mb_l2.h
new file mode 100644
index 000000000000..9470cf059ce5
--- /dev/null
+++ b/drivers/net/dsa/realtek/rtl8365mb_l2.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Forwarding and multicast database interface for the rtl8365mb switch family
+ *
+ * Copyright (C) 2022 Alvin Šipraga <alsi@bang-olufsen.dk>
+ */
+
+#ifndef _REALTEK_RTL8365MB_L2_H
+#define _REALTEK_RTL8365MB_L2_H
+
+#include <linux/if_ether.h>
+#include <linux/types.h>
+
+#include "realtek.h"
+
+int rtl8365mb_l2_get_next_uc(struct realtek_priv *priv, u16 *addr, int port,
+ struct realtek_fdb_entry *entry);
+int rtl8365mb_l2_add_uc(struct realtek_priv *priv, int port,
+ const unsigned char addr[static ETH_ALEN],
+ u16 efid, u16 vid);
+int rtl8365mb_l2_del_uc(struct realtek_priv *priv, int port,
+ const unsigned char addr[static ETH_ALEN],
+ u16 efid, u16 vid);
+int rtl8365mb_l2_flush(struct realtek_priv *priv, int port, u16 vid);
+
+int rtl8365mb_l2_add_mc(struct realtek_priv *priv, int port,
+ const unsigned char mac_addr[static ETH_ALEN],
+ u16 vid);
+int rtl8365mb_l2_del_mc(struct realtek_priv *priv, int port,
+ const unsigned char mac_addr[static ETH_ALEN],
+ u16 vid);
+
+#endif /* _REALTEK_RTL8365MB_L2_H */
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index 576bec52d863..1b8034311b17 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -104,6 +104,7 @@
#include "realtek-smi.h"
#include "realtek-mdio.h"
#include "rtl83xx.h"
+#include "rtl8365mb_l2.h"
#include "rtl8365mb_vlan.h"
/* Family-specific data and limits */
@@ -111,8 +112,9 @@
#define RTL8365MB_NUM_PHYREGS 32
#define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)
#define RTL8365MB_MAX_NUM_PORTS 11
-#define RTL8365MB_MAX_NUM_EXTINTS 3
+/* Valid for the whole family except RTL8370B, which has 4160 entries. */
#define RTL8365MB_LEARN_LIMIT_MAX 2112
+#define RTL8365MB_MAX_NUM_EXTINTS 3
/* Chip identification registers */
#define RTL8365MB_CHIP_ID_REG 0x1300
@@ -2229,6 +2231,8 @@ static int rtl8365mb_setup(struct dsa_switch *ds)
mb = priv->chip_data;
cpu = &mb->cpu;
+ mutex_init(&priv->l2_lock);
+
ret = rtl8365mb_reset_chip(priv);
if (ret) {
dev_err(priv->dev, "failed to reset chip: %pe\n",
@@ -2314,6 +2318,8 @@ static int rtl8365mb_setup(struct dsa_switch *ds)
if (ret)
goto out_teardown_irq;
+ ds->assisted_learning_on_cpu_port = true;
+ ds->fdb_isolation = true;
/* The EFID is 3 bits, but EFID 0 is reserved for standalone ports */
ds->max_num_bridges = FIELD_MAX(RTL8365MB_EFID_MASK);
ds->configure_vlan_while_not_filtering = true;
@@ -2442,6 +2448,12 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops = {
.port_bridge_join = rtl83xx_port_bridge_join,
.port_bridge_leave = rtl83xx_port_bridge_leave,
.port_stp_state_set = rtl8365mb_port_stp_state_set,
+ .port_fast_age = rtl83xx_port_fast_age,
+ .port_fdb_add = rtl83xx_port_fdb_add,
+ .port_fdb_del = rtl83xx_port_fdb_del,
+ .port_fdb_dump = rtl83xx_port_fdb_dump,
+ .port_mdb_add = rtl83xx_port_mdb_add,
+ .port_mdb_del = rtl83xx_port_mdb_del,
.port_vlan_add = rtl8365mb_port_vlan_add,
.port_vlan_del = rtl8365mb_port_vlan_del,
.port_vlan_filtering = rtl8365mb_port_vlan_filtering,
@@ -2463,6 +2475,12 @@ static const struct realtek_ops rtl8365mb_ops = {
.port_add_isolation = rtl8365mb_port_add_isolation,
.port_remove_isolation = rtl8365mb_port_remove_isolation,
.port_set_efid = rtl8365mb_port_set_efid,
+ .l2_add_uc = rtl8365mb_l2_add_uc,
+ .l2_del_uc = rtl8365mb_l2_del_uc,
+ .l2_get_next_uc = rtl8365mb_l2_get_next_uc,
+ .l2_add_mc = rtl8365mb_l2_add_mc,
+ .l2_del_mc = rtl8365mb_l2_del_mc,
+ .l2_flush = rtl8365mb_l2_flush,
.phy_read = rtl8365mb_phy_read,
.phy_write = rtl8365mb_phy_write,
};
@@ -2474,6 +2492,7 @@ const struct realtek_variant rtl8365mb_variant = {
.clk_delay = 10,
.cmd_read = 0xb9,
.cmd_write = 0xb8,
+ .l2_table_size = RTL8365MB_LEARN_LIMIT_MAX,
.chip_data_sz = sizeof(struct rtl8365mb),
};
diff --git a/drivers/net/dsa/realtek/rtl83xx.c b/drivers/net/dsa/realtek/rtl83xx.c
index 3ab91cd82743..36158209a192 100644
--- a/drivers/net/dsa/realtek/rtl83xx.c
+++ b/drivers/net/dsa/realtek/rtl83xx.c
@@ -439,6 +439,274 @@ void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
}
EXPORT_SYMBOL_NS_GPL(rtl83xx_port_bridge_leave, "REALTEK_DSA");
+/**
+ * rtl83xx_port_fast_age() - flush dynamic FDB entries learned on a port
+ * @ds: DSA switch instance
+ * @port: port index
+ *
+ * This function requests the switch to age out dynamic FDB entries learned on
+ * @port.
+ *
+ * Context: Can sleep.
+ * Return: Nothing.
+ */
+void rtl83xx_port_fast_age(struct dsa_switch *ds, int port)
+{
+ struct realtek_priv *priv = ds->priv;
+ int ret;
+
+ if (!priv->ops->l2_flush) {
+ dev_warn_once(priv->dev, "l2_flush op not defined\n");
+ return;
+ }
+
+ dev_dbg(priv->dev, "fast_age port %d\n", port);
+
+ mutex_lock(&priv->l2_lock);
+ ret = priv->ops->l2_flush(priv, port, 0);
+ mutex_unlock(&priv->l2_lock);
+ if (ret)
+ dev_err(priv->dev, "failed to fast age on port %d: %d\n", port,
+ ret);
+}
+EXPORT_SYMBOL_NS_GPL(rtl83xx_port_fast_age, "REALTEK_DSA");
+
+/**
+ * rtl83xx_port_fdb_add() - add a static FDB entry to a port database
+ * @ds: DSA switch instance
+ * @port: port index
+ * @addr: MAC address to add
+ * @vid: VLAN ID associated with @addr
+ * @db: database where the entry should be added
+ *
+ * This function adds a static unicast FDB entry to the standalone port
+ * database or to a bridge database.
+ *
+ * Context: Can sleep.
+ * Return: 0 on success, negative value for failure.
+ */
+int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct realtek_priv *priv = ds->priv;
+ int efid;
+ int ret;
+
+ if (!priv->ops->l2_add_uc)
+ return -EOPNOTSUPP;
+
+ if (db.type != DSA_DB_PORT && db.type != DSA_DB_BRIDGE)
+ return -EOPNOTSUPP;
+
+ /*
+ * DSA_DB_BRIDGE ports use bridge number [1..N] as EFID, while
+ * DSA_DB_PORT use the default EFID (0), not used by any bridge.
+ */
+ efid = db.type == DSA_DB_BRIDGE ? db.bridge.num : 0;
+
+ dev_dbg(priv->dev, "fdb_add port %d addr %pM efid %d vid %d\n",
+ port, addr, efid, vid);
+
+ mutex_lock(&priv->l2_lock);
+ ret = priv->ops->l2_add_uc(priv, port, addr, efid, vid);
+ mutex_unlock(&priv->l2_lock);
+
+ if (ret)
+ dev_err(priv->dev, "fdb_add ERROR %pe\n", ERR_PTR(ret));
+ return ret;
+}
+EXPORT_SYMBOL_NS_GPL(rtl83xx_port_fdb_add, "REALTEK_DSA");
+
+/**
+ * rtl83xx_port_fdb_del() - delete a static FDB entry from a port database
+ * @ds: DSA switch instance
+ * @port: port index
+ * @addr: MAC address to delete
+ * @vid: VLAN ID associated with @addr
+ * @db: database where the entry should be removed
+ *
+ * This function deletes a static unicast FDB entry from the standalone port
+ * database or from a bridge database.
+ *
+ * Context: Can sleep.
+ * Return: 0 on success, negative value for failure.
+ */
+int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct realtek_priv *priv = ds->priv;
+ int efid;
+ int ret;
+
+ if (!priv->ops->l2_del_uc)
+ return -EOPNOTSUPP;
+
+ if (db.type != DSA_DB_PORT && db.type != DSA_DB_BRIDGE)
+ return -EOPNOTSUPP;
+
+ /*
+ * DSA_DB_BRIDGE ports use bridge number [1..N] as EFID, while
+ * DSA_DB_PORT use the default EFID (0), not used by any bridge.
+ */
+ efid = db.type == DSA_DB_BRIDGE ? db.bridge.num : 0;
+
+ dev_dbg(priv->dev, "fdb_del port %d addr %pM efid %d vid %d\n",
+ port, addr, efid, vid);
+
+ mutex_lock(&priv->l2_lock);
+ ret = priv->ops->l2_del_uc(priv, port, addr, efid, vid);
+ mutex_unlock(&priv->l2_lock);
+
+ if (ret)
+ dev_err(priv->dev, "fdb_del ERROR %pe\n", ERR_PTR(ret));
+ return ret;
+}
+EXPORT_SYMBOL_NS_GPL(rtl83xx_port_fdb_del, "REALTEK_DSA");
+
+/**
+ * rtl83xx_port_fdb_dump() - iterate over FDB entries associated with a port
+ * @ds: DSA switch instance
+ * @port: port index
+ * @cb: callback invoked for each entry
+ * @data: opaque pointer passed to @cb
+ *
+ * This function walks the unicast FDB entries associated with @port and calls
+ * @cb for each matching entry.
+ *
+ * Context: Can sleep.
+ * Return: 0 on success, -ENOENT when the table walk reaches the end, or
+ * another negative value for failure.
+ */
+int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
+ dsa_fdb_dump_cb_t *cb, void *data)
+{
+ struct realtek_priv *priv = ds->priv;
+ struct realtek_fdb_entry entry;
+ u16 l2_table_size = priv->variant->l2_table_size;
+ u16 start_addr, addr = 0;
+ int ret = 0;
+
+ if (!priv->ops->l2_get_next_uc)
+ return -EOPNOTSUPP;
+ if (!l2_table_size) {
+ dev_warn_once(priv->dev, "l2_table_size not defined\n");
+ return -EOPNOTSUPP;
+ }
+
+ mutex_lock(&priv->l2_lock);
+ while (true) {
+ start_addr = addr;
+
+ dev_dbg(priv->dev, "l2_get_next_uc, addr:%d, port:%d\n",
+ addr, port);
+ ret = priv->ops->l2_get_next_uc(priv, &addr, port, &entry);
+ dev_dbg(priv->dev,
+ "l2_get_next_uc addr:%d mac:%pM vid:%d static:%d ret:%pe\n",
+ addr, entry.mac_addr, entry.vid, entry.is_static,
+ ERR_PTR(ret));
+
+ if (ret == -ENOENT)
+ break;
+ if (ret)
+ break;
+
+ if (addr < start_addr)
+ break;
+
+ cb(entry.mac_addr, entry.vid, entry.is_static, data);
+
+ addr++;
+
+ /* Avoid querying beyond the valid L2 table range. */
+ if (addr > l2_table_size)
+ break;
+ }
+ mutex_unlock(&priv->l2_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_NS_GPL(rtl83xx_port_fdb_dump, "REALTEK_DSA");
+
+/**
+ * rtl83xx_port_mdb_add() - add a multicast database entry to a port database
+ * @ds: DSA switch instance
+ * @port: port index
+ * @mdb: multicast database entry to add
+ * @db: database where the entry should be added
+ *
+ * This function adds a multicast database entry to the standalone port
+ * database or to a bridge database.
+ *
+ * Context: Can sleep.
+ * Return: 0 on success, negative value for failure.
+ */
+int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ struct realtek_priv *priv = ds->priv;
+ int ret;
+
+ if (!priv->ops->l2_add_mc)
+ return -EOPNOTSUPP;
+
+ if (db.type != DSA_DB_PORT && db.type != DSA_DB_BRIDGE)
+ return -EOPNOTSUPP;
+
+ dev_dbg(priv->dev, "mdb_add port %d addr %pM vid %d\n",
+ port, mdb->addr, mdb->vid);
+
+ mutex_lock(&priv->l2_lock);
+ ret = priv->ops->l2_add_mc(priv, port, mdb->addr, mdb->vid);
+ mutex_unlock(&priv->l2_lock);
+
+ if (ret)
+ dev_err(priv->dev, "mdb_add ERROR %pe\n", ERR_PTR(ret));
+ return ret;
+}
+EXPORT_SYMBOL_NS_GPL(rtl83xx_port_mdb_add, "REALTEK_DSA");
+
+/**
+ * rtl83xx_port_mdb_del() - delete a multicast database entry from a port database
+ * @ds: DSA switch instance
+ * @port: port index
+ * @mdb: multicast database entry to delete
+ * @db: database where the entry should be removed
+ *
+ * This function deletes a multicast database entry from the standalone port
+ * database or from a bridge database.
+ *
+ * Context: Can sleep.
+ * Return: 0 on success, negative value for failure.
+ */
+int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ struct realtek_priv *priv = ds->priv;
+ int ret;
+
+ if (!priv->ops->l2_del_mc)
+ return -EOPNOTSUPP;
+
+ if (db.type != DSA_DB_PORT && db.type != DSA_DB_BRIDGE)
+ return -EOPNOTSUPP;
+
+ dev_dbg(priv->dev, "mdb_del port %d addr %pM vid %d\n",
+ port, mdb->addr, mdb->vid);
+
+ mutex_lock(&priv->l2_lock);
+ ret = priv->ops->l2_del_mc(priv, port, mdb->addr, mdb->vid);
+ mutex_unlock(&priv->l2_lock);
+
+ if (ret)
+ dev_err(priv->dev, "mdb_del ERROR %pe\n", ERR_PTR(ret));
+ return ret;
+}
+EXPORT_SYMBOL_NS_GPL(rtl83xx_port_mdb_del, "REALTEK_DSA");
+
MODULE_AUTHOR("Luiz Angelo Daros de Luca <luizluca@gmail.com>");
MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
MODULE_DESCRIPTION("Realtek DSA switches common module");
diff --git a/drivers/net/dsa/realtek/rtl83xx.h b/drivers/net/dsa/realtek/rtl83xx.h
index 2481a1aaa226..dcb819fe567f 100644
--- a/drivers/net/dsa/realtek/rtl83xx.h
+++ b/drivers/net/dsa/realtek/rtl83xx.h
@@ -28,4 +28,20 @@ int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
struct dsa_bridge bridge);
+void rtl83xx_port_fast_age(struct dsa_switch *ds, int port);
+int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db);
+int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db);
+int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
+ dsa_fdb_dump_cb_t *cb, void *data);
+int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db);
+int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db);
+
#endif /* _RTL83XX_H */
--
2.54.0
^ permalink raw reply related
* [net-next PATCH v3 6/8] net: dsa: realtek: rtl8365mb: add port_bridge_{join,leave}
From: Luiz Angelo Daros de Luca @ 2026-05-07 2:58 UTC (permalink / raw)
To: Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Linus Walleij,
Alvin Šipraga, Yury Norov, Rasmus Villemoes, Russell King
Cc: netdev, linux-kernel, Luiz Angelo Daros de Luca
In-Reply-To: <20260506-realtek_forward-v3-0-1d87c5f85a3b@gmail.com>
From: Alvin Šipraga <alsi@bang-olufsen.dk>
Implement hardware offloading of bridge functionality. This is achieved
by using the per-port isolation registers, which contain a forwarding
port mask. The switch will refuse to forward packets ingressed on a
given port to a port which is not in its forwarding mask.
For each bridge that is offloaded, use the DSA-provided bridge number
for the Extended Filtering ID (EFID). When using Independent VLAN
Learning (IVL), the forwarding database is keyed with the tuple
{VID, MAC, EFID}. There are 8 EFIDs available (0~7), but we reserve the
default EFID 0 for standalone ports where learning is disabled. This
fits nicely because DSA indexes the bridge number starting from 1.
Because of the limited number of EFIDs, we have to set the
max_num_bridges property of our switch to 7: we can't offload more than
that or we will fail to offer IVL as at least two bridges would end up
having to share an EFID.
Co-developed-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
drivers/net/dsa/realtek/realtek.h | 5 ++
drivers/net/dsa/realtek/rtl8365mb_main.c | 57 +++++++++++++++-
drivers/net/dsa/realtek/rtl83xx.c | 114 +++++++++++++++++++++++++++++++
drivers/net/dsa/realtek/rtl83xx.h | 7 ++
4 files changed, 182 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/realtek/realtek.h b/drivers/net/dsa/realtek/realtek.h
index c03485a80d93..0942f534834d 100644
--- a/drivers/net/dsa/realtek/realtek.h
+++ b/drivers/net/dsa/realtek/realtek.h
@@ -107,6 +107,11 @@ struct realtek_ops {
int (*enable_vlan)(struct realtek_priv *priv, bool enable);
int (*enable_vlan4k)(struct realtek_priv *priv, bool enable);
int (*enable_port)(struct realtek_priv *priv, int port, bool enable);
+ int (*port_add_isolation)(struct realtek_priv *priv, int port,
+ u32 mask);
+ int (*port_remove_isolation)(struct realtek_priv *priv, int port,
+ u32 mask);
+ int (*port_set_efid)(struct realtek_priv *priv, int port, u32 efid);
int (*phy_read)(struct realtek_priv *priv, int phy, int regnum);
int (*phy_write)(struct realtek_priv *priv, int phy, int regnum,
u16 val);
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index b37aa847a9aa..576bec52d863 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -285,6 +285,15 @@
(RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport))
#define RTL8365MB_PORT_ISOLATION_MASK 0x07FF
+/* Extended filter ID registers - used to key forwarding database with IVL */
+#define RTL8365MB_EFID_MASK GENMASK(2, 0)
+#define RTL8365MB_PORT_EFID_REG_BASE 0x0A32
+#define RTL8365MB_PORT_EFID_REG(_p) \
+ (RTL8365MB_PORT_EFID_REG_BASE + ((_p) >> 2))
+#define RTL8365MB_PORT_EFID_OFFSET(_p) (((_p) & 0x3) << 2)
+#define RTL8365MB_PORT_EFID_MASK(_p) \
+ (RTL8365MB_EFID_MASK << RTL8365MB_PORT_EFID_OFFSET(_p))
+
/* MSTP port state registers - indexed by tree instance */
#define RTL8365MB_MSTI_CTRL_BASE 0x0A00
#define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \
@@ -1439,10 +1448,44 @@ static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port,
enable ? RTL8365MB_LEARN_LIMIT_MAX : 0);
}
+static int rtl8365mb_port_set_efid(struct realtek_priv *priv, int port,
+ u32 efid)
+{
+ return regmap_update_bits(priv->map, RTL8365MB_PORT_EFID_REG(port),
+ RTL8365MB_PORT_EFID_MASK(port),
+ efid << RTL8365MB_PORT_EFID_OFFSET(port));
+}
+
+/* Port isolation manipulation functions.
+ *
+ * The port isolation register controls the forwarding mask of a given
+ * port. The switch will not forward packets ingressed on a given port
+ * to ports which are not enabled in its forwarding mask.
+ *
+ * The port forwarding mask has the highest priority in forwarding
+ * decisions. The only exception to this rule is when the switch
+ * receives a packet on its CPU port with ALLOW=0. In that case the TX
+ * field of the CPU tag will override the forwarding port mask.
+ */
static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port,
u32 mask)
{
- return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask);
+ return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port),
+ mask);
+}
+
+static int rtl8365mb_port_add_isolation(struct realtek_priv *priv, int port,
+ u32 mask)
+{
+ return regmap_update_bits(priv->map, RTL8365MB_PORT_ISOLATION_REG(port),
+ mask, mask);
+}
+
+static int rtl8365mb_port_remove_isolation(struct realtek_priv *priv, int port,
+ u32 mask)
+{
+ return regmap_update_bits(priv->map, RTL8365MB_PORT_ISOLATION_REG(port),
+ mask, 0);
}
static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port,
@@ -2223,6 +2266,11 @@ static int rtl8365mb_setup(struct dsa_switch *ds)
if (ret)
goto out_teardown_irq;
+ /* Set the default EFID 0 for standalone mode */
+ ret = rtl8365mb_port_set_efid(priv, dp->index, 0);
+ if (ret)
+ goto out_teardown_irq;
+
/* Disable learning */
ret = rtl8365mb_port_set_learning(priv, dp->index, false);
if (ret)
@@ -2266,6 +2314,8 @@ static int rtl8365mb_setup(struct dsa_switch *ds)
if (ret)
goto out_teardown_irq;
+ /* The EFID is 3 bits, but EFID 0 is reserved for standalone ports */
+ ds->max_num_bridges = FIELD_MAX(RTL8365MB_EFID_MASK);
ds->configure_vlan_while_not_filtering = true;
/* Set up VLAN */
@@ -2389,6 +2439,8 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops = {
.setup = rtl8365mb_setup,
.teardown = rtl8365mb_teardown,
.phylink_get_caps = rtl8365mb_phylink_get_caps,
+ .port_bridge_join = rtl83xx_port_bridge_join,
+ .port_bridge_leave = rtl83xx_port_bridge_leave,
.port_stp_state_set = rtl8365mb_port_stp_state_set,
.port_vlan_add = rtl8365mb_port_vlan_add,
.port_vlan_del = rtl8365mb_port_vlan_del,
@@ -2408,6 +2460,9 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops = {
static const struct realtek_ops rtl8365mb_ops = {
.detect = rtl8365mb_detect,
+ .port_add_isolation = rtl8365mb_port_add_isolation,
+ .port_remove_isolation = rtl8365mb_port_remove_isolation,
+ .port_set_efid = rtl8365mb_port_set_efid,
.phy_read = rtl8365mb_phy_read,
.phy_write = rtl8365mb_phy_write,
};
diff --git a/drivers/net/dsa/realtek/rtl83xx.c b/drivers/net/dsa/realtek/rtl83xx.c
index 2b9bd4462714..3ab91cd82743 100644
--- a/drivers/net/dsa/realtek/rtl83xx.c
+++ b/drivers/net/dsa/realtek/rtl83xx.c
@@ -325,6 +325,120 @@ void rtl83xx_reset_deassert(struct realtek_priv *priv)
gpiod_set_value(priv->reset, false);
}
+/**
+ * rtl83xx_port_bridge_join() - join a port to a bridge
+ * @ds: DSA switch instance
+ * @port: port index
+ * @bridge: bridge being joined
+ * @tx_forward_offload: if the switch can offload TX forwarding
+ * @extack: netlink extended ack for reporting errors
+ *
+ * This function handles joining a port to a bridge. It updates the port
+ * isolation masks and EFID.
+ *
+ * Context: Can sleep.
+ * Return: 0 on success, negative value for failure.
+ */
+int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge,
+ bool *tx_forward_offload,
+ struct netlink_ext_ack *extack)
+{
+ struct realtek_priv *priv = ds->priv;
+ struct dsa_port *dp;
+ u32 mask = 0;
+ int ret;
+
+ if (!priv->ops->port_add_isolation)
+ return -EOPNOTSUPP;
+
+ dev_dbg(priv->dev, "bridge %d join port %d\n", bridge.num, port);
+
+ /* Add this port to the isolation group of every other port
+ * offloading this bridge.
+ */
+ dsa_switch_for_each_user_port(dp, ds) {
+ /* Handle this port after */
+ if (dp->index == port)
+ continue;
+
+ /* Skip ports that are not in this bridge */
+ if (!dsa_port_offloads_bridge(dp, &bridge))
+ continue;
+
+ ret = priv->ops->port_add_isolation(priv, dp->index, BIT(port));
+ if (ret)
+ return ret;
+
+ mask |= BIT(dp->index);
+ }
+
+ /* Add those ports to the isolation group of this port */
+ ret = priv->ops->port_add_isolation(priv, port, mask);
+ if (ret)
+ return ret;
+
+ /* Use the bridge number as the EFID for this port */
+ if (priv->ops->port_set_efid) {
+ ret = priv->ops->port_set_efid(priv, port, bridge.num);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(rtl83xx_port_bridge_join, "REALTEK_DSA");
+
+/**
+ * rtl83xx_port_bridge_leave() - leave a bridge
+ * @ds: DSA switch instance
+ * @port: port index
+ * @bridge: bridge being left
+ *
+ * This function handles removing a port from a bridge. It updates the port
+ * isolation masks and EFID.
+ *
+ * Context: Can sleep.
+ * Return: nothing
+ */
+void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge)
+{
+ struct realtek_priv *priv = ds->priv;
+ struct dsa_port *dp;
+ u32 mask = 0;
+
+ if (!priv->ops->port_remove_isolation)
+ return;
+
+ dev_dbg(priv->dev, "bridge %d leave port %d\n", bridge.num, port);
+
+ /* Remove this port from the isolation group of every other
+ * port offloading this bridge.
+ */
+ dsa_switch_for_each_user_port(dp, ds) {
+ /* Handle this port after */
+ if (dp->index == port)
+ continue;
+
+ /* Skip ports that are not in this bridge */
+ if (!dsa_port_offloads_bridge(dp, &bridge))
+ continue;
+
+ priv->ops->port_remove_isolation(priv, dp->index, BIT(port));
+
+ mask |= BIT(dp->index);
+ }
+
+ /* Remove those ports from the isolation group of this port */
+ priv->ops->port_remove_isolation(priv, port, mask);
+
+ /* Revert to the default EFID 0 for standalone mode */
+ if (priv->ops->port_set_efid)
+ priv->ops->port_set_efid(priv, port, 0);
+}
+EXPORT_SYMBOL_NS_GPL(rtl83xx_port_bridge_leave, "REALTEK_DSA");
+
MODULE_AUTHOR("Luiz Angelo Daros de Luca <luizluca@gmail.com>");
MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
MODULE_DESCRIPTION("Realtek DSA switches common module");
diff --git a/drivers/net/dsa/realtek/rtl83xx.h b/drivers/net/dsa/realtek/rtl83xx.h
index c8a0ff8fd75e..2481a1aaa226 100644
--- a/drivers/net/dsa/realtek/rtl83xx.h
+++ b/drivers/net/dsa/realtek/rtl83xx.h
@@ -21,4 +21,11 @@ void rtl83xx_remove(struct realtek_priv *priv);
void rtl83xx_reset_assert(struct realtek_priv *priv);
void rtl83xx_reset_deassert(struct realtek_priv *priv);
+int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge,
+ bool *tx_forward_offload,
+ struct netlink_ext_ack *extack);
+void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge);
+
#endif /* _RTL83XX_H */
--
2.54.0
^ permalink raw reply related
* [net-next PATCH v3 5/8] net: dsa: realtek: rtl8365mb: add VLAN support
From: Luiz Angelo Daros de Luca @ 2026-05-07 2:58 UTC (permalink / raw)
To: Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Linus Walleij,
Alvin Šipraga, Yury Norov, Rasmus Villemoes, Russell King
Cc: netdev, linux-kernel, Yury Norov, Abdulkader Alrezej,
Luiz Angelo Daros de Luca
In-Reply-To: <20260506-realtek_forward-v3-0-1d87c5f85a3b@gmail.com>
From: Alvin Šipraga <alsi@bang-olufsen.dk>
Realtek RTL8365MB switches (a.k.a. RTL8367C family) use two different
structures for VLANs:
- VLAN4K: A full table with 4096 entries defining port membership and
tagging.
- VLANMC: A smaller table with 32 entries used primarily for PVID
assignment.
In this hardware, a port's PVID must point to an index in the VLANMC
table rather than a VID directly. Since the VLANMC table is limited to
32 entries, the driver implements a dynamic allocation scheme to
maximize resource usage:
- VLAN4K is treated by the driver as the source of truth for membership.
- A VLANMC entry is only allocated when a port is configured to use a
specific VID as its PVID.
- VLANMC entries are deleted when no longer needed as a PVID by any port.
Although VLANMC has a members field, the switch only checks membership
in the VLAN4K table. However, when a corresponding VLAN entry also exists
in VLANMC, this driver keeps both membership configurations in sync.
VLANMC index 0, although a valid entry, is reserved in this driver as a
neutral PVID value for ports not using a specific PVID.
In the subsequent RTL8367D switch family, VLANMC table was
removed and PVID assignment was delegated to a dedicated set of
registers.
All ports start isolated, forwarding exclusively to CPU ports, and
with VLAN transparent, ignoring VLAN membership. Once a member in a
bridge, the port isolation is expanded to include the bridge members.
When that bridge enables VLAN filtering, the VLAN transparent feature is
disabled, letting the switch filter based on VLAN setup.
The use of FIELD_PREP for reconstructing LO/HI values was suggested by
Yury Norov.
Fix for vlan_setup and vlan_filtering was suggested by Abdulkader
Alrezej.
Suggested-by: Yury Norov <ynorov@nvidia.com>
Suggested-by: Abdulkader Alrezej <abdulkader.alrezej@gmail.com>
Co-developed-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
drivers/net/dsa/realtek/Makefile | 1 +
drivers/net/dsa/realtek/rtl8365mb_main.c | 248 ++++++++++
drivers/net/dsa/realtek/rtl8365mb_vlan.c | 797 +++++++++++++++++++++++++++++++
drivers/net/dsa/realtek/rtl8365mb_vlan.h | 25 +
4 files changed, 1071 insertions(+)
diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Makefile
index 99654c4c5a3d..b7fc4e852fd8 100644
--- a/drivers/net/dsa/realtek/Makefile
+++ b/drivers/net/dsa/realtek/Makefile
@@ -18,3 +18,4 @@ endif
obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8365mb.o
rtl8365mb-objs := rtl8365mb_main.o \
rtl8365mb_table.o \
+ rtl8365mb_vlan.o \
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index 7ddb82fcd026..b37aa847a9aa 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c
@@ -104,6 +104,7 @@
#include "realtek-smi.h"
#include "realtek-mdio.h"
#include "rtl83xx.h"
+#include "rtl8365mb_vlan.h"
/* Family-specific data and limits */
#define RTL8365MB_PHYADDRMAX 7
@@ -292,6 +293,67 @@
#define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \
(0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport)))
+/* Miscellaneous port configuration register, incl. VLAN egress mode */
+#define RTL8365MB_PORT_MISC_CFG_REG_BASE 0x000E
+#define RTL8365MB_PORT_MISC_CFG_REG(_p) \
+ (RTL8365MB_PORT_MISC_CFG_REG_BASE + ((_p) << 5))
+#define RTL8365MB_PORT_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000
+#define RTL8365MB_PORT_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000
+#define RTL8365MB_PORT_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000
+#define RTL8365MB_PORT_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000
+#define RTL8365MB_PORT_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x0800
+#define RTL8365MB_PORT_MISC_CFG_INGRESSBW_IFG_MASK 0x0400
+#define RTL8365MB_PORT_MISC_CFG_RX_SPC_MASK 0x0200
+#define RTL8365MB_PORT_MISC_CFG_CRC_SKIP_MASK 0x0100
+#define RTL8365MB_PORT_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x0080
+#define RTL8365MB_PORT_MISC_CFG_MAC_LOOPBACK_MASK 0x0040
+/* See &rtl8365mb_vlan_egress_mode */
+#define RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x0030
+#define RTL8365MB_PORT_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0x000F
+
+/**
+ * enum rtl8365mb_vlan_egress_mode - port VLAN egress mode
+ * @RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL: follow untag mask in VLAN4k table entry
+ * @RTL8365MB_VLAN_EGRESS_MODE_KEEP: the VLAN tag format of egressed packets
+ * will remain the same as their ingressed format, but the priority and VID
+ * fields may be altered
+ * @RTL8365MB_VLAN_EGRESS_MODE_PRI_TAG: always egress with priority tag
+ * @RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP: the VLAN tag format of egressed
+ * packets will remain the same as their ingressed format, and neither the
+ * priority nor VID fields can be altered
+ */
+enum rtl8365mb_vlan_egress_mode {
+ RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL = 0,
+ RTL8365MB_VLAN_EGRESS_MODE_KEEP = 1,
+ RTL8365MB_VLAN_EGRESS_MODE_PRI_TAG = 2,
+ RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP = 3,
+};
+
+/* VLAN control register */
+#define RTL8365MB_VLAN_CTRL_REG 0x07A8
+#define RTL8365MB_VLAN_CTRL_EN_MASK 0x0001
+
+/* VLAN ingress filter register */
+#define RTL8365MB_VLAN_INGRESS_REG 0x07A9
+#define RTL8365MB_VLAN_INGRESS_MASK GENMASK(10, 0)
+#define RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_OFFSET(_p) (_p)
+#define RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(_p) BIT(_p)
+
+/* VLAN "transparent" setting registers */
+#define RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG_BASE 0x09D0
+#define RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG(_p) \
+ (RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG_BASE + (_p))
+
+/* Frame type filtering registers */
+#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_BASE 0x07aa
+#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_REG(port) \
+ (RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_BASE + ((port) >> 3))
+/* required as FIELD_PREP cannot use non-constant masks */
+#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_MASK(port) \
+ (0x3 << RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_OFFSET(port))
+#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_OFFSET(port) \
+ (((port) & 0x7) << 1)
+
/* MIB counter value registers */
#define RTL8365MB_MIB_COUNTER_BASE 0x1000
#define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x))
@@ -1196,6 +1258,175 @@ static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port,
val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port));
}
+static int rtl8365mb_port_set_transparent(struct realtek_priv *priv,
+ int igr_port, int egr_port,
+ bool enable)
+{
+ dev_dbg(priv->dev, "%s transparent VLAN from %d to %d\n",
+ enable ? "Enable" : "Disable", igr_port, egr_port);
+
+ /* "Transparent" between the two ports means that packets forwarded by
+ * igr_port and egressed on egr_port will not be filtered by the usual
+ * VLAN membership settings.
+ */
+ return regmap_update_bits(priv->map,
+ RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG(egr_port),
+ BIT(igr_port), enable ? BIT(igr_port) : 0);
+}
+
+static int rtl8365mb_port_set_ingress_filtering(struct realtek_priv *priv,
+ int port, bool enable)
+{
+ /* Ingress filtering enabled: Discard VLAN-tagged frames if the port is
+ * not a member of the VLAN with which the packet is associated.
+ * Untagged packets will also be discarded unless the port has a PVID
+ * programmed. Priority-tagged frames are treated as untagged frames.
+ *
+ * Ingress filtering disabled: Accept all tagged and untagged frames.
+ */
+ return regmap_update_bits(priv->map, RTL8365MB_VLAN_INGRESS_REG,
+ RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(port),
+ enable ?
+ RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(port) :
+ 0);
+}
+
+static int
+rtl8365mb_port_set_vlan_egress_mode(struct realtek_priv *priv, int port,
+ enum rtl8365mb_vlan_egress_mode mode)
+{
+ u32 val;
+
+ val = FIELD_PREP(RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK, mode);
+ return regmap_update_bits(priv->map,
+ RTL8365MB_PORT_MISC_CFG_REG(port),
+ RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK, val);
+}
+
+static int rtl8365mb_port_vlan_filtering(struct dsa_switch *ds, int port,
+ bool vlan_filtering,
+ struct netlink_ext_ack *extack)
+{
+ enum rtl8365mb_vlan_egress_mode mode;
+ struct realtek_priv *priv = ds->priv;
+ struct dsa_port *dp;
+ int ret;
+
+ dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
+ vlan_filtering ? "enable" : "disable");
+
+ /* When vlan filter is enable/disabled in a bridge, this function is
+ * called for all member ports. We need to enable/disable ingress
+ * VLAN membership check.
+ */
+ ret = rtl8365mb_port_set_ingress_filtering(priv, port, vlan_filtering);
+ if (ret)
+ return ret;
+
+ /* However, we also enable/disable egress filtering because the switch
+ * still consider the egress interface VLAN membership to forward the
+ * traffic. We enable/disable that check disabling/enabling transparent
+ * VLAN between the ingress port and all other available ports.
+ */
+ dsa_switch_for_each_available_port(dp, ds) {
+ /* port isolation will still keep traffic inside the bridge */
+ ret = rtl8365mb_port_set_transparent(priv, port, dp->index,
+ !vlan_filtering);
+ if (ret)
+ return ret;
+ }
+
+ /* When VLAN filtering is disabled, preserve frames exactly as received.
+ * Otherwise, the VLAN egress pipeline may still alter tag state
+ * according to VLAN membership and untag configuration.
+ */
+ if (vlan_filtering)
+ mode = RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL;
+ else
+ mode = RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP;
+
+ return rtl8365mb_port_set_vlan_egress_mode(priv, port, mode);
+}
+
+static int rtl8365mb_port_vlan_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack)
+{
+ bool untagged = !!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
+ bool pvid = !!(vlan->flags & BRIDGE_VLAN_INFO_PVID);
+ struct realtek_priv *priv = ds->priv;
+ int ret;
+
+ dev_dbg(priv->dev, "add VLAN %d on port %d, %s, %s\n",
+ vlan->vid, port, untagged ? "untagged" : "tagged",
+ pvid ? "PVID" : "no PVID");
+ /* add port to vlan4k. It knows nothing about PVID */
+ ret = rtl8365mb_vlan_4k_port_add(ds, port, vlan, extack);
+ if (ret)
+ return ret;
+
+ /* Set PVID if needed */
+ if (pvid) {
+ ret = rtl8365mb_vlan_pvid_port_add(ds, port, vlan, extack);
+ if (ret)
+ goto undo_vlan_4k;
+ }
+
+ return 0;
+
+undo_vlan_4k:
+ (void)rtl8365mb_vlan_4k_port_del(ds, port, vlan);
+ return ret;
+}
+
+static int rtl8365mb_port_vlan_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan)
+{
+ bool untagged = !!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
+ bool pvid = !!(vlan->flags & BRIDGE_VLAN_INFO_PVID);
+ struct realtek_priv *priv = ds->priv;
+ int ret1, ret2;
+
+ dev_dbg(priv->dev, "del VLAN %d on port %d, %s, %s\n",
+ vlan->vid, port, untagged ? "untagged" : "tagged",
+ pvid ? "PVID" : "no PVID");
+
+ ret1 = rtl8365mb_vlan_pvid_port_del(ds, port, vlan);
+ ret2 = rtl8365mb_vlan_4k_port_del(ds, port, vlan);
+
+ return ret1 ?: ret2;
+}
+
+/* VLAN support is always enabled in the switch.
+ *
+ * Standalone forwarding relies on transparent VLAN mode combined with per-port
+ * isolation masks restricting egress to CPU ports only.
+ *
+ */
+static int rtl8365mb_vlan_setup(struct dsa_switch *ds)
+{
+ struct realtek_priv *priv = ds->priv;
+ struct dsa_port *dp;
+ int ret;
+
+ dsa_switch_for_each_available_port(dp, ds) {
+ /* Disable vlan-filtering for all ports */
+ ret = rtl8365mb_port_vlan_filtering(ds, dp->index, false, NULL);
+ if (ret) {
+ dev_err(priv->dev,
+ "Failed to disable vlan filtering on port %d\n",
+ dp->index);
+ return ret;
+ }
+ }
+
+ /* VLAN is always enabled. */
+ ret = regmap_update_bits(priv->map, RTL8365MB_VLAN_CTRL_REG,
+ RTL8365MB_VLAN_CTRL_EN_MASK,
+ FIELD_PREP(RTL8365MB_VLAN_CTRL_EN_MASK, 1));
+ return ret;
+}
+
static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port,
bool enable)
{
@@ -2035,6 +2266,20 @@ static int rtl8365mb_setup(struct dsa_switch *ds)
if (ret)
goto out_teardown_irq;
+ ds->configure_vlan_while_not_filtering = true;
+
+ /* Set up VLAN */
+ ret = rtl8365mb_vlan_setup(ds);
+ if (ret)
+ goto out_teardown_irq;
+
+ /* Set maximum packet length to 1536 bytes */
+ ret = regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG,
+ RTL8365MB_CFG0_MAX_LEN_MASK,
+ FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1536));
+ if (ret)
+ goto out_teardown_irq;
+
ret = rtl83xx_setup_user_mdio(ds);
if (ret) {
dev_err(priv->dev, "could not set up MDIO bus\n");
@@ -2145,6 +2390,9 @@ static const struct dsa_switch_ops rtl8365mb_switch_ops = {
.teardown = rtl8365mb_teardown,
.phylink_get_caps = rtl8365mb_phylink_get_caps,
.port_stp_state_set = rtl8365mb_port_stp_state_set,
+ .port_vlan_add = rtl8365mb_port_vlan_add,
+ .port_vlan_del = rtl8365mb_port_vlan_del,
+ .port_vlan_filtering = rtl8365mb_port_vlan_filtering,
.get_strings = rtl8365mb_get_strings,
.get_ethtool_stats = rtl8365mb_get_ethtool_stats,
.get_sset_count = rtl8365mb_get_sset_count,
diff --git a/drivers/net/dsa/realtek/rtl8365mb_vlan.c b/drivers/net/dsa/realtek/rtl8365mb_vlan.c
new file mode 100644
index 000000000000..a68e0d18a611
--- /dev/null
+++ b/drivers/net/dsa/realtek/rtl8365mb_vlan.c
@@ -0,0 +1,797 @@
+// SPDX-License-Identifier: GPL-2.0
+/* VLAN configuration interface for the rtl8365mb switch family
+ *
+ * Copyright (C) 2022 Alvin Šipraga <alsi@bang-olufsen.dk>
+ *
+ * VLAN configuration takes place in two separate domains of the switch: the
+ * VLAN4k table and the VLAN membership configuration (MC) database. While the
+ * VLAN4k table is exhaustive and can be fully populated with 4096 VLAN
+ * configurations, the same does not hold for the VLAN membership configuration
+ * database, which is limited to 32 entries.
+ *
+ * The switch will normally only use the VLAN4k table when making forwarding
+ * decisions. The VLAN membership configuration database is a vestigial ASIC
+ * design and is only used for a few specific features in the rtl8365mb
+ * family. This means that the limit of 32 entries should not hinder us in
+ * programming a huge number of VLANs into the switch.
+ *
+ * One necessary use of the VLAN membership configuration database is for the
+ * programming of a port-based VLAN ID (PVID). The PVID is programmed on a
+ * per-port basis via register field, which refers to a specific VLAN membership
+ * configuration via an index 0~31. In order to maintain coherent behaviour on a
+ * port with a PVID, it is necessary to keep the VLAN configuration synchronized
+ * between the VLAN4k table and the VLAN membership configuration database.
+ *
+ * Since VLAN membership configs are a scarce resource, it will only be used
+ * when strictly needed (i.e. a VLAN with members using PVID). Otherwise, the
+ * VLAN4k will be enough.
+ *
+ * With some exceptions, the entries in both the VLAN4k table and the VLAN
+ * membership configuration database offer the same configuration options. The
+ * differences are as follows:
+ *
+ * 1. VLAN4k entries can specify whether to use Independent or Shared VLAN
+ * Learning (IVL or SVL respectively). VLAN membership config entries
+ * cannot. This underscores the fact that VLAN membership configs are not
+ * involved in the learning process of the ASIC.
+ *
+ * 2. VLAN membership config entries use an "enhanced VLAN ID" (efid), which has
+ * a range 0~8191 compared with the standard 0~4095 range of the VLAN4k
+ * table. This underscores the fact that VLAN membership configs can be used
+ * to group ports on a layer beyond the standard VLAN configuration, which
+ * may be useful for ACL rules which specify alternative forwarding
+ * decisions.
+ *
+ * VLANMC index 0 is reserved as a neutral PVID, used for standalone ports.
+ *
+ */
+
+#include "rtl8365mb_vlan.h"
+#include "rtl8365mb_table.h"
+#include <linux/if_bridge.h>
+#include <linux/regmap.h>
+
+/* CVLAN (i.e. VLAN4k) table entry layout, u16[3] */
+#define RTL8365MB_CVLAN_ENTRY_SIZE 3 /* 48-bits */
+#define RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK GENMASK(7, 0)
+#define RTL8365MB_CVLAN_MBR_LO_MASK GENMASK(7, 0)
+#define RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK GENMASK(15, 8)
+#define RTL8365MB_CVLAN_UNTAG_LO_MASK GENMASK(7, 0)
+#define RTL8365MB_CVLAN_ENTRY_D1_FID_MASK GENMASK(3, 0)
+#define RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK GENMASK(4, 4)
+#define RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK GENMASK(7, 5)
+#define RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK GENMASK(8, 8)
+#define RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK GENMASK(13, 9)
+#define RTL8365MB_CVLAN_METERIDX_LO_MASK GENMASK(4, 0)
+#define RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK GENMASK(14, 14)
+/* extends RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK */
+#define RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK GENMASK(2, 0)
+#define RTL8365MB_CVLAN_MBR_HI_MASK GENMASK(10, 8)
+/* extends RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK */
+#define RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK GENMASK(5, 3)
+#define RTL8365MB_CVLAN_UNTAG_HI_MASK GENMASK(10, 8)
+/* extends RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK */
+#define RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK GENMASK(6, 6)
+#define RTL8365MB_CVLAN_METERIDX_HI_MASK GENMASK(5, 5)
+
+/* VLAN member configuration registers 0~31, u16[3] */
+#define RTL8365MB_VLAN_MC_BASE 0x0728
+#define RTL8365MB_VLAN_MC_ENTRY_SIZE 4 /* 64-bit */
+#define RTL8365MB_VLAN_MC_REG(index) \
+ (RTL8365MB_VLAN_MC_BASE + \
+ (RTL8365MB_VLAN_MC_ENTRY_SIZE * (index)))
+#define RTL8365MB_VLAN_MC_D0_MBR_MASK GENMASK(10, 0)
+#define RTL8365MB_VLAN_MC_D1_FID_MASK GENMASK(3, 0)
+
+#define RTL8365MB_VLAN_MC_D2_VBPEN_MASK GENMASK(0, 0)
+#define RTL8365MB_VLAN_MC_D2_VBPRI_MASK GENMASK(3, 1)
+#define RTL8365MB_VLAN_MC_D2_ENVLANPOL_MASK GENMASK(4, 4)
+#define RTL8365MB_VLAN_MC_D2_METERIDX_MASK GENMASK(10, 5)
+#define RTL8365MB_VLAN_MC_D3_EVID_MASK GENMASK(12, 0)
+
+/* Some limits for VLAN4k/VLAN membership config entries */
+#define RTL8365MB_PRIORITYMAX 7
+#define RTL8365MB_FIDMAX 15
+#define RTL8365MB_METERMAX 63
+#define RTL8365MB_VLAN_MCMAX 31
+
+/* RTL8367S supports 4k vlans (vid<=4095) and 32 enhanced vlans
+ * for VIDs up to 8191
+ */
+#define RTL8365MB_MAX_4K_VID 0x0FFF /* 4095 */
+#define RTL8365MB_MAX_MC_VID 0x1FFF /* 8191 */
+
+ /* Port-based VID registers 0~5 - each one holds an MC index for two ports */
+#define RTL8365MB_VLAN_PVID_CTRL_BASE 0x0700
+#define RTL8365MB_VLAN_PVID_CTRL_REG(_p) \
+ (RTL8365MB_VLAN_PVID_CTRL_BASE + ((_p) >> 1))
+#define RTL8365MB_VLAN_PVID_CTRL_PORT0_MCIDX_MASK 0x001F
+#define RTL8365MB_VLAN_PVID_CTRL_PORT1_MCIDX_MASK 0x1F00
+#define RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_OFFSET(_p) \
+ (((_p) & 1) << 3)
+#define RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_MASK(_p) \
+ (0x1F << RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_OFFSET(_p))
+
+/* Frame type filtering registers */
+#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_BASE 0x07aa
+#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_REG(port) \
+ (RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_BASE + ((port) >> 3))
+/* required as FIELD_PREP cannot use non-constant masks */
+#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_MASK(port) \
+ (0x3 << RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_OFFSET(port))
+#define RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_OFFSET(port) \
+ (((port) & 0x7) << 1)
+
+/**
+ * struct rtl8365mb_vlan4k - VLAN4k table entry
+ * @vid: VLAN ID (0~4095)
+ * @member: port mask of ports in this VLAN
+ * @untag: port mask of ports which untag on egress
+ * @fid: filter ID - only used with SVL (unused)
+ * @priority: priority classification (unused)
+ * @priority_en: enable priority (unused)
+ * @policing_en: enable policing (unused)
+ * @ivl_en: enable IVL instead of default SVL
+ * @meteridx: metering index (unused)
+ *
+ * This structure is used to get/set entries in the VLAN4k table. The
+ * VLAN4k table dictates the VLAN configuration for the switch for the
+ * vast majority of features.
+ */
+struct rtl8365mb_vlan4k {
+ u16 vid;
+ u16 member;
+ u16 untag;
+ u8 fid : 4;
+ u8 priority : 3;
+ u8 priority_en : 1;
+ u8 policing_en : 1;
+ u8 ivl_en : 1;
+ u8 meteridx : 6;
+};
+
+/**
+ * struct rtl8365mb_vlanmc - VLAN membership config
+ * @evid: Enhanced VLAN ID (0~8191)
+ * @member: port mask of ports in this VLAN
+ * @fid: filter ID - only used with SVL (unused)
+ * @priority: priority classification (unused)
+ * @priority_en: enable priority (unused)
+ * @policing_en: enable policing (unused)
+ * @meteridx: metering index (unused)
+ *
+ * This structure is used to get/set entries in the VLAN membership
+ * configuration database. This feature is largely vestigial, but
+ * still needed for at least the following features:
+ * - PVID configuration
+ * - ACL configuration
+ * - selection of VLAN by the CPU tag when VSEL=1, although the switch
+ * can also select VLAN based on the VLAN tag if VSEL=0
+ *
+ * This is a low-level structure and it is recommended to interface with
+ * the VLAN membership config database via &struct rtl8365mb_vlanmc_entry.
+ */
+struct rtl8365mb_vlanmc {
+ u16 evid;
+ u16 member;
+ u8 fid : 4;
+ u8 priority : 3;
+ u8 priority_en : 1;
+ u8 policing_en : 1;
+ u8 meteridx : 6;
+};
+
+enum rtl8365mb_frame_ingress {
+ RTL8365MB_FRAME_TYPE_ANY_FRAME = 0,
+ RTL8365MB_FRAME_TYPE_TAGGED_ONLY,
+ RTL8365MB_FRAME_TYPE_UNTAGGED_ONLY,
+};
+
+static int rtl8365mb_vlan_4k_read(struct realtek_priv *priv, u16 vid,
+ struct rtl8365mb_vlan4k *vlan4k)
+{
+ u16 data[RTL8365MB_CVLAN_ENTRY_SIZE];
+ int val;
+ int ret;
+
+ ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_CVLAN,
+ RTL8365MB_TABLE_OP_READ, &vid, 0, 0,
+ data, ARRAY_SIZE(data));
+ if (ret)
+ return ret;
+
+ /* Unpack table entry */
+ memset(vlan4k, 0, sizeof(*vlan4k));
+ vlan4k->vid = vid;
+
+ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK, data[0]);
+ vlan4k->member = FIELD_PREP(RTL8365MB_CVLAN_MBR_LO_MASK, val);
+ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, data[2]);
+ vlan4k->member |= FIELD_PREP(RTL8365MB_CVLAN_MBR_HI_MASK, val);
+
+ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK, data[0]);
+ vlan4k->untag = FIELD_PREP(RTL8365MB_CVLAN_UNTAG_LO_MASK, val);
+ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK, data[2]);
+ vlan4k->untag |= FIELD_PREP(RTL8365MB_CVLAN_UNTAG_HI_MASK, val);
+
+ vlan4k->fid = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, data[1]);
+ vlan4k->priority_en =
+ FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK, data[1]);
+ vlan4k->priority =
+ FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK, data[1]);
+ vlan4k->policing_en =
+ FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK, data[1]);
+
+ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK, data[1]);
+ val = FIELD_PREP(RTL8365MB_CVLAN_METERIDX_LO_MASK, val);
+ vlan4k->meteridx = val;
+ val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK, data[2]);
+ val = FIELD_PREP(RTL8365MB_CVLAN_METERIDX_HI_MASK, val);
+ vlan4k->meteridx |= val;
+
+ vlan4k->ivl_en =
+ FIELD_GET(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK, data[1]);
+
+ return 0;
+}
+
+static int rtl8365mb_vlan_4k_write(struct realtek_priv *priv,
+ const struct rtl8365mb_vlan4k *vlan4k)
+{
+ u16 data[RTL8365MB_CVLAN_ENTRY_SIZE] = { 0 };
+ u16 vid;
+ int val;
+
+ /* Pack table entry value */
+ val = FIELD_GET(RTL8365MB_CVLAN_MBR_LO_MASK, vlan4k->member);
+ data[0] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK, val);
+
+ val = FIELD_GET(RTL8365MB_CVLAN_UNTAG_LO_MASK, vlan4k->untag);
+ data[0] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK, val);
+
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_FID_MASK, vlan4k->fid);
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPEN_MASK,
+ vlan4k->priority_en);
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_VBPRI_MASK,
+ vlan4k->priority);
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_ENVLANPOL_MASK,
+ vlan4k->policing_en);
+
+ /* FIELD_* does not play nice with struct bitfield. */
+ val = vlan4k->meteridx;
+ val = FIELD_GET(RTL8365MB_CVLAN_METERIDX_LO_MASK, val);
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK, val);
+
+ data[1] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK,
+ vlan4k->ivl_en);
+
+ val = FIELD_GET(RTL8365MB_CVLAN_MBR_HI_MASK, vlan4k->member);
+ data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK, val);
+
+ val = FIELD_GET(RTL8365MB_CVLAN_UNTAG_HI_MASK, vlan4k->untag);
+ data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_UNTAG_EXT_MASK, val);
+
+ val = vlan4k->meteridx;
+ val = FIELD_GET(RTL8365MB_CVLAN_METERIDX_HI_MASK, val);
+ data[2] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D2_METERIDX_EXT_MASK, val);
+
+ vid = vlan4k->vid;
+ return rtl8365mb_table_query(priv, RTL8365MB_TABLE_CVLAN,
+ RTL8365MB_TABLE_OP_WRITE, &vid, 0, 0,
+ data, ARRAY_SIZE(data));
+}
+
+#define RTL_VLAN_ERR(msg) \
+ do { \
+ const char *__msg = (msg); \
+ \
+ if (extack) \
+ NL_SET_ERR_MSG_FMT_MOD(extack, "%s", __msg); \
+ dev_err(priv->dev, "%s", __msg); \
+ } while (0)
+
+static int
+rtl8365mb_vlan_4k_port_set(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack,
+ bool include)
+{
+ struct realtek_priv *priv = ds->priv;
+ struct rtl8365mb_vlan4k vlan4k = {0};
+ int ret;
+
+ dev_dbg(priv->dev, "%s VLAN %d 4K on port %d\n",
+ include ? "add" : "del",
+ vlan->vid, port);
+
+ if (vlan->vid > RTL8365MB_MAX_4K_VID) {
+ RTL_VLAN_ERR("VLAN ID greater than "
+ __stringify(RTL8365MB_MAX_4K_VID));
+ return -EINVAL;
+ }
+
+ ret = rtl8365mb_vlan_4k_read(priv, vlan->vid, &vlan4k);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to read VLAN 4k table");
+ return ret;
+ }
+
+ if (include)
+ vlan4k.member |= BIT(port);
+ else
+ vlan4k.member &= ~BIT(port);
+
+ if (include && (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
+ vlan4k.untag |= BIT(port);
+ else
+ vlan4k.untag &= ~BIT(port);
+ vlan4k.ivl_en = true; /* always use Independent VLAN Learning */
+
+ ret = rtl8365mb_vlan_4k_write(priv, &vlan4k);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to write VLAN 4k table");
+ return ret;
+ }
+
+ return 0;
+}
+
+int rtl8365mb_vlan_4k_port_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack)
+{
+ return rtl8365mb_vlan_4k_port_set(ds, port, vlan, extack, true);
+}
+
+int rtl8365mb_vlan_4k_port_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan)
+{
+ return rtl8365mb_vlan_4k_port_set(ds, port, vlan, NULL, false);
+}
+
+static int rtl8365mb_vlan_mc_read(struct realtek_priv *priv, u32 index,
+ struct rtl8365mb_vlanmc *vlanmc)
+{
+ u16 data[RTL8365MB_VLAN_MC_ENTRY_SIZE];
+ int ret;
+
+ ret = regmap_bulk_read(priv->map, RTL8365MB_VLAN_MC_REG(index), &data,
+ RTL8365MB_VLAN_MC_ENTRY_SIZE);
+ if (ret)
+ return ret;
+
+ vlanmc->member = FIELD_GET(RTL8365MB_VLAN_MC_D0_MBR_MASK, data[0]);
+ vlanmc->fid = FIELD_GET(RTL8365MB_VLAN_MC_D1_FID_MASK, data[1]);
+ vlanmc->priority = FIELD_GET(RTL8365MB_VLAN_MC_D2_VBPRI_MASK, data[2]);
+ vlanmc->evid = FIELD_GET(RTL8365MB_VLAN_MC_D3_EVID_MASK, data[3]);
+
+ return 0;
+}
+
+static int rtl8365mb_vlan_mc_write(struct realtek_priv *priv, u32 index,
+ const struct rtl8365mb_vlanmc *vlanmc)
+{
+ u16 data[4] = { 0 };
+ int ret;
+
+ data[0] |= FIELD_PREP(RTL8365MB_VLAN_MC_D0_MBR_MASK, vlanmc->member);
+ data[1] |= FIELD_PREP(RTL8365MB_VLAN_MC_D1_FID_MASK, vlanmc->fid);
+ data[2] |= FIELD_PREP(RTL8365MB_VLAN_MC_D2_METERIDX_MASK,
+ vlanmc->meteridx);
+ data[2] |= FIELD_PREP(RTL8365MB_VLAN_MC_D2_ENVLANPOL_MASK,
+ vlanmc->policing_en);
+ data[2] |=
+ FIELD_PREP(RTL8365MB_VLAN_MC_D2_VBPRI_MASK, vlanmc->priority);
+ data[2] |= FIELD_PREP(RTL8365MB_VLAN_MC_D2_VBPEN_MASK,
+ vlanmc->priority_en);
+ data[3] |= FIELD_PREP(RTL8365MB_VLAN_MC_D3_EVID_MASK, vlanmc->evid);
+
+ ret = regmap_bulk_write(priv->map, RTL8365MB_VLAN_MC_REG(index), &data,
+ RTL8365MB_VLAN_MC_ENTRY_SIZE);
+
+ return ret;
+}
+
+static int rtl8365mb_vlan_mc_erase(struct realtek_priv *priv, u32 index)
+{
+ u16 data[4] = { 0 };
+ int ret;
+
+ ret = regmap_bulk_write(priv->map, RTL8365MB_VLAN_MC_REG(index), &data,
+ RTL8365MB_VLAN_MC_ENTRY_SIZE);
+
+ return ret;
+}
+
+/**
+ * rtl8365mb_vlan_mc_find() - find VLANMC index by VID or the first free index
+ *
+ * @priv: realtek_priv pointer
+ * @vid: VLAN ID
+ * @index: found index
+ * @first_free: found free index
+ *
+ * If a VLAN MC entry using @vid was found, @index will return the matched index
+ * and @first_free is undefined. If not found, @index will return 0 and
+ * @first_free will return the first found free index in VLAN MC or 0 if the
+ * table is full.
+ *
+ * Although 0 is a valid VLAN MC index, it is reserved for ports without PVID,
+ * including standalone, non-member ports.
+ *
+ * Both @index and @first_free will be in the * 1..@RTL8365MB_VLAN_MCMAX range.
+ *
+ * Return: Returns 0 on success, a negative error on failure.
+ *
+ */
+static int rtl8365mb_vlan_mc_find(struct realtek_priv *priv, u16 vid,
+ u8 *index, u8 *first_free)
+{
+ u32 vlan_entry_d3;
+ u8 vlanmc_idx;
+ u16 evid;
+ int ret;
+
+ *index = 0;
+ *first_free = 0;
+
+ /* look for existing entry or an empty one */
+ /* vlanmc index 0 is reserved as a neutral PVID value for standalone
+ * ports. Traffic reaches the CPU via VLAN transparent mode.
+ **/
+ for (vlanmc_idx = 1; vlanmc_idx <= RTL8365MB_VLAN_MCMAX; vlanmc_idx++) {
+ /* just read the 4th word, where the evid is */
+ ret = regmap_read(priv->map,
+ RTL8365MB_VLAN_MC_REG(vlanmc_idx) + 3,
+ &vlan_entry_d3);
+ if (ret)
+ return ret;
+
+ evid = FIELD_GET(RTL8365MB_VLAN_MC_D3_EVID_MASK, vlan_entry_d3);
+
+ if (evid == vid) {
+ *index = vlanmc_idx;
+ return 0;
+ }
+
+ if (evid == 0x0 && *first_free < 1)
+ *first_free = vlanmc_idx;
+ }
+ return 0;
+}
+
+static int rtl8365mb_vlan_port_get_pvid(struct realtek_priv *priv,
+ int port, u8 *vlanmc_idx)
+{
+ u32 data;
+ int ret;
+
+ ret = regmap_read(priv->map, RTL8365MB_VLAN_PVID_CTRL_REG(port), &data);
+ if (ret)
+ return ret;
+
+ *vlanmc_idx = (data & RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_MASK(port))
+ >> RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_OFFSET(port);
+
+ return 0;
+}
+
+/**
+ * rtl8365mb_vlan_mc_pvid_members() - Get a bitmap of vlan PVID members
+ *
+ * @ds: DSA switch
+ * @vlanmc_idx: the index of a VLAN in VLAN MC table
+ * @members: the returned bitmap of members that have PVID status
+ *
+ * This function iterates over DSA ports and creates a bitmap representation of
+ * those ports that have PVID pointing to this VLAN (identified by its table
+ * index and not VID). If you need to get the table index from VID, see
+ * rtl8365mb_vlan_mc_find()
+ *
+ * Return: Returns 0 on success, a negative error on failure.
+ **/
+static int rtl8365mb_vlan_mc_pvid_members(struct dsa_switch *ds,
+ u8 vlanmc_idx, u16 *members)
+{
+ struct realtek_priv *priv = ds->priv;
+ struct dsa_port *dp;
+ u8 _vlanmc_idx;
+ int ret;
+
+ *members = 0;
+
+ dsa_switch_for_each_available_port(dp, ds) {
+ ret = rtl8365mb_vlan_port_get_pvid(priv, dp->index,
+ &_vlanmc_idx);
+ if (ret)
+ return ret;
+
+ if (_vlanmc_idx == vlanmc_idx)
+ *members |= BIT(dp->index);
+ }
+
+ return 0;
+}
+
+/**
+ * rtl8365mb_vlan_mc_port_set() - include or exclude a port from vlanMC
+ * @ds: dsa switch
+ * @port: the port number
+ * @vlan: the vlan to include/exclude @port
+ * @extack: optional extack to return errors
+ * @include: whether to include or exclude @port
+ *
+ * This function is used to include/exclude ports to the vlanMC table.
+ *
+ * VlanMC stands for VLAN membership config and it is used exclusively for
+ * PVID. If @vlan members are not using PVID, this function will either
+ * remove or not create a new vlanMC entry.
+ *
+ * vlanMC members are kept in sync with vlan4k, although the switch only
+ * checks membership in vlan4k table.
+ *
+ * Port PVID and accepted frame type are updated as well.
+ *
+ * Return: Returns 0 on success, a negative error on failure.
+ */
+static
+int rtl8365mb_vlan_mc_port_set(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack,
+ bool include)
+{
+ bool pvid = !!(vlan->flags & BRIDGE_VLAN_INFO_PVID);
+ struct realtek_priv *priv = ds->priv;
+ struct rtl8365mb_vlan4k vlan4k = {0};
+ struct rtl8365mb_vlanmc vlanmc = {0};
+ u16 pvid_members = 0;
+ u8 first_unused = 0;
+ u8 vlanmc_idx = 0;
+ int ret;
+
+ dev_dbg(priv->dev, "%s VLAN %d MC on port %d\n",
+ include ? "add" : "del",
+ vlan->vid, port);
+
+ if (vlan->vid > RTL8365MB_MAX_MC_VID) {
+ RTL_VLAN_ERR("VLAN ID greater than "
+ __stringify(RTL8365MB_MAX_MC_VID));
+ return -EINVAL;
+ }
+
+ /* look for existing entry or an empty slot */
+ ret = rtl8365mb_vlan_mc_find(priv, vlan->vid, &vlanmc_idx,
+ &first_unused);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to find a VLAN MC table index");
+ return ret;
+ }
+
+ if (vlanmc_idx) {
+ ret = rtl8365mb_vlan_mc_read(priv, vlanmc_idx, &vlanmc);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to read VLAN MC table");
+ return ret;
+ }
+ } else if (include) {
+ /* for now, vlan_mc is only required for PVID. Defer allocation
+ * until at least one port uses PVID.
+ */
+ if (!pvid) {
+ dev_dbg(priv->dev,
+ "Not creating VlanMC for vlan %d until a port uses PVID (%d does not)\n",
+ vlan->vid, port);
+ return 0;
+ }
+
+ if (!first_unused) {
+ RTL_VLAN_ERR("All VLAN MC entries ("
+ __stringify(RTL8365MB_VLAN_MCMAX + 1)
+ ") are in use.");
+ return -E2BIG;
+ }
+
+ /* Retrieve vlan4k members as we might have deferred VlanMC
+ * before.
+ */
+ if (vlan->vid <= RTL8365MB_MAX_4K_VID) {
+ ret = rtl8365mb_vlan_4k_read(priv, vlan->vid, &vlan4k);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to read VLAN 4k table");
+ return ret;
+ }
+ }
+
+ vlanmc_idx = first_unused;
+ vlanmc.evid = vlan->vid;
+
+ /* for new vlan_mc, sync current vlan4k members,
+ * although only vlan4k members matter.
+ */
+ vlanmc.member |= vlan4k.member;
+ } else /* excluding and VLANMC not found */ {
+ return 0;
+ }
+
+ ret = rtl8365mb_vlan_mc_pvid_members(ds, vlanmc_idx,
+ &pvid_members);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to read VLANMC PVID members");
+ return ret;
+ }
+ dev_dbg(priv->dev,
+ "VLAN %d (idx: %d) PVID curr members: %08x\n",
+ vlan->vid, vlanmc_idx, pvid_members);
+
+ /* here we either have an existing VLANMC (with PVID members) or the
+ * added port is using this VLAN as PVID
+ */
+ if (include) {
+ vlanmc.member |= BIT(port);
+ if (pvid)
+ pvid_members |= BIT(port);
+ } else {
+ vlanmc.member &= ~BIT(port);
+ pvid_members &= ~BIT(port);
+ }
+
+ /* just like we don't need to create a VLAN_MC when there is no port
+ * using it as PVID, we can erase it when there is no more port using
+ * it as PVID.
+ */
+ if (!pvid_members) {
+ dev_dbg(priv->dev,
+ "Clearing VlanMC index %d previously used by VID %d\n",
+ vlanmc_idx, vlan->vid);
+ ret = rtl8365mb_vlan_mc_erase(priv, vlanmc_idx);
+ } else {
+ dev_dbg(priv->dev,
+ "Saving VlanMC index %d with VID %d\n",
+ vlanmc_idx, vlan->vid);
+ ret = rtl8365mb_vlan_mc_write(priv, vlanmc_idx, &vlanmc);
+ }
+ if (ret) {
+ RTL_VLAN_ERR("Failed to write vlan MC entry");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rtl8365mb_vlan_port_set_pvid(struct realtek_priv *priv,
+ int port, u16 vlanmc_idx)
+{
+ int ret;
+ u32 val;
+
+ val = vlanmc_idx << RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_OFFSET(port);
+ ret = regmap_update_bits(priv->map,
+ RTL8365MB_VLAN_PVID_CTRL_REG(port),
+ RTL8365MB_VLAN_PVID_CTRL_PORT_MCIDX_MASK(port),
+ val);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int
+rtl8365mb_vlan_port_set_framefilter(struct realtek_priv *priv,
+ int port,
+ enum rtl8365mb_frame_ingress accepted_frame)
+{
+ /* Even if ACCEPT_FRAME_TYPE_ANY, the switch will still check if the
+ * port is a member of vlan PVID
+ */
+ accepted_frame = accepted_frame
+ << RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_OFFSET(port);
+
+ return regmap_update_bits(priv->map,
+ RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_REG(port),
+ RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_MASK(port),
+ accepted_frame);
+}
+
+int rtl8365mb_vlan_pvid_port_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack)
+{
+ bool pvid = !!(vlan->flags & BRIDGE_VLAN_INFO_PVID);
+ enum rtl8365mb_frame_ingress accepted_frame;
+ struct realtek_priv *priv = ds->priv;
+ u8 _unused_first_free_idx;
+ u8 vlanmc_idx;
+ int ret;
+
+ if (!pvid)
+ return 0;
+
+ /* Find or allocate a new vlan MC and add port to members,
+ * although members are not checked by the HW in vlan MC.
+ */
+ ret = rtl8365mb_vlan_mc_port_set(ds, port, vlan, extack, true);
+ if (ret)
+ return ret;
+
+ /* look for existing entry */
+ ret = rtl8365mb_vlan_mc_find(priv, vlan->vid, &vlanmc_idx,
+ &_unused_first_free_idx);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to find a VLAN MC table index");
+ goto undo_vlan_mc_port_set;
+ }
+
+ if (!vlanmc_idx) {
+ RTL_VLAN_ERR("VLAN should already exist in VLAN MC");
+ goto undo_vlan_mc_port_set;
+ }
+
+ ret = rtl8365mb_vlan_port_set_pvid(priv, port, vlanmc_idx);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to set port PVID");
+ goto undo_vlan_mc_port_set;
+ }
+
+ /* Changing accept frame is what enables PVID (if not enabled before) */
+ accepted_frame = RTL8365MB_FRAME_TYPE_ANY_FRAME;
+ ret = rtl8365mb_vlan_port_set_framefilter(priv, port, accepted_frame);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to set port frame filter");
+ goto undo_vlan_pvid_port_set;
+ }
+
+ return 0;
+
+undo_vlan_pvid_port_set:
+ (void)rtl8365mb_vlan_port_set_pvid(priv, port, 0);
+
+undo_vlan_mc_port_set:
+ (void)rtl8365mb_vlan_mc_port_set(ds, port, vlan, NULL, false);
+ return ret;
+}
+
+int rtl8365mb_vlan_pvid_port_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan)
+{
+ enum rtl8365mb_frame_ingress accepted_frame;
+ struct netlink_ext_ack *extack = NULL;
+ struct realtek_priv *priv = ds->priv;
+ struct rtl8365mb_vlanmc vlanmc = {0};
+ u8 vlanmc_idx;
+ int ret;
+
+ ret = rtl8365mb_vlan_port_get_pvid(priv, port, &vlanmc_idx);
+ if (ret)
+ return ret;
+
+ /* Port is not using PVID. Nothing to remove. */
+ if (!vlanmc_idx)
+ return 0;
+
+ ret = rtl8365mb_vlan_mc_read(priv, vlanmc_idx, &vlanmc);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to read VLAN MC table");
+ return ret;
+ }
+
+ /* We are leaving a non PVID vlan, Nothing to remove. */
+ if (vlanmc.evid != vlan->vid)
+ return 0;
+
+ /* Changing accept frame is what really removes PVID */
+ accepted_frame = RTL8365MB_FRAME_TYPE_TAGGED_ONLY;
+ ret = rtl8365mb_vlan_port_set_framefilter(priv, port, accepted_frame);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to set port frame filter");
+ return ret;
+ }
+
+ ret = rtl8365mb_vlan_port_set_pvid(priv, port, 0);
+ if (ret) {
+ RTL_VLAN_ERR("Failed to set port PVID to 0");
+ return ret;
+ }
+
+ /* Clears the VLAN MC membership and maybe VLAN MC entry if empty */
+ return rtl8365mb_vlan_mc_port_set(ds, port, vlan, NULL, false);
+}
diff --git a/drivers/net/dsa/realtek/rtl8365mb_vlan.h b/drivers/net/dsa/realtek/rtl8365mb_vlan.h
new file mode 100644
index 000000000000..ed63a0ec0d10
--- /dev/null
+++ b/drivers/net/dsa/realtek/rtl8365mb_vlan.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* VLAN configuration interface for the rtl8365mb switch family
+ *
+ * Copyright (C) 2022 Alvin Šipraga <alsi@bang-olufsen.dk>
+ *
+ */
+
+#ifndef _REALTEK_RTL8365MB_VLAN_H
+#define _REALTEK_RTL8365MB_VLAN_H
+
+#include <linux/types.h>
+
+#include "realtek.h"
+
+int rtl8365mb_vlan_4k_port_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack);
+int rtl8365mb_vlan_4k_port_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan);
+int rtl8365mb_vlan_pvid_port_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack);
+int rtl8365mb_vlan_pvid_port_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan);
+#endif /* _REALTEK_RTL8365MB_VLAN_H */
--
2.54.0
^ permalink raw reply related
* [net-next PATCH v3 4/8] net: dsa: realtek: rtl8365mb: add table lookup interface
From: Luiz Angelo Daros de Luca @ 2026-05-07 2:58 UTC (permalink / raw)
To: Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Simon Horman, Linus Walleij,
Alvin Šipraga, Yury Norov, Rasmus Villemoes, Russell King
Cc: netdev, linux-kernel, Luiz Angelo Daros de Luca
In-Reply-To: <20260506-realtek_forward-v3-0-1d87c5f85a3b@gmail.com>
From: Alvin Šipraga <alsi@bang-olufsen.dk>
Add a generic table lookup interface to centralize access to
the RTL8365MB internal tables.
This interface abstracts the low-level table access logic and
will be used by subsequent commits to implement FDB and VLAN
operations.
Co-developed-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
drivers/net/dsa/realtek/Makefile | 1 +
drivers/net/dsa/realtek/rtl8365mb_table.c | 214 ++++++++++++++++++++++++++++++
drivers/net/dsa/realtek/rtl8365mb_table.h | 131 ++++++++++++++++++
3 files changed, 346 insertions(+)
diff --git a/drivers/net/dsa/realtek/Makefile b/drivers/net/dsa/realtek/Makefile
index 3f986e04912f..99654c4c5a3d 100644
--- a/drivers/net/dsa/realtek/Makefile
+++ b/drivers/net/dsa/realtek/Makefile
@@ -17,3 +17,4 @@ rtl8366-objs += rtl8366rb-leds.o
endif
obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8365mb.o
rtl8365mb-objs := rtl8365mb_main.o \
+ rtl8365mb_table.o \
diff --git a/drivers/net/dsa/realtek/rtl8365mb_table.c b/drivers/net/dsa/realtek/rtl8365mb_table.c
new file mode 100644
index 000000000000..df312769b0be
--- /dev/null
+++ b/drivers/net/dsa/realtek/rtl8365mb_table.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Look-up table query interface for the rtl8365mb switch family
+ *
+ * Copyright (C) 2022 Alvin Šipraga <alsi@bang-olufsen.dk>
+ */
+
+#include "rtl8365mb_table.h"
+#include <linux/regmap.h>
+
+/* Table access control register */
+#define RTL8365MB_TABLE_CTRL_REG 0x0500
+/* Should be one of rtl8365mb_table enum members */
+#define RTL8365MB_TABLE_CTRL_TABLE_MASK GENMASK(2, 0)
+/* Should be one of rtl8365mb_table_op enum members */
+#define RTL8365MB_TABLE_CTRL_OP_MASK GENMASK(3, 3)
+/* Should be one of rtl8365mb_table_l2_method enum members */
+#define RTL8365MB_TABLE_CTRL_METHOD_MASK GENMASK(7, 4)
+/* NOTE: PORT_MASK is only 4 bit, which suggests that port-based
+ * look-up of the L2 table only works for physical port addresses
+ * 0~4. It could be that the Realtek driver is out-of-date and
+ * actually the mask is something like 0xFF00, but this is
+ * unconfirmed.
+ */
+#define RTL8365MB_TABLE_CTRL_PORT_MASK GENMASK(11, 8)
+
+/* Table access address register */
+#define RTL8365MB_TABLE_ACCESS_ADDR_REG 0x0501
+#define RTL8365MB_TABLE_ADDR_MASK GENMASK(13, 0)
+
+/* Table status register */
+#define RTL8365MB_TABLE_STATUS_REG 0x0502
+#define RTL8365MB_TABLE_STATUS_ADDRESS_MASK GENMASK(10, 0)
+/* set for L3, unset for L2 */
+#define RTL8365MB_TABLE_STATUS_ADDR_TYPE_MASK GENMASK(11, 11)
+#define RTL8365MB_TABLE_STATUS_HIT_STATUS_MASK GENMASK(12, 12)
+#define RTL8365MB_TABLE_STATUS_BUSY_FLAG_MASK GENMASK(13, 13)
+#define RTL8365MB_TABLE_STATUS_ADDRESS_EXT_MASK GENMASK(14, 14)
+
+/* Table read/write registers */
+#define RTL8365MB_TABLE_WRITE_BASE 0x0510
+#define RTL8365MB_TABLE_WRITE_REG(_x) \
+ (RTL8365MB_TABLE_WRITE_BASE + (_x))
+#define RTL8365MB_TABLE_READ_BASE 0x0520
+#define RTL8365MB_TABLE_READ_REG(_x) \
+ (RTL8365MB_TABLE_READ_BASE + (_x))
+#define RTL8365MB_TABLE_ENTRY_MAX_SIZE 10
+#define RTL8365MB_TABLE_10TH_DATA_MASK GENMASK(3, 0)
+#define RTL8365MB_TABLE_WRITE_10TH_REG \
+ RTL8365MB_TABLE_WRITE_REG(RTL8365MB_TABLE_ENTRY_MAX_SIZE - 1)
+
+static int rtl8365mb_table_poll_busy(struct realtek_priv *priv)
+{
+ u32 val;
+
+ return regmap_read_poll_timeout(priv->map_nolock,
+ RTL8365MB_TABLE_STATUS_REG, val,
+ !FIELD_GET(RTL8365MB_TABLE_STATUS_BUSY_FLAG_MASK, val),
+ 10, 100);
+}
+
+int rtl8365mb_table_query(struct realtek_priv *priv,
+ enum rtl8365mb_table table,
+ enum rtl8365mb_table_op op, u16 *addr,
+ enum rtl8365mb_table_l2_method method,
+ u16 port, u16 *data, size_t size)
+{
+ bool addr_as_input = true;
+ bool write_data = false;
+ int ret = 0;
+ u32 cmd;
+ u32 val;
+ u32 hit;
+
+ /* Prepare target table and operation (read or write) */
+ cmd = 0;
+ cmd |= FIELD_PREP(RTL8365MB_TABLE_CTRL_TABLE_MASK, table);
+ cmd |= FIELD_PREP(RTL8365MB_TABLE_CTRL_OP_MASK, op);
+ if (op == RTL8365MB_TABLE_OP_READ && table == RTL8365MB_TABLE_L2) {
+ cmd |= FIELD_PREP(RTL8365MB_TABLE_CTRL_METHOD_MASK, method);
+ switch (method) {
+ case RTL8365MB_TABLE_L2_METHOD_MAC:
+ /*
+ * Method MAC requires as input the same L2 table format
+ * you'll get as result. However, it might only use mac
+ * address and FID/VID fields.
+ */
+ write_data = true;
+
+ /* METHOD_MAC does not use addr as input, but may return
+ * the matched index.
+ */
+ addr_as_input = false;
+
+ break;
+ case RTL8365MB_TABLE_L2_METHOD_ADDR:
+ case RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT:
+ case RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC:
+ case RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC:
+ break;
+ case RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT:
+ cmd |= FIELD_PREP(RTL8365MB_TABLE_CTRL_PORT_MASK, port);
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else if (op == RTL8365MB_TABLE_OP_WRITE) {
+ write_data = true;
+
+ /* Writing to L2 does not use addr as input, as the table index
+ * is derived from key fields.
+ */
+ if (table == RTL8365MB_TABLE_L2)
+ addr_as_input = false;
+ }
+
+ /* To prevent concurrent access to the look-up tables, take the regmap
+ * lock manually and access via the map_nolock regmap.
+ */
+ mutex_lock(&priv->map_lock);
+
+ /* Write entry data if writing to the table (or L2_METHOD_MAC) */
+ if (write_data) {
+ /* bulk write data up to 9th byte */
+ ret = regmap_bulk_write(priv->map_nolock,
+ RTL8365MB_TABLE_WRITE_BASE,
+ data,
+ min_t(size_t, size,
+ RTL8365MB_TABLE_ENTRY_MAX_SIZE -
+ 1));
+ if (ret)
+ goto out;
+
+ /* 10th register uses only 4 less significant bits */
+ if (size == RTL8365MB_TABLE_ENTRY_MAX_SIZE) {
+ val = FIELD_PREP(RTL8365MB_TABLE_10TH_DATA_MASK,
+ data[size - 1]);
+ ret = regmap_update_bits(priv->map_nolock,
+ RTL8365MB_TABLE_WRITE_10TH_REG,
+ RTL8365MB_TABLE_10TH_DATA_MASK,
+ val);
+ }
+
+ if (ret)
+ goto out;
+ }
+
+ /* Write address (if needed) */
+ if (addr_as_input) {
+ ret = regmap_write(priv->map_nolock,
+ RTL8365MB_TABLE_ACCESS_ADDR_REG,
+ FIELD_PREP(RTL8365MB_TABLE_ADDR_MASK,
+ *addr));
+ if (ret)
+ goto out;
+ }
+
+ /* Execute */
+ ret = regmap_write(priv->map_nolock, RTL8365MB_TABLE_CTRL_REG, cmd);
+ if (ret)
+ goto out;
+
+ /* Poll for completion */
+ ret = rtl8365mb_table_poll_busy(priv);
+ if (ret)
+ goto out;
+
+ /* For both reads and writes to the L2 table, check status */
+ if (table == RTL8365MB_TABLE_L2) {
+ ret = regmap_read(priv->map_nolock, RTL8365MB_TABLE_STATUS_REG,
+ &val);
+ if (ret)
+ goto out;
+
+ /* Did the query find an entry? */
+ hit = FIELD_GET(RTL8365MB_TABLE_STATUS_HIT_STATUS_MASK, val);
+ if (!hit) {
+ ret = -ENOENT;
+ goto out;
+ }
+
+ /* If so, extract the address */
+ *addr = 0;
+ *addr |= FIELD_GET(RTL8365MB_TABLE_STATUS_ADDRESS_MASK, val);
+ *addr |= FIELD_GET(RTL8365MB_TABLE_STATUS_ADDRESS_EXT_MASK, val)
+ << 11;
+ /* only set if it is a L3 address */
+ *addr |= FIELD_GET(RTL8365MB_TABLE_STATUS_ADDR_TYPE_MASK, val)
+ << 12;
+ }
+
+ /* Finally, get the table entry if we were reading */
+ if (op == RTL8365MB_TABLE_OP_READ) {
+ ret = regmap_bulk_read(priv->map_nolock,
+ RTL8365MB_TABLE_READ_BASE,
+ data, size);
+
+ /* For the biggest table entries, the uppermost table
+ * entry register has space for only one nibble. Mask
+ * out the remainder bits. Empirically I saw nothing
+ * wrong with omitting this mask, but it may prevent
+ * unwanted behaviour. FYI.
+ */
+ if (size == RTL8365MB_TABLE_ENTRY_MAX_SIZE) {
+ val = FIELD_GET(RTL8365MB_TABLE_10TH_DATA_MASK,
+ data[size - 1]);
+ data[size - 1] = val;
+ }
+ }
+
+out:
+ mutex_unlock(&priv->map_lock);
+
+ return ret;
+}
diff --git a/drivers/net/dsa/realtek/rtl8365mb_table.h b/drivers/net/dsa/realtek/rtl8365mb_table.h
new file mode 100644
index 000000000000..413af4f9759c
--- /dev/null
+++ b/drivers/net/dsa/realtek/rtl8365mb_table.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Look-up table query interface for the rtl8365mb switch family
+ *
+ * Copyright (C) 2022 Alvin Šipraga <alsi@bang-olufsen.dk>
+ */
+
+#ifndef _REALTEK_RTL8365MB_TABLE_H
+#define _REALTEK_RTL8365MB_TABLE_H
+
+#include <linux/if_ether.h>
+#include <linux/types.h>
+
+#include "realtek.h"
+
+/**
+ * enum rtl8365mb_table - available switch tables
+ * @RTL8365MB_TABLE_ACL_RULE: ACL rules
+ * @RTL8365MB_TABLE_ACL_ACTION: ACL actions
+ * @RTL8365MB_TABLE_CVLAN: VLAN4k configurations
+ * @RTL8365MB_TABLE_L2: filtering database (2K hash table)
+ * @RTL8365MB_TABLE_IGMP_GROUP: IGMP group database (readonly)
+ *
+ * NOTE: Don't change the enum values. They must concur with the field
+ * described by @RTL8365MB_TABLE_CTRL_TABLE_MASK.
+ */
+enum rtl8365mb_table {
+ RTL8365MB_TABLE_ACL_RULE = 1,
+ RTL8365MB_TABLE_ACL_ACTION = 2,
+ RTL8365MB_TABLE_CVLAN = 3,
+ RTL8365MB_TABLE_L2 = 4,
+ RTL8365MB_TABLE_IGMP_GROUP = 5,
+};
+
+/**
+ * enum rtl8365mb_table_op - table query operation
+ * @RTL8365MB_TABLE_OP_READ: read an entry from the target table
+ * @RTL8365MB_TABLE_OP_WRITE: write an entry to the target table
+ *
+ * NOTE: Don't change the enum values. They must concur with the field
+ * described by @RTL8365MB_TABLE_CTRL_OP_MASK.
+ */
+enum rtl8365mb_table_op {
+ RTL8365MB_TABLE_OP_READ = 0,
+ RTL8365MB_TABLE_OP_WRITE = 1,
+};
+
+/**
+ * enum rtl8365mb_table_l2_method - look-up method for read queries of L2 table
+ * @RTL8365MB_TABLE_L2_METHOD_MAC: look-up by source MAC address and FID (or
+ * VID)
+ * @RTL8365MB_TABLE_L2_METHOD_ADDR: look-up by entry address
+ * @RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT: look-up next entry starting from the
+ * supplied address
+ * @RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC: same as ADDR_NEXT but search only
+ * unicast addresses
+ * @RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC: same as ADDR_NEXT but search only
+ * multicast addresses
+ * @RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT: same as ADDR_NEXT_UC but
+ * search only entries with matching source port
+ *
+ * NOTE: Don't change the enum values. They must concur with the field
+ * described by @RTL8365MB_TABLE_CTRL_METHOD_MASK
+ */
+enum rtl8365mb_table_l2_method {
+ RTL8365MB_TABLE_L2_METHOD_MAC = 0,
+ RTL8365MB_TABLE_L2_METHOD_ADDR = 1,
+ RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT = 2,
+ RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC = 3,
+ RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC = 4,
+ /*
+ * RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC_L3 = 5,
+ * RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_MC_L2L3 = 6,
+ */
+ RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT = 7,
+};
+
+/**
+ * rtl8365mb_table_query() - read from or write to a switch table
+ * @priv: driver context
+ * @table: target table, see &enum rtl8365mb_table
+ * @op: read or write operation, see &enum rtl8365mb_table_op
+ * @addr: table address. For indexed tables, this selects the entry to access.
+ * For L2 read queries, it is ignored as input for MAC-based lookup
+ * methods and used as input for address-based lookup methods. On
+ * successful L2 queries, it is updated with the matched entry address.
+ * @method: L2 table lookup method, see &enum rtl8365mb_table_l2_method.
+ * Ignored for non-L2 tables.
+ * @port: for L2 read queries using method
+ * %RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT, restrict the search
+ * to entries associated with this source port. Ignored otherwise.
+ * @data: data buffer used to read from or write to the table. For L2 MAC
+ * lookups, this buffer provides the lookup key and receives the
+ * matched entry contents on success.
+ * @size: size of @data in 16-bit words
+ *
+ * This function provides unified access to the internal tables of the switch.
+ * All tables except the L2 table are simple indexed tables, where @addr
+ * selects the entry and @op determines whether the access is a read or a
+ * write operation.
+ *
+ * The L2 table is a hash table and supports multiple lookup methods. For
+ * %RTL8365MB_TABLE_L2_METHOD_MAC, an entry is searched based on the MAC
+ * address and FID/VID fields provided in @data, using the same format as
+ * an L2 table entry. Address-based methods either read a specific entry
+ * (%RTL8365MB_TABLE_L2_METHOD_ADDR) or iterate over valid entries starting
+ * from @addr (%RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT and variants). When using
+ * %RTL8365MB_TABLE_L2_METHOD_ADDR_NEXT_UC_PORT, only entries associated with
+ * the specified @port are considered.
+ *
+ * On successful L2 lookups, @addr is updated with the matched table address
+ * and @data contains the corresponding table entry. If no matching entry
+ * is found, -ENOENT is returned.
+ *
+ * The contents of @data are used as input when writing to tables or when
+ * specifying the lookup key for L2 MAC searches, and as output for all
+ * successful read operations. If an error occurs, the contents of @addr
+ * and @data are undefined.
+ *
+ * @size must match the size of the target table entry, expressed in 16-bit
+ * words. This function only validates that it is non-zero and fits in the
+ * available register space.
+ *
+ * Return: 0 on success, or a negative error code on failure.
+ */
+int rtl8365mb_table_query(struct realtek_priv *priv,
+ enum rtl8365mb_table table,
+ enum rtl8365mb_table_op op, u16 *addr,
+ enum rtl8365mb_table_l2_method method,
+ u16 port, u16 *data, size_t size);
+
+#endif /* _REALTEK_RTL8365MB_TABLE_H */
--
2.54.0
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