* Re: [PATCH net-next] gtp: annotate PDP lookups under RTNL
From: Simon Horman @ 2026-07-08 10:35 UTC (permalink / raw)
To: Pablo Neira Ayuso
Cc: Runyu Xiao, laforge, andrew+netdev, davem, edumazet, kuba, pabeni,
osmocom-net-gprs, netdev, linux-kernel, jianhao.xu
In-Reply-To: <ak0SYEOvw6K_8C_w@chamomile>
On Tue, Jul 07, 2026 at 04:51:12PM +0200, Pablo Neira Ayuso wrote:
> Hi Simon,
>
> On Tue, Jul 07, 2026 at 03:28:20PM +0100, Simon Horman wrote:
> > On Wed, Jul 01, 2026 at 08:39:25PM +0800, Runyu Xiao wrote:
> > > The GTP PDP lookup helpers are shared by RCU-protected data and report
> > > paths and RTNL-protected control paths such as gtp_genl_new_pdp(). The
> > > helpers walk RCU hlists, but they do not currently pass the RTNL
> > > condition for the control-path lookups.
> > >
> > > Pass lockdep_rtnl_is_held() to the PDP hlist iterators. Existing
> > > RCU-reader callers remain valid because the RCU-list macros also accept
> > > an active RCU read-side section; the added condition only documents the
> > > non-RCU protection already used by RTNL control paths.
> > >
> > > This was found by our static analysis tool and then manually reviewed
> > > against the current tree. The dynamic triage evidence is a
> > > target-matched CONFIG_PROVE_RCU_LIST warning; the change is limited
> > > to documenting the existing protection contract.
> > >
> > > This is a lockdep annotation cleanup. It does not change PDP lifetime or
> > > hash updates.
> > >
> > > Signed-off-by: Runyu Xiao <runyu.xiao@seu.edu.cn>
> >
> > Reviewed-by: Simon Horman <horms@kernel.org>
> >
> > There is an AI-generated review of this patch available on sashko.dev.
> > While I don't believe that the issues raised there should impede progress
> > of this patch you may want to look into them as possible follow-up.
>
> This patch refers to the rtnl_lock, but it is the genetlink mutex that
> protects updates on the PDP context list.
>
> Then, from packet path, rcu lookups are performed.
>
> I think this patch is not correct.
Hi Pablo,
Of course you are correct.
Sorry for not realising this earlier.
^ permalink raw reply
* Re: [PATCH nf-next v4 5/6] net: netfilter: Add SIT tunnel flowtable acceleration
From: Lorenzo Bianconi @ 2026-07-08 10:33 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Felix Fietkau, Matthias Brugger,
AngeloGioacchino Del Regno, Simon Horman, David Ahern,
Ido Schimmel, Pablo Neira Ayuso, Florian Westphal, Phil Sutter,
Shuah Khan
Cc: linux-arm-kernel, linux-mediatek, netdev, netfilter-devel,
coreteam, linux-kselftest
In-Reply-To: <20260703-b4-flowtable-sw-accel-ip6ip-v4-5-00398cd12382@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 20415 bytes --]
commenting on sashiko's report:
https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260703-b4-flowtable-sw-accel-ip6ip-v4-0-00398cd12382%40kernel.org
> Introduce sw flowtable acceleration for the TX/RX paths of
> SIT tunnels, relying on the netfilter flowtable infrastructure.
> The feature can be tested with a forwarding scenario between two
> NICs (eth0 and eth1), where a SIT tunnel is used to reach a remote
> site via eth1 as the underlay device:
>
> ETH0 -- TUN0 <==> ETH1 -- [IP network] -- TUN1 (192.168.2.2)
>
> [IP configuration]
>
> 6: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc noqueue state UP group default qlen 1000
> link/ether 00:00:22:33:11:55 brd ff:ff:ff:ff:ff:ff
> inet6 2001:db8:1::2/64 scope global nodad
> valid_lft forever preferred_lft forever
> 7: eth1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc noqueue state UP group default qlen 1000
> link/ether 00:11:22:33:11:55 brd ff:ff:ff:ff:ff:ff
> inet 192.168.2.1/24 scope global eth1
> valid_lft forever preferred_lft forever
> 8: tun0@NONE: <POINTOPOINT,NOARP,UP,LOWER_UP> mtu 1480 qdisc noqueue state UNKNOWN group default qlen 1000
> link/sit 192.168.2.1 peer 192.168.2.2
> inet6 2001:db8:200::1/64 scope global nodad
> valid_lft forever preferred_lft forever
>
> $ ip route show
> 192.168.2.0/24 dev eth1 proto kernel scope link src 192.168.2.1
>
> $ ip -6 route show
> 2001:db8:1::/64 dev eth0 proto kernel metric 256 pref medium
> 2001:db8:200::/64 dev tun0 proto kernel metric 256 pref medium
> default via 2001:db8:200::2 dev tun0 metric 1024 pref medium
>
> $ nft list ruleset
> table inet filter {
> flowtable ft {
> hook ingress priority filter
> devices = { eth0, eth1 }
> }
>
> chain forward {
> type filter hook forward priority filter; policy accept;
> meta l4proto { tcp, udp } flow add @ft
> }
> }
>
> When reproducing this scenario using veth interfaces, the following
> results were observed:
>
> - TCP stream received from SIT tunnel:
> - net-next (baseline): ~118 Gbps
> - net-next + SIT flowtable support: ~148 Gbps
>
> - TCP stream transmitted to SIT tunnel:
> - net-next (baseline): ~131 Gbps
> - net-next + SIT flowtable support: ~147 Gbps
>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
> net/ipv6/sit.c | 26 ++++
> net/netfilter/nf_flow_table_ip.c | 290 +++++++++++++++++++++------------------
> 2 files changed, 182 insertions(+), 134 deletions(-)
>
> diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c
> index a38b24fb8384..0ac6f7839878 100644
> --- a/net/ipv6/sit.c
> +++ b/net/ipv6/sit.c
> @@ -1365,6 +1365,31 @@ ipip6_tunnel_ctl(struct net_device *dev, struct ip_tunnel_parm_kern *p,
> }
> }
>
> +static int ipip6_tunnel_fill_forward_path(struct net_device_path_ctx *ctx,
> + struct net_device_path *path)
> +{
> + struct ip_tunnel *tunnel = netdev_priv(ctx->dev);
> + const struct iphdr *tiph = &tunnel->parms.iph;
> + struct rtable *rt;
> +
> + rt = ip_route_output(dev_net(ctx->dev), tiph->daddr, 0, 0, 0,
> + RT_SCOPE_UNIVERSE);
> + if (IS_ERR(rt))
> + return PTR_ERR(rt);
> +
> + path->type = DEV_PATH_TUN;
> + path->tun.src_v4.s_addr = tiph->saddr;
> + path->tun.dst_v4.s_addr = tiph->daddr;
> + path->tun.l3_proto = IPPROTO_IPV6;
> + path->tun.encap_proto = AF_INET;
> + path->dev = ctx->dev;
> +
> + ctx->dev = rt->dst.dev;
> + ip_rt_put(rt);
> +
> + return 0;
- Is tiph->daddr always meaningful here? SIT supports several modes where
tunnel->parms.iph.daddr is either zero or a placeholder and the real
outer IPv4 endpoint is derived per-packet from the inner IPv6
destination:
- ISATAP (dev->priv_flags & IFF_ISATAP), resolved by
ipip6_tunnel_dst_find(..., true)
- 6rd / 6to4, resolved per-packet via try_6rd() / check_6rd()
- NBMA / point-to-multipoint (tiph->daddr == 0), resolved by
ipip6_tunnel_dst_find(..., false)
In these cases ip_route_output(daddr=0) will fall through to the default
route, ctx->dev gets resolved to the wrong underlay, and every
accelerated packet is encapsulated toward 0.0.0.0 (or a fixed unicast
that does not match the flow) regardless of the actual inner
destination.
Compare ip6_tnl_fill_forward_path() which returns -EOPNOTSUPP when it
detects unsupported tunnel features; would something equivalent make
sense here, at least for !tiph->daddr, IFF_ISATAP, and 6rd configured
tunnels?
Does this path also need to consider tunnel->encap? SIT supports FOU
and GUE via ip_tunnel_encap(skb, &tunnel->encap, &protocol, &fl4) in the
slow path, and there is no rejection here when tunnel->encap.type is
not TUNNEL_ENCAP_NONE. Once a SIT tunnel that was configured with
encap fou/gue is attached to a flowtable, the fast path pushes a plain
IPv4 outer header via nf_flow_tunnel_ipip_push() and skips the FOU/GUE
encapsulation entirely. ip6_tnl_fill_forward_path() has an
-EOPNOTSUPP guard for its own analogous case (encaplimit); would a
similar guard work here?
The slow path in ipip6_tunnel_xmit() uses flowi4_init_output() with
tunnel->parms.link (oif), tunnel->fwmark, tos & INET_DSCP_MASK, and
tiph->saddr:
flowi4_init_output(&fl4, tunnel->parms.link, tunnel->fwmark,
tos & INET_DSCP_MASK, RT_SCOPE_UNIVERSE,
IPPROTO_IPV6, 0, dst, tiph->saddr, ...);
The call above passes 0 for saddr, dscp and oif and does not pass a
fwmark. For a SIT tunnel bound to a specific link, using fwmark-based
policy routing, or configured with a source address, can the fast-path
route lookup diverge from what the slow path would pick, so that
rt->dst.dev (which becomes ctx->dev and drives the flowtable egress)
ends up on a different underlay device than slow-path packets on the
same tunnel?
- I will fix it in v5.
- Is it safe to hardcode IPPROTO_IPV6 here? sit_tunnel_xmit() dispatches
on skb->protocol and legitimately supports ETH_P_IP (IPv4-in-IPv4 via
IPPROTO_IPIP) and, if CONFIG_MPLS is set, ETH_P_MPLS_UC (IPPROTO_MPLS);
ipip6_valid_ip_proto() also accepts both on the receive side.
If flowtable acceleration engages for a flow whose inner payload is
IPv4 or MPLS through a SIT device, the outer iph->protocol that
nf_flow_tunnel_ipip_push() synthesises from tuple->tun.l3_proto will be
IPPROTO_IPV6, and the receiver will drop or misparse the packet.
ip6_tnl_fill_forward_path() selects l3_proto from ctx->ether_type
(ETH_P_IP => IPPROTO_IPIP, else IPPROTO_IPV6) — would something similar
be appropriate here?
- I will fix it in v5.
Regards,
Lorenzo
> +}
> +
> static int
> ipip6_tunnel_siocdevprivate(struct net_device *dev, struct ifreq *ifr,
> void __user *data, int cmd)
> @@ -1401,6 +1426,7 @@ static const struct net_device_ops ipip6_netdev_ops = {
> .ndo_siocdevprivate = ipip6_tunnel_siocdevprivate,
> .ndo_get_iflink = ip_tunnel_get_iflink,
> .ndo_tunnel_ctl = ipip6_tunnel_ctl,
> + .ndo_fill_forward_path = ipip6_tunnel_fill_forward_path,
> };
>
> static void ipip6_dev_free(struct net_device *dev)
> diff --git a/net/netfilter/nf_flow_table_ip.c b/net/netfilter/nf_flow_table_ip.c
> index 4b6de16bd4f3..f02e71ae5448 100644
> --- a/net/netfilter/nf_flow_table_ip.c
> +++ b/net/netfilter/nf_flow_table_ip.c
> @@ -338,7 +338,7 @@ static bool nf_flow_ip4_tunnel_proto(struct nf_flowtable_ctx *ctx,
> if (iph->ttl <= 1)
> return false;
>
> - if (iph->protocol == IPPROTO_IPIP) {
> + if (iph->protocol == IPPROTO_IPIP || iph->protocol == IPPROTO_IPV6) {
> ctx->tun.proto = iph->protocol;
> ctx->tun.hdr_size = size;
> ctx->offset += ctx->tun.hdr_size;
> @@ -464,21 +464,6 @@ static void nf_flow_encap_pop(struct nf_flowtable_ctx *ctx,
> nf_flow_ip_tunnel_pop(ctx, skb);
> }
>
> -static struct flow_offload_tuple_rhash *
> -nf_flow_offload_lookup(struct nf_flowtable_ctx *ctx,
> - struct nf_flowtable *flow_table, struct sk_buff *skb)
> -{
> - struct flow_offload_tuple tuple = {};
> -
> - if (!nf_flow_skb_encap_protocol(ctx, skb, htons(ETH_P_IP)))
> - return NULL;
> -
> - if (nf_flow_tuple_ip(ctx, skb, &tuple) < 0)
> - return NULL;
> -
> - return flow_offload_lookup(flow_table, &tuple);
> -}
> -
> static int nf_flow_offload_forward(struct nf_flowtable_ctx *ctx,
> struct nf_flowtable *flow_table,
> struct flow_offload_tuple_rhash *tuplehash,
> @@ -606,19 +591,33 @@ static int nf_flow_tunnel_ipip_push(struct net *net, struct sk_buff *skb,
> struct flow_offload_tuple *tuple,
> __be32 *ip_daddr)
> {
> - struct iphdr *iph = (struct iphdr *)skb_network_header(skb);
> struct rtable *rt = dst_rtable(tuple->dst_cache);
> - u8 tos = iph->tos, ttl = iph->ttl;
> - __be16 frag_off = iph->frag_off;
> - u32 headroom = sizeof(*iph);
> + __be16 frag_off = 0;
> + struct iphdr *iph;
> + u8 tos = 0, ttl;
> + u32 headroom;
> int err;
>
> + if (tuple->tun.l3_proto == IPPROTO_IPV6) {
> + struct ipv6hdr *ip6h;
> +
> + ip6h = (struct ipv6hdr *)skb_network_header(skb);
> + tos = ipv6_get_dsfield(ip6h);
> + ttl = ip6h->hop_limit;
> + } else {
> + iph = (struct iphdr *)skb_network_header(skb);
> + frag_off = iph->frag_off;
> + tos = iph->tos;
> + ttl = iph->ttl;
> + }
> +
> err = iptunnel_handle_offloads(skb, SKB_GSO_IPXIP4);
> if (err)
> return err;
>
> - skb_set_inner_ipproto(skb, IPPROTO_IPIP);
> - headroom += LL_RESERVED_SPACE(rt->dst.dev) + rt->dst.header_len;
> + skb_set_inner_ipproto(skb, tuple->tun.l3_proto);
> + headroom = sizeof(*iph) + LL_RESERVED_SPACE(rt->dst.dev) +
> + rt->dst.header_len;
> err = skb_cow_head(skb, headroom);
> if (err)
> return err;
> @@ -629,6 +628,7 @@ static int nf_flow_tunnel_ipip_push(struct net *net, struct sk_buff *skb,
> /* Push down and install the IP header. */
> skb_push(skb, sizeof(*iph));
> skb_reset_network_header(skb);
> + skb->protocol = htons(ETH_P_IP);
>
> iph = ip_hdr(skb);
> iph->version = 4;
> @@ -723,16 +723,6 @@ static int nf_flow_tunnel_push(struct net *net, struct sk_buff *skb,
> }
> }
>
> -static int nf_flow_tunnel_v6_push(struct net *net, struct sk_buff *skb,
> - struct flow_offload_tuple *tuple,
> - struct in6_addr **ip6_daddr)
> -{
> - if (tuple->tun_num)
> - return nf_flow_tunnel_ip6ip6_push(net, skb, tuple, ip6_daddr);
> -
> - return 0;
> -}
> -
> static int nf_flow_encap_push(struct sk_buff *skb,
> struct flow_offload_tuple *tuple,
> struct net_device *outdev)
> @@ -830,103 +820,6 @@ static unsigned int nf_flow_queue_xmit(struct net *net, struct sk_buff *skb,
> return NF_STOLEN;
> }
>
> -unsigned int
> -nf_flow_offload_ip_hook(void *priv, struct sk_buff *skb,
> - const struct nf_hook_state *state)
> -{
> - struct flow_offload_tuple_rhash *tuplehash;
> - struct nf_flowtable *flow_table = priv;
> - struct flow_offload_tuple *other_tuple;
> - enum flow_offload_tuple_dir dir;
> - struct nf_flowtable_ctx ctx = {
> - .in = state->in,
> - };
> - struct nf_flow_xmit xmit = {};
> - struct in6_addr *ip6_daddr;
> - struct flow_offload *flow;
> - struct neighbour *neigh;
> - struct rtable *rt;
> - __be32 ip_daddr;
> - int ret;
> -
> - tuplehash = nf_flow_offload_lookup(&ctx, flow_table, skb);
> - if (!tuplehash)
> - return NF_ACCEPT;
> -
> - ret = nf_flow_offload_forward(&ctx, flow_table, tuplehash, skb);
> - if (ret < 0)
> - return NF_DROP;
> - else if (ret == 0)
> - return NF_ACCEPT;
> -
> - if (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) {
> - rt = dst_rtable(tuplehash->tuple.dst_cache);
> - memset(skb->cb, 0, sizeof(struct inet_skb_parm));
> - IPCB(skb)->iif = skb->dev->ifindex;
> - IPCB(skb)->flags = IPSKB_FORWARDED;
> - return nf_flow_xmit_xfrm(skb, state, &rt->dst);
> - }
> -
> - dir = tuplehash->tuple.dir;
> - flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);
> - other_tuple = &flow->tuplehash[!dir].tuple;
> - ip_daddr = other_tuple->src_v4.s_addr;
> -
> - if (nf_flow_tunnel_push(state->net, skb, other_tuple, &ip_daddr,
> - &ip6_daddr) < 0)
> - return NF_DROP;
> -
> - switch (tuplehash->tuple.xmit_type) {
> - case FLOW_OFFLOAD_XMIT_NEIGH: {
> - struct dst_entry *dst;
> -
> - xmit.outdev = dev_get_by_index_rcu(state->net, tuplehash->tuple.ifidx);
> - if (!xmit.outdev) {
> - flow_offload_teardown(flow);
> - return NF_DROP;
> - }
> - if (other_tuple->tun.encap_proto == AF_INET6 ||
> - ctx.tun.proto == IPPROTO_IPV6) {
> - struct rt6_info *rt6;
> -
> - rt6 = dst_rt6_info(tuplehash->tuple.dst_cache);
> - neigh = ip_neigh_gw6(rt6->dst.dev,
> - rt6_nexthop(rt6, ip6_daddr));
> - dst = &rt6->dst;
> - } else {
> - rt = dst_rtable(tuplehash->tuple.dst_cache);
> - neigh = ip_neigh_gw4(rt->dst.dev,
> - rt_nexthop(rt, ip_daddr));
> - dst = &rt->dst;
> - }
> - if (IS_ERR(neigh)) {
> - flow_offload_teardown(flow);
> - return NF_DROP;
> - }
> - xmit.dest = neigh->ha;
> - skb_dst_set_noref(skb, dst);
> - break;
> - }
> - case FLOW_OFFLOAD_XMIT_DIRECT:
> - xmit.outdev = dev_get_by_index_rcu(state->net, tuplehash->tuple.out.ifidx);
> - if (!xmit.outdev) {
> - flow_offload_teardown(flow);
> - return NF_DROP;
> - }
> - xmit.dest = tuplehash->tuple.out.h_dest;
> - xmit.source = tuplehash->tuple.out.h_source;
> - break;
> - default:
> - WARN_ON_ONCE(1);
> - return NF_DROP;
> - }
> - xmit.tuple = other_tuple;
> - xmit.needs_gso_segment = tuplehash->tuple.needs_gso_segment;
> -
> - return nf_flow_queue_xmit(state->net, skb, &xmit);
> -}
> -EXPORT_SYMBOL_GPL(nf_flow_offload_ip_hook);
> -
> static void nf_flow_nat_ipv6_tcp(struct sk_buff *skb, unsigned int thoff,
> struct in6_addr *addr,
> struct in6_addr *new_addr,
> @@ -1111,8 +1004,16 @@ static int nf_flow_offload_ipv6_forward(struct nf_flowtable_ctx *ctx,
> flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);
>
> mtu = flow->tuplehash[dir].tuple.mtu + ctx->offset;
> - if (flow->tuplehash[!dir].tuple.tun_num)
> + switch (flow->tuplehash[!dir].tuple.tun.encap_proto) {
> + case AF_INET:
> + mtu -= sizeof(struct iphdr);
> + break;
> + case AF_INET6:
> mtu -= sizeof(*ip6h);
> + break;
> + default:
> + break;
> + }
>
> if (unlikely(nf_flow_exceeds_mtu(skb, mtu)))
> return 0;
> @@ -1146,6 +1047,25 @@ static int nf_flow_offload_ipv6_forward(struct nf_flowtable_ctx *ctx,
> return 1;
> }
>
> +static struct flow_offload_tuple_rhash *
> +nf_flow_offload_lookup(struct nf_flowtable_ctx *ctx,
> + struct nf_flowtable *flow_table, struct sk_buff *skb)
> +{
> + struct flow_offload_tuple tuple = {};
> +
> + if (!nf_flow_skb_encap_protocol(ctx, skb, htons(ETH_P_IP)))
> + return NULL;
> +
> + if (ctx->tun.proto == IPPROTO_IPV6) {
> + if (nf_flow_tuple_ipv6(ctx, skb, &tuple) < 0)
> + return NULL;
> + } else if (nf_flow_tuple_ip(ctx, skb, &tuple) < 0) {
> + return NULL;
> + }
> +
> + return flow_offload_lookup(flow_table, &tuple);
> +}
> +
> static struct flow_offload_tuple_rhash *
> nf_flow_offload_ipv6_lookup(struct nf_flowtable_ctx *ctx,
> struct nf_flowtable *flow_table,
> @@ -1166,6 +1086,108 @@ nf_flow_offload_ipv6_lookup(struct nf_flowtable_ctx *ctx,
> return flow_offload_lookup(flow_table, &tuple);
> }
>
> +unsigned int
> +nf_flow_offload_ip_hook(void *priv, struct sk_buff *skb,
> + const struct nf_hook_state *state)
> +{
> + struct flow_offload_tuple_rhash *tuplehash;
> + struct nf_flowtable *flow_table = priv;
> + struct flow_offload_tuple *other_tuple;
> + enum flow_offload_tuple_dir dir;
> + struct nf_flowtable_ctx ctx = {
> + .in = state->in,
> + };
> + struct nf_flow_xmit xmit = {};
> + struct in6_addr *ip6_daddr;
> + struct flow_offload *flow;
> + struct neighbour *neigh;
> + struct rtable *rt;
> + __be32 ip_daddr;
> + int ret;
> +
> + tuplehash = nf_flow_offload_lookup(&ctx, flow_table, skb);
> + if (!tuplehash)
> + return NF_ACCEPT;
> +
> + if (ctx.tun.proto == IPPROTO_IPV6)
> + ret = nf_flow_offload_ipv6_forward(&ctx, flow_table, tuplehash,
> + skb);
> + else
> + ret = nf_flow_offload_forward(&ctx, flow_table, tuplehash, skb);
> + if (ret < 0)
> + return NF_DROP;
> + else if (ret == 0)
> + return NF_ACCEPT;
> +
> + if (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) {
> + rt = dst_rtable(tuplehash->tuple.dst_cache);
> + memset(skb->cb, 0, sizeof(struct inet_skb_parm));
> + IPCB(skb)->iif = skb->dev->ifindex;
> + IPCB(skb)->flags = IPSKB_FORWARDED;
> + return nf_flow_xmit_xfrm(skb, state, &rt->dst);
> + }
> +
> + dir = tuplehash->tuple.dir;
> + flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);
> + other_tuple = &flow->tuplehash[!dir].tuple;
> + ip_daddr = other_tuple->src_v4.s_addr;
> + ip6_daddr = &other_tuple->src_v6;
> +
> + if (nf_flow_tunnel_push(state->net, skb, other_tuple, &ip_daddr,
> + &ip6_daddr) < 0)
> + return NF_DROP;
> +
> + switch (tuplehash->tuple.xmit_type) {
> + case FLOW_OFFLOAD_XMIT_NEIGH: {
> + struct dst_entry *dst;
> +
> + xmit.outdev = dev_get_by_index_rcu(state->net, tuplehash->tuple.ifidx);
> + if (!xmit.outdev) {
> + flow_offload_teardown(flow);
> + return NF_DROP;
> + }
> + if (other_tuple->tun.encap_proto == AF_INET6 ||
> + ctx.tun.proto == IPPROTO_IPV6) {
> + struct rt6_info *rt6;
> +
> + rt6 = dst_rt6_info(tuplehash->tuple.dst_cache);
> + neigh = ip_neigh_gw6(rt6->dst.dev,
> + rt6_nexthop(rt6, ip6_daddr));
> + dst = &rt6->dst;
> + } else {
> + rt = dst_rtable(tuplehash->tuple.dst_cache);
> + neigh = ip_neigh_gw4(rt->dst.dev,
> + rt_nexthop(rt, ip_daddr));
> + dst = &rt->dst;
> + }
> + if (IS_ERR(neigh)) {
> + flow_offload_teardown(flow);
> + return NF_DROP;
> + }
> + xmit.dest = neigh->ha;
> + skb_dst_set_noref(skb, dst);
> + break;
> + }
> + case FLOW_OFFLOAD_XMIT_DIRECT:
> + xmit.outdev = dev_get_by_index_rcu(state->net, tuplehash->tuple.out.ifidx);
> + if (!xmit.outdev) {
> + flow_offload_teardown(flow);
> + return NF_DROP;
> + }
> + xmit.dest = tuplehash->tuple.out.h_dest;
> + xmit.source = tuplehash->tuple.out.h_source;
> + break;
> + default:
> + WARN_ON_ONCE(1);
> + return NF_DROP;
> + }
> + xmit.tuple = other_tuple;
> + xmit.needs_gso_segment = tuplehash->tuple.needs_gso_segment;
> +
> + return nf_flow_queue_xmit(state->net, skb, &xmit);
> +}
> +EXPORT_SYMBOL_GPL(nf_flow_offload_ip_hook);
> +
> unsigned int
> nf_flow_offload_ipv6_hook(void *priv, struct sk_buff *skb,
> const struct nf_hook_state *state)
> @@ -1182,6 +1204,7 @@ nf_flow_offload_ipv6_hook(void *priv, struct sk_buff *skb,
> struct flow_offload *flow;
> struct neighbour *neigh;
> struct rt6_info *rt;
> + __be32 ip_daddr;
> int ret;
>
> tuplehash = nf_flow_offload_ipv6_lookup(&ctx, flow_table, skb);
> @@ -1209,10 +1232,11 @@ nf_flow_offload_ipv6_hook(void *priv, struct sk_buff *skb,
> dir = tuplehash->tuple.dir;
> flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);
> other_tuple = &flow->tuplehash[!dir].tuple;
> + ip_daddr = other_tuple->src_v4.s_addr;
> ip6_daddr = &other_tuple->src_v6;
>
> - if (nf_flow_tunnel_v6_push(state->net, skb, other_tuple,
> - &ip6_daddr) < 0)
> + if (nf_flow_tunnel_push(state->net, skb, other_tuple, &ip_daddr,
> + &ip6_daddr) < 0)
> return NF_DROP;
>
> switch (tuplehash->tuple.xmit_type) {
> @@ -1226,10 +1250,8 @@ nf_flow_offload_ipv6_hook(void *priv, struct sk_buff *skb,
> }
> if (other_tuple->tun.encap_proto == AF_INET ||
> ctx.tun.proto == IPPROTO_IPIP) {
> - __be32 ip_daddr = other_tuple->src_v4.s_addr;
> struct rtable *rt4;
>
> - skb->protocol = htons(ETH_P_IP);
> rt4 = dst_rtable(tuplehash->tuple.dst_cache);
> neigh = ip_neigh_gw4(rt4->dst.dev,
> rt_nexthop(rt4, ip_daddr));
>
> --
> 2.55.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [PATCH net v2 2/2] vsock/test: add test for small packets under pressure
From: Stefano Garzarella @ 2026-07-08 10:29 UTC (permalink / raw)
To: netdev
Cc: Jason Wang, Stefano Garzarella, Xuan Zhuo, Eric Dumazet,
Eugenio Pérez, Simon Horman, Stefan Hajnoczi,
David S. Miller, linux-kernel, Michael S. Tsirkin, kvm,
Paolo Abeni, virtualization, Jakub Kicinski, Jason Wang
In-Reply-To: <20260708102904.50732-1-sgarzare@redhat.com>
From: Stefano Garzarella <sgarzare@redhat.com>
Add a test that sends 2 MB of data using randomly sized small packets
(129-512 bytes) over a SOCK_STREAM connection. Packets above
GOOD_COPY_LEN (128) bypass the in-place coalescing in recv_enqueue(),
forcing each one into its own skb.
Without receive queue collapsing, the per-skb overhead eventually
exceeds buf_alloc and the connection is reset. The test verifies
that all data arrives and that content integrity is preserved.
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
---
tools/testing/vsock/vsock_test.c | 87 ++++++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/tools/testing/vsock/vsock_test.c b/tools/testing/vsock/vsock_test.c
index 76be0e4a7f0e..b4ff9f946565 100644
--- a/tools/testing/vsock/vsock_test.c
+++ b/tools/testing/vsock/vsock_test.c
@@ -2347,6 +2347,88 @@ static void test_stream_tx_credit_bounds_server(const struct test_opts *opts)
close(fd);
}
+/* Test that many small packets don't cause a connection reset under pressure
+ * and that data integrity is preserved. Packet sizes vary randomly between
+ * 129 and 512 bytes, above GOOD_COPY_LEN (128) to bypass in-place coalescing
+ * in recv_enqueue, forcing each one into its own skb. Without receive queue
+ * collapsing, the per-skb overhead eventually exceeds buf_alloc and the
+ * connection is reset.
+ */
+#define COLLAPSE_PKT_MIN 129
+#define COLLAPSE_PKT_MAX 512
+#define COLLAPSE_TOTAL (2 * 1024 * 1024)
+
+static void test_stream_collapse_client(const struct test_opts *opts)
+{
+ unsigned char *data;
+ unsigned long hash;
+ size_t offset = 0;
+ int i, fd;
+
+ data = malloc(COLLAPSE_TOTAL);
+ if (!data) {
+ perror("malloc");
+ exit(EXIT_FAILURE);
+ }
+
+ for (i = 0; i < COLLAPSE_TOTAL; i++)
+ data[i] = rand() & 0xff;
+
+ fd = vsock_stream_connect(opts->peer_cid, opts->peer_port);
+ if (fd < 0) {
+ perror("connect");
+ exit(EXIT_FAILURE);
+ }
+
+ while (offset < COLLAPSE_TOTAL) {
+ size_t pkt_size = COLLAPSE_PKT_MIN +
+ rand() % (COLLAPSE_PKT_MAX - COLLAPSE_PKT_MIN + 1);
+
+ pkt_size = min(pkt_size, COLLAPSE_TOTAL - offset);
+
+ send_buf(fd, data + offset, pkt_size, 0, pkt_size);
+ offset += pkt_size;
+ }
+
+ hash = hash_djb2(data, COLLAPSE_TOTAL);
+ control_writeulong(hash);
+
+ free(data);
+ close(fd);
+}
+
+static void test_stream_collapse_server(const struct test_opts *opts)
+{
+ unsigned long hash, remote_hash;
+ unsigned char *data;
+ int fd;
+
+ data = malloc(COLLAPSE_TOTAL);
+ if (!data) {
+ perror("malloc");
+ exit(EXIT_FAILURE);
+ }
+
+ fd = vsock_stream_accept(VMADDR_CID_ANY, opts->peer_port, NULL);
+ if (fd < 0) {
+ perror("accept");
+ exit(EXIT_FAILURE);
+ }
+
+ recv_buf(fd, data, COLLAPSE_TOTAL, 0, COLLAPSE_TOTAL);
+
+ hash = hash_djb2(data, COLLAPSE_TOTAL);
+ remote_hash = control_readulong();
+ if (hash != remote_hash) {
+ fprintf(stderr, "hash mismatch: local %lu remote %lu\n",
+ hash, remote_hash);
+ exit(EXIT_FAILURE);
+ }
+
+ free(data);
+ close(fd);
+}
+
static struct test_case test_cases[] = {
{
.name = "SOCK_STREAM connection reset",
@@ -2546,6 +2628,11 @@ static struct test_case test_cases[] = {
.run_client = test_stream_msg_peek_client,
.run_server = test_stream_peek_after_recv_server,
},
+ {
+ .name = "SOCK_STREAM small packets backpressure",
+ .run_client = test_stream_collapse_client,
+ .run_server = test_stream_collapse_server,
+ },
{},
};
--
2.55.0
^ permalink raw reply related
* [PATCH net v2 0/2] vsock/virtio: collapse receive queue under memory pressure
From: Stefano Garzarella @ 2026-07-08 10:29 UTC (permalink / raw)
To: netdev
Cc: Jason Wang, Stefano Garzarella, Xuan Zhuo, Eric Dumazet,
Eugenio Pérez, Simon Horman, Stefan Hajnoczi,
David S. Miller, linux-kernel, Michael S. Tsirkin, kvm,
Paolo Abeni, virtualization, Jakub Kicinski, Jason Wang
This series contains a patch (the first one) that is part of work I'm
doing to improve the tracking of memory used by AF_VSOCK sockets.
The second patch is a test for our suite that highlights the issue.
Since Brien reported an issue with his environment (based on Linux 6.12.y)
related to the work I’m doing, I extracted this patch and tried to make it
as easy as possible to backport. Brien tested it by backporting it to
6.12.y, which now contains the backport of the 059b7dbd20a6
("vsock/virtio: fix potential unbounded skb queue").
This patch primarily fixes STREAM sockets, but also partially fixes
SEQPACKET (with the exception of EOMs, which are kept in separate skbs to
avoid overcomplicating the code).
The rest of the work, I feel, is more net-next material and still needs
some work to be completed.
Changelog
---------
v2:
- defined MAX_COLLAPSE_LEN macro instead of using a variable [Paolo]
- added a threshold to avoid walking all the queue while collapsing
[Paolo]
- collapsed the queue before calling virtio_transport_inc_rx_pkt().
While working on the threshold, I figured out that the check I was
introducing can also be used to proactively trigger the collapse, so I
moved the call to virtio_transport_collapse_rx_queue() before acquiring
the rx_lock to have also a better diff to simplify backports
- improved code readability (removed `out` label, `keep` initialization,
etc.) [Paolo + other small stuff]
- Brien kindly retested this version as well (thank you so much)
v1: https://lore.kernel.org/netdev/20260626134823.206676-1-sgarzare@redhat.com/
Thanks,
Stefano
Stefano Garzarella (2):
vsock/virtio: collapse receive queue under memory pressure
vsock/test: add test for small packets under pressure
net/vmw_vsock/virtio_transport_common.c | 165 +++++++++++++++++++++++-
tools/testing/vsock/vsock_test.c | 87 +++++++++++++
2 files changed, 251 insertions(+), 1 deletion(-)
--
2.55.0
^ permalink raw reply
* [PATCH net v2 1/2] vsock/virtio: collapse receive queue under memory pressure
From: Stefano Garzarella @ 2026-07-08 10:29 UTC (permalink / raw)
To: netdev
Cc: Jason Wang, Stefano Garzarella, Xuan Zhuo, Eric Dumazet,
Eugenio Pérez, Simon Horman, Stefan Hajnoczi,
David S. Miller, linux-kernel, Michael S. Tsirkin, kvm,
Paolo Abeni, virtualization, Jakub Kicinski, Jason Wang, stable,
Brien Oberstein
In-Reply-To: <20260708102904.50732-1-sgarzare@redhat.com>
From: Stefano Garzarella <sgarzare@redhat.com>
When many small packets accumulate in the receive queue, the skb overhead
can exceed buf_alloc even while the payload is within bounds. This causes
virtio_transport_inc_rx_pkt() to reject packets, leading to connection
resets during large transfers under backpressure.
The issue was reported by Brien, who has a reproducer, but it is also
easily reproducible with iperf-vsock [1] using a small packet size:
iperf3 --vsock -c $CID -l 129
which fails immediately without this patch but with commit 059b7dbd20a6
("vsock/virtio: fix potential unbounded skb queue").
Inspired by TCP's tcp_collapse() which solves a similar problem, add
virtio_transport_collapse_rx_queue() that walks the receive queue and
re-copies data into compact linear skbs to reduce the overhead.
The collapse is triggered proactively from when the number of skb queued
is close to exceeding the overhead budget.
A pre-scan counts the eligible bytes to size each allocation precisely,
avoiding waste for isolated small packets. Partially consumed skbs are
kept as-is to preserve buf_used/fwd_cnt accounting, EOM-marked skbs to
maintain SEQPACKET message boundaries, and skbs already larger than the
collapse target because they already have a good data-to-overhead ratio.
Walking a large queue may take a significant amount of time and cache
misses, causing traffic burstiness. To limit this, the collapse stops
once enough room is freed for this packet and the next one, but may
opportunistically free more to fill each collapsed skb to capacity.
[1] https://github.com/stefano-garzarella/iperf-vsock
Fixes: 059b7dbd20a6 ("vsock/virtio: fix potential unbounded skb queue")
Cc: stable@vger.kernel.org
Reported-by: Brien Oberstein <brienpub@gmail.com>
Closes: https://lore.kernel.org/netdev/618701dd023e$063de350$12b9a9f0$@gmail.com/
Tested-by: Brien Oberstein <brienpub@gmail.com>
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
---
v2:
- defined MAX_COLLAPSE_LEN macro instead of using a variable [Paolo]
- added a threshold to avoid walking all the queue while collapsing
[Paolo]
- collapsed the queue before calling virtio_transport_inc_rx_pkt().
While working on the threshold, I figured out that the check I was
introducing can also be used to proactively trigger the collapse, so I
moved the call to virtio_transport_collapse_rx_queue() before acquiring
the rx_lock to have also a better diff to simplify backports
- improved code readability (removed `out` label, `keep` initialization,
etc.) [Paolo + other small stuff]
- Brien kindly retested this version as well (thank you so much)
---
net/vmw_vsock/virtio_transport_common.c | 165 +++++++++++++++++++++++-
1 file changed, 164 insertions(+), 1 deletion(-)
diff --git a/net/vmw_vsock/virtio_transport_common.c b/net/vmw_vsock/virtio_transport_common.c
index 09475007165b..8becad81279c 100644
--- a/net/vmw_vsock/virtio_transport_common.c
+++ b/net/vmw_vsock/virtio_transport_common.c
@@ -26,6 +26,13 @@
/* Threshold for detecting small packets to copy */
#define GOOD_COPY_LEN 128
+/* Max payload that can be collapsed into a single linear skb, using the same
+ * allocation threshold as virtio_vsock_alloc_skb() to avoid adding pressure
+ * on the page allocator.
+ */
+#define MAX_COLLAPSE_LEN \
+ SKB_MAX_ORDER(VIRTIO_VSOCK_SKB_HEADROOM, PAGE_ALLOC_COSTLY_ORDER)
+
static void virtio_transport_cancel_close_work(struct vsock_sock *vsk,
bool cancel_timeout);
static s64 virtio_transport_has_space(struct virtio_vsock_sock *vvs);
@@ -420,6 +427,145 @@ static int virtio_transport_send_pkt_info(struct vsock_sock *vsk,
return ret;
}
+static bool virtio_transport_can_collapse(struct sk_buff *skb)
+{
+ /* skbs that are partially consumed, mark a SEQPACKET message boundary,
+ * or are already large enough should not be collapsed: they either
+ * need special accounting, carry protocol state, or already have a
+ * good data-to-overhead ratio.
+ */
+ if (VIRTIO_VSOCK_SKB_CB(skb)->offset)
+ return false;
+ if (le32_to_cpu(virtio_vsock_hdr(skb)->flags) & VIRTIO_VSOCK_SEQ_EOM)
+ return false;
+ if (skb->len >= MAX_COLLAPSE_LEN)
+ return false;
+ return true;
+}
+
+/* Iterate through the packets in the queue starting from the current skb to
+ * count the number of bytes we can collapse.
+ */
+static unsigned int
+virtio_transport_collapse_size(struct sk_buff *skb, struct sk_buff_head *queue)
+{
+ unsigned int target = skb->len - VIRTIO_VSOCK_SKB_CB(skb)->offset;
+
+ while ((skb = skb_peek_next(skb, queue)) &&
+ virtio_transport_can_collapse(skb)) {
+ unsigned int len = skb->len - VIRTIO_VSOCK_SKB_CB(skb)->offset;
+
+ if (len > MAX_COLLAPSE_LEN - target)
+ return target;
+
+ target += len;
+ }
+
+ return target;
+}
+
+/* Called under lock_sock to compact the receive queue by merging small skbs.
+ * @min_to_free: minimum number of skbs to eliminate from the queue. May free
+ * more to fill each collapsed skb to capacity.
+ */
+static void
+virtio_transport_collapse_rx_queue(struct virtio_vsock_sock *vvs,
+ u32 min_to_free)
+{
+ struct sk_buff *skb, *next_skb, *new_skb = NULL;
+ struct sk_buff_head new_queue;
+ u32 saved = 0;
+
+ __skb_queue_head_init(&new_queue);
+
+ skb_queue_walk_safe(&vvs->rx_queue, skb, next_skb) {
+ struct virtio_vsock_hdr *hdr = virtio_vsock_hdr(skb);
+ u32 src_off = VIRTIO_VSOCK_SKB_CB(skb)->offset;
+ u32 src_len = skb->len - src_off;
+ bool keep;
+
+ keep = !virtio_transport_can_collapse(skb);
+ if (keep) {
+ /* Finalize pending collapsed skb to preserve packet
+ * ordering.
+ */
+ if (new_skb) {
+ __skb_queue_tail(&new_queue, new_skb);
+ new_skb = NULL;
+ saved--;
+ }
+ goto next;
+ }
+
+ /* Finalize if this packet won't fit in the remaining tailroom,
+ * so we can allocate a right-sized new_skb.
+ */
+ if (new_skb && src_len > skb_tailroom(new_skb)) {
+ __skb_queue_tail(&new_queue, new_skb);
+ new_skb = NULL;
+ saved--;
+ }
+
+ if (!new_skb) {
+ unsigned int alloc_size;
+
+ /* Check after finalizing to opportunistically fill
+ * each collapsed skb to capacity, merging more skbs
+ * than strictly required.
+ */
+ if (saved >= min_to_free)
+ break;
+
+ alloc_size = virtio_transport_collapse_size(skb, &vvs->rx_queue);
+
+ /* Only this skb's data is eligible, nothing to merge
+ * with. Keep as-is.
+ */
+ if (alloc_size <= src_len) {
+ keep = true;
+ goto next;
+ }
+
+ new_skb = virtio_vsock_alloc_linear_skb(alloc_size +
+ VIRTIO_VSOCK_SKB_HEADROOM, GFP_KERNEL);
+ if (!new_skb)
+ break;
+
+ memcpy(virtio_vsock_hdr(new_skb), hdr,
+ sizeof(struct virtio_vsock_hdr));
+ virtio_vsock_hdr(new_skb)->len = 0;
+ }
+
+ /* Cannot fail since src_off/src_len are within bounds, but if
+ * it does, discard new_skb to avoid queuing corrupted data.
+ */
+ if (WARN_ON_ONCE(skb_copy_bits(skb, src_off,
+ skb_put(new_skb, src_len),
+ src_len))) {
+ kfree_skb(new_skb);
+ new_skb = NULL;
+ break;
+ }
+
+ le32_add_cpu(&virtio_vsock_hdr(new_skb)->len, src_len);
+ virtio_vsock_hdr(new_skb)->flags |= hdr->flags;
+
+next:
+ __skb_unlink(skb, &vvs->rx_queue);
+ if (keep) {
+ __skb_queue_tail(&new_queue, skb);
+ } else {
+ consume_skb(skb);
+ saved++;
+ }
+ }
+
+ if (new_skb)
+ __skb_queue_tail(&new_queue, new_skb);
+
+ skb_queue_splice(&new_queue, &vvs->rx_queue);
+}
+
static bool virtio_transport_inc_rx_pkt(struct virtio_vsock_sock *vvs,
u32 len)
{
@@ -1354,12 +1500,29 @@ virtio_transport_recv_enqueue(struct vsock_sock *vsk,
{
struct virtio_vsock_sock *vvs = vsk->trans;
bool can_enqueue, free_pkt = false;
+ u32 len, queue_max, queue_len;
struct virtio_vsock_hdr *hdr;
- u32 len;
hdr = virtio_vsock_hdr(skb);
len = le32_to_cpu(hdr->len);
+ /* virtio_transport_inc_rx_pkt() rejects packets when the per-skb
+ * overhead (skb_queue_len * SKB_TRUESIZE(0)) exceeds buf_alloc.
+ * Proactively collapse the queue before that happens.
+ * No rx_lock needed: lock_sock is held by caller, preventing
+ * concurrent enqueue or dequeue.
+ */
+ queue_max = vvs->buf_alloc / SKB_TRUESIZE(0);
+ queue_len = skb_queue_len(&vvs->rx_queue);
+ if (queue_len >= queue_max) {
+ /* Walking a large queue may take a significant amount of time
+ * and cache misses, causing traffic burstiness. Limit the
+ * collapse to freeing room for this packet and the next one.
+ * It may free more to fill each collapsed skb to capacity.
+ */
+ virtio_transport_collapse_rx_queue(vvs, queue_len + 2 - queue_max);
+ }
+
spin_lock_bh(&vvs->rx_lock);
can_enqueue = virtio_transport_inc_rx_pkt(vvs, len);
--
2.55.0
^ permalink raw reply related
* Re: [PATCH net-next v3 07/15] net: macb: introduce macb_context struct for buffer management
From: Paolo Abeni @ 2026-07-08 10:27 UTC (permalink / raw)
To: theo.lebrun
Cc: conor.dooley, andrew+netdev, davem, edumazet, kuba, pabeni,
richardcochran, linux, netdev, linux-kernel, nicolas.ferre,
claudiu.beznea, pvalerio, nb, vladimir.kondratiev,
gregory.clement, benoit.monin, tawfik.bayouk, thomas.petazzoni,
maxime.chevallier
In-Reply-To: <20260701-macb-context-v3-7-00268d5b1502@bootlin.com>
From: AI Reviewer <ai@example.com>
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
Full review at: https://netdev-ai.bots.linux.dev/sashiko/
---
net: macb: introduce macb_context struct for buffer management
This patch moves per-queue ring buffers and ring-size parameters out of
struct macb / struct macb_queue into a new struct macb_context that is
allocated on open and freed on close, so future patches can swap in a
new context while the interface is running.
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index 951a7f080225..dfb1d49d841c 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
[ ... ]
> @@ -1257,6 +1288,7 @@ static void macb_tx_error_task(struct work_struct *work)
> struct macb_queue *queue = container_of(work, struct macb_queue,
> tx_error_task);
> unsigned int q = queue - queue->bp->queues;
> + struct macb_txq *txq = macb_txq(queue);
> struct macb *bp = queue->bp;
[High]
Can macb_tx_error_task() dereference a freed context?
macb_tx_error_task is scheduled from macb_interrupt():
schedule_work(&queue->tx_error_task);
After this patch, the very first thing the worker does is:
struct macb_txq *txq = macb_txq(queue);
which expands to &bp->ctx->txq[q] and dereferences bp->ctx.
Looking at macb_close():
macb_reset_hw(bp);
...
macb_free(bp);
kfree(bp->ctx);
bp->ctx = NULL;
There is no cancel_work_sync(&queue->tx_error_task), and macb_reset_hw()
does not drain the workqueue. If an interrupt scheduled the work just
before close, or the work was already pending, the worker can run after
kfree(bp->ctx) and hit a NULL dereference (and a use-after-free if
macb_open() re-allocates ctx concurrently via ethtool ring reconfig).
The same reasoning applies to bp->hresp_err_bh_work, which is queued
from macb_interrupt() and whose handler calls
mog_init_rings()/macb_init_buffers() that read bp->ctx->tx_ring_size and
bp->ctx->{tx,rx}q[q]. cancel_work_sync(&bp->hresp_err_bh_work) is only
called from macb_remove(), not macb_close().
Pre-patch these fields lived inside the embedded struct macb_queue so a
late worker would touch stale-but-addressable memory; post-patch the
first indirection through bp->ctx faults.
Would adding cancel_work_sync(&queue->tx_error_task) per queue and
cancel_work_sync(&bp->hresp_err_bh_work) before kfree(bp->ctx) in
macb_close() close this window?
[ ... ]
> @@ -3690,8 +3778,8 @@ static int macb_set_ringparam(struct net_device *netdev,
> macb_close(bp->netdev);
> }
>
> - bp->rx_ring_size = new_rx_size;
> - bp->tx_ring_size = new_tx_size;
> + bp->configured_rx_ring_size = new_rx_size;
> + bp->configured_tx_ring_size = new_tx_size;
>
> if (reset)
> macb_open(bp->netdev);
[Medium]
Should the return value of macb_open() be checked here?
This patch adds a new failure point inside macb_open():
bp->ctx = kzalloc_obj(*bp->ctx);
if (!bp->ctx) {
err = -ENOMEM;
goto pm_exit;
}
On failure, bp->ctx remains NULL and the interface stays down, but
macb_set_ringparam() ignores the return value and reports success to
userspace. The commit message says the motivation is to improve
reliability under memory pressure, but this caller silently swallows the
new allocation failure.
[ ... ]
> @@ -5039,6 +5125,12 @@ static int at91ether_open(struct net_device *netdev)
> if (ret < 0)
> return ret;
>
> + bp->ctx = kzalloc_obj(*bp->ctx);
> + if (!bp->ctx) {
> + ret = -ENOMEM;
> + goto pm_exit;
> + }
> +
> /* Clear internal statistics */
> ctl = macb_readl(bp, NCR);
> macb_writel(bp, NCR, ctl | MACB_BIT(CLRSTAT));
[Low]
Should bp->ctx->rx_ring_size, tx_ring_size and rx_buffer_size be
initialized on this path?
macb_open() sets them from configured_{rx,tx}_ring_size and calls
macb_init_rx_buffer_size(), but at91ether_open() leaves them at zero
after kzalloc_obj().
Helpers such as macb_rx_ring_wrap() compute:
return index & (bp->ctx->rx_ring_size - 1);
which becomes index & 0xFFFFFFFF when rx_ring_size is 0. It happens to
be harmless today because the at91ether path constrains indices to
[0, AT91ETHER_MAX_RX_DESCR-1] independently and macb_get_regs() reports
zeroed head/tail for the tx-less at91ether, but pre-patch macb_init_dflt()
unconditionally set bp->rx_ring_size = DEFAULT_RX_RING_SIZE.
Any future shared helper that used tx_ring_size as a stride or divisor
would misbehave on at91ether.
[ ... ]
> @@ -5076,6 +5171,9 @@ static int at91ether_close(struct net_device *netdev)
>
> at91ether_stop(bp);
>
> + kfree(bp->ctx);
> + bp->ctx = NULL;
> +
> pm_runtime_put(&bp->pdev->dev);
>
> return 0;
[High]
Is there IRQ synchronization missing before freeing bp->ctx on this
path?
at91ether_stop() disables MAC RX/TX and writes IDR to mask further
interrupts, but does not synchronize with a handler already running or
already dispatched on another CPU. at91ether_interrupt() calls
at91ether_rx(), which after this patch does:
struct macb_rxq *rxq = &bp->ctx->rxq[0];
...
desc = macb_rx_desc(queue, rxq->tail);
...
p_recv = rxq->buffers + rxq->tail * AT91ETHER_MAX_RBUFF_SZ;
If the handler is in flight when kfree(bp->ctx); bp->ctx = NULL runs,
the next access through bp->ctx faults. The macb_open()/macb_close()
path is somewhat protected by napi_disable() before macb_free(), but
at91ether does not use NAPI and has no equivalent barrier.
Would a synchronize_irq(bp->netdev->irq) between at91ether_stop() and
kfree(bp->ctx) close this?
--
This is an AI-generated review.
^ permalink raw reply
* [PATCH iwl-next v3] ixgbe: E610: force phy link to get down when interface is down
From: Jedrzej Jagielski @ 2026-07-08 10:06 UTC (permalink / raw)
To: intel-wired-lan
Cc: anthony.l.nguyen, netdev, pmenzel, Jedrzej Jagielski,
Aleksandr Loktionov
For the E610 family, similarly to the E8xx adapters, the default behavior
is for the PHY link to remain up even when the corresponding OS interface
is down.
Add function setting down the PHY config IXGBE_ACI_PHY_ENA_LINK bit
what leads to disabling PHY link.
Now ixgbe_close() needs to share some of the ixgbe_watchdog_link_is_down
code so move the common part into the separate function.
Align functionality with the implementation of the ice driver.
Let user to configure link-down-on-close enablement through ethtool.
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>
---
v2: apply Paul's notes
v3: use e_err
---
drivers/net/ethernet/intel/ixgbe/ixgbe.h | 1 +
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 35 ++++++++++++++++++-
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h | 1 +
.../net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 15 ++++++++
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 27 +++++++++++---
5 files changed, 73 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
index 30f62174acf2..7bbb82dd962c 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
@@ -685,6 +685,7 @@ struct ixgbe_adapter {
#define IXGBE_FLAG2_MOD_POWER_UNSUPPORTED BIT(22)
#define IXGBE_FLAG2_API_MISMATCH BIT(23)
#define IXGBE_FLAG2_FW_ROLLBACK BIT(24)
+#define IXGBE_FLAG2_LINK_DOWN_ON_CLOSE BIT(25)
/* Tx fast path data */
int num_tx_queues;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
index 831cfe9a4697..02bc0dac5123 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
@@ -1923,6 +1923,33 @@ void ixgbe_fc_autoneg_e610(struct ixgbe_hw *hw)
hw->fc.current_mode = hw->fc.requested_mode;
}
+/**
+ * ixgbe_disable_phy_link - force phy link to get down
+ * @hw: pointer to hardware structure
+ *
+ * Send 0x0601 with the IXGBE_ACI_PHY_ENA_LINK bit set down.
+ *
+ * Return: the exit code of the operation.
+ */
+int ixgbe_disable_phy_link(struct ixgbe_hw *hw)
+{
+ struct ixgbe_aci_cmd_get_phy_caps_data pcaps = {};
+ struct ixgbe_aci_cmd_set_phy_cfg_data pcfg = {};
+ int err;
+
+ err = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_ACTIVE_CFG,
+ &pcaps);
+ if (err)
+ return err;
+
+ ixgbe_copy_phy_caps_to_cfg(&pcaps, &pcfg);
+
+ pcfg.caps &= ~IXGBE_ACI_PHY_ENA_LINK;
+ pcfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT;
+
+ return ixgbe_aci_set_phy_cfg(hw, &pcfg);
+}
+
/**
* ixgbe_disable_rx_e610 - Disable RX unit
* @hw: pointer to hardware structure
@@ -2207,6 +2234,7 @@ int ixgbe_setup_phy_link_e610(struct ixgbe_hw *hw)
u8 rmode = IXGBE_ACI_REPORT_TOPO_CAP_MEDIA;
u64 sup_phy_type_low, sup_phy_type_high;
u64 phy_type_low = 0, phy_type_high = 0;
+ bool force_on_required;
int err;
err = ixgbe_aci_get_link_info(hw, false, NULL);
@@ -2272,6 +2300,11 @@ int ixgbe_setup_phy_link_e610(struct ixgbe_hw *hw)
phy_type_high |= IXGBE_PHY_TYPE_HIGH_10G_USXGMII;
}
+ /* If IXGBE_ACI_PHY_ENA_LINK has been explicitly disabled that means
+ * we need to force PHY link UP state during PHY link setup
+ */
+ force_on_required = !(pcfg.caps & IXGBE_ACI_PHY_ENA_LINK);
+
/* Mask the set values to avoid requesting unsupported link types. */
phy_type_low &= sup_phy_type_low;
pcfg.phy_type_low = cpu_to_le64(phy_type_low);
@@ -2280,7 +2313,7 @@ int ixgbe_setup_phy_link_e610(struct ixgbe_hw *hw)
if (pcfg.phy_type_high != pcaps.phy_type_high ||
pcfg.phy_type_low != pcaps.phy_type_low ||
- pcfg.caps != pcaps.caps) {
+ pcfg.caps != pcaps.caps || force_on_required) {
pcfg.caps |= IXGBE_ACI_PHY_ENA_LINK;
pcfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h
index 2cb76a3d30ae..59044d67ebeb 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h
@@ -50,6 +50,7 @@ int ixgbe_cfg_phy_fc(struct ixgbe_hw *hw,
enum ixgbe_fc_mode req_mode);
int ixgbe_setup_fc_e610(struct ixgbe_hw *hw);
void ixgbe_fc_autoneg_e610(struct ixgbe_hw *hw);
+int ixgbe_disable_phy_link(struct ixgbe_hw *hw);
void ixgbe_disable_rx_e610(struct ixgbe_hw *hw);
int ixgbe_init_phy_ops_e610(struct ixgbe_hw *hw);
int ixgbe_identify_phy_e610(struct ixgbe_hw *hw);
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
index b8e85bc91a27..16e26d54f3be 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
@@ -139,6 +139,8 @@ static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = {
"vf-ipsec",
#define IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF BIT(2)
"mdd-disable-vf",
+#define IXGBE_PRIV_LINK_DOWN_ON_CLOSE BIT(3)
+ "link-down-on-close",
};
#define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings)
@@ -3822,6 +3824,9 @@ static u32 ixgbe_get_priv_flags(struct net_device *netdev)
if (adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF)
priv_flags |= IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF;
+ if (adapter->flags2 & IXGBE_FLAG2_LINK_DOWN_ON_CLOSE)
+ priv_flags |= IXGBE_PRIV_LINK_DOWN_ON_CLOSE;
+
return priv_flags;
}
@@ -3859,6 +3864,16 @@ static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags)
}
}
+ flags2 &= ~IXGBE_FLAG2_LINK_DOWN_ON_CLOSE;
+ if (priv_flags & IXGBE_PRIV_LINK_DOWN_ON_CLOSE) {
+ if (adapter->hw.mac.type == ixgbe_mac_e610) {
+ flags2 |= IXGBE_FLAG2_LINK_DOWN_ON_CLOSE;
+ } else {
+ e_info(probe, "Cannot set private flags: Feature supported only for E610 devices\n");
+ return -EOPNOTSUPP;
+ }
+ }
+
if (flags2 != adapter->flags2) {
adapter->flags2 = flags2;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 7a0783c1abc1..d0bba3e202ca 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -7551,6 +7551,17 @@ static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
ixgbe_free_all_rx_resources(adapter);
}
+static void ixgbe_handle_link_down(struct ixgbe_adapter *adapter)
+{
+ struct net_device *netdev = adapter->netdev;
+
+ if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
+ ixgbe_ptp_start_cyclecounter(adapter);
+
+ e_info(drv, "NIC Link is Down\n");
+ netif_carrier_off(netdev);
+}
+
/**
* ixgbe_close - Disables a network interface
* @netdev: network interface device structure
@@ -7573,6 +7584,16 @@ int ixgbe_close(struct net_device *netdev)
ixgbe_fdir_filter_exit(adapter);
+ if (adapter->flags2 & IXGBE_FLAG2_LINK_DOWN_ON_CLOSE) {
+ int err;
+
+ err = ixgbe_disable_phy_link(&adapter->hw);
+ if (err)
+ e_err(drv, "Cannot set PHY link down\n");
+
+ ixgbe_handle_link_down(adapter);
+ }
+
ixgbe_release_hw_control(adapter);
return 0;
@@ -8251,11 +8272,7 @@ static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
- if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
- ixgbe_ptp_start_cyclecounter(adapter);
-
- e_info(drv, "NIC Link is Down\n");
- netif_carrier_off(netdev);
+ ixgbe_handle_link_down(adapter);
}
static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
--
2.31.1
^ permalink raw reply related
* Re: [PATCH net-next v6 3/3] net: libwx: support vf per-queue statistics via ethtool -S
From: mengyuanlou @ 2026-07-08 10:23 UTC (permalink / raw)
To: Paolo Abeni; +Cc: netdev, jiawenwu, duanqiangwen, horms, kuba
In-Reply-To: <20260707095046.104606-1-pabeni@redhat.com>
> 2026年7月7日 17:50，Paolo Abeni <pabeni@redhat.com> 写道：
>
> From: AI Reviewer <ai@example.com>
>
> This is an AI-generated review of your patch. The human sending this
> email has considered the AI review valid, or at least plausible.
> Full review at: https://netdev-ai.bots.linux.dev/sashiko/
> ---
> Now I have enough information to produce the report.
>
> commit e59c58bb080afb34cac34c91b8c320a1f05134e6
> Author: Mengyuan Lou <mengyuanlou@net-swift.com>
>
> net: libwx: support vf per-queue statistics via ethtool -S
>
> The patch wires wx_get_sset_count, wx_get_strings, and wx_get_ethtool_stats
> into wx_ethtool_ops_vf, adds a small vf-only global stats table, and starts
> calling wx_update_stats() from wxvf_service_task. It also adds NULL checks
> for wx->rx_ring[i] / wx->tx_ring[i] inside wx_update_stats.
>
>> diff --git a/drivers/net/ethernet/wangxun/libwx/wx_ethtool.c b/drivers/net/ethernet/wangxun/libwx/wx_ethtool.c
>> index 22037f015ded..f72908630ea4 100644
>> --- a/drivers/net/ethernet/wangxun/libwx/wx_ethtool.c
>> +++ b/drivers/net/ethernet/wangxun/libwx/wx_ethtool.c
>
> [ ... ]
>
>> @@ -114,7 +133,7 @@ void wx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
>> ethtool_sprintf(&p, "tx_queue_%u_packets", i);
>> ethtool_sprintf(&p, "tx_queue_%u_bytes", i);
>> }
>> - for (i = 0; i < WX_NUM_RX_QUEUES; i++) {
>> + for (i = 0; i < WX_NUM_RX_QUEUES(netdev); i++) {
>> ethtool_sprintf(&p, "rx_queue_%u_packets", i);
>> ethtool_sprintf(&p, "rx_queue_%u_bytes", i);
>> }
>
> [ ... ]
>
>> @@ -852,6 +878,9 @@ static const struct ethtool_ops wx_ethtool_ops_vf = {
>> .set_coalesce = wx_set_coalesce,
>> .get_ts_info = ethtool_op_get_ts_info,
>> .get_link_ksettings = wx_get_link_ksettings_vf,
>> + .get_sset_count = wx_get_sset_count,
>> + .get_strings = wx_get_strings,
>> + .get_ethtool_stats = wx_get_ethtool_stats,
>> };
>
> [Medium]
> Before this change wx_ethtool_ops_vf had no get_sset_count / get_strings /
> get_ethtool_stats callbacks, so the VF exposed no ethtool -S output at all.
> Wiring these in also picks up the shared per-queue string loop that emits
> tx_queue_%u_packets / tx_queue_%u_bytes and rx_queue_%u_packets /
> rx_queue_%u_bytes.
>
> Per-queue TX/RX packet and byte counters are a category that already has a
> standard uAPI (netdev_stat_ops with queue_stats_rx / queue_stats_tx,
> surfaced by netlink and ynl). Documentation/networking/statistics.rst and
> the ethtool -S guidance state that new counters covering values that have a
> standard uAPI should not be added to ethtool -S even when the driver does
> not yet implement the standard interface.
>
> The wangxun tree does not implement netdev_stat_ops (no
> get_base_stats / get_queue_stats_rx / get_queue_stats_tx callbacks are
> present under drivers/net/ethernet/wangxun/).
Ok，I will remove patch3（support vf per-queue statistics via ethtool -S).
>
> Would it be preferable to expose the per-queue counters on the VF via
> netdev_stat_ops instead of adding them to ethtool -S here?
netdev_stat_ops support is deferred to a follow-up patch; this one only extends ethtool ops.
>
>> void wx_set_ethtool_ops_vf(struct net_device *netdev)
>> diff --git a/drivers/net/ethernet/wangxun/libwx/wx_hw.c b/drivers/net/ethernet/wangxun/libwx/wx_hw.c
>> index 260e14d5d541..349afbe60132 100644
>> --- a/drivers/net/ethernet/wangxun/libwx/wx_hw.c
>> +++ b/drivers/net/ethernet/wangxun/libwx/wx_hw.c
>> @@ -2886,6 +2886,8 @@ void wx_update_stats(struct wx *wx)
>> for (i = 0; i < wx->num_rx_queues; i++) {
>> struct wx_ring *rx_ring = wx->rx_ring[i];
>>
>> + if (!rx_ring)
>> + continue;
>> non_eop_descs += rx_ring->rx_stats.non_eop_descs;
>
> [ ... ]
>
>> diff --git a/drivers/net/ethernet/wangxun/libwx/wx_vf_common.c b/drivers/net/ethernet/wangxun/libwx/wx_vf_common.c
>> index 26de78e9a69e..1d84fe35d7d9 100644
>> --- a/drivers/net/ethernet/wangxun/libwx/wx_vf_common.c
>> +++ b/drivers/net/ethernet/wangxun/libwx/wx_vf_common.c
>> @@ -409,6 +410,7 @@ static void wxvf_service_task(struct work_struct *work)
>>
>> wxvf_link_config_subtask(wx);
>> wxvf_reset_subtask(wx);
>> + wx_update_stats(wx);
>> wx_service_event_complete(wx);
>> }
>
> [High]
> Can this call race with VF PCI suspend and shutdown to produce a
> use-after-free on wx->rx_ring[i] / wx->tx_ring[i]?
>
> Both ngbevf and txgbevf use wxvf_suspend as their PM suspend callback and
> wxvf_shutdown (which calls wxvf_suspend) as their pci_driver ->shutdown
> callback:
>
> static DEFINE_SIMPLE_DEV_PM_OPS(ngbevf_pm_ops, wxvf_suspend, wxvf_resume);
> ...
> .shutdown = wxvf_shutdown,
>
> wxvf_suspend() in wx_vf_common.c does:
>
> int wxvf_suspend(struct device *dev_d)
> {
> struct pci_dev *pdev = to_pci_dev(dev_d);
> struct wx *wx = pci_get_drvdata(pdev);
>
> netif_device_detach(wx->netdev);
> wx_clear_interrupt_scheme(wx);
> pci_disable_device(pdev);
>
> return 0;
> }
>
> wx_clear_interrupt_scheme() ends up freeing the q_vectors (via
> kfree_rcu), and the ring allocations are embedded in the q_vector, so
> wx->rx_ring[i] / wx->tx_ring[i] end up pointing at memory that will be
> freed after an RCU grace period.
>
> wxvf_suspend / wxvf_shutdown do not call timer_shutdown_sync on
> wx->service_timer or cancel_work_sync on wx->service_task, and they do
> not set WX_STATE_DOWN.
>
> With this hunk in place, the service_task now walks wx->rx_ring[] and
> wx->tx_ring[]:
>
> void wx_update_stats(struct wx *wx)
> {
> ...
> for (i = 0; i < wx->num_rx_queues; i++) {
> struct wx_ring *rx_ring = wx->rx_ring[i];
>
> if (!rx_ring)
> continue;
> non_eop_descs += rx_ring->rx_stats.non_eop_descs;
> ...
> }
> ...
> for (i = 0; i < wx->num_tx_queues; i++) {
> struct wx_ring *tx_ring = wx->tx_ring[i];
>
> if (!tx_ring)
> continue;
> restart_queue += tx_ring->tx_stats.restart_queue;
> ...
> }
>
> If the service_task latches a non-NULL rx_ring / tx_ring pointer just
> before wx_clear_interrupt_scheme runs, the added NULL check does not
> help, and the subsequent ->rx_stats / ->tx_stats reads touch memory
> that has been kfree_rcu'd. wxvf_remove() covers this by calling
> timer_shutdown_sync + cancel_work_sync before wx_clear_interrupt_scheme,
> but wxvf_suspend / wxvf_shutdown do not.
>
> Should wxvf_suspend (and hence wxvf_shutdown) quiesce the service_timer
> and service_task, or set WX_STATE_DOWN, before wx_clear_interrupt_scheme
> now that wx_update_stats is on the service_task's call path?
> --
> This is an AI-generated review.
>
>
^ permalink raw reply
* [PATCH net-next 5/5] net: phy: mediatek: add calibration logic for AN7583
From: Christian Marangi @ 2026-07-08 10:23 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Christian Marangi,
Daniel Golle, Qingfang Deng, SkyLake Huang, Matthias Brugger,
AngeloGioacchino Del Regno, linux-kernel, netdev,
linux-arm-kernel, linux-mediatek
In-Reply-To: <20260708102341.53919-1-ansuelsmth@gmail.com>
Similar to Airoha AN7581 Switch PHY also the Airoha AN7583 SoC
requires dedicated calibration and tuneup to make EEE correctly work.
Airoha AN7583 differ from AN7581 by having a dedicated table for
calibration and additional EEE logic tuneup.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/mediatek/airoha-ge-soc.c | 227 ++++++++++++++++++++++-
drivers/net/phy/mediatek/mtk.h | 1 +
2 files changed, 225 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/mediatek/airoha-ge-soc.c b/drivers/net/phy/mediatek/airoha-ge-soc.c
index bc487b093cfa..601a64d83365 100644
--- a/drivers/net/phy/mediatek/airoha-ge-soc.c
+++ b/drivers/net/phy/mediatek/airoha-ge-soc.c
@@ -159,6 +159,106 @@ static u8 an7581_zcal_to_r45ohm[64] = {
52, 50, 48, 46, 44, 42, 40, 39, 36, 35, 32, 32, 30, 28, 27, 25
};
+/*
+ * 2 chip revision
+ * TXMR or discrete
+ * 2 MDI type
+ * TX AMP test/TX AMP 1G/TX AMP 100M/TX AMP 10M/R50
+ * 4 PHY
+ */
+static int an7583_tx_amp_compensation_tbl[TRANSFORMER_TYPE_MAX][MDI_TYPE_MAX][CALIB_CONST_TYPE_MAX][4] = {
+ [TXMR] = {
+ [MDI_0R] = {
+ [TX_AMP_TEST_A] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_B] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_C] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_D] = { -3, -3, -3, -3 },
+ [TX_AMP_1G_A] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_B] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_C] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_D] = { 0, 0, 0, 0 },
+ [TX_AMP_100M_A] = { 4, 4, 4, 4 },
+ [TX_AMP_100M_B] = { 4, 4, 4, 4 },
+ [TX_AMP_10M_A] = { 0, 0, 0, 0 },
+ [TX_AMP_10M_B] = { 0, 0, 0, 0 },
+ [R50_A] = { 4, 4, 0, 0 },
+ [R50_B] = { 4, 4, 0, 0 },
+ [R50_C] = { 5, 5, 3, 4 },
+ [R50_D] = { 4, 4, 4, 0 },
+ },
+ [MDI_5R] = {
+ [TX_AMP_TEST_A] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_B] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_C] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_D] = { -3, -3, -3, -3 },
+ [TX_AMP_1G_A] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_B] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_C] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_D] = { 0, 0, 0, 0 },
+ [TX_AMP_100M_A] = { 4, 4, 4, 4 },
+ [TX_AMP_100M_B] = { 4, 4, 4, 4 },
+ [TX_AMP_10M_A] = { 0, 0, 0, 0 },
+ [TX_AMP_10M_B] = { 0, 0, 0, 0 },
+ [R50_A] = { -4, -4, -4, -4 },
+ [R50_B] = { -4, -4, -4, -4 },
+ [R50_C] = { -2, -2, -2, -2 },
+ [R50_D] = { -3, -3, -2, -2 },
+ },
+ },
+ [DISCRETE] = {
+ [MDI_0R] = {
+ [TX_AMP_TEST_A] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_B] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_C] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_D] = { -3, -3, -3, -3 },
+ [TX_AMP_1G_A] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_B] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_C] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_D] = { 0, 0, 0, 0 },
+ [TX_AMP_100M_A] = { 4, 4, 4, 4 },
+ [TX_AMP_100M_B] = { 4, 4, 4, 4 },
+ [TX_AMP_10M_A] = { 0, 0, 0, 0 },
+ [TX_AMP_10M_B] = { 0, 0, 0, 0 },
+ [R50_A] = { 4, 4, 4, 4 },
+ [R50_B] = { 4, 4, 4, 4 },
+ [R50_C] = { 6, 6, 6, 6 },
+ [R50_D] = { 4, 4, 4, 4 },
+ },
+ [MDI_5R] = {
+ [TX_AMP_TEST_A] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_B] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_C] = { -3, -3, -3, -3 },
+ [TX_AMP_TEST_D] = { -3, -3, -3, -3 },
+ [TX_AMP_1G_A] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_B] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_C] = { 0, 0, 0, 0 },
+ [TX_AMP_1G_D] = { 0, 0, 0, 0 },
+ [TX_AMP_100M_A] = { 4, 4, 4, 4 },
+ [TX_AMP_100M_B] = { 4, 4, 4, 4 },
+ [TX_AMP_10M_A] = { 0, 0, 0, 0 },
+ [TX_AMP_10M_B] = { 0, 0, 0, 0 },
+ [R50_A] = { 0, 0, 0, 0 },
+ [R50_B] = { 0, 0, 0, 0 },
+ [R50_C] = { 0, 0, 0, 0 },
+ [R50_D] = { 0, 0, 0, 0 },
+ },
+ },
+};
+
+static u8 an7583_zcal_to_r50ohm_0R[64] = {
+ 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127,
+ 127, 127, 127, 122, 118, 114, 110, 106, 102, 98, 96, 92, 88, 85, 82, 80,
+ 76, 72, 70, 68, 64, 62, 60, 57, 55, 52, 50, 48, 46, 44, 41, 40,
+ 38, 36, 33, 32, 30, 28, 26, 24, 24, 22, 20, 18, 16, 16, 14, 12,
+};
+
+static u8 an7583_zcal_to_r50ohm_5R[64] = {
+ 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127,
+ 127, 127, 127, 127, 127, 127, 127, 127, 127, 124, 120, 116, 112, 110, 106, 102,
+ 99, 96, 93, 90, 88, 84, 81, 79, 76, 73, 71, 68, 66, 64, 61, 59,
+ 56, 54, 52, 50, 48, 46, 44, 42, 40, 39, 37, 36, 33, 32, 31, 29,
+};
+
static int airoha_cal_cycle(struct phy_device *phydev, int devad,
u32 regnum, u16 mask, u16 cal_val)
{
@@ -766,8 +866,9 @@ static int airoha_rx_offset_cal_sw(struct phy_device *phydev)
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0x171,
BIT(8) | BIT(7));
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG6,
- 0x1);
+ if (phydev->drv->phy_id == AIROHA_GPHY_ID_AN7581)
+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_ANA_CAL_RG6, 0x1);
return 0;
}
@@ -1540,8 +1641,126 @@ static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index,
static int an7583_phy_config_init(struct phy_device *phydev)
{
+ struct airoha_socphy_shared *shared = phy_package_get_priv(phydev);
+ struct phy_device *phydev_p0;
+ u8 phy_offset;
+ int ret;
+
/* BMCR_PDOWN is enabled by default */
- return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
+ phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
+
+ phydev_p0 = shared->phydev_p0;
+ phy_offset = phydev->mdio.addr - phydev_p0->mdio.addr;
+
+ /* FIXME: Read SoC MDI Resister Type if available or default to 5R */
+ shared->mdi_resister_type = MDI_5R;
+
+ shared->mdi_resister_type = MDI_5R;
+ if (shared->mdi_resister_type == MDI_0R)
+ shared->r50_cal_tbl = an7583_zcal_to_r50ohm_0R;
+ if (shared->mdi_resister_type == MDI_5R)
+ shared->r50_cal_tbl = an7583_zcal_to_r50ohm_5R;
+ shared->tx_amp_compensation_tbl = &an7583_tx_amp_compensation_tbl;
+
+ ret = airoha_phy_calib(phydev);
+ if (ret)
+ return ret;
+
+ ret = airoha_phy_auto_select_transformer(phydev);
+ if (ret)
+ return ret;
+
+ ret = airoha_phy_tx_amp_compensation(phydev);
+ if (ret)
+ return ret;
+
+ /* Enable Idle Mode Power Setting */
+ if (phy_offset == 0) {
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x268, 0x07F1);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x703, 0x3111);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x271, 0x3C24);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x701, 0x1023);
+ }
+
+ if (shared->transformer_type[phy_offset] == TXMR) {
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x23, 0x0881);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x24, 0x0881);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x25, 0x0881);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x26, 0x0881);
+
+ if (shared->mdi_resister_type == MDI_0R)
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0205);
+ else
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0200);
+ } else {
+ if (shared->mdi_resister_type == MDI_0R) {
+ /* RX setting for 5R_TXMR before AN setting */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xe7, 0x6666);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xe9, 0x0003);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xfe, 0x0006);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xe6, 0x1111);
+ /* 100M sharp */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x23, 0x0c86);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x24, 0x0c86);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x25, 0x0c86);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x26, 0x0c86);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01, 0x01cb);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x02, 0x01c2);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x03, 0x0108);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x04, 0x0211);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0205);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x06, 0x0387);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x07, 0x03ce);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x08, 0x03c8);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0b, 0x0005);
+ } else {
+ /* 100M sharp */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x23, 0x0886);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x24, 0x0886);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x25, 0x0886);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x26, 0x0886);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x00, 0x0195);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01, 0x01cb);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x02, 0x01c2);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x03, 0x0108);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x04, 0x0211);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0205);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x06, 0x0387);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x07, 0x03ce);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x08, 0x03c3);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0a, 0x0010);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0b, 0x0005);
+ }
+ }
+
+ /* RX Setting */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3c, 0xc000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3d, 0x0000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3e, 0xc000);
+
+ /* EEE setting */
+ phy_write_mmd(phydev, MDIO_MMD_AN, 0x3c, 0x0000);
+
+ /* 10M settings */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x1a3, 0x00d2);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x1a4, 0x010e);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x27b, 0x1177);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x27c, 0x0808);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
+ __phy_write(phydev, 0x14, 0x190);
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_1);
+ __phy_write(phydev, 0x14, 0x3a18);
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ phy_write(phydev, 0x9, 0x0600);
+
+ /* EEE keep only Pair A ON */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x630, 0x006E);
+
+ return 0;
}
static struct phy_driver mtk_socphy_driver[] = {
@@ -1572,6 +1791,8 @@ static struct phy_driver mtk_socphy_driver[] = {
.led_hw_control_set = mt798x_phy_led_hw_control_set,
.led_hw_control_get = mt798x_phy_led_hw_control_get,
.led_polarity_set = an7581_phy_led_polarity_set,
+ .read_page = mtk_phy_read_page,
+ .write_page = mtk_phy_write_page,
},
};
diff --git a/drivers/net/phy/mediatek/mtk.h b/drivers/net/phy/mediatek/mtk.h
index c690aaf38124..cd9d4c5550c3 100644
--- a/drivers/net/phy/mediatek/mtk.h
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -13,6 +13,7 @@
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_EXTENDED_1 0x0001
+#define MTK_PHY_PAGE_EXTENDED_3 0x0003
#define MTK_PHY_PAGE_STANDARD 0x0000
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 4/5] net: phy: mediatek: add calibration logic for AN7581
From: Christian Marangi @ 2026-07-08 10:23 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Christian Marangi,
Daniel Golle, Qingfang Deng, SkyLake Huang, Matthias Brugger,
AngeloGioacchino Del Regno, linux-kernel, netdev,
linux-arm-kernel, linux-mediatek
In-Reply-To: <20260708102341.53919-1-ansuelsmth@gmail.com>
Airoha AN7581 require dedicated calibration and specific tuneup to make
the Ethernet port work on specific HW PCB layout.
The calibration process is similar to Mediatek PHY but Airoha PHY use
Software calibration process instead of making use of EFUSE.
It does also require some complex table for TX Amp compensation and
multiple register settings for EEE and 10/100M to correctly work.
Also the PHY apply a different TX Amp compensation table based on the
SoC PDIDR version. Such version info is stored in the SCU SoC registers.
Add module version as suggested by Airoha to identify the calibration logic
with a specific version.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/mediatek/airoha-ge-soc.c | 1489 ++++++++++++++++++++++
drivers/net/phy/mediatek/mtk-ge-soc.h | 13 +
2 files changed, 1502 insertions(+)
diff --git a/drivers/net/phy/mediatek/airoha-ge-soc.c b/drivers/net/phy/mediatek/airoha-ge-soc.c
index 429594f27792..bc487b093cfa 100644
--- a/drivers/net/phy/mediatek/airoha-ge-soc.c
+++ b/drivers/net/phy/mediatek/airoha-ge-soc.c
@@ -1,16 +1,1493 @@
// SPDX-License-Identifier: GPL-2.0+
+#include <linux/bitfield.h>
#include <linux/pinctrl/consumer.h>
#include <linux/phy.h>
+#include "../phylib.h"
#include "mtk.h"
#include "mtk-ge-soc.h"
+#define AIROHA_DEFAULT_PORT0_ADDR 0x9
#define AIROHA_PHY_MAX_LEDS 2
+enum airoha_mdi_resister_type {
+ MDI_0R,
+ MDI_5R,
+
+ MDI_TYPE_MAX,
+};
+
+enum airoha_transformer_type {
+ TXMR,
+ DISCRETE,
+
+ TRANSFORMER_TYPE_MAX,
+};
+
+enum airoha_calib_const_type {
+ TX_AMP_TEST_A,
+ TX_AMP_TEST_B,
+ TX_AMP_TEST_C,
+ TX_AMP_TEST_D,
+ TX_AMP_1G_A,
+ TX_AMP_1G_B,
+ TX_AMP_1G_C,
+ TX_AMP_1G_D,
+ TX_AMP_100M_A,
+ TX_AMP_100M_B,
+ TX_AMP_10M_A,
+ TX_AMP_10M_B,
+ R50_A,
+ R50_B,
+ R50_C,
+ R50_D,
+
+ CALIB_CONST_TYPE_MAX,
+};
+
+struct airoha_socphy_shared {
+ struct phy_device *phydev_p0;
+ enum airoha_transformer_type transformer_type[4];
+ enum airoha_mdi_resister_type mdi_resister_type;
+ bool rext_sw_calib_done;
+ int (*tx_amp_compensation_tbl)[TRANSFORMER_TYPE_MAX][MDI_TYPE_MAX][CALIB_CONST_TYPE_MAX][4];
+ u8 *r50_cal_tbl;
+};
+
+/*
+ * 2 chip revision
+ * TXMR or discrete
+ * 2 MDI type
+ * TX AMP test/TX AMP 1G/TX AMP 100M/TX AMP 10M/R50
+ * 4 PHY
+ */
+static int an7581_tx_amp_compensation_tbl[2][TRANSFORMER_TYPE_MAX][MDI_TYPE_MAX][CALIB_CONST_TYPE_MAX][4] = {
+ { /* IC version 1 */
+ [TXMR] = {
+ { },
+ {
+ [TX_AMP_TEST_A] = { -12, -11, -9, -6 },
+ [TX_AMP_TEST_B] = { -9, -13, -9, -5 },
+ [TX_AMP_TEST_C] = { -5, -4, -3, 1 },
+ [TX_AMP_TEST_D] = { -9, -8, -7, -5 },
+ [TX_AMP_1G_A] = { -12, -11, -9, -6 },
+ [TX_AMP_1G_B] = { -9, -13, -9, -5 },
+ [TX_AMP_1G_C] = { -5, -4, -3, 1 },
+ [TX_AMP_1G_D] = { -9, -8, -7, -5 },
+ [TX_AMP_100M_A] = { -2, -2, 0, 2 },
+ [TX_AMP_100M_B] = { -2, -2, 1, 1 },
+ [TX_AMP_10M_A] = { 0, 0, 0, 0 },
+ [TX_AMP_10M_B] = { 0, 0, 0, 0 },
+ [R50_A] = { 15, 15, 15, 15 },
+ [R50_B] = { 15, 15, 18, 15 },
+ [R50_C] = { -8, -8, -8, -8 },
+ [R50_D] = { -8, -8, -8, -8 },
+ },
+ },
+ [DISCRETE] = {
+ { },
+ {
+ [TX_AMP_TEST_A] = { -9, -7, -7, -5 },
+ [TX_AMP_TEST_B] = { -9, -9, -7, -4 },
+ [TX_AMP_TEST_C] = { -9, -7, -9, -6 },
+ [TX_AMP_TEST_D] = { -11, -9, -10, -8 },
+ [TX_AMP_1G_A] = { -9, -7, -7, -5 },
+ [TX_AMP_1G_B] = { -9, -8, -7, -4 },
+ [TX_AMP_1G_C] = { -9, -7, -9, -6 },
+ [TX_AMP_1G_D] = { -11, -8, -10, -8 },
+ [TX_AMP_100M_A] = { 4, 3, 4, 4 },
+ [TX_AMP_100M_B] = { 4, 4, 5, 4 },
+ [TX_AMP_10M_A] = { 0, 0, 0, 0 },
+ [TX_AMP_10M_B] = { 0, 0, 0, 0 },
+ [R50_A] = { 0, 0, 0, 0 },
+ [R50_B] = { 0, 0, 0, 0 },
+ [R50_C] = { 0, 0, 0, 0 },
+ [R50_D] = { 0, 0, 0, 0 },
+ },
+ },
+ },
+ { /* IC version 2 */
+ [TXMR] = {
+ { },
+ {
+ [TX_AMP_TEST_A] = { -10, -12, -12, -11 },
+ [TX_AMP_TEST_B] = { -10, -11, -11, -10 },
+ [TX_AMP_TEST_C] = { -5, -7, -9, -3 },
+ [TX_AMP_TEST_D] = { -8, -10, -7, -8 },
+ [TX_AMP_1G_A] = { -12, -6, -6, 4 },
+ [TX_AMP_1G_B] = { -10, -5, -5, 1 },
+ [TX_AMP_1G_C] = { -5, -3, -4, 11 },
+ [TX_AMP_1G_D] = { -8, -3, -3, 4 },
+ [TX_AMP_100M_A] = { 2, 1, 0, 3 },
+ [TX_AMP_100M_B] = { 0, 0, 0, 3 },
+ [TX_AMP_10M_A] = { 0, 0, 0, 0 },
+ [TX_AMP_10M_B] = { 0, 0, 0, 0 },
+ [R50_A] = { 15, 15, 15, 15 },
+ [R50_B] = { 15, 15, 18, 15 },
+ [R50_C] = { 4, 4, 4, 4 },
+ [R50_D] = { 4, 4, 4, 4 },
+ },
+ },
+ [DISCRETE] = {
+ { },
+ {
+ [TX_AMP_TEST_A] = { -11, 11, -12, -7 },
+ [TX_AMP_TEST_B] = { -9, -10, -9, -8 },
+ [TX_AMP_TEST_C] = { -6, -3, -7, -4 },
+ [TX_AMP_TEST_D] = { -7, -8, -10, -7 },
+ [TX_AMP_1G_A] = { -11, -11, -12, -7 },
+ [TX_AMP_1G_B] = { -9, -10, -9, -8 },
+ [TX_AMP_1G_C] = { -6, -3, -7, -4 },
+ [TX_AMP_1G_D] = { -7, -8, -10, -7 },
+ [TX_AMP_100M_A] = { 2, 2, 1, 2 },
+ [TX_AMP_100M_B] = { 3, 3, 3, 3 },
+ [TX_AMP_10M_A] = { 0, 0, 0, 0 },
+ [TX_AMP_10M_B] = { 0, 0, 0, 0 },
+ [R50_A] = { 12, 12, 12, 12 },
+ [R50_B] = { 7, 7, 7, 7 },
+ [R50_C] = { 2, 2, 0, 0 },
+ [R50_D] = { 0, 0, 2, 2 },
+ },
+ },
+ },
+};
+
+static u8 an7581_zcal_to_r45ohm[64] = {
+ 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127,
+ 127, 127, 127, 127, 127, 127, 127, 127, 123, 119, 115, 112, 108, 104, 100, 96,
+ 94, 92, 88, 85, 82, 80, 76, 74, 72, 68, 66, 64, 62, 60, 56, 55,
+ 52, 50, 48, 46, 44, 42, 40, 39, 36, 35, 32, 32, 30, 28, 27, 25
+};
+
+static int airoha_cal_cycle(struct phy_device *phydev, int devad,
+ u32 regnum, u16 mask, u16 cal_val)
+{
+ struct airoha_socphy_shared *shared = phy_package_get_priv(phydev);
+ struct phy_device *phydev_p0;
+ int ret;
+
+ phydev_p0 = shared->phydev_p0;
+
+ phy_modify_mmd(phydev, devad, regnum, mask, cal_val);
+
+ ret = mtk_cal_cycle_wait(phydev_p0);
+ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
+
+ return ret;
+}
+
+static int airoha_rext_cal_sw(struct phy_device *phydev)
+{
+ int calibration_polarity;
+ u8 zcal_ctrl = 32;
+ int first_calib;
+ int ret;
+
+ /* BG voltage output */
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x100, 0xc000);
+ /* tst_mode2 */
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xff, 0x2);
+
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 0xff,
+ GENMASK(15, 4) | GENMASK(1, 0));
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
+ MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN |
+ MTK_PHY_RG_REXT_CALEN);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG6, 0);
+
+ phydev_dbg(phydev, "Start REXT SW cal.\n");
+ first_calib = airoha_cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
+ MTK_PHY_RG_REXT_ZCAL_CTRL_MASK, zcal_ctrl);
+
+ if (first_calib < 0) {
+ phydev_err(phydev, "REXT SW calibration failed.\n");
+ return -EINVAL;
+ }
+
+ /* If REXT calibration failed:
+ * - increase dB until calibration succeed.
+ * If REXT calibration succeeded:
+ * - decrease dB until calibration fail to fine tune it.
+ */
+ if (first_calib == 1)
+ calibration_polarity = -1;
+ else
+ calibration_polarity = 1;
+
+ while (zcal_ctrl > 0 &&
+ zcal_ctrl < FIELD_MAX(MTK_PHY_RG_REXT_ZCAL_CTRL_MASK)) {
+ zcal_ctrl += calibration_polarity;
+
+ ret = airoha_cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
+ MTK_PHY_RG_REXT_ZCAL_CTRL_MASK, zcal_ctrl);
+ /* Exit if we either failed or succeeded compared to the
+ * first calibration result. (aka we finished fine tuning or
+ * we succeeded with calibration)
+ */
+ if (ret != first_calib)
+ break;
+ }
+
+ if (ret < 0) {
+ phydev_err(phydev, "REXT SW calibration failed.\n");
+ return -EINVAL;
+ }
+
+ if (zcal_ctrl == 0 ||
+ zcal_ctrl == FIELD_MAX(MTK_PHY_RG_REXT_ZCAL_CTRL_MASK)) {
+ zcal_ctrl = 32;
+ phydev_err(phydev, "REXT SW calibration saturation. Defaulting to %x.\n",
+ zcal_ctrl);
+ }
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
+ MTK_PHY_RG_REXT_TRIM_MASK,
+ FIELD_PREP(MTK_PHY_RG_REXT_TRIM_MASK, zcal_ctrl));
+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
+ MTK_PHY_RG_BG_RASEL_MASK,
+ FIELD_PREP(MTK_PHY_RG_BG_RASEL_MASK, zcal_ctrl >> 3));
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 0);
+
+ return 0;
+}
+
+static int airoha_tx_offset_cal_sw(struct phy_device *phydev, u8 txg_calen_x)
+{
+ struct airoha_socphy_shared *shared = phy_package_get_priv(phydev);
+ struct phy_device *phydev_p0;
+ u16 dev1e_145_tmp, bmcr_tmp;
+ int calibration_polarity;
+ u16 reg_dac1, reg_dac2;
+ int zcal_ctrl = 0;
+ int first_calib;
+ u16 reg, mask;
+ int ret;
+
+ phydev_p0 = shared->phydev_p0;
+
+ /* BG voltage output */
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND2, 0x100, 0xc000);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
+ MTK_PHY_RG_ANA_CALEN);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
+ MTK_PHY_RG_TXVOS_CALEN);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
+ MTK_PHY_RG_ANA_CALEN);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
+ MTK_PHY_RG_TXVOS_CALEN);
+
+ /* Force 1G full duplex for calibration */
+ bmcr_tmp = phy_read(phydev, MII_BMCR);
+ phy_write(phydev, MII_BMCR, BMCR_FULLDPLX | BMCR_SPEED1000);
+
+ /* Force MDI */
+ dev1e_145_tmp = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x0145);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0145, 0x1010);
+
+ /* 1e_96[15]:bypass_tx_offset_cal, Hw bypass, Fw cal */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x96,
+ 0x8000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3e,
+ 0xf808);
+
+ switch (txg_calen_x) {
+ case PAIR_A:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, BIT(12));
+ reg_dac1 = MTK_PHY_RG_DASN_DAC_IN0_A;
+ reg_dac2 = MTK_PHY_RG_DASN_DAC_IN1_A;
+ reg = MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B;
+ mask = MTK_PHY_CR_TX_AMP_OFFSET_A_MASK;
+ break;
+ case PAIR_B:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, BIT(8));
+ reg_dac1 = MTK_PHY_RG_DASN_DAC_IN0_B;
+ reg_dac2 = MTK_PHY_RG_DASN_DAC_IN1_B;
+ reg = MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B;
+ mask = MTK_PHY_CR_TX_AMP_OFFSET_B_MASK;
+ break;
+ case PAIR_C:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, BIT(4));
+ reg_dac1 = MTK_PHY_RG_DASN_DAC_IN0_C;
+ reg_dac2 = MTK_PHY_RG_DASN_DAC_IN1_C;
+ reg = MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D;
+ mask = MTK_PHY_CR_TX_AMP_OFFSET_C_MASK;
+ break;
+ case PAIR_D:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, BIT(0));
+ reg_dac1 = MTK_PHY_RG_DASN_DAC_IN0_D;
+ reg_dac2 = MTK_PHY_RG_DASN_DAC_IN1_D;
+ reg = MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D;
+ mask = MTK_PHY_CR_TX_AMP_OFFSET_D_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg_dac1,
+ 0x8000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg_dac2,
+ 0x8000);
+
+ phydev_dbg(phydev, "Start TX Offset SW cal.\n");
+
+ first_calib = airoha_cal_cycle(phydev, MDIO_MMD_VEND1, reg, mask,
+ zcal_ctrl << __ffs(mask));
+
+ /* If TX Offset calibration failed:
+ * - increase dB until calibration succeed.
+ * If TX Offset calibration succeeded:
+ * - decrease dB until calibration fail to fine tune it.
+ */
+ if (first_calib == 1)
+ calibration_polarity = -1;
+ else
+ calibration_polarity = 1;
+
+ while (zcal_ctrl > -32 && zcal_ctrl < 32) {
+ u32 val;
+
+ zcal_ctrl += calibration_polarity;
+ if (zcal_ctrl >= 0)
+ val = zcal_ctrl;
+ else
+ /* BIT(5) signal negative number for TX Offset */
+ val = BIT(5) | abs(zcal_ctrl);
+
+ ret = airoha_cal_cycle(phydev, MDIO_MMD_VEND1, reg, mask,
+ val << __ffs(mask));
+ /* Exit if we either failed or succeeded compared to the
+ * first calibration result. (aka we finished fine tuning or
+ * we succeeded with calibration)
+ */
+ if (ret != first_calib)
+ break;
+ }
+
+ if (ret < 0) {
+ phydev_err(phydev, "TX Offset calibration failed.\n");
+ return -EINVAL;
+ }
+
+ if (zcal_ctrl == -32 ||
+ zcal_ctrl == 32) {
+ zcal_ctrl = 0;
+ phydev_err(phydev, "TX Offset SW calibration saturation. Defaulting to %x.\n",
+ zcal_ctrl);
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, reg, mask,
+ zcal_ctrl << __ffs(mask));
+ }
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x100, 0x0);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_A, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_B, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_C, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_D, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_A, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_B, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_C, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_D, 0);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 0);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 0);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x96, 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3e, 0xc000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, 0);
+
+ /* Restore BMCR */
+ phy_write(phydev, MII_BMCR, bmcr_tmp);
+
+ /* Restore MDI */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0145, dev1e_145_tmp);
+
+ return 0;
+}
+
+static int airoha_tx_amp_cal_sw(struct phy_device *phydev, u8 txg_calen_x)
+{
+ struct airoha_socphy_shared *shared = phy_package_get_priv(phydev);
+ u16 mask_gbe, mask_tbt, mask_tst, mask_hbt;
+ u16 reg, reg_100, reg_dac1, reg_dac2;
+ struct phy_device *phydev_p0;
+ int calibration_polarity;
+ u8 zcal_ctrl = 32;
+ int first_calib;
+ int ret;
+
+ phydev_p0 = shared->phydev_p0;
+
+ /* BG voltage output */
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND2, 0x100, 0xc000);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x145, 0x1010);
+
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
+ MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
+ MTK_PHY_RG_TXVOS_CALEN);
+
+ /* select 1V */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG6, 0x10);
+
+ /* enable Tx VLD*/
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3e, 0xf808);
+
+ /* Force 1G full duplex for calibration */
+ phy_write(phydev, MII_BMCR, BMCR_FULLDPLX | BMCR_SPEED1000);
+
+ switch (txg_calen_x) {
+ case PAIR_A:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, BIT(12));
+ reg_dac1 = MTK_PHY_RG_DASN_DAC_IN0_A;
+ reg_dac2 = MTK_PHY_RG_DASN_DAC_IN1_A;
+ reg = MTK_PHY_TXVLD_DA_RG;
+ mask_gbe = MTK_PHY_DA_TX_I2MPB_A_GBE_MASK;
+ mask_tbt = MTK_PHY_DA_TX_I2MPB_A_TBT_MASK;
+ reg_100 = MTK_PHY_TX_I2MPB_TEST_MODE_A2;
+ mask_hbt = MTK_PHY_DA_TX_I2MPB_A_HBT_MASK;
+ mask_tst = MTK_PHY_DA_TX_I2MPB_A_TST_MASK;
+ break;
+ case PAIR_B:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, BIT(8));
+ reg_dac1 = MTK_PHY_RG_DASN_DAC_IN0_B;
+ reg_dac2 = MTK_PHY_RG_DASN_DAC_IN1_B;
+ reg = MTK_PHY_TX_I2MPB_TEST_MODE_B1;
+ mask_gbe = MTK_PHY_DA_TX_I2MPB_B_GBE_MASK;
+ mask_tbt = MTK_PHY_DA_TX_I2MPB_B_TBT_MASK;
+ reg_100 = MTK_PHY_TX_I2MPB_TEST_MODE_B2;
+ mask_hbt = MTK_PHY_DA_TX_I2MPB_B_HBT_MASK;
+ mask_tst = MTK_PHY_DA_TX_I2MPB_B_TST_MASK;
+ break;
+ case PAIR_C:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, BIT(4));
+ reg_dac1 = MTK_PHY_RG_DASN_DAC_IN0_C;
+ reg_dac2 = MTK_PHY_RG_DASN_DAC_IN1_C;
+ reg = MTK_PHY_TX_I2MPB_TEST_MODE_C1;
+ mask_gbe = MTK_PHY_DA_TX_I2MPB_C_GBE_MASK;
+ mask_tbt = MTK_PHY_DA_TX_I2MPB_C_TBT_MASK;
+ reg_100 = MTK_PHY_TX_I2MPB_TEST_MODE_C2;
+ mask_hbt = MTK_PHY_DA_TX_I2MPB_C_HBT_MASK;
+ mask_tst = MTK_PHY_DA_TX_I2MPB_C_TST_MASK;
+ break;
+ case PAIR_D:
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, BIT(0));
+ reg_dac1 = MTK_PHY_RG_DASN_DAC_IN0_D;
+ reg_dac2 = MTK_PHY_RG_DASN_DAC_IN1_D;
+ reg = MTK_PHY_TX_I2MPB_TEST_MODE_D1;
+ mask_gbe = MTK_PHY_DA_TX_I2MPB_D_GBE_MASK;
+ mask_tbt = MTK_PHY_DA_TX_I2MPB_D_TBT_MASK;
+ reg_100 = MTK_PHY_TX_I2MPB_TEST_MODE_D2;
+ mask_hbt = MTK_PHY_DA_TX_I2MPB_D_HBT_MASK;
+ mask_tst = MTK_PHY_DA_TX_I2MPB_D_TST_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg_dac1,
+ 0x8000 | 0xf0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg_dac2,
+ 0x8000 | 0xf0);
+
+ phydev_dbg(phydev, "Start TX Amp SW cal.\n");
+ first_calib = airoha_cal_cycle(phydev, MDIO_MMD_VEND1, reg,
+ mask_gbe, zcal_ctrl << __ffs(mask_gbe));
+
+ /* If TX Amp calibration failed:
+ * - increase dB until calibration succeed.
+ * If TX Amp calibration succeeded:
+ * - decrease dB until calibration fail to fine tune it.
+ */
+ if (first_calib == 1)
+ calibration_polarity = -1;
+ else
+ calibration_polarity = 1;
+
+ while (zcal_ctrl > 0 &&
+ zcal_ctrl < FIELD_MAX(MTK_PHY_RG_REXT_ZCAL_CTRL_MASK)) {
+ zcal_ctrl += calibration_polarity;
+
+ ret = airoha_cal_cycle(phydev, MDIO_MMD_VEND1, reg,
+ mask_gbe, zcal_ctrl << __ffs(mask_gbe));
+ /* Exit if we either failed or succeeded compared to the
+ * first calibration result. (aka we finished fine tuning or
+ * we succeeded with calibration)
+ */
+ if (ret != first_calib)
+ break;
+ }
+
+ if (ret < 0) {
+ phydev_err(phydev, "TX AMP calibration failed.\n");
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, reg,
+ mask_gbe | mask_tbt,
+ (zcal_ctrl << __ffs(mask_gbe)) |
+ (zcal_ctrl << __ffs(mask_tbt)));
+
+ return -EINVAL;
+ }
+
+ if (zcal_ctrl == 0 ||
+ zcal_ctrl == FIELD_MAX(MTK_PHY_RG_REXT_ZCAL_CTRL_MASK))
+ phydev_warn(phydev, "TX AMP SW calibration saturation.\n");
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, reg,
+ mask_gbe | mask_tbt,
+ (zcal_ctrl << __ffs(mask_gbe)) |
+ (zcal_ctrl << __ffs(mask_tbt)));
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, reg_100,
+ mask_hbt | mask_tst,
+ (zcal_ctrl << __ffs(mask_hbt)) |
+ (zcal_ctrl << __ffs(mask_tst)));
+
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND2, 0x100, 0x0);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_A, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_B, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_C, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_D, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_A, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_B, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_C, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_D, 0);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, 0x145, 0x1000);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 0);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 0);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3e, 0xc000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, 0);
+
+ /* Restore AN enable */
+ phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
+
+ return 0;
+}
+
+static int airoha_tx_r50_cal_sw(struct phy_device *phydev, u8 txg_calen_x)
+{
+ struct airoha_socphy_shared *shared = phy_package_get_priv(phydev);
+ struct phy_device *phydev_p0;
+ u16 dev1e_145_tmp, bmcr_tmp;
+ int calibration_polarity;
+ u8 zcal_ctrl = 32;
+ int first_calib;
+ u16 reg;
+ int ret;
+
+ phydev_p0 = shared->phydev_p0;
+
+ /* BG voltage output */
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND2, 0x100, 0xc000);
+
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
+ MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 0);
+ /* select 1V */
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG6, 0x10);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
+ MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 0);
+ /* select 1V */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG6, 0x10);
+
+ /* Force 1G full duplex for calibration */
+ bmcr_tmp = phy_read(phydev, MII_BMCR);
+ phy_write(phydev, MII_BMCR, BMCR_FULLDPLX | BMCR_SPEED1000);
+
+ /* Force MDI */
+ dev1e_145_tmp = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x0145);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0145, 0x1010);
+
+ /* disable tx slew control */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0185, 0x0000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x00fb, 0x0100);
+
+ switch (txg_calen_x) {
+ case PAIR_A:
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_ANA_CAL_RG0,
+ MTK_PHY_RG_ZCALEN_A);
+ break;
+ case PAIR_B:
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_ANA_CAL_RG1,
+ MTK_PHY_RG_ZCALEN_B);
+ break;
+ case PAIR_C:
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_ANA_CAL_RG1,
+ MTK_PHY_RG_ZCALEN_C);
+ break;
+ case PAIR_D:
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_ANA_CAL_RG1,
+ MTK_PHY_RG_ZCALEN_D);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ phydev_dbg(phydev, "Start TX r50 SW cal.\n");
+ first_calib = airoha_cal_cycle(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
+ MTK_PHY_RG_REXT_ZCAL_CTRL_MASK, zcal_ctrl);
+
+ if (first_calib < 0) {
+ phydev_err(phydev, "TX r50 SW calibration failed.\n");
+ return -EINVAL;
+ }
+
+ /* If TX r50 calibration failed:
+ * - increase dB until calibration succeed.
+ * If TX r50 calibration succeeded:
+ * - decrease dB until calibration fail to fine tune it.
+ */
+ if (first_calib == 1)
+ calibration_polarity = -1;
+ else
+ calibration_polarity = 1;
+
+ while (zcal_ctrl > 0 &&
+ zcal_ctrl < FIELD_MAX(MTK_PHY_RG_REXT_ZCAL_CTRL_MASK)) {
+ zcal_ctrl += calibration_polarity;
+
+ ret = airoha_cal_cycle(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
+ MTK_PHY_RG_REXT_ZCAL_CTRL_MASK, zcal_ctrl);
+ /* Exit if we either failed or succeeded compared to the
+ * first calibration result. (aka we finished fine tuning or
+ * we succeeded with calibration)
+ */
+ if (ret != first_calib)
+ break;
+ }
+
+ if (ret < 0) {
+ phydev_err(phydev, "TX r50 SW calibration failed.\n");
+ return -EINVAL;
+ }
+
+ if (zcal_ctrl == 0 ||
+ zcal_ctrl == FIELD_MAX(MTK_PHY_RG_REXT_ZCAL_CTRL_MASK))
+ phydev_warn(phydev, "TX r50 SW calibration saturation.\n");
+
+ zcal_ctrl = shared->r50_cal_tbl[zcal_ctrl];
+
+ switch (txg_calen_x) {
+ case PAIR_A:
+ reg = BIT(7) | FIELD_PREP(MTK_PHY_CR_TX_R50_OFFSET_A_MASK, zcal_ctrl);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_CR_TX_R50_OFFSET_A_B,
+ BIT(7) | MTK_PHY_CR_TX_R50_OFFSET_A_MASK, reg);
+ break;
+ case PAIR_B:
+ reg = BIT(7) | FIELD_PREP(MTK_PHY_CR_TX_R50_OFFSET_B_MASK, zcal_ctrl);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_CR_TX_R50_OFFSET_A_B,
+ BIT(7) | MTK_PHY_CR_TX_R50_OFFSET_B_MASK, reg);
+ break;
+ case PAIR_C:
+ reg = BIT(7) | FIELD_PREP(MTK_PHY_CR_TX_R50_OFFSET_C_MASK, zcal_ctrl);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_CR_TX_R50_OFFSET_C_D,
+ BIT(7) | MTK_PHY_CR_TX_R50_OFFSET_C_MASK, reg);
+ break;
+ case PAIR_D:
+ reg = BIT(7) | FIELD_PREP(MTK_PHY_CR_TX_R50_OFFSET_D_MASK, zcal_ctrl);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_CR_TX_R50_OFFSET_C_D,
+ BIT(7) | MTK_PHY_CR_TX_R50_OFFSET_D_MASK, reg);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 0);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 0);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 0);
+
+ /* Enable tx slew control */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0185, 0x0001);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x00fb, 0x0000);
+
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND2, 0x100, 0x0);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG6, 0x0);
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG6, 0x0);
+
+ /* Restore BMCR */
+ phy_write(phydev, MII_BMCR, bmcr_tmp);
+
+ /* Restore MDI */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0145, dev1e_145_tmp);
+
+ return 0;
+}
+
+static int airoha_rx_offset_cal_sw(struct phy_device *phydev)
+{
+ /* Hw bypass, Fw cal */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x96, 0x8000);
+ /* tx/rx_cal_criteria_value */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x37, 0x0033);
+
+ /* rx offset cal by Hw setup */
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0x39,
+ BIT(14) | BIT(11));
+
+ /* disable rtune calibration */
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 0x107,
+ BIT(12));
+
+ /* bypass tx/rx dc offset cancellation process */
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 0x171,
+ BIT(8) | BIT(7));
+
+ /* rx offset calibration start */
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 0x39,
+ BIT(13));
+
+ /* rx offset calibration stop */
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0x39,
+ BIT(13));
+
+ mdelay(10);
+
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0x171,
+ BIT(8) | BIT(7));
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG6,
+ 0x1);
+
+ return 0;
+}
+
+static int airoha_cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
+ u8 start_pair, u8 end_pair)
+{
+ u8 pair_n;
+ int ret;
+
+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
+ switch (cal_item) {
+ case REXT:
+ ret = airoha_rext_cal_sw(phydev);
+ break;
+ case TX_OFFSET:
+ ret = airoha_tx_offset_cal_sw(phydev, pair_n);
+ break;
+ case TX_AMP:
+ ret = airoha_tx_amp_cal_sw(phydev, pair_n);
+ break;
+ case TX_R50:
+ ret = airoha_tx_r50_cal_sw(phydev, pair_n);
+ break;
+ case RX_OFFSET:
+ ret = airoha_rx_offset_cal_sw(phydev);
+ break;
+ default:
+ return -EINVAL;
+ }
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+
+static int airoha_start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
+ enum CAL_MODE cal_mode, u8 start_pair,
+ u8 end_pair, u32 *buf)
+{
+ int ret;
+
+ switch (cal_mode) {
+ case SW_M:
+ ret = airoha_cal_sw(phydev, cal_item, start_pair, end_pair);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (ret) {
+ phydev_err(phydev, "cal %d failed\n", cal_item);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int airoha_phy_calib(struct phy_device *phydev)
+{
+ struct airoha_socphy_shared *shared = phy_package_get_priv(phydev);
+ struct phy_device *phydev_p0;
+ int ret;
+
+ phydev_p0 = shared->phydev_p0;
+
+ /* PreCalibrate Set */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x5c, 0x6666);
+
+ if (!shared->rext_sw_calib_done) {
+ ret = airoha_start_cal(phydev, REXT, SW_M, NO_PAIR, NO_PAIR, NULL);
+ if (ret)
+ return ret;
+
+ shared->rext_sw_calib_done = true;
+ }
+
+ ret = airoha_start_cal(phydev, TX_R50, SW_M, PAIR_A, PAIR_D, NULL);
+ if (ret)
+ return ret;
+
+ ret = airoha_start_cal(phydev, TX_OFFSET, SW_M, PAIR_A, PAIR_D, NULL);
+ if (ret)
+ return ret;
+
+ ret = airoha_start_cal(phydev, TX_AMP, SW_M, PAIR_A, PAIR_D, NULL);
+ if (ret)
+ return ret;
+
+ ret = airoha_start_cal(phydev, RX_OFFSET, SW_M, NO_PAIR, NO_PAIR, NULL);
+ if (ret)
+ return ret;
+
+ /* Gating, short with other pair */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x15, 0x0);
+
+ phy_write_mmd(phydev_p0, MDIO_MMD_VEND2, 0x100, 0x0);
+
+ return 0;
+}
+
+static int airoha_phy_auto_select_transformer(struct phy_device *phydev)
+{
+ struct airoha_socphy_shared *shared = phy_package_get_priv(phydev);
+ struct phy_device *phydev_p0;
+ u8 phy_offset;
+ u16 bmcr_tmp;
+ u16 val;
+ int i;
+
+ phydev_p0 = shared->phydev_p0;
+ phy_offset = phydev->mdio.addr - phydev_p0->mdio.addr;
+
+ /* Force 1G full duplex for calibration */
+ bmcr_tmp = phy_read(phydev, MII_BMCR);
+ phy_write(phydev, MII_BMCR, BMCR_FULLDPLX | BMCR_SPEED1000);
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0x271, GENMASK(4, 0),
+ FIELD_PREP(GENMASK(4, 0), 0x3));
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0x269, GENMASK(15, 12),
+ FIELD_PREP(GENMASK(15, 12), 0x2));
+
+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0x26f, GENMASK(14, 12),
+ FIELD_PREP(GENMASK(14, 12), 0x0));
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, BIT(12));
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_A,
+ 0x8000 | 0xf0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_A,
+ 0x8000 | 0xf0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_B,
+ 0x8000 | 0xf0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_B,
+ 0x8000 | 0xf0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_C,
+ 0x8000 | 0xf0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_C,
+ 0x8000 | 0xf0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_D,
+ 0x8000 | 0xf0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_D,
+ 0x8000 | 0xf0);
+
+ /* Force pGA gain */
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x10,
+ GENMASK(20, 15),
+ FIELD_PREP(GENMASK(20, 15), 0x1f));
+
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x11,
+ GENMASK(23, 18) | GENMASK(15, 10) | GENMASK(7, 2),
+ FIELD_PREP(GENMASK(23, 18), 0x1f) |
+ FIELD_PREP(GENMASK(15, 10), 0x1f) |
+ FIELD_PREP(GENMASK(7, 2), 0x1f));
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xc9, 0xffff);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x151, 0x12);
+
+ switch (phy_offset) {
+ case 0:
+ val = 0x1;
+ break;
+ case 1:
+ val = 0x3;
+ break;
+ case 2:
+ val = 0x5;
+ break;
+ case 3:
+ val = 0x7;
+ break;
+ default:
+ return -EINVAL;
+ }
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x15,
+ FIELD_PREP(GENMASK(14, 12), val) | 0x161);
+ mdelay(500);
+
+ for (i = 0; i < 3; i++)
+ val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0x1a);
+
+ /* Check the value and report transformer type for later */
+ shared->transformer_type[phy_offset] = val < 0xe0;
+
+ /* Switch to Default */
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x15, 0x1000);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xdd, 0x0);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_A,
+ 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_A,
+ 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_B,
+ 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_B,
+ 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_C,
+ 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_C,
+ 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN0_D,
+ 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DASN_DAC_IN1_D,
+ 0x0);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xc9, 0xfff);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x151, 0x0);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x10,
+ GENMASK(20, 15),
+ FIELD_PREP(GENMASK(20, 15), 0x4));
+
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x11,
+ GENMASK(23, 18) | GENMASK(15, 10) | GENMASK(7, 2),
+ FIELD_PREP(GENMASK(23, 18), 0x0) |
+ FIELD_PREP(GENMASK(15, 10), 0x0) |
+ FIELD_PREP(GENMASK(7, 2), 0x0));
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ /* Restore BMCR */
+ phy_write(phydev, MII_BMCR, bmcr_tmp);
+
+ return 0;
+}
+
+static int airoha_phy_tx_amp_compensation(struct phy_device *phydev)
+{
+ struct airoha_socphy_shared *shared = phy_package_get_priv(phydev);
+
+ u16 reg_1e_12_read;
+ u16 reg_1e_16_read;
+ u16 reg_1e_17_read;
+ u16 reg_1e_18_read;
+ u16 reg_1e_19_read;
+ u16 reg_1e_20_read;
+ u16 reg_1e_21_read;
+ u16 reg_1e_22_read;
+ u16 reg_1e_174_read;
+ u16 reg_1e_175_read;
+
+ int reg_1e_12_header;
+ int reg_1e_16_header;
+ int reg_1e_17_header;
+ int reg_1e_18_header;
+ int reg_1e_19_header;
+ int reg_1e_21_header;
+ int reg_1e_174_header;
+ int reg_1e_175_header;
+
+ int reg_1e_12_end;
+ int reg_1e_16_end;
+ int reg_1e_17_end;
+ int reg_1e_18_end;
+ int reg_1e_20_end;
+ int reg_1e_22_end;
+ int reg_1e_174_end;
+ int reg_1e_175_end;
+
+ struct phy_device *phydev_p0;
+ u8 phy_offset;
+
+ int txamp_low_limit = -3;
+ int txamp_high_limit = 0x42;
+
+ int r50_low_limit = -8;
+ int r50_high_limit = 0x88;
+
+ bool overflow;
+ int (*tx_amp_table)[CALIB_CONST_TYPE_MAX][4];
+ int transformer_type, mdi_resister_type;
+
+ phydev_p0 = shared->phydev_p0;
+ phy_offset = phydev->mdio.addr - phydev_p0->mdio.addr;
+
+ transformer_type = shared->transformer_type[phy_offset];
+ mdi_resister_type = shared->mdi_resister_type;
+ tx_amp_table = shared->tx_amp_compensation_tbl[transformer_type][mdi_resister_type];
+
+ reg_1e_12_read = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x12);
+ reg_1e_16_read = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x16);
+ reg_1e_17_read = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x17);
+ reg_1e_18_read = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x18);
+ reg_1e_19_read = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x19);
+ reg_1e_20_read = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x20);
+ reg_1e_21_read = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x21);
+ reg_1e_22_read = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x22);
+ reg_1e_174_read = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x174);
+ reg_1e_175_read = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x175);
+
+ reg_1e_12_header = ((reg_1e_12_read & 0xfc00) / 1024) + *tx_amp_table[TX_AMP_1G_A][phy_offset];
+ reg_1e_17_header = ((reg_1e_17_read & 0x3f00) / 256) + *tx_amp_table[TX_AMP_1G_B][phy_offset];
+ reg_1e_19_header = ((reg_1e_19_read & 0x3f00) / 256) + *tx_amp_table[TX_AMP_1G_C][phy_offset];
+ reg_1e_21_header = ((reg_1e_21_read & 0x3f00) / 256) + *tx_amp_table[TX_AMP_1G_D][phy_offset];
+
+ overflow = false;
+ if (reg_1e_12_header < txamp_low_limit ||
+ reg_1e_12_header > txamp_high_limit)
+ overflow = true;
+ if (reg_1e_17_header < txamp_low_limit ||
+ reg_1e_17_header > txamp_high_limit)
+ overflow = true;
+ if (reg_1e_19_header < txamp_low_limit ||
+ reg_1e_19_header > txamp_high_limit)
+ overflow = true;
+ if (reg_1e_21_header < txamp_low_limit ||
+ reg_1e_21_header > txamp_high_limit)
+ overflow = true;
+
+ if (overflow) {
+ reg_1e_12_header = 0x20;
+ reg_1e_17_header = 0x20;
+ reg_1e_19_header = 0x20;
+ reg_1e_21_header = 0x20;
+ } else {
+ if (reg_1e_12_header < 0)
+ reg_1e_12_header = 0;
+ else if (reg_1e_12_header > 0x3f)
+ reg_1e_12_header = 0x3f;
+ if (reg_1e_17_header < 0)
+ reg_1e_17_header = 0;
+ else if (reg_1e_17_header > 0x3f)
+ reg_1e_17_header = 0x3f;
+ if (reg_1e_19_header < 0)
+ reg_1e_19_header = 0;
+ else if (reg_1e_19_header > 0x3f)
+ reg_1e_19_header = 0x3f;
+ if (reg_1e_21_header < 0)
+ reg_1e_21_header = 0;
+ else if (reg_1e_21_header > 0x3f)
+ reg_1e_21_header = 0x3f;
+ }
+
+ reg_1e_16_end = (reg_1e_16_read & 0x003f) + *tx_amp_table[TX_AMP_TEST_A][phy_offset];
+ reg_1e_18_end = (reg_1e_18_read & 0x003f) + *tx_amp_table[TX_AMP_TEST_B][phy_offset];
+ reg_1e_20_end = (reg_1e_20_read & 0x003f) + *tx_amp_table[TX_AMP_TEST_C][phy_offset];
+ reg_1e_22_end = (reg_1e_22_read & 0x003f) + *tx_amp_table[TX_AMP_TEST_D][phy_offset];
+
+ overflow = false;
+ if (reg_1e_16_end < txamp_low_limit ||
+ reg_1e_16_end > txamp_high_limit)
+ overflow = true;
+ if (reg_1e_18_end < txamp_low_limit ||
+ reg_1e_18_end > txamp_high_limit)
+ overflow = true;
+ if (reg_1e_20_end < txamp_low_limit ||
+ reg_1e_20_end > txamp_high_limit)
+ overflow = true;
+ if (reg_1e_22_end < txamp_low_limit ||
+ reg_1e_22_end > txamp_high_limit)
+ overflow = true;
+
+ if (overflow) {
+ reg_1e_16_end = 0x20;
+ reg_1e_18_end = 0x20;
+ reg_1e_20_end = 0x20;
+ reg_1e_22_end = 0x20;
+ } else {
+ if (reg_1e_16_end < 0)
+ reg_1e_16_end = 0;
+ else if (reg_1e_16_end > 0x3f)
+ reg_1e_16_end = 0x3f;
+ if (reg_1e_18_end < 0)
+ reg_1e_18_end = 0;
+ else if (reg_1e_18_end > 0x3f)
+ reg_1e_18_end = 0x3f;
+ if (reg_1e_20_end < 0)
+ reg_1e_20_end = 0;
+ else if (reg_1e_20_end > 0x3f)
+ reg_1e_20_end = 0x3f;
+ if (reg_1e_22_end < 0)
+ reg_1e_22_end = 0;
+ else if (reg_1e_22_end > 0x3f)
+ reg_1e_22_end = 0x3f;
+ }
+
+ reg_1e_16_header = ((reg_1e_16_read & 0xfc00) / 1024) + *tx_amp_table[TX_AMP_100M_A][phy_offset];
+ reg_1e_18_header = ((reg_1e_18_read & 0x3f00) / 256) + *tx_amp_table[TX_AMP_100M_B][phy_offset];
+
+ overflow = false;
+ if (reg_1e_16_header < txamp_low_limit ||
+ reg_1e_16_header > txamp_high_limit)
+ overflow = true;
+ if (reg_1e_18_header < txamp_low_limit ||
+ reg_1e_18_header > txamp_high_limit)
+ overflow = true;
+
+ if (overflow) {
+ reg_1e_16_header = 0x20;
+ reg_1e_18_header = 0x20;
+ } else {
+ if (reg_1e_16_header < 0)
+ reg_1e_16_header = 0;
+ else if (reg_1e_16_header > 0x3f)
+ reg_1e_16_header = 0x3f;
+ if (reg_1e_18_header < 0)
+ reg_1e_18_header = 0;
+ else if (reg_1e_18_header > 0x3f)
+ reg_1e_18_header = 0x3f;
+ }
+
+ reg_1e_12_end = (reg_1e_12_read & 0x003f) + *tx_amp_table[TX_AMP_10M_A][phy_offset];
+ reg_1e_17_end = (reg_1e_17_read & 0x003f) + *tx_amp_table[TX_AMP_10M_B][phy_offset];
+
+ overflow = false;
+ if (reg_1e_12_end < txamp_low_limit ||
+ reg_1e_12_end > txamp_high_limit)
+ overflow = true;
+ if (reg_1e_17_end < txamp_low_limit ||
+ reg_1e_17_end > txamp_high_limit)
+ overflow = true;
+
+ if (overflow) {
+ reg_1e_12_end = 0x20;
+ reg_1e_17_end = 0x20;
+ } else {
+ if (reg_1e_12_end < 0)
+ reg_1e_12_end = 0;
+ else if (reg_1e_12_end > 0x3f)
+ reg_1e_12_end = 0x3f;
+ if (reg_1e_17_end < 0)
+ reg_1e_17_end = 0;
+ else if (reg_1e_17_end > 0x3f)
+ reg_1e_17_end = 0x3f;
+ }
+
+ reg_1e_174_header = ((reg_1e_174_read & 0x7f00) / 256) + *tx_amp_table[R50_A][phy_offset];
+ reg_1e_174_end = (reg_1e_174_read & 0x007f) + *tx_amp_table[R50_B][phy_offset];
+ reg_1e_175_header = ((reg_1e_175_read & 0x7f00) / 256) + *tx_amp_table[R50_C][phy_offset];
+ reg_1e_175_end = (reg_1e_175_read & 0x007f) + *tx_amp_table[R50_D][phy_offset];
+
+ overflow = false;
+ if (reg_1e_174_header < r50_low_limit ||
+ reg_1e_174_header > r50_high_limit)
+ overflow = true;
+ if (reg_1e_174_end < r50_low_limit ||
+ reg_1e_174_end > r50_high_limit)
+ overflow = true;
+ if (reg_1e_175_header < r50_low_limit ||
+ reg_1e_175_header > r50_high_limit)
+ overflow = true;
+ if (reg_1e_175_end < r50_low_limit ||
+ reg_1e_175_end > r50_high_limit)
+ overflow = true;
+
+ if (overflow) {
+ reg_1e_174_header = 0x34;
+ reg_1e_174_end = 0x34;
+ reg_1e_175_header = 0x34;
+ reg_1e_175_end = 0x34;
+ } else {
+ if (reg_1e_174_header < 0)
+ reg_1e_174_header = 0;
+ else if (reg_1e_174_header > 0x7f)
+ reg_1e_174_header = 0x7f;
+ if (reg_1e_174_end < 0)
+ reg_1e_174_end = 0;
+ else if (reg_1e_174_end > 0x7f)
+ reg_1e_174_end = 0x7f;
+ if (reg_1e_175_header < 0)
+ reg_1e_175_header = 0;
+ else if (reg_1e_175_header > 0x7f)
+ reg_1e_175_header = 0x7f;
+ if (reg_1e_175_end < 0)
+ reg_1e_175_end = 0;
+ else if (reg_1e_175_end > 0x7f)
+ reg_1e_175_end = 0x7f;
+ }
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x12,
+ (reg_1e_12_header * 1024) + reg_1e_12_end);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x16,
+ (reg_1e_16_header * 1024) + reg_1e_16_end);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x17,
+ (reg_1e_17_header * 256) + reg_1e_17_end);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x18,
+ (reg_1e_18_header * 256) + reg_1e_18_end);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x19,
+ (reg_1e_19_read & 0x00ff) + (reg_1e_19_header * 256));
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x20,
+ (reg_1e_20_read & 0xff00) + reg_1e_20_end);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x21,
+ (reg_1e_21_read & 0x00ff) + (reg_1e_21_header * 256));
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x22,
+ (reg_1e_22_read & 0xff00) + reg_1e_22_end);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x174,
+ 0x8080 + (reg_1e_174_header * 256) + reg_1e_174_end);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x175,
+ 0x8080 + (reg_1e_175_header * 256) + reg_1e_175_end);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x176, 0x4400);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x177, 0x0044);
+
+ return 0;
+}
+
+static int an7581_phy_config_init(struct phy_device *phydev)
+{
+ struct airoha_socphy_shared *shared = phy_package_get_priv(phydev);
+ struct phy_device *phydev_p0;
+ u32 soc_pdidr;
+ u8 phy_offset;
+ int ret;
+
+ phydev_p0 = shared->phydev_p0;
+ phy_offset = phydev->mdio.addr - phydev_p0->mdio.addr;
+
+ /* FIXME: Read SoC PDIDR if available or default to 1 */
+ soc_pdidr = 1;
+
+ shared->mdi_resister_type = MDI_5R;
+ if (soc_pdidr == 1)
+ shared->tx_amp_compensation_tbl = &an7581_tx_amp_compensation_tbl[0];
+ else
+ shared->tx_amp_compensation_tbl = &an7581_tx_amp_compensation_tbl[1];
+ shared->r50_cal_tbl = an7581_zcal_to_r45ohm;
+
+ ret = airoha_phy_calib(phydev);
+ if (ret)
+ return ret;
+
+ ret = airoha_phy_auto_select_transformer(phydev);
+ if (ret)
+ return ret;
+
+ ret = airoha_phy_tx_amp_compensation(phydev);
+ if (ret)
+ return ret;
+
+ /* RX setting for 5R_TXMR before AN setting */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xe6, 0x1111);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xe7, 0x5555);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xe9, 0x0001);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xfe, 0x0000);
+
+ /* Long Loop Reach setting */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x11, 0xff00);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x202, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x203, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x204, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x205, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x206, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x207, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x208, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x209, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x20a, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x20b, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x20e, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x20f, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x210, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x211, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x212, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x213, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x214, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x215, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x216, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x217, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x21a, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x21b, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x21c, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x21d, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x21e, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x21f, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x220, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x221, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x222, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x223, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x226, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x227, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x228, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x229, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x22a, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x22b, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x22c, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x22d, 0x0025);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x22e, 0x2310);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x22f, 0x0025);
+
+ /* RX Setting */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3c, 0xc000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3d, 0x0000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3e, 0xc000);
+
+ /* EEE setting */
+ phy_write_mmd(phydev, MDIO_MMD_AN, 0x3c, 0x0000);
+
+ /* RX */
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x41, 0x3333);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x44, 0x00c0);
+
+ /* 10M settings */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x1a3, 0x00d2);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x1a4, 0x010e);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x27b, 0x1177);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x27c, 0x0808);
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_1);
+ __phy_write(phydev, 0x14, 0x3a18);
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ phy_write(phydev, 0x9, 0x1e00);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x269, 0x2114);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x26a, 0x1113);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x26f, 0x0000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x271, 0x2c63);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x272, 0x0c2b);
+
+ /* EEE set because power down can't set tokenring */
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ __mtk_tr_write(phydev, 0x0, 0x7, 0x15, 0x0055a0);
+ __mtk_tr_write(phydev, 0x0, 0x7, 0x17, 0x07ff3f);
+ __mtk_tr_write(phydev, 0x1, 0xf, 0x0, 0x00001e);
+ __mtk_tr_write(phydev, 0x1, 0xf, 0x1, 0x6fb90a);
+ __mtk_tr_write(phydev, 0x1, 0xf, 0x18, 0x0e2f00);
+ __mtk_tr_write(phydev, 0x1, 0xd, 0x26, 0x444444);
+ __mtk_tr_write(phydev, 0x2, 0xd, 0x3, 0x000004);
+ __mtk_tr_write(phydev, 0x2, 0xd, 0x6, 0x2ebaef);
+ __mtk_tr_write(phydev, 0x2, 0xd, 0x8, 0x00000b);
+ __mtk_tr_write(phydev, 0x2, 0xd, 0xc, 0x00504d);
+ __mtk_tr_write(phydev, 0x2, 0xd, 0xd, 0x02314f);
+ __mtk_tr_write(phydev, 0x2, 0xd, 0xf, 0x003028);
+ __mtk_tr_write(phydev, 0x2, 0xd, 0x10, 0x00000a);
+ __mtk_tr_write(phydev, 0x2, 0xd, 0x11, 0x040001);
+ __mtk_tr_write(phydev, 0x2, 0xd, 0x14, 0x00024a);
+ __mtk_tr_write(phydev, 0x2, 0xd, 0x1c, 0x003210);
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x120, 0x8014);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x122, 0xffff);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x144, 0x0200);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14a, 0xee20);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x19b, 0x0111);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x234, 0x1181);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x238, 0x0120);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x239, 0x0117);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x2d1, 0x0733);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x323, 0x0011);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x324, 0x013f);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x326, 0x0037);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x268, 0x07f4);
+
+ if (shared->transformer_type[phy_offset] == TXMR) {
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x00, 0x0187);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01, 0x01cc);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x02, 0x01c2);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x03, 0x0109);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x04, 0x020b);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0202);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x06, 0x0387);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x07, 0x03c5);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x08, 0x03c2);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x09, 0x0309);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0a, 0x000e);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0b, 0x0002);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x23, 0x0880);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x24, 0x0880);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x25, 0x0880);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x26, 0x0880);
+ } else {
+ if (soc_pdidr == 2) {
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x269, 0x1114);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x26a, 0x1113);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x26f, 0x2000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x271, 0x4c88);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x272, 0x0c2b);
+
+ /* 100M sharp */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x00, 0x0190);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01, 0x01c8);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x02, 0x01c0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x03, 0x0030);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x04, 0x0208);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x06, 0x0318);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x07, 0x03c8);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x08, 0x03c0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x09, 0x0230);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0a, 0x0008);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0b, 0x0200);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x23, 0x0885);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x24, 0x0885);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x25, 0x0885);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x26, 0x0885);
+ } else {
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x00, 0x0190);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01, 0x01cf);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x02, 0x01c0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x03, 0x0030);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x04, 0x020f);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0000);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x06, 0x0318);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x07, 0x03cf);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x08, 0x03c0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x09, 0x0230);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0a, 0x000f);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0b, 0x0200);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x23, 0x0003);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x24, 0x0003);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x25, 0x0003);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x26, 0x0003);
+ }
+ }
+
+ return 0;
+}
+
static int an7581_phy_probe(struct phy_device *phydev)
{
+ struct airoha_socphy_shared *shared;
struct mtk_socphy_priv *priv;
struct pinctrl *pinctrl;
+ int ret;
/* Toggle pinctrl to enable PHY LED */
pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
@@ -18,10 +1495,18 @@ static int an7581_phy_probe(struct phy_device *phydev)
dev_err(&phydev->mdio.bus->dev,
"Failed to setup PHY LED pinctrl\n");
+ ret = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
+ sizeof(struct airoha_socphy_shared));
+ if (ret)
+ return ret;
+
priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+ if (phydev->mdio.addr == AIROHA_DEFAULT_PORT0_ADDR)
+ shared->phydev_p0 = phydev;
+
phydev->priv = priv;
return 0;
@@ -63,6 +1548,7 @@ static struct phy_driver mtk_socphy_driver[] = {
{
PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_AN7581),
.name = "Airoha AN7581 PHY",
+ .config_init = an7581_phy_config_init,
.config_intr = genphy_no_config_intr,
.handle_interrupt = genphy_handle_interrupt_no_ack,
.probe = an7581_phy_probe,
@@ -72,6 +1558,8 @@ static struct phy_driver mtk_socphy_driver[] = {
.led_hw_control_set = mt798x_phy_led_hw_control_set,
.led_hw_control_get = mt798x_phy_led_hw_control_get,
.led_polarity_set = an7581_phy_led_polarity_set,
+ .read_page = mtk_phy_read_page,
+ .write_page = mtk_phy_write_page,
},
{
PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_AN7583),
@@ -98,5 +1586,6 @@ static const struct mdio_device_id __maybe_unused airoha_socphy_tbl[] = {
MODULE_DESCRIPTION("Airoha SoC Gigabit Ethernet PHY driver");
MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
MODULE_LICENSE("GPL");
+MODULE_VERSION("01.01.20260306");
MODULE_DEVICE_TABLE(mdio, airoha_socphy_tbl);
diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.h b/drivers/net/phy/mediatek/mtk-ge-soc.h
index 507e68343576..5e9d24a9833c 100644
--- a/drivers/net/phy/mediatek/mtk-ge-soc.h
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.h
@@ -12,6 +12,7 @@
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_STANDARD 0x0000
+#define MTK_PHY_PAGE_EXTENDED_1 0x0001
#define MTK_PHY_PAGE_EXTENDED_3 0x0003
#define MTK_PHY_LPI_REG_14 0x14
@@ -177,6 +178,7 @@
#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
#define MTK_PHY_RG_CAL_CKINV BIT(12)
#define MTK_PHY_RG_ANA_CALEN BIT(8)
+#define MTK_PHY_RG_REXT_CALEN BIT(4)
#define MTK_PHY_RG_ZCALEN_A BIT(0)
#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
@@ -187,6 +189,9 @@
#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
+#define MTK_PHY_RG_REXT_ZCAL_CTRL_MASK GENMASK(5, 0)
+
+#define MTK_PHY_RG_ANA_CAL_RG6 0xe1
#define MTK_PHY_RG_TX_FILTER 0xfe
@@ -208,6 +213,14 @@
#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
+#define MTK_PHY_RG_CR_TX_R50_OFFSET_A_B 0x174
+#define MTK_PHY_CR_TX_R50_OFFSET_A_MASK GENMASK(13, 8)
+#define MTK_PHY_CR_TX_R50_OFFSET_B_MASK GENMASK(6, 0)
+
+#define MTK_PHY_RG_CR_TX_R50_OFFSET_C_D 0x175
+#define MTK_PHY_CR_TX_R50_OFFSET_C_MASK GENMASK(13, 8)
+#define MTK_PHY_CR_TX_R50_OFFSET_D_MASK GENMASK(6, 0)
+
#define MTK_PHY_RG_AD_CAL_COMP 0x17a
#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8)
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 3/5] net: phy: mediatek: split Airoha code to dedicated source
From: Christian Marangi @ 2026-07-08 10:23 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Christian Marangi,
Daniel Golle, Qingfang Deng, SkyLake Huang, Matthias Brugger,
AngeloGioacchino Del Regno, linux-kernel, netdev,
linux-arm-kernel, linux-mediatek
In-Reply-To: <20260708102341.53919-1-ansuelsmth@gmail.com>
In preparation for Airoha PHYs software calibration support, split the
Airoha code to dedicated source following Mediatek naming pattern of
"ge-soc".
This is to tidy things up and not overload the mediatek driver of specific
Airoha code and ship a bigger PHY kernel module with dead code.
Move the shared LEDs function to mtk-phy-lib to permit the split instead of
duplicating the code.
Also add myself as MAINTAINER of the now new airoha-ge-soc driver.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
MAINTAINERS | 8 ++
drivers/net/phy/mediatek/Kconfig | 16 ++-
drivers/net/phy/mediatek/Makefile | 1 +
drivers/net/phy/mediatek/airoha-ge-soc.c | 102 ++++++++++++++++
drivers/net/phy/mediatek/mtk-ge-soc.c | 146 -----------------------
drivers/net/phy/mediatek/mtk-ge-soc.h | 4 +-
drivers/net/phy/mediatek/mtk-phy-lib.c | 72 +++++++++++
drivers/net/phy/mediatek/mtk.h | 12 ++
8 files changed, 211 insertions(+), 150 deletions(-)
create mode 100644 drivers/net/phy/mediatek/airoha-ge-soc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 16e47aea84c3..e914bccf5cbb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -760,6 +760,14 @@ S: Maintained
F: Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
F: drivers/net/ethernet/airoha/
+AIROHA ETHERNET PHY DRIVER
+M: Christian Marangi <ansuelsmth@gmail.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
+L: netdev@vger.kernel.org
+S: Maintained
+F: drivers/net/phy/mediatek/airoha-ge-soc.c
+
AIROHA PCIE PHY DRIVER
M: Lorenzo Bianconi <lorenzo@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kconfig
index bb7dc876271e..fe51f4616c54 100644
--- a/drivers/net/phy/mediatek/Kconfig
+++ b/drivers/net/phy/mediatek/Kconfig
@@ -1,4 +1,17 @@
# SPDX-License-Identifier: GPL-2.0-only
+config AIROHA_GE_SOC_PHY
+ tristate "Airoha SoC Ethernet PHYs"
+ depends on ARM64 || COMPILE_TEST
+ depends on ARCH_AIROHA || COMPILE_TEST
+ select MTK_NET_PHYLIB
+ select PHY_PACKAGE
+ help
+ Supports Airoha SoC built-in Gigabit Ethernet PHYs.
+
+ Include support for built-in Ethernet PHYs which are present in
+ the AN7581 and AN7583 SoCs. These PHYs d will dynamically
+ calibrate during startup.
+
config MEDIATEK_2P5GE_PHY
tristate "MediaTek 2.5Gb Ethernet PHYs"
depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
@@ -24,8 +37,7 @@ config MEDIATEK_GE_PHY
config MEDIATEK_GE_SOC_PHY
tristate "MediaTek SoC Ethernet PHYs"
depends on ARM64 || COMPILE_TEST
- depends on ARCH_AIROHA || (ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || \
- COMPILE_TEST
+ depends on (ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || COMPILE_TEST
select MTK_NET_PHYLIB
select PHY_PACKAGE
help
diff --git a/drivers/net/phy/mediatek/Makefile b/drivers/net/phy/mediatek/Makefile
index ac57ecc799fc..eb430f008169 100644
--- a/drivers/net/phy/mediatek/Makefile
+++ b/drivers/net/phy/mediatek/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_AIROHA_GE_SOC_PHY) += airoha-ge-soc.o
obj-$(CONFIG_MEDIATEK_2P5GE_PHY) += mtk-2p5ge.o
obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o
diff --git a/drivers/net/phy/mediatek/airoha-ge-soc.c b/drivers/net/phy/mediatek/airoha-ge-soc.c
new file mode 100644
index 000000000000..429594f27792
--- /dev/null
+++ b/drivers/net/phy/mediatek/airoha-ge-soc.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <linux/pinctrl/consumer.h>
+#include <linux/phy.h>
+
+#include "mtk.h"
+#include "mtk-ge-soc.h"
+
+#define AIROHA_PHY_MAX_LEDS 2
+
+static int an7581_phy_probe(struct phy_device *phydev)
+{
+ struct mtk_socphy_priv *priv;
+ struct pinctrl *pinctrl;
+
+ /* Toggle pinctrl to enable PHY LED */
+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
+ if (IS_ERR(pinctrl))
+ dev_err(&phydev->mdio.bus->dev,
+ "Failed to setup PHY LED pinctrl\n");
+
+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index,
+ unsigned long modes)
+{
+ u16 val = 0;
+ u32 mode;
+
+ if (index >= AIROHA_PHY_MAX_LEDS)
+ return -EINVAL;
+
+ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+ switch (mode) {
+ case PHY_LED_ACTIVE_LOW:
+ val = MTK_PHY_LED_ON_POLARITY;
+ break;
+ case PHY_LED_ACTIVE_HIGH:
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
+ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
+ MTK_PHY_LED_ON_POLARITY, val);
+}
+
+static int an7583_phy_config_init(struct phy_device *phydev)
+{
+ /* BMCR_PDOWN is enabled by default */
+ return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
+}
+
+static struct phy_driver mtk_socphy_driver[] = {
+ {
+ PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_AN7581),
+ .name = "Airoha AN7581 PHY",
+ .config_intr = genphy_no_config_intr,
+ .handle_interrupt = genphy_handle_interrupt_no_ack,
+ .probe = an7581_phy_probe,
+ .led_blink_set = mt798x_phy_led_blink_set,
+ .led_brightness_set = mt798x_phy_led_brightness_set,
+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
+ .led_hw_control_set = mt798x_phy_led_hw_control_set,
+ .led_hw_control_get = mt798x_phy_led_hw_control_get,
+ .led_polarity_set = an7581_phy_led_polarity_set,
+ },
+ {
+ PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_AN7583),
+ .name = "Airoha AN7583 PHY",
+ .config_init = an7583_phy_config_init,
+ .probe = an7581_phy_probe,
+ .led_blink_set = mt798x_phy_led_blink_set,
+ .led_brightness_set = mt798x_phy_led_brightness_set,
+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
+ .led_hw_control_set = mt798x_phy_led_hw_control_set,
+ .led_hw_control_get = mt798x_phy_led_hw_control_get,
+ .led_polarity_set = an7581_phy_led_polarity_set,
+ },
+};
+
+module_phy_driver(mtk_socphy_driver);
+
+static const struct mdio_device_id __maybe_unused airoha_socphy_tbl[] = {
+ { PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_AN7581) },
+ { PHY_ID_MATCH_EXACT(AIROHA_GPHY_ID_AN7583) },
+ { }
+};
+
+MODULE_DESCRIPTION("Airoha SoC Gigabit Ethernet PHY driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
+
+MODULE_DEVICE_TABLE(mdio, airoha_socphy_tbl);
diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c
index 46bae11ad740..868ae089013d 100644
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -886,73 +886,6 @@ static int mt798x_phy_config_init(struct phy_device *phydev)
return mt798x_phy_calibration(phydev);
}
-static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
- unsigned long *delay_on,
- unsigned long *delay_off)
-{
- bool blinking = false;
- int err;
-
- err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
- if (err < 0)
- return err;
-
- err = mtk_phy_hw_led_blink_set(phydev, index, blinking);
- if (err)
- return err;
-
- return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
- false);
-}
-
-static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
- u8 index, enum led_brightness value)
-{
- int err;
-
- err = mtk_phy_hw_led_blink_set(phydev, index, false);
- if (err)
- return err;
-
- return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
- (value != LED_OFF));
-}
-
-static const unsigned long supported_triggers =
- BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
- BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
- BIT(TRIGGER_NETDEV_LINK) |
- BIT(TRIGGER_NETDEV_LINK_10) |
- BIT(TRIGGER_NETDEV_LINK_100) |
- BIT(TRIGGER_NETDEV_LINK_1000) |
- BIT(TRIGGER_NETDEV_RX) |
- BIT(TRIGGER_NETDEV_TX);
-
-static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
- unsigned long rules)
-{
- return mtk_phy_led_hw_is_supported(phydev, index, rules,
- supported_triggers);
-}
-
-static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
- unsigned long *rules)
-{
- return mtk_phy_led_hw_ctrl_get(phydev, index, rules,
- MTK_GPHY_LED_ON_SET,
- MTK_GPHY_LED_RX_BLINK_SET,
- MTK_GPHY_LED_TX_BLINK_SET);
-};
-
-static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
- unsigned long rules)
-{
- return mtk_phy_led_hw_ctrl_set(phydev, index, rules,
- MTK_GPHY_LED_ON_SET,
- MTK_GPHY_LED_RX_BLINK_SET,
- MTK_GPHY_LED_TX_BLINK_SET);
-};
-
static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
{
struct mtk_socphy_shared *priv = phy_package_get_priv(phydev);
@@ -1089,58 +1022,6 @@ static int mt7981_phy_probe(struct phy_device *phydev)
return mt798x_phy_calibration(phydev);
}
-static int an7581_phy_probe(struct phy_device *phydev)
-{
- struct mtk_socphy_priv *priv;
- struct pinctrl *pinctrl;
-
- /* Toggle pinctrl to enable PHY LED */
- pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
- if (IS_ERR(pinctrl))
- dev_err(&phydev->mdio.bus->dev,
- "Failed to setup PHY LED pinctrl\n");
-
- priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
-
- phydev->priv = priv;
-
- return 0;
-}
-
-static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index,
- unsigned long modes)
-{
- u16 val = 0;
- u32 mode;
-
- if (index >= MTK_PHY_MAX_LEDS)
- return -EINVAL;
-
- for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
- switch (mode) {
- case PHY_LED_ACTIVE_LOW:
- val = MTK_PHY_LED_ON_POLARITY;
- break;
- case PHY_LED_ACTIVE_HIGH:
- break;
- default:
- return -EINVAL;
- }
- }
-
- return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
- MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
- MTK_PHY_LED_ON_POLARITY, val);
-}
-
-static int an7583_phy_config_init(struct phy_device *phydev)
-{
- /* BMCR_PDOWN is enabled by default */
- return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
-}
-
static struct phy_driver mtk_socphy_driver[] = {
{
PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
@@ -1176,31 +1057,6 @@ static struct phy_driver mtk_socphy_driver[] = {
.led_hw_control_set = mt798x_phy_led_hw_control_set,
.led_hw_control_get = mt798x_phy_led_hw_control_get,
},
- {
- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581),
- .name = "Airoha AN7581 PHY",
- .config_intr = genphy_no_config_intr,
- .handle_interrupt = genphy_handle_interrupt_no_ack,
- .probe = an7581_phy_probe,
- .led_blink_set = mt798x_phy_led_blink_set,
- .led_brightness_set = mt798x_phy_led_brightness_set,
- .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
- .led_hw_control_set = mt798x_phy_led_hw_control_set,
- .led_hw_control_get = mt798x_phy_led_hw_control_get,
- .led_polarity_set = an7581_phy_led_polarity_set,
- },
- {
- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7583),
- .name = "Airoha AN7583 PHY",
- .config_init = an7583_phy_config_init,
- .probe = an7581_phy_probe,
- .led_blink_set = mt798x_phy_led_blink_set,
- .led_brightness_set = mt798x_phy_led_brightness_set,
- .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
- .led_hw_control_set = mt798x_phy_led_hw_control_set,
- .led_hw_control_get = mt798x_phy_led_hw_control_get,
- .led_polarity_set = an7581_phy_led_polarity_set,
- },
};
module_phy_driver(mtk_socphy_driver);
@@ -1208,8 +1064,6 @@ module_phy_driver(mtk_socphy_driver);
static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
- { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581) },
- { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7583) },
{ }
};
diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.h b/drivers/net/phy/mediatek/mtk-ge-soc.h
index 9aaa7e3caa41..507e68343576 100644
--- a/drivers/net/phy/mediatek/mtk-ge-soc.h
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.h
@@ -7,8 +7,8 @@
#define MTK_GPHY_ID_MT7981 0x03a29461
#define MTK_GPHY_ID_MT7988 0x03a29481
-#define MTK_GPHY_ID_AN7581 0x03a294c1
-#define MTK_GPHY_ID_AN7583 0xc0ff0420
+#define AIROHA_GPHY_ID_AN7581 0x03a294c1
+#define AIROHA_GPHY_ID_AN7583 0xc0ff0420
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_STANDARD 0x0000
diff --git a/drivers/net/phy/mediatek/mtk-phy-lib.c b/drivers/net/phy/mediatek/mtk-phy-lib.c
index 78b998af5238..8c2b26f9b840 100644
--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
@@ -342,6 +342,78 @@ void mtk_phy_leds_state_init(struct phy_device *phydev)
}
EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init);
+int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
+ unsigned long *delay_on,
+ unsigned long *delay_off)
+{
+ bool blinking = false;
+ int err;
+
+ err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
+ if (err < 0)
+ return err;
+
+ err = mtk_phy_hw_led_blink_set(phydev, index, blinking);
+ if (err)
+ return err;
+
+ return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
+ false);
+}
+EXPORT_SYMBOL_GPL(mt798x_phy_led_blink_set);
+
+int mt798x_phy_led_brightness_set(struct phy_device *phydev,
+ u8 index, enum led_brightness value)
+{
+ int err;
+
+ err = mtk_phy_hw_led_blink_set(phydev, index, false);
+ if (err)
+ return err;
+
+ return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
+ (value != LED_OFF));
+}
+EXPORT_SYMBOL_GPL(mt798x_phy_led_brightness_set);
+
+static const unsigned long supported_triggers =
+ BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
+ BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
+ BIT(TRIGGER_NETDEV_LINK) |
+ BIT(TRIGGER_NETDEV_LINK_10) |
+ BIT(TRIGGER_NETDEV_LINK_100) |
+ BIT(TRIGGER_NETDEV_LINK_1000) |
+ BIT(TRIGGER_NETDEV_RX) |
+ BIT(TRIGGER_NETDEV_TX);
+
+int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+{
+ return mtk_phy_led_hw_is_supported(phydev, index, rules,
+ supported_triggers);
+}
+EXPORT_SYMBOL_GPL(mt798x_phy_led_hw_is_supported);
+
+int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
+ unsigned long *rules)
+{
+ return mtk_phy_led_hw_ctrl_get(phydev, index, rules,
+ MTK_GPHY_LED_ON_SET,
+ MTK_GPHY_LED_RX_BLINK_SET,
+ MTK_GPHY_LED_TX_BLINK_SET);
+};
+EXPORT_SYMBOL_GPL(mt798x_phy_led_hw_control_get);
+
+int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+{
+ return mtk_phy_led_hw_ctrl_set(phydev, index, rules,
+ MTK_GPHY_LED_ON_SET,
+ MTK_GPHY_LED_RX_BLINK_SET,
+ MTK_GPHY_LED_TX_BLINK_SET);
+};
+EXPORT_SYMBOL_GPL(mt798x_phy_led_hw_control_set);
+
MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common");
MODULE_AUTHOR("Sky Huang <SkyLake.Huang@mediatek.com>");
MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
diff --git a/drivers/net/phy/mediatek/mtk.h b/drivers/net/phy/mediatek/mtk.h
index f172f7d671c9..c690aaf38124 100644
--- a/drivers/net/phy/mediatek/mtk.h
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -103,4 +103,16 @@ int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
bool blinking);
void mtk_phy_leds_state_init(struct phy_device *phydev);
+int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
+ unsigned long *delay_on,
+ unsigned long *delay_off);
+int mt798x_phy_led_brightness_set(struct phy_device *phydev,
+ u8 index, enum led_brightness value);
+int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules);
+int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
+ unsigned long *rules);
+int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
+ unsigned long rules);
+
#endif /* _MTK_EPHY_H_ */
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 2/5] net: phy: mediatek: move MTK GE SoC registers define to dedicated header
From: Christian Marangi @ 2026-07-08 10:23 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Christian Marangi,
Daniel Golle, Qingfang Deng, SkyLake Huang, Matthias Brugger,
AngeloGioacchino Del Regno, linux-kernel, netdev,
linux-arm-kernel, linux-mediatek
In-Reply-To: <20260708102341.53919-1-ansuelsmth@gmail.com>
In preparation for support of special Software Calibration for Airoha
PHY, move the MTK GE SoC registers define to a dedicated header.
It's also needed to generalize the cal_cycle function as Airoha needs
only part of its logic (the wait logic) to complete a calibration cycle.
This is to keep cleaner code and permit sharing these define in multiple
source code.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
MAINTAINERS | 1 +
drivers/net/phy/mediatek/mtk-ge-soc.c | 371 ++------------------------
drivers/net/phy/mediatek/mtk-ge-soc.h | 351 ++++++++++++++++++++++++
3 files changed, 373 insertions(+), 350 deletions(-)
create mode 100644 drivers/net/phy/mediatek/mtk-ge-soc.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c3f72058a2f2..16e47aea84c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16512,6 +16512,7 @@ L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/phy/mediatek/mtk-2p5ge.c
F: drivers/net/phy/mediatek/mtk-ge-soc.c
+F: drivers/net/phy/mediatek/mtk-ge-soc.h
F: drivers/net/phy/mediatek/mtk-phy-lib.c
F: drivers/net/phy/mediatek/mtk-ge.c
F: drivers/net/phy/mediatek/mtk.h
diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c
index 9a54949644d5..46bae11ad740 100644
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -11,322 +11,10 @@
#include "../phylib.h"
#include "mtk.h"
+#include "mtk-ge-soc.h"
#define MTK_PHY_MAX_LEDS 2
-#define MTK_GPHY_ID_MT7981 0x03a29461
-#define MTK_GPHY_ID_MT7988 0x03a29481
-#define MTK_GPHY_ID_AN7581 0x03a294c1
-#define MTK_GPHY_ID_AN7583 0xc0ff0420
-
-#define MTK_EXT_PAGE_ACCESS 0x1f
-#define MTK_PHY_PAGE_STANDARD 0x0000
-#define MTK_PHY_PAGE_EXTENDED_3 0x0003
-
-#define MTK_PHY_LPI_REG_14 0x14
-#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
-
-#define MTK_PHY_LPI_REG_1c 0x1c
-#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
-
-#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
-
-/* Registers on Token Ring debug nodes */
-/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
-/* NormMseLoThresh */
-#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8)
-
-/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
-/* RemAckCntLimitCtrl */
-#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1)
-
-/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
-/* VcoSlicerThreshBitsHigh */
-#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0)
-
-/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
-/* DfeTailEnableVgaThresh1000 */
-#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1)
-
-/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
-/* MrvlTrFix100Kp */
-#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20)
-/* MrvlTrFix100Kf */
-#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17)
-/* MrvlTrFix1000Kp */
-#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14)
-/* MrvlTrFix1000Kf */
-#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11)
-
-/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
-/* VgaDecRate */
-#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5)
-
-/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
-/* SlvDSPreadyTime */
-#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
-/* MasDSPreadyTime */
-#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)
-
-/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
-/* EnabRandUpdTrig */
-#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8)
-
-/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
-/* ResetSyncOffset */
-#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)
-
-/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
-/* FfeUpdGainForceVal */
-#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7)
-/* FfeUpdGainForce */
-#define FFE_UPDATE_GAIN_FORCE BIT(6)
-
-/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
-/* TrFreeze */
-#define TR_FREEZE_MASK GENMASK(11, 0)
-
-/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
-/* SS: Steady-state, KP: Proportional Gain */
-/* SSTrKp100 */
-#define SS_TR_KP100_MASK GENMASK(21, 19)
-/* SSTrKf100 */
-#define SS_TR_KF100_MASK GENMASK(18, 16)
-/* SSTrKp1000Mas */
-#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13)
-/* SSTrKf1000Mas */
-#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10)
-/* SSTrKp1000Slv */
-#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7)
-/* SSTrKf1000Slv */
-#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)
-
-/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
-/* clear this bit if wanna select from AFE */
-/* Regsigdet_sel_1000 */
-#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4)
-
-/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
-/* RegEEE_st2TrKf1000 */
-#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)
-
-/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
-/* RegEEE_slv_waketr_timer_tar */
-#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11)
-/* RegEEE_slv_remtx_timer_tar */
-#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1)
-
-/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
-/* RegEEE_slv_wake_int_timer_tar */
-#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1)
-
-/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
-/* RegEEE_trfreeze_timer2 */
-#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0)
-
-/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
-/* RegEEE100Stg1_tar */
-#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
-
-/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
-/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
-#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11)
-
-#define ANALOG_INTERNAL_OPERATION_MAX_US 20
-#define TXRESERVE_MIN 0
-#define TXRESERVE_MAX 7
-
-#define MTK_PHY_ANARG_RG 0x10
-#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
-
-/* Registers on MDIO_MMD_VEND1 */
-#define MTK_PHY_TXVLD_DA_RG 0x12
-#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
-#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
-#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
-#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
-#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
-#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
-#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
-#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
-#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
-#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
-
-#define MTK_PHY_RXADC_CTRL_RG7 0xc6
-#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
-
-#define MTK_PHY_RXADC_CTRL_RG9 0xc8
-#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
-#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
-#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
-#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
-
-#define MTK_PHY_LDO_OUTPUT_V 0xd7
-
-#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
-#define MTK_PHY_RG_CAL_CKINV BIT(12)
-#define MTK_PHY_RG_ANA_CALEN BIT(8)
-#define MTK_PHY_RG_ZCALEN_A BIT(0)
-
-#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
-#define MTK_PHY_RG_ZCALEN_B BIT(12)
-#define MTK_PHY_RG_ZCALEN_C BIT(8)
-#define MTK_PHY_RG_ZCALEN_D BIT(4)
-#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
-
-#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
-#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
-
-#define MTK_PHY_RG_TX_FILTER 0xfe
-
-#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
-#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
-#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
-
-#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
-#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
-
-#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
-#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
-
-#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
-#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
-#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
-
-#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
-#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
-#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
-
-#define MTK_PHY_RG_AD_CAL_COMP 0x17a
-#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8)
-
-#define MTK_PHY_RG_AD_CAL_CLK 0x17b
-#define MTK_PHY_DA_CAL_CLK BIT(0)
-
-#define MTK_PHY_RG_AD_CALIN 0x17c
-#define MTK_PHY_DA_CALIN_FLAG BIT(0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
-#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
-#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
-#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
-#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
-#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
-#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
-#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
-#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DEV1E_REG19b 0x19b
-#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
-
-#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
-#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
-#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
-#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
-#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
-#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
-#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
-#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
-#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
-#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
-
-#define MTK_PHY_RG_DEV1E_REG234 0x234
-#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
-#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
-#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
-
-#define MTK_PHY_RG_LPF_CNT_VAL 0x235
-
-#define MTK_PHY_RG_DEV1E_REG238 0x238
-#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
-#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
-
-#define MTK_PHY_RG_DEV1E_REG239 0x239
-#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
-#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
-
-#define MTK_PHY_RG_DEV1E_REG27C 0x27c
-#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
-#define MTK_PHY_RG_DEV1E_REG27D 0x27d
-#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
-
-#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
-#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
-#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
-
-#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
-#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
-#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
-#define MTK_PHY_LPI_TR_READY BIT(9)
-#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
-
-#define MTK_PHY_RG_DEV1E_REG323 0x323
-#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
-#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
-
-#define MTK_PHY_RG_DEV1E_REG324 0x324
-#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
-#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
-
-#define MTK_PHY_RG_DEV1E_REG326 0x326
-#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
-#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
-#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
-#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
-#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
-
-#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
-#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
-
-#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
-#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
-#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
-#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
-
-/* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
-
-#define MTK_PHY_RG_BG_RASEL 0x115
-#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
-
-/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
-#define RG_GPIO_MISC_TPBANK0 0x6f0
-#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
-
/* These macro privides efuse parsing for internal phy. */
#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
@@ -346,51 +34,16 @@
#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
-enum {
- NO_PAIR,
- PAIR_A,
- PAIR_B,
- PAIR_C,
- PAIR_D,
-};
-
-enum calibration_mode {
- EFUSE_K,
- SW_K
-};
-
-enum CAL_ITEM {
- REXT,
- TX_OFFSET,
- TX_AMP,
- TX_R50,
- TX_VCM
-};
-
-enum CAL_MODE {
- EFUSE_M,
- SW_M
-};
-
struct mtk_socphy_shared {
u32 boottrap;
struct mtk_socphy_priv priv[4];
};
-/* One calibration cycle consists of:
- * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
- * until AD_CAL_COMP is ready to output calibration result.
- * 2.Wait until DA_CAL_CLK is available.
- * 3.Fetch AD_CAL_COMP_OUT.
- */
-static int cal_cycle(struct phy_device *phydev, int devad,
- u32 regnum, u16 mask, u16 cal_val)
+int mtk_cal_cycle_wait(struct phy_device *phydev)
{
int reg_val;
int ret;
- phy_modify_mmd(phydev, devad, regnum,
- mask, cal_val);
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
MTK_PHY_DA_CALIN_FLAG);
@@ -409,7 +62,25 @@ static int cal_cycle(struct phy_device *phydev, int devad,
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP);
if (ret < 0)
return ret;
- ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret);
+
+ return FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret);
+}
+
+/* One calibration cycle consists of:
+ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
+ * until AD_CAL_COMP is ready to output calibration result.
+ * 2.Wait until DA_CAL_CLK is available.
+ * 3.Fetch AD_CAL_COMP_OUT.
+ */
+static int cal_cycle(struct phy_device *phydev, int devad,
+ u32 regnum, u16 mask, u16 cal_val)
+{
+ int ret;
+
+ phy_modify_mmd(phydev, devad, regnum,
+ mask, cal_val);
+
+ ret = mtk_cal_cycle_wait(phydev);
phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
return ret;
diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.h b/drivers/net/phy/mediatek/mtk-ge-soc.h
new file mode 100644
index 000000000000..9aaa7e3caa41
--- /dev/null
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.h
@@ -0,0 +1,351 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _MTK_GE_SOC_H_
+#define _MTK_GE_SOC_H_
+
+#include <linux/bitfield.h>
+
+#define MTK_GPHY_ID_MT7981 0x03a29461
+#define MTK_GPHY_ID_MT7988 0x03a29481
+#define MTK_GPHY_ID_AN7581 0x03a294c1
+#define MTK_GPHY_ID_AN7583 0xc0ff0420
+
+#define MTK_EXT_PAGE_ACCESS 0x1f
+#define MTK_PHY_PAGE_STANDARD 0x0000
+#define MTK_PHY_PAGE_EXTENDED_3 0x0003
+
+#define MTK_PHY_LPI_REG_14 0x14
+#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
+
+#define MTK_PHY_LPI_REG_1c 0x1c
+#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
+
+#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+
+/* Registers on Token Ring debug nodes */
+/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
+/* NormMseLoThresh */
+#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8)
+
+/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
+/* RemAckCntLimitCtrl */
+#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1)
+
+/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
+/* VcoSlicerThreshBitsHigh */
+#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
+/* DfeTailEnableVgaThresh1000 */
+#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
+/* MrvlTrFix100Kp */
+#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20)
+/* MrvlTrFix100Kf */
+#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17)
+/* MrvlTrFix1000Kp */
+#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14)
+/* MrvlTrFix1000Kf */
+#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
+/* VgaDecRate */
+#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
+/* SlvDSPreadyTime */
+#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
+/* MasDSPreadyTime */
+#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
+/* EnabRandUpdTrig */
+#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
+/* ResetSyncOffset */
+#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
+/* FfeUpdGainForceVal */
+#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7)
+/* FfeUpdGainForce */
+#define FFE_UPDATE_GAIN_FORCE BIT(6)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
+/* TrFreeze */
+#define TR_FREEZE_MASK GENMASK(11, 0)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
+/* SS: Steady-state, KP: Proportional Gain */
+/* SSTrKp100 */
+#define SS_TR_KP100_MASK GENMASK(21, 19)
+/* SSTrKf100 */
+#define SS_TR_KF100_MASK GENMASK(18, 16)
+/* SSTrKp1000Mas */
+#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13)
+/* SSTrKf1000Mas */
+#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10)
+/* SSTrKp1000Slv */
+#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7)
+/* SSTrKf1000Slv */
+#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
+/* clear this bit if wanna select from AFE */
+/* Regsigdet_sel_1000 */
+#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
+/* RegEEE_st2TrKf1000 */
+#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
+/* RegEEE_slv_waketr_timer_tar */
+#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11)
+/* RegEEE_slv_remtx_timer_tar */
+#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
+/* RegEEE_slv_wake_int_timer_tar */
+#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
+/* RegEEE_trfreeze_timer2 */
+#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
+/* RegEEE100Stg1_tar */
+#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
+/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
+#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11)
+
+#define ANALOG_INTERNAL_OPERATION_MAX_US 20
+#define TXRESERVE_MIN 0
+#define TXRESERVE_MAX 7
+
+#define MTK_PHY_ANARG_RG 0x10
+#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
+
+/* Registers on MDIO_MMD_VEND1 */
+#define MTK_PHY_TXVLD_DA_RG 0x12
+#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
+#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
+
+#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
+#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
+#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
+
+#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
+#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
+#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
+
+#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
+#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
+#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
+
+#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
+#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
+#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
+
+#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
+#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
+#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
+
+#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
+#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
+#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
+
+#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
+#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
+#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
+
+#define MTK_PHY_RXADC_CTRL_RG7 0xc6
+#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
+
+#define MTK_PHY_RXADC_CTRL_RG9 0xc8
+#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
+#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
+#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
+#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
+
+#define MTK_PHY_LDO_OUTPUT_V 0xd7
+
+#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
+#define MTK_PHY_RG_CAL_CKINV BIT(12)
+#define MTK_PHY_RG_ANA_CALEN BIT(8)
+#define MTK_PHY_RG_ZCALEN_A BIT(0)
+
+#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
+#define MTK_PHY_RG_ZCALEN_B BIT(12)
+#define MTK_PHY_RG_ZCALEN_C BIT(8)
+#define MTK_PHY_RG_ZCALEN_D BIT(4)
+#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
+
+#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
+#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
+
+#define MTK_PHY_RG_TX_FILTER 0xfe
+
+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
+#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
+#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
+
+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
+#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
+
+#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
+#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
+
+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
+#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
+#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
+
+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
+#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
+#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
+
+#define MTK_PHY_RG_AD_CAL_COMP 0x17a
+#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8)
+
+#define MTK_PHY_RG_AD_CAL_CLK 0x17b
+#define MTK_PHY_DA_CAL_CLK BIT(0)
+
+#define MTK_PHY_RG_AD_CALIN 0x17c
+#define MTK_PHY_DA_CALIN_FLAG BIT(0)
+
+#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
+#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
+
+#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
+#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
+
+#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
+#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
+
+#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
+#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
+
+#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
+#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
+
+#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
+#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
+
+#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
+#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
+
+#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
+#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
+
+#define MTK_PHY_RG_DEV1E_REG19b 0x19b
+#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
+
+#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
+#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
+#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
+#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
+#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
+#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
+#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
+#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
+#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
+#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
+
+#define MTK_PHY_RG_DEV1E_REG234 0x234
+#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
+#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
+#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
+
+#define MTK_PHY_RG_LPF_CNT_VAL 0x235
+
+#define MTK_PHY_RG_DEV1E_REG238 0x238
+#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
+#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
+
+#define MTK_PHY_RG_DEV1E_REG239 0x239
+#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
+#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
+
+#define MTK_PHY_RG_DEV1E_REG27C 0x27c
+#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
+#define MTK_PHY_RG_DEV1E_REG27D 0x27d
+#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
+
+#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
+#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
+#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
+
+#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
+#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
+#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
+#define MTK_PHY_LPI_TR_READY BIT(9)
+#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
+
+#define MTK_PHY_RG_DEV1E_REG323 0x323
+#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
+#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
+
+#define MTK_PHY_RG_DEV1E_REG324 0x324
+#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
+#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
+
+#define MTK_PHY_RG_DEV1E_REG326 0x326
+#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
+#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
+#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
+#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
+#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
+
+#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
+#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
+
+#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
+#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
+#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
+#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
+
+/* Registers on MDIO_MMD_VEND2 */
+#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
+
+#define MTK_PHY_RG_BG_RASEL 0x115
+#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
+
+/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
+#define RG_GPIO_MISC_TPBANK0 0x6f0
+#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
+
+enum CAL_ITEM {
+ REXT,
+ TX_OFFSET,
+ TX_AMP,
+ TX_R50,
+ TX_VCM,
+ RX_OFFSET,
+};
+
+enum {
+ NO_PAIR,
+ PAIR_A,
+ PAIR_B,
+ PAIR_C,
+ PAIR_D,
+};
+
+enum calibration_mode {
+ EFUSE_K,
+ SW_K
+};
+
+enum CAL_MODE {
+ EFUSE_M,
+ SW_M
+};
+
+/* MTK GE SoC common functions */
+int mtk_cal_cycle_wait(struct phy_device *phydev);
+
+#endif /* _MTK_GE_SOC_H_ */
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 1/5] net: phy: mediatek: export __mtk_tr_write
From: Christian Marangi @ 2026-07-08 10:23 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Christian Marangi,
Daniel Golle, Qingfang Deng, SkyLake Huang, Matthias Brugger,
AngeloGioacchino Del Regno, linux-kernel, netdev,
linux-arm-kernel, linux-mediatek
In-Reply-To: <20260708102341.53919-1-ansuelsmth@gmail.com>
Export __mtk_tr_write to directly write to debug register.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/mediatek/mtk-phy-lib.c | 5 +++--
drivers/net/phy/mediatek/mtk.h | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/mediatek/mtk-phy-lib.c b/drivers/net/phy/mediatek/mtk-phy-lib.c
index dfd0f4e439a2..78b998af5238 100644
--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
@@ -36,8 +36,8 @@ static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
*tr_high, *tr_low);
}
-static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
- u8 data_addr, u32 tr_data)
+void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 tr_data)
{
__phy_write(phydev, 0x11, tr_data & 0xffff);
__phy_write(phydev, 0x12, tr_data >> 16);
@@ -45,6 +45,7 @@ static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
tr_data >> 16, tr_data & 0xffff);
__mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr);
}
+EXPORT_SYMBOL_GPL(__mtk_tr_write);
void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
u8 data_addr, u32 mask, u32 set)
diff --git a/drivers/net/phy/mediatek/mtk.h b/drivers/net/phy/mediatek/mtk.h
index 320f76ffa81f..f172f7d671c9 100644
--- a/drivers/net/phy/mediatek/mtk.h
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -72,6 +72,8 @@ struct mtk_socphy_priv {
unsigned long led_state;
};
+void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 tr_data);
void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
u8 data_addr, u32 mask, u32 set);
void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 0/5] net: phy: mediatek: calibration for AN7581/3
From: Christian Marangi @ 2026-07-08 10:23 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit, Russell King, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Christian Marangi,
Daniel Golle, Qingfang Deng, SkyLake Huang, Matthias Brugger,
AngeloGioacchino Del Regno, linux-kernel, netdev,
linux-arm-kernel, linux-mediatek
This small series adds calibration support for Airoha AN7581 and
AN7583 integrated PHYs.
The calibration logic is quite big so I decided to split
the driver from the mediatek one to keep things organized.
Minor change were needed and just additional symbol to use what
is common between mediatek and airoha PHYs.
I followed the naming pattern of mtk by calling the new source
airoha-ge-soc and related config.
The calibration use lots of static table and software calibration
at runtime instead of using efuse to calibrate.
There is one pecularity where some register and calibration needs
to be done on port0 first and then with the related port.
This is O.K. as port0 presence is mandatory for the functionality
of the integrated switch and it's assumed to be always present
on the MDIO bus.
MAINTAINERS is updated to reflect the changed code.
(this was tested from a long time and also verified by Airoha for
correct order of calibration)
Christian Marangi (5):
net: phy: mediatek: export __mtk_tr_write
net: phy: mediatek: move MTK GE SoC registers define to dedicated
header
net: phy: mediatek: split Airoha code to dedicated source
net: phy: mediatek: add calibration logic for AN7581
net: phy: mediatek: add calibration logic for AN7583
MAINTAINERS | 9 +
drivers/net/phy/mediatek/Kconfig | 16 +-
drivers/net/phy/mediatek/Makefile | 1 +
drivers/net/phy/mediatek/airoha-ge-soc.c | 1812 ++++++++++++++++++++++
drivers/net/phy/mediatek/mtk-ge-soc.c | 517 +-----
drivers/net/phy/mediatek/mtk-ge-soc.h | 364 +++++
drivers/net/phy/mediatek/mtk-phy-lib.c | 77 +-
drivers/net/phy/mediatek/mtk.h | 15 +
8 files changed, 2311 insertions(+), 500 deletions(-)
create mode 100644 drivers/net/phy/mediatek/airoha-ge-soc.c
create mode 100644 drivers/net/phy/mediatek/mtk-ge-soc.h
--
2.53.0
^ permalink raw reply
* Re: [PATCH v5 net 0/7] i40e: re-init and UAF fixes
From: Maciej Fijalkowski @ 2026-07-08 10:14 UTC (permalink / raw)
To: Paolo Abeni
Cc: intel-wired-lan, netdev, magnus.karlsson, kuba, horms,
przemyslaw.kitszel, jacob.e.keller
In-Reply-To: <1240f40e-ba1b-4773-bf65-facad8b4fc0c@redhat.com>
On Wed, Jul 08, 2026 at 10:51:54AM +0200, Paolo Abeni wrote:
> On 7/1/26 2:45 PM, Maciej Fijalkowski wrote:
> > v5:
> > - include three new patches to address last Sashiko review
> > *
> > - do not release the irq lump in rebuild path in patch 7
> > - clear dangling pointers from rx and xdp rings arrays
> > v4:
> > - add preceding patch that fixes a case when some of re-init allocations
> > failed and we missed de-registering netdev at failure path
> > - pull out i40e_vsi_setup() changes onto separate patch
> > v3:
> > - address UAF when ring arrays were freed before q_vector's ring
> > containers (Sashiko, Jacob)
> > - remove bool params from alloc/free array routines (Simon)
> > v2:
> > - NULL vsi->tx_rings in i40e_vsi_alloc_arrays() (Sashiko)
>
> FTR, I'm not 100% sure about the actual target here: the subj prefix
> point to the net tree, but the to recipient is IWL.
>
> Since this is not sent by Tony, I assume the real target is IWL and
> tentatively set the series to 'Awaiting upstream'. Note that for 'net'
> inclusion you will need an actual, not empty, cover letter.
Yeah should be iwl-net. I assume excitement of satisfying sashiko (sorta)
took over and i messed up target tree.
It's driver-only set so to follow process it should go via Tony...HOWEVER
I am fed up with these changes and the faster they would be accepted the
better for my mental health. But that's a irrelevant side-note.
>
> /P
>
^ permalink raw reply
* Re: [PATCH nf-next v4 3/6] net: netfilter: Add IPv4 over IPv6 tunnel flowtable acceleration
From: Lorenzo Bianconi @ 2026-07-08 10:11 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Felix Fietkau, Matthias Brugger,
AngeloGioacchino Del Regno, Simon Horman, David Ahern,
Ido Schimmel, Pablo Neira Ayuso, Florian Westphal, Phil Sutter,
Shuah Khan
Cc: linux-arm-kernel, linux-mediatek, netdev, netfilter-devel,
coreteam, linux-kselftest
In-Reply-To: <20260703-b4-flowtable-sw-accel-ip6ip-v4-3-00398cd12382@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 18997 bytes --]
commenting on sashiko's report:
https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260703-b4-flowtable-sw-accel-ip6ip-v4-0-00398cd12382%40kernel.org
> Introduce sw flowtable acceleration for the TX/RX paths of
> IPv4 over IPv6 tunnels, relying on the netfilter flowtable
> infrastructure.
> The feature can be tested with a forwarding scenario between two
> NICs (eth0 and eth1), where an IPv4 over IPv6 tunnel is used to
> reach a remote site via eth1 as the underlay device:
>
> ETH0 -- TUN0 <==> ETH1 -- [IP network] -- TUN1 (2001:db8:2::2)
>
> [IP configuration]
>
> 6: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc noqueue state UP group default qlen 1000
> link/ether 00:00:22:33:11:55 brd ff:ff:ff:ff:ff:ff
> inet 192.168.0.2/24 scope global eth0
> valid_lft forever preferred_lft forever
> 7: eth1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc noqueue state UP group default qlen 1000
> link/ether 00:11:22:33:11:55 brd ff:ff:ff:ff:ff:ff
> inet6 2001:db8:2::1/64 scope global nodad
> valid_lft forever preferred_lft forever
> 8: tun0@NONE: <POINTOPOINT,NOARP,UP,LOWER_UP> mtu 1480 qdisc noqueue state UNKNOWN group default qlen 1000
> link/tunnel6 2001:db8:2::1 peer 2001:db8:2::2 permaddr ce9c:2940:7dcc::
> inet 192.168.100.1/24 scope global tun0
> valid_lft forever preferred_lft forever
>
> $ ip route show
> default via 192.168.100.2 dev tun0
> 192.168.0.0/24 dev eth0 proto kernel scope link src 192.168.0.2
> 192.168.100.0/24 dev tun0 proto kernel scope link src 192.168.100.1
>
> $ ip -6 route show
> 2001:db8:2::/64 dev eth1 proto kernel metric 256 pref medium
>
> $ nft list ruleset
> table inet filter {
> flowtable ft {
> hook ingress priority filter
> devices = { eth0, eth1 }
> }
>
> chain forward {
> type filter hook forward priority filter; policy accept;
> meta l4proto { tcp, udp } flow add @ft
> }
> }
>
> When reproducing this scenario using veth interfaces, the following
> results were observed:
>
> - TCP stream received from IPv4 over IPv6 tunnel:
> - net-next (baseline): ~126 Gbps
> - net-next + IP6IP flowtable support: ~138 Gbps
>
> - TCP stream transmitted to IPv4 over IPv6 tunnel:
> - net-next (baseline): ~127 Gbps
> - net-next + IP6IP flowtable support: ~140 Gbps
>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
> net/netfilter/nf_flow_table_core.c | 16 +++-
> net/netfilter/nf_flow_table_ip.c | 161 ++++++++++++++++++++++++++-----------
> net/netfilter/nf_flow_table_path.c | 10 ++-
> 3 files changed, 133 insertions(+), 54 deletions(-)
>
> diff --git a/net/netfilter/nf_flow_table_core.c b/net/netfilter/nf_flow_table_core.c
> index 99c5b9d671a0..18f89e6fb435 100644
> --- a/net/netfilter/nf_flow_table_core.c
> +++ b/net/netfilter/nf_flow_table_core.c
> @@ -76,9 +76,14 @@ struct flow_offload *flow_offload_alloc(struct nf_conn *ct)
> }
> EXPORT_SYMBOL_GPL(flow_offload_alloc);
>
> -static u32 flow_offload_dst_cookie(struct flow_offload_tuple *flow_tuple)
> +static u32 flow_offload_dst_cookie(struct flow_offload_tuple *flow_tuple,
> + u8 tun_encap_proto)
> {
> - if (flow_tuple->l3proto == NFPROTO_IPV6)
> + bool dst_v6;
> +
> + dst_v6 = tun_encap_proto ? tun_encap_proto == NFPROTO_IPV6
> + : flow_tuple->l3proto == NFPROTO_IPV6;
> + if (dst_v6)
> return rt6_get_cookie(dst_rt6_info(flow_tuple->dst_cache));
>
> return 0;
> @@ -99,10 +104,12 @@ static int flow_offload_fill_route(struct flow_offload *flow,
> enum flow_offload_tuple_dir dir)
> {
> struct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple;
> + u8 l3proto, encap_proto = route->tuple[!dir].in.tun.encap_proto;
> struct dst_entry *dst = nft_route_dst_fetch(route, dir);
> int i, j = 0;
>
> - switch (flow_tuple->l3proto) {
> + l3proto = encap_proto ? encap_proto : flow_tuple->l3proto;
> + switch (l3proto) {
> case NFPROTO_IPV4:
> flow_tuple->mtu = ip_dst_mtu_maybe_forward(dst, true);
> break;
> @@ -138,7 +145,8 @@ static int flow_offload_fill_route(struct flow_offload *flow,
> case FLOW_OFFLOAD_XMIT_NEIGH:
> flow_tuple->ifidx = route->tuple[dir].out.ifindex;
> flow_tuple->dst_cache = dst;
> - flow_tuple->dst_cookie = flow_offload_dst_cookie(flow_tuple);
> + flow_tuple->dst_cookie = flow_offload_dst_cookie(flow_tuple,
> + encap_proto);
> break;
> default:
> WARN_ON_ONCE(1);
> diff --git a/net/netfilter/nf_flow_table_ip.c b/net/netfilter/nf_flow_table_ip.c
> index cf2c74e3fd56..4b6de16bd4f3 100644
> --- a/net/netfilter/nf_flow_table_ip.c
> +++ b/net/netfilter/nf_flow_table_ip.c
> @@ -191,27 +191,27 @@ static void nf_flow_tuple_encap(struct nf_flowtable_ctx *ctx,
> break;
> }
>
> - switch (inner_proto) {
> - case htons(ETH_P_IP):
> - iph = (struct iphdr *)(skb_network_header(skb) + offset);
> - if (ctx->tun.proto == IPPROTO_IPIP) {
> + if (ctx->tun.proto == IPPROTO_IPIP || ctx->tun.proto == IPPROTO_IPV6) {
> + switch (inner_proto) {
> + case htons(ETH_P_IP):
> + iph = (struct iphdr *)(skb_network_header(skb) +
> + offset);
> tuple->tun.dst_v4.s_addr = iph->daddr;
> tuple->tun.src_v4.s_addr = iph->saddr;
> - tuple->tun.l3_proto = IPPROTO_IPIP;
> + tuple->tun.l3_proto = ctx->tun.proto;
> tuple->tun.encap_proto = AF_INET;
> - }
> - break;
> - case htons(ETH_P_IPV6):
> - ip6h = (struct ipv6hdr *)(skb_network_header(skb) + offset);
> - if (ctx->tun.proto == IPPROTO_IPV6) {
> + break;
> + case htons(ETH_P_IPV6):
> + ip6h = (struct ipv6hdr *)(skb_network_header(skb) +
> + offset);
> tuple->tun.dst_v6 = ip6h->daddr;
> tuple->tun.src_v6 = ip6h->saddr;
> - tuple->tun.l3_proto = IPPROTO_IPV6;
> + tuple->tun.l3_proto = ctx->tun.proto;
> tuple->tun.encap_proto = AF_INET6;
> + break;
> + default:
> + break;
> }
> - break;
> - default:
> - break;
> }
> }
>
> @@ -363,7 +363,7 @@ static bool nf_flow_ip6_tunnel_proto(struct nf_flowtable_ctx *ctx,
> if (ipv6_ext_hdr(ip6h->nexthdr))
> return false;
>
> - if (ip6h->nexthdr == IPPROTO_IPV6) {
> + if (ip6h->nexthdr == IPPROTO_IPIP || ip6h->nexthdr == IPPROTO_IPV6) {
> ctx->tun.proto = ip6h->nexthdr;
> ctx->tun.hdr_size = sizeof(*ip6h);
> ctx->offset += ctx->tun.hdr_size;
> @@ -384,6 +384,10 @@ static void nf_flow_ip_tunnel_pop(struct nf_flowtable_ctx *ctx,
>
> skb_pull(skb, ctx->tun.hdr_size);
> skb_reset_network_header(skb);
> + if (ctx->tun.proto == IPPROTO_IPIP)
> + skb->protocol = htons(ETH_P_IP);
> + else
> + skb->protocol = htons(ETH_P_IPV6);
> }
>
> static bool nf_flow_skb_encap_protocol(struct nf_flowtable_ctx *ctx,
> @@ -489,8 +493,16 @@ static int nf_flow_offload_forward(struct nf_flowtable_ctx *ctx,
> flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);
>
> mtu = flow->tuplehash[dir].tuple.mtu + ctx->offset;
> - if (flow->tuplehash[!dir].tuple.tun_num)
> + switch (flow->tuplehash[!dir].tuple.tun.encap_proto) {
> + case AF_INET:
> mtu -= sizeof(*iph);
> + break;
> + case AF_INET6:
> + mtu -= sizeof(struct ipv6hdr);
> + break;
> + default:
> + break;
> + }
>
> if (unlikely(nf_flow_exceeds_mtu(skb, mtu)))
> return 0;
> @@ -636,56 +648,57 @@ static int nf_flow_tunnel_ipip_push(struct net *net, struct sk_buff *skb,
> return 0;
> }
>
> -static int nf_flow_tunnel_v4_push(struct net *net, struct sk_buff *skb,
> - struct flow_offload_tuple *tuple,
> - __be32 *ip_daddr)
> -{
> - if (tuple->tun_num)
> - return nf_flow_tunnel_ipip_push(net, skb, tuple, ip_daddr);
> -
> - return 0;
> -}
> -
> static int nf_flow_tunnel_ip6ip6_push(struct net *net, struct sk_buff *skb,
> struct flow_offload_tuple *tuple,
> struct in6_addr **ip6_daddr)
- This helper is still named nf_flow_tunnel_ip6ip6_push() but now also
encapsulates IPv4 inner packets inside an IPv6 outer header, branching on
tuple->tun.l3_proto and writing that value into ip6h->nexthdr rather than
hard-coding IPPROTO_IPV6.
Would a name like nf_flow_tunnel_ip6_push() (or splitting the inner-family
preamble into a small helper) better reflect that this now covers both
6-in-6 and 4-in-6 encapsulation?
- I will fix it in v5.
> {
> - struct ipv6hdr *ip6h = (struct ipv6hdr *)skb_network_header(skb);
> - struct rtable *rt = dst_rtable(tuple->dst_cache);
> - __u8 dsfield = ipv6_get_dsfield(ip6h);
> + struct dst_entry *dst = tuple->dst_cache;
> struct flowi6 fl6 = {
> .daddr = tuple->tun.src_v6,
> .saddr = tuple->tun.dst_v6,
> .flowi6_proto = IPPROTO_IPV6,
> };
> - u8 hop_limit = ip6h->hop_limit;
> + u8 hop_limit, dsfield;
> + struct ipv6hdr *ip6h;
> int err, mtu;
> u32 headroom;
>
> + if (tuple->tun.l3_proto == IPPROTO_IPIP) {
> + struct iphdr *iph = (struct iphdr *)skb_network_header(skb);
> +
> + dsfield = ipv4_get_dsfield(iph);
> + hop_limit = iph->ttl;
> + } else {
> + ip6h = (struct ipv6hdr *)skb_network_header(skb);
> + dsfield = ipv6_get_dsfield(ip6h);
> + hop_limit = ip6h->hop_limit;
> + }
> +
> err = iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6);
> if (err)
> return err;
>
> - skb_set_inner_ipproto(skb, IPPROTO_IPV6);
> - headroom = sizeof(*ip6h) + LL_RESERVED_SPACE(rt->dst.dev) +
> - rt->dst.header_len;
> + skb_set_inner_ipproto(skb, tuple->tun.l3_proto);
> + headroom = sizeof(*ip6h) + LL_RESERVED_SPACE(dst->dev) +
> + dst->header_len;
> err = skb_cow_head(skb, headroom);
> if (err)
> return err;
>
> skb_scrub_packet(skb, true);
> - mtu = dst_mtu(&rt->dst) - sizeof(*ip6h);
> + mtu = dst_mtu(dst) - sizeof(*ip6h);
> mtu = max(mtu, IPV6_MIN_MTU);
> skb_dst_update_pmtu_no_confirm(skb, mtu);
>
> skb_push(skb, sizeof(*ip6h));
> skb_reset_network_header(skb);
> + skb->protocol = htons(ETH_P_IPV6);
>
> ip6h = ipv6_hdr(skb);
> ip6_flow_hdr(ip6h, dsfield,
> ip6_make_flowlabel(net, skb, fl6.flowlabel, true, &fl6));
> ip6h->hop_limit = hop_limit;
> - ip6h->nexthdr = IPPROTO_IPV6;
> + ip6h->nexthdr = tuple->tun.l3_proto;
> ip6h->daddr = tuple->tun.src_v6;
> ip6h->saddr = tuple->tun.dst_v6;
> ipv6_hdr(skb)->payload_len = htons(skb->len - sizeof(*ip6h));
> @@ -696,6 +709,20 @@ static int nf_flow_tunnel_ip6ip6_push(struct net *net, struct sk_buff *skb,
> return 0;
> }
>
> +static int nf_flow_tunnel_push(struct net *net, struct sk_buff *skb,
> + struct flow_offload_tuple *tuple,
> + __be32 *ip_daddr, struct in6_addr **ip6_daddr)
> +{
> + switch (tuple->tun.encap_proto) {
> + case AF_INET:
> + return nf_flow_tunnel_ipip_push(net, skb, tuple, ip_daddr);
> + case AF_INET6:
> + return nf_flow_tunnel_ip6ip6_push(net, skb, tuple, ip6_daddr);
> + default:
> + return 0;
> + }
> +}
> +
> static int nf_flow_tunnel_v6_push(struct net *net, struct sk_buff *skb,
> struct flow_offload_tuple *tuple,
> struct in6_addr **ip6_daddr)
- The IPv4 hook now goes through the family-aware nf_flow_tunnel_push()
dispatcher while the IPv6 hook still calls the narrow
nf_flow_tunnel_v6_push() wrapper below.
Would it be preferable to route both hooks through nf_flow_tunnel_push()
so that the two entry points share the same abstraction?
- I will fix it in v5.
> @@ -815,6 +842,7 @@ nf_flow_offload_ip_hook(void *priv, struct sk_buff *skb,
> .in = state->in,
> };
> struct nf_flow_xmit xmit = {};
> + struct in6_addr *ip6_daddr;
> struct flow_offload *flow;
> struct neighbour *neigh;
> struct rtable *rt;
> @@ -844,25 +872,41 @@ nf_flow_offload_ip_hook(void *priv, struct sk_buff *skb,
> other_tuple = &flow->tuplehash[!dir].tuple;
> ip_daddr = other_tuple->src_v4.s_addr;
>
> - if (nf_flow_tunnel_v4_push(state->net, skb, other_tuple, &ip_daddr) < 0)
> + if (nf_flow_tunnel_push(state->net, skb, other_tuple, &ip_daddr,
> + &ip6_daddr) < 0)
- ip6_daddr is left uninitialized here, then its address is passed to
nf_flow_tunnel_push() below. nf_flow_tunnel_push() only writes through
ip6_daddr in the AF_INET6 case; the AF_INET and default cases leave the
pointer untouched:
switch (tuple->tun.encap_proto) {
case AF_INET:
return nf_flow_tunnel_ipip_push(net, skb, tuple, ip_daddr);
case AF_INET6:
return nf_flow_tunnel_ip6ip6_push(net, skb, tuple, ip6_daddr);
default:
return 0;
}
The symmetric IPv6 hook explicitly pre-initialises the corresponding
pointer with ip6_daddr = &other_tuple->src_v6 before the push call. Should
the IPv4 hook mirror that pattern here?
- I will fix it in v5.
> return NF_DROP;
>
> switch (tuplehash->tuple.xmit_type) {
> - case FLOW_OFFLOAD_XMIT_NEIGH:
> - rt = dst_rtable(tuplehash->tuple.dst_cache);
> + case FLOW_OFFLOAD_XMIT_NEIGH: {
> + struct dst_entry *dst;
> +
> xmit.outdev = dev_get_by_index_rcu(state->net, tuplehash->tuple.ifidx);
> if (!xmit.outdev) {
> flow_offload_teardown(flow);
> return NF_DROP;
> }
> - neigh = ip_neigh_gw4(rt->dst.dev, rt_nexthop(rt, ip_daddr));
> + if (other_tuple->tun.encap_proto == AF_INET6 ||
> + ctx.tun.proto == IPPROTO_IPV6) {
> + struct rt6_info *rt6;
> +
> + rt6 = dst_rt6_info(tuplehash->tuple.dst_cache);
> + neigh = ip_neigh_gw6(rt6->dst.dev,
> + rt6_nexthop(rt6, ip6_daddr));
> + dst = &rt6->dst;
> + } else {
> + rt = dst_rtable(tuplehash->tuple.dst_cache);
> + neigh = ip_neigh_gw4(rt->dst.dev,
> + rt_nexthop(rt, ip_daddr));
> + dst = &rt->dst;
> + }
> if (IS_ERR(neigh)) {
> flow_offload_teardown(flow);
> return NF_DROP;
> }
> xmit.dest = neigh->ha;
> - skb_dst_set_noref(skb, &rt->dst);
> + skb_dst_set_noref(skb, dst);
> break;
> + }
> case FLOW_OFFLOAD_XMIT_DIRECT:
> xmit.outdev = dev_get_by_index_rcu(state->net, tuplehash->tuple.out.ifidx);
> if (!xmit.outdev) {
> @@ -1112,8 +1156,12 @@ nf_flow_offload_ipv6_lookup(struct nf_flowtable_ctx *ctx,
> if (!nf_flow_skb_encap_protocol(ctx, skb, htons(ETH_P_IPV6)))
> return NULL;
>
> - if (nf_flow_tuple_ipv6(ctx, skb, &tuple) < 0)
> + if (ctx->tun.proto == IPPROTO_IPIP) {
> + if (nf_flow_tuple_ip(ctx, skb, &tuple) < 0)
> + return NULL;
> + } else if (nf_flow_tuple_ipv6(ctx, skb, &tuple) < 0) {
> return NULL;
> + }
>
> return flow_offload_lookup(flow_table, &tuple);
> }
> @@ -1140,7 +1188,11 @@ nf_flow_offload_ipv6_hook(void *priv, struct sk_buff *skb,
> if (tuplehash == NULL)
> return NF_ACCEPT;
>
> - ret = nf_flow_offload_ipv6_forward(&ctx, flow_table, tuplehash, skb);
> + if (ctx.tun.proto == IPPROTO_IPIP)
> + ret = nf_flow_offload_forward(&ctx, flow_table, tuplehash, skb);
> + else
> + ret = nf_flow_offload_ipv6_forward(&ctx, flow_table, tuplehash,
> + skb);
> if (ret < 0)
> return NF_DROP;
> else if (ret == 0)
> @@ -1164,21 +1216,38 @@ nf_flow_offload_ipv6_hook(void *priv, struct sk_buff *skb,
> return NF_DROP;
>
> switch (tuplehash->tuple.xmit_type) {
> - case FLOW_OFFLOAD_XMIT_NEIGH:
> - rt = dst_rt6_info(tuplehash->tuple.dst_cache);
> + case FLOW_OFFLOAD_XMIT_NEIGH: {
> + struct dst_entry *dst;
> +
> xmit.outdev = dev_get_by_index_rcu(state->net, tuplehash->tuple.ifidx);
> if (!xmit.outdev) {
> flow_offload_teardown(flow);
> return NF_DROP;
> }
> - neigh = ip_neigh_gw6(rt->dst.dev, rt6_nexthop(rt, ip6_daddr));
> + if (other_tuple->tun.encap_proto == AF_INET ||
> + ctx.tun.proto == IPPROTO_IPIP) {
> + __be32 ip_daddr = other_tuple->src_v4.s_addr;
> + struct rtable *rt4;
> +
> + skb->protocol = htons(ETH_P_IP);
> + rt4 = dst_rtable(tuplehash->tuple.dst_cache);
> + neigh = ip_neigh_gw4(rt4->dst.dev,
> + rt_nexthop(rt4, ip_daddr));
> + dst = &rt4->dst;
> + } else {
> + rt = dst_rt6_info(tuplehash->tuple.dst_cache);
> + neigh = ip_neigh_gw6(rt->dst.dev,
> + rt6_nexthop(rt, ip6_daddr));
> + dst = &rt->dst;
> + }
> if (IS_ERR(neigh)) {
> flow_offload_teardown(flow);
> return NF_DROP;
> }
> xmit.dest = neigh->ha;
> - skb_dst_set_noref(skb, &rt->dst);
> + skb_dst_set_noref(skb, dst);
> break;
> + }
> case FLOW_OFFLOAD_XMIT_DIRECT:
> xmit.outdev = dev_get_by_index_rcu(state->net, tuplehash->tuple.out.ifidx);
> if (!xmit.outdev) {
> diff --git a/net/netfilter/nf_flow_table_path.c b/net/netfilter/nf_flow_table_path.c
> index caaf48c5fd2a..5e84b7f18a26 100644
> --- a/net/netfilter/nf_flow_table_path.c
> +++ b/net/netfilter/nf_flow_table_path.c
> @@ -216,12 +216,13 @@ static int nft_flow_tunnel_update_route(const struct nft_pktinfo *pkt,
> struct dst_entry *tun_dst = NULL;
> struct flowi fl = {};
>
> - switch (nft_pf(pkt)) {
> + switch (tun->encap_proto) {
> case NFPROTO_IPV4:
> fl.u.ip4.daddr = tun->dst_v4.s_addr;
> fl.u.ip4.saddr = tun->src_v4.s_addr;
> fl.u.ip4.flowi4_iif = nft_in(pkt)->ifindex;
> - fl.u.ip4.flowi4_dscp = ip4h_dscp(ip_hdr(pkt->skb));
> + if (nft_pf(pkt) == NFPROTO_IPV4)
> + fl.u.ip4.flowi4_dscp = ip4h_dscp(ip_hdr(pkt->skb));
> fl.u.ip4.flowi4_mark = pkt->skb->mark;
> fl.u.ip4.flowi4_flags = FLOWI_FLAG_ANYSRC;
> break;
> @@ -229,13 +230,14 @@ static int nft_flow_tunnel_update_route(const struct nft_pktinfo *pkt,
> fl.u.ip6.daddr = tun->dst_v6;
> fl.u.ip6.saddr = tun->src_v6;
> fl.u.ip6.flowi6_iif = nft_in(pkt)->ifindex;
> - fl.u.ip6.flowlabel = ip6_flowinfo(ipv6_hdr(pkt->skb));
> + if (nft_pf(pkt) == NFPROTO_IPV6)
> + fl.u.ip6.flowlabel = ip6_flowinfo(ipv6_hdr(pkt->skb));
> fl.u.ip6.flowi6_mark = pkt->skb->mark;
> fl.u.ip6.flowi6_flags = FLOWI_FLAG_ANYSRC;
> break;
- This changes route-family selection from nft_pf(pkt) to tun->encap_proto
and gates the DSCP and flowlabel inputs on nft_pf(pkt) matching the outer
family, so cross-family flows now pass zero DSCP or flowlabel into the
flowi used for the FIB lookup.
Setups that use policy routing keyed on TOS/DSCP or flow label may see
different route selection than before. The changelog describes the
IPv4-over-IPv6 feature and its benchmarks but does not mention this
behavioural change on tunnel route selection.
Could this behavioural change be called out in the commit message so it
is discoverable during bisection and stable-tree evaluation?
- I will fix commit logs in v5.
Regards,
Lorenzo
> }
>
> - nf_route(nft_net(pkt), &tun_dst, &fl, false, nft_pf(pkt));
> + nf_route(nft_net(pkt), &tun_dst, &fl, false, tun->encap_proto);
> if (!tun_dst)
> return -ENOENT;
>
>
> --
> 2.55.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH net v4] octeontx2-pf: check DMAC extraction support before filtering
From: patchwork-bot+netdevbpf @ 2026-07-08 10:10 UTC (permalink / raw)
To: Nitin Shetty J
Cc: netdev, linux-kernel, sgoutham, gakula, sbhatta, hkelam,
bbhushan2, andrew+netdev, davem, edumazet, kuba, pabeni, naveenm,
tduszynski, sumang, hramamurthy, rkannoth
In-Reply-To: <20260702033451.2969880-1-nshettyj@marvell.com>
Hello:
This patch was applied to netdev/net.git (main)
by Paolo Abeni <pabeni@redhat.com>:
On Thu, 2 Jul 2026 09:04:51 +0530 you wrote:
> From: Suman Ghosh <sumang@marvell.com>
>
> Currently, configuring a VF MAC address via the PF (e.g., 'ip link
> set <pf> vf 0 mac <mac>') blindly attempts to install a DMAC-based
> hardware filter. However, the hardware parser profile might not
> support DMAC extraction.
>
> [...]
Here is the summary with links:
- [net,v4] octeontx2-pf: check DMAC extraction support before filtering
https://git.kernel.org/netdev/net/c/235acadd3105
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* [PATCH V3 4/4] dmaengine: xilinx_dma: Extend metadata handling for AXI DMA and MCDMA
From: Srinivas Neeli @ 2026-07-08 10:06 UTC (permalink / raw)
To: Vinod Koul, Radhey Shyam Pandey
Cc: Frank Li, Michal Simek, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Suraj Gupta,
Marek Vasut, Tomi Valkeinen, Alex Bereza, Folker Schwesinger,
dmaengine, netdev, linux-arm-kernel, linux-kernel, git
In-Reply-To: <20260708100652.603074-1-srinivas.neeli@amd.com>
From: Suraj Gupta <suraj.gupta2@amd.com>
xilinx_dma_get_metadata_ptr() exposed only the descriptor APP fields. Both
AXI DMA and AXI MCDMA descriptors carry a status word with the transfer
status, and AXI MCDMA additionally carries an AXI4-Stream sideband status
word holding TID, TDEST and TUSER that clients may need. Extend the
metadata handling to expose these.
The returned pointer now starts at the descriptor status word for both AXI
DMA and AXI MCDMA. As the descriptor words are contiguous, the client sees
the status at index 0, followed for AXI MCDMA by the sideband status
(TID/TDEST/TUSER) at index 1 and the APP fields, or for AXI DMA by the APP
fields directly. The payload length is derived from the field sizes.
This changes the get_metadata_ptr() contract for AXI DMA. The pointer now
starts at the status word of the last (EOF) descriptor instead of the APP
fields of the first, and the payload grows from 20 to 24 bytes. A client
reading app[0] now reads the status word. No in-tree consumer is affected,
as the axienet driver reads the RX frame length from result->residue
rather than the APP fields. Reading the EOF descriptor is also correct, as
the hardware writes the status and APP fields there.
The index 0 and 1 layout described above is for the AXI MCDMA receive
(S2MM) direction, which is where metadata is consumed. On the transmit
(MM2S) direction the same descriptor words hold different fields.
The probe logic is extended to read xlnx,axistream-connected for MCDMA, and
xilinx_mcdma_prep_slave_sg() attaches metadata_ops when an AXI Stream
interface is present, so MCDMA clients can use the metadata API in the same
way as AXI DMA clients.
Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
Co-developed-by: Srinivas Neeli <srinivas.neeli@amd.com>
Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
---
Changes in V3:
- Renamed subject to include "AXI DMA and MCDMA" (was "AXI MCDMA" only).
- Complete rewrite of commit message and implementation.
- Metadata pointer now returns status field at index 0 instead of APP
fields, exposing status and sideband information to clients.
- Changed from list_first_entry to list_last_entry to return the EOF
descriptor where hardware writes status and APP fields.
- Added explicit handling for both AXIDMA and MCDMA types with proper
payload length calculation.
- Added WARN_ON_ONCE for unsupported DMA types.
- Removed the 'chan' field from struct xilinx_dma_tx_descriptor (was
added in V2) as it's no longer needed; channel is obtained from
tx->chan instead.
- Dropped V2 patches 4/5 (dt-bindings xlnx,include-stscntrl-strm) and
5/5 (xferred_bytes support) as the approach changed to use residue.
Changes in V2:
- Added support for MCDMA metadata handling alongside AXIDMA.
- Added 'chan' field to struct xilinx_dma_tx_descriptor.
---
drivers/dma/xilinx/xilinx_dma.c | 48 ++++++++++++++++++++++++++++-----
1 file changed, 41 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 1b5b00f08c5f..f5c4e0ca2cc4 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -651,18 +651,48 @@ static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan,
* @tx: async transaction descriptor
* @payload_len: metadata payload length
* @max_len: metadata max length
- * Return: The app field pointer.
+ *
+ * The returned pointer starts at the descriptor status word for both AXI DMA
+ * and AXI MCDMA. As the descriptor words are contiguous, the client sees the
+ * status at index 0, followed for AXI MCDMA by the sideband status
+ * (TID/TDEST/TUSER) at index 1 and the APP fields from index 2, or for AXI DMA
+ * by the APP fields from index 1. These fields are populated by the hardware on
+ * the End-Of-Frame descriptor, so the pointer is taken from there.
+ *
+ * Return: Pointer to the descriptor status field.
*/
static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx,
size_t *payload_len, size_t *max_len)
{
struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
- struct xilinx_axidma_tx_segment *seg;
+ struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
+
+ if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
+ struct xilinx_aximcdma_tx_segment *seg =
+ list_last_entry(&desc->segments,
+ struct xilinx_aximcdma_tx_segment, node);
+
+ /* [0] = status, [1] = sideband (TID/TDEST/TUSER), [2..] = app */
+ *max_len = *payload_len = sizeof(seg->hw.s2mm_status) +
+ sizeof(seg->hw.s2mm_sideband_status) +
+ sizeof(seg->hw.app);
+ return &seg->hw.s2mm_status;
+ }
+
+ if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
+ struct xilinx_axidma_tx_segment *seg =
+ list_last_entry(&desc->segments,
+ struct xilinx_axidma_tx_segment, node);
+
+ /* [0] = status, [1..] = app */
+ *max_len = *payload_len = sizeof(seg->hw.status) +
+ sizeof(seg->hw.app);
+ return &seg->hw.status;
+ }
- *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS;
- seg = list_first_entry(&desc->segments,
- struct xilinx_axidma_tx_segment, node);
- return seg->hw.app;
+ /* Only AXIDMA and MCDMA attach metadata_ops today. */
+ WARN_ON_ONCE(1);
+ return ERR_PTR(-EINVAL);
}
static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = {
@@ -2639,6 +2669,9 @@ xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
segment->hw.control |= XILINX_MCDMA_BD_EOP;
}
+ if (chan->xdev->has_axistream_connected)
+ desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops;
+
return &desc->async_tx;
error:
@@ -3287,7 +3320,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)
dma_set_max_seg_size(xdev->dev, xdev->max_buffer_len);
- if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
+ if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA ||
+ xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
xdev->has_axistream_connected =
of_property_read_bool(node, "xlnx,axistream-connected");
}
--
2.25.1
^ permalink raw reply related
* [PATCH V3 3/4] net: xilinx: axienet: Derive RX frame length from DMA residue
From: Srinivas Neeli @ 2026-07-08 10:06 UTC (permalink / raw)
To: Vinod Koul, Radhey Shyam Pandey
Cc: Frank Li, Michal Simek, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Suraj Gupta,
Marek Vasut, Tomi Valkeinen, Alex Bereza, Folker Schwesinger,
dmaengine, netdev, linux-arm-kernel, linux-kernel, git
In-Reply-To: <20260708100652.603074-1-srinivas.neeli@amd.com>
The dmaengine RX path determined the received frame length by reading APP
word 4 of the DMA descriptor metadata, masking the lower 16 bits of
app_metadata[LEN_APP].
This relies on the optional AXI4-Stream status/control interface being
present in the design. The descriptor APP fields are only populated by the
hardware when that interface is enabled. On designs without it the APP
fields are not updated, so the length read back is invalid.
The AXI DMA engine already reports how many bytes it wrote into the buffer
through the standard dmaengine residue mechanism
(dmaengine_result.residue). The received frame length is therefore the
posted buffer length minus the residue, which is independent of the
status/control interface and correct across all designs, including
multi-descriptor frames where the residue is summed over the chain.
Use result->residue to compute the RX frame length and drop the descriptor
metadata lookup, which was only used for this purpose. The error path now
uses the standard dmaengine_result.result status instead of the metadata
pointer return value, and the now-unused LEN_APP macro is removed.
The transmit path is unaffected. It still passes APP metadata for checksum
offload and derives its length from the skb.
Fixes: 6a91b846af85 ("net: axienet: Introduce dmaengine support")
Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
---
Changes in V3:
- New patch in this series.
- This patch enables axienet to work on designs where the AXI4-Stream
status/control interface is not present. By using the standard
dmaengine residue mechanism, the driver no longer depends on APP
fields being populated by hardware.
- This approach replaces the V2 xferred_bytes mechanism (V2 patch 5/5),
making the dt-bindings patch (V2 patch 4/5) for xlnx,include-stscntrl-strm
also unnecessary. Both V2 patches are dropped in this series.
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index fcf517069d16..67d1b8e91d68 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -53,7 +53,6 @@
#define TX_BD_NUM_MAX 4096
#define RX_BD_NUM_MAX 4096
#define DMA_NUM_APP_WORDS 5
-#define LEN_APP 4
#define RX_BUF_NUM_DEFAULT 128
/* Must be shorter than length of ethtool_drvinfo.driver field to fit */
@@ -1159,29 +1158,26 @@ axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
static void axienet_dma_rx_cb(void *data, const struct dmaengine_result *result)
{
struct skbuf_dma_descriptor *skbuf_dma;
- size_t meta_len, meta_max_len, rx_len;
struct axienet_local *lp = data;
struct sk_buff *skb;
- u32 *app_metadata;
+ size_t rx_len;
int i;
skbuf_dma = axienet_get_rx_desc(lp, lp->rx_ring_tail++);
skb = skbuf_dma->skb;
- app_metadata = dmaengine_desc_get_metadata_ptr(skbuf_dma->desc, &meta_len,
- &meta_max_len);
dma_unmap_single(lp->dev, skbuf_dma->dma_address, lp->max_frm_size,
DMA_FROM_DEVICE);
- if (IS_ERR(app_metadata)) {
+ if (result->result != DMA_TRANS_NOERROR) {
if (net_ratelimit())
- netdev_err(lp->ndev, "Failed to get RX metadata pointer\n");
+ netdev_err(lp->ndev, "RX DMA transfer failed\n");
dev_kfree_skb_any(skb);
lp->ndev->stats.rx_dropped++;
goto rx_submit;
}
- /* TODO: Derive app word index programmatically */
- rx_len = (app_metadata[LEN_APP] & 0xFFFF);
+ /* Actual length = posted buffer length - residue. */
+ rx_len = lp->max_frm_size - result->residue;
skb_put(skb, rx_len);
skb->protocol = eth_type_trans(skb, lp->ndev);
skb->ip_summed = CHECKSUM_NONE;
--
2.25.1
^ permalink raw reply related
* [PATCH V3 2/4] dmaengine: xilinx_dma: Move descriptors to done list based on completion bit
From: Srinivas Neeli @ 2026-07-08 10:06 UTC (permalink / raw)
To: Vinod Koul, Radhey Shyam Pandey
Cc: Frank Li, Michal Simek, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Suraj Gupta,
Marek Vasut, Tomi Valkeinen, Alex Bereza, Folker Schwesinger,
dmaengine, netdev, linux-arm-kernel, linux-kernel, git
In-Reply-To: <20260708100652.603074-1-srinivas.neeli@amd.com>
In AXI MCDMA scatter-gather mode, xilinx_dma_complete_descriptor() walks
the channel's active_list and unconditionally moves every entry to the
done_list. The MCDMA IOC interrupt handler invokes this function on
every interrupt-on-completion, but with interrupt coalescing
(IRQThreshold > 1) an IOC interrupt may fire after only a subset of the
queued descriptors have actually been processed by the hardware. As a
result, descriptors whose completion bit is not yet set in the BD status
were being reported as completed to client drivers.
Add a check for the descriptor completion bit before moving entries from
the active list to the done list, using the appropriate direction-
specific status field (s2mm_status for DMA_DEV_TO_MEM, mm2s_status for
DMA_MEM_TO_DEV).
The MCDMA completion check is intentionally not guarded by chan->has_sg,
unlike the AXIDMA branch above. AXI MCDMA only operates in scatter-gather
mode (has_sg is always true), so the guard would always pass and is
omitted. The completion bit is therefore checked unconditionally.
Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support")
Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
---
Changes in V3:
- Added Fixes tag.
- Expanded commit message to explain the interrupt coalescing scenario
and why the has_sg guard is omitted for MCDMA.
- Changed local variable from 'bool completed' to 'u32 status' for
cleaner status field access.
- Simplified completion check logic.
Changes in V2:
- No change.
---
drivers/dma/xilinx/xilinx_dma.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index ff5b29a808e9..1b5b00f08c5f 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1784,6 +1784,17 @@ static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
struct xilinx_axidma_tx_segment, node);
if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg)
break;
+ } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
+ struct xilinx_aximcdma_tx_segment *seg;
+ u32 status;
+
+ seg = list_last_entry(&desc->segments,
+ struct xilinx_aximcdma_tx_segment,
+ node);
+ status = (chan->direction == DMA_DEV_TO_MEM) ?
+ seg->hw.s2mm_status : seg->hw.mm2s_status;
+ if (!(status & XILINX_DMA_BD_COMP_MASK))
+ break;
}
if (chan->has_sg && chan->xdev->dma_config->dmatype !=
XDMA_TYPE_VDMA)
--
2.25.1
^ permalink raw reply related
* [PATCH V3 1/4] dmaengine: xilinx_dma: Fix MCDMA descriptor fields based on DMA direction
From: Srinivas Neeli @ 2026-07-08 10:06 UTC (permalink / raw)
To: Vinod Koul, Radhey Shyam Pandey
Cc: Frank Li, Michal Simek, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Suraj Gupta,
Marek Vasut, Tomi Valkeinen, Alex Bereza, Folker Schwesinger,
dmaengine, netdev, linux-arm-kernel, linux-kernel, git
In-Reply-To: <20260708100652.603074-1-srinivas.neeli@amd.com>
The MCDMA BD format differs between memory-to-device (MM2S) and
device-to-memory (S2MM) directions, but the driver was using generic
'status' and 'sideband_status' fields for both. This led to incorrect
residue calculations when the hardware updates direction-specific fields.
Refactor the descriptor structure to use unions with direction-specific
field mappings, and update the residue calculation logic to select the
correct status field based on DMA direction.
This matches the hardware descriptor layout and fixes incorrect
residue reporting.
Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support")
Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
---
Changes in V3:
- Renamed subject from "for MM2S vs S2MM" to "based on DMA direction".
- Reworded commit message for clarity.
- Added XILINX_MCDMA_BD_HW_SIZE macro and static_assert to verify
descriptor size at compile time.
- Refactored residue calculation to separate addition and subtraction
operations for better readability.
Changes in V2:
- No change.
---
drivers/dma/xilinx/xilinx_dma.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 98b41b8f8915..ff5b29a808e9 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -223,6 +223,7 @@
#define XILINX_MCDMA_IRQ_ERR_MASK BIT(7)
#define XILINX_MCDMA_BD_EOP BIT(30)
#define XILINX_MCDMA_BD_SOP BIT(31)
+#define XILINX_MCDMA_BD_HW_SIZE 64
/**
* struct xilinx_vdma_desc_hw - Hardware Descriptor
@@ -277,8 +278,10 @@ struct xilinx_axidma_desc_hw {
* @buf_addr_msb: MSB of Buffer address @0x0C
* @rsvd: Reserved field @0x10
* @control: Control Information field @0x14
- * @status: Status field @0x18
- * @sideband_status: Status of sideband signals @0x1C
+ * @mm2s_ctrl_sideband: Sideband control info for mm2s @0x18
+ * @s2mm_status: Status field for s2mm @0x18
+ * @mm2s_status: Status field for mm2s @0x1C
+ * @s2mm_sideband_status: Sideband status for s2mm @0x1C
* @app: APP Fields @0x20 - 0x30
*/
struct xilinx_aximcdma_desc_hw {
@@ -288,10 +291,17 @@ struct xilinx_aximcdma_desc_hw {
u32 buf_addr_msb;
u32 rsvd;
u32 control;
- u32 status;
- u32 sideband_status;
+ union {
+ u32 mm2s_ctrl_sideband;
+ u32 s2mm_status;
+ };
+ union {
+ u32 mm2s_status;
+ u32 s2mm_sideband_status;
+ };
u32 app[XILINX_DMA_NUM_APP_WORDS];
} __aligned(64);
+static_assert(sizeof(struct xilinx_aximcdma_desc_hw) == XILINX_MCDMA_BD_HW_SIZE);
/**
* struct xilinx_cdma_desc_hw - Hardware Descriptor
@@ -1015,9 +1025,11 @@ static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
struct xilinx_aximcdma_tx_segment,
node);
aximcdma_hw = &aximcdma_seg->hw;
- residue +=
- (aximcdma_hw->control & chan->xdev->max_buffer_len) -
- (aximcdma_hw->status & chan->xdev->max_buffer_len);
+ residue += aximcdma_hw->control & chan->xdev->max_buffer_len;
+ if (chan->direction == DMA_DEV_TO_MEM)
+ residue -= aximcdma_hw->s2mm_status & chan->xdev->max_buffer_len;
+ else
+ residue -= aximcdma_hw->mm2s_status & chan->xdev->max_buffer_len;
}
}
--
2.25.1
^ permalink raw reply related
* [PATCH V3 0/4] dmaengine: xilinx_dma: MCDMA descriptor and metadata handling improvements
From: Srinivas Neeli @ 2026-07-08 10:06 UTC (permalink / raw)
To: Vinod Koul, Radhey Shyam Pandey
Cc: Frank Li, Michal Simek, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Suraj Gupta,
Marek Vasut, Tomi Valkeinen, Alex Bereza, Folker Schwesinger,
dmaengine, netdev, linux-arm-kernel, linux-kernel, git
This series improves the Xilinx AXI DMA and MCDMA driver's descriptor
handling and metadata reporting. It fixes direction-specific descriptor
field usage, ensures completion is based on the hardware completion bit
(important with interrupt coalescing), and extends metadata handling to
expose status and sideband fields alongside APP fields.
The axienet driver is updated to derive RX frame length from the standard
dmaengine residue mechanism rather than descriptor APP fields, making it
work on designs where the AXI4-Stream status/control interface is not
present.
Changes in V3:
- Patch 1: Renamed subject, added static_assert for descriptor size,
refactored residue calculation for clarity.
- Patch 2: Added Fixes tag, expanded commit message explaining interrupt
coalescing scenario, simplified completion check logic.
- Patch 3: New patch - axienet now uses result->residue for RX length
instead of APP metadata, removing dependency on status/control stream.
- Patch 4: Complete rewrite - metadata pointer now starts at status field
(index 0) exposing status/sideband to clients; uses EOF descriptor;
removed 'chan' field from descriptor struct.
- Dropped V2 patches 4/5 (dt-bindings) and 5/5 (xferred_bytes) as the
approach changed to use standard residue mechanism.
Changes in V2:
- Rebased on the AXI DMA binding YAML conversion.
- Added xlnx,include-stscntrl-strm in the YAML binding.
- Clarified cover letter to reflect metadata behavior with and without
APP fields.
https://lore.kernel.org/all/20260309033444.3472359-1-abin.joseph@amd.com/
Srinivas Neeli (3):
dmaengine: xilinx_dma: Fix MCDMA descriptor fields based on DMA
direction
dmaengine: xilinx_dma: Move descriptors to done list based on
completion bit
net: xilinx: axienet: Derive RX frame length from DMA residue
Suraj Gupta (1):
dmaengine: xilinx_dma: Extend metadata handling for AXI DMA and MCDMA
drivers/dma/xilinx/xilinx_dma.c | 85 ++++++++++++++++---
.../net/ethernet/xilinx/xilinx_axienet_main.c | 14 ++-
2 files changed, 76 insertions(+), 23 deletions(-)
--
2.25.1
^ permalink raw reply
* [PATCH net-next v3 12/12] net: mctp: usb: Allow multiple urbs in flight
From: Jeremy Kerr @ 2026-07-08 9:58 UTC (permalink / raw)
To: Matt Johnston, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Greg Kroah-Hartman
Cc: netdev, linux-usb
In-Reply-To: <20260708-dev-mctp-usb-1-1-v3-0-9e710155cdbf@codeconstruct.com.au>
Currently, we stop tx queues when we have one urb submitted. This means
we will immediately hit dev_hard_start_xmit's tx-queues-off ->
NETDEV_TX_BUSY case, and revert to the requeue -> gso_skb single-dequeue
path, and no longer be able to pack skbs without an xmit_more
indication.
Instead, allow a few urbs to be in-flight, with a limit of 16kB of data
outstanding (after which we will disable queues). With this, the tx path
will cause fewer requeues (and therefore non-packed transfers) under
normal loads.
Signed-off-by: Jeremy Kerr <jk@codeconstruct.com.au>
---
v2:
- rework tx_qmem locking, prevent race between completion and
submission for stopping/waking the tx queues; perform the wake while
locked
- only wake if netif_running()
---
drivers/net/mctp/mctp-usb.c | 33 +++++++++++++++++++++++++++++----
1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/net/mctp/mctp-usb.c b/drivers/net/mctp/mctp-usb.c
index 8e29be9ebd1d..2d31075374b4 100644
--- a/drivers/net/mctp/mctp-usb.c
+++ b/drivers/net/mctp/mctp-usb.c
@@ -42,6 +42,9 @@ struct mctp_usb {
struct mctp_usblib_tx tx;
struct usb_anchor tx_anchor;
+ /* serialises tx_qmem updates to netdev queue states */
+ spinlock_t tx_qmem_lock;
+ int tx_qmem;
};
enum {
@@ -49,23 +52,41 @@ enum {
MCTP_USB_SUBCLASS_SPAN = 0x02,
};
+/* We use a total-size limit for outstanding URBs, as the transfer counts
+ * may vary a lot between spanning- and non-spanning modes. In spanning mode,
+ * this will allow for a couple of max-sized transfers to be in flight. In
+ * non-spanning mode, 32.
+ *
+ * We want to avoid disabling the tx queue if possible; doing so will end up
+ * requeueing to gso_skb, and we only dequeue from that one skb at a time,
+ * so can no longer perform transfer packing.
+ */
+static const unsigned int TX_QMEM_MAX = 16384;
+
static void mctp_usb_out_complete(struct urb *urb)
{
struct mctp_usblib_tx_ctx *tx_ctx = urb->context;
struct mctp_usb *mctp_usb = mctp_usblib_tx_ctx_priv(tx_ctx);
+ unsigned int len = urb->transfer_buffer_length;
struct net_device *netdev = mctp_usb->netdev;
+ unsigned long flags;
mctp_usblib_tx_send_complete(tx_ctx, netdev, urb->status == 0);
usb_free_urb(urb);
- netif_wake_queue(netdev);
+ spin_lock_irqsave(&mctp_usb->tx_qmem_lock, flags);
+ mctp_usb->tx_qmem -= len;
+ if (mctp_usb->tx_qmem < TX_QMEM_MAX && netif_running(netdev))
+ netif_wake_queue(netdev);
+ spin_unlock_irqrestore(&mctp_usb->tx_qmem_lock, flags);
}
static int mctp_usb_tx_send(struct mctp_usblib_tx_ctx *tx_ctx,
void *data, size_t len)
{
struct mctp_usb *mctp_usb = mctp_usblib_tx_ctx_priv(tx_ctx);
+ unsigned long flags;
struct urb *urb;
int rc;
@@ -80,8 +101,6 @@ static int mctp_usb_tx_send(struct mctp_usblib_tx_ctx *tx_ctx,
if (mctp_usb->span)
urb->transfer_flags |= URB_ZERO_PACKET;
- netif_stop_queue(mctp_usb->netdev);
-
usb_anchor_urb(urb, &mctp_usb->tx_anchor);
rc = usb_submit_urb(urb, GFP_ATOMIC);
@@ -89,7 +108,12 @@ static int mctp_usb_tx_send(struct mctp_usblib_tx_ctx *tx_ctx,
netdev_dbg(mctp_usb->netdev, "TX urb submit failed, %d\n", rc);
usb_unanchor_urb(urb);
usb_free_urb(urb);
- netif_start_queue(mctp_usb->netdev);
+ } else {
+ spin_lock_irqsave(&mctp_usb->tx_qmem_lock, flags);
+ mctp_usb->tx_qmem += len;
+ if (mctp_usb->tx_qmem >= TX_QMEM_MAX)
+ netif_stop_queue(mctp_usb->netdev);
+ spin_unlock_irqrestore(&mctp_usb->tx_qmem_lock, flags);
}
return rc;
@@ -333,6 +357,7 @@ static int mctp_usb_probe(struct usb_interface *intf,
spin_lock_init(&dev->rx_lock);
if (dev->span)
netdev->max_mtu = MCTP_USB_1_1_MTU_MAX;
+ spin_lock_init(&dev->tx_qmem_lock);
usb_set_intfdata(intf, dev);
mctp_usblib_rx_init(&dev->rx, le16_to_cpu(ep_in->wMaxPacketSize),
--
2.47.3
^ permalink raw reply related
* [PATCH net-next v3 11/12] net: mctp: usb: enable v1.1 packet spanning
From: Jeremy Kerr @ 2026-07-08 9:58 UTC (permalink / raw)
To: Matt Johnston, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Greg Kroah-Hartman
Cc: netdev, linux-usb
In-Reply-To: <20260708-dev-mctp-usb-1-1-v3-0-9e710155cdbf@codeconstruct.com.au>
Now that mctp-usblib supports DSP0283 v1.1 packet spanning, enable it in
our host-side transport driver.
Add a match for the new device subclass (0x02), and indicating spanning
mode to the usblib rx/tx implementation.
Signed-off-by: Jeremy Kerr <jk@codeconstruct.com.au>
---
drivers/net/mctp/mctp-usb.c | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/net/mctp/mctp-usb.c b/drivers/net/mctp/mctp-usb.c
index 0507307c875f..8e29be9ebd1d 100644
--- a/drivers/net/mctp/mctp-usb.c
+++ b/drivers/net/mctp/mctp-usb.c
@@ -3,9 +3,9 @@
* mctp-usb.c - MCTP-over-USB (DMTF DSP0283) transport binding driver.
*
* DSP0283 is available at:
- * https://www.dmtf.org/sites/default/files/standards/documents/DSP0283_1.0.1.pdf
+ * https://www.dmtf.org/sites/default/files/standards/documents/DSP0283_1.1.0.pdf
*
- * Copyright (C) 2024-2025 Code Construct Pty Ltd
+ * Copyright (C) 2024-2026 Code Construct Pty Ltd
*/
#include <linux/module.h>
@@ -22,6 +22,7 @@
struct mctp_usb {
struct usb_device *usbdev;
struct usb_interface *intf;
+ bool span;
struct net_device *netdev;
@@ -43,6 +44,11 @@ struct mctp_usb {
struct usb_anchor tx_anchor;
};
+enum {
+ MCTP_USB_SUBCLASS_BASE = 0x00,
+ MCTP_USB_SUBCLASS_SPAN = 0x02,
+};
+
static void mctp_usb_out_complete(struct urb *urb)
{
struct mctp_usblib_tx_ctx *tx_ctx = urb->context;
@@ -71,6 +77,9 @@ static int mctp_usb_tx_send(struct mctp_usblib_tx_ctx *tx_ctx,
usb_sndbulkpipe(mctp_usb->usbdev, mctp_usb->ep_out),
data, len, mctp_usb_out_complete, tx_ctx);
+ if (mctp_usb->span)
+ urb->transfer_flags |= URB_ZERO_PACKET;
+
netif_stop_queue(mctp_usb->netdev);
usb_anchor_urb(urb, &mctp_usb->tx_anchor);
@@ -296,6 +305,7 @@ static int mctp_usb_probe(struct usb_interface *intf,
struct usb_host_interface *iface_desc;
struct net_device *netdev;
struct mctp_usb *dev;
+ bool span;
int rc;
/* only one alternate */
@@ -307,6 +317,8 @@ static int mctp_usb_probe(struct usb_interface *intf,
return rc;
}
+ span = iface_desc->desc.bInterfaceSubClass == MCTP_USB_SUBCLASS_SPAN;
+
netdev = alloc_netdev(sizeof(*dev), "mctpusb%d", NET_NAME_ENUM,
mctp_usb_netdev_setup);
if (!netdev)
@@ -314,14 +326,18 @@ static int mctp_usb_probe(struct usb_interface *intf,
SET_NETDEV_DEV(netdev, &intf->dev);
dev = netdev_priv(netdev);
+ dev->span = span;
dev->netdev = netdev;
dev->usbdev = interface_to_usbdev(intf);
dev->intf = intf;
spin_lock_init(&dev->rx_lock);
+ if (dev->span)
+ netdev->max_mtu = MCTP_USB_1_1_MTU_MAX;
usb_set_intfdata(intf, dev);
- mctp_usblib_rx_init(&dev->rx, le16_to_cpu(ep_in->wMaxPacketSize), false);
- mctp_usblib_tx_init(&dev->tx, &tx_ops, dev, false);
+ mctp_usblib_rx_init(&dev->rx, le16_to_cpu(ep_in->wMaxPacketSize),
+ dev->span);
+ mctp_usblib_tx_init(&dev->tx, &tx_ops, dev, dev->span);
init_usb_anchor(&dev->tx_anchor);
dev->ep_in = ep_in->bEndpointAddress;
@@ -362,7 +378,8 @@ static void mctp_usb_disconnect(struct usb_interface *intf)
}
static const struct usb_device_id mctp_usb_devices[] = {
- { USB_INTERFACE_INFO(USB_CLASS_MCTP, 0x0, 0x1) },
+ { USB_INTERFACE_INFO(USB_CLASS_MCTP, MCTP_USB_SUBCLASS_BASE, 0x1) },
+ { USB_INTERFACE_INFO(USB_CLASS_MCTP, MCTP_USB_SUBCLASS_SPAN, 0x1) },
{ 0 },
};
--
2.47.3
^ permalink raw reply related
* [PATCH net-next v3 10/12] net: mctp: usblib: Add initial kunit tests
From: Jeremy Kerr @ 2026-07-08 9:58 UTC (permalink / raw)
To: Matt Johnston, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Greg Kroah-Hartman
Cc: netdev, linux-usb
In-Reply-To: <20260708-dev-mctp-usb-1-1-v3-0-9e710155cdbf@codeconstruct.com.au>
Add some initial tests for the usblib receive path, where we're
extracting MCTP packets from incoming USB transfer data.
Signed-off-by: Jeremy Kerr <jk@codeconstruct.com.au>
---
v2:
- account for KUNIT_ASSERT-based exits; do cleanup through kunit_action
facilities.
- fix off-by-one in packet count duing skb length checks, in case we
ended up with more skbs than expected
- perform route updates under rntl lock
---
drivers/net/mctp/Kconfig | 5 +
drivers/net/mctp/mctp-usblib-test.c | 410 ++++++++++++++++++++++++++++++++++++
drivers/net/mctp/mctp-usblib.c | 4 +
3 files changed, 419 insertions(+)
diff --git a/drivers/net/mctp/Kconfig b/drivers/net/mctp/Kconfig
index a564a792801d..c40ac9c665b7 100644
--- a/drivers/net/mctp/Kconfig
+++ b/drivers/net/mctp/Kconfig
@@ -57,6 +57,11 @@ config MCTP_TRANSPORT_USBLIB
This will be automatically enabled by the transport driver.
+config MCTP_TRANSPORT_USBLIB_TEST
+ bool "MCTP usblib tests" if !KUNIT_ALL_TESTS
+ depends on MCTP_TRANSPORT_USBLIB=y && KUNIT=y
+ default KUNIT_ALL_TESTS
+
config MCTP_TRANSPORT_USB
tristate "MCTP USB transport"
depends on USB
diff --git a/drivers/net/mctp/mctp-usblib-test.c b/drivers/net/mctp/mctp-usblib-test.c
new file mode 100644
index 000000000000..2a22be999fa0
--- /dev/null
+++ b/drivers/net/mctp/mctp-usblib-test.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * mctp-usblib-test.c - MCTP-over-USB (DMTF DSP0283) transport helper library,
+ * unit test definitions.
+ *
+ * Copyright (C) 2026 Code Construct Pty Ltd
+ */
+
+#include <uapi/linux/netdevice.h>
+#include <linux/netdevice.h>
+#include <kunit/test.h>
+#include <linux/if_arp.h>
+#include <net/mctp.h>
+#include <net/mctpdevice.h>
+#include <linux/usb/mctp-usb.h>
+
+struct mctp_usblib_test_dev {
+ struct net_device *ndev;
+ struct mctp_dev *mdev;
+ struct sk_buff_head rx_pkts;
+};
+
+struct mctp_usblib_test_ctx {
+ struct mctp_usblib_test_dev *dev;
+ struct mctp_route rt;
+};
+
+static netdev_tx_t mctp_usblib_dev_tx(struct sk_buff *skb,
+ struct net_device *ndev)
+{
+ /* we don't track any TXed packets at present */
+ kfree_skb(skb);
+ return NETDEV_TX_OK;
+}
+
+static const struct net_device_ops mctp_test_netdev_ops = {
+ .ndo_start_xmit = mctp_usblib_dev_tx,
+};
+
+static const u16 ep_maxpacket = 512;
+static const mctp_eid_t local_eid = 8;
+
+static void mctp_usblib_dev_setup(struct net_device *ndev)
+{
+ ndev->type = ARPHRD_MCTP;
+ ndev->mtu = 8192;
+ ndev->flags = IFF_NOARP;
+ ndev->netdev_ops = &mctp_test_netdev_ops;
+ ndev->needs_free_netdev = true;
+ ndev->pcpu_stat_type = NETDEV_PCPU_STAT_DSTATS;
+}
+
+static void mctp_usblib_test_dev_action(void *data)
+{
+ struct mctp_usblib_test_dev *dev = data;
+
+ skb_queue_purge(&dev->rx_pkts);
+ if (dev->mdev)
+ mctp_dev_put(dev->mdev);
+ unregister_netdev(dev->ndev);
+}
+
+static struct mctp_usblib_test_dev *
+mctp_usblib_test_create_dev(struct kunit *test)
+{
+ struct mctp_usblib_test_dev *dev;
+ struct net_device *ndev;
+ int rc;
+
+ ndev = alloc_netdev(sizeof(*dev), "mctptest%d", NET_NAME_ENUM,
+ mctp_usblib_dev_setup);
+ if (!ndev)
+ return NULL;
+
+ dev = netdev_priv(ndev);
+ dev->ndev = ndev;
+ skb_queue_head_init(&dev->rx_pkts);
+
+ rc = register_netdev(ndev);
+ if (rc) {
+ free_netdev(ndev);
+ return NULL;
+ }
+
+ rc = kunit_add_action_or_reset(test, mctp_usblib_test_dev_action, dev);
+ if (rc)
+ return NULL;
+
+ rcu_read_lock();
+ dev->mdev = __mctp_dev_get(ndev);
+ if (dev->mdev)
+ dev->mdev->net = mctp_default_net(dev_net(ndev));
+ rcu_read_unlock();
+
+ if (!dev->mdev)
+ return NULL;
+
+ rtnl_lock();
+ rc = dev_open(ndev, NULL);
+ rtnl_unlock();
+ if (rc)
+ return NULL;
+
+ return dev;
+}
+
+static int mctp_usblib_test_dst_output(struct mctp_dst *dst,
+ struct sk_buff *skb)
+{
+ struct mctp_usblib_test_dev *dev = netdev_priv(skb->dev);
+
+ skb_queue_tail(&dev->rx_pkts, skb);
+
+ return 0;
+}
+
+static void mctp_usblib_test_fini_action(void *data)
+{
+ struct mctp_usblib_test_ctx *ctx = data;
+
+ /* The device will have been destroyed, so ->rt will be unlinked.
+ * Just ensure that the refcount is as expected.
+ */
+ KUNIT_ASSERT_TRUE(current->kunit_test,
+ refcount_dec_and_test(&ctx->rt.refs));
+
+ kfree(ctx);
+}
+
+static struct mctp_usblib_test_ctx *mctp_usblib_test_init(struct kunit *test)
+{
+ struct mctp_usblib_test_ctx *ctx;
+ struct mctp_route *rt;
+ int rc;
+
+ ctx = kzalloc_obj(*ctx);
+ KUNIT_ASSERT_NOT_NULL(test, ctx);
+
+ INIT_LIST_HEAD(&ctx->rt.list);
+ rt = &ctx->rt;
+ refcount_set(&rt->refs, 1);
+
+ rc = kunit_add_action_or_reset(test, mctp_usblib_test_fini_action, ctx);
+ KUNIT_ASSERT_EQ(test, rc, 0);
+
+ ctx->dev = mctp_usblib_test_create_dev(test);
+ KUNIT_ASSERT_NOT_NULL(test, ctx->dev);
+
+ rt->min = local_eid;
+ rt->max = local_eid;
+ rt->dst_type = MCTP_ROUTE_DIRECT;
+ rt->type = RTN_LOCAL;
+ rt->dev = ctx->dev->mdev;
+ rt->output = mctp_usblib_test_dst_output;
+
+ rtnl_lock();
+ list_add_rcu(&ctx->rt.list, &init_net.mctp.routes);
+ refcount_inc(&rt->refs);
+ rtnl_unlock();
+
+ return ctx;
+}
+
+/* Init a MCTP-over-USB packet within a buffer. @len is the length of the
+ * buffer to write, @payload_len is the reported size of the MCTP-over-USB
+ * packet.
+ */
+static void mctp_usblib_test_init_pkt(void *data, size_t len,
+ size_t payload_len)
+{
+ struct {
+ struct mctp_usb_hdr usb;
+ struct mctp_hdr mctp;
+ } hdr;
+
+ hdr.usb.id = cpu_to_be16(MCTP_USB_DMTF_ID);
+ hdr.usb.len = cpu_to_be16(payload_len);
+ hdr.mctp.ver = 1;
+ hdr.mctp.dest = local_eid;
+ hdr.mctp.src = 0;
+ hdr.mctp.flags_seq_tag = 0;
+
+ memcpy(data, &hdr, min(len, sizeof(hdr)));
+ if (len > sizeof(hdr))
+ memset(data + sizeof(hdr), 0, len - sizeof(hdr));
+}
+
+static void action_rx_fini(void *data)
+{
+ struct mctp_usblib_rx *rx = data;
+
+ mctp_usblib_rx_fini(rx);
+ kfree(rx);
+}
+
+static struct mctp_usblib_rx *
+mctp_usblib_test_rx_init(struct kunit *test, bool span)
+{
+ struct mctp_usblib_rx *rx;
+ int rc;
+
+ rx = kzalloc_obj(*rx);
+ if (rx) {
+ rc = kunit_add_action_or_reset(test, action_rx_fini, rx);
+ KUNIT_ASSERT_EQ(test, rc, 0);
+ }
+ KUNIT_ASSERT_NOT_NULL(test, rx);
+ mctp_usblib_rx_init(rx, ep_maxpacket, span);
+
+ return rx;
+}
+
+/* Wrappers for usblib's rx_complete callback, which is intended to be called
+ * from atomic context
+ */
+static int mctp_usblib_test_rx_complete(struct net_device *netdev,
+ struct mctp_usblib_rx *rx, size_t len)
+{
+ int rc;
+
+ local_bh_disable();
+ rc = mctp_usblib_rx_complete(netdev, rx, len);
+ local_bh_enable();
+
+ return rc;
+}
+
+/* Single packet, starting on a transfer boundary, contained entirely within
+ * the transfer
+ */
+static void mctp_usblib_test_rx_single(struct kunit *test)
+{
+ struct mctp_usblib_test_dev *dev;
+ struct mctp_usblib_test_ctx *ctx;
+ struct mctp_usblib_rx *rx;
+ struct sk_buff *skb;
+ size_t len;
+ void *buf;
+ int rc;
+
+ ctx = mctp_usblib_test_init(test);
+ dev = ctx->dev;
+
+ rx = mctp_usblib_test_rx_init(test, true);
+
+ rc = mctp_usblib_rx_prepare(dev->ndev, rx,
+ &buf, &len, GFP_KERNEL);
+ KUNIT_ASSERT_EQ(test, rc, 0);
+
+ /* we should always have a maxpacket of transfer available */
+ KUNIT_ASSERT_GE(test, len, ep_maxpacket);
+
+ mctp_usblib_test_init_pkt(buf, 8, 8);
+
+ rc = mctp_usblib_test_rx_complete(dev->ndev, rx, 8);
+ KUNIT_ASSERT_EQ(test, rc, 0);
+
+ skb = __skb_dequeue(&dev->rx_pkts);
+ KUNIT_EXPECT_NOT_NULL(test, skb);
+ if (skb)
+ KUNIT_EXPECT_EQ(test, skb->len, 4);
+ kfree_skb(skb);
+}
+
+struct mctp_usblib_test_pkt_span {
+ const char *name;
+ size_t n_pkts;
+ size_t pkts[6];
+ size_t n_xfers;
+ size_t xfers[6];
+};
+
+static void
+mctp_usblib_test_pkt_span_to_desc(const struct mctp_usblib_test_pkt_span *t,
+ char *desc)
+{
+ strscpy(desc, t->name, KUNIT_PARAM_DESC_SIZE);
+}
+
+static void
+mctp_usblib_test_pkt_span_validate(struct kunit *test,
+ const struct mctp_usblib_test_pkt_span *span,
+ size_t *len)
+{
+ size_t pkt_len = 0, xfer_len = 0;
+ unsigned int i;
+
+ for (i = 0; i < span->n_pkts; i++) {
+ KUNIT_ASSERT_GE_MSG(test, span->pkts[i], 8,
+ "pkt[%d] len too small (%zd) for %s",
+ i, span->pkts[i], span->name);
+ pkt_len += span->pkts[i];
+ }
+
+ for (i = 0; i < span->n_xfers; i++)
+ xfer_len += span->xfers[i];
+
+ KUNIT_ASSERT_EQ_MSG(test, pkt_len, xfer_len,
+ "invalid pkt_len (%zd) != xfer_len (%zd) for %s",
+ pkt_len, xfer_len, span->name);
+
+ *len = pkt_len;
+}
+
+static void mctp_usblib_test_rx_pkt_span(struct kunit *test)
+{
+ const struct mctp_usblib_test_pkt_span *pkt_span = test->param_value;
+ size_t len, xfer_len, off, xfer_off;
+ struct mctp_usblib_test_dev *dev;
+ struct mctp_usblib_test_ctx *ctx;
+ struct mctp_usblib_rx *rx;
+ unsigned int i;
+ u8 *pktbuf;
+ void *buf;
+ int rc;
+
+ mctp_usblib_test_pkt_span_validate(test, pkt_span, &len);
+ pktbuf = kunit_kmalloc_array(test, 1, len, GFP_KERNEL);
+ KUNIT_ASSERT_NOT_NULL(test, pktbuf);
+
+ /* lay out packets */
+ for (off = 0, i = 0; i < pkt_span->n_pkts; i++) {
+ len = pkt_span->pkts[i];
+ mctp_usblib_test_init_pkt(pktbuf + off, len, len);
+ off += len;
+ }
+
+ ctx = mctp_usblib_test_init(test);
+ dev = ctx->dev;
+
+ rx = mctp_usblib_test_rx_init(test, true);
+
+ /* feed transfers */
+ for (off = 0, xfer_off = 0, i = 0; i < pkt_span->n_xfers;) {
+ xfer_len = pkt_span->xfers[i] - xfer_off;
+ rc = mctp_usblib_rx_prepare(dev->ndev, rx,
+ &buf, &len, GFP_KERNEL);
+ KUNIT_ASSERT_EQ(test, rc, 0);
+
+ KUNIT_ASSERT_GE(test, len, ep_maxpacket);
+
+ len = min(len, xfer_len);
+ memcpy(buf, pktbuf + off, len);
+
+ if (len == xfer_len) {
+ /* whole/end xfer, proceed to next */
+ xfer_off = 0;
+ i++;
+ } else {
+ /* partial */
+ xfer_off += len;
+ }
+
+ rc = mctp_usblib_test_rx_complete(dev->ndev, rx, len);
+ KUNIT_ASSERT_EQ(test, rc, 0);
+ off += len;
+ }
+
+ /* check received packets */
+ KUNIT_EXPECT_EQ(test, dev->rx_pkts.qlen, pkt_span->n_pkts);
+ for (i = 0; ; i++) {
+ struct sk_buff *skb = __skb_dequeue(&dev->rx_pkts);
+
+ if (!skb)
+ break;
+
+ if (i < pkt_span->n_pkts)
+ KUNIT_EXPECT_EQ(test, skb->len, pkt_span->pkts[i] - 4);
+
+ kfree_skb(skb);
+ }
+}
+
+static const struct mctp_usblib_test_pkt_span mctp_usblib_test_pkt_spans[] = {
+ /* One packet completely within a transfer */
+ { "1p1x-complete", 1, { 8 }, 1, { 8 } },
+ /* Two small packets combined within one transfer */
+ { "2p1x-combined", 2, { 8, 8 }, 1, { 16 } },
+ /* A packet split over two transfers, at the MCTP payload */
+ { "1p2x-split-payload", 1, { 16 }, 2, { 8, 8 } },
+ /* A packet split over two transfers, at the USB transport header */
+ { "1p2x-split-usbhdr", 1, { 16 }, 2, { 2, 14 } },
+ /* A packet split over two transfers, at the MCTP header */
+ { "1p2x-split-mctphdr", 1, { 16 }, 2, { 6, 10 } },
+ /* Single packet split over 3 transfers, middle entirely continuation */
+ { "1p3x-split", 1, { 12 }, 3, { 4, 4, 4 } },
+ /* Max-sized single transfer */
+ { "1p1x-large", 1, { 8191 }, 1, { 8191 } },
+ /* Two large packets, split at the worst-case for allocation, with a
+ * single byte continuing the span
+ */
+ { "2p2x-large-split", 2, { 8190, 8190 }, 2, { 8191, 8189 } },
+};
+
+KUNIT_ARRAY_PARAM(mctp_usblib_test_rx_pkt_span, mctp_usblib_test_pkt_spans,
+ mctp_usblib_test_pkt_span_to_desc);
+
+static struct kunit_case mctp_usblib_test_cases[] = {
+ KUNIT_CASE(mctp_usblib_test_rx_single),
+ KUNIT_CASE_PARAM(mctp_usblib_test_rx_pkt_span,
+ mctp_usblib_test_rx_pkt_span_gen_params),
+ {}
+};
+
+static struct kunit_suite mctp_usblib_test_suite = {
+ .name = "mctp-usblib",
+ .test_cases = mctp_usblib_test_cases,
+};
+
+kunit_test_suite(mctp_usblib_test_suite);
diff --git a/drivers/net/mctp/mctp-usblib.c b/drivers/net/mctp/mctp-usblib.c
index 4131be31db1a..fc0282152e6e 100644
--- a/drivers/net/mctp/mctp-usblib.c
+++ b/drivers/net/mctp/mctp-usblib.c
@@ -610,3 +610,7 @@ EXPORT_SYMBOL_GPL(mctp_usblib_tx_cancel);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jeremy Kerr <jk@codeconstruct.com.au>");
MODULE_DESCRIPTION("MCTP USB transport library");
+
+#if IS_ENABLED(CONFIG_MCTP_TRANSPORT_USBLIB_TEST)
+#include "mctp-usblib-test.c"
+#endif
--
2.47.3
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