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From: Samuel Pitoiset <samuel.pitoiset-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Ilia Mirkin <imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>,
	nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
Date: Mon, 17 Oct 2016 11:46:11 +0200	[thread overview]
Message-ID: <2183f35a-731b-fe0c-e090-45315390a48d@gmail.com> (raw)
In-Reply-To: <1476645274-9939-4-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>

Few comments below.

On 10/16/2016 09:14 PM, Ilia Mirkin wrote:
> This flips GM10x to using the updated format, which is what I tested
> with. However GM20x and GP10x also use this TIC format.
>
> Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
> ---
>  src/nvc0_accel.c | 11 ++++++++++
>  src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
>  src/nvc0_exa.c   | 22 ++++---------------
>  src/nvc0_xv.c    | 67 +++++++++++++++++++-------------------------------------
>  4 files changed, 93 insertions(+), 63 deletions(-)
>
> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
> index 0682806..8da5051 100644
> --- a/src/nvc0_accel.c
> +++ b/src/nvc0_accel.c
> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
>  		PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
>  		PUSH_DATA (push, (bo->offset + MISC_OFFSET));
>  		PUSH_DATA (push, 1);
> +	} else {
> +		/* Use new TIC format. Not strictly necessary for GM20x+ */

Yes, but it's also enabled by default in mesa, looks fine.

> +		IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
> +		if (pNv->dev->chipset >= 0x120) {
> +			/* Use center sample locations. */
> +			BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
> +			PUSH_DATA (push, 0x88888888);
> +			PUSH_DATA (push, 0x88888888);
> +			PUSH_DATA (push, 0x88888888);
> +			PUSH_DATA (push, 0x88888888);
> +		}
>  	}
>
>  	BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
> diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
> index 607e97b..9378236 100644
> --- a/src/nvc0_accel.h
> +++ b/src/nvc0_accel.h
> @@ -7,6 +7,7 @@
>  #include "hwdefs/nvc0_m2mf.xml.h"
>  #include "hwdefs/nv50_defs.xml.h"
>  #include "hwdefs/nv50_texture.h"
> +#include "hwdefs/gm107_texture.xml.h"
>  #include "hwdefs/nv_3ddefs.xml.h"
>
>  /* subchannel assignments, compatible with kepler's fixed layout  */
> @@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct nouveau_bo *bo,
>  	}
>  }
>
> +static __inline__ void
> +PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned offset,
> +	 unsigned width, unsigned height, unsigned pitch, unsigned format)
> +{
> +	if (push->client->device->chipset < 0x110) {
> +		unsigned tic2 = 0xd0001000;
> +		if (pitch == 0)
> +			tic2 |= 0x00004000;
> +		else
> +			tic2 |= 0x0005c000;
> +		PUSH_DATA(push, format);
> +		PUSH_DATA(push, bo->offset + offset);
> +		PUSH_DATA(push, ((bo->offset + offset) >> 32) |
> +			        (bo->config.nvc0.tile_mode << 18) |
> +			        tic2);
> +		PUSH_DATA(push, 0x00300000);
> +		PUSH_DATA(push, 0x80000000 | width);
> +		PUSH_DATA(push, 0x00010000 | height);
> +		PUSH_DATA (push, 0x03000000);
> +		PUSH_DATA (push, 0x00000000);

Cosmetic.

> +	} else {
> +		unsigned tile_mode = bo->config.nvc0.tile_mode;
> +		PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) << 1));
> +		PUSH_DATA(push, bo->offset + offset);
> +		if (pitch == 0) {
> +			PUSH_DATA(push, ((bo->offset + offset) >> 32) |
> +				  GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
> +			PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
> +				  (tile_mode & 0x007) |
> +				  (tile_mode & 0x070 >> (4 - 3)) |
> +				  (tile_mode & 0x700 >> (8 - 6)));
> +			PUSH_DATA(push, GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
> +				  GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
> +				  GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
> +				  (width - 1));
> +			PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
> +				        ((height - 1) & 0xffff));
> +			PUSH_DATA(push, GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO |
> +				        GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
> +			PUSH_DATA(push, 0x00000000);
> +		} else {
> +			PUSH_DATA(push, ((bo->offset + offset) >> 32) |
> +				        GM107_TIC2_2_HEADER_VERSION_PITCH);
> +			PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
> +				        (pitch >> 5));
> +			PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
> +				  GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
> +				  (width - 1));
> +			PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | (height - 1));
> +			PUSH_DATA(push, 0x000000000);
> +			PUSH_DATA(push, 0x000000000);
> +		}
> +	}
> +}
> +
>  #endif
> diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
> index a53dfe6..c8ace97 100644
> --- a/src/nvc0_exa.c
> +++ b/src/nvc0_exa.c
> @@ -538,14 +538,8 @@ NVC0EXAPictSolid(NVPtr pNv, PicturePtr ppict, unsigned unit)
>  	PUSH_DATAu(push, pNv->scratch, SOLID(unit), 1);
>  	PUSH_DATA (push, ppict->pSourcePict->solidFill.color);
>  	PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
> -	PUSH_DATA (push, _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
> -	PUSH_DATA (push,  offset);
> -	PUSH_DATA (push, (offset >> 32) | 0xd005d000);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, 0x00000001);
> -	PUSH_DATA (push, 0x00010001);
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
> +	PUSH_TIC  (push, pNv->scratch, SOLID(unit), 1, 1, 4,
> +		   _(B_C0, G_C1, R_C2, A_C3, 8_8_8_8));
>  	PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
>  	PUSH_DATA (push, NV50TSC_1_0_WRAPS_REPEAT |
>  			 NV50TSC_1_0_WRAPT_REPEAT |
> @@ -651,16 +645,8 @@ NVC0EXAPictTexture(NVPtr pNv, PixmapPtr ppix, PicturePtr ppict, unsigned unit)
>
>  	PUSH_REFN (push, bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
>  	PUSH_DATAu(push, pNv->scratch, TIC_OFFSET + (unit * 32), 8);
> -	PUSH_DATA (push, format);
> -	PUSH_DATA (push, bo->offset);
> -	PUSH_DATA (push, (bo->offset >> 32) |
> -			 (bo->config.nvc0.tile_mode << 18) |
> -			 0xd0005000);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, (1 << 31) | ppix->drawable.width);
> -	PUSH_DATA (push, (1 << 16) | ppix->drawable.height);
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
> +	PUSH_TIC  (push, bo, 0, ppix->drawable.width, ppix->drawable.height, 0,
> +		   format);
>
>  	PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
>  	if (ppict->repeat) {
> diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
> index 129c505..c3e58da 100644
> --- a/src/nvc0_xv.c
> +++ b/src/nvc0_xv.c
> @@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
>  		{ dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
>  	};
>  	struct nouveau_pushbuf *push = pNv->pushbuf;
> -	uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
>  	float X1, X2, Y1, Y2;
>  	BoxPtr pbox;
>  	int nbox;
> @@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
>
>  	PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16);
>  	if (id == FOURCC_YV12 || id == FOURCC_I420) {
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
> +		PUSH_TIC(push, src, packed_y, width, height, 0,
> +			 NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
>  			 NV50TIC_0_0_FMT_8);
> -	PUSH_DATA (push, ((src->offset + packed_y)));
> -	PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, width);
> -	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
> +		PUSH_TIC(push, src, uv, width >> 1, height >> 1, 0,

At first look, this seems wrong. Why do you shift width/height here?

> +			 NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
>  			 NV50TIC_0_0_FMT_8_8);
> -	PUSH_DATA (push, ((src->offset + uv)));
> -	PUSH_DATA (push, ((src->offset + uv) >> 32) | mode);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, width >> 1);
> -	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >> 1));
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
>  	} else {
> -	if (id == FOURCC_UYVY) {
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
> +		unsigned format;
> +		if (id == FOURCC_UYVY) {
> +		format = NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
> -			 NV50TIC_0_0_FMT_8_8);
> -	} else {
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
> +			 NV50TIC_0_0_FMT_8_8;
> +		} else {
> +		format = NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
> -			 NV50TIC_0_0_FMT_8_8);
> -	}
> -	PUSH_DATA (push, ((src->offset + packed_y)));
> -	PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, width);
> -	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
> -	if (id == FOURCC_UYVY) {
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
> +			 NV50TIC_0_0_FMT_8_8;
> +		}
> +		PUSH_TIC(push, src, packed_y, width, height, 0, format);
> +
> +		if (id == FOURCC_UYVY) {
> +		format = NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
> -			 NV50TIC_0_0_FMT_8_8_8_8);
> -	} else {
> -	PUSH_DATA (push, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
> +			 NV50TIC_0_0_FMT_8_8_8_8;
> +		} else {
> +		format = NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
>  			 NV50TIC_0_0_MAPB_C1 | NV50TIC_0_0_TYPEB_UNORM |
>  			 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
>  			 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
> -			 NV50TIC_0_0_FMT_8_8_8_8);
> -	}
> -	PUSH_DATA (push, ((src->offset + packed_y)));
> -	PUSH_DATA (push, ((src->offset + packed_y) >> 32) | mode);
> -	PUSH_DATA (push, 0x00300000);
> -	PUSH_DATA (push, (width >> 1));
> -	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
> -	PUSH_DATA (push, 0x03000000);
> -	PUSH_DATA (push, 0x00000000);
> +			 NV50TIC_0_0_FMT_8_8_8_8;
> +		}
> +		PUSH_TIC(push, src, packed_y, width >> 1, height, 0, format);
>  	}
>
>  	PUSH_DATAu(push, pNv->scratch, TSC_OFFSET, 16);
>

-- 
-Samuel
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Nouveau@lists.freedesktop.org
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  parent reply	other threads:[~2016-10-17  9:46 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-16 19:14 [PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format Ilia Mirkin
     [not found] ` <1476645274-9939-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
2016-10-16 19:14   ` [PATCH 2/5] nvc0: make use of the new hwdefs for TEX_CB_INDEX Ilia Mirkin
     [not found]     ` <1476645274-9939-2-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
2016-10-17  9:31       ` Samuel Pitoiset
2016-10-16 19:14   ` [PATCH 3/5] nvc0: rename BEGIN_IMC0 to IMMED_NVC0 Ilia Mirkin
     [not found]     ` <1476645274-9939-3-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
2016-10-17  9:31       ` Samuel Pitoiset
2016-10-16 19:14   ` [PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation Ilia Mirkin
     [not found]     ` <1476645274-9939-4-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
2016-10-17  9:46       ` Samuel Pitoiset [this message]
     [not found]         ` <2183f35a-731b-fe0c-e090-45315390a48d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-10-17 12:24           ` Ilia Mirkin
     [not found]             ` <CAKb7Uvi=97nnPn0Kypud0bm9UWRmCMct+8UfcmuK4qxLp7P9pw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-10-17 12:37               ` Samuel Pitoiset
2016-10-16 19:14   ` [PATCH 5/5] recognize and accelerate GM20x Ilia Mirkin
     [not found]     ` <1476645274-9939-5-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
2016-10-17  9:47       ` Samuel Pitoiset
     [not found]         ` <ca9bc26d-f9b4-9cd9-17b8-e8f0a087db91-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-10-18  9:19           ` Alexandre Courbot
     [not found]             ` <CAAVeFuLEwcyJEjShVVp1cqRdrXbk7SHEJf+otqQqu5CkPr3-dg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-10-19 12:19               ` Martin Peres
2016-10-17  9:31   ` [PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format Samuel Pitoiset
2016-10-17 17:30   ` Emil Velikov

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