Re: [PATCH v12 15/22] gpu: nova-core: Hopper/Blackwell: add FSP message infrastructure

["Alexandre Courbot" <acourbot@nvidia.com>]

On Tue Jun 2, 2026 at 12:21 PM JST, John Hubbard wrote:
<snip>
> diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
> index da7a10c0346a..8c51609d0281 100644
> --- a/drivers/gpu/nova-core/regs.rs
> +++ b/drivers/gpu/nova-core/regs.rs
> @@ -576,6 +576,27 @@ pub(crate) fn mem_scrubbing_done(self) -> bool {
>      }
>  }
>  
> +// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust.
> +// These registers manage falcon EMEM communication queues.
> +
> +register! {
> +    pub(crate) NV_PFSP_QUEUE_HEAD(u32) @ 0x008f2c00 {
> +        31:0    address => u32;
> +    }
> +
> +    pub(crate) NV_PFSP_QUEUE_TAIL(u32) @ 0x008f2c04 {
> +        31:0    address => u32;
> +    }
> +
> +    pub(crate) NV_PFSP_MSGQ_HEAD(u32) @ 0x008f2c80 {
> +        31:0    address => u32;
> +    }
> +
> +    pub(crate) NV_PFSP_MSGQ_TAIL(u32) @ 0x008f2c84 {
> +        31:0    address => u32;
> +    }

For these last two, OpenRM names the field `val`, not `address`.

> +}

In OpenRM these 4 registers are also actually arrays of 8 (because of
the 8 channels for which EMEM is also divided). Although we only use the
first one for now, I think that fact should be reflected here, e.g.

    pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 {
        ...
    }

With user code converted to e.g:

    bar.write(
        Array::at(0),
        regs::NV_PFSP_QUEUE_HEAD::zeroed().with_address(0),
    );

`poll_msgq`, `send_msg` an `recv_msg` should normally take an extra
`channel` argument as a result, but since we are not dividing EMEM
accordingly and using only channel 0 for now, I think this can be done
later.