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From: "Alexandre Courbot" <acourbot@nvidia.com>
To: "Antonin Malzieu Ridolfi via B4 Relay"
	<devnull+dev.nanonej.com@kernel.org>
Cc: <dev@nanonej.com>, "Danilo Krummrich" <dakr@kernel.org>,
	"Alice Ryhl" <aliceryhl@google.com>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>, <nova-gpu@lists.linux.dev>,
	<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
	<daniel.almeida@collabora.com>
Subject: Re: [PATCH 1/3] gpu: nova-core: Add function to query WPR2 range
Date: Sat, 25 Jul 2026 22:24:11 +0900	[thread overview]
Message-ID: <DK7OOBTQZKDQ.QOMIKY35YTVP@nvidia.com> (raw)
In-Reply-To: <20260721-nova-core-regs-split-v1-1-384fa2a42244@nanonej.com>

On Wed Jul 22, 2026 at 12:41 AM JST, Antonin Malzieu Ridolfi via B4 Relay wrote:
> From: Antonin Malzieu Ridolfi <dev@nanonej.com>
>
> Create new function abstracting WPR2 region range query.
> Refactor gsp hal tu102 to query the WPR2 region range using this new
> function.
>
> Suggested-by: Alexandre Courbot <acourbot@nvidia.com>
> Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com>
> ---
>  drivers/gpu/nova-core/fb.rs            | 15 +++++++++
>  drivers/gpu/nova-core/gsp/hal/tu102.rs | 58 +++++++++++++++-------------------
>  2 files changed, 41 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs
> index 273cff752fae..864a34ca20b8 100644
> --- a/drivers/gpu/nova-core/fb.rs
> +++ b/drivers/gpu/nova-core/fb.rs
> @@ -270,3 +270,18 @@ pub(crate) fn new(chipset: Chipset, bar: Bar0<'_>, gsp_fw: &GspFirmware) -> Resu
>          })
>      }
>  }
> +
> +/// Reads the WPR2 memory region registers and returns the range if set.
> +/// Returns `None` if the WPR2 region is not set.
> +pub(crate) fn wpr2_range(bar: Bar0<'_>) -> Option<Range<u64>> {
> +    let (wpr2_lo, wpr2_hi) = (
> +        bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO),
> +        bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI),
> +    );
> +
> +    if !wpr2_hi.is_wpr2_set() {
> +        return None;
> +    }

To preserve the current semantics, let's read WPR_ADDR_HI first, check
`is_wpr2_set` (and early-return `None` if not set), and then read
`WPR_ADDR_LO` to build the range.

> +
> +    Some(wpr2_lo.lower_bound()..wpr2_hi.higher_bound())
> +}
> diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core/gsp/hal/tu102.rs
> index 29bb17171f56..b3242aaeea45 100644
> --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs
> +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs
> @@ -17,7 +17,10 @@
>          sec2::Sec2,
>          Falcon, //
>      },
> -    fb::FbLayout,
> +    fb::{
> +        wpr2_range,
> +        FbLayout, //
> +    },
>      firmware::{
>          booter::{
>              BooterFirmware,
> @@ -90,9 +93,8 @@ fn run(&self, ctx: &mut GspBootContext<'_, '_>) -> Result {
>              .inspect_err(|e| dev_err!(dev, "FWSEC-SB failed to run: {:?}\n", e));
>  
>          // Remove WPR2 region if set.
> -        let wpr2_hi = bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI);
>          let booter_unloader_res = (|| {
> -            if !wpr2_hi.is_wpr2_set() {
> +            if wpr2_range(bar).is_none() {
>                  return Ok(());
>              }
>  
> @@ -110,8 +112,7 @@ fn run(&self, ctx: &mut GspBootContext<'_, '_>) -> Result {
>              }
>  
>              // Confirm that the WPR2 region has been removed.
> -            let wpr2_hi = bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI);
> -            if wpr2_hi.is_wpr2_set() {
> +            if wpr2_range(bar).is_some() {
>                  dev_err!(
>                      dev,
>                      "WPR2 region still set after Booter Unloader returned\n"
> @@ -144,9 +145,9 @@ fn run_fwsec_frts(
>          bios: &Vbios,
>          fb_layout: &FbLayout,
>      ) -> Result {
> -        // Check that the WPR2 region does not already exist - if it does, we cannot run
> -        // FWSEC-FRTS until the GPU is reset.
> -        if bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound() != 0 {
> +        // Check that the WPR2 region does not already exist -
> +        // if it does, we cannot run FWSEC-FRTS until the GPU is reset.

This comment is reformatted for now good reason iiuc.

  reply	other threads:[~2026-07-25 13:24 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-21 15:41 [PATCH 0/3] gpu: nova-core: Move PFB and PBUS register Antonin Malzieu Ridolfi via B4 Relay
2026-07-21 15:41 ` [PATCH 1/3] gpu: nova-core: Add function to query WPR2 range Antonin Malzieu Ridolfi via B4 Relay
2026-07-25 13:24   ` Alexandre Courbot [this message]
2026-07-21 15:41 ` [PATCH 2/3] gpu: nova-core: Move PFB registers definitions Antonin Malzieu Ridolfi via B4 Relay
2026-07-25 13:27   ` Alexandre Courbot
2026-07-21 15:41 ` [PATCH 3/3] gpu: nova-core: Move one PBUS register definition Antonin Malzieu Ridolfi via B4 Relay
2026-07-21 15:51   ` Nanonej Dev
2026-07-25 13:28     ` Alexandre Courbot
2026-07-25 13:30   ` Alexandre Courbot
2026-07-21 15:46 ` [PATCH 0/3] gpu: nova-core: Move PFB and PBUS register Nanonej Dev

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