From: Jon Mason <jdmason@kudzu.us>
To: Dave Jiang <dave.jiang@intel.com>
Cc: Allen.Hubbe@emc.com, linux-ntb@googlegroups.com,
Sandeep Mann <sandeep@purestorage.com>,
Zachary Ross <zacharyx.ross@intel.com>
Subject: Re: [PATCH] ntb: fix SKX NTB config space size register offsets
Date: Wed, 21 Dec 2016 11:54:14 -0500 [thread overview]
Message-ID: <20161221165413.GD32599@kudzu.us> (raw)
In-Reply-To: <148164499341.194663.8632238363765425811.stgit@djiang5-desk3.ch.intel.com>
On Tue, Dec 13, 2016 at 09:03:13AM -0700, Dave Jiang wrote:
> The offsets for the SZ registers are wrong. Updated.
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> Reported-by: Sandeep Mann <sandeep@purestorage.com>
> Tested-by: Zachary Ross <zacharyx.ross@intel.com>
Applied to my ntb branch
Thanks,
Jon
> ---
> drivers/ntb/hw/intel/ntb_hw_intel.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h
> index 6e8c182..f2cf8a7 100644
> --- a/drivers/ntb/hw/intel/ntb_hw_intel.h
> +++ b/drivers/ntb/hw/intel/ntb_hw_intel.h
> @@ -152,10 +152,10 @@
> #define XEON_SPAD_COUNT 16
>
> /* Intel Skylake Xeon hardware */
> -#define SKX_IMBAR1SZ_OFFSET 0x00d1
> -#define SKX_IMBAR2SZ_OFFSET 0x00d5
> -#define SKX_EMBAR1SZ_OFFSET 0x00d3
> -#define SKX_EMBAR2SZ_OFFSET 0x00d6
> +#define SKX_IMBAR1SZ_OFFSET 0x00d0
> +#define SKX_IMBAR2SZ_OFFSET 0x00d1
> +#define SKX_EMBAR1SZ_OFFSET 0x00d2
> +#define SKX_EMBAR2SZ_OFFSET 0x00d3
> #define SKX_DEVCTRL_OFFSET 0x0098
> #define SKX_DEVSTS_OFFSET 0x009a
> #define SKX_UNCERRSTS_OFFSET 0x014c
>
> --
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prev parent reply other threads:[~2016-12-21 16:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-13 16:03 [PATCH] ntb: fix SKX NTB config space size register offsets Dave Jiang
2016-12-21 16:54 ` Jon Mason [this message]
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