From: Jon Mason <jdmason@kudzu.us>
To: Allen Hubbe <Allen.Hubbe@dell.com>
Cc: 'Shyam Sundar S K' <ssundark@amd.com>,
"'Yu, Xiangliang'" <Xiangliang.Yu@amd.com>,
'Dave Jiang' <dave.jiang@intel.com>,
"'Shah, Nehal-bakulchandra'" <Nehal-bakulchandra.Shah@amd.com>,
"'Sen, Pankaj'" <Pankaj.Sen@amd.com>,
"'Agrawal, Nitesh-kumar'" <Nitesh-kumar.Agrawal@amd.com>,
"'Su, Richard (Bin)'" <Richard1.Su@amd.com>,
"'Subramaniyan, Ramkumar'" <ramkumar.ks@amd.com>,
linux-ntb@googlegroups.com
Subject: Re: [PATCH 2/2] NTB: Register and offset values fix for memory window
Date: Wed, 21 Dec 2016 11:58:36 -0500 [thread overview]
Message-ID: <20161221165836.GG32599@kudzu.us> (raw)
In-Reply-To: <000001d24c42$f407cc70$dc176550$@dell.com>
On Thu, Dec 01, 2016 at 09:22:37PM -0500, Allen Hubbe wrote:
> From: Shyam Sundar S K
> > Due to incorrect limit and translation register values, NTB link was
> > going down when the memory window was setup. Made appropriate changes
> > as per spec.
> >
> > Fix limit register values for BAR1, which was overlapping
> > with the BAR23 address.
> >
> > Reviewed-by: Sen, Pankaj <Pankaj.Sen@amd.com>
> > Reviewed-by: Shah, Nehal-bakulchandra <Nehal-bakulchandra.Shah@amd.com>
> > Acked-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
> > Signed-off-by: S-k, Shyam-sundar <Shyam-sundar.S-k@amd.com>
>
> Acked-by: Allen Hubbe <Allen.Hubbe@dell.com>
Applied to my NTB branch
Thanks,
Jon
>
> > ---
> > drivers/ntb/hw/amd/ntb_hw_amd.c | 14 ++++----------
> > 1 file changed, 4 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c
> > index 6ccba0d..d59f494 100644
> > --- a/drivers/ntb/hw/amd/ntb_hw_amd.c
> > +++ b/drivers/ntb/hw/amd/ntb_hw_amd.c
> > @@ -138,11 +138,11 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx,
> > base_addr = pci_resource_start(ndev->ntb.pdev, bar);
> >
> > if (bar != 1) {
> > - xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 3);
> > - limit_reg = AMD_BAR23LMT_OFFSET + ((bar - 2) << 3);
> > + xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 2);
> > + limit_reg = AMD_BAR23LMT_OFFSET + ((bar - 2) << 2);
> >
> > /* Set the limit if supported */
> > - limit = base_addr + size;
> > + limit = size;
> >
> > /* set and verify setting the translation address */
> > write64(addr, peer_mmio + xlat_reg);
> > @@ -164,14 +164,8 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx,
> > xlat_reg = AMD_BAR1XLAT_OFFSET;
> > limit_reg = AMD_BAR1LMT_OFFSET;
> >
> > - /* split bar addr range must all be 32 bit */
> > - if (addr & (~0ull << 32))
> > - return -EINVAL;
> > - if ((addr + size) & (~0ull << 32))
> > - return -EINVAL;
> > -
> > /* Set the limit if supported */
> > - limit = base_addr + size;
> > + limit = size;
> >
> > /* set and verify setting the translation address */
> > write64(addr, peer_mmio + xlat_reg);
> > --
> > 2.7.4
>
prev parent reply other threads:[~2016-12-21 16:58 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-01 19:14 [PATCH 2/2] NTB: Register and offset values fix for memory window Shyam Sundar S K
2016-12-02 2:22 ` Allen Hubbe
2016-12-21 16:58 ` Jon Mason [this message]
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