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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, Robert Richter <rrichter@amd.com>,
	<alison.schofield@intel.com>, <terry.bowman@amd.com>,
	<bhelgaas@google.com>, <dave.jiang@intel.com>,
	<nvdimm@lists.linux.dev>
Subject: Re: [PATCH v6 09/12] cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem
Date: Fri, 2 Dec 2022 16:40:52 +0000	[thread overview]
Message-ID: <20221202164052.00007b5c@Huawei.com> (raw)
In-Reply-To: <166993045072.1882361.13944923741276843683.stgit@dwillia2-xfh.jf.intel.com>

On Thu, 01 Dec 2022 13:34:10 -0800
Dan Williams <dan.j.williams@intel.com> wrote:

> tl;dr: Clean up an unnecessary export and enable cxl_test.
> 
> An RCD (Restricted CXL Device), in contrast to a typical CXL device in
> a VH topology, obtains its component registers from the bottom half of
> the associated CXL host bridge RCRB (Root Complex Register Block). In
> turn this means that cxl_rcrb_to_component() needs to be called from
> devm_cxl_add_endpoint().
> 
> Presently devm_cxl_add_endpoint() is part of the CXL core, but the only
> user is the CXL mem module. Move it from cxl_core to cxl_mem to not only
> get rid of an unnecessary export, but to also enable its call out to
> cxl_rcrb_to_component(), in a subsequent patch, to be mocked by
> cxl_test. Recall that cxl_test can only mock exported symbols, and since
> cxl_rcrb_to_component() is itself inside the core, all callers must be
> outside of cxl_core to allow cxl_test to mock it.
> 
> Reviewed-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reasoning for the move is sound and patch is clearly just a move so
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/cxl/core/core.h |    8 --------
>  drivers/cxl/core/port.c |   39 ---------------------------------------
>  drivers/cxl/cxl.h       |    2 --
>  drivers/cxl/cxlmem.h    |    9 +++++++++
>  drivers/cxl/mem.c       |   38 ++++++++++++++++++++++++++++++++++++++
>  5 files changed, 47 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index 1d8f87be283f..8c04672dca56 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -58,14 +58,6 @@ extern struct rw_semaphore cxl_dpa_rwsem;
>  
>  bool is_switch_decoder(struct device *dev);
>  struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
> -static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
> -					 struct cxl_memdev *cxlmd)
> -{
> -	if (!port)
> -		return NULL;
> -
> -	return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
> -}
>  
>  int cxl_memdev_init(void);
>  void cxl_memdev_exit(void);
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index dae2ca31885e..4982b6902ef5 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1212,45 +1212,6 @@ static void reap_dports(struct cxl_port *port)
>  	}
>  }
>  
> -int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd,
> -			  struct cxl_dport *parent_dport)
> -{
> -	struct cxl_port *parent_port = parent_dport->port;
> -	struct cxl_dev_state *cxlds = cxlmd->cxlds;
> -	struct cxl_port *endpoint, *iter, *down;
> -	int rc;
> -
> -	/*
> -	 * Now that the path to the root is established record all the
> -	 * intervening ports in the chain.
> -	 */
> -	for (iter = parent_port, down = NULL; !is_cxl_root(iter);
> -	     down = iter, iter = to_cxl_port(iter->dev.parent)) {
> -		struct cxl_ep *ep;
> -
> -		ep = cxl_ep_load(iter, cxlmd);
> -		ep->next = down;
> -	}
> -
> -	endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
> -				     cxlds->component_reg_phys, parent_dport);
> -	if (IS_ERR(endpoint))
> -		return PTR_ERR(endpoint);
> -
> -	rc = cxl_endpoint_autoremove(cxlmd, endpoint);
> -	if (rc)
> -		return rc;
> -
> -	if (!endpoint->dev.driver) {
> -		dev_err(&cxlmd->dev, "%s failed probe\n",
> -			dev_name(&endpoint->dev));
> -		return -ENXIO;
> -	}
> -
> -	return 0;
> -}
> -EXPORT_SYMBOL_NS_GPL(devm_cxl_add_endpoint, CXL);
> -
>  static void cxl_detach_ep(void *data)
>  {
>  	struct cxl_memdev *cxlmd = data;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 1342e4e61537..9a212ab3cae4 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -560,8 +560,6 @@ struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
>  struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
>  				   resource_size_t component_reg_phys,
>  				   struct cxl_dport *parent_dport);
> -int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd,
> -			  struct cxl_dport *parent_dport);
>  struct cxl_port *find_cxl_root(struct device *dev);
>  int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
>  void cxl_bus_rescan(void);
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index c1c9960ab05f..e082991bc58c 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -80,6 +80,15 @@ static inline bool is_cxl_endpoint(struct cxl_port *port)
>  
>  struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);
>  
> +static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
> +					 struct cxl_memdev *cxlmd)
> +{
> +	if (!port)
> +		return NULL;
> +
> +	return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
> +}
> +
>  /**
>   * struct cxl_mbox_cmd - A command to be submitted to hardware.
>   * @opcode: (input) The command set and command submitted to hardware.
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 549b6b499bae..aa63ce8c7ca6 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -45,6 +45,44 @@ static int cxl_mem_dpa_show(struct seq_file *file, void *data)
>  	return 0;
>  }
>  
> +static int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd,
> +				 struct cxl_dport *parent_dport)
> +{
> +	struct cxl_port *parent_port = parent_dport->port;
> +	struct cxl_dev_state *cxlds = cxlmd->cxlds;
> +	struct cxl_port *endpoint, *iter, *down;
> +	int rc;
> +
> +	/*
> +	 * Now that the path to the root is established record all the
> +	 * intervening ports in the chain.
> +	 */
> +	for (iter = parent_port, down = NULL; !is_cxl_root(iter);
> +	     down = iter, iter = to_cxl_port(iter->dev.parent)) {
> +		struct cxl_ep *ep;
> +
> +		ep = cxl_ep_load(iter, cxlmd);
> +		ep->next = down;
> +	}
> +
> +	endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
> +				     cxlds->component_reg_phys, parent_dport);
> +	if (IS_ERR(endpoint))
> +		return PTR_ERR(endpoint);
> +
> +	rc = cxl_endpoint_autoremove(cxlmd, endpoint);
> +	if (rc)
> +		return rc;
> +
> +	if (!endpoint->dev.driver) {
> +		dev_err(&cxlmd->dev, "%s failed probe\n",
> +			dev_name(&endpoint->dev));
> +		return -ENXIO;
> +	}
> +
> +	return 0;
> +}
> +
>  static int cxl_mem_probe(struct device *dev)
>  {
>  	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> 


  reply	other threads:[~2022-12-02 16:40 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-01 21:33 [PATCH v6 00/12] cxl: Add support for Restricted CXL hosts (RCD mode) Dan Williams
2022-12-01 21:33 ` [PATCH v6 01/12] cxl/acpi: Simplify cxl_nvdimm_bridge probing Dan Williams
2022-12-02 15:02   ` Jonathan Cameron
2022-12-01 21:33 ` [PATCH v6 02/12] cxl/region: Drop redundant pmem region release handling Dan Williams
2022-12-02 15:43   ` Jonathan Cameron
2022-12-01 21:33 ` [PATCH v6 03/12] cxl/pmem: Refactor nvdimm device registration, delete the workqueue Dan Williams
2022-12-02 15:42   ` Jonathan Cameron
2022-12-01 21:33 ` [PATCH v6 04/12] cxl/pmem: Remove the cxl_pmem_wq and related infrastructure Dan Williams
2022-12-02 15:44   ` Jonathan Cameron
2022-12-01 21:33 ` [PATCH v6 05/12] cxl/acpi: Move rescan to the workqueue Dan Williams
2022-12-02 15:50   ` Jonathan Cameron
2022-12-03  7:14     ` Dan Williams
2022-12-01 21:33 ` [PATCH v6 06/12] tools/testing/cxl: Make mock CEDT parsing more robust Dan Williams
2022-12-01 21:57   ` Dave Jiang
2022-12-02 15:58   ` Jonathan Cameron
2022-12-03  7:22     ` Dan Williams
2022-12-01 21:33 ` [PATCH v6 07/12] cxl/ACPI: Register CXL host ports by bridge device Dan Williams
2022-12-01 22:00   ` Dave Jiang
2022-12-02 16:11   ` Jonathan Cameron
2022-12-03  7:28     ` Dan Williams
2022-12-01 21:34 ` [PATCH v6 08/12] cxl/acpi: Extract component registers of restricted hosts from RCRB Dan Williams
2022-12-01 23:55   ` Dave Jiang
2022-12-02  8:16   ` Robert Richter
2022-12-03  7:04     ` Dan Williams
2022-12-03  8:41       ` Dan Williams
2022-12-03 16:03       ` Robert Richter
2022-12-03 17:06         ` Dan Williams
2022-12-02 16:38   ` Jonathan Cameron
2022-12-03  7:39     ` Dan Williams
2022-12-01 21:34 ` [PATCH v6 09/12] cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem Dan Williams
2022-12-02 16:40   ` Jonathan Cameron [this message]
2022-12-01 21:34 ` [PATCH v6 10/12] cxl/port: Add RCD endpoint port enumeration Dan Williams
2022-12-02  8:21   ` Robert Richter
2022-12-03  7:05     ` Dan Williams
2022-12-02 16:45   ` Jonathan Cameron
2022-12-01 21:34 ` [PATCH v6 11/12] tools/testing/cxl: Add an RCH topology Dan Williams
2022-12-02  8:05   ` Robert Richter
2022-12-02 17:04   ` Jonathan Cameron
2022-12-03  7:50     ` Dan Williams
2022-12-01 21:34 ` [PATCH v6 12/12] cxl/acpi: Set ACPI's CXL _OSC to indicate RCD mode support Dan Williams
2022-12-02 17:05   ` Jonathan Cameron

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