* [PATCH v2 1/4] tune-cortexa78.inc: Add cortexa78 tune, based on cortexa77
2024-02-01 20:45 [PATCH v2 0/4] Updates for ARM tunings Mark Hatle
@ 2024-02-01 20:45 ` Mark Hatle
2024-02-01 20:45 ` [PATCH v2 2/4] feature-arm-vfp.inc: Allow hard-float on newer simd targets Mark Hatle
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Mark Hatle @ 2024-02-01 20:45 UTC (permalink / raw)
To: openembedded-core; +Cc: mark.hatle, raj.khem, jon.mason
From: Mark Hatle <mark.hatle@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
---
.../include/arm/armv8-2a/tune-cortexa78.inc | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 meta/conf/machine/include/arm/armv8-2a/tune-cortexa78.inc
diff --git a/meta/conf/machine/include/arm/armv8-2a/tune-cortexa78.inc b/meta/conf/machine/include/arm/armv8-2a/tune-cortexa78.inc
new file mode 100644
index 0000000000..198b94c679
--- /dev/null
+++ b/meta/conf/machine/include/arm/armv8-2a/tune-cortexa78.inc
@@ -0,0 +1,17 @@
+#
+# Tune Settings for Cortex-A78
+#
+DEFAULTTUNE ?= "cortexa78"
+
+TUNEVALID[cortexa78] = "Enable Cortex-A78 specific processor optimizations"
+TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa78', ' -mcpu=cortex-a78', '', d)}"
+
+require conf/machine/include/arm/arch-armv8-2a.inc
+
+# Little Endian base configs
+AVAILTUNES += "cortexa78"
+ARMPKGARCH:tune-cortexa78 = "cortexa78"
+# We do not want -march since -mcpu is added above to cover for it
+TUNE_FEATURES:tune-cortexa78 = "aarch64 crypto cortexa78"
+PACKAGE_EXTRA_ARCHS:tune-cortexa78 = "${PACKAGE_EXTRA_ARCHS:tune-armv8-2a-crypto} cortexa78"
+BASE_LIB:tune-cortexa78 = "lib64"
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 2/4] feature-arm-vfp.inc: Allow hard-float on newer simd targets
2024-02-01 20:45 [PATCH v2 0/4] Updates for ARM tunings Mark Hatle
2024-02-01 20:45 ` [PATCH v2 1/4] tune-cortexa78.inc: Add cortexa78 tune, based on cortexa77 Mark Hatle
@ 2024-02-01 20:45 ` Mark Hatle
2024-02-01 20:45 ` [PATCH v2 3/4] tune-cortexr5: Add hard-float variant Mark Hatle
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Mark Hatle @ 2024-02-01 20:45 UTC (permalink / raw)
To: openembedded-core; +Cc: mark.hatle, raj.khem, jon.mason
From: Mark Hatle <mark.hatle@amd.com>
Currently hard-float is dependency upon the special TUNE_CCARGS_MFPU which
contains custom -mfpu= values. However, newer 32-bit architectures like
cortex-r52 use 'simd' instead. There is no 'simd' entry for -mfpu=
according to the GCC manual, it's more or less automatic based on the
cpu settings.
Add this as an exception to the TUNE_CCARGS_FLOAT setting of hard or softfp.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
---
meta/conf/machine/include/arm/feature-arm-vfp.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/meta/conf/machine/include/arm/feature-arm-vfp.inc b/meta/conf/machine/include/arm/feature-arm-vfp.inc
index 678888e638..d020100daa 100644
--- a/meta/conf/machine/include/arm/feature-arm-vfp.inc
+++ b/meta/conf/machine/include/arm/feature-arm-vfp.inc
@@ -5,11 +5,12 @@
TUNEVALID[vfp] = "Enable Vector Floating Point (vfp) unit."
TUNE_CCARGS_MFPU .= "${@bb.utils.contains('TUNE_FEATURES', 'vfp', ' vfp', '', d)}"
+# simd is special, we don't pass this to the -mfpu, it's implied
TUNE_CCARGS .= "${@ (' -mfpu=%s' % d.getVar('TUNE_CCARGS_MFPU').split()[-1]) if (d.getVar('TUNE_CCARGS_MFPU') != '') else ''}"
# The following deals with both vfpv3-d16 and vfpv4-d16
ARMPKGSFX_FPU = "${@ ('-%s' % d.getVar('TUNE_CCARGS_MFPU').split()[-1].replace('-d16', 'd16')) if (d.getVar('TUNE_CCARGS_MFPU') != '') else ''}"
TUNEVALID[callconvention-hard] = "Enable EABI hard float call convention, requires VFP."
-TUNE_CCARGS_MFLOAT = "${@ bb.utils.contains('TUNE_FEATURES', 'callconvention-hard', 'hard', 'softfp', d) if (d.getVar('TUNE_CCARGS_MFPU') != '') else '' }"
+TUNE_CCARGS_MFLOAT = "${@ bb.utils.contains('TUNE_FEATURES', 'callconvention-hard', 'hard', 'softfp', d) if (d.getVar('TUNE_CCARGS_MFPU') != '' or bb.utils.contains('TUNE_FEATURES', 'simd', True, False, d)) else '' }"
TUNE_CCARGS .= "${@ ' -mfloat-abi=${TUNE_CCARGS_MFLOAT}' if (d.getVar('TUNE_CCARGS_MFLOAT') != '') else ''}"
ARMPKGSFX_EABI = "${@ 'hf' if (d.getVar('TUNE_CCARGS_MFLOAT') == 'hard') else ''}"
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 3/4] tune-cortexr5: Add hard-float variant
2024-02-01 20:45 [PATCH v2 0/4] Updates for ARM tunings Mark Hatle
2024-02-01 20:45 ` [PATCH v2 1/4] tune-cortexa78.inc: Add cortexa78 tune, based on cortexa77 Mark Hatle
2024-02-01 20:45 ` [PATCH v2 2/4] feature-arm-vfp.inc: Allow hard-float on newer simd targets Mark Hatle
@ 2024-02-01 20:45 ` Mark Hatle
2024-02-01 20:45 ` [PATCH v2 4/4] tune-cortexr52: " Mark Hatle
2024-02-01 20:51 ` [PATCH v2 0/4] Updates for ARM tunings Khem Raj
4 siblings, 0 replies; 6+ messages in thread
From: Mark Hatle @ 2024-02-01 20:45 UTC (permalink / raw)
To: openembedded-core; +Cc: mark.hatle, raj.khem, jon.mason
From: Mark Hatle <mark.hatle@amd.com>
Add the ability to specify cortexr5hf to get a version that enables the
hard-float calling convention.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
---
meta/conf/machine/include/arm/armv7r/tune-cortexr5.inc | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/meta/conf/machine/include/arm/armv7r/tune-cortexr5.inc b/meta/conf/machine/include/arm/armv7r/tune-cortexr5.inc
index ecaaa0d846..4c8985292b 100644
--- a/meta/conf/machine/include/arm/armv7r/tune-cortexr5.inc
+++ b/meta/conf/machine/include/arm/armv7r/tune-cortexr5.inc
@@ -12,3 +12,8 @@ AVAILTUNES += "cortexr5"
ARMPKGARCH:tune-cortexr5 = "cortexr5"
TUNE_FEATURES:tune-cortexr5 = "${TUNE_FEATURES:tune-armv7r-vfpv3d16} cortexr5 idiv"
PACKAGE_EXTRA_ARCHS:tune-cortexr5 = "${PACKAGE_EXTRA_ARCHS:tune-armv7r-vfpv3d16} cortexr5-vfpv3d16"
+
+AVAILTUNES += "cortexr5hf"
+ARMPKGARCH:tune-cortexr5hf = "cortexr5"
+TUNE_FEATURES:tune-cortexr5hf = "${TUNE_FEATURES:tune-cortexr5} callconvention-hard"
+PACKAGE_EXTRA_ARCHS:tune-cortexr5hf = "cortexr5hf-vfpv3d16"
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 4/4] tune-cortexr52: Add hard-float variant
2024-02-01 20:45 [PATCH v2 0/4] Updates for ARM tunings Mark Hatle
` (2 preceding siblings ...)
2024-02-01 20:45 ` [PATCH v2 3/4] tune-cortexr5: Add hard-float variant Mark Hatle
@ 2024-02-01 20:45 ` Mark Hatle
2024-02-01 20:51 ` [PATCH v2 0/4] Updates for ARM tunings Khem Raj
4 siblings, 0 replies; 6+ messages in thread
From: Mark Hatle @ 2024-02-01 20:45 UTC (permalink / raw)
To: openembedded-core; +Cc: mark.hatle, raj.khem, jon.mason
From: Mark Hatle <mark.hatle@amd.com>
Add the ability to specify cortexr52hf to get a version that enables the
hard-float calling convention.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
---
meta/conf/machine/include/arm/armv8r/tune-cortexr52.inc | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/meta/conf/machine/include/arm/armv8r/tune-cortexr52.inc b/meta/conf/machine/include/arm/armv8r/tune-cortexr52.inc
index 02507d9b78..89f0e09450 100644
--- a/meta/conf/machine/include/arm/armv8r/tune-cortexr52.inc
+++ b/meta/conf/machine/include/arm/armv8r/tune-cortexr52.inc
@@ -13,3 +13,8 @@ ARMPKGARCH:tune-cortexr52 = "cortexr52"
# We do not want -march since -mcpu is added above to cover for it
TUNE_FEATURES:tune-cortexr52 = "aarch64 crc simd cortexr52"
PACKAGE_EXTRA_ARCHS:tune-cortexr52 = "${PACKAGE_EXTRA_ARCHS:tune-armv8r-crc-simd} cortexr52"
+
+AVAILTUNES += "cortexr52hf"
+ARMPKGARCH:tune-cortexr52hf = "cortexr52"
+TUNE_FEATURES:tune-cortexr52hf = "${TUNE_FEATURES:tune-cortexr52} callconvention-hard"
+PACKAGE_EXTRA_ARCHS:tune-cortexr52hf = "cortexr52hf"
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2 0/4] Updates for ARM tunings
2024-02-01 20:45 [PATCH v2 0/4] Updates for ARM tunings Mark Hatle
` (3 preceding siblings ...)
2024-02-01 20:45 ` [PATCH v2 4/4] tune-cortexr52: " Mark Hatle
@ 2024-02-01 20:51 ` Khem Raj
4 siblings, 0 replies; 6+ messages in thread
From: Khem Raj @ 2024-02-01 20:51 UTC (permalink / raw)
To: Mark Hatle; +Cc: openembedded-core, mark.hatle, jon.mason
this series looks ok to me on top of master-next.
On Thu, Feb 1, 2024 at 12:47 PM Mark Hatle
<mark.hatle@kernel.crashing.org> wrote:
>
> From: Mark Hatle <mark.hatle@amd.com>
>
> cortexa78 missing seems to be an oversight. It (according to wikipedia) is a
> successor to the cortexa77 which already exists. This was created by
> copying the cortexa77 and changing it to be a78. A test system was build to
> verify no obvious issues with the toolchain.
>
> The remaining three changes are related. I've got a need for a cortex-r5 and
> cortex-r52 that enables the hard-float calling convention (this might also
> be useful to others with other cortex-r and maybe even cortex-m processors,
> but I'm not in a position to know this outside of my specific need.)
>
> tune-cortexr5 simply adds an hf variant that adds the callconvention-hard.
> Since there is no armv7r-vfp3d16 w/ this, the package_arch list is more
> limited then the regular r5.
>
> tune-cortexr52 requires the change to feature-arm-vfp to allow the setting
> when 'simd' is enabled (since we don't specify vfp or neon). Otherwise
> this follows the same convention as the r5 change.
>
> v2:
> Rebase cortex-a78 tune based on current master-next branch. THis addresses
> Khem's comment.
>
> Mark Hatle (4):
> tune-cortexa78.inc: Add cortexa78 tune, based on cortexa77
> feature-arm-vfp.inc: Allow hard-float on newer simd targets
> tune-cortexr5: Add hard-float variant
> tune-cortexr52: Add hard-float variant
>
> .../include/arm/armv7r/tune-cortexr5.inc | 5 +++++
> .../include/arm/armv8-2a/tune-cortexa78.inc | 17 +++++++++++++++++
> .../include/arm/armv8r/tune-cortexr52.inc | 5 +++++
> .../machine/include/arm/feature-arm-vfp.inc | 3 ++-
> 4 files changed, 29 insertions(+), 1 deletion(-)
> create mode 100644 meta/conf/machine/include/arm/armv8-2a/tune-cortexa78.inc
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread