[PATCH] musl: Fix riscv64 CAS functions

[PATCH] musl: Fix riscv64 CAS functions

[Khem Raj]

Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
 ...and-specifiers-in-the-riscv64-CAS-ro.patch | 55 +++++++++++++++++++
 meta/recipes-core/musl/musl_git.bb            |  1 +
 2 files changed, 56 insertions(+)
 create mode 100644 meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch

diff --git a/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch b/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch
new file mode 100644
index 0000000000..09b71cb299
--- /dev/null
+++ b/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch
@@ -0,0 +1,55 @@
+From 59f2954fcaacd9426827c69a729e2647cb9977e5 Mon Sep 17 00:00:00 2001
+From: Palmer Dabbelt <palmer@sifive.com>
+Date: Tue, 24 Sep 2019 20:30:15 -0700
+Subject: [PATCH] correct the operand specifiers in the riscv64 CAS routines
+
+The operand sepcifiers in a_cas and a_casp for riscv64 were incorrect:
+there's a backwards branch in the routine, so despite tmp being written
+at the end of the assembly fragment it cannot be allocated in one of the
+input registers because the input values may be needed for another trip
+around the loop.
+
+For code that follows the guarnteed forward progress requirements, he
+backwards branch is rarely taken: SiFive's hardware only fails a store
+conditional on execptional cases (ie, instruction cache misses inside
+the loop), and until recently a bug in QEMU allowed back-to-back
+store conditionals to succeed.  The bug has been fixed in the latest
+QEMU release, but it turns out that the fix caused this latent bug in
+musl to manifest.
+
+Full disclosure: I haven't actually even compiled musl.  I just guessed
+this would fix a bug introducted by the new QEMU behavior, Alistair
+(CC'd) actually checked it fixes the problem.  The rest is just
+conjecture.
+
+Upstream-Status: Submitted
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ arch/riscv64/atomic_arch.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h
+index c9765342..41ad4d04 100644
+--- a/arch/riscv64/atomic_arch.h
++++ b/arch/riscv64/atomic_arch.h
+@@ -14,7 +14,7 @@ static inline int a_cas(volatile int *p, int t, int s)
+ 		"	sc.w.aqrl %1, %4, (%2)\n"
+ 		"	bnez %1, 1b\n"
+ 		"1:"
+-		: "=&r"(old), "=r"(tmp)
++		: "=&r"(old), "=&r"(tmp)
+ 		: "r"(p), "r"(t), "r"(s)
+ 		: "memory");
+ 	return old;
+@@ -31,7 +31,7 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s)
+ 		"	sc.d.aqrl %1, %4, (%2)\n"
+ 		"	bnez %1, 1b\n"
+ 		"1:"
+-		: "=&r"(old), "=r"(tmp)
++		: "=&r"(old), "=&r"(tmp)
+ 		: "r"(p), "r"(t), "r"(s)
+ 		: "memory");
+ 	return old;
+-- 
+2.23.0
+
diff --git a/meta/recipes-core/musl/musl_git.bb b/meta/recipes-core/musl/musl_git.bb
index 87453be07f..335d53d42f 100644
--- a/meta/recipes-core/musl/musl_git.bb
+++ b/meta/recipes-core/musl/musl_git.bb
@@ -15,6 +15,7 @@ PV = "${BASEVER}+git${SRCPV}"
 SRC_URI = "git://git.musl-libc.org/musl \
            file://0001-Make-dynamic-linker-a-relative-symlink-to-libc.patch \
            file://0002-ldso-Use-syslibdir-and-libdir-as-default-pathes-to-l.patch \
+           file://0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch \
           "
 
 S = "${WORKDIR}/git"
-- 
2.23.0

✗ patchtest: failure for musl: Fix riscv64 CAS functions

[Patchwork]

== Series Details ==

Series: musl: Fix riscv64 CAS functions
Revision: 1
URL   : https://patchwork.openembedded.org/series/20146/
State : failure

== Summary ==


Thank you for submitting this patch series to OpenEmbedded Core. This is
an automated response. Several tests have been executed on the proposed
series by patchtest resulting in the following failures:



* Issue             Upstream-Status is Submitted, but it is not mentioned where [test_upstream_status_presence_format] 
  Suggested fix    Include where 0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch was submitted
  Current          Upstream-Status: Submitted
  Standard format  Upstream-Status: Submitted [where]



If you believe any of these test results are incorrect, please reply to the
mailing list (openembedded-core@lists.openembedded.org) raising your concerns.
Otherwise we would appreciate you correcting the issues and submitting a new
version of the patchset if applicable. Please ensure you add/increment the
version number when sending the new version (i.e. [PATCH] -> [PATCH v2] ->
[PATCH v3] -> ...).

---
Guidelines:     https://www.openembedded.org/wiki/Commit_Patch_Message_Guidelines
Test framework: http://git.yoctoproject.org/cgit/cgit.cgi/patchtest
Test suite:     http://git.yoctoproject.org/cgit/cgit.cgi/patchtest-oe