* [OE-core][PATCH RFC v2 01/19] tune-riscv: be explicit about riscv32gc, riscv64gc defaults
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-10-08 15:19 ` Mark Hatle
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 02/19] tune-riscv.inc: add 'riscv64gcv' tune Trevor Gamblin
` (18 subsequent siblings)
19 siblings, 1 reply; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
The string 'riscv64' is a generic descriptor for the 64-bit RISC-V ISA,
and can mean different things under different contexts. In the case of
tune-riscv.inc, it has served as an alias for the 'riscv64gc' profile
which packages are typically built against, resulting in the following
output (from a typical bitbake preamble):
|TUNE_FEATURES = "rv 64 i m a f d c zicsr zifencei"
Modify tune-riscv.inc to avoid overloading the 'riscv64' string in this
way, instead setting DEFAULTTUNE to 'riscv64gc', and changing other
occurrences to match. TUNE_FEATURES remains the same under this
adjustment, but the .inc file is clearer which profile is being
targeted.
Do the same for riscv32 -> riscv32gc. In this case, we also need to
update qemuriscv32.conf, since it sets DEFAULTTUNE to override the
default.
Also add TUNE_FEATURE aliases for the old riscv32 and riscv64 names so
that other layers using them don't break.
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/tune-riscv.inc | 18 ++++++++++++------
meta/conf/machine/qemuriscv32.conf | 2 +-
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index 12c1125c8b..8a14971d5f 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -1,15 +1,21 @@
require conf/machine/include/riscv/arch-riscv.inc
-DEFAULTTUNE ?= "riscv64"
+DEFAULTTUNE ?= "riscv64gc"
-AVAILTUNES += "riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
+AVAILTUNES += "riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
# Default
-TUNE_FEATURES:tune-riscv64 := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
-PACKAGE_EXTRA_ARCHS:tune-riscv64 = "${TUNE_RISCV_PKGARCH}"
+TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
+PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}"
-TUNE_FEATURES:tune-riscv32 := "${@oe.tune.riscv_isa_to_tune("rv32gc")}"
-PACKAGE_EXTRA_ARCHS:tune-riscv32 = "${TUNE_RISCV_PKGARCH}"
+TUNE_FEATURES:tune-riscv32gc := "${@oe.tune.riscv_isa_to_tune("rv32gc")}"
+PACKAGE_EXTRA_ARCHS:tune-riscv32gc = "${TUNE_RISCV_PKGARCH}"
+
+# Compatibility aliases so that layers using old tunes don't break
+TUNE_FEATURES:tune-riscv64 := "${TUNE_FEATURES:tune-riscv64gc}"
+PACKAGE_EXTRA_ARCHS:tune-riscv64 = "${PACKAGE_EXTRA_ARCHS:tune-riscv64gc}"
+TUNE_FEATURES:tune-riscv32 := "${TUNE_FEATURES:tune-riscv32gc}"
+PACKAGE_EXTRA_ARCHS:tune-riscv32 = "${PACKAGE_EXTRA_ARCHS:tune-riscv32gc}"
# No float
TUNE_FEATURES:tune-riscv64nf := "${@oe.tune.riscv_isa_to_tune("rv64imac_zicsr_zifencei")}"
diff --git a/meta/conf/machine/qemuriscv32.conf b/meta/conf/machine/qemuriscv32.conf
index aff36c28a5..5cb9ba5aa9 100644
--- a/meta/conf/machine/qemuriscv32.conf
+++ b/meta/conf/machine/qemuriscv32.conf
@@ -2,7 +2,7 @@
#@NAME: generic riscv32 machine
#@DESCRIPTION: Machine configuration for running a generic riscv32
-DEFAULTTUNE ?= "riscv32"
+DEFAULTTUNE ?= "riscv32gc"
require conf/machine/include/riscv/qemuriscv.inc
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [OE-core][PATCH RFC v2 01/19] tune-riscv: be explicit about riscv32gc, riscv64gc defaults
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 01/19] tune-riscv: be explicit about riscv32gc, riscv64gc defaults Trevor Gamblin
@ 2026-10-08 15:19 ` Mark Hatle
0 siblings, 0 replies; 26+ messages in thread
From: Mark Hatle @ 2026-10-08 15:19 UTC (permalink / raw)
To: Trevor Gamblin, openembedded-core; +Cc: raj.khem
Sorry for the late reply, but I missed this when it came in.
On 9/30/26 11:38 AM, Trevor Gamblin wrote:
> The string 'riscv64' is a generic descriptor for the 64-bit RISC-V ISA,
> and can mean different things under different contexts. In the case of
> tune-riscv.inc, it has served as an alias for the 'riscv64gc' profile
> which packages are typically built against, resulting in the following
> output (from a typical bitbake preamble):
>
> |TUNE_FEATURES = "rv 64 i m a f d c zicsr zifencei"
>
> Modify tune-riscv.inc to avoid overloading the 'riscv64' string in this
> way, instead setting DEFAULTTUNE to 'riscv64gc', and changing other
> occurrences to match. TUNE_FEATURES remains the same under this
> adjustment, but the .inc file is clearer which profile is being
> targeted.
>
> Do the same for riscv32 -> riscv32gc. In this case, we also need to
> update qemuriscv32.conf, since it sets DEFAULTTUNE to override the
> default.
>
> Also add TUNE_FEATURE aliases for the old riscv32 and riscv64 names so
> that other layers using them don't break.
>
> Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
> ---
> meta/conf/machine/include/riscv/tune-riscv.inc | 18 ++++++++++++------
> meta/conf/machine/qemuriscv32.conf | 2 +-
> 2 files changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
> index 12c1125c8b..8a14971d5f 100644
> --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> @@ -1,15 +1,21 @@
> require conf/machine/include/riscv/arch-riscv.inc
>
> -DEFAULTTUNE ?= "riscv64"
> +DEFAULTTUNE ?= "riscv64gc"
>
> -AVAILTUNES += "riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
> +AVAILTUNES += "riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
I am in favor of the above. The original riscv64 was there only for legacy
compatibility, but I never liked it. Being more specific, especially on
_embedded_ riscv systems seems like a good thing to me.
--Mark
> # Default
> -TUNE_FEATURES:tune-riscv64 := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
> -PACKAGE_EXTRA_ARCHS:tune-riscv64 = "${TUNE_RISCV_PKGARCH}"
> +TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
> +PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}"
>
> -TUNE_FEATURES:tune-riscv32 := "${@oe.tune.riscv_isa_to_tune("rv32gc")}"
> -PACKAGE_EXTRA_ARCHS:tune-riscv32 = "${TUNE_RISCV_PKGARCH}"
> +TUNE_FEATURES:tune-riscv32gc := "${@oe.tune.riscv_isa_to_tune("rv32gc")}"
> +PACKAGE_EXTRA_ARCHS:tune-riscv32gc = "${TUNE_RISCV_PKGARCH}"
> +
> +# Compatibility aliases so that layers using old tunes don't break
> +TUNE_FEATURES:tune-riscv64 := "${TUNE_FEATURES:tune-riscv64gc}"
> +PACKAGE_EXTRA_ARCHS:tune-riscv64 = "${PACKAGE_EXTRA_ARCHS:tune-riscv64gc}"
> +TUNE_FEATURES:tune-riscv32 := "${TUNE_FEATURES:tune-riscv32gc}"
> +PACKAGE_EXTRA_ARCHS:tune-riscv32 = "${PACKAGE_EXTRA_ARCHS:tune-riscv32gc}"
>
> # No float
> TUNE_FEATURES:tune-riscv64nf := "${@oe.tune.riscv_isa_to_tune("rv64imac_zicsr_zifencei")}"
> diff --git a/meta/conf/machine/qemuriscv32.conf b/meta/conf/machine/qemuriscv32.conf
> index aff36c28a5..5cb9ba5aa9 100644
> --- a/meta/conf/machine/qemuriscv32.conf
> +++ b/meta/conf/machine/qemuriscv32.conf
> @@ -2,7 +2,7 @@
> #@NAME: generic riscv32 machine
> #@DESCRIPTION: Machine configuration for running a generic riscv32
>
> -DEFAULTTUNE ?= "riscv32"
> +DEFAULTTUNE ?= "riscv32gc"
>
> require conf/machine/include/riscv/qemuriscv.inc
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [OE-core][PATCH RFC v2 02/19] tune-riscv.inc: add 'riscv64gcv' tune
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 01/19] tune-riscv: be explicit about riscv32gc, riscv64gc defaults Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 03/19] arch-riscv.inc: add missing RVA20 extensions Trevor Gamblin
` (17 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Add a new RISC-V tune option which adds the 'v' (vector) extension,
compared to the default.
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/tune-riscv.inc | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index 8a14971d5f..ed71dc06ba 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -2,12 +2,15 @@ require conf/machine/include/riscv/arch-riscv.inc
DEFAULTTUNE ?= "riscv64gc"
-AVAILTUNES += "riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
+AVAILTUNES += "riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
# Default
TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}"
+TUNE_FEATURES:tune-riscv64gcv := "${@oe.tune.riscv_isa_to_tune("rv64gcv")}"
+PACKAGE_EXTRA_ARCHS:tune-riscv64gcv = "${TUNE_RISCV_PKGARCH}"
+
TUNE_FEATURES:tune-riscv32gc := "${@oe.tune.riscv_isa_to_tune("rv32gc")}"
PACKAGE_EXTRA_ARCHS:tune-riscv32gc = "${TUNE_RISCV_PKGARCH}"
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 03/19] arch-riscv.inc: add missing RVA20 extensions
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 01/19] tune-riscv: be explicit about riscv32gc, riscv64gc defaults Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 02/19] tune-riscv.inc: add 'riscv64gcv' tune Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 04/19] meta/lib/oe/tune.py: support profile strings, add rva20u64 Trevor Gamblin
` (16 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
There are currently many RISC-V ISA extensions missing from the
arch-riscv.inc file, even some which are required by core 'riscv64gc'
extensions. For example:
|tgamblin@megalith ~/workspace/ypbuilds/poky-qemuriscv64/layers/openembedded-core (master)$ riscv64-linux-gnu-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -Q --help=target | grep rv64
| -march= rv64imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd
versus:
|TUNE_FEATURES = "rv 64 i m a f d c zicsr zifencei"
which is missing zmmul, zaamo, zalrsc, zca, and zcd. There are even more
absent when comparing against the official RVA20 spec - passing
'-march=rva20u64' to gcc and checking the ISA extension string shows:
|tgamblin@alchemist ~ $ riscv64-linux-gnu-gcc -march=rva20u64 -mabi=lp64d -Q --help=target | grep rv64
| -march= rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd
Add the following extensions to arch-riscv.inc, along with their
conditional inclusions required:
- za128rs
- zaamo (required by 'a')
- zalrsc (required by 'a')
- zca (required by 'c')
- zcd
- ziccamoa
- ziccif
- zicclsm
- ziccrse
- zicntr
- zmmul (required by 'm')
We also need to change the extension ordering in the file, so that they
appear in the same order as the compiler expects.
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/arch-riscv.inc | 46 +++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc
index 6f9b74974d..0f12059159 100644
--- a/meta/conf/machine/include/riscv/arch-riscv.inc
+++ b/meta/conf/machine/include/riscv/arch-riscv.inc
@@ -86,14 +86,58 @@ TUNEVALID[zicbom] = "Cache-block management extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
+TUNEVALID[ziccamoa] = "PMA guarantees for A-extension atomics extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}"
+
+TUNEVALID[ziccif] = "Patching instructions at run time extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", "_ziccif", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", "_ziccif", "", d)}"
+
+TUNEVALID[zicclsm] = "Software that assumes misaligned access works extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", "_zicclsm", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", "_zicclsm", "", d)}"
+
+TUNEVALID[ziccrse] = "Guarantees LR/SC forward progress extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", "_ziccrse", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", "_ziccrse", "", d)}"
+
+TUNEVALID[zicntr] = "Cycle and instruction counting for profiling extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}"
+
TUNEVALID[zicsr] = "Control and status register access extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
-TUNEVALID[zifencei] = "Instruction-fetch fence extension"
+TUNEVALID[zifencei] = "Instruction-fetch fence extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
+TUNEVALID[zmmul] = "Cheaper M subset (mul only) extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}"
+
+TUNEVALID[za128rs] = "Reservation set granularity (128-byte) extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}"
+
+TUNEVALID[zaamo] = "Atomic read-modify-write memory operations extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}"
+
+TUNEVALID[zalrsc] = "Extended LR/SC semantics extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}"
+
+TUNEVALID[zca] = "Compressed base integer ops extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "c zca", "_zca", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", "_zca", "", d)}"
+
+TUNEVALID[zcd] = "16-bit encodings for 64-bit FP extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}"
+
TUNEVALID[zba] = "Address bit manipulation extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 04/19] meta/lib/oe/tune.py: support profile strings, add rva20u64
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (2 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 03/19] arch-riscv.inc: add missing RVA20 extensions Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 05/19] tune-riscv.inc: add rva20u64 to AVAILTUNES Trevor Gamblin
` (15 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/lib/oe/tune.py | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py
index 7fda19430d..fed593e9af 100644
--- a/meta/lib/oe/tune.py
+++ b/meta/lib/oe/tune.py
@@ -4,16 +4,25 @@
# SPDX-License-Identifier: GPL-2.0-only
#
+# RISC-V profile name -> equivalent ISA string. These are determined from compiler output, like:
+# tgamblin@alchemist ~ $ riscv64-linux-gnu-gcc -march=rva20u64 -mabi=lp64d -Q --help=target | grep rv64
+# -march=rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd
+RISCV_PROFILES = {
+ 'rva20u64': 'rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd',
+}
+
# riscv_isa_to_tune(isa)
#
# Automatically translate a RISC-V ISA string to TUNE_FEATURES
#
# Abbreviations, such as rv32g -> rv32imaffd_zicsr_zifencei are supported.
#
-# Profiles, such as rva22u64, are NOT supported, you must use ISA strings.
+# Profiles are supported for the names listed in RISCV_PROFILES. Otherwise, you
+# must use ISA strings.
#
def riscv_isa_to_tune(isa):
_isa = isa.lower()
+ _isa = RISCV_PROFILES.get(_isa, _isa)
feature = []
iter = 0
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 05/19] tune-riscv.inc: add rva20u64 to AVAILTUNES
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (3 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 04/19] meta/lib/oe/tune.py: support profile strings, add rva20u64 Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 06/19] arch-riscv.inc: add rva22u64 extensions Trevor Gamblin
` (14 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
riscv64gc remains the default for now.
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/tune-riscv.inc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index ed71dc06ba..80c17ea0b7 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -2,7 +2,12 @@ require conf/machine/include/riscv/arch-riscv.inc
DEFAULTTUNE ?= "riscv64gc"
-AVAILTUNES += "riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
+AVAILTUNES += "rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
+
+# zifencei isn't part of these profiles per gcc's -march expansion, but the
+# Linux kernel requires it, so add it on top of the profile's extensions.
+TUNE_FEATURES:tune-rva20u64 := "${@oe.tune.riscv_isa_to_tune("rva20u64")} zifencei"
+PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${TUNE_RISCV_PKGARCH}"
# Default
TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 06/19] arch-riscv.inc: add rva22u64 extensions
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (4 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 05/19] tune-riscv.inc: add rva20u64 to AVAILTUNES Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 07/19] meta/lib/oe/tune.py: add rva22u64 profile Trevor Gamblin
` (13 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
gcc reports the following extension string for '-march=rva22u64':
|tgamblin@megalith ~/workspace/ypbuilds/poky-qemuriscv64/layers/openembedded-core (master)$ riscv64-linux-gnu-gcc -march=rva22u64 -mabi=lp64d -Q --help=target | grep rv64
| -march= rv64imafdcb_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zihintpause_zmmul_za64rs_zaamo_zalrsc_zfhmin_zca_zcd_zba_zbb_zbs_zkt
Add the following extensions needed to complete the profile:
- za64rs
- zfhmin
- zic64b
- zicbop
- zicboz
- zihintpause
- zkt
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/arch-riscv.inc | 28 ++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc
index 0f12059159..352d6bd878 100644
--- a/meta/conf/machine/include/riscv/arch-riscv.inc
+++ b/meta/conf/machine/include/riscv/arch-riscv.inc
@@ -82,10 +82,22 @@ TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}"
# Now the special Z extensions
+TUNEVALID[zic64b] = "Cache block size is 64 bytes extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zic64b", "_zic64b", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zic64b", "_zic64b", "", d)}"
+
TUNEVALID[zicbom] = "Cache-block management extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
+TUNEVALID[zicbop] = "Cache-block prefetching extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbop", "_zicbop", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbop", "_zicbop", "", d)}"
+
+TUNEVALID[zicboz] = "Cache-block zeroing extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicboz", "_zicboz", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicboz", "_zicboz", "", d)}"
+
TUNEVALID[ziccamoa] = "PMA guarantees for A-extension atomics extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}"
@@ -114,6 +126,10 @@ TUNEVALID[zifencei] = "Instruction-fetch fence extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
+TUNEVALID[zihintpause] = "Pause hint extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}"
+
TUNEVALID[zmmul] = "Cheaper M subset (mul only) extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}"
@@ -122,6 +138,10 @@ TUNEVALID[za128rs] = "Reservation set granularity (128-byte) extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}"
+TUNEVALID[za64rs] = "Reservation set size of at most 64 bytes extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za64rs", "_za64rs", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za64rs", "_za64rs", "", d)}"
+
TUNEVALID[zaamo] = "Atomic read-modify-write memory operations extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}"
@@ -130,6 +150,10 @@ TUNEVALID[zalrsc] = "Extended LR/SC semantics extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}"
+TUNEVALID[zfhmin] = "Minimal half-precision floating point extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}"
+
TUNEVALID[zca] = "Compressed base integer ops extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "c zca", "_zca", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", "_zca", "", d)}"
@@ -154,6 +178,10 @@ TUNEVALID[zbs] = "Single-bit manipulation extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}"
+TUNEVALID[zkt] = "Data-independent execution latency extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}"
+
# Construct TUNE_CCARGS
# This should result in a CCARG similar to:
# -march=rv32imac -mabi=ilp32
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 07/19] meta/lib/oe/tune.py: add rva22u64 profile
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (5 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 06/19] arch-riscv.inc: add rva22u64 extensions Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 08/19] tune-riscv.inc: add rva22u64 to AVAILTUNES Trevor Gamblin
` (12 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/lib/oe/tune.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py
index fed593e9af..8827d68a23 100644
--- a/meta/lib/oe/tune.py
+++ b/meta/lib/oe/tune.py
@@ -9,6 +9,7 @@
# -march=rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd
RISCV_PROFILES = {
'rva20u64': 'rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd',
+ 'rva22u64': 'rv64imafdcb_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zihintpause_zmmul_za64rs_zaamo_zalrsc_zfhmin_zca_zcd_zba_zbb_zbs_zkt',
}
# riscv_isa_to_tune(isa)
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 08/19] tune-riscv.inc: add rva22u64 to AVAILTUNES
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (6 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 07/19] meta/lib/oe/tune.py: add rva22u64 profile Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 09/19] arch-riscv.inc: add rva23u64 extensions Trevor Gamblin
` (11 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/tune-riscv.inc | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index 80c17ea0b7..e3f3897978 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -2,13 +2,16 @@ require conf/machine/include/riscv/arch-riscv.inc
DEFAULTTUNE ?= "riscv64gc"
-AVAILTUNES += "rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
+AVAILTUNES += "rva22u64 rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
# zifencei isn't part of these profiles per gcc's -march expansion, but the
# Linux kernel requires it, so add it on top of the profile's extensions.
TUNE_FEATURES:tune-rva20u64 := "${@oe.tune.riscv_isa_to_tune("rva20u64")} zifencei"
PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${TUNE_RISCV_PKGARCH}"
+TUNE_FEATURES:tune-rva22u64 := "${@oe.tune.riscv_isa_to_tune("rva22u64")} zifencei"
+PACKAGE_EXTRA_ARCHS:tune-rva22u64 = "${TUNE_RISCV_PKGARCH}"
+
# Default
TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}"
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 09/19] arch-riscv.inc: add rva23u64 extensions
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (7 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 08/19] tune-riscv.inc: add rva22u64 to AVAILTUNES Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 10/19] meta/lib/oe/tune.py: add rva23u64 profile Trevor Gamblin
` (10 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
gcc reports the following extension string for '-march=rva23u64':
|tgamblin@megalith ~/workspace/ypbuilds/poky-qemuriscv64/layers/openembedded-core (master)$ riscv64-linux-gnu-gcc -march=rva23u64 -mabi=lp64d -Q --help=target | grep rv64
| -march= rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_z
Add the following extensions to complete the profile:
- zawrs
- zcb
- zcmop
- zfa
- zicond
- zihintntl
- zihpm
- zimop
- zvbb
- zve32f
- zve32x
- zve64d
- zve64f
- zve64x
- zvfhmin
- zvkb
- zvkt
- zvl32b
- zvl64b
- zvl128b
- supm
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/arch-riscv.inc | 84 ++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc
index 352d6bd878..aa5c430eba 100644
--- a/meta/conf/machine/include/riscv/arch-riscv.inc
+++ b/meta/conf/machine/include/riscv/arch-riscv.inc
@@ -118,6 +118,10 @@ TUNEVALID[zicntr] = "Cycle and instruction counting for profiling extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}"
+TUNEVALID[zicond] = "Conditional zeroing operations extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicond", "_zicond", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicond", "_zicond", "", d)}"
+
TUNEVALID[zicsr] = "Control and status register access extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
@@ -126,10 +130,22 @@ TUNEVALID[zifencei] = "Instruction-fetch fence extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
+TUNEVALID[zihintntl] = "Non-temporal locality hints extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintntl", "_zihintntl", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintntl", "_zihintntl", "", d)}"
+
TUNEVALID[zihintpause] = "Pause hint extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}"
+TUNEVALID[zihpm] = "Hardware performance counters extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihpm", "_zihpm", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihpm", "_zihpm", "", d)}"
+
+TUNEVALID[zimop] = "Hardware performance counters extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zimop", "_zimop", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zimop", "_zimop", "", d)}"
+
TUNEVALID[zmmul] = "Cheaper M subset (mul only) extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}"
@@ -150,6 +166,14 @@ TUNEVALID[zalrsc] = "Extended LR/SC semantics extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}"
+TUNEVALID[zawrs] = "Wait-on-reservation-set instructions extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zawrs", "_zawrs", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zawrs", "_zawrs", "", d)}"
+
+TUNEVALID[zfa] = "Additional floating point instructions extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfa", "_zfa", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfa", "_zfa", "", d)}"
+
TUNEVALID[zfhmin] = "Minimal half-precision floating point extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}"
@@ -158,10 +182,18 @@ TUNEVALID[zca] = "Compressed base integer ops extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "c zca", "_zca", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", "_zca", "", d)}"
+TUNEVALID[zcb] = "Extra compressed integer ops extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcb", "_zcb", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcb", "_zcb", "", d)}"
+
TUNEVALID[zcd] = "16-bit encodings for 64-bit FP extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}"
+TUNEVALID[zcmop] = "Compressed may-be-ops extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcmop", "_zcmop", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcmop", "_zcmop", "", d)}"
+
TUNEVALID[zba] = "Address bit manipulation extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
@@ -182,6 +214,58 @@ TUNEVALID[zkt] = "Data-independent execution latency extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}"
TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}"
+TUNEVALID[zvbb] = "Vector basic bit-manipulation extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvbb", "_zvbb", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvbb", "_zvbb", "", d)}"
+
+TUNEVALID[zve32f] = "Embedded vector computation (32-bit integer, 32-bit FP) extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32f", "_zve32f", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32f", "_zve32f", "", d)}"
+
+TUNEVALID[zve32x] = "Embedded vector computation (32-bit integer) extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32x", "_zve32x", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32x", "_zve32x", "", d)}"
+
+TUNEVALID[zve64d] = "Embedded vector computation (64-bit integer, 64-bit FP) extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64d", "_zve64d", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64d", "_zve64d", "", d)}"
+
+TUNEVALID[zve64f] = "Embedded vector computation (64-bit integer, 32-bit FP) extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64f", "_zve64f", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64f", "_zve64f", "", d)}"
+
+TUNEVALID[zve64x] = "Embedded vector computation (64-bit integer) extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64x", "_zve64x", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64x", "_zve64x", "", d)}"
+
+TUNEVALID[zvfhmin] = "Vector half-precision minimal extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvfhmin", "_zvfhmin", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvfhmin", "_zvfhmin", "", d)}"
+
+TUNEVALID[zvkb] = "Vector cryptography bit-manipulation extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkb", "_zvkb", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkb", "_zvkb", "", d)}"
+
+TUNEVALID[zvkt] = "Vector data independent execution latency extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkt", "_zvkt", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkt", "_zvkt", "", d)}"
+
+TUNEVALID[zvl128b] = "Minimum vector length standard extensions (128-bit)."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl128b", "_zvl128b", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl128b", "_zvl128b", "", d)}"
+
+TUNEVALID[zvl32b] = "Minimum vector length standard extensions (32-bit)."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl32b", "_zvl32b", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl32b", "_zvl32b", "", d)}"
+
+TUNEVALID[zvl64b] = "Minimum vector length standard extensions (64-bit)."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl64b", "_zvl64b", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl64b", "_zvl64b", "", d)}"
+
+TUNEVALID[supm] = "User-mode pointer masking extension."
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "supm", "_supm", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "supm", "_supm", "", d)}"
+
# Construct TUNE_CCARGS
# This should result in a CCARG similar to:
# -march=rv32imac -mabi=ilp32
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 10/19] meta/lib/oe/tune.py: add rva23u64 profile
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (8 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 09/19] arch-riscv.inc: add rva23u64 extensions Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 11/19] tune-riscv.inc: add rva23u64 to AVAILTUNES Trevor Gamblin
` (9 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/lib/oe/tune.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py
index 8827d68a23..7296f39e66 100644
--- a/meta/lib/oe/tune.py
+++ b/meta/lib/oe/tune.py
@@ -10,6 +10,7 @@
RISCV_PROFILES = {
'rva20u64': 'rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd',
'rva22u64': 'rv64imafdcb_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zihintpause_zmmul_za64rs_zaamo_zalrsc_zfhmin_zca_zcd_zba_zbb_zbs_zkt',
+ 'rva23u64': 'rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_zvl128b_zvl32b_zvl64b_supm',
}
# riscv_isa_to_tune(isa)
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 11/19] tune-riscv.inc: add rva23u64 to AVAILTUNES
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (9 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 10/19] meta/lib/oe/tune.py: add rva23u64 profile Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 12/19] meta/lib/oe/tune.py: add riscv_pkgarch() Trevor Gamblin
` (8 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/tune-riscv.inc | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index e3f3897978..500808ef12 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -2,7 +2,7 @@ require conf/machine/include/riscv/arch-riscv.inc
DEFAULTTUNE ?= "riscv64gc"
-AVAILTUNES += "rva22u64 rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
+AVAILTUNES += "rva23u64 rva22u64 rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
# zifencei isn't part of these profiles per gcc's -march expansion, but the
# Linux kernel requires it, so add it on top of the profile's extensions.
@@ -12,6 +12,9 @@ PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${TUNE_RISCV_PKGARCH}"
TUNE_FEATURES:tune-rva22u64 := "${@oe.tune.riscv_isa_to_tune("rva22u64")} zifencei"
PACKAGE_EXTRA_ARCHS:tune-rva22u64 = "${TUNE_RISCV_PKGARCH}"
+TUNE_FEATURES:tune-rva23u64 := "${@oe.tune.riscv_isa_to_tune("rva23u64")} zifencei"
+PACKAGE_EXTRA_ARCHS:tune-rva23u64 = "${TUNE_RISCV_PKGARCH}"
+
# Default
TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}"
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 12/19] meta/lib/oe/tune.py: add riscv_pkgarch()
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (10 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 11/19] tune-riscv.inc: add rva23u64 to AVAILTUNES Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-10-08 15:26 ` Mark Hatle
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 13/19] arch-riscv.inc: rename TUNE_RISCV_PKGARCH -> TUNE_RISCV_PKGARCH_EXACT in assignments Trevor Gamblin
` (7 subsequent siblings)
19 siblings, 1 reply; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Create a new function to help match RISC-V ISA extension combinations
against recognized profile strings (e.g. 'rva22u64'), so that we can use
simpler patterns for naming things like sstate/build paths.
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/lib/oe/tune.py | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py
index 7296f39e66..0d8e4417e7 100644
--- a/meta/lib/oe/tune.py
+++ b/meta/lib/oe/tune.py
@@ -90,3 +90,32 @@ def riscv_isa_to_tune(isa):
# Eliminate duplicates, but preserve the order
feature = list(dict.fromkeys(feature))
return ' '.join(feature)
+
+# riscv_pkgarch(features, exact_pkgarch)
+#
+# Prefer a RISCV_PROFILES name (plus any extensions enabled on top of it) as the
+# package arch fragment, since otherwise the full ISA extension list will exceed
+# what the sstate class can handle. When several profiles match, the one with
+# the most extensions is preferred, as it is the more specific/clearer match.
+# If there's no clear profile matching the extension list, then fall back to
+# exact_pkgarch.
+def riscv_pkgarch(features, exact_pkgarch):
+ if not features:
+ return exact_pkgarch
+
+ current = set(features.split())
+
+ best_match = None
+ best_features = None
+ for name in RISCV_PROFILES:
+ profile_features = set(riscv_isa_to_tune(name).split())
+ if profile_features.issubset(current):
+ if best_features is None or len(profile_features) > len(best_features):
+ best_match = name
+ best_features = profile_features
+
+ if best_match is None:
+ return exact_pkgarch
+
+ extra = sorted(current - best_features)
+ return '_'.join([best_match] + extra)
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [OE-core][PATCH RFC v2 12/19] meta/lib/oe/tune.py: add riscv_pkgarch()
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 12/19] meta/lib/oe/tune.py: add riscv_pkgarch() Trevor Gamblin
@ 2026-10-08 15:26 ` Mark Hatle
0 siblings, 0 replies; 26+ messages in thread
From: Mark Hatle @ 2026-10-08 15:26 UTC (permalink / raw)
To: Trevor Gamblin, openembedded-core; +Cc: raj.khem
On 9/30/26 11:38 AM, Trevor Gamblin wrote:
> Create a new function to help match RISC-V ISA extension combinations
> against recognized profile strings (e.g. 'rva22u64'), so that we can use
> simpler patterns for naming things like sstate/build paths.
>
> Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
> ---
> meta/lib/oe/tune.py | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py
> index 7296f39e66..0d8e4417e7 100644
> --- a/meta/lib/oe/tune.py
> +++ b/meta/lib/oe/tune.py
> @@ -90,3 +90,32 @@ def riscv_isa_to_tune(isa):
> # Eliminate duplicates, but preserve the order
> feature = list(dict.fromkeys(feature))
> return ' '.join(feature)
> +
> +# riscv_pkgarch(features, exact_pkgarch)
> +#
> +# Prefer a RISCV_PROFILES name (plus any extensions enabled on top of it) as the
> +# package arch fragment, since otherwise the full ISA extension list will exceed
> +# what the sstate class can handle. When several profiles match, the one with
> +# the most extensions is preferred, as it is the more specific/clearer match.
> +# If there's no clear profile matching the extension list, then fall back to
> +# exact_pkgarch.
> +def riscv_pkgarch(features, exact_pkgarch):
> + if not features:
> + return exact_pkgarch
> +
> + current = set(features.split())
> +
> + best_match = None
> + best_features = None
> + for name in RISCV_PROFILES:
Where is 'RISCV_PROFILES' defined?
As long as someone is willing to keep this up to date with all of the new
profiles, I don't have a concern with it.
On my AMD platforms, we have dynamic (user defined) ISA for our parts, the users
don't really use 'profiles', but select individual isa components. I would LIKE
(but only because it's easier for me) a way to see the ISA and not have it
converted back to a profile. However, if profiles are the risc-v ISA standard,
I'm fine without a way to disable the translation.
--Mark
> + profile_features = set(riscv_isa_to_tune(name).split())
> + if profile_features.issubset(current):
> + if best_features is None or len(profile_features) > len(best_features):
> + best_match = name
> + best_features = profile_features
> +
> + if best_match is None:
> + return exact_pkgarch
> +
> + extra = sorted(current - best_features)
> + return '_'.join([best_match] + extra)
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [OE-core][PATCH RFC v2 13/19] arch-riscv.inc: rename TUNE_RISCV_PKGARCH -> TUNE_RISCV_PKGARCH_EXACT in assignments
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (11 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 12/19] meta/lib/oe/tune.py: add riscv_pkgarch() Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 14/19] tune.py: add implied tuning logic Trevor Gamblin
` (6 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Change the naming convention we use when determining TUNE_RISCV_PKGARCH,
so that we have the option of relying on a known RISC-V profile name
(e.g. 'rva22u64') as a baseline, rather than always specifying the full
ISA extension set. An example from 'bitbake -e opensbi' with
'DEFAULTTUNE = "rva22u64" in conf/local.conf:
|TUNE_RISCV_PKGARCH="rva22u64"
|# $TUNE_RISCV_PKGARCH_EXACT [48 operations]
|TUNE_RISCV_PKGARCH_EXACT="riscv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zihintpause_zmmul_za64rs_zaamo_zalrsc_zfhmin_zca_zcd_zba_zbb_zbs_zkt"
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/arch-riscv.inc | 118 +++++++++++++------------
1 file changed, 62 insertions(+), 56 deletions(-)
diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc
index aa5c430eba..c1ccf6bda3 100644
--- a/meta/conf/machine/include/riscv/arch-riscv.inc
+++ b/meta/conf/machine/include/riscv/arch-riscv.inc
@@ -32,7 +32,7 @@ TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "64", "lp64", "", d)}"
# The package arch starts with the canonical arch, but adds some extensions to make
# package compatibility clear
-TUNE_RISCV_PKGARCH = "${TUNE_RISCV_ARCH}"
+TUNE_RISCV_PKGARCH_EXACT = "${TUNE_RISCV_ARCH}"
# i, e, or g are defined by gcc, but 'g' refers to 'i' + extensions 'MAFD Zicsr Zifencei'
# So 'g' will not be defined here as it is an abbreviation of the expanded version
@@ -40,231 +40,237 @@ TUNEVALID[e] = "Reduced register base integer extension"
TUNECONFLICTS[e] = "i"
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}"
TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}"
TUNEVALID[i] = "Base integer extension"
TUNECONFLICTS[i] = "e"
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}"
# Extensions
TUNEVALID[m] = "Integer multiplication and division extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}"
TUNEVALID[a] = "Atomic extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}"
TUNEVALID[f] = "Single-precision floating-point extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}"
TUNEVALID[d] = "Double-precision floating-point extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}"
# Only f OR d, but just one
TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", bb.utils.contains("TUNE_FEATURES", "f", "f", "", d), d)}"
TUNEVALID[c] = "Compressed extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}"
TUNEVALID[b] = "Bit Manipulation extension"
# Handled below via zba, zbb, zbs
# This matches current Linux kernel behavior
#TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}"
-#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}"
+#TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}"
TUNEVALID[v] = "Vector operations extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}"
# Now the special Z extensions
TUNEVALID[zic64b] = "Cache block size is 64 bytes extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zic64b", "_zic64b", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zic64b", "_zic64b", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zic64b", "_zic64b", "", d)}"
TUNEVALID[zicbom] = "Cache-block management extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
TUNEVALID[zicbop] = "Cache-block prefetching extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbop", "_zicbop", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbop", "_zicbop", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbop", "_zicbop", "", d)}"
TUNEVALID[zicboz] = "Cache-block zeroing extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicboz", "_zicboz", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicboz", "_zicboz", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicboz", "_zicboz", "", d)}"
TUNEVALID[ziccamoa] = "PMA guarantees for A-extension atomics extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}"
TUNEVALID[ziccif] = "Patching instructions at run time extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", "_ziccif", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", "_ziccif", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", "_ziccif", "", d)}"
TUNEVALID[zicclsm] = "Software that assumes misaligned access works extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", "_zicclsm", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", "_zicclsm", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", "_zicclsm", "", d)}"
TUNEVALID[ziccrse] = "Guarantees LR/SC forward progress extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", "_ziccrse", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", "_ziccrse", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", "_ziccrse", "", d)}"
TUNEVALID[zicntr] = "Cycle and instruction counting for profiling extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}"
TUNEVALID[zicond] = "Conditional zeroing operations extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicond", "_zicond", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicond", "_zicond", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zicond", "_zicond", "", d)}"
TUNEVALID[zicsr] = "Control and status register access extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
TUNEVALID[zifencei] = "Instruction-fetch fence extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
TUNEVALID[zihintntl] = "Non-temporal locality hints extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintntl", "_zihintntl", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintntl", "_zihintntl", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zihintntl", "_zihintntl", "", d)}"
TUNEVALID[zihintpause] = "Pause hint extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}"
TUNEVALID[zihpm] = "Hardware performance counters extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihpm", "_zihpm", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihpm", "_zihpm", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zihpm", "_zihpm", "", d)}"
TUNEVALID[zimop] = "Hardware performance counters extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zimop", "_zimop", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zimop", "_zimop", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zimop", "_zimop", "", d)}"
TUNEVALID[zmmul] = "Cheaper M subset (mul only) extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}"
TUNEVALID[za128rs] = "Reservation set granularity (128-byte) extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}"
TUNEVALID[za64rs] = "Reservation set size of at most 64 bytes extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za64rs", "_za64rs", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za64rs", "_za64rs", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "za64rs", "_za64rs", "", d)}"
TUNEVALID[zaamo] = "Atomic read-modify-write memory operations extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}"
TUNEVALID[zalrsc] = "Extended LR/SC semantics extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}"
TUNEVALID[zawrs] = "Wait-on-reservation-set instructions extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zawrs", "_zawrs", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zawrs", "_zawrs", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zawrs", "_zawrs", "", d)}"
TUNEVALID[zfa] = "Additional floating point instructions extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfa", "_zfa", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfa", "_zfa", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zfa", "_zfa", "", d)}"
TUNEVALID[zfhmin] = "Minimal half-precision floating point extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}"
TUNEVALID[zca] = "Compressed base integer ops extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "c zca", "_zca", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", "_zca", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", "_zca", "", d)}"
TUNEVALID[zcb] = "Extra compressed integer ops extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcb", "_zcb", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcb", "_zcb", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zcb", "_zcb", "", d)}"
TUNEVALID[zcd] = "16-bit encodings for 64-bit FP extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}"
TUNEVALID[zcmop] = "Compressed may-be-ops extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcmop", "_zcmop", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcmop", "_zcmop", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zcmop", "_zcmop", "", d)}"
TUNEVALID[zba] = "Address bit manipulation extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
TUNEVALID[zbb] = "Basic bit manipulation extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}"
TUNEVALID[zbc] = "Carry-less multiplication extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}"
TUNEVALID[zbs] = "Single-bit manipulation extension"
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}"
TUNEVALID[zkt] = "Data-independent execution latency extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}"
TUNEVALID[zvbb] = "Vector basic bit-manipulation extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvbb", "_zvbb", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvbb", "_zvbb", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvbb", "_zvbb", "", d)}"
TUNEVALID[zve32f] = "Embedded vector computation (32-bit integer, 32-bit FP) extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32f", "_zve32f", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32f", "_zve32f", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32f", "_zve32f", "", d)}"
TUNEVALID[zve32x] = "Embedded vector computation (32-bit integer) extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32x", "_zve32x", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32x", "_zve32x", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32x", "_zve32x", "", d)}"
TUNEVALID[zve64d] = "Embedded vector computation (64-bit integer, 64-bit FP) extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64d", "_zve64d", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64d", "_zve64d", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64d", "_zve64d", "", d)}"
TUNEVALID[zve64f] = "Embedded vector computation (64-bit integer, 32-bit FP) extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64f", "_zve64f", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64f", "_zve64f", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64f", "_zve64f", "", d)}"
TUNEVALID[zve64x] = "Embedded vector computation (64-bit integer) extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64x", "_zve64x", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64x", "_zve64x", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64x", "_zve64x", "", d)}"
TUNEVALID[zvfhmin] = "Vector half-precision minimal extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvfhmin", "_zvfhmin", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvfhmin", "_zvfhmin", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvfhmin", "_zvfhmin", "", d)}"
TUNEVALID[zvkb] = "Vector cryptography bit-manipulation extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkb", "_zvkb", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkb", "_zvkb", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkb", "_zvkb", "", d)}"
TUNEVALID[zvkt] = "Vector data independent execution latency extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkt", "_zvkt", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkt", "_zvkt", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkt", "_zvkt", "", d)}"
TUNEVALID[zvl128b] = "Minimum vector length standard extensions (128-bit)."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl128b", "_zvl128b", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl128b", "_zvl128b", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl128b", "_zvl128b", "", d)}"
TUNEVALID[zvl32b] = "Minimum vector length standard extensions (32-bit)."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl32b", "_zvl32b", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl32b", "_zvl32b", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl32b", "_zvl32b", "", d)}"
TUNEVALID[zvl64b] = "Minimum vector length standard extensions (64-bit)."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl64b", "_zvl64b", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl64b", "_zvl64b", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl64b", "_zvl64b", "", d)}"
TUNEVALID[supm] = "User-mode pointer masking extension."
TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "supm", "_supm", "", d)}"
-TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "supm", "_supm", "", d)}"
+TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "supm", "_supm", "", d)}"
+
+# Prefer a known RVA profile name (e.g. "rva22u64"), plus any extensions on
+# top of the profile (e.g. "rva22u64_zvbb"), over the fully expanded exact
+# extension list, when TUNE_FEATURES clearly matches a profile. Falls back
+# to TUNE_RISCV_PKGARCH_EXACT for combinations that don't match a profile.
+TUNE_RISCV_PKGARCH = "${@oe.tune.riscv_pkgarch(d.getVar('TUNE_FEATURES'), d.getVar('TUNE_RISCV_PKGARCH_EXACT'))}"
# Construct TUNE_CCARGS
# This should result in a CCARG similar to:
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 14/19] tune.py: add implied tuning logic
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (12 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 13/19] arch-riscv.inc: rename TUNE_RISCV_PKGARCH -> TUNE_RISCV_PKGARCH_EXACT in assignments Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 15/19] tune.py: add vector extensions to RISCV_IMPLIED Trevor Gamblin
` (5 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Add a new function, riscv_implied() and corresponding tuning lists to
help with shortening PKGARCH-related variables. There's no need to
specify every extension when some (e.g. 'm' implying 'zmmul') are
automatic.
AI-Generated: Uses Claude Opus 5.5
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/lib/oe/tune.py | 59 ++++++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 54 insertions(+), 5 deletions(-)
diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py
index 0d8e4417e7..1ff4b32e74 100644
--- a/meta/lib/oe/tune.py
+++ b/meta/lib/oe/tune.py
@@ -4,15 +4,42 @@
# SPDX-License-Identifier: GPL-2.0-only
#
-# RISC-V profile name -> equivalent ISA string. These are determined from compiler output, like:
-# tgamblin@alchemist ~ $ riscv64-linux-gnu-gcc -march=rva20u64 -mabi=lp64d -Q --help=target | grep rv64
-# -march=rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd
+# RISC-V profile name -> equivalent ISA string, i.e. the mandatory extensions of
+# each profile as ratified in the RISC-V Profiles specification
+# (https://github.com/riscv/riscv-profiles):
+# RVA20U64, RVA22U64: RVA20/RVA22 Profiles, version 1.0
+# RVA23U64: RVA23 Profiles, version 1.0
+# plus the extensions those imply (e.g. zmmul, zaamo, zca, zve*).
+#
+# The profile names are used as package architectures, so each entry here is an
+# ABI claim: packages built for "rva22u64" must keep meaning exactly this
+# extension set. Do not regenerate these from compiler output (e.g. gcc's
+# -march expansion); a newer compiler, or clang, may expand a profile
+# differently. Changing an entry changes what existing package feeds mean.
RISCV_PROFILES = {
'rva20u64': 'rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd',
'rva22u64': 'rv64imafdcb_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zihintpause_zmmul_za64rs_zaamo_zalrsc_zfhmin_zca_zcd_zba_zbb_zbs_zkt',
'rva23u64': 'rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_zvl128b_zvl32b_zvl64b_supm',
}
+# Extensions implied by another enabled extension (per GCC's
+# riscv_implied_info). zicsr (implied by f) is left out for backwards
+# compatibility, i.e. so the package archs of the existing non-profile tunes
+# (e.g. riscv64imafdc_zicsr_zifencei) stay the same.
+RISCV_IMPLIED = {
+ 'm': ['zmmul'],
+ 'a': ['zaamo', 'zalrsc'],
+ 'c': ['zca'],
+ 'b': ['zba', 'zbb', 'zbs'],
+ 'v': ['zve32f', 'zve32x', 'zve64d', 'zve64f', 'zve64x', 'zvl32b', 'zvl64b', 'zvl128b'],
+ 'zcb': ['zca'],
+ 'zcd': ['zca'],
+ 'zcmop': ['zca'],
+ 'zvbb': ['zvkb'],
+ # a reservation set of at most 64 bytes is also at most 128 bytes
+ 'za64rs': ['za128rs'],
+}
+
# riscv_isa_to_tune(isa)
#
# Automatically translate a RISC-V ISA string to TUNE_FEATURES
@@ -91,6 +118,15 @@ def riscv_isa_to_tune(isa):
feature = list(dict.fromkeys(feature))
return ' '.join(feature)
+# riscv_implied(enabled)
+#
+# Return the set of extensions implied by those in enabled.
+def riscv_implied(enabled):
+ implied = {i for e in enabled for i in RISCV_IMPLIED.get(e, [])}
+ if 'c' in enabled and 'd' in enabled:
+ implied |= {'zcd', 'zca'}
+ return implied
+
# riscv_pkgarch(features, exact_pkgarch)
#
# Prefer a RISCV_PROFILES name (plus any extensions enabled on top of it) as the
@@ -98,12 +134,25 @@ def riscv_isa_to_tune(isa):
# what the sstate class can handle. When several profiles match, the one with
# the most extensions is preferred, as it is the more specific/clearer match.
# If there's no clear profile matching the extension list, then fall back to
-# exact_pkgarch.
+# exact_pkgarch. Either way, extensions implied by others are left out.
def riscv_pkgarch(features, exact_pkgarch):
if not features:
return exact_pkgarch
current = set(features.split())
+ # Match profiles whether or not implied extensions (or the b shorthand)
+ # were listed
+ if {'zba', 'zbb', 'zbs'} <= current:
+ current.add('b')
+ implied = riscv_implied(current)
+ current |= implied
+
+ # Drop implied extensions from the exact form too, keeping its base
+ # (e.g. riscv64imafdc) and canonical ordering. Only drop what the string
+ # itself implies, as b is never written out there.
+ base, *exts = exact_pkgarch.split('_')
+ exact_implied = riscv_implied(set(base[len('riscv64'):]) | set(exts))
+ exact_pkgarch = '_'.join([base] + [e for e in exts if e not in exact_implied])
best_match = None
best_features = None
@@ -117,5 +166,5 @@ def riscv_pkgarch(features, exact_pkgarch):
if best_match is None:
return exact_pkgarch
- extra = sorted(current - best_features)
+ extra = sorted(current - best_features - implied)
return '_'.join([best_match] + extra)
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 15/19] tune.py: add vector extensions to RISCV_IMPLIED
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (13 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 14/19] tune.py: add implied tuning logic Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 16/19] tune-riscv.inc: add RISCV_PKGARCH vars, set PACKAGE_EXTRA_ARCHS Trevor Gamblin
` (4 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
AI-Generated: Uses Claude Opus 5.5
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/lib/oe/tune.py | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py
index 1ff4b32e74..2ab3428da7 100644
--- a/meta/lib/oe/tune.py
+++ b/meta/lib/oe/tune.py
@@ -36,6 +36,17 @@ RISCV_IMPLIED = {
'zcd': ['zca'],
'zcmop': ['zca'],
'zvbb': ['zvkb'],
+ # The vector subsets nest, for tunes with some of them but not v. Each
+ # entry lists everything it implies, since riscv_implied() only does one
+ # level of lookup.
+ 'zve64d': ['zve32f', 'zve32x', 'zve64f', 'zve64x', 'zvl32b', 'zvl64b'],
+ 'zve64f': ['zve32f', 'zve32x', 'zve64x', 'zvl32b', 'zvl64b'],
+ 'zve64x': ['zve32x', 'zvl32b', 'zvl64b'],
+ 'zve32f': ['zve32x', 'zvl32b'],
+ 'zve32x': ['zvl32b'],
+ 'zvfhmin': ['zve32f', 'zve32x', 'zvl32b'],
+ 'zvl128b': ['zvl32b', 'zvl64b'],
+ 'zvl64b': ['zvl32b'],
# a reservation set of at most 64 bytes is also at most 128 bytes
'za64rs': ['za128rs'],
}
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 16/19] tune-riscv.inc: add RISCV_PKGARCH vars, set PACKAGE_EXTRA_ARCHS
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (14 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 15/19] tune.py: add vector extensions to RISCV_IMPLIED Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 17/19] tune-riscv.inc: clarify zifencei comment Trevor Gamblin
` (3 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Add the RISCV_PKGARCH variables to help with indicating which tuning
profiles are valid for use on configurations which are supersets of
them, e.g. 'riscv64gc' packages are valid also for the 'rva20u64'
profile.
AI-Generated: Uses Claude Opus 5.5
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/tune-riscv.inc | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index 500808ef12..b31d903172 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -4,23 +4,33 @@ DEFAULTTUNE ?= "riscv64gc"
AVAILTUNES += "rva23u64 rva22u64 rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
-# zifencei isn't part of these profiles per gcc's -march expansion, but the
+# Each profile is a superset of the previous one and of riscv64gc (with the same
+# lp64d ABI), so list those as compatible package archs, with lowest priority
+# first. TUNE_RISCV_PKGARCH only expands to the currently selected tune's name.
+RISCV_PKGARCH_GC = "riscv64imafdc_zicsr_zifencei"
+RISCV_PKGARCH_RVA20 = "rva20u64_zifencei"
+RISCV_PKGARCH_RVA22 = "rva22u64_zifencei"
+
+# riscv64gcv is unique in that rva20 and rva22 are not strict supersets of it
+# (they lack the 'v' extension) but rva23 is, so split it out for comprehension.
+RISCV_PKGARCH_GCV = "riscv64imafdcv_zicsr_zifencei"
+
# Linux kernel requires it, so add it on top of the profile's extensions.
TUNE_FEATURES:tune-rva20u64 := "${@oe.tune.riscv_isa_to_tune("rva20u64")} zifencei"
-PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${TUNE_RISCV_PKGARCH}"
+PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${RISCV_PKGARCH_GC} ${TUNE_RISCV_PKGARCH}"
TUNE_FEATURES:tune-rva22u64 := "${@oe.tune.riscv_isa_to_tune("rva22u64")} zifencei"
-PACKAGE_EXTRA_ARCHS:tune-rva22u64 = "${TUNE_RISCV_PKGARCH}"
+PACKAGE_EXTRA_ARCHS:tune-rva22u64 = "${RISCV_PKGARCH_GC} ${RISCV_PKGARCH_RVA20} ${TUNE_RISCV_PKGARCH}"
TUNE_FEATURES:tune-rva23u64 := "${@oe.tune.riscv_isa_to_tune("rva23u64")} zifencei"
-PACKAGE_EXTRA_ARCHS:tune-rva23u64 = "${TUNE_RISCV_PKGARCH}"
+PACKAGE_EXTRA_ARCHS:tune-rva23u64 = "${RISCV_PKGARCH_GC} ${RISCV_PKGARCH_GCV} ${RISCV_PKGARCH_RVA20} ${RISCV_PKGARCH_RVA22} ${TUNE_RISCV_PKGARCH}"
# Default
TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}"
TUNE_FEATURES:tune-riscv64gcv := "${@oe.tune.riscv_isa_to_tune("rv64gcv")}"
-PACKAGE_EXTRA_ARCHS:tune-riscv64gcv = "${TUNE_RISCV_PKGARCH}"
+PACKAGE_EXTRA_ARCHS:tune-riscv64gcv = "${RISCV_PKGARCH_GC} ${TUNE_RISCV_PKGARCH}"
TUNE_FEATURES:tune-riscv32gc := "${@oe.tune.riscv_isa_to_tune("rv32gc")}"
PACKAGE_EXTRA_ARCHS:tune-riscv32gc = "${TUNE_RISCV_PKGARCH}"
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 17/19] tune-riscv.inc: clarify zifencei comment
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (15 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 16/19] tune-riscv.inc: add RISCV_PKGARCH vars, set PACKAGE_EXTRA_ARCHS Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 18/19] selftest: oelib: add tune.py Trevor Gamblin
` (2 subsequent siblings)
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/conf/machine/include/riscv/tune-riscv.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index b31d903172..76c7dad713 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -15,7 +15,8 @@ RISCV_PKGARCH_RVA22 = "rva22u64_zifencei"
# (they lack the 'v' extension) but rva23 is, so split it out for comprehension.
RISCV_PKGARCH_GCV = "riscv64imafdcv_zicsr_zifencei"
-# Linux kernel requires it, so add it on top of the profile's extensions.
+# zifencei isn't a mandatory extension in these profiles, but the Linux
+# kernel requires it, so add it on top of the profile's extensions.
TUNE_FEATURES:tune-rva20u64 := "${@oe.tune.riscv_isa_to_tune("rva20u64")} zifencei"
PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${RISCV_PKGARCH_GC} ${TUNE_RISCV_PKGARCH}"
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 18/19] selftest: oelib: add tune.py
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (16 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 17/19] tune-riscv.inc: clarify zifencei comment Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 19/19] selftest: cases: add riscvtune.py Trevor Gamblin
2026-10-01 9:13 ` [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Paul Barker
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Add a basic suite for meta/lib/oe/tune.py to test:
- riscv_isa_to_tune() logic/expansion/parsing
- riscv_implied() rules handling
- Profile compatibility/nesting (e.g. rva22 is a superset of rva20)
- riscv_pkgarch() profile naming/matching, including zifencei
- Include testing of vector subsets when 'v' isn't specified, since
these are technically valid
AI-Generated: Uses Claude Opus 5.5
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/lib/oeqa/selftest/cases/oelib/tune.py | 88 ++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/meta/lib/oeqa/selftest/cases/oelib/tune.py b/meta/lib/oeqa/selftest/cases/oelib/tune.py
new file mode 100644
index 0000000000..ff9b895fce
--- /dev/null
+++ b/meta/lib/oeqa/selftest/cases/oelib/tune.py
@@ -0,0 +1,88 @@
+#
+# Copyright OpenEmbedded Contributors
+#
+# SPDX-License-Identifier: MIT
+#
+
+from unittest.case import TestCase
+from oe.tune import RISCV_PROFILES, riscv_isa_to_tune, riscv_implied, riscv_pkgarch
+
+def features(isa):
+ return set(riscv_isa_to_tune(isa).split())
+
+class TestRiscvIsaToTune(TestCase):
+ def test_abbreviation(self):
+ self.assertEqual(riscv_isa_to_tune('rv64gc'), 'rv 64 i m a f d c zicsr zifencei')
+ self.assertEqual(riscv_isa_to_tune('rv32gcv'), 'rv 32 i m a f d c v zicsr zifencei')
+
+ def test_explicit(self):
+ self.assertEqual(riscv_isa_to_tune('rv32imac_zicsr_zifencei'), 'rv 32 i m a c zicsr zifencei')
+ self.assertEqual(riscv_isa_to_tune('RV64IMAFD_Zicsr'), 'rv 64 i m a f d zicsr')
+
+ def test_profile(self):
+ for name, isa in RISCV_PROFILES.items():
+ self.assertEqual(riscv_isa_to_tune(name), riscv_isa_to_tune(isa))
+
+ def test_not_riscv(self):
+ self.assertEqual(riscv_isa_to_tune('x86_64'), 'x86_64')
+
+class TestRiscvImplied(TestCase):
+ def test_implied(self):
+ self.assertEqual(riscv_implied({'m'}), {'zmmul'})
+ self.assertEqual(riscv_implied({'c', 'd'}), {'zca', 'zcd'})
+ self.assertEqual(riscv_implied({'za64rs'}), {'za128rs'})
+ self.assertIn('zve64d', riscv_implied({'v'}))
+ # vector subsets, without v
+ self.assertEqual(riscv_implied({'zve64d', 'zvl128b'}),
+ {'zve32f', 'zve32x', 'zve64f', 'zve64x', 'zvl32b', 'zvl64b'})
+
+ def test_zicsr_kept(self):
+ # Dropping zicsr would rename the existing non-profile package archs
+ self.assertNotIn('zicsr', riscv_implied({'f', 'd'}))
+
+ def test_profiles_nest(self):
+ # Later profiles are supersets of earlier ones, which tune-riscv.inc
+ # relies on for PACKAGE_EXTRA_ARCHS
+ names = ['rva20u64', 'rva22u64', 'rva23u64']
+ for lower, higher in zip(names, names[1:]):
+ h = features(higher)
+ self.assertLessEqual(features(lower), h | riscv_implied(h), '%s is not a subset of %s' % (lower, higher))
+
+class TestRiscvPkgarch(TestCase):
+ def test_no_features(self):
+ self.assertEqual(riscv_pkgarch('', 'riscv64imafdc'), 'riscv64imafdc')
+
+ def test_profiles(self):
+ for name in RISCV_PROFILES:
+ self.assertEqual(riscv_pkgarch(riscv_isa_to_tune(name), 'unused'), name)
+ self.assertEqual(riscv_pkgarch(riscv_isa_to_tune(name) + ' zifencei', 'unused'), name + '_zifencei')
+
+ def test_existing_names_unchanged(self):
+ self.assertEqual(riscv_pkgarch(riscv_isa_to_tune('rv64gc'), 'riscv64imafdc_zicsr_zifencei'),
+ 'riscv64imafdc_zicsr_zifencei')
+ self.assertEqual(riscv_pkgarch(riscv_isa_to_tune('rv32imac_zicsr_zifencei'), 'riscv32imac_zicsr_zifencei'),
+ 'riscv32imac_zicsr_zifencei')
+
+ def test_most_specific_profile(self):
+ # rva23u64 without supm isn't rva23u64, but still contains all of rva22u64
+ f = riscv_isa_to_tune('rva23u64').replace(' supm', '')
+ pkgarch = riscv_pkgarch(f, 'unused')
+ self.assertTrue(pkgarch.startswith('rva22u64_v_'), pkgarch)
+ # implied by v, so left out
+ self.assertNotIn('zve', pkgarch)
+
+ def test_implied_not_listed(self):
+ # b is implied by zba/zbb/zbs, so leaving it out still matches the profile
+ f = riscv_isa_to_tune('rva22u64').replace(' b ', ' ')
+ self.assertEqual(riscv_pkgarch(f, 'unused'), 'rva22u64')
+
+ def test_exact_drops_implied(self):
+ f = riscv_isa_to_tune('rv32imafdcv_zmmul_zaamo_zalrsc_zca_zcd_zve32x_zvl32b_zicsr_zifencei')
+ exact = 'riscv32imafdcv_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zve32x_zvl32b'
+ self.assertEqual(riscv_pkgarch(f, exact), 'riscv32imafdcv_zicsr_zifencei')
+
+ def test_exact_keeps_bitmanip(self):
+ # b is never written out in the exact pkgarch, so zba/zbb/zbs must stay
+ f = riscv_isa_to_tune('rv64gc_zba_zbb_zbs')
+ exact = 'riscv64imafdc_zicsr_zifencei_zba_zbb_zbs'
+ self.assertEqual(riscv_pkgarch(f, exact), exact)
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* [OE-core][PATCH RFC v2 19/19] selftest: cases: add riscvtune.py
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (17 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 18/19] selftest: oelib: add tune.py Trevor Gamblin
@ 2026-09-30 16:38 ` Trevor Gamblin
2026-10-01 9:13 ` [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Paul Barker
19 siblings, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-09-30 16:38 UTC (permalink / raw)
To: openembedded-core; +Cc: raj.khem, mark.hatle, Trevor Gamblin
Add a test suite to ensure that all RISC-V tunes (default or 'unusual')
yield valid pkgarch combinations and that PACKAGES_EXTRA_ARCHS lists
only compatible tunings.
AI-Generated: Uses Claude Opus 5.5
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
meta/lib/oeqa/selftest/cases/riscvtune.py | 96 +++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/meta/lib/oeqa/selftest/cases/riscvtune.py b/meta/lib/oeqa/selftest/cases/riscvtune.py
new file mode 100644
index 0000000000..2716b5bd02
--- /dev/null
+++ b/meta/lib/oeqa/selftest/cases/riscvtune.py
@@ -0,0 +1,96 @@
+#
+# Copyright OpenEmbedded Contributors
+#
+# SPDX-License-Identifier: MIT
+#
+
+from oe.tune import riscv_implied, riscv_isa_to_tune
+from oeqa.selftest.case import OESelftestTestCase
+from oeqa.utils.commands import bitbake, get_bb_var, get_bb_vars
+
+class RiscvTuneTests(OESelftestTestCase):
+ @classmethod
+ def setUpClass(cls):
+ super().setUpClass()
+ cls.orig_machine = get_bb_var('MACHINE')
+
+ def machine_config(self, machine):
+ # Builds set up by bitbake-setup select the machine with a builtin
+ # fragment, which is fatal alongside a MACHINE assignment, so drop it
+ return 'OE_FRAGMENTS:remove = "machine/%s"\nMACHINE = "%s"\n' % (self.orig_machine, machine)
+
+ def test_riscv_default_tunes(self):
+ """
+ Parse every RISC-V tune and check it yields a usable package arch, and
+ that PACKAGE_EXTRA_ARCHS only lists archs of other tunes whose
+ extensions are all available in this one.
+ """
+ self.write_config(self.machine_config('qemuriscv64'))
+ tunes = get_bb_var('AVAILTUNES').split()
+
+ vars = {}
+ for tune in tunes:
+ machine = 'qemuriscv32' if 'riscv32' in tune else 'qemuriscv64'
+ self.write_config(self.machine_config(machine) + 'DEFAULTTUNE = "%s"\n' % tune)
+ vars[tune] = get_bb_vars(['TUNE_FEATURES', 'TUNE_PKGARCH', 'PACKAGE_EXTRA_ARCHS', 'PACKAGE_ARCHS'])
+
+ pkgarch_features = {v['TUNE_PKGARCH']: set(v['TUNE_FEATURES'].split()) for v in vars.values()}
+
+ for tune, v in vars.items():
+ with self.subTest(tune=tune):
+ self.assertTrue(v['TUNE_FEATURES'], 'empty TUNE_FEATURES')
+ self.assertTrue(v['TUNE_PKGARCH'], 'empty TUNE_PKGARCH')
+ self.assertIn(v['TUNE_PKGARCH'], v['PACKAGE_ARCHS'].split())
+ # sstate/package names get unwieldy past this
+ self.assertLessEqual(len(v['TUNE_PKGARCH']), 64, v['TUNE_PKGARCH'])
+
+ features = set(v['TUNE_FEATURES'].split())
+ features |= riscv_implied(features)
+ for arch in v['PACKAGE_EXTRA_ARCHS'].split():
+ self.assertIn(arch, pkgarch_features, '%s is not the package arch of any tune' % arch)
+ self.assertLessEqual(pkgarch_features[arch], features, '%s needs extensions %s lacks' % (arch, tune))
+
+ # Profile tunes are named after the profile
+ for profile in ['rva20u64', 'rva22u64', 'rva23u64']:
+ self.assertEqual(vars[profile]['TUNE_PKGARCH'], profile + '_zifencei')
+
+ # Legacy tune names behave exactly like the tunes they alias
+ for alias, target in [('riscv64', 'riscv64gc'), ('riscv32', 'riscv32gc')]:
+ with self.subTest(alias=alias):
+ self.assertIn(alias, tunes)
+ self.assertEqual(vars[alias], vars[target])
+
+ def test_riscv_unusual_tunes(self):
+ """
+ Define custom tunes with unusual extension combinations, as a BSP
+ might, and check each one builds: the sanity checks accept the
+ package arch, gcc and binutils accept the -march string, and the
+ package arch fits in the sstate object names.
+ """
+ def profile(name, drop=None):
+ return ' '.join(f for f in riscv_isa_to_tune(name).split() if f != drop) + ' zifencei'
+ tunes = {
+ # no float (lp64 ABI), with bitmanip
+ 'rv64-nofloat-bitmanip': riscv_isa_to_tune('rv64imac_zicsr_zifencei_zba_zbb_zbs'),
+ # no profile, scalar extensions on top of gc
+ 'rv64gc-scalar-extras': riscv_isa_to_tune('rv64gc_zicbom_zicboz_zicond_zfa_zfhmin'),
+ # profile plus vector crypto extensions
+ 'rva20-vector-crypto': profile('rva20u64') + ' v zvbb zvkt',
+ # a profile missing one extension, falling back to the previous one
+ 'rva22-no-zkt': profile('rva22u64', 'zkt'),
+ # rva23u64 without the full vector extension
+ 'rva23-no-v': profile('rva23u64', 'v'),
+ }
+
+ config = self.machine_config('qemuriscv64')
+ for tune, features in tunes.items():
+ config += 'AVAILTUNES += "%s"\n' % tune
+ config += 'TUNE_FEATURES:tune-%s = "%s"\n' % (tune, features)
+ config += 'PACKAGE_EXTRA_ARCHS:tune-%s = "${TUNE_RISCV_PKGARCH}"\n' % tune
+
+ for tune in tunes:
+ with self.subTest(tune=tune):
+ self.write_config(config + 'DEFAULTTUNE = "%s"\n' % tune)
+ # small, and compiled with TUNE_CCARGS. It has no do_build, and
+ # populate_sysroot also writes an sstate object.
+ bitbake('libgcc-initial -c populate_sysroot')
--
2.55.0
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support
2026-09-30 16:38 [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Trevor Gamblin
` (18 preceding siblings ...)
2026-09-30 16:38 ` [OE-core][PATCH RFC v2 19/19] selftest: cases: add riscvtune.py Trevor Gamblin
@ 2026-10-01 9:13 ` Paul Barker
2026-10-08 7:15 ` Trevor Gamblin
2026-10-08 10:56 ` Khem Raj
19 siblings, 2 replies; 26+ messages in thread
From: Paul Barker @ 2026-10-01 9:13 UTC (permalink / raw)
To: Trevor Gamblin, openembedded-core; +Cc: raj.khem, mark.hatle
Hi Trevor,
Snipping a lot of the cover letter to give some initial thoughts...
On Wed, 2026-09-30 at 12:38 -0400, Trevor Gamblin wrote:
> A list of changes, by group:
>
> 1. Basic clarification changes and extra tunings:
> a. tune-riscv: be explicit about riscv32gc, riscv64gc defaults
> b. tune-riscv.inc: add 'riscv64gcv' tune
I think these changes make sense, and now master has diverged from
blacksail it may be a good time to take them.
> 2. Adding official RVA20 profile extensions, and supporting the explicit choice
> of 'rva20u64' as a tuning option for builds:
> a. arch-riscv.inc: add missing RVA20 extensions
> b. meta/lib/oe/tune.py: support profile strings, add rva20u64
> c. tune-riscv.inc: add rva20u64 to AVAILTUNES
> 3. Adding RVA22 profile support:
> a. arch-riscv.inc: add rva22u64 extensions
> b. meta/lib/oe/tune.py: add rva22u64 profile
> c. tune-riscv.inc: add rva22u64 to AVAILTUNES
> 4. Adding RVA23 profile support:
> a. arch-riscv.inc: add rva23u64 extensions
> b. meta/lib/oe/tune.py: add rva23u64 profile
> c. tune-riscv.inc: add rva23u64 to AVAILTUNES
> 5. Quality-of-life fixups after 1-4:
> a. meta/lib/oe/tune.py: add riscv_pkgarch()
> b. arch-riscv.inc: rename TUNE_RISCV_PKGARCH -> TUNE_RISCV_PKGARCH_EXACT
> in assignments
> c. tune.py: add implied tuning logic
> d. tune.py: add vector extensions to RISCV_IMPLIED
> e. tune-riscv.inc: add RISCV_PKGARCH vars, set PACKAGE_EXTRA_ARCHS
> f. tune-riscv.inc: clarify zifencei comment
> 6. Selftests:
> a. selftest: oelib: add tune.py
> b. selftest: cases: add riscvtune.py
There are no users of the RVA20, RVA22 or RVA23 profiles in OE-core, so
it's hard to be confident that the approach is right here. I assume the
goal is to convert some of the machines in meta-riscv to use the
appropriate TUNE once these changes are merged? If so, it may be better
to first add support for the new profiles in meta-riscv and update
relevant machine configurations to use them. Once they've had some time
to stabilise in meta-riscv we could then move them into OE-core.
> One significant change to the way profile strings are processed with
> these patches shows up in sstate/build path naming, and is part of the
> reason for patch 5a-5d above. Before, a build directory
> might have a path in it like:
>
> > build/tmp/work/riscv64imafdc_zicsr_zifencei-poky-linux/
>
> This was fine when the extension list was short (for riscv64gc), but with the
> full RVA profiles, the paths started to get so long that bitbake would produce
> this error:
>
> > ERROR: Unable to reduce sstate name to less than 255 chararacters
>
> To solve this problem, meta/lib/oe/tune.py now supports a very short
> list of profile names, and includes new functions (riscv_pkgarch() and
> riscv_implied()) designed to compare selected extensions against
> dependencies (profile and otherwise), and shorten path names
> appropriately. As an example, if you set the following in local.conf:
>
> > AVAILTUNES += "my-rva20-tune"
> > TUNE_FEATURES:tune-my-rva20-tune = "${@oe.tune.riscv_isa_to_tune('rv64gc')} ziccamoa ziccif zicclsm ziccrse zicntr za128rs"
> > PACKAGE_EXTRA_ARCHS:tune-my-rva20-tune = "${TUNE_RISCV_PKGARCH}"
> > DEFAULTTUNE = "my-rva20-tune"
>
> then 'bitbake-getvar --value TUNE_PKGARCH' shows that it is recognized
> as the RVA20 profile:
>
> > rva20u64_zifencei
>
> Extensions implied by others (e.g. 'zmmul', implied by 'm') don't need
> to be listed, but if they are the same result is obtained.
>
> With all of this combined, subdirectories in tmp/work/ look like:
>
> > tgamblin@megalith ~/workspace/ypbuilds/poky-qemuriscv64 $ ls build/tmp/work/
> > all-poky-linux qemuriscv64-poky-linux rva20u64_zcmop_zifencei_zihintpause_zimop_zvbb-poky-linux rva23u64_zifencei-poky-linux
> > qemuriscv32-poky-linux riscv32imafdc_zicsr_zifencei-poky-linux rva20u64_zifencei-poky-linux x86_64-linux
>
> Note that 'rva20u64_zcmop_zifencei_zihintpause_zimop_zvbb-poky-linux' is
> a custom configuration that I set in local.conf only for testing
> purposes. Custom tunings still run the ris(c|k) of exceeding the naming
> length, which we may need some extra hashing logic (maybe a bitmask?) to
> handle if we want to enable freely customizing build tunings.
I think this approach makes a lot of sense, given the way RISC-V
extensions work it's probably the only way to make things readable.
>
> # Testing
>
> Testing different profiles' validity against the compiler involved
> setting (for example) DEFAULTTUNE = "rva23u64" and then running 'bitbake
> opensbi' (which also results in a kernel rebuild) as a quick smoke test.
> I've also opted to do full image builds to make sure that the new
> profiles fully boot and run without any obvious errors. I've also run a
> series of boot tests (including ptests for packages like coreutils).
> Note that when the vector extension is enabled (riscv64gcv, rva23u64),
> test durations will generally be higher.
>
> As of v2, I've added some selftests to help:
>
> 1. The 'oelib.tune' suite at meta/lib/oeqa/selftest/cases/oelib/tune.py,
> for testing the riscv_pkgarch(), riscv_isa_to_tune(), and
> riscv_implied() functions
> 2. The 'riscvtune' suite at meta/lib/oeqa/selftest/cases/riscvtune.py,
> for parsing and building against defined and unusual custom tunes to
> ensure they each yield a usable package arch
Looking at qemuriscv.inc we set QB_CPU to rva23s64 for qemuriscv64. I
think we should do some boot testing with different QB_CPU values (e.g.
build for rva20 and test with rva20 virtual CPU).
Long term we may want to set the default TUNE for qemuriscv64 to align
with RVA23.
Best regards,
--
Paul Barker
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support
2026-10-01 9:13 ` [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Paul Barker
@ 2026-10-08 7:15 ` Trevor Gamblin
2026-10-08 10:56 ` Khem Raj
1 sibling, 0 replies; 26+ messages in thread
From: Trevor Gamblin @ 2026-10-08 7:15 UTC (permalink / raw)
To: Paul Barker, Trevor Gamblin, openembedded-core; +Cc: raj.khem, mark.hatle
On Thu Oct 1, 2026 at 5:13 AM EDT, Paul Barker wrote:
> Hi Trevor,
>
> Snipping a lot of the cover letter to give some initial thoughts...
>
> On Wed, 2026-09-30 at 12:38 -0400, Trevor Gamblin wrote:
>> A list of changes, by group:
>>
>> 1. Basic clarification changes and extra tunings:
>> a. tune-riscv: be explicit about riscv32gc, riscv64gc defaults
>> b. tune-riscv.inc: add 'riscv64gcv' tune
>
> I think these changes make sense, and now master has diverged from
> blacksail it may be a good time to take them.
Alright. Do you want me to resubmit them as a smaller, separate series?
>
>> 2. Adding official RVA20 profile extensions, and supporting the explicit choice
>> of 'rva20u64' as a tuning option for builds:
>> a. arch-riscv.inc: add missing RVA20 extensions
>> b. meta/lib/oe/tune.py: support profile strings, add rva20u64
>> c. tune-riscv.inc: add rva20u64 to AVAILTUNES
>> 3. Adding RVA22 profile support:
>> a. arch-riscv.inc: add rva22u64 extensions
>> b. meta/lib/oe/tune.py: add rva22u64 profile
>> c. tune-riscv.inc: add rva22u64 to AVAILTUNES
>> 4. Adding RVA23 profile support:
>> a. arch-riscv.inc: add rva23u64 extensions
>> b. meta/lib/oe/tune.py: add rva23u64 profile
>> c. tune-riscv.inc: add rva23u64 to AVAILTUNES
>> 5. Quality-of-life fixups after 1-4:
>> a. meta/lib/oe/tune.py: add riscv_pkgarch()
>> b. arch-riscv.inc: rename TUNE_RISCV_PKGARCH -> TUNE_RISCV_PKGARCH_EXACT
>> in assignments
>> c. tune.py: add implied tuning logic
>> d. tune.py: add vector extensions to RISCV_IMPLIED
>> e. tune-riscv.inc: add RISCV_PKGARCH vars, set PACKAGE_EXTRA_ARCHS
>> f. tune-riscv.inc: clarify zifencei comment
>> 6. Selftests:
>> a. selftest: oelib: add tune.py
>> b. selftest: cases: add riscvtune.py
>
> There are no users of the RVA20, RVA22 or RVA23 profiles in OE-core, so
> it's hard to be confident that the approach is right here. I assume the
> goal is to convert some of the machines in meta-riscv to use the
> appropriate TUNE once these changes are merged? If so, it may be better
> to first add support for the new profiles in meta-riscv and update
> relevant machine configurations to use them. Once they've had some time
> to stabilise in meta-riscv we could then move them into OE-core.
Yes, that is the idea (in addition to supporting more profiles for development).
I am fine with adding these to meta-riscv in the short-term.
>
>> One significant change to the way profile strings are processed with
>> these patches shows up in sstate/build path naming, and is part of the
>> reason for patch 5a-5d above. Before, a build directory
>> might have a path in it like:
>>
>> > build/tmp/work/riscv64imafdc_zicsr_zifencei-poky-linux/
>>
>> This was fine when the extension list was short (for riscv64gc), but with the
>> full RVA profiles, the paths started to get so long that bitbake would produce
>> this error:
>>
>> > ERROR: Unable to reduce sstate name to less than 255 chararacters
>>
>> To solve this problem, meta/lib/oe/tune.py now supports a very short
>> list of profile names, and includes new functions (riscv_pkgarch() and
>> riscv_implied()) designed to compare selected extensions against
>> dependencies (profile and otherwise), and shorten path names
>> appropriately. As an example, if you set the following in local.conf:
>>
>> > AVAILTUNES += "my-rva20-tune"
>> > TUNE_FEATURES:tune-my-rva20-tune = "${@oe.tune.riscv_isa_to_tune('rv64gc')} ziccamoa ziccif zicclsm ziccrse zicntr za128rs"
>> > PACKAGE_EXTRA_ARCHS:tune-my-rva20-tune = "${TUNE_RISCV_PKGARCH}"
>> > DEFAULTTUNE = "my-rva20-tune"
>>
>> then 'bitbake-getvar --value TUNE_PKGARCH' shows that it is recognized
>> as the RVA20 profile:
>>
>> > rva20u64_zifencei
>>
>> Extensions implied by others (e.g. 'zmmul', implied by 'm') don't need
>> to be listed, but if they are the same result is obtained.
>>
>> With all of this combined, subdirectories in tmp/work/ look like:
>>
>> > tgamblin@megalith ~/workspace/ypbuilds/poky-qemuriscv64 $ ls build/tmp/work/
>> > all-poky-linux qemuriscv64-poky-linux rva20u64_zcmop_zifencei_zihintpause_zimop_zvbb-poky-linux rva23u64_zifencei-poky-linux
>> > qemuriscv32-poky-linux riscv32imafdc_zicsr_zifencei-poky-linux rva20u64_zifencei-poky-linux x86_64-linux
>>
>> Note that 'rva20u64_zcmop_zifencei_zihintpause_zimop_zvbb-poky-linux' is
>> a custom configuration that I set in local.conf only for testing
>> purposes. Custom tunings still run the ris(c|k) of exceeding the naming
>> length, which we may need some extra hashing logic (maybe a bitmask?) to
>> handle if we want to enable freely customizing build tunings.
>
> I think this approach makes a lot of sense, given the way RISC-V
> extensions work it's probably the only way to make things readable.
Ack.
Trevor
>
>>
>> # Testing
>>
>> Testing different profiles' validity against the compiler involved
>> setting (for example) DEFAULTTUNE = "rva23u64" and then running 'bitbake
>> opensbi' (which also results in a kernel rebuild) as a quick smoke test.
>> I've also opted to do full image builds to make sure that the new
>> profiles fully boot and run without any obvious errors. I've also run a
>> series of boot tests (including ptests for packages like coreutils).
>> Note that when the vector extension is enabled (riscv64gcv, rva23u64),
>> test durations will generally be higher.
>>
>> As of v2, I've added some selftests to help:
>>
>> 1. The 'oelib.tune' suite at meta/lib/oeqa/selftest/cases/oelib/tune.py,
>> for testing the riscv_pkgarch(), riscv_isa_to_tune(), and
>> riscv_implied() functions
>> 2. The 'riscvtune' suite at meta/lib/oeqa/selftest/cases/riscvtune.py,
>> for parsing and building against defined and unusual custom tunes to
>> ensure they each yield a usable package arch
>
> Looking at qemuriscv.inc we set QB_CPU to rva23s64 for qemuriscv64. I
> think we should do some boot testing with different QB_CPU values (e.g.
> build for rva20 and test with rva20 virtual CPU).
>
> Long term we may want to set the default TUNE for qemuriscv64 to align
> with RVA23.
>
> Best regards,
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support
2026-10-01 9:13 ` [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support Paul Barker
2026-10-08 7:15 ` Trevor Gamblin
@ 2026-10-08 10:56 ` Khem Raj
2026-10-08 15:42 ` Mark Hatle
1 sibling, 1 reply; 26+ messages in thread
From: Khem Raj @ 2026-10-08 10:56 UTC (permalink / raw)
To: Paul Barker
Cc: Trevor Gamblin, Patches and discussions about the oe-core layer,
mark.hatle
[-- Attachment #1: Type: text/plain, Size: 6519 bytes --]
I will review rest of series in detail later
On Thu, Oct 1, 2026, 11:13 AM Paul Barker <paul@pbarker.dev> wrote:
> Hi Trevor,
>
> Snipping a lot of the cover letter to give some initial thoughts...
>
> On Wed, 2026-09-30 at 12:38 -0400, Trevor Gamblin wrote:
> > A list of changes, by group:
> >
> > 1. Basic clarification changes and extra tunings:
> > a. tune-riscv: be explicit about riscv32gc, riscv64gc defaults
> > b. tune-riscv.inc: add 'riscv64gcv' tune
>
> I think these changes make sense, and now master has diverged from
> blacksail it may be a good time to take them.
>
> > 2. Adding official RVA20 profile extensions, and supporting the explicit
> choice
> > of 'rva20u64' as a tuning option for builds:
> > a. arch-riscv.inc: add missing RVA20 extensions
> > b. meta/lib/oe/tune.py: support profile strings, add rva20u64
> > c. tune-riscv.inc: add rva20u64 to AVAILTUNES
> > 3. Adding RVA22 profile support:
> > a. arch-riscv.inc: add rva22u64 extensions
> > b. meta/lib/oe/tune.py: add rva22u64 profile
> > c. tune-riscv.inc: add rva22u64 to AVAILTUNES
> > 4. Adding RVA23 profile support:
> > a. arch-riscv.inc: add rva23u64 extensions
> > b. meta/lib/oe/tune.py: add rva23u64 profile
> > c. tune-riscv.inc: add rva23u64 to AVAILTUNES
> > 5. Quality-of-life fixups after 1-4:
> > a. meta/lib/oe/tune.py: add riscv_pkgarch()
> > b. arch-riscv.inc: rename TUNE_RISCV_PKGARCH ->
> TUNE_RISCV_PKGARCH_EXACT
> > in assignments
> > c. tune.py: add implied tuning logic
> > d. tune.py: add vector extensions to RISCV_IMPLIED
> > e. tune-riscv.inc: add RISCV_PKGARCH vars, set PACKAGE_EXTRA_ARCHS
> > f. tune-riscv.inc: clarify zifencei comment
> > 6. Selftests:
> > a. selftest: oelib: add tune.py
> > b. selftest: cases: add riscvtune.py
>
> There are no users of the RVA20, RVA22 or RVA23 profiles in OE-core, so
> it's hard to be confident that the approach is right here. I assume the
> goal is to convert some of the machines in meta-riscv to use the
> appropriate TUNE once these changes are merged? If so, it may be better
> to first add support for the new profiles in meta-riscv and update
> relevant machine configurations to use them. Once they've had some time
> to stabilise in meta-riscv we could then move them into OE-core.
>
Its better to handle it in one place in oe-core. We do similar for arm.
Where we have all kind of tunes in core its simpler to get the logic
working that way. Older editions of architectures aren't going away anytime
soon.
>
> > One significant change to the way profile strings are processed with
> > these patches shows up in sstate/build path naming, and is part of the
> > reason for patch 5a-5d above. Before, a build directory
> > might have a path in it like:
> >
> > > build/tmp/work/riscv64imafdc_zicsr_zifencei-poky-linux/
> >
> > This was fine when the extension list was short (for riscv64gc), but
> with the
> > full RVA profiles, the paths started to get so long that bitbake would
> produce
> > this error:
> >
> > > ERROR: Unable to reduce sstate name to less than 255 chararacters
> >
> > To solve this problem, meta/lib/oe/tune.py now supports a very short
> > list of profile names, and includes new functions (riscv_pkgarch() and
> > riscv_implied()) designed to compare selected extensions against
> > dependencies (profile and otherwise), and shorten path names
> > appropriately. As an example, if you set the following in local.conf:
> >
> > > AVAILTUNES += "my-rva20-tune"
> > > TUNE_FEATURES:tune-my-rva20-tune =
> "${@oe.tune.riscv_isa_to_tune('rv64gc')} ziccamoa ziccif zicclsm ziccrse
> zicntr za128rs"
> > > PACKAGE_EXTRA_ARCHS:tune-my-rva20-tune = "${TUNE_RISCV_PKGARCH}"
> > > DEFAULTTUNE = "my-rva20-tune"
> >
> > then 'bitbake-getvar --value TUNE_PKGARCH' shows that it is recognized
> > as the RVA20 profile:
> >
> > > rva20u64_zifencei
> >
> > Extensions implied by others (e.g. 'zmmul', implied by 'm') don't need
> > to be listed, but if they are the same result is obtained.
> >
> > With all of this combined, subdirectories in tmp/work/ look like:
> >
> > > tgamblin@megalith ~/workspace/ypbuilds/poky-qemuriscv64 $ ls
> build/tmp/work/
> > > all-poky-linux qemuriscv64-poky-linux
> rva20u64_zcmop_zifencei_zihintpause_zimop_zvbb-poky-linux
> rva23u64_zifencei-poky-linux
> > > qemuriscv32-poky-linux riscv32imafdc_zicsr_zifencei-poky-linux
> rva20u64_zifencei-poky-linux x86_64-linux
> >
> > Note that 'rva20u64_zcmop_zifencei_zihintpause_zimop_zvbb-poky-linux' is
> > a custom configuration that I set in local.conf only for testing
> > purposes. Custom tunings still run the ris(c|k) of exceeding the naming
> > length, which we may need some extra hashing logic (maybe a bitmask?) to
> > handle if we want to enable freely customizing build tunings.
>
> I think this approach makes a lot of sense, given the way RISC-V
> extensions work it's probably the only way to make things readable.
>
> >
> > # Testing
> >
> > Testing different profiles' validity against the compiler involved
> > setting (for example) DEFAULTTUNE = "rva23u64" and then running 'bitbake
> > opensbi' (which also results in a kernel rebuild) as a quick smoke test.
> > I've also opted to do full image builds to make sure that the new
> > profiles fully boot and run without any obvious errors. I've also run a
> > series of boot tests (including ptests for packages like coreutils).
> > Note that when the vector extension is enabled (riscv64gcv, rva23u64),
> > test durations will generally be higher.
> >
> > As of v2, I've added some selftests to help:
> >
> > 1. The 'oelib.tune' suite at meta/lib/oeqa/selftest/cases/oelib/tune.py,
> > for testing the riscv_pkgarch(), riscv_isa_to_tune(), and
> > riscv_implied() functions
> > 2. The 'riscvtune' suite at meta/lib/oeqa/selftest/cases/riscvtune.py,
> > for parsing and building against defined and unusual custom tunes to
> > ensure they each yield a usable package arch
>
> Looking at qemuriscv.inc we set QB_CPU to rva23s64 for qemuriscv64. I
> think we should do some boot testing with different QB_CPU values (e.g.
> build for rva20 and test with rva20 virtual CPU).
>
> Long term we may want to set the default TUNE for qemuriscv64 to align
> with RVA23.
>
> Best regards,
>
> --
> Paul Barker
>
>
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^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [OE-core][PATCH RFC v2 00/19] riscv: add new ISA extensions and profile support
2026-10-08 10:56 ` Khem Raj
@ 2026-10-08 15:42 ` Mark Hatle
0 siblings, 0 replies; 26+ messages in thread
From: Mark Hatle @ 2026-10-08 15:42 UTC (permalink / raw)
To: Khem Raj, Paul Barker
Cc: Trevor Gamblin, Patches and discussions about the oe-core layer
On 10/8/26 5:56 AM, Khem Raj wrote:
> I will review rest of series in detail later
>
> On Thu, Oct 1, 2026, 11:13 AM Paul Barker <paul@pbarker.dev
> <mailto:paul@pbarker.dev>> wrote:
>
> Hi Trevor,
>
> Snipping a lot of the cover letter to give some initial thoughts...
>
> On Wed, 2026-09-30 at 12:38 -0400, Trevor Gamblin wrote:
> > A list of changes, by group:
> >
> > 1. Basic clarification changes and extra tunings:
> > a. tune-riscv: be explicit about riscv32gc, riscv64gc defaults
> > b. tune-riscv.inc: add 'riscv64gcv' tune
>
> I think these changes make sense, and now master has diverged from
> blacksail it may be a good time to take them.
>
> > 2. Adding official RVA20 profile extensions, and supporting the explicit
> choice
> > of 'rva20u64' as a tuning option for builds:
> > a. arch-riscv.inc: add missing RVA20 extensions
> > b. meta/lib/oe/tune.py: support profile strings, add rva20u64
> > c. tune-riscv.inc: add rva20u64 to AVAILTUNES
> > 3. Adding RVA22 profile support:
> > a. arch-riscv.inc: add rva22u64 extensions
> > b. meta/lib/oe/tune.py: add rva22u64 profile
> > c. tune-riscv.inc: add rva22u64 to AVAILTUNES
> > 4. Adding RVA23 profile support:
> > a. arch-riscv.inc: add rva23u64 extensions
> > b. meta/lib/oe/tune.py: add rva23u64 profile
> > c. tune-riscv.inc: add rva23u64 to AVAILTUNES
> > 5. Quality-of-life fixups after 1-4:
> > a. meta/lib/oe/tune.py: add riscv_pkgarch()
> > b. arch-riscv.inc: rename TUNE_RISCV_PKGARCH -> TUNE_RISCV_PKGARCH_EXACT
> > in assignments
> > c. tune.py: add implied tuning logic
> > d. tune.py: add vector extensions to RISCV_IMPLIED
> > e. tune-riscv.inc: add RISCV_PKGARCH vars, set PACKAGE_EXTRA_ARCHS
> > f. tune-riscv.inc: clarify zifencei comment
> > 6. Selftests:
> > a. selftest: oelib: add tune.py
> > b. selftest: cases: add riscvtune.py
>
> There are no users of the RVA20, RVA22 or RVA23 profiles in OE-core, so
> it's hard to be confident that the approach is right here. I assume the
> goal is to convert some of the machines in meta-riscv to use the
> appropriate TUNE once these changes are merged? If so, it may be better
> to first add support for the new profiles in meta-riscv and update
> relevant machine configurations to use them. Once they've had some time
> to stabilise in meta-riscv we could then move them into OE-core.
>
>
> Its better to handle it in one place in oe-core. We do similar for arm. Where we
> have all kind of tunes in core its simpler to get the logic working that way.
> Older editions of architectures aren't going away anytime soon.
I'm not attempting to speak for RP here, but when I did the initial code. RP
wanted to be sure that we did not introduce additional maintenance by just
adding a boat load of new ISA options without someone willing to maintain them,
a way to test them (i.e. gcc/llvm/etc), and more to the point some sort of
target system(s) that were actively using them.
The initial implementation was formed based on existing OE, plus the AMD FPGA
based Risc-V components, so everything had an active "user" and test path.
I think RP's request from the initial work is still valid. We should be adding
ISA items because they are useful to actual embedded users, and not just because
someone defined them. If they don't exist (yet) in gcc, llvm, etc, we should
not be including them. If there is no hardware (qemu counts as hardware) to
exercise an ISA, I would be reluctant to include it as it just increases
maintenance without a path for testing.
With the above said, I don't have a good view of the risc-v world outside of my
specific workflows and use-cases, so I can't recommend any particular ISA
extensions (in this patch set) that should or should not be included, but I
think the general design above is a good one to keep things reasonable and bound
the problem. (We could try to implement ALL risc-v ISA extensions, but it's
pretty clear to me from reading the docs a lot of them are theoretical or not
used within the scope of what OE is current used for.
>
> > One significant change to the way profile strings are processed with
> > these patches shows up in sstate/build path naming, and is part of the
> > reason for patch 5a-5d above. Before, a build directory
> > might have a path in it like:
> >
> > > build/tmp/work/riscv64imafdc_zicsr_zifencei-poky-linux/
> >
> > This was fine when the extension list was short (for riscv64gc), but with the
> > full RVA profiles, the paths started to get so long that bitbake would
> produce
> > this error:
> >
> > > ERROR: Unable to reduce sstate name to less than 255 chararacters
> >
> > To solve this problem, meta/lib/oe/tune.py now supports a very short
> > list of profile names, and includes new functions (riscv_pkgarch() and
> > riscv_implied()) designed to compare selected extensions against
> > dependencies (profile and otherwise), and shorten path names
> > appropriately. As an example, if you set the following in local.conf:
> >
> > > AVAILTUNES += "my-rva20-tune"
> > > TUNE_FEATURES:tune-my-rva20-tune =
> "${@oe.tune.riscv_isa_to_tune('rv64gc')} ziccamoa ziccif zicclsm ziccrse
> zicntr za128rs"
> > > PACKAGE_EXTRA_ARCHS:tune-my-rva20-tune = "${TUNE_RISCV_PKGARCH}"
> > > DEFAULTTUNE = "my-rva20-tune"
> >
> > then 'bitbake-getvar --value TUNE_PKGARCH' shows that it is recognized
> > as the RVA20 profile:
> >
> > > rva20u64_zifencei
> >
> > Extensions implied by others (e.g. 'zmmul', implied by 'm') don't need
> > to be listed, but if they are the same result is obtained.
> >
> > With all of this combined, subdirectories in tmp/work/ look like:
> >
> > > tgamblin@megalith ~/workspace/ypbuilds/poky-qemuriscv64 $ ls
> build/tmp/work/
> > > all-poky-linux qemuriscv64-poky-linux
> rva20u64_zcmop_zifencei_zihintpause_zimop_zvbb-poky-linux
> rva23u64_zifencei-poky-linux
> > > qemuriscv32-poky-linux riscv32imafdc_zicsr_zifencei-poky-linux
> rva20u64_zifencei-poky-linux x86_64-linux
> >
> > Note that 'rva20u64_zcmop_zifencei_zihintpause_zimop_zvbb-poky-linux' is
> > a custom configuration that I set in local.conf only for testing
> > purposes. Custom tunings still run the ris(c|k) of exceeding the naming
> > length, which we may need some extra hashing logic (maybe a bitmask?) to
> > handle if we want to enable freely customizing build tunings.
>
> I think this approach makes a lot of sense, given the way RISC-V
> extensions work it's probably the only way to make things readable.
>
> >
> > # Testing
> >
> > Testing different profiles' validity against the compiler involved
> > setting (for example) DEFAULTTUNE = "rva23u64" and then running 'bitbake
> > opensbi' (which also results in a kernel rebuild) as a quick smoke test.
> > I've also opted to do full image builds to make sure that the new
> > profiles fully boot and run without any obvious errors. I've also run a
> > series of boot tests (including ptests for packages like coreutils).
> > Note that when the vector extension is enabled (riscv64gcv, rva23u64),
> > test durations will generally be higher.
> >
> > As of v2, I've added some selftests to help:
> >
> > 1. The 'oelib.tune' suite at meta/lib/oeqa/selftest/cases/oelib/tune.py,
> > for testing the riscv_pkgarch(), riscv_isa_to_tune(), and
> > riscv_implied() functions
> > 2. The 'riscvtune' suite at meta/lib/oeqa/selftest/cases/riscvtune.py,
> > for parsing and building against defined and unusual custom tunes to
> > ensure they each yield a usable package arch
>
> Looking at qemuriscv.inc we set QB_CPU to rva23s64 for qemuriscv64. I
> think we should do some boot testing with different QB_CPU values (e.g.
> build for rva20 and test with rva20 virtual CPU).
>
> Long term we may want to set the default TUNE for qemuriscv64 to align
> with RVA23.
>
> Best regards,
>
> --
> Paul Barker
>
^ permalink raw reply [flat|nested] 26+ messages in thread