* [PATCH 2/5] mtd-utils: Explicitly add pthread options to cflags
2018-03-17 3:40 [PATCH 0/5] RISC-V Build fixes Khem Raj
2018-03-17 3:40 ` [PATCH 1/5] gcc: Do not use --with-linker-hash-style if LINKER_HASH_STYLE is empty Khem Raj
@ 2018-03-17 3:40 ` Khem Raj
2018-03-17 3:40 ` [PATCH 3/5] x264: Use updated gnu-config artifacts Khem Raj
` (2 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Khem Raj @ 2018-03-17 3:40 UTC (permalink / raw)
To: openembedded-core
Some architectures e.g. riscv gcc does not add -D_REENTRANT
when enabling pthreads. Help it here by adding these options
while gcc gets fixed
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
meta/recipes-devtools/mtd/mtd-utils_git.bb | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meta/recipes-devtools/mtd/mtd-utils_git.bb b/meta/recipes-devtools/mtd/mtd-utils_git.bb
index 3c34bdd84e..d09d633022 100644
--- a/meta/recipes-devtools/mtd/mtd-utils_git.bb
+++ b/meta/recipes-devtools/mtd/mtd-utils_git.bb
@@ -24,6 +24,8 @@ S = "${WORKDIR}/git/"
PACKAGECONFIG ?= "${@bb.utils.filter('DISTRO_FEATURES', 'xattr', d)}"
PACKAGECONFIG[xattr] = ",,acl,"
+CPPFLAGS_append_riscv64 = " -pthread -D_REENTRANT"
+
EXTRA_OEMAKE = "'CC=${CC}' 'RANLIB=${RANLIB}' 'AR=${AR}' 'CFLAGS=${CFLAGS} ${@bb.utils.contains('PACKAGECONFIG', 'xattr', '', '-DWITHOUT_XATTR', d)} -I${S}/include' 'BUILDDIR=${S}'"
ALTERNATIVE_${PN} = "flash_eraseall"
--
2.16.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 4/5] python-numpy: Fix build for riscv64
2018-03-17 3:40 [PATCH 0/5] RISC-V Build fixes Khem Raj
` (2 preceding siblings ...)
2018-03-17 3:40 ` [PATCH 3/5] x264: Use updated gnu-config artifacts Khem Raj
@ 2018-03-17 3:40 ` Khem Raj
2018-03-17 3:40 ` [PATCH 5/5] dpkg: Backport riscv support Khem Raj
4 siblings, 0 replies; 12+ messages in thread
From: Khem Raj @ 2018-03-17 3:40 UTC (permalink / raw)
To: openembedded-core
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
.../files/0001-npy_cpu-Add-riscv-support.patch | 28 +++++
.../python-numpy/files/riscv64/_numpyconfig.h | 32 +++++
.../python-numpy/files/riscv64/config.h | 139 +++++++++++++++++++++
.../recipes-devtools/python-numpy/python-numpy.inc | 5 +
4 files changed, 204 insertions(+)
create mode 100644 meta/recipes-devtools/python-numpy/files/0001-npy_cpu-Add-riscv-support.patch
create mode 100644 meta/recipes-devtools/python-numpy/files/riscv64/_numpyconfig.h
create mode 100644 meta/recipes-devtools/python-numpy/files/riscv64/config.h
diff --git a/meta/recipes-devtools/python-numpy/files/0001-npy_cpu-Add-riscv-support.patch b/meta/recipes-devtools/python-numpy/files/0001-npy_cpu-Add-riscv-support.patch
new file mode 100644
index 0000000000..4f5c4f5f0d
--- /dev/null
+++ b/meta/recipes-devtools/python-numpy/files/0001-npy_cpu-Add-riscv-support.patch
@@ -0,0 +1,28 @@
+From 30fb1bf9244bb0789c02ec7c98a923acc7200206 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Fri, 16 Mar 2018 19:55:21 -0700
+Subject: [PATCH] npy_cpu: Add riscv support
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+Upstream-Status: Submitted [https://github.com/numpy/numpy/pull/10761]
+
+ numpy/core/include/numpy/npy_cpu.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/numpy/core/include/numpy/npy_cpu.h b/numpy/core/include/numpy/npy_cpu.h
+index 84653ea18..9e88db873 100644
+--- a/numpy/core/include/numpy/npy_cpu.h
++++ b/numpy/core/include/numpy/npy_cpu.h
+@@ -78,6 +78,8 @@
+ #define NPY_CPU_AARCH64
+ #elif defined(__mc68000__)
+ #define NPY_CPU_M68K
++#elif defined(__riscv)
++ #define NPY_CPU_RISCV
+ #elif defined(__arc__) && defined(__LITTLE_ENDIAN__)
+ #define NPY_CPU_ARCEL
+ #elif defined(__arc__) && defined(__BIG_ENDIAN__)
+--
+2.16.2
+
diff --git a/meta/recipes-devtools/python-numpy/files/riscv64/_numpyconfig.h b/meta/recipes-devtools/python-numpy/files/riscv64/_numpyconfig.h
new file mode 100644
index 0000000000..109deb0435
--- /dev/null
+++ b/meta/recipes-devtools/python-numpy/files/riscv64/_numpyconfig.h
@@ -0,0 +1,32 @@
+#define NPY_HAVE_ENDIAN_H 1
+#define NPY_SIZEOF_SHORT SIZEOF_SHORT
+#define NPY_SIZEOF_INT SIZEOF_INT
+#define NPY_SIZEOF_LONG SIZEOF_LONG
+#define NPY_SIZEOF_FLOAT 4
+#define NPY_SIZEOF_COMPLEX_FLOAT 8
+#define NPY_SIZEOF_DOUBLE 8
+#define NPY_SIZEOF_COMPLEX_DOUBLE 16
+#define NPY_SIZEOF_LONGDOUBLE 16
+#define NPY_SIZEOF_COMPLEX_LONGDOUBLE 32
+#define NPY_SIZEOF_PY_INTPTR_T 8
+#define NPY_SIZEOF_PY_LONG_LONG 8
+#define NPY_SIZEOF_LONGLONG 8
+#define NPY_SIZEOF_OFF_T 8
+#define NPY_NO_SMP 0
+#define NPY_HAVE_DECL_ISNAN
+#define NPY_HAVE_DECL_ISINF
+#define NPY_HAVE_DECL_ISFINITE
+#define NPY_HAVE_DECL_SIGNBIT
+#define NPY_USE_C99_COMPLEX 1
+#define NPY_HAVE_COMPLEX_DOUBLE 1
+#define NPY_HAVE_COMPLEX_FLOAT 1
+#define NPY_HAVE_COMPLEX_LONG_DOUBLE 1
+#define NPY_ENABLE_SEPARATE_COMPILATION 1
+#define NPY_USE_C99_FORMATS 1
+#define NPY_VISIBILITY_HIDDEN __attribute__((visibility("hidden")))
+#define NPY_ABI_VERSION 0x01000009
+#define NPY_API_VERSION 0x0000000A
+
+#ifndef __STDC_FORMAT_MACROS
+#define __STDC_FORMAT_MACROS 1
+#endif
diff --git a/meta/recipes-devtools/python-numpy/files/riscv64/config.h b/meta/recipes-devtools/python-numpy/files/riscv64/config.h
new file mode 100644
index 0000000000..c30b868f2f
--- /dev/null
+++ b/meta/recipes-devtools/python-numpy/files/riscv64/config.h
@@ -0,0 +1,139 @@
+#define HAVE_ENDIAN_H 1
+#define SIZEOF_PY_INTPTR_T 8
+#define SIZEOF_PY_LONG_LONG 8
+#define MATHLIB m
+#define HAVE_SIN 1
+#define HAVE_COS 1
+#define HAVE_TAN 1
+#define HAVE_SINH 1
+#define HAVE_COSH 1
+#define HAVE_TANH 1
+#define HAVE_FABS 1
+#define HAVE_FLOOR 1
+#define HAVE_CEIL 1
+#define HAVE_SQRT 1
+#define HAVE_LOG10 1
+#define HAVE_LOG 1
+#define HAVE_EXP 1
+#define HAVE_ASIN 1
+#define HAVE_ACOS 1
+#define HAVE_ATAN 1
+#define HAVE_FMOD 1
+#define HAVE_MODF 1
+#define HAVE_FREXP 1
+#define HAVE_LDEXP 1
+#define HAVE_RINT 1
+#define HAVE_TRUNC 1
+#define HAVE_EXP2 1
+#define HAVE_LOG2 1
+#define HAVE_ATAN2 1
+#define HAVE_POW 1
+#define HAVE_NEXTAFTER 1
+#define HAVE_SINF 1
+#define HAVE_COSF 1
+#define HAVE_TANF 1
+#define HAVE_SINHF 1
+#define HAVE_COSHF 1
+#define HAVE_TANHF 1
+#define HAVE_FABSF 1
+#define HAVE_FLOORF 1
+#define HAVE_CEILF 1
+#define HAVE_RINTF 1
+#define HAVE_TRUNCF 1
+#define HAVE_SQRTF 1
+#define HAVE_LOG10F 1
+#define HAVE_LOGF 1
+#define HAVE_LOG1PF 1
+#define HAVE_EXPF 1
+#define HAVE_EXPM1F 1
+#define HAVE_ASINF 1
+#define HAVE_ACOSF 1
+#define HAVE_ATANF 1
+#define HAVE_ASINHF 1
+#define HAVE_ACOSHF 1
+#define HAVE_ATANHF 1
+#define HAVE_HYPOTF 1
+#define HAVE_ATAN2F 1
+#define HAVE_POWF 1
+#define HAVE_FMODF 1
+#define HAVE_MODFF 1
+#define HAVE_FREXPF 1
+#define HAVE_LDEXPF 1
+#define HAVE_EXP2F 1
+#define HAVE_LOG2F 1
+#define HAVE_COPYSIGNF 1
+#define HAVE_NEXTAFTERF 1
+#define HAVE_SINL 1
+#define HAVE_COSL 1
+#define HAVE_TANL 1
+#define HAVE_SINHL 1
+#define HAVE_COSHL 1
+#define HAVE_TANHL 1
+#define HAVE_FABSL 1
+#define HAVE_FLOORL 1
+#define HAVE_CEILL 1
+#define HAVE_RINTL 1
+#define HAVE_TRUNCL 1
+#define HAVE_SQRTL 1
+#define HAVE_LOG10L 1
+#define HAVE_LOGL 1
+#define HAVE_LOG1PL 1
+#define HAVE_EXPL 1
+#define HAVE_EXPM1L 1
+#define HAVE_ASINL 1
+#define HAVE_ACOSL 1
+#define HAVE_ATANL 1
+#define HAVE_ASINHL 1
+#define HAVE_ACOSHL 1
+#define HAVE_ATANHL 1
+#define HAVE_HYPOTL 1
+#define HAVE_ATAN2L 1
+#define HAVE_POWL 1
+#define HAVE_FMODL 1
+#define HAVE_MODFL 1
+#define HAVE_FREXPL 1
+#define HAVE_LDEXPL 1
+#define HAVE_EXP2L 1
+#define HAVE_LOG2L 1
+#define HAVE_COPYSIGNL 1
+#define HAVE_NEXTAFTERL 1
+#define HAVE_DECL_SIGNBIT
+#define HAVE_COMPLEX_H 1
+#define HAVE_CREAL 1
+#define HAVE_CIMAG 1
+#define HAVE_CABS 1
+#define HAVE_CARG 1
+#define HAVE_CEXP 1
+#define HAVE_CSQRT 1
+#define HAVE_CLOG 1
+#define HAVE_CCOS 1
+#define HAVE_CSIN 1
+#define HAVE_CPOW 1
+#define HAVE_CREALF 1
+#define HAVE_CIMAGF 1
+#define HAVE_CABSF 1
+#define HAVE_CARGF 1
+#define HAVE_CEXPF 1
+#define HAVE_CSQRTF 1
+#define HAVE_CLOGF 1
+#define HAVE_CCOSF 1
+#define HAVE_CSINF 1
+#define HAVE_CPOWF 1
+#define HAVE_CREALL 1
+#define HAVE_CIMAGL 1
+#define HAVE_CABSL 1
+#define HAVE_CARGL 1
+#define HAVE_CEXPL 1
+#define HAVE_CSQRTL 1
+#define HAVE_CLOGL 1
+#define HAVE_CCOSL 1
+#define HAVE_CSINL 1
+#define HAVE_CPOWL 1
+#define HAVE_LDOUBLE_IEEE_QUAD_LE 1
+#ifndef __cplusplus
+/* #undef inline */
+#endif
+
+#ifndef _NPY_NPY_CONFIG_H_
+#error config.h should never be included directly, include npy_config.h instead
+#endif
diff --git a/meta/recipes-devtools/python-numpy/python-numpy.inc b/meta/recipes-devtools/python-numpy/python-numpy.inc
index 10af4c50e3..5c5f0c837a 100644
--- a/meta/recipes-devtools/python-numpy/python-numpy.inc
+++ b/meta/recipes-devtools/python-numpy/python-numpy.inc
@@ -8,6 +8,7 @@ SRCNAME = "numpy"
SRC_URI = "https://github.com/${SRCNAME}/${SRCNAME}/releases/download/v${PV}/${SRCNAME}-${PV}.tar.gz \
file://0001-Don-t-search-usr-and-so-on-for-libraries-by-default-.patch \
file://fix_shebang_f2py.patch \
+ file://0001-npy_cpu-Add-riscv-support.patch \
${CONFIGFILESURI} "
SRC_URI[md5sum] = "0e09f20f62ab9f8a02cb7bd3fd023482"
SRC_URI[sha256sum] = "8708a775be9a9a457b80a49193c57bd9d51a8a195ed1f1c4b8e89eaf3aa646ee"
@@ -69,6 +70,10 @@ CONFIGFILESURI_mipsarchn32el = " \
file://config.h \
file://_numpyconfig.h \
"
+CONFIGFILESURI_riscv64 = " \
+ file://config.h \
+ file://_numpyconfig.h \
+"
S = "${WORKDIR}/numpy-${PV}"
--
2.16.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 5/5] dpkg: Backport riscv support
2018-03-17 3:40 [PATCH 0/5] RISC-V Build fixes Khem Raj
` (3 preceding siblings ...)
2018-03-17 3:40 ` [PATCH 4/5] python-numpy: Fix build for riscv64 Khem Raj
@ 2018-03-17 3:40 ` Khem Raj
4 siblings, 0 replies; 12+ messages in thread
From: Khem Raj @ 2018-03-17 3:40 UTC (permalink / raw)
To: openembedded-core
Refresh patches with devtool
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
.../0001-arch-Add-support-for-riscv64-CPU.patch | 54 ++++++++++++++++++++++
.../dpkg/dpkg/glibc2.5-sync_file_range.patch | 21 +++++++--
meta/recipes-devtools/dpkg/dpkg_1.18.24.bb | 1 +
3 files changed, 71 insertions(+), 5 deletions(-)
create mode 100644 meta/recipes-devtools/dpkg/dpkg/0001-arch-Add-support-for-riscv64-CPU.patch
diff --git a/meta/recipes-devtools/dpkg/dpkg/0001-arch-Add-support-for-riscv64-CPU.patch b/meta/recipes-devtools/dpkg/dpkg/0001-arch-Add-support-for-riscv64-CPU.patch
new file mode 100644
index 0000000000..45c606e690
--- /dev/null
+++ b/meta/recipes-devtools/dpkg/dpkg/0001-arch-Add-support-for-riscv64-CPU.patch
@@ -0,0 +1,54 @@
+From 319f32d743f5b5e725012654d124e49226d5de91 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Fri, 16 Mar 2018 20:28:24 -0700
+Subject: [PATCH] arch: Add support for riscv64 CPU
+
+ * Architecture support:
+ - Add support for riscv64 CPU. Closes: #822914
+ Thanks to Manuel A. Fernandez Montecelo <mafm@debian.org>
+
+Upstream-Status: Backport [https://alioth.debian.org/plugins/scmgit/cgi-bin/gitweb.cgi?p=dpkg%2Fdpkg.git;a=commitdiff_plain;h=ee0855cc66076691de4796be48f8a0d889fde001;hp=2f5816d8be40b449d2473b22f9e0c33b32f3bd78]
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ data/cputable | 1 +
+ scripts/t/Dpkg_Arch.t | 4 ++--
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/data/cputable b/data/cputable
+index a2bd7d6..9f2a8e0 100644
+--- a/data/cputable
++++ b/data/cputable
+@@ -41,6 +41,7 @@ powerpc powerpc (powerpc|ppc) 32 big
+ powerpcel powerpcle powerpcle 32 little
+ ppc64 powerpc64 (powerpc|ppc)64 64 big
+ ppc64el powerpc64le powerpc64le 64 little
++riscv64 riscv64 riscv64 64 little
+ s390 s390 s390 32 big
+ s390x s390x s390x 64 big
+ sh3 sh3 sh3 32 little
+diff --git a/scripts/t/Dpkg_Arch.t b/scripts/t/Dpkg_Arch.t
+index d478b49..ecd5d66 100644
+--- a/scripts/t/Dpkg_Arch.t
++++ b/scripts/t/Dpkg_Arch.t
+@@ -16,7 +16,7 @@
+ use strict;
+ use warnings;
+
+-use Test::More tests => 16367;
++use Test::More tests => 16832;
+
+ use_ok('Dpkg::Arch', qw(debarch_to_debtuple debarch_to_multiarch
+ debarch_eq debarch_is debarch_is_wildcard
+@@ -162,7 +162,7 @@ is(gnutriplet_to_debarch(undef), undef, 'undef gnutriplet');
+ is(gnutriplet_to_debarch('unknown-unknown-unknown'), undef, 'unknown gnutriplet');
+ is(gnutriplet_to_debarch('x86_64-linux-gnu'), 'amd64', 'known gnutriplet');
+
+-is(scalar get_valid_arches(), 524, 'expected amount of known architectures');
++is(scalar get_valid_arches(), 539, 'expected amount of known architectures');
+
+ {
+ local $ENV{CC} = 'false';
+--
+2.16.2
+
diff --git a/meta/recipes-devtools/dpkg/dpkg/glibc2.5-sync_file_range.patch b/meta/recipes-devtools/dpkg/dpkg/glibc2.5-sync_file_range.patch
index d56b8a69a3..d48386647e 100644
--- a/meta/recipes-devtools/dpkg/dpkg/glibc2.5-sync_file_range.patch
+++ b/meta/recipes-devtools/dpkg/dpkg/glibc2.5-sync_file_range.patch
@@ -1,12 +1,17 @@
+From 9d260d408f9e17abd1d1dccd685bd7e80a3655a9 Mon Sep 17 00:00:00 2001
+From: Donn Seeley <donn.seeley@windriver.com>
+Date: Tue, 25 Feb 2014 17:44:04 +0800
+Subject: [PATCH] dpkg: fix a link problem for dpkg-native on CentOS 5.8
+
CentOS 5.8 kernels and headers support the sync_file_range() system call,
but glibc 2.5 doesn't provide the syscall stub. It appears that this
problem is known but will never be fixed:
https://bugzilla.redhat.com/show_bug.cgi?id=518581
- Bug 518581 - [RHEL5] glibc misses sync_file_range syscall interface
+ Bug 518581 - [RHEL5] glibc misses sync_file_range syscall interface
- Status: CLOSED CANTFIX
+ Status: CLOSED CANTFIX
Last Closed: 2009-11-22 22:19:55
Kirby Zhou 2009-08-20 23:37:55 EDT
@@ -60,13 +65,16 @@ Upstream-Status: Inappropriate [everyone else builds on newer hosts :-)]
Signed-off-by: Donn Seeley <donn.seeley@windriver.com>
Signed-off-by: Lei Liu <lei.liu2@windriver.com>
+
---
- src/archives.c | 4 ++--
+ src/archives.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/src/archives.c b/src/archives.c
+index 4b2fc92..a92b795 100644
--- a/src/archives.c
+++ b/src/archives.c
-@@ -75,7 +75,7 @@
+@@ -69,7 +69,7 @@ fd_writeback_init(int fd)
/* Ignore the return code as it should be considered equivalent to an
* asynchronous hint for the kernel, we are doing an fsync() later on
* anyway. */
@@ -75,7 +83,7 @@ Signed-off-by: Lei Liu <lei.liu2@windriver.com>
sync_file_range(fd, 0, 0, SYNC_FILE_RANGE_WRITE);
#elif defined(HAVE_POSIX_FADVISE)
posix_fadvise(fd, 0, 0, POSIX_FADV_DONTNEED);
-@@ -1179,7 +1179,7 @@
+@@ -1078,7 +1078,7 @@ tarobject(void *ctx, struct tar_entry *ti)
return 0;
}
@@ -84,3 +92,6 @@ Signed-off-by: Lei Liu <lei.liu2@windriver.com>
static void
tar_writeback_barrier(struct fileinlist *files, struct pkginfo *pkg)
{
+--
+2.16.2
+
diff --git a/meta/recipes-devtools/dpkg/dpkg_1.18.24.bb b/meta/recipes-devtools/dpkg/dpkg_1.18.24.bb
index c0c59f1410..6d8ec34768 100644
--- a/meta/recipes-devtools/dpkg/dpkg_1.18.24.bb
+++ b/meta/recipes-devtools/dpkg/dpkg_1.18.24.bb
@@ -14,6 +14,7 @@ SRC_URI = "http://snapshot.debian.org/archive/debian/20170518T093838Z/pool/main/
file://0006-add-musleabi-to-known-target-tripets.patch \
file://0007-dpkg-deb-build.c-Remove-usage-of-clamp-mtime-in-tar.patch \
file://0001-dpkg-Support-muslx32-build.patch \
+ file://0001-arch-Add-support-for-riscv64-CPU.patch \
"
SRC_URI_append_class-native = " file://glibc2.5-sync_file_range.patch "
--
2.16.2
^ permalink raw reply related [flat|nested] 12+ messages in thread