From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v2 02/14] openrisc: define CPU_BIG_ENDIAN as true
Date: Sun, 10 Sep 2017 15:49:14 +0900 [thread overview]
Message-ID: <20170910064926.5874-3-shorne@gmail.com> (raw)
In-Reply-To: <20170910064926.5874-1-shorne@gmail.com>
While working on SMP for OpenRISC I found this is needed for qrwlocks to
work correctly. OpenRISC is big endian so this should have been here
already.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index ee34d94f7aa2..356dd67a86ea 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -29,6 +29,9 @@ config OPENRISC
select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
select NO_BOOTMEM
+config CPU_BIG_ENDIAN
+ def_bool y
+
config MMU
def_bool y
--
2.13.5
next prev parent reply other threads:[~2017-09-10 6:49 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-10 6:49 [OpenRISC] [PATCH v2 00/14] OpenRISC SMP Support Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 01/14] openrisc: use shadow registers to save regs on exception Stafford Horne
2017-09-10 6:49 ` Stafford Horne [this message]
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 03/14] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 04/14] openrisc: use qspinlocks and qrwlocks Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list Stafford Horne
2017-09-10 11:13 ` Andreas =?unknown-8bit?q?F=C3=A4rber?=
2017-09-18 20:39 ` Rob Herring
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 06/14] irqchip: add initial support for ompic Stafford Horne
2017-09-13 17:21 ` Marc Zyngier
2017-09-14 6:54 ` Stafford Horne
2017-09-14 18:31 ` Marc Zyngier
2017-09-18 20:29 ` Rob Herring
2017-09-19 12:14 ` Stafford Horne
2017-09-18 20:43 ` Rob Herring
2017-09-19 12:10 ` Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 07/14] openrisc: initial SMP support Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 08/14] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 09/14] openrisc: sleep instead of spin on secondary wait Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 10/14] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 11/14] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 12/14] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 13/14] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 14/14] openrisc: add tick timer multicore sync logic Stafford Horne
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