From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v2 04/14] openrisc: use qspinlocks and qrwlocks
Date: Sun, 10 Sep 2017 15:49:16 +0900 [thread overview]
Message-ID: <20170910064926.5874-5-shorne@gmail.com> (raw)
In-Reply-To: <20170910064926.5874-1-shorne@gmail.com>
Enable OpenRISC to use qspinlocks and qrwlocks for upcoming SMP support.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 2 ++
arch/openrisc/include/asm/Kbuild | 4 ++++
arch/openrisc/include/asm/spinlock.h | 12 +++++++++++-
arch/openrisc/include/asm/spinlock_types.h | 7 +++++++
4 files changed, 24 insertions(+), 1 deletion(-)
create mode 100644 arch/openrisc/include/asm/spinlock_types.h
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 356dd67a86ea..b49acda5e8f4 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -28,6 +28,8 @@ config OPENRISC
select OR1K_PIC
select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
select NO_BOOTMEM
+ select ARCH_USE_QUEUED_SPINLOCKS
+ select ARCH_USE_QUEUED_RWLOCKS
config CPU_BIG_ENDIAN
def_bool y
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 5bea416a7792..5f066780d870 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -28,6 +28,10 @@ generic-y += module.h
generic-y += pci.h
generic-y += percpu.h
generic-y += preempt.h
+generic-y += qspinlock_types.h
+generic-y += qspinlock.h
+generic-y += qrwlock_types.h
+generic-y += qrwlock.h
generic-y += sections.h
generic-y += segment.h
generic-y += string.h
diff --git a/arch/openrisc/include/asm/spinlock.h b/arch/openrisc/include/asm/spinlock.h
index fd00a3a24123..9b761e0e22c3 100644
--- a/arch/openrisc/include/asm/spinlock.h
+++ b/arch/openrisc/include/asm/spinlock.h
@@ -19,6 +19,16 @@
#ifndef __ASM_OPENRISC_SPINLOCK_H
#define __ASM_OPENRISC_SPINLOCK_H
-#error "or32 doesn't do SMP yet"
+#include <asm/qspinlock.h>
+
+#include <asm/qrwlock.h>
+
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
+#define arch_spin_relax(lock) cpu_relax()
+#define arch_read_relax(lock) cpu_relax()
+#define arch_write_relax(lock) cpu_relax()
+
#endif
diff --git a/arch/openrisc/include/asm/spinlock_types.h b/arch/openrisc/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..7c6fb1208c88
--- /dev/null
+++ b/arch/openrisc/include/asm/spinlock_types.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_OPENRISC_SPINLOCK_TYPES_H
+#define _ASM_OPENRISC_SPINLOCK_TYPES_H
+
+#include <asm/qspinlock_types.h>
+#include <asm/qrwlock_types.h>
+
+#endif /* _ASM_OPENRISC_SPINLOCK_TYPES_H */
--
2.13.5
next prev parent reply other threads:[~2017-09-10 6:49 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-10 6:49 [OpenRISC] [PATCH v2 00/14] OpenRISC SMP Support Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 01/14] openrisc: use shadow registers to save regs on exception Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 02/14] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 03/14] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
2017-09-10 6:49 ` Stafford Horne [this message]
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list Stafford Horne
2017-09-10 11:13 ` Andreas =?unknown-8bit?q?F=C3=A4rber?=
2017-09-18 20:39 ` Rob Herring
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 06/14] irqchip: add initial support for ompic Stafford Horne
2017-09-13 17:21 ` Marc Zyngier
2017-09-14 6:54 ` Stafford Horne
2017-09-14 18:31 ` Marc Zyngier
2017-09-18 20:29 ` Rob Herring
2017-09-19 12:14 ` Stafford Horne
2017-09-18 20:43 ` Rob Herring
2017-09-19 12:10 ` Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 07/14] openrisc: initial SMP support Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 08/14] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 09/14] openrisc: sleep instead of spin on secondary wait Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 10/14] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 11/14] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 12/14] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 13/14] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
2017-09-10 6:49 ` [OpenRISC] [PATCH v2 14/14] openrisc: add tick timer multicore sync logic Stafford Horne
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