* [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support
@ 2018-03-15 10:50 Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 02/28] net: Remove Blackfin Ethernet support Aaron Wu
` (26 more replies)
0 siblings, 27 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin CPU arch general support
---
arch/blackfin/Clear_BSD.txt | 33 -
arch/blackfin/Kconfig | 1463 --------
arch/blackfin/Kconfig.debug | 258 --
arch/blackfin/Makefile | 168 -
arch/blackfin/boot/.gitignore | 3 -
arch/blackfin/boot/Makefile | 71 -
arch/blackfin/boot/install.sh | 57 -
arch/blackfin/configs/BF518F-EZBRD_defconfig | 121 -
arch/blackfin/configs/BF526-EZBRD_defconfig | 158 -
arch/blackfin/configs/BF527-AD7160-EVAL_defconfig | 104 -
arch/blackfin/configs/BF527-EZKIT-V2_defconfig | 188 -
arch/blackfin/configs/BF527-EZKIT_defconfig | 181 -
arch/blackfin/configs/BF527-TLL6527M_defconfig | 178 -
arch/blackfin/configs/BF533-EZKIT_defconfig | 114 -
arch/blackfin/configs/BF533-STAMP_defconfig | 124 -
arch/blackfin/configs/BF537-STAMP_defconfig | 136 -
arch/blackfin/configs/BF538-EZKIT_defconfig | 133 -
arch/blackfin/configs/BF548-EZKIT_defconfig | 207 --
arch/blackfin/configs/BF561-ACVILON_defconfig | 149 -
arch/blackfin/configs/BF561-EZKIT-SMP_defconfig | 112 -
arch/blackfin/configs/BF561-EZKIT_defconfig | 114 -
arch/blackfin/configs/BF609-EZKIT_defconfig | 154 -
arch/blackfin/configs/BlackStamp_defconfig | 108 -
arch/blackfin/configs/CM-BF527_defconfig | 129 -
arch/blackfin/configs/CM-BF533_defconfig | 76 -
arch/blackfin/configs/CM-BF537E_defconfig | 107 -
arch/blackfin/configs/CM-BF537U_defconfig | 96 -
arch/blackfin/configs/CM-BF548_defconfig | 170 -
arch/blackfin/configs/CM-BF561_defconfig | 104 -
arch/blackfin/configs/DNP5370_defconfig | 118 -
arch/blackfin/configs/H8606_defconfig | 87 -
arch/blackfin/configs/IP0X_defconfig | 91 -
arch/blackfin/configs/PNAV-10_defconfig | 111 -
arch/blackfin/configs/SRV1_defconfig | 88 -
arch/blackfin/configs/TCM-BF518_defconfig | 131 -
arch/blackfin/configs/TCM-BF537_defconfig | 95 -
arch/blackfin/include/asm/Kbuild | 28 -
arch/blackfin/include/asm/asm-offsets.h | 1 -
arch/blackfin/include/asm/atomic.h | 47 -
arch/blackfin/include/asm/barrier.h | 86 -
arch/blackfin/include/asm/bfin-global.h | 95 -
arch/blackfin/include/asm/bfin-lq035q1.h | 40 -
arch/blackfin/include/asm/bfin5xx_spi.h | 86 -
arch/blackfin/include/asm/bfin_can.h | 728 ----
arch/blackfin/include/asm/bfin_dma.h | 165 -
arch/blackfin/include/asm/bfin_pfmon.h | 44 -
arch/blackfin/include/asm/bfin_ppi.h | 181 -
arch/blackfin/include/asm/bfin_sdh.h | 161 -
arch/blackfin/include/asm/bfin_serial.h | 429 ---
arch/blackfin/include/asm/bfin_simple_timer.h | 27 -
arch/blackfin/include/asm/bfin_sport.h | 71 -
arch/blackfin/include/asm/bfin_sport3.h | 107 -
arch/blackfin/include/asm/bfin_twi.h | 214 --
arch/blackfin/include/asm/bfin_watchdog.h | 30 -
arch/blackfin/include/asm/bfrom.h | 90 -
arch/blackfin/include/asm/bitops.h | 140 -
arch/blackfin/include/asm/blackfin.h | 88 -
arch/blackfin/include/asm/bug.h | 73 -
arch/blackfin/include/asm/cache.h | 70 -
arch/blackfin/include/asm/cacheflush.h | 118 -
arch/blackfin/include/asm/cdef_LPBlackfin.h | 309 --
arch/blackfin/include/asm/checksum.h | 44 -
arch/blackfin/include/asm/clocks.h | 74 -
arch/blackfin/include/asm/cmpxchg.h | 132 -
arch/blackfin/include/asm/context.S | 407 ---
arch/blackfin/include/asm/cplb.h | 153 -
arch/blackfin/include/asm/cplbinit.h | 66 -
arch/blackfin/include/asm/cpu.h | 24 -
arch/blackfin/include/asm/def_LPBlackfin.h | 697 ----
arch/blackfin/include/asm/delay.h | 51 -
arch/blackfin/include/asm/dma-mapping.h | 46 -
arch/blackfin/include/asm/dma.h | 349 --
arch/blackfin/include/asm/dpmc.h | 794 -----
arch/blackfin/include/asm/early_printk.h | 36 -
arch/blackfin/include/asm/elf.h | 135 -
arch/blackfin/include/asm/entry.h | 178 -
arch/blackfin/include/asm/exec.h | 1 -
arch/blackfin/include/asm/fixed_code.h | 30 -
arch/blackfin/include/asm/flat.h | 62 -
arch/blackfin/include/asm/ftrace.h | 73 -
arch/blackfin/include/asm/gpio.h | 234 --
arch/blackfin/include/asm/gptimers.h | 337 --
arch/blackfin/include/asm/hardirq.h | 17 -
arch/blackfin/include/asm/io.h | 49 -
arch/blackfin/include/asm/ipipe.h | 209 --
arch/blackfin/include/asm/ipipe_base.h | 75 -
arch/blackfin/include/asm/irq.h | 41 -
arch/blackfin/include/asm/irq_handler.h | 66 -
arch/blackfin/include/asm/irqflags.h | 289 --
arch/blackfin/include/asm/kgdb.h | 169 -
arch/blackfin/include/asm/l1layout.h | 37 -
arch/blackfin/include/asm/linkage.h | 13 -
arch/blackfin/include/asm/mem_init.h | 500 ---
arch/blackfin/include/asm/mem_map.h | 84 -
arch/blackfin/include/asm/mmu.h | 36 -
arch/blackfin/include/asm/mmu_context.h | 218 --
arch/blackfin/include/asm/module.h | 22 -
arch/blackfin/include/asm/nand.h | 40 -
arch/blackfin/include/asm/nmi.h | 14 -
arch/blackfin/include/asm/page.h | 22 -
arch/blackfin/include/asm/page_offset.h | 11 -
arch/blackfin/include/asm/pci.h | 13 -
arch/blackfin/include/asm/pda.h | 73 -
arch/blackfin/include/asm/perf_event.h | 1 -
arch/blackfin/include/asm/pgtable.h | 104 -
arch/blackfin/include/asm/pm.h | 31 -
arch/blackfin/include/asm/portmux.h | 1204 -------
arch/blackfin/include/asm/processor.h | 145 -
arch/blackfin/include/asm/pseudo_instructions.h | 18 -
arch/blackfin/include/asm/ptrace.h | 42 -
arch/blackfin/include/asm/reboot.h | 20 -
arch/blackfin/include/asm/rwlock.h | 7 -
arch/blackfin/include/asm/scb.h | 21 -
arch/blackfin/include/asm/sections.h | 67 -
arch/blackfin/include/asm/segment.h | 13 -
arch/blackfin/include/asm/smp.h | 54 -
arch/blackfin/include/asm/spinlock.h | 81 -
arch/blackfin/include/asm/spinlock_types.h | 28 -
arch/blackfin/include/asm/string.h | 38 -
arch/blackfin/include/asm/switch_to.h | 39 -
arch/blackfin/include/asm/syscall.h | 96 -
arch/blackfin/include/asm/thread_info.h | 98 -
arch/blackfin/include/asm/time.h | 46 -
arch/blackfin/include/asm/timex.h | 23 -
arch/blackfin/include/asm/tlb.h | 22 -
arch/blackfin/include/asm/tlbflush.h | 2 -
arch/blackfin/include/asm/trace.h | 106 -
arch/blackfin/include/asm/traps.h | 131 -
arch/blackfin/include/asm/uaccess.h | 234 --
arch/blackfin/include/asm/unistd.h | 22 -
arch/blackfin/include/asm/vga.h | 1 -
arch/blackfin/include/mach-common/irq.h | 58 -
arch/blackfin/include/mach-common/pll.h | 86 -
arch/blackfin/include/mach-common/ports-a.h | 26 -
arch/blackfin/include/mach-common/ports-b.h | 26 -
arch/blackfin/include/mach-common/ports-c.h | 26 -
arch/blackfin/include/mach-common/ports-d.h | 26 -
arch/blackfin/include/mach-common/ports-e.h | 26 -
arch/blackfin/include/mach-common/ports-f.h | 26 -
arch/blackfin/include/mach-common/ports-g.h | 26 -
arch/blackfin/include/mach-common/ports-h.h | 26 -
arch/blackfin/include/mach-common/ports-i.h | 26 -
arch/blackfin/include/mach-common/ports-j.h | 26 -
arch/blackfin/include/uapi/asm/Kbuild | 25 -
arch/blackfin/include/uapi/asm/bfin_sport.h | 137 -
arch/blackfin/include/uapi/asm/byteorder.h | 7 -
arch/blackfin/include/uapi/asm/cachectl.h | 21 -
arch/blackfin/include/uapi/asm/fcntl.h | 18 -
arch/blackfin/include/uapi/asm/fixed_code.h | 39 -
arch/blackfin/include/uapi/asm/ioctls.h | 8 -
arch/blackfin/include/uapi/asm/poll.h | 17 -
arch/blackfin/include/uapi/asm/posix_types.h | 31 -
arch/blackfin/include/uapi/asm/ptrace.h | 171 -
arch/blackfin/include/uapi/asm/sigcontext.h | 62 -
arch/blackfin/include/uapi/asm/siginfo.h | 16 -
arch/blackfin/include/uapi/asm/signal.h | 8 -
arch/blackfin/include/uapi/asm/stat.h | 70 -
arch/blackfin/include/uapi/asm/swab.h | 51 -
arch/blackfin/include/uapi/asm/unistd.h | 448 ---
arch/blackfin/kernel/.gitignore | 1 -
arch/blackfin/kernel/Makefile | 44 -
arch/blackfin/kernel/asm-offsets.c | 164 -
arch/blackfin/kernel/bfin_dma.c | 612 ----
arch/blackfin/kernel/bfin_gpio.c | 1208 -------
arch/blackfin/kernel/bfin_ksyms.c | 126 -
arch/blackfin/kernel/cplb-mpu/Makefile | 10 -
arch/blackfin/kernel/cplb-mpu/cplbinit.c | 102 -
arch/blackfin/kernel/cplb-mpu/cplbmgr.c | 379 ---
arch/blackfin/kernel/cplb-nompu/Makefile | 11 -
arch/blackfin/kernel/cplb-nompu/cplbinit.c | 212 --
arch/blackfin/kernel/cplb-nompu/cplbmgr.c | 227 --
arch/blackfin/kernel/cplbinfo.c | 180 -
arch/blackfin/kernel/debug-mmrs.c | 1891 ----------
arch/blackfin/kernel/dma-mapping.c | 172 -
arch/blackfin/kernel/dumpstack.c | 177 -
arch/blackfin/kernel/early_printk.c | 271 --
arch/blackfin/kernel/entry.S | 59 -
arch/blackfin/kernel/exception.c | 45 -
arch/blackfin/kernel/fixed_code.S | 155 -
arch/blackfin/kernel/flat.c | 84 -
arch/blackfin/kernel/ftrace-entry.S | 207 --
arch/blackfin/kernel/ftrace.c | 125 -
arch/blackfin/kernel/gptimers.c | 383 ---
arch/blackfin/kernel/ipipe.c | 397 ---
arch/blackfin/kernel/irqchip.c | 132 -
arch/blackfin/kernel/kgdb.c | 473 ---
arch/blackfin/kernel/kgdb_test.c | 114 -
arch/blackfin/kernel/module.c | 292 --
arch/blackfin/kernel/nmi.c | 287 --
arch/blackfin/kernel/perf_event.c | 482 ---
arch/blackfin/kernel/process.c | 438 ---
arch/blackfin/kernel/pseudodbg.c | 191 --
arch/blackfin/kernel/ptrace.c | 413 ---
arch/blackfin/kernel/reboot.c | 115 -
arch/blackfin/kernel/setup.c | 1468 --------
arch/blackfin/kernel/shadow_console.c | 111 -
arch/blackfin/kernel/signal.c | 287 --
arch/blackfin/kernel/stacktrace.c | 54 -
arch/blackfin/kernel/sys_bfin.c | 88 -
arch/blackfin/kernel/time-ts.c | 400 ---
arch/blackfin/kernel/time.c | 160 -
arch/blackfin/kernel/trace.c | 988 ------
arch/blackfin/kernel/traps.c | 585 ----
arch/blackfin/kernel/vmlinux.lds.S | 271 --
arch/blackfin/lib/Makefile | 12 -
arch/blackfin/lib/ashldi3.c | 35 -
arch/blackfin/lib/ashrdi3.c | 36 -
arch/blackfin/lib/divsi3.S | 199 --
arch/blackfin/lib/gcclib.h | 24 -
arch/blackfin/lib/ins.S | 118 -
arch/blackfin/lib/lshrdi3.c | 35 -
arch/blackfin/lib/memchr.S | 47 -
arch/blackfin/lib/memcmp.S | 92 -
arch/blackfin/lib/memcpy.S | 124 -
arch/blackfin/lib/memmove.S | 93 -
arch/blackfin/lib/memset.S | 87 -
arch/blackfin/lib/modsi3.S | 57 -
arch/blackfin/lib/muldi3.S | 74 -
arch/blackfin/lib/outs.S | 68 -
arch/blackfin/lib/smulsi3_highpart.S | 38 -
arch/blackfin/lib/strcmp.S | 43 -
arch/blackfin/lib/strcpy.S | 35 -
arch/blackfin/lib/strncmp.S | 52 -
arch/blackfin/lib/strncpy.S | 85 -
arch/blackfin/lib/udivsi3.S | 277 --
arch/blackfin/lib/umodsi3.S | 49 -
arch/blackfin/lib/umulsi3_highpart.S | 31 -
arch/blackfin/mach-bf518/Kconfig | 320 --
arch/blackfin/mach-bf518/Makefile | 5 -
arch/blackfin/mach-bf518/boards/Kconfig | 18 -
arch/blackfin/mach-bf518/boards/Makefile | 6 -
arch/blackfin/mach-bf518/boards/ezbrd.c | 794 -----
arch/blackfin/mach-bf518/boards/tcm-bf518.c | 739 ----
arch/blackfin/mach-bf518/dma.c | 98 -
arch/blackfin/mach-bf518/include/mach/anomaly.h | 170 -
arch/blackfin/mach-bf518/include/mach/bf518.h | 214 --
.../blackfin/mach-bf518/include/mach/bfin_serial.h | 14 -
arch/blackfin/mach-bf518/include/mach/blackfin.h | 43 -
arch/blackfin/mach-bf518/include/mach/cdefBF512.h | 1043 ------
arch/blackfin/mach-bf518/include/mach/cdefBF514.h | 80 -
arch/blackfin/mach-bf518/include/mach/cdefBF516.h | 178 -
arch/blackfin/mach-bf518/include/mach/cdefBF518.h | 56 -
arch/blackfin/mach-bf518/include/mach/defBF512.h | 1304 -------
arch/blackfin/mach-bf518/include/mach/defBF514.h | 48 -
arch/blackfin/mach-bf518/include/mach/defBF516.h | 392 ---
arch/blackfin/mach-bf518/include/mach/defBF518.h | 67 -
arch/blackfin/mach-bf518/include/mach/dma.h | 33 -
arch/blackfin/mach-bf518/include/mach/gpio.h | 62 -
arch/blackfin/mach-bf518/include/mach/irq.h | 205 --
arch/blackfin/mach-bf518/include/mach/mem_map.h | 70 -
arch/blackfin/mach-bf518/include/mach/pll.h | 1 -
arch/blackfin/mach-bf518/include/mach/portmux.h | 223 --
arch/blackfin/mach-bf518/ints-priority.c | 78 -
arch/blackfin/mach-bf527/Kconfig | 325 --
arch/blackfin/mach-bf527/Makefile | 5 -
arch/blackfin/mach-bf527/boards/Kconfig | 38 -
arch/blackfin/mach-bf527/boards/Makefile | 11 -
arch/blackfin/mach-bf527/boards/ad7160eval.c | 868 -----
arch/blackfin/mach-bf527/boards/cm_bf527.c | 992 ------
arch/blackfin/mach-bf527/boards/ezbrd.c | 891 -----
arch/blackfin/mach-bf527/boards/ezkit.c | 1335 --------
arch/blackfin/mach-bf527/boards/tll6527m.c | 946 -----
arch/blackfin/mach-bf527/dma.c | 98 -
arch/blackfin/mach-bf527/include/mach/anomaly.h | 290 --
arch/blackfin/mach-bf527/include/mach/bf527.h | 237 --
.../blackfin/mach-bf527/include/mach/bfin_serial.h | 14 -
arch/blackfin/mach-bf527/include/mach/blackfin.h | 37 -
arch/blackfin/mach-bf527/include/mach/cdefBF522.h | 1095 ------
arch/blackfin/mach-bf527/include/mach/cdefBF525.h | 421 ---
arch/blackfin/mach-bf527/include/mach/cdefBF527.h | 178 -
arch/blackfin/mach-bf527/include/mach/defBF522.h | 1309 -------
arch/blackfin/mach-bf527/include/mach/defBF525.h | 678 ----
arch/blackfin/mach-bf527/include/mach/defBF527.h | 391 ---
arch/blackfin/mach-bf527/include/mach/dma.h | 38 -
arch/blackfin/mach-bf527/include/mach/gpio.h | 69 -
arch/blackfin/mach-bf527/include/mach/irq.h | 204 --
arch/blackfin/mach-bf527/include/mach/mem_map.h | 70 -
arch/blackfin/mach-bf527/include/mach/pll.h | 1 -
arch/blackfin/mach-bf527/include/mach/portmux.h | 220 --
arch/blackfin/mach-bf527/ints-priority.c | 79 -
arch/blackfin/mach-bf533/Kconfig | 96 -
arch/blackfin/mach-bf533/Makefile | 5 -
arch/blackfin/mach-bf533/boards/H8606.c | 452 ---
arch/blackfin/mach-bf533/boards/Kconfig | 42 -
arch/blackfin/mach-bf533/boards/Makefile | 11 -
arch/blackfin/mach-bf533/boards/blackstamp.c | 523 ---
arch/blackfin/mach-bf533/boards/cm_bf533.c | 582 ----
arch/blackfin/mach-bf533/boards/ezkit.c | 551 ---
arch/blackfin/mach-bf533/boards/ip0x.c | 319 --
arch/blackfin/mach-bf533/boards/stamp.c | 919 -----
arch/blackfin/mach-bf533/dma.c | 78 -
arch/blackfin/mach-bf533/include/mach/anomaly.h | 383 ---
arch/blackfin/mach-bf533/include/mach/bf533.h | 138 -
.../blackfin/mach-bf533/include/mach/bfin_serial.h | 14 -
arch/blackfin/mach-bf533/include/mach/blackfin.h | 23 -
arch/blackfin/mach-bf533/include/mach/cdefBF532.h | 682 ----
arch/blackfin/mach-bf533/include/mach/defBF532.h | 831 -----
arch/blackfin/mach-bf533/include/mach/dma.h | 26 -
arch/blackfin/mach-bf533/include/mach/gpio.h | 33 -
arch/blackfin/mach-bf533/include/mach/irq.h | 92 -
arch/blackfin/mach-bf533/include/mach/mem_map.h | 139 -
arch/blackfin/mach-bf533/include/mach/pll.h | 1 -
arch/blackfin/mach-bf533/include/mach/portmux.h | 71 -
arch/blackfin/mach-bf533/ints-priority.c | 44 -
arch/blackfin/mach-bf537/Kconfig | 118 -
arch/blackfin/mach-bf537/Makefile | 5 -
arch/blackfin/mach-bf537/boards/Kconfig | 49 -
arch/blackfin/mach-bf537/boards/Makefile | 12 -
arch/blackfin/mach-bf537/boards/cm_bf537e.c | 945 -----
arch/blackfin/mach-bf537/boards/cm_bf537u.c | 802 -----
arch/blackfin/mach-bf537/boards/dnp5370.c | 413 ---
arch/blackfin/mach-bf537/boards/minotaur.c | 585 ----
arch/blackfin/mach-bf537/boards/pnav10.c | 538 ---
arch/blackfin/mach-bf537/boards/stamp.c | 3019 ----------------
arch/blackfin/mach-bf537/boards/tcm_bf537.c | 792 -----
arch/blackfin/mach-bf537/dma.c | 98 -
arch/blackfin/mach-bf537/include/mach/anomaly.h | 241 --
arch/blackfin/mach-bf537/include/mach/bf537.h | 108 -
.../blackfin/mach-bf537/include/mach/bfin_serial.h | 14 -
arch/blackfin/mach-bf537/include/mach/blackfin.h | 33 -
arch/blackfin/mach-bf537/include/mach/cdefBF534.h | 1736 ----------
arch/blackfin/mach-bf537/include/mach/cdefBF537.h | 178 -
arch/blackfin/mach-bf537/include/mach/defBF534.h | 1470 --------
arch/blackfin/mach-bf537/include/mach/defBF537.h | 377 --
arch/blackfin/mach-bf537/include/mach/dma.h | 31 -
arch/blackfin/mach-bf537/include/mach/gpio.h | 69 -
arch/blackfin/mach-bf537/include/mach/irq.h | 184 -
arch/blackfin/mach-bf537/include/mach/mem_map.h | 147 -
arch/blackfin/mach-bf537/include/mach/pll.h | 1 -
arch/blackfin/mach-bf537/include/mach/portmux.h | 152 -
arch/blackfin/mach-bf537/ints-priority.c | 214 --
arch/blackfin/mach-bf538/Kconfig | 166 -
arch/blackfin/mach-bf538/Makefile | 6 -
arch/blackfin/mach-bf538/boards/Kconfig | 13 -
arch/blackfin/mach-bf538/boards/Makefile | 5 -
arch/blackfin/mach-bf538/boards/ezkit.c | 987 ------
arch/blackfin/mach-bf538/dma.c | 141 -
arch/blackfin/mach-bf538/ext-gpio.c | 158 -
arch/blackfin/mach-bf538/include/mach/anomaly.h | 215 --
arch/blackfin/mach-bf538/include/mach/bf538.h | 103 -
.../blackfin/mach-bf538/include/mach/bfin_serial.h | 14 -
arch/blackfin/mach-bf538/include/mach/blackfin.h | 33 -
arch/blackfin/mach-bf538/include/mach/cdefBF538.h | 1960 -----------
arch/blackfin/mach-bf538/include/mach/cdefBF539.h | 240 --
arch/blackfin/mach-bf538/include/mach/defBF538.h | 1749 ----------
arch/blackfin/mach-bf538/include/mach/defBF539.h | 152 -
arch/blackfin/mach-bf538/include/mach/dma.h | 41 -
arch/blackfin/mach-bf538/include/mach/gpio.h | 81 -
arch/blackfin/mach-bf538/include/mach/irq.h | 148 -
arch/blackfin/mach-bf538/include/mach/mem_map.h | 74 -
arch/blackfin/mach-bf538/include/mach/pll.h | 1 -
arch/blackfin/mach-bf538/include/mach/portmux.h | 114 -
arch/blackfin/mach-bf538/ints-priority.c | 73 -
arch/blackfin/mach-bf548/Kconfig | 383 ---
arch/blackfin/mach-bf548/Makefile | 5 -
arch/blackfin/mach-bf548/boards/Kconfig | 19 -
arch/blackfin/mach-bf548/boards/Makefile | 6 -
arch/blackfin/mach-bf548/boards/cm_bf548.c | 1268 -------
arch/blackfin/mach-bf548/boards/ezkit.c | 2199 ------------
arch/blackfin/mach-bf548/dma.c | 139 -
arch/blackfin/mach-bf548/include/mach/anomaly.h | 301 --
arch/blackfin/mach-bf548/include/mach/bf548.h | 105 -
.../blackfin/mach-bf548/include/mach/bf54x-lq043.h | 36 -
arch/blackfin/mach-bf548/include/mach/bf54x_keys.h | 23 -
.../blackfin/mach-bf548/include/mach/bfin_serial.h | 16 -
arch/blackfin/mach-bf548/include/mach/blackfin.h | 49 -
arch/blackfin/mach-bf548/include/mach/cdefBF542.h | 554 ---
arch/blackfin/mach-bf548/include/mach/cdefBF544.h | 913 -----
arch/blackfin/mach-bf548/include/mach/cdefBF547.h | 796 -----
arch/blackfin/mach-bf548/include/mach/cdefBF548.h | 761 -----
arch/blackfin/mach-bf548/include/mach/cdefBF549.h | 302 --
.../mach-bf548/include/mach/cdefBF54x_base.h | 2633 --------------
arch/blackfin/mach-bf548/include/mach/defBF542.h | 763 -----
arch/blackfin/mach-bf548/include/mach/defBF544.h | 630 ----
arch/blackfin/mach-bf548/include/mach/defBF547.h | 1034 ------
arch/blackfin/mach-bf548/include/mach/defBF548.h | 399 ---
arch/blackfin/mach-bf548/include/mach/defBF549.h | 186 -
.../mach-bf548/include/mach/defBF54x_base.h | 2294 -------------
arch/blackfin/mach-bf548/include/mach/dma.h | 72 -
arch/blackfin/mach-bf548/include/mach/gpio.h | 210 --
arch/blackfin/mach-bf548/include/mach/irq.h | 454 ---
arch/blackfin/mach-bf548/include/mach/mem_map.h | 84 -
arch/blackfin/mach-bf548/include/mach/pll.h | 1 -
arch/blackfin/mach-bf548/include/mach/portmux.h | 318 --
arch/blackfin/mach-bf548/ints-priority.c | 116 -
arch/blackfin/mach-bf561/Kconfig | 213 --
arch/blackfin/mach-bf561/Makefile | 9 -
arch/blackfin/mach-bf561/atomic.S | 945 -----
arch/blackfin/mach-bf561/boards/Kconfig | 30 -
arch/blackfin/mach-bf561/boards/Makefile | 8 -
arch/blackfin/mach-bf561/boards/acvilon.c | 543 ---
arch/blackfin/mach-bf561/boards/cm_bf561.c | 556 ---
arch/blackfin/mach-bf561/boards/ezkit.c | 688 ----
arch/blackfin/mach-bf561/boards/tepla.c | 162 -
arch/blackfin/mach-bf561/coreb.c | 64 -
arch/blackfin/mach-bf561/dma.c | 114 -
arch/blackfin/mach-bf561/hotplug.c | 40 -
arch/blackfin/mach-bf561/include/mach/anomaly.h | 353 --
arch/blackfin/mach-bf561/include/mach/bf561.h | 200 --
.../blackfin/mach-bf561/include/mach/bfin_serial.h | 14 -
arch/blackfin/mach-bf561/include/mach/blackfin.h | 41 -
arch/blackfin/mach-bf561/include/mach/cdefBF561.h | 1460 --------
arch/blackfin/mach-bf561/include/mach/defBF561.h | 1402 --------
arch/blackfin/mach-bf561/include/mach/dma.h | 39 -
arch/blackfin/mach-bf561/include/mach/gpio.h | 67 -
arch/blackfin/mach-bf561/include/mach/irq.h | 236 --
arch/blackfin/mach-bf561/include/mach/mem_map.h | 219 --
arch/blackfin/mach-bf561/include/mach/pll.h | 56 -
arch/blackfin/mach-bf561/include/mach/portmux.h | 97 -
arch/blackfin/mach-bf561/include/mach/smp.h | 32 -
arch/blackfin/mach-bf561/ints-priority.c | 87 -
arch/blackfin/mach-bf561/secondary.S | 192 --
arch/blackfin/mach-bf561/smp.c | 172 -
arch/blackfin/mach-bf609/Kconfig | 1684 ---------
arch/blackfin/mach-bf609/Makefile | 7 -
arch/blackfin/mach-bf609/boards/Kconfig | 13 -
arch/blackfin/mach-bf609/boards/Makefile | 5 -
arch/blackfin/mach-bf609/boards/ezkit.c | 2191 ------------
arch/blackfin/mach-bf609/clock.c | 409 ---
arch/blackfin/mach-bf609/dma.c | 202 --
arch/blackfin/mach-bf609/dpm.S | 158 -
arch/blackfin/mach-bf609/include/mach/anomaly.h | 137 -
arch/blackfin/mach-bf609/include/mach/bf609.h | 93 -
.../blackfin/mach-bf609/include/mach/bfin_serial.h | 17 -
arch/blackfin/mach-bf609/include/mach/blackfin.h | 25 -
arch/blackfin/mach-bf609/include/mach/cdefBF609.h | 15 -
.../mach-bf609/include/mach/cdefBF60x_base.h | 3254 ------------------
arch/blackfin/mach-bf609/include/mach/defBF609.h | 286 --
.../mach-bf609/include/mach/defBF60x_base.h | 3596 --------------------
arch/blackfin/mach-bf609/include/mach/dma.h | 116 -
arch/blackfin/mach-bf609/include/mach/gpio.h | 165 -
arch/blackfin/mach-bf609/include/mach/irq.h | 319 --
arch/blackfin/mach-bf609/include/mach/mem_map.h | 86 -
arch/blackfin/mach-bf609/include/mach/pll.h | 1 -
arch/blackfin/mach-bf609/include/mach/pm.h | 25 -
arch/blackfin/mach-bf609/include/mach/portmux.h | 349 --
arch/blackfin/mach-bf609/ints-priority.c | 156 -
arch/blackfin/mach-bf609/pm.c | 361 --
arch/blackfin/mach-bf609/scb.c | 363 --
arch/blackfin/mach-common/Makefile | 17 -
arch/blackfin/mach-common/arch_checks.c | 66 -
arch/blackfin/mach-common/cache-c.c | 85 -
arch/blackfin/mach-common/cache.S | 124 -
arch/blackfin/mach-common/clock.h | 28 -
arch/blackfin/mach-common/clocks-init.c | 121 -
arch/blackfin/mach-common/dpmc.c | 164 -
arch/blackfin/mach-common/dpmc_modes.S | 320 --
arch/blackfin/mach-common/entry.S | 1711 ----------
arch/blackfin/mach-common/head.S | 229 --
arch/blackfin/mach-common/interrupt.S | 326 --
arch/blackfin/mach-common/ints-priority.c | 1366 --------
arch/blackfin/mach-common/pm.c | 301 --
arch/blackfin/mach-common/scb-init.c | 52 -
arch/blackfin/mach-common/smp.c | 432 ---
arch/blackfin/mm/Makefile | 5 -
arch/blackfin/mm/blackfin_sram.h | 14 -
arch/blackfin/mm/init.c | 122 -
arch/blackfin/mm/isram-driver.c | 411 ---
arch/blackfin/mm/maccess.c | 97 -
arch/blackfin/mm/sram-alloc.c | 899 -----
arch/blackfin/oprofile/Makefile | 14 -
arch/blackfin/oprofile/bfin_oprofile.c | 18 -
fs/Kconfig.binfmt | 2 +-
include/linux/cpuhotplug.h | 1 -
include/uapi/asm-generic/siginfo.h | 29 +-
include/uapi/linux/elf-em.h | 1 -
init/Kconfig | 2 +-
lib/Kconfig.debug | 2 +-
lib/test_user_copy.c | 1 -
469 files changed, 5 insertions(+), 123672 deletions(-)
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delete mode 100644 arch/blackfin/mach-bf537/Makefile
delete mode 100644 arch/blackfin/mach-bf537/boards/Kconfig
delete mode 100644 arch/blackfin/mach-bf537/boards/Makefile
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delete mode 100644 arch/blackfin/mach-bf537/include/mach/cdefBF537.h
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delete mode 100644 arch/blackfin/mach-bf538/boards/Makefile
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delete mode 100644 arch/blackfin/mach-bf538/include/mach/defBF538.h
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delete mode 100644 arch/blackfin/mach-bf548/include/mach/cdefBF548.h
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delete mode 100644 arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
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delete mode 100644 arch/blackfin/mach-bf561/Kconfig
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delete mode 100644 arch/blackfin/mach-bf561/include/mach/cdefBF561.h
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delete mode 100644 arch/blackfin/mach-bf561/ints-priority.c
delete mode 100644 arch/blackfin/mach-bf561/secondary.S
delete mode 100644 arch/blackfin/mach-bf561/smp.c
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delete mode 100644 arch/blackfin/mach-bf609/Makefile
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delete mode 100644 arch/blackfin/mach-bf609/include/mach/bfin_serial.h
delete mode 100644 arch/blackfin/mach-bf609/include/mach/blackfin.h
delete mode 100644 arch/blackfin/mach-bf609/include/mach/cdefBF609.h
delete mode 100644 arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
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delete mode 100644 arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
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delete mode 100644 arch/blackfin/mach-common/arch_checks.c
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delete mode 100644 arch/blackfin/mach-common/clock.h
delete mode 100644 arch/blackfin/mach-common/clocks-init.c
delete mode 100644 arch/blackfin/mach-common/dpmc.c
delete mode 100644 arch/blackfin/mach-common/dpmc_modes.S
delete mode 100644 arch/blackfin/mach-common/entry.S
delete mode 100644 arch/blackfin/mach-common/head.S
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delete mode 100644 arch/blackfin/mach-common/ints-priority.c
delete mode 100644 arch/blackfin/mach-common/pm.c
delete mode 100644 arch/blackfin/mach-common/scb-init.c
delete mode 100644 arch/blackfin/mach-common/smp.c
delete mode 100644 arch/blackfin/mm/Makefile
delete mode 100644 arch/blackfin/mm/blackfin_sram.h
delete mode 100644 arch/blackfin/mm/init.c
delete mode 100644 arch/blackfin/mm/isram-driver.c
delete mode 100644 arch/blackfin/mm/maccess.c
delete mode 100644 arch/blackfin/mm/sram-alloc.c
delete mode 100644 arch/blackfin/oprofile/Makefile
delete mode 100644 arch/blackfin/oprofile/bfin_oprofile.c
diff --git a/arch/blackfin/Clear_BSD.txt b/arch/blackfin/Clear_BSD.txt
deleted file mode 100644
index bfa4b37..0000000
--- a/arch/blackfin/Clear_BSD.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-The Clear BSD license:
-
-Copyright (c) 2012, Analog Devices, Inc. All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted (subject to the limitations in the
-disclaimer below) provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the
- distribution.
-
-* Neither the name of Analog Devices, Inc. nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
-NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
deleted file mode 100644
index d9c2866..0000000
--- a/arch/blackfin/Kconfig
+++ /dev/null
@@ -1,1463 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config MMU
- def_bool n
-
-config FPU
- def_bool n
-
-config RWSEM_GENERIC_SPINLOCK
- def_bool y
-
-config RWSEM_XCHGADD_ALGORITHM
- def_bool n
-
-config BLACKFIN
- def_bool y
- select HAVE_ARCH_KGDB
- select HAVE_ARCH_TRACEHOOK
- select HAVE_DYNAMIC_FTRACE
- select HAVE_FTRACE_MCOUNT_RECORD
- select HAVE_FUNCTION_GRAPH_TRACER
- select HAVE_FUNCTION_TRACER
- select HAVE_IDE
- select HAVE_KERNEL_GZIP if RAMKERNEL
- select HAVE_KERNEL_BZIP2 if RAMKERNEL
- select HAVE_KERNEL_LZMA if RAMKERNEL
- select HAVE_KERNEL_LZO if RAMKERNEL
- select HAVE_OPROFILE
- select HAVE_PERF_EVENTS
- select ARCH_HAVE_CUSTOM_GPIO_H
- select GPIOLIB
- select HAVE_UID16
- select HAVE_UNDERSCORE_SYMBOL_PREFIX
- select VIRT_TO_BUS
- select ARCH_WANT_IPC_PARSE_VERSION
- select GENERIC_ATOMIC64
- select GENERIC_IRQ_PROBE
- select GENERIC_IRQ_SHOW
- select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
- select GENERIC_SMP_IDLE_THREAD
- select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
- select HAVE_MOD_ARCH_SPECIFIC
- select MODULES_USE_ELF_RELA
- select HAVE_DEBUG_STACKOVERFLOW
- select HAVE_NMI
- select ARCH_NO_COHERENT_DMA_MMAP
-
-config GENERIC_CSUM
- def_bool y
-
-config GENERIC_BUG
- def_bool y
- depends on BUG
-
-config ZONE_DMA
- def_bool y
-
-config FORCE_MAX_ZONEORDER
- int
- default "14"
-
-config GENERIC_CALIBRATE_DELAY
- def_bool y
-
-config LOCKDEP_SUPPORT
- def_bool y
-
-config STACKTRACE_SUPPORT
- def_bool y
-
-config TRACE_IRQFLAGS_SUPPORT
- def_bool y
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.preempt"
-
-source "kernel/Kconfig.freezer"
-
-menu "Blackfin Processor Options"
-
-comment "Processor and Board Settings"
-
-choice
- prompt "CPU"
- default BF533
-
-config BF512
- bool "BF512"
- help
- BF512 Processor Support.
-
-config BF514
- bool "BF514"
- help
- BF514 Processor Support.
-
-config BF516
- bool "BF516"
- help
- BF516 Processor Support.
-
-config BF518
- bool "BF518"
- help
- BF518 Processor Support.
-
-config BF522
- bool "BF522"
- help
- BF522 Processor Support.
-
-config BF523
- bool "BF523"
- help
- BF523 Processor Support.
-
-config BF524
- bool "BF524"
- help
- BF524 Processor Support.
-
-config BF525
- bool "BF525"
- help
- BF525 Processor Support.
-
-config BF526
- bool "BF526"
- help
- BF526 Processor Support.
-
-config BF527
- bool "BF527"
- help
- BF527 Processor Support.
-
-config BF531
- bool "BF531"
- help
- BF531 Processor Support.
-
-config BF532
- bool "BF532"
- help
- BF532 Processor Support.
-
-config BF533
- bool "BF533"
- help
- BF533 Processor Support.
-
-config BF534
- bool "BF534"
- help
- BF534 Processor Support.
-
-config BF536
- bool "BF536"
- help
- BF536 Processor Support.
-
-config BF537
- bool "BF537"
- help
- BF537 Processor Support.
-
-config BF538
- bool "BF538"
- help
- BF538 Processor Support.
-
-config BF539
- bool "BF539"
- help
- BF539 Processor Support.
-
-config BF542_std
- bool "BF542"
- help
- BF542 Processor Support.
-
-config BF542M
- bool "BF542m"
- help
- BF542 Processor Support.
-
-config BF544_std
- bool "BF544"
- help
- BF544 Processor Support.
-
-config BF544M
- bool "BF544m"
- help
- BF544 Processor Support.
-
-config BF547_std
- bool "BF547"
- help
- BF547 Processor Support.
-
-config BF547M
- bool "BF547m"
- help
- BF547 Processor Support.
-
-config BF548_std
- bool "BF548"
- help
- BF548 Processor Support.
-
-config BF548M
- bool "BF548m"
- help
- BF548 Processor Support.
-
-config BF549_std
- bool "BF549"
- help
- BF549 Processor Support.
-
-config BF549M
- bool "BF549m"
- help
- BF549 Processor Support.
-
-config BF561
- bool "BF561"
- help
- BF561 Processor Support.
-
-config BF609
- bool "BF609"
- select CLKDEV_LOOKUP
- help
- BF609 Processor Support.
-
-endchoice
-
-config SMP
- depends on BF561
- select TICKSOURCE_CORETMR
- bool "Symmetric multi-processing support"
- ---help---
- This enables support for systems with more than one CPU,
- like the dual core BF561. If you have a system with only one
- CPU, say N. If you have a system with more than one CPU, say Y.
-
- If you don't know what to do here, say N.
-
-config NR_CPUS
- int
- depends on SMP
- default 2 if BF561
-
-config HOTPLUG_CPU
- bool "Support for hot-pluggable CPUs"
- depends on SMP
- default y
-
-config BF_REV_MIN
- int
- default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
- default 2 if (BF537 || BF536 || BF534)
- default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
- default 4 if (BF538 || BF539)
-
-config BF_REV_MAX
- int
- default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
- default 3 if (BF537 || BF536 || BF534 || BF54xM)
- default 5 if (BF561 || BF538 || BF539)
- default 6 if (BF533 || BF532 || BF531)
-
-choice
- prompt "Silicon Rev"
- default BF_REV_0_0 if (BF51x || BF52x || BF60x)
- default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
- default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
-
-config BF_REV_0_0
- bool "0.0"
- depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
-
-config BF_REV_0_1
- bool "0.1"
- depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
-
-config BF_REV_0_2
- bool "0.2"
- depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
-
-config BF_REV_0_3
- bool "0.3"
- depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
-
-config BF_REV_0_4
- bool "0.4"
- depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
-
-config BF_REV_0_5
- bool "0.5"
- depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
-
-config BF_REV_0_6
- bool "0.6"
- depends on (BF533 || BF532 || BF531)
-
-config BF_REV_ANY
- bool "any"
-
-config BF_REV_NONE
- bool "none"
-
-endchoice
-
-config BF53x
- bool
- depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
- default y
-
-config GPIO_ADI
- def_bool y
- depends on !PINCTRL
- depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
-
-config PINCTRL_BLACKFIN_ADI2
- def_bool y
- depends on (BF54x || BF60x)
- select PINCTRL
- select PINCTRL_ADI2
-
-config MEM_MT48LC64M4A2FB_7E
- bool
- depends on (BFIN533_STAMP)
- default y
-
-config MEM_MT48LC16M16A2TG_75
- bool
- depends on (BFIN533_EZKIT || BFIN561_EZKIT \
- || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
- || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
- || BFIN527_BLUETECHNIX_CM)
- default y
-
-config MEM_MT48LC32M8A2_75
- bool
- depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
- default y
-
-config MEM_MT48LC8M32B2B5_7
- bool
- depends on (BFIN561_BLUETECHNIX_CM)
- default y
-
-config MEM_MT48LC32M16A2TG_75
- bool
- depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
- default y
-
-config MEM_MT48H32M16LFCJ_75
- bool
- depends on (BFIN526_EZBRD)
- default y
-
-config MEM_MT47H64M16
- bool
- depends on (BFIN609_EZKIT)
- default y
-
-source "arch/blackfin/mach-bf518/Kconfig"
-source "arch/blackfin/mach-bf527/Kconfig"
-source "arch/blackfin/mach-bf533/Kconfig"
-source "arch/blackfin/mach-bf561/Kconfig"
-source "arch/blackfin/mach-bf537/Kconfig"
-source "arch/blackfin/mach-bf538/Kconfig"
-source "arch/blackfin/mach-bf548/Kconfig"
-source "arch/blackfin/mach-bf609/Kconfig"
-
-menu "Board customizations"
-
-config CMDLINE_BOOL
- bool "Default bootloader kernel arguments"
-
-config CMDLINE
- string "Initial kernel command string"
- depends on CMDLINE_BOOL
- default "console=ttyBF0,57600"
- help
- If you don't have a boot loader capable of passing a command line string
- to the kernel, you may specify one here. As a minimum, you should specify
- the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
-
-config BOOT_LOAD
- hex "Kernel load address for booting"
- default "0x1000"
- range 0x1000 0x20000000
- help
- This option allows you to set the load address of the kernel.
- This can be useful if you are on a board which has a small amount
- of memory or you wish to reserve some memory at the beginning of
- the address space.
-
- Note that you need to keep this value above 4k (0x1000) as this
- memory region is used to capture NULL pointer references as well
- as some core kernel functions.
-
-config PHY_RAM_BASE_ADDRESS
- hex "Physical RAM Base"
- default 0x0
- help
- set BF609 FPGA physical SRAM base address
-
-config ROM_BASE
- hex "Kernel ROM Base"
- depends on ROMKERNEL
- default "0x20040040"
- range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
- range 0x20000000 0x30000000 if (BF54x || BF561)
- range 0xB0000000 0xC0000000 if (BF60x)
- help
- Make sure your ROM base does not include any file-header
- information that is prepended to the kernel.
-
- For example, the bootable U-Boot format (created with
- mkimage) has a 64 byte header (0x40). So while the image
- you write to flash might start at say 0x20080000, you have
- to add 0x40 to get the kernel's ROM base as it will come
- after the header.
-
-comment "Clock/PLL Setup"
-
-config CLKIN_HZ
- int "Frequency of the crystal on the board in Hz"
- default "10000000" if BFIN532_IP0X
- default "11059200" if BFIN533_STAMP
- default "24576000" if PNAV10
- default "25000000" # most people use this
- default "27000000" if BFIN533_EZKIT
- default "30000000" if BFIN561_EZKIT
- default "24000000" if BFIN527_AD7160EVAL
- help
- The frequency of CLKIN crystal oscillator on the board in Hz.
- Warning: This value should match the crystal on the board. Otherwise,
- peripherals won't work properly.
-
-config BFIN_KERNEL_CLOCK
- bool "Re-program Clocks while Kernel boots?"
- default n
- help
- This option decides if kernel clocks are re-programed from the
- bootloader settings. If the clocks are not set, the SDRAM settings
- are also not changed, and the Bootloader does 100% of the hardware
- configuration.
-
-config PLL_BYPASS
- bool "Bypass PLL"
- depends on BFIN_KERNEL_CLOCK && (!BF60x)
- default n
-
-config CLKIN_HALF
- bool "Half Clock In"
- depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
- default n
- help
- If this is set the clock will be divided by 2, before it goes to the PLL.
-
-config VCO_MULT
- int "VCO Multiplier"
- depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
- range 1 64
- default "22" if BFIN533_EZKIT
- default "45" if BFIN533_STAMP
- default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
- default "22" if BFIN533_BLUETECHNIX_CM
- default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
- default "20" if (BFIN561_EZKIT || BF609)
- default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
- default "25" if BFIN527_AD7160EVAL
- help
- This controls the frequency of the on-chip PLL. This can be between 1 and 64.
- PLL Frequency = (Crystal Frequency) * (this setting)
-
-choice
- prompt "Core Clock Divider"
- depends on BFIN_KERNEL_CLOCK
- default CCLK_DIV_1
- help
- This sets the frequency of the core. It can be 1, 2, 4 or 8
- Core Frequency = (PLL frequency) / (this setting)
-
-config CCLK_DIV_1
- bool "1"
-
-config CCLK_DIV_2
- bool "2"
-
-config CCLK_DIV_4
- bool "4"
-
-config CCLK_DIV_8
- bool "8"
-endchoice
-
-config SCLK_DIV
- int "System Clock Divider"
- depends on BFIN_KERNEL_CLOCK
- range 1 15
- default 4
- help
- This sets the frequency of the system clock (including SDRAM or DDR) on
- !BF60x else it set the clock for system buses and provides the
- source from which SCLK0 and SCLK1 are derived.
- This can be between 1 and 15
- System Clock = (PLL frequency) / (this setting)
-
-config SCLK0_DIV
- int "System Clock0 Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 1
- help
- This sets the frequency of the system clock0 for PVP and all other
- peripherals not clocked by SCLK1.
- This can be between 1 and 15
- System Clock0 = (System Clock) / (this setting)
-
-config SCLK1_DIV
- int "System Clock1 Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 1
- help
- This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
- This can be between 1 and 15
- System Clock1 = (System Clock) / (this setting)
-
-config DCLK_DIV
- int "DDR Clock Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 2
- help
- This sets the frequency of the DDR memory.
- This can be between 1 and 15
- DDR Clock = (PLL frequency) / (this setting)
-
-choice
- prompt "DDR SDRAM Chip Type"
- depends on BFIN_KERNEL_CLOCK
- depends on BF54x
- default MEM_MT46V32M16_5B
-
-config MEM_MT46V32M16_6T
- bool "MT46V32M16_6T"
-
-config MEM_MT46V32M16_5B
- bool "MT46V32M16_5B"
-endchoice
-
-choice
- prompt "DDR/SDRAM Timing"
- depends on BFIN_KERNEL_CLOCK && !BF60x
- default BFIN_KERNEL_CLOCK_MEMINIT_CALC
- help
- This option allows you to specify Blackfin SDRAM/DDR Timing parameters
- The calculated SDRAM timing parameters may not be 100%
- accurate - This option is therefore marked experimental.
-
-config BFIN_KERNEL_CLOCK_MEMINIT_CALC
- bool "Calculate Timings"
-
-config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
- bool "Provide accurate Timings based on target SCLK"
- help
- Please consult the Blackfin Hardware Reference Manuals as well
- as the memory device datasheet.
- http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
-endchoice
-
-menu "Memory Init Control"
- depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
-
-config MEM_DDRCTL0
- depends on BF54x
- hex "DDRCTL0"
- default 0x0
-
-config MEM_DDRCTL1
- depends on BF54x
- hex "DDRCTL1"
- default 0x0
-
-config MEM_DDRCTL2
- depends on BF54x
- hex "DDRCTL2"
- default 0x0
-
-config MEM_EBIU_DDRQUE
- depends on BF54x
- hex "DDRQUE"
- default 0x0
-
-config MEM_SDRRC
- depends on !BF54x
- hex "SDRRC"
- default 0x0
-
-config MEM_SDGCTL
- depends on !BF54x
- hex "SDGCTL"
- default 0x0
-endmenu
-
-#
-# Max & Min Speeds for various Chips
-#
-config MAX_VCO_HZ
- int
- default 400000000 if BF512
- default 400000000 if BF514
- default 400000000 if BF516
- default 400000000 if BF518
- default 400000000 if BF522
- default 600000000 if BF523
- default 400000000 if BF524
- default 600000000 if BF525
- default 400000000 if BF526
- default 600000000 if BF527
- default 400000000 if BF531
- default 400000000 if BF532
- default 750000000 if BF533
- default 500000000 if BF534
- default 400000000 if BF536
- default 600000000 if BF537
- default 533333333 if BF538
- default 533333333 if BF539
- default 600000000 if BF542
- default 533333333 if BF544
- default 600000000 if BF547
- default 600000000 if BF548
- default 533333333 if BF549
- default 600000000 if BF561
- default 800000000 if BF609
-
-config MIN_VCO_HZ
- int
- default 50000000
-
-config MAX_SCLK_HZ
- int
- default 200000000 if BF609
- default 133333333
-
-config MIN_SCLK_HZ
- int
- default 27000000
-
-comment "Kernel Timer/Scheduler"
-
-source kernel/Kconfig.hz
-
-config SET_GENERIC_CLOCKEVENTS
- bool "Generic clock events"
- default y
- select GENERIC_CLOCKEVENTS
-
-menu "Clock event device"
- depends on GENERIC_CLOCKEVENTS
-config TICKSOURCE_GPTMR0
- bool "GPTimer0"
- depends on !SMP
- select BFIN_GPTIMERS
-
-config TICKSOURCE_CORETMR
- bool "Core timer"
- default y
-endmenu
-
-menu "Clock source"
- depends on GENERIC_CLOCKEVENTS
-config CYCLES_CLOCKSOURCE
- bool "CYCLES"
- default y
- depends on !BFIN_SCRATCH_REG_CYCLES
- depends on !SMP
- help
- If you say Y here, you will enable support for using the 'cycles'
- registers as a clock source. Doing so means you will be unable to
- safely write to the 'cycles' register during runtime. You will
- still be able to read it (such as for performance monitoring), but
- writing the registers will most likely crash the kernel.
-
-config GPTMR0_CLOCKSOURCE
- bool "GPTimer0"
- select BFIN_GPTIMERS
- depends on !TICKSOURCE_GPTMR0
-endmenu
-
-comment "Misc"
-
-choice
- prompt "Blackfin Exception Scratch Register"
- default BFIN_SCRATCH_REG_RETN
- help
- Select the resource to reserve for the Exception handler:
- - RETN: Non-Maskable Interrupt (NMI)
- - RETE: Exception Return (JTAG/ICE)
- - CYCLES: Performance counter
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_RETN
- bool "RETN"
- help
- Use the RETN register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use NMI on the Blackfin while running Linux, but
- you can debug the system with a JTAG ICE and use the
- CYCLES performance registers.
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_RETE
- bool "RETE"
- help
- Use the RETE register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use a JTAG ICE while debugging a Blackfin board,
- but you can safely use the CYCLES performance registers
- and the NMI.
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_CYCLES
- bool "CYCLES"
- help
- Use the CYCLES register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use the CYCLES performance registers on a Blackfin
- board at anytime, but you can debug the system with a JTAG
- ICE and use the NMI.
-
- If you are unsure, please select "RETN".
-
-endchoice
-
-endmenu
-
-
-menu "Blackfin Kernel Optimizations"
-
-comment "Memory Optimizations"
-
-config I_ENTRY_L1
- bool "Locate interrupt entry code in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
- into L1 instruction memory. (less latency)
-
-config EXCPT_IRQ_SYSC_L1
- bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the entire ASM lowlevel exception and interrupt entry code
- (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
- (less latency)
-
-config DO_IRQ_L1
- bool "Locate frequently called do_irq dispatcher function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called do_irq dispatcher function is linked
- into L1 instruction memory. (less latency)
-
-config CORE_TIMER_IRQ_L1
- bool "Locate frequently called timer_interrupt() function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called timer_interrupt() function is linked
- into L1 instruction memory. (less latency)
-
-config IDLE_L1
- bool "Locate frequently idle function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called idle function is linked
- into L1 instruction memory. (less latency)
-
-config SCHEDULE_L1
- bool "Locate kernel schedule function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called kernel schedule is linked
- into L1 instruction memory. (less latency)
-
-config ARITHMETIC_OPS_L1
- bool "Locate kernel owned arithmetic functions in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, arithmetic functions are linked
- into L1 instruction memory. (less latency)
-
-config ACCESS_OK_L1
- bool "Locate access_ok function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the access_ok function is linked
- into L1 instruction memory. (less latency)
-
-config MEMSET_L1
- bool "Locate memset function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the memset function is linked
- into L1 instruction memory. (less latency)
-
-config MEMCPY_L1
- bool "Locate memcpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the memcpy function is linked
- into L1 instruction memory. (less latency)
-
-config STRCMP_L1
- bool "locate strcmp function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strcmp function is linked
- into L1 instruction memory (less latency).
-
-config STRNCMP_L1
- bool "locate strncmp function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strncmp function is linked
- into L1 instruction memory (less latency).
-
-config STRCPY_L1
- bool "locate strcpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strcpy function is linked
- into L1 instruction memory (less latency).
-
-config STRNCPY_L1
- bool "locate strncpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strncpy function is linked
- into L1 instruction memory (less latency).
-
-config SYS_BFIN_SPINLOCK_L1
- bool "Locate sys_bfin_spinlock function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, sys_bfin_spinlock function is linked
- into L1 instruction memory. (less latency)
-
-config CACHELINE_ALIGNED_L1
- bool "Locate cacheline_aligned data to L1 Data Memory"
- default y if !BF54x
- default n if BF54x
- depends on !SMP && !BF531 && !CRC32
- help
- If enabled, cacheline_aligned data is linked
- into L1 data memory. (less latency)
-
-config SYSCALL_TAB_L1
- bool "Locate Syscall Table L1 Data Memory"
- default n
- depends on !SMP && !BF531
- help
- If enabled, the Syscall LUT is linked
- into L1 data memory. (less latency)
-
-config CPLB_SWITCH_TAB_L1
- bool "Locate CPLB Switch Tables L1 Data Memory"
- default n
- depends on !SMP && !BF531
- help
- If enabled, the CPLB Switch Tables are linked
- into L1 data memory. (less latency)
-
-config ICACHE_FLUSH_L1
- bool "Locate icache flush funcs in L1 Inst Memory"
- default y
- help
- If enabled, the Blackfin icache flushing functions are linked
- into L1 instruction memory.
-
- Note that this might be required to address anomalies, but
- these functions are pretty small, so it shouldn't be too bad.
- If you are using a processor affected by an anomaly, the build
- system will double check for you and prevent it.
-
-config DCACHE_FLUSH_L1
- bool "Locate dcache flush funcs in L1 Inst Memory"
- default y
- depends on !SMP
- help
- If enabled, the Blackfin dcache flushing functions are linked
- into L1 instruction memory.
-
-config APP_STACK_L1
- bool "Support locating application stack in L1 Scratch Memory"
- default y
- depends on !SMP
- help
- If enabled the application stack can be located in L1
- scratch memory (less latency).
-
- Currently only works with FLAT binaries.
-
-config EXCEPTION_L1_SCRATCH
- bool "Locate exception stack in L1 Scratch Memory"
- default n
- depends on !SMP && !APP_STACK_L1
- help
- Whenever an exception occurs, use the L1 Scratch memory for
- stack storage. You cannot place the stacks of FLAT binaries
- in L1 when using this option.
-
- If you don't use L1 Scratch, then you should say Y here.
-
-comment "Speed Optimizations"
-config BFIN_INS_LOWOVERHEAD
- bool "ins[bwl] low overhead, higher interrupt latency"
- default y
- depends on !SMP
- help
- Reads on the Blackfin are speculative. In Blackfin terms, this means
- they can be interrupted at any time (even after they have been issued
- on to the external bus), and re-issued after the interrupt occurs.
- For memory - this is not a big deal, since memory does not change if
- it sees a read.
-
- If a FIFO is sitting on the end of the read, it will see two reads,
- when the core only sees one since the FIFO receives both the read
- which is cancelled (and not delivered to the core) and the one which
- is re-issued (which is delivered to the core).
-
- To solve this, interrupts are turned off before reads occur to
- I/O space. This option controls which the overhead/latency of
- controlling interrupts during this time
- "n" turns interrupts off every read
- (higher overhead, but lower interrupt latency)
- "y" turns interrupts off every loop
- (low overhead, but longer interrupt latency)
-
- default behavior is to leave this set to on (type "Y"). If you are experiencing
- interrupt latency issues, it is safe and OK to turn this off.
-
-endmenu
-
-choice
- prompt "Kernel executes from"
- help
- Choose the memory type that the kernel will be running in.
-
-config RAMKERNEL
- bool "RAM"
- help
- The kernel will be resident in RAM when running.
-
-config ROMKERNEL
- bool "ROM"
- help
- The kernel will be resident in FLASH/ROM when running.
-
-endchoice
-
-# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
-config XIP_KERNEL
- bool
- default y
- depends on ROMKERNEL
-
-source "mm/Kconfig"
-
-config BFIN_GPTIMERS
- tristate "Enable Blackfin General Purpose Timers API"
- default n
- help
- Enable support for the General Purpose Timers API. If you
- are unsure, say N.
-
- To compile this driver as a module, choose M here: the module
- will be called gptimers.
-
-choice
- prompt "Uncached DMA region"
- default DMA_UNCACHED_1M
-config DMA_UNCACHED_32M
- bool "Enable 32M DMA region"
-config DMA_UNCACHED_16M
- bool "Enable 16M DMA region"
-config DMA_UNCACHED_8M
- bool "Enable 8M DMA region"
-config DMA_UNCACHED_4M
- bool "Enable 4M DMA region"
-config DMA_UNCACHED_2M
- bool "Enable 2M DMA region"
-config DMA_UNCACHED_1M
- bool "Enable 1M DMA region"
-config DMA_UNCACHED_512K
- bool "Enable 512K DMA region"
-config DMA_UNCACHED_256K
- bool "Enable 256K DMA region"
-config DMA_UNCACHED_128K
- bool "Enable 128K DMA region"
-config DMA_UNCACHED_NONE
- bool "Disable DMA region"
-endchoice
-
-
-comment "Cache Support"
-
-config BFIN_ICACHE
- bool "Enable ICACHE"
- default y
-config BFIN_EXTMEM_ICACHEABLE
- bool "Enable ICACHE for external memory"
- depends on BFIN_ICACHE
- default y
-config BFIN_L2_ICACHEABLE
- bool "Enable ICACHE for L2 SRAM"
- depends on BFIN_ICACHE
- depends on (BF54x || BF561 || BF60x) && !SMP
- default n
-
-config BFIN_DCACHE
- bool "Enable DCACHE"
- default y
-config BFIN_DCACHE_BANKA
- bool "Enable only 16k BankA DCACHE - BankB is SRAM"
- depends on BFIN_DCACHE && !BF531
- default n
-config BFIN_EXTMEM_DCACHEABLE
- bool "Enable DCACHE for external memory"
- depends on BFIN_DCACHE
- default y
-choice
- prompt "External memory DCACHE policy"
- depends on BFIN_EXTMEM_DCACHEABLE
- default BFIN_EXTMEM_WRITEBACK if !SMP
- default BFIN_EXTMEM_WRITETHROUGH if SMP
-config BFIN_EXTMEM_WRITEBACK
- bool "Write back"
- depends on !SMP
- help
- Write Back Policy:
- Cached data will be written back to SDRAM only when needed.
- This can give a nice increase in performance, but beware of
- broken drivers that do not properly invalidate/flush their
- cache.
-
- Write Through Policy:
- Cached data will always be written back to SDRAM when the
- cache is updated. This is a completely safe setting, but
- performance is worse than Write Back.
-
- If you are unsure of the options and you want to be safe,
- then go with Write Through.
-
-config BFIN_EXTMEM_WRITETHROUGH
- bool "Write through"
- help
- Write Back Policy:
- Cached data will be written back to SDRAM only when needed.
- This can give a nice increase in performance, but beware of
- broken drivers that do not properly invalidate/flush their
- cache.
-
- Write Through Policy:
- Cached data will always be written back to SDRAM when the
- cache is updated. This is a completely safe setting, but
- performance is worse than Write Back.
-
- If you are unsure of the options and you want to be safe,
- then go with Write Through.
-
-endchoice
-
-config BFIN_L2_DCACHEABLE
- bool "Enable DCACHE for L2 SRAM"
- depends on BFIN_DCACHE
- depends on (BF54x || BF561 || BF60x) && !SMP
- default n
-choice
- prompt "L2 SRAM DCACHE policy"
- depends on BFIN_L2_DCACHEABLE
- default BFIN_L2_WRITEBACK
-config BFIN_L2_WRITEBACK
- bool "Write back"
-
-config BFIN_L2_WRITETHROUGH
- bool "Write through"
-endchoice
-
-
-comment "Memory Protection Unit"
-config MPU
- bool "Enable the memory protection unit"
- default n
- help
- Use the processor's MPU to protect applications from accessing
- memory they do not own. This comes at a performance penalty
- and is recommended only for debugging.
-
-comment "Asynchronous Memory Configuration"
-
-menu "EBIU_AMGCTL Global Control"
- depends on !BF60x
-config C_AMCKEN
- bool "Enable CLKOUT"
- default y
-
-config C_CDPRIO
- bool "DMA has priority over core for ext. accesses"
- default n
-
-config C_B0PEN
- depends on BF561
- bool "Bank 0 16 bit packing enable"
- default y
-
-config C_B1PEN
- depends on BF561
- bool "Bank 1 16 bit packing enable"
- default y
-
-config C_B2PEN
- depends on BF561
- bool "Bank 2 16 bit packing enable"
- default y
-
-config C_B3PEN
- depends on BF561
- bool "Bank 3 16 bit packing enable"
- default n
-
-choice
- prompt "Enable Asynchronous Memory Banks"
- default C_AMBEN_ALL
-
-config C_AMBEN
- bool "Disable All Banks"
-
-config C_AMBEN_B0
- bool "Enable Bank 0"
-
-config C_AMBEN_B0_B1
- bool "Enable Bank 0 & 1"
-
-config C_AMBEN_B0_B1_B2
- bool "Enable Bank 0 & 1 & 2"
-
-config C_AMBEN_ALL
- bool "Enable All Banks"
-endchoice
-endmenu
-
-menu "EBIU_AMBCTL Control"
- depends on !BF60x
-config BANK_0
- hex "Bank 0 (AMBCTL0.L)"
- default 0x7BB0
- help
- These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
- used to control the Asynchronous Memory Bank 0 settings.
-
-config BANK_1
- hex "Bank 1 (AMBCTL0.H)"
- default 0x7BB0
- default 0x5558 if BF54x
- help
- These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
- used to control the Asynchronous Memory Bank 1 settings.
-
-config BANK_2
- hex "Bank 2 (AMBCTL1.L)"
- default 0x7BB0
- help
- These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
- used to control the Asynchronous Memory Bank 2 settings.
-
-config BANK_3
- hex "Bank 3 (AMBCTL1.H)"
- default 0x99B3
- help
- These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
- used to control the Asynchronous Memory Bank 3 settings.
-
-endmenu
-
-config EBIU_MBSCTLVAL
- hex "EBIU Bank Select Control Register"
- depends on BF54x
- default 0
-
-config EBIU_MODEVAL
- hex "Flash Memory Mode Control Register"
- depends on BF54x
- default 1
-
-config EBIU_FCTLVAL
- hex "Flash Memory Bank Control Register"
- depends on BF54x
- default 6
-endmenu
-
-#############################################################################
-menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
-
-config PCI
- bool "PCI support"
- depends on BROKEN
- help
- Support for PCI bus.
-
-source "drivers/pci/Kconfig"
-
-source "drivers/pcmcia/Kconfig"
-
-endmenu
-
-menu "Executable file formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-menu "Power management options"
-
-source "kernel/power/Kconfig"
-
-config ARCH_SUSPEND_POSSIBLE
- def_bool y
-
-choice
- prompt "Standby Power Saving Mode"
- depends on PM && !BF60x
- default PM_BFIN_SLEEP_DEEPER
-config PM_BFIN_SLEEP_DEEPER
- bool "Sleep Deeper"
- help
- Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
- power dissipation by disabling the clock to the processor core (CCLK).
- Furthermore, Standby sets the internal power supply voltage (VDDINT)
- to 0.85 V to provide the greatest power savings, while preserving the
- processor state.
- The PLL and system clock (SCLK) continue to operate at a very low
- frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
- the SDRAM is put into Self Refresh Mode. Typically an external event
- such as GPIO interrupt or RTC activity wakes up the processor.
- Various Peripherals such as UART, SPORT, PPI may not function as
- normal during Sleep Deeper, due to the reduced SCLK frequency.
- When in the sleep mode, system DMA access to L1 memory is not supported.
-
- If unsure, select "Sleep Deeper".
-
-config PM_BFIN_SLEEP
- bool "Sleep"
- help
- Sleep Mode (High Power Savings) - The sleep mode reduces power
- dissipation by disabling the clock to the processor core (CCLK).
- The PLL and system clock (SCLK), however, continue to operate in
- this mode. Typically an external event or RTC activity will wake
- up the processor. When in the sleep mode, system DMA access to L1
- memory is not supported.
-
- If unsure, select "Sleep Deeper".
-endchoice
-
-comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
- depends on PM
-
-config PM_BFIN_WAKE_PH6
- bool "Allow Wake-Up from on-chip PHY or PH6 GP"
- depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
- default n
- help
- Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
-
-config PM_BFIN_WAKE_GP
- bool "Allow Wake-Up from GPIOs"
- depends on PM && BF54x
- default n
- help
- Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
- (all processors, except ADSP-BF549). This option sets
- the general-purpose wake-up enable (GPWE) control bit to enable
- wake-up upon detection of an active low signal on the /GPW (PH7) pin.
- On ADSP-BF549 this option enables the same functionality on the
- /MRXON pin also PH7.
-
-config PM_BFIN_WAKE_PA15
- bool "Allow Wake-Up from PA15"
- depends on PM && BF60x
- default n
- help
- Enable PA15 Wake-Up
-
-config PM_BFIN_WAKE_PA15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PA15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PB15
- bool "Allow Wake-Up from PB15"
- depends on PM && BF60x
- default n
- help
- Enable PB15 Wake-Up
-
-config PM_BFIN_WAKE_PB15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PB15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PC15
- bool "Allow Wake-Up from PC15"
- depends on PM && BF60x
- default n
- help
- Enable PC15 Wake-Up
-
-config PM_BFIN_WAKE_PC15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PC15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PD06
- bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
- depends on PM && BF60x
- default n
- help
- Enable PD06(ETH0_PHYINT) Wake-up
-
-config PM_BFIN_WAKE_PD06_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PD06
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PE12
- bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
- depends on PM && BF60x
- default n
- help
- Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
-
-config PM_BFIN_WAKE_PE12_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PE12
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PG04
- bool "Allow Wake-Up from PG04(CAN0_RX)"
- depends on PM && BF60x
- default n
- help
- Enable PG04(CAN0_RX) Wake-up
-
-config PM_BFIN_WAKE_PG04_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PG04
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PG13
- bool "Allow Wake-Up from PG13"
- depends on PM && BF60x
- default n
- help
- Enable PG13 Wake-Up
-
-config PM_BFIN_WAKE_PG13_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PG13
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_USB
- bool "Allow Wake-Up from (USB)"
- depends on PM && BF60x
- default n
- help
- Enable (USB) Wake-up
-
-config PM_BFIN_WAKE_USB_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_USB
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-endmenu
-
-menu "CPU Frequency scaling"
-
-source "drivers/cpufreq/Kconfig"
-
-config BFIN_CPU_FREQ
- bool
- depends on CPU_FREQ
- default y
-
-config CPU_VOLTAGE
- bool "CPU Voltage scaling"
- depends on CPU_FREQ
- default n
- help
- Say Y here if you want CPU voltage scaling according to the CPU frequency.
- This option violates the PLL BYPASS recommendation in the Blackfin Processor
- manuals. There is a theoretical risk that during VDDINT transitions
- the PLL may unlock.
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "drivers/firmware/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/blackfin/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
deleted file mode 100644
index c8d9572..0000000
--- a/arch/blackfin/Kconfig.debug
+++ /dev/null
@@ -1,258 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-source "lib/Kconfig.debug"
-
-config DEBUG_VERBOSE
- bool "Verbose fault messages"
- default y
- select PRINTK
- help
- When a program crashes due to an exception, or the kernel detects
- an internal error, the kernel can print a not so brief message
- explaining what the problem was. This debugging information is
- useful to developers and kernel hackers when tracking down problems,
- but mostly meaningless to other people. This is always helpful for
- debugging but serves no purpose on a production system.
- Most people should say N here.
-
-config DEBUG_MMRS
- tristate "Generate Blackfin MMR tree"
- depends on !PINCTRL
- select DEBUG_FS
- help
- Create a tree of Blackfin MMRs via the debugfs tree. If
- you enable this, you will find all MMRs laid out in the
- /sys/kernel/debug/blackfin/ directory where you can read/write
- MMRs directly from userspace. This is obviously just a debug
- feature.
-
-config DEBUG_HWERR
- bool "Hardware error interrupt debugging"
- depends on DEBUG_KERNEL
- help
- When enabled, the hardware error interrupt is never disabled, and
- will happen immediately when an error condition occurs. This comes
- at a slight cost in code size, but is necessary if you are getting
- hardware error interrupts and need to know where they are coming
- from.
-
-config EXACT_HWERR
- bool "Try to make Hardware errors exact"
- depends on DEBUG_HWERR
- help
- By default, the Blackfin hardware errors are not exact - the error
- be reported multiple cycles after the error happens. This delay
- can cause the wrong application, or even the kernel to receive a
- signal to be killed. If you are getting HW errors in your system,
- try turning this on to ensure they are at least coming from the
- proper thread.
-
- On production systems, it is safe (and a small optimization) to say N.
-
-config DEBUG_DOUBLEFAULT
- bool "Debug Double Faults"
- default n
- help
- If an exception is caused while executing code within the exception
- handler, the NMI handler, the reset vector, or in emulator mode,
- a double fault occurs. On the Blackfin, this is a unrecoverable
- event. You have two options:
- - RESET exactly when double fault occurs. The excepting
- instruction address is stored in RETX, where the next kernel
- boot will print it out.
- - Print debug message. This is much more error prone, although
- easier to handle. It is error prone since:
- - The excepting instruction is not committed.
- - All writebacks from the instruction are prevented.
- - The generated exception is not taken.
- - The EXCAUSE field is updated with an unrecoverable event
- The only way to check this is to see if EXCAUSE contains the
- unrecoverable event value at every exception return. By selecting
- this option, you are skipping over the faulting instruction, and
- hoping things stay together enough to print out a debug message.
-
- This does add a little kernel code, but is the only method to debug
- double faults - if unsure say "Y"
-
-choice
- prompt "Double Fault Failure Method"
- default DEBUG_DOUBLEFAULT_PRINT
- depends on DEBUG_DOUBLEFAULT
-
-config DEBUG_DOUBLEFAULT_PRINT
- bool "Print"
-
-config DEBUG_DOUBLEFAULT_RESET
- bool "Reset"
-
-endchoice
-
-config DEBUG_HUNT_FOR_ZERO
- bool "Catch NULL pointer reads/writes"
- default y
- help
- Say Y here to catch reads/writes to anywhere in the memory range
- from 0x0000 - 0x0FFF (the first 4k) of memory. This is useful in
- catching common programming errors such as NULL pointer dereferences.
-
- Misbehaving applications will be killed (generate a SEGV) while the
- kernel will trigger a panic.
-
- Enabling this option will take up an extra entry in CPLB table.
- Otherwise, there is no extra overhead.
-
-config DEBUG_BFIN_HWTRACE_ON
- bool "Turn on Blackfin's Hardware Trace"
- default y
- help
- All Blackfins include a Trace Unit which stores a history of the last
- 16 changes in program flow taken by the program sequencer. The history
- allows the user to recreate the program sequencer’s recent path. This
- can be handy when an application dies - we print out the execution
- path of how it got to the offending instruction.
-
- By turning this off, you may save a tiny amount of power.
-
-choice
- prompt "Omit loop Tracing"
- default DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- depends on DEBUG_BFIN_HWTRACE_ON
- help
- The trace buffer can be configured to omit recording of changes in
- program flow that match either the last entry or one of the last
- two entries. Omitting one of these entries from the record prevents
- the trace buffer from overflowing because of any sort of loop (for, do
- while, etc) in the program.
-
- Because zero-overhead Hardware loops are not recorded in the trace buffer,
- this feature can be used to prevent trace overflow from loops that
- are nested four deep.
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- bool "Trace all Loops"
- help
- The trace buffer records all changes of flow
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_ONE
- bool "Compress single-level loops"
- help
- The trace buffer does not record single loops - helpful if trace
- is spinning on a while or do loop.
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_TWO
- bool "Compress two-level loops"
- help
- The trace buffer does not record loops two levels deep. Helpful if
- the trace is spinning in a nested loop
-
-endchoice
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION
- int
- depends on DEBUG_BFIN_HWTRACE_ON
- default 0 if DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- default 1 if DEBUG_BFIN_HWTRACE_COMPRESSION_ONE
- default 2 if DEBUG_BFIN_HWTRACE_COMPRESSION_TWO
-
-
-config DEBUG_BFIN_HWTRACE_EXPAND
- bool "Expand Trace Buffer greater than 16 entries"
- depends on DEBUG_BFIN_HWTRACE_ON
- default n
- help
- By selecting this option, every time the 16 hardware entries in
- the Blackfin's HW Trace buffer are full, the kernel will move them
- into a software buffer, for dumping when there is an issue. This
- has a great impact on performance, (an interrupt every 16 change of
- flows) and should normally be turned off, except in those nasty
- debugging sessions
-
-config DEBUG_BFIN_HWTRACE_EXPAND_LEN
- int "Size of Trace buffer (in power of 2k)"
- range 0 4
- depends on DEBUG_BFIN_HWTRACE_EXPAND
- default 1
- help
- This sets the size of the software buffer that the trace information
- is kept in.
- 0 for (2^0) 1k, or 256 entries,
- 1 for (2^1) 2k, or 512 entries,
- 2 for (2^2) 4k, or 1024 entries,
- 3 for (2^3) 8k, or 2048 entries,
- 4 for (2^4) 16k, or 4096 entries
-
-config DEBUG_BFIN_NO_KERN_HWTRACE
- bool "Turn off hwtrace in CPLB handlers"
- depends on DEBUG_BFIN_HWTRACE_ON
- default y
- help
- The CPLB error handler contains a lot of flow changes which can
- quickly fill up the hardware trace buffer. When debugging crashes,
- the hardware trace may indicate that the problem lies in kernel
- space when in reality an application is buggy.
-
- Say Y here to disable hardware tracing in some known "jumpy" pieces
- of code so that the trace buffer will extend further back.
-
-config EARLY_PRINTK
- bool "Early printk"
- default n
- select SERIAL_CORE_CONSOLE
- help
- This option enables special console drivers which allow the kernel
- to print messages very early in the bootup process.
-
- This is useful for kernel debugging when your machine crashes very
- early before the console code is initialized. After enabling this
- feature, you must add "earlyprintk=serial,uart0,57600" to the
- command line (bootargs). It is safe to say Y here in all cases, as
- all of this lives in the init section and is thrown away after the
- kernel boots completely.
-
-config NMI_WATCHDOG
- bool "Enable NMI watchdog to help debugging lockup on SMP"
- default n
- depends on SMP
- help
- If any CPU in the system does not execute the period local timer
- interrupt for more than 5 seconds, then the NMI handler dumps debug
- information. This information can be used to debug the lockup.
-
-config CPLB_INFO
- bool "Display the CPLB information"
- help
- Display the CPLB information via /proc/cplbinfo.
-
-config ACCESS_CHECK
- bool "Check the user pointer address"
- default y
- help
- Usually the pointer transfer from user space is checked to see if its
- address is in the kernel space.
-
- Say N here to disable that check to improve the performance.
-
-config BFIN_ISRAM_SELF_TEST
- bool "isram boot self tests"
- default n
- help
- Run some self tests of the isram driver code at boot.
-
-config BFIN_PSEUDODBG_INSNS
- bool "Support pseudo debug instructions"
- default n
- help
- This option allows the kernel to emulate some pseudo instructions which
- allow simulator test cases to be run under Linux with no changes.
-
- Most people should say N here.
-
-config BFIN_PM_WAKEUP_TIME_BENCH
- bool "Display the total time for kernel to resume from power saving mode"
- default n
- help
- Display the total time when kernel resumes normal from standby or
- suspend to mem mode.
-
-endmenu
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
deleted file mode 100644
index 1fce086..0000000
--- a/arch/blackfin/Makefile
+++ /dev/null
@@ -1,168 +0,0 @@
-#
-# arch/blackfin/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := bfin-uclinux-
-endif
-LDFLAGS_vmlinux := -X
-OBJCOPYFLAGS := -O binary -R .note -R .comment -S
-GZFLAGS := -9
-
-KBUILD_CFLAGS += $(call cc-option,-mno-fdpic)
-ifeq ($(CONFIG_ROMKERNEL),y)
-KBUILD_CFLAGS += -mlong-calls
-endif
-KBUILD_AFLAGS += $(call cc-option,-mno-fdpic)
-KBUILD_CFLAGS_MODULE += -mlong-calls
-LDFLAGS += -m elf32bfin
-
-KBUILD_DEFCONFIG := BF537-STAMP_defconfig
-
-# setup the machine name and the machine dependent settings
-machine-$(CONFIG_BF512) := bf518
-machine-$(CONFIG_BF514) := bf518
-machine-$(CONFIG_BF516) := bf518
-machine-$(CONFIG_BF518) := bf518
-machine-$(CONFIG_BF522) := bf527
-machine-$(CONFIG_BF523) := bf527
-machine-$(CONFIG_BF524) := bf527
-machine-$(CONFIG_BF525) := bf527
-machine-$(CONFIG_BF526) := bf527
-machine-$(CONFIG_BF527) := bf527
-machine-$(CONFIG_BF531) := bf533
-machine-$(CONFIG_BF532) := bf533
-machine-$(CONFIG_BF533) := bf533
-machine-$(CONFIG_BF534) := bf537
-machine-$(CONFIG_BF536) := bf537
-machine-$(CONFIG_BF537) := bf537
-machine-$(CONFIG_BF538) := bf538
-machine-$(CONFIG_BF539) := bf538
-machine-$(CONFIG_BF542) := bf548
-machine-$(CONFIG_BF542M) := bf548
-machine-$(CONFIG_BF544) := bf548
-machine-$(CONFIG_BF544M) := bf548
-machine-$(CONFIG_BF547) := bf548
-machine-$(CONFIG_BF547M) := bf548
-machine-$(CONFIG_BF548) := bf548
-machine-$(CONFIG_BF548M) := bf548
-machine-$(CONFIG_BF549) := bf548
-machine-$(CONFIG_BF549M) := bf548
-machine-$(CONFIG_BF561) := bf561
-machine-$(CONFIG_BF609) := bf609
-MACHINE := $(machine-y)
-export MACHINE
-
-cpu-$(CONFIG_BF512) := bf512
-cpu-$(CONFIG_BF514) := bf514
-cpu-$(CONFIG_BF516) := bf516
-cpu-$(CONFIG_BF518) := bf518
-cpu-$(CONFIG_BF522) := bf522
-cpu-$(CONFIG_BF523) := bf523
-cpu-$(CONFIG_BF524) := bf524
-cpu-$(CONFIG_BF525) := bf525
-cpu-$(CONFIG_BF526) := bf526
-cpu-$(CONFIG_BF527) := bf527
-cpu-$(CONFIG_BF531) := bf531
-cpu-$(CONFIG_BF532) := bf532
-cpu-$(CONFIG_BF533) := bf533
-cpu-$(CONFIG_BF534) := bf534
-cpu-$(CONFIG_BF536) := bf536
-cpu-$(CONFIG_BF537) := bf537
-cpu-$(CONFIG_BF538) := bf538
-cpu-$(CONFIG_BF539) := bf539
-cpu-$(CONFIG_BF542) := bf542
-cpu-$(CONFIG_BF542M) := bf542m
-cpu-$(CONFIG_BF544) := bf544
-cpu-$(CONFIG_BF544M) := bf544m
-cpu-$(CONFIG_BF547) := bf547
-cpu-$(CONFIG_BF547M) := bf547m
-cpu-$(CONFIG_BF548) := bf548
-cpu-$(CONFIG_BF548M) := bf548m
-cpu-$(CONFIG_BF549) := bf549
-cpu-$(CONFIG_BF549M) := bf549m
-cpu-$(CONFIG_BF561) := bf561
-cpu-$(CONFIG_BF609) := bf609
-
-rev-$(CONFIG_BF_REV_0_0) := 0.0
-rev-$(CONFIG_BF_REV_0_1) := 0.1
-rev-$(CONFIG_BF_REV_0_2) := 0.2
-rev-$(CONFIG_BF_REV_0_3) := 0.3
-rev-$(CONFIG_BF_REV_0_4) := 0.4
-rev-$(CONFIG_BF_REV_0_5) := 0.5
-rev-$(CONFIG_BF_REV_0_6) := 0.6
-rev-$(CONFIG_BF_REV_NONE) := none
-rev-$(CONFIG_BF_REV_ANY) := any
-
-CPU_REV := $(cpu-y)-$(rev-y)
-export CPU_REV
-
-KBUILD_CFLAGS += -mcpu=$(CPU_REV)
-KBUILD_AFLAGS += -mcpu=$(CPU_REV)
-
-# - we utilize the silicon rev from the toolchain, so move it over to the checkflags
-CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
-CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -D__bfin__
-
-core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/
-
-# If we have a machine-specific directory, then include it in the build.
-ifneq ($(machine-y),)
-core-y += arch/$(ARCH)/mach-$(MACHINE)/
-core-y += arch/$(ARCH)/mach-$(MACHINE)/boards/
-endif
-
-ifeq ($(CONFIG_MPU),y)
-core-y += arch/$(ARCH)/kernel/cplb-mpu/
-else
-core-y += arch/$(ARCH)/kernel/cplb-nompu/
-endif
-
-drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/
-
-libs-y += arch/$(ARCH)/lib/
-
-machdirs := $(patsubst %,arch/blackfin/mach-%/, $(machine-y))
-
-KBUILD_CFLAGS += -Iarch/$(ARCH)/include/
-KBUILD_CFLAGS += -Iarch/$(ARCH)/mach-$(MACHINE)/include
-
-KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
-
-CLEAN_FILES += \
- arch/$(ARCH)/kernel/asm-offsets.s \
-
-archclean:
- $(Q)$(MAKE) $(clean)=$(boot)
-
-INSTALL_PATH ?= /tftpboot
-boot := arch/$(ARCH)/boot
-BOOT_TARGETS = uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
-PHONY += $(BOOT_TARGETS) install
-KBUILD_IMAGE := $(boot)/uImage
-
-all: uImage
-
-$(BOOT_TARGETS): vmlinux
- $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
-
-install:
- $(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(KBUILD_IMAGE) install
-
-define archhelp
- echo '* vmImage - Alias to selected kernel format (vmImage.gz by default)'
- echo ' vmImage.bin - Uncompressed Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bin)'
- echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)'
- echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)'
- echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)'
- echo ' vmImage.lzo - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzo)'
- echo ' vmImage.xip - XIP Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.xip)'
- echo ' install - Install kernel using'
- echo ' (your) ~/bin/$(INSTALLKERNEL) or'
- echo ' (distribution) PATH: $(INSTALLKERNEL) or'
- echo ' install to $$(INSTALL_PATH)'
-endef
diff --git a/arch/blackfin/boot/.gitignore b/arch/blackfin/boot/.gitignore
deleted file mode 100644
index 1287a54..0000000
--- a/arch/blackfin/boot/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-vmImage*
-vmlinux*
-uImage*
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
deleted file mode 100644
index 3efaa09..0000000
--- a/arch/blackfin/boot/Makefile
+++ /dev/null
@@ -1,71 +0,0 @@
-#
-# arch/blackfin/boot/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-
-targets := uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
-extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
-
-ifeq ($(CONFIG_RAMKERNEL),y)
-UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
-else # CONFIG_ROMKERNEL must be set
-UIMAGE_LOADADDR = $(CONFIG_ROM_BASE)
-endif
-UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}')
-UIMAGE_NAME = '$(CPU_REV)-$(KERNELRELEASE)'
-UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -x
-
-$(obj)/vmlinux.bin: vmlinux FORCE
- $(call if_changed,objcopy)
-
-$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
- $(call if_changed,gzip)
-
-$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
- $(call if_changed,bzip2)
-
-$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzma)
-
-$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzo)
-
-# The mkimage tool wants 64bytes prepended to the image
-quiet_cmd_mk_bin_xip = BIN $@
- cmd_mk_bin_xip = ( printf '%64s' | tr ' ' '\377' ; cat $< ) > $@
-$(obj)/vmlinux.bin.xip: $(obj)/vmlinux.bin FORCE
- $(call if_changed,mk_bin_xip)
-
-$(obj)/uImage.bin: $(obj)/vmlinux.bin
- $(call if_changed,uimage,none)
-
-$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2
- $(call if_changed,uimage,bzip2)
-
-$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
- $(call if_changed,uimage,gzip)
-
-$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
- $(call if_changed,uimage,lzma)
-
-$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
- $(call if_changed,uimage,lzo)
-
-$(obj)/uImage.xip: $(obj)/vmlinux.bin.xip
- $(call if_changed,uimage,none)
-
-suffix-y := bin
-suffix-$(CONFIG_KERNEL_GZIP) := gz
-suffix-$(CONFIG_KERNEL_BZIP2) := bz2
-suffix-$(CONFIG_KERNEL_LZMA) := lzma
-suffix-$(CONFIG_KERNEL_LZO) := lzo
-suffix-$(CONFIG_ROMKERNEL) := xip
-
-$(obj)/uImage: $(obj)/uImage.$(suffix-y)
- @ln -sf $(notdir $<) $@
-
-install:
- sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)"
diff --git a/arch/blackfin/boot/install.sh b/arch/blackfin/boot/install.sh
deleted file mode 100644
index e2c6e40..0000000
--- a/arch/blackfin/boot/install.sh
+++ /dev/null
@@ -1,57 +0,0 @@
-#!/bin/sh
-#
-# arch/blackfin/boot/install.sh
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1995 by Linus Torvalds
-#
-# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
-# Adapted from code in arch/i386/boot/install.sh by Mike Frysinger
-#
-# "make install" script for Blackfin architecture
-#
-# Arguments:
-# $1 - kernel version
-# $2 - kernel image file
-# $3 - kernel map file
-# $4 - default install path (blank if root directory)
-#
-
-verify () {
- if [ ! -f "$1" ]; then
- echo "" 1>&2
- echo " *** Missing file: $1" 1>&2
- echo ' *** You need to run "make" before "make install".' 1>&2
- echo "" 1>&2
- exit 1
- fi
-}
-
-# Make sure the files actually exist
-verify "$2"
-verify "$3"
-
-# User may have a custom install script
-
-if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi
-if which ${INSTALLKERNEL} >/dev/null 2>&1; then
- exec ${INSTALLKERNEL} "$@"
-fi
-
-# Default install - same as make zlilo
-
-back_it_up() {
- local file=$1
- [ -f ${file} ] || return 0
- local stamp=$(stat -c %Y ${file} 2>/dev/null)
- mv ${file} ${file}.${stamp:-old}
-}
-
-back_it_up $4/uImage
-back_it_up $4/System.map
-
-cat $2 > $4/uImage
-cp $3 $4/System.map
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
deleted file mode 100644
index 99c00d8..0000000
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ /dev/null
@@ -1,121 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF518=y
-CONFIG_IRQ_TIMER0=12
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_SDH_BFIN=y
-CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
deleted file mode 100644
index e66ba31..0000000
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ /dev/null
@@ -1,158 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF526=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN526_EZBRD=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_STORAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
deleted file mode 100644
index d95658f..0000000
--- a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_IRQ_TWI=7
-CONFIG_IRQ_PORTH_INTA=7
-CONFIG_IRQ_PORTH_INTB=7
-CONFIG_BFIN527_AD7160EVAL=y
-CONFIG_BF527_SPORT0_PORTF=y
-CONFIG_BF527_UART1_PORTG=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="bootargs=root=/dev/mtdblock0 rw clkin_hz=24000000 earlyprintk=serial,uart0,57600 console=tty0 console=ttyBF0,57600"
-CONFIG_CLKIN_HZ=24000000
-CONFIG_HZ_300=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_1=0x5554
-CONFIG_BANK_3=0xFFC0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-# CONFIG_WIRELESS is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7160=y
-CONFIG_TOUCHSCREEN_AD7160_FW=y
-# CONFIG_SERIO is not set
-# CONFIG_BFIN_DMA_INTERFACE is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_BFIN_OTP is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=400
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_VBUS_DRAW=500
-CONFIG_USB_G_SERIAL=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
deleted file mode 100644
index 0207c58..0000000
--- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
+++ /dev/null
@@ -1,188 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_BFIN527_EZKIT_V2=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_ADP5520=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=y
-CONFIG_TOUCHSCREEN_AD7879_I2C=y
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_PMIC_ADP5520=y
-CONFIG_FB=y
-CONFIG_FB_BFIN_LQ035Q1=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_ADP5520=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
deleted file mode 100644
index 99c131b..0000000
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ /dev/null
@@ -1,181 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_1=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=y
-CONFIG_FB_BFIN_T350MCQB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_LTV350QV=m
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF527-TLL6527M_defconfig b/arch/blackfin/configs/BF527-TLL6527M_defconfig
deleted file mode 100644
index cdeb518..0000000
--- a/arch/blackfin/configs/BF527-TLL6527M_defconfig
+++ /dev/null
@@ -1,178 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="DEV_0-1_pre2010"
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_BFIN527_TLL6527M=y
-CONFIG_BF527_UART1_PORTG=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-CONFIG_BOOT_LOAD=0x400000
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0xFFC2
-CONFIG_BANK_1=0xFFC2
-CONFIG_BANK_2=0xFFC2
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_AD714X=y
-CONFIG_INPUT_ADXL34X=y
-# CONFIG_SERIO is not set
-CONFIG_BFIN_PPI=m
-CONFIG_BFIN_SIMPLE_TIMER=m
-CONFIG_BFIN_SPORT=m
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_SMBUS=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_VIDEO_BLACKFIN_CAM=m
-CONFIG_OV9655=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC7=m
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
deleted file mode 100644
index ed7d2c0..0000000
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ /dev/null
@@ -1,114 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BFIN533_EZKIT=y
-CONFIG_TIMER0=11
-CONFIG_CLKIN_HZ=27000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
deleted file mode 100644
index 0c241f4..0000000
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ /dev/null
@@ -1,124 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_TIMER0=11
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_GPIO=m
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FIRMWARE_EDID=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_AD73311=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
deleted file mode 100644
index e5360b3..0000000
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ /dev/null
@@ -1,136 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR1=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FIRMWARE_EDID=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_AD73311=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
deleted file mode 100644
index 60f6fb8..0000000
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ /dev/null
@@ -1,133 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF538=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_IRQ_TIMER1=12
-CONFIG_IRQ_TIMER2=12
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
-CONFIG_MTD_NAND=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=y
-CONFIG_TOUCHSCREEN_AD7879_SPI=y
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-CONFIG_SERIAL_BFIN_UART2=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FB_BFIN_LQ035Q1=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
deleted file mode 100644
index 38cb17d..0000000
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ /dev/null
@@ -1,207 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF548_std=y
-CONFIG_IRQ_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_CACHELINE_ALIGNED_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BANK_3=0x99B2
-CONFIG_EBIU_MBSCTLVAL=0x0
-CONFIG_EBIU_MODEVAL=0x1
-CONFIG_EBIU_FCTLVAL=0x6
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR3=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_BF5XX=y
-# CONFIG_MTD_NAND_BF5XX_HWECC is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_ATA=y
-# CONFIG_SATA_PMP is not set
-CONFIG_PATA_BF54X=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMSC911X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_BFIN=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_BF54X_LQ043=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_AC97=y
-CONFIG_SND_BF5XX_SOC_AD1980=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=m
-CONFIG_SDH_BFIN=y
-CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-CONFIG_CIFS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig
deleted file mode 100644
index 78f6bc7..0000000
--- a/arch/blackfin/configs/BF561-ACVILON_defconfig
+++ /dev/null
@@ -1,149 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_BF_REV_0_5=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_BFIN561_ACVILON=y
-# CONFIG_BF561_COREB is not set
-CONFIG_CLKIN_HZ=12000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_DMA_UNCACHED_4M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0x99b2
-CONFIG_BANK_1=0x3350
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_PHRAM=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=2
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_PIO=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PCA_PLATFORM=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_SENSORS_LM75=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SPORT_NUM=1
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=866
-CONFIG_FAT_DEFAULT_IOCHARSET="cp1251"
-CONFIG_NTFS_FS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-# CONFIG_JFFS2_ZLIB is not set
-CONFIG_JFFS2_LZO=y
-# CONFIG_JFFS2_RTIME is not set
-CONFIG_JFFS2_CMODE_FAVOURLZO=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_DEFAULT="cp1251"
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_CODEPAGE_1251=y
-CONFIG_NLS_KOI8_R=y
-CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
deleted file mode 100644
index fac8bb5..0000000
--- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
+++ /dev/null
@@ -1,112 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_SMP=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_CLKIN_HZ=30000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
deleted file mode 100644
index 2a2e4d0..0000000
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ /dev/null
@@ -1,114 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_CLKIN_HZ=30000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BFIN_L2_DCACHEABLE=y
-CONFIG_BFIN_L2_WRITETHROUGH=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig
deleted file mode 100644
index 3ce77f0..0000000
--- a/arch/blackfin/configs/BF609-EZKIT_defconfig
+++ /dev/null
@@ -1,154 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF609=y
-CONFIG_PINT1_ASSIGN=0x01010000
-CONFIG_PINT2_ASSIGN=0x07000101
-CONFIG_PINT3_ASSIGN=0x02020303
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-# CONFIG_APP_STACK_L1 is not set
-# CONFIG_BFIN_INS_LOWOVERHEAD is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM_BFIN_WAKE_PE12=y
-CONFIG_PM_BFIN_WAKE_PE12_POL=1
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_CAN=y
-CONFIG_CAN_BFIN=y
-CONFIG_IRDA=y
-CONFIG_IRTTY_SIR=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=m
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_IEEE1588=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_BFIN_ROTARY=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_SIMPLE_TIMER=m
-# CONFIG_BFIN_CRC is not set
-CONFIG_BFIN_LINKPORT=y
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_ADI_V3=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_PINCTRL_MCP23S08=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=m
-CONFIG_USB=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_ZERO=y
-CONFIG_MMC=y
-CONFIG_SDH_BFIN=y
-# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=m
-CONFIG_UBIFS_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO_HMAC=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_DEV_BFIN_CRC=m
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
deleted file mode 100644
index f4a9200..0000000
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_BLACKSTAMP=y
-CONFIG_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_ROMKERNEL=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_GPIO=m
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=m
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_SMB_FS=y
-CONFIG_CIFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_UTF8=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
deleted file mode 100644
index 1902bb0..0000000
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ /dev/null
@@ -1,129 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_1=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN527_BLUETECHNIX_CM=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_USB=m
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=m
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_PERIPHERAL=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig
deleted file mode 100644
index 9a5716d..0000000
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_BFIN533_BLUETECHNIX_CM=y
-CONFIG_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SPI=m
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig
deleted file mode 100644
index 6845928..0000000
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ /dev/null
@@ -1,107 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_CM_E=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig
deleted file mode 100644
index d9915e9..0000000
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ /dev/null
@@ -1,96 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_CM_U=y
-CONFIG_CLKIN_HZ=30000000
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_2=0xFFC2
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
deleted file mode 100644
index 92d8130..0000000
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ /dev/null
@@ -1,170 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF548_std=y
-CONFIG_BF_REV_ANY=y
-CONFIG_IRQ_TIMER0=11
-CONFIG_BFIN548_BLUETECHNIX_CM=y
-# CONFIG_DEB_DMA_URGENT is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_CACHELINE_ALIGNED_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BANK_1=0x5554
-CONFIG_EBIU_MBSCTLVAL=0x0
-CONFIG_EBIU_MODEVAL=0x1
-CONFIG_EBIU_FCTLVAL=0x6
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_PIO=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=m
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=m
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_PERIPHERAL=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_MMC=m
-CONFIG_SDH_BFIN=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=m
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_CIFS=m
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
deleted file mode 100644
index fa8d911..0000000
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF561=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_BFIN561_BLUETECHNIX_CM=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_SMSC911X=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig
deleted file mode 100644
index 8860059..0000000
--- a/arch/blackfin/configs/DNP5370_defconfig
+++ /dev/null
@@ -1,118 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="DNP5370"
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLOB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_BF537=y
-CONFIG_BF_REV_0_3=y
-CONFIG_DNP5370=y
-CONFIG_IRQ_ERROR=7
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_C_CDPRIO=y
-CONFIG_C_AMBEN_B0_B1_B2=y
-CONFIG_PM=y
-# CONFIG_SUSPEND is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_LLC2=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=1
-CONFIG_MTD_BLOCK=y
-CONFIG_NFTL=y
-CONFIG_NFTL_RW=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_ABSENT=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_BFIN_DMA_INTERFACE is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=y
-CONFIG_BFIN_JTAG_COMM_CONSOLE=y
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_LEGACY_PTY_COUNT=64
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_SENSORS_LM75=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_DMADEVICES=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=850
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_OBJECTS=y
-CONFIG_DEBUG_LOCK_ALLOC=y
-CONFIG_DEBUG_KOBJECT=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_VM=y
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_LIST=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_PAGE_POISONING=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig
deleted file mode 100644
index 0ff97d8..0000000
--- a/arch/blackfin/configs/H8606_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_H8606_HVSISTEMAS=y
-CONFIG_TIMER0=11
-# CONFIG_CACHELINE_ALIGNED_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_WATCHDOG=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS=m
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
deleted file mode 100644
index 9e3ae4b..0000000
--- a/arch/blackfin/configs/IP0X_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_BFIN532_IP0X=y
-CONFIG_TIMER0=11
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-# CONFIG_BFIN_ICACHE is not set
-# CONFIG_BFIN_DCACHE is not set
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0xffc2
-CONFIG_BANK_1=0xffc2
-CONFIG_BANK_2=0xffc2
-CONFIG_BANK_3=0xffc2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_MANGLE=y
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_USB=y
-CONFIG_USB_OTG_WHITELIST=y
-CONFIG_USB_MON=y
-CONFIG_USB_ISP1362_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
deleted file mode 100644
index c792681..0000000
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_PNAV10=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_1=0x33B0
-CONFIG_BANK_2=0x33B0
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_BFIN_MAC_USE_L1 is not set
-CONFIG_BFIN_TX_DESC_NUM=100
-CONFIG_BFIN_RX_DESC_NUM=100
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7877=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_SOUND=y
-CONFIG_SND=m
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_SOUND_PRIME=y
-# CONFIG_HID is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_HUNT_FOR_ZERO is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_ACCESS_CHECK is not set
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
deleted file mode 100644
index 23fdc57..0000000
--- a/arch/blackfin/configs/SRV1_defconfig
+++ /dev/null
@@ -1,88 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BOOT_LOAD=0x400000
-CONFIG_CLKIN_HZ=22118400
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_NAND=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=m
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_HWMON=m
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
diff --git a/arch/blackfin/configs/TCM-BF518_defconfig b/arch/blackfin/configs/TCM-BF518_defconfig
deleted file mode 100644
index e289594..0000000
--- a/arch/blackfin/configs/TCM-BF518_defconfig
+++ /dev/null
@@ -1,131 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF518=y
-CONFIG_BF_REV_0_1=y
-CONFIG_BFIN518F_TCM=y
-CONFIG_IRQ_TIMER0=12
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_MMC_SPI=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig
deleted file mode 100644
index 39e85cc..0000000
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_TCM=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
deleted file mode 100644
index fe73697..0000000
--- a/arch/blackfin/include/asm/Kbuild
+++ /dev/null
@@ -1,28 +0,0 @@
-generic-y += bugs.h
-generic-y += current.h
-generic-y += device.h
-generic-y += div64.h
-generic-y += emergency-restart.h
-generic-y += extable.h
-generic-y += fb.h
-generic-y += futex.h
-generic-y += hw_irq.h
-generic-y += irq_regs.h
-generic-y += irq_work.h
-generic-y += kdebug.h
-generic-y += kmap_types.h
-generic-y += kprobes.h
-generic-y += local.h
-generic-y += local64.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += percpu.h
-generic-y += pgalloc.h
-generic-y += preempt.h
-generic-y += serial.h
-generic-y += topology.h
-generic-y += trace_clock.h
-generic-y += unaligned.h
-generic-y += user.h
-generic-y += word-at-a-time.h
-generic-y += xor.h
diff --git a/arch/blackfin/include/asm/asm-offsets.h b/arch/blackfin/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee3..0000000
--- a/arch/blackfin/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
deleted file mode 100644
index 63c7dec..0000000
--- a/arch/blackfin/include/asm/atomic.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_ATOMIC__
-#define __ARCH_BLACKFIN_ATOMIC__
-
-#include <asm/cmpxchg.h>
-
-#ifdef CONFIG_SMP
-
-#include <asm/barrier.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-
-asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr);
-asmlinkage int __raw_atomic_add_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_xadd_asm(volatile int *ptr, int value);
-
-asmlinkage int __raw_atomic_and_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_or_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_xor_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_test_asm(const volatile int *ptr, int value);
-
-#define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter)
-
-#define atomic_add_return(i, v) __raw_atomic_add_asm(&(v)->counter, i)
-#define atomic_sub_return(i, v) __raw_atomic_add_asm(&(v)->counter, -(i))
-
-#define atomic_fetch_add(i, v) __raw_atomic_xadd_asm(&(v)->counter, i)
-#define atomic_fetch_sub(i, v) __raw_atomic_xadd_asm(&(v)->counter, -(i))
-
-#define atomic_or(i, v) (void)__raw_atomic_or_asm(&(v)->counter, i)
-#define atomic_and(i, v) (void)__raw_atomic_and_asm(&(v)->counter, i)
-#define atomic_xor(i, v) (void)__raw_atomic_xor_asm(&(v)->counter, i)
-
-#define atomic_fetch_or(i, v) __raw_atomic_or_asm(&(v)->counter, i)
-#define atomic_fetch_and(i, v) __raw_atomic_and_asm(&(v)->counter, i)
-#define atomic_fetch_xor(i, v) __raw_atomic_xor_asm(&(v)->counter, i)
-
-#endif
-
-#include <asm-generic/atomic.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/barrier.h b/arch/blackfin/include/asm/barrier.h
deleted file mode 100644
index 7cca51c..0000000
--- a/arch/blackfin/include/asm/barrier.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * Tony Kou (tonyko at lineo.ca)
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BLACKFIN_BARRIER_H
-#define _BLACKFIN_BARRIER_H
-
-#include <asm/cache.h>
-
-#define nop() __asm__ __volatile__ ("nop;\n\t" : : )
-
-/*
- * Force strict CPU ordering.
- */
-#ifdef CONFIG_SMP
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-/* Force Core data cache coherence */
-# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
-# define rmb() do { barrier(); smp_check_barrier(); } while (0)
-# define wmb() do { barrier(); smp_mark_barrier(); } while (0)
-/*
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier. All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads. This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies. See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- * CPU 0 CPU 1
- *
- * b = 2;
- * memory_barrier();
- * p = &b; q = p;
- * read_barrier_depends();
- * d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends(). However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- * CPU 0 CPU 1
- *
- * a = 2;
- * memory_barrier();
- * b = 3; y = b;
- * read_barrier_depends();
- * x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b". Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
- * in cases like this where there are no data dependencies.
- */
-# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
-#endif
-
-#endif /* !CONFIG_SMP */
-
-#define __smp_mb__before_atomic() barrier()
-#define __smp_mb__after_atomic() barrier()
-
-#include <asm-generic/barrier.h>
-
-#endif /* _BLACKFIN_BARRIER_H */
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
deleted file mode 100644
index dc47d79..0000000
--- a/arch/blackfin/include/asm/bfin-global.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Global extern defines for blackfin
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_GLOBAL_H_
-#define _BFIN_GLOBAL_H_
-
-#ifndef __ASSEMBLY__
-
-#include <linux/linkage.h>
-#include <linux/types.h>
-
-#if defined(CONFIG_DMA_UNCACHED_32M)
-# define DMA_UNCACHED_REGION (32 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_16M)
-# define DMA_UNCACHED_REGION (16 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_8M)
-# define DMA_UNCACHED_REGION (8 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_4M)
-# define DMA_UNCACHED_REGION (4 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_2M)
-# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_1M)
-# define DMA_UNCACHED_REGION (1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_512K)
-# define DMA_UNCACHED_REGION (512 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_256K)
-# define DMA_UNCACHED_REGION (256 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_128K)
-# define DMA_UNCACHED_REGION (128 * 1024)
-#else
-# define DMA_UNCACHED_REGION (0)
-#endif
-
-extern void bfin_setup_caches(unsigned int cpu);
-extern void bfin_setup_cpudata(unsigned int cpu);
-
-extern unsigned long get_cclk(void);
-extern unsigned long get_sclk(void);
-#ifdef CONFIG_BF60x
-extern unsigned long get_sclk0(void);
-extern unsigned long get_sclk1(void);
-extern unsigned long get_dclk(void);
-#endif
-extern unsigned long sclk_to_usecs(unsigned long sclk);
-extern unsigned long usecs_to_sclk(unsigned long usecs);
-
-struct pt_regs;
-#if defined(CONFIG_DEBUG_VERBOSE)
-extern void dump_bfin_process(struct pt_regs *regs);
-extern void dump_bfin_mem(struct pt_regs *regs);
-extern void dump_bfin_trace_buffer(void);
-#else
-#define dump_bfin_process(regs)
-#define dump_bfin_mem(regs)
-#define dump_bfin_trace_buffer()
-#endif
-
-extern void *l1_data_A_sram_alloc(size_t);
-extern void *l1_data_B_sram_alloc(size_t);
-extern void *l1_inst_sram_alloc(size_t);
-extern void *l1_data_sram_alloc(size_t);
-extern void *l1_data_sram_zalloc(size_t);
-extern void *l2_sram_alloc(size_t);
-extern void *l2_sram_zalloc(size_t);
-extern int l1_data_A_sram_free(const void*);
-extern int l1_data_B_sram_free(const void*);
-extern int l1_inst_sram_free(const void*);
-extern int l1_data_sram_free(const void*);
-extern int l2_sram_free(const void *);
-extern int sram_free(const void*);
-
-#define L1_INST_SRAM 0x00000001
-#define L1_DATA_A_SRAM 0x00000002
-#define L1_DATA_B_SRAM 0x00000004
-#define L1_DATA_SRAM 0x00000006
-#define L2_SRAM 0x00000008
-extern void *sram_alloc_with_lsl(size_t, unsigned long);
-extern int sram_free_with_lsl(const void*);
-
-extern void *isram_memcpy(void *dest, const void *src, size_t n);
-
-extern const char bfin_board_name[];
-
-extern unsigned long bfin_sic_iwr[];
-extern unsigned vr_wakeup;
-extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
-
-#endif
-
-#endif /* _BLACKFIN_H_ */
diff --git a/arch/blackfin/include/asm/bfin-lq035q1.h b/arch/blackfin/include/asm/bfin-lq035q1.h
deleted file mode 100644
index 8368951..0000000
--- a/arch/blackfin/include/asm/bfin-lq035q1.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
- *
- * Copyright 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef BFIN_LQ035Q1_H
-#define BFIN_LQ035Q1_H
-
-/*
- * LCD Modes
- */
-#define LQ035_RL (0 << 8) /* Right -> Left Scan */
-#define LQ035_LR (1 << 8) /* Left -> Right Scan */
-#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
-#define LQ035_BT (0 << 9) /* Botton -> Top Scan */
-#define LQ035_BGR (1 << 11) /* Use BGR format */
-#define LQ035_RGB (0 << 11) /* Use RGB format */
-#define LQ035_NORM (1 << 13) /* Reversal */
-#define LQ035_REV (0 << 13) /* Reversal */
-
-/*
- * PPI Modes
- */
-
-#define USE_RGB565_16_BIT_PPI 1
-#define USE_RGB565_8_BIT_PPI 2
-#define USE_RGB888_8_BIT_PPI 3
-
-struct bfin_lq035q1fb_disp_info {
-
- unsigned mode;
- unsigned ppi_mode;
- /* GPIOs */
- int use_bl;
- unsigned gpio_bl;
-};
-
-#endif /* BFIN_LQ035Q1_H */
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
deleted file mode 100644
index fb95c85..0000000
--- a/arch/blackfin/include/asm/bfin5xx_spi.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Blackfin On-Chip SPI Driver
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _SPI_CHANNEL_H_
-#define _SPI_CHANNEL_H_
-
-#define MIN_SPI_BAUD_VAL 2
-
-#define BIT_CTL_ENABLE 0x4000
-#define BIT_CTL_OPENDRAIN 0x2000
-#define BIT_CTL_MASTER 0x1000
-#define BIT_CTL_CPOL 0x0800
-#define BIT_CTL_CPHA 0x0400
-#define BIT_CTL_LSBF 0x0200
-#define BIT_CTL_WORDSIZE 0x0100
-#define BIT_CTL_EMISO 0x0020
-#define BIT_CTL_PSSE 0x0010
-#define BIT_CTL_GM 0x0008
-#define BIT_CTL_SZ 0x0004
-#define BIT_CTL_RXMOD 0x0000
-#define BIT_CTL_TXMOD 0x0001
-#define BIT_CTL_TIMOD_DMA_TX 0x0003
-#define BIT_CTL_TIMOD_DMA_RX 0x0002
-#define BIT_CTL_SENDOPT 0x0004
-#define BIT_CTL_TIMOD 0x0003
-
-#define BIT_STAT_SPIF 0x0001
-#define BIT_STAT_MODF 0x0002
-#define BIT_STAT_TXE 0x0004
-#define BIT_STAT_TXS 0x0008
-#define BIT_STAT_RBSY 0x0010
-#define BIT_STAT_RXS 0x0020
-#define BIT_STAT_TXCOL 0x0040
-#define BIT_STAT_CLR 0xFFFF
-
-#define BIT_STU_SENDOVER 0x0001
-#define BIT_STU_RECVFULL 0x0020
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin spi registers layout
- */
-struct bfin_spi_regs {
- __BFP(ctl);
- __BFP(flg);
- __BFP(stat);
- __BFP(tdbr);
- __BFP(rdbr);
- __BFP(baud);
- __BFP(shadow);
-};
-
-#undef __BFP
-
-#define MAX_CTRL_CS 8 /* cs in spi controller */
-
-/* device.platform_data for SSP controller devices */
-struct bfin5xx_spi_master {
- u16 num_chipselect;
- u8 enable_dma;
- u16 pin_req[7];
-};
-
-/* spi_board_info.controller_data for SPI slave devices,
- * copied to spi_device.platform_data ... mostly for dma tuning
- */
-struct bfin5xx_spi_chip {
- u16 ctl_reg;
- u8 enable_dma;
- u16 cs_chg_udelay; /* Some devices require 16-bit delays */
- /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
- u16 idle_tx_val;
- u8 pio_interrupt; /* Enable spi data irq */
-};
-
-#endif /* _SPI_CHANNEL_H_ */
diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h
deleted file mode 100644
index b1492e0..0000000
--- a/arch/blackfin/include/asm/bfin_can.h
+++ /dev/null
@@ -1,728 +0,0 @@
-/*
- * bfin_can.h - interface to Blackfin CANs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_CAN_H__
-#define __ASM_BFIN_CAN_H__
-
-/*
- * transmit and receive channels
- */
-#define TRANSMIT_CHL 24
-#define RECEIVE_STD_CHL 0
-#define RECEIVE_EXT_CHL 4
-#define RECEIVE_RTR_CHL 8
-#define RECEIVE_EXT_RTR_CHL 12
-#define MAX_CHL_NUMBER 32
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin can registers layout
- */
-struct bfin_can_mask_regs {
- __BFP(aml);
- __BFP(amh);
-};
-
-struct bfin_can_channel_regs {
- /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
- u16 data[8];
- __BFP(dlc);
- __BFP(tsv);
- __BFP(id0);
- __BFP(id1);
-};
-
-struct bfin_can_regs {
- /*
- * global control and status registers
- */
- __BFP(mc1); /* offset 0x00 */
- __BFP(md1); /* offset 0x04 */
- __BFP(trs1); /* offset 0x08 */
- __BFP(trr1); /* offset 0x0c */
- __BFP(ta1); /* offset 0x10 */
- __BFP(aa1); /* offset 0x14 */
- __BFP(rmp1); /* offset 0x18 */
- __BFP(rml1); /* offset 0x1c */
- __BFP(mbtif1); /* offset 0x20 */
- __BFP(mbrif1); /* offset 0x24 */
- __BFP(mbim1); /* offset 0x28 */
- __BFP(rfh1); /* offset 0x2c */
- __BFP(opss1); /* offset 0x30 */
- u32 __pad1[3];
- __BFP(mc2); /* offset 0x40 */
- __BFP(md2); /* offset 0x44 */
- __BFP(trs2); /* offset 0x48 */
- __BFP(trr2); /* offset 0x4c */
- __BFP(ta2); /* offset 0x50 */
- __BFP(aa2); /* offset 0x54 */
- __BFP(rmp2); /* offset 0x58 */
- __BFP(rml2); /* offset 0x5c */
- __BFP(mbtif2); /* offset 0x60 */
- __BFP(mbrif2); /* offset 0x64 */
- __BFP(mbim2); /* offset 0x68 */
- __BFP(rfh2); /* offset 0x6c */
- __BFP(opss2); /* offset 0x70 */
- u32 __pad2[3];
- __BFP(clock); /* offset 0x80 */
- __BFP(timing); /* offset 0x84 */
- __BFP(debug); /* offset 0x88 */
- __BFP(status); /* offset 0x8c */
- __BFP(cec); /* offset 0x90 */
- __BFP(gis); /* offset 0x94 */
- __BFP(gim); /* offset 0x98 */
- __BFP(gif); /* offset 0x9c */
- __BFP(control); /* offset 0xa0 */
- __BFP(intr); /* offset 0xa4 */
- __BFP(version); /* offset 0xa8 */
- __BFP(mbtd); /* offset 0xac */
- __BFP(ewr); /* offset 0xb0 */
- __BFP(esr); /* offset 0xb4 */
- u32 __pad3[2];
- __BFP(ucreg); /* offset 0xc0 */
- __BFP(uccnt); /* offset 0xc4 */
- __BFP(ucrc); /* offset 0xc8 */
- __BFP(uccnf); /* offset 0xcc */
- u32 __pad4[1];
- __BFP(version2); /* offset 0xd4 */
- u32 __pad5[10];
-
- /*
- * channel(mailbox) mask and message registers
- */
- struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */
- struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
-};
-
-#undef __BFP
-
-/* CAN_CONTROL Masks */
-#define SRS 0x0001 /* Software Reset */
-#define DNM 0x0002 /* Device Net Mode */
-#define ABO 0x0004 /* Auto-Bus On Enable */
-#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
-#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
-#define SMR 0x0020 /* Sleep Mode Request */
-#define CSR 0x0040 /* CAN Suspend Mode Request */
-#define CCR 0x0080 /* CAN Configuration Mode Request */
-
-/* CAN_STATUS Masks */
-#define WT 0x0001 /* TX Warning Flag */
-#define WR 0x0002 /* RX Warning Flag */
-#define EP 0x0004 /* Error Passive Mode */
-#define EBO 0x0008 /* Error Bus Off Mode */
-#define SMA 0x0020 /* Sleep Mode Acknowledge */
-#define CSA 0x0040 /* Suspend Mode Acknowledge */
-#define CCA 0x0080 /* Configuration Mode Acknowledge */
-#define MBPTR 0x1F00 /* Mailbox Pointer */
-#define TRM 0x4000 /* Transmit Mode */
-#define REC 0x8000 /* Receive Mode */
-
-/* CAN_CLOCK Masks */
-#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
-
-/* CAN_TIMING Masks */
-#define TSEG1 0x000F /* Time Segment 1 */
-#define TSEG2 0x0070 /* Time Segment 2 */
-#define SAM 0x0080 /* Sampling */
-#define SJW 0x0300 /* Synchronization Jump Width */
-
-/* CAN_DEBUG Masks */
-#define DEC 0x0001 /* Disable CAN Error Counters */
-#define DRI 0x0002 /* Disable CAN RX Input */
-#define DTO 0x0004 /* Disable CAN TX Output */
-#define DIL 0x0008 /* Disable CAN Internal Loop */
-#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
-#define MRB 0x0020 /* Mode Read Back Enable */
-#define CDE 0x8000 /* CAN Debug Enable */
-
-/* CAN_CEC Masks */
-#define RXECNT 0x00FF /* Receive Error Counter */
-#define TXECNT 0xFF00 /* Transmit Error Counter */
-
-/* CAN_INTR Masks */
-#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
-#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
-#define GIRQ 0x0004 /* Global Interrupt */
-#define SMACK 0x0008 /* Sleep Mode Acknowledge */
-#define CANTX 0x0040 /* CAN TX Bus Value */
-#define CANRX 0x0080 /* CAN RX Bus Value */
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
-#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define IDE 0x2000 /* Identifier Extension */
-#define RTR 0x4000 /* Remote Frame Transmission Request */
-#define AME 0x8000 /* Acceptance Mask Enable */
-
-/* CAN_MBxx_TIMESTAMP Masks */
-#define TSV 0xFFFF /* Timestamp */
-
-/* CAN_MBxx_LENGTH Masks */
-#define DLC 0x000F /* Data Length Code */
-
-/* CAN_AMxxH and CAN_AMxxL Masks */
-#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
-#define FMD 0x4000 /* Full Mask Data Field Enable */
-#define FDF 0x8000 /* Filter On Data Field Enable */
-
-/* CAN_MC1 Masks */
-#define MC0 0x0001 /* Enable Mailbox 0 */
-#define MC1 0x0002 /* Enable Mailbox 1 */
-#define MC2 0x0004 /* Enable Mailbox 2 */
-#define MC3 0x0008 /* Enable Mailbox 3 */
-#define MC4 0x0010 /* Enable Mailbox 4 */
-#define MC5 0x0020 /* Enable Mailbox 5 */
-#define MC6 0x0040 /* Enable Mailbox 6 */
-#define MC7 0x0080 /* Enable Mailbox 7 */
-#define MC8 0x0100 /* Enable Mailbox 8 */
-#define MC9 0x0200 /* Enable Mailbox 9 */
-#define MC10 0x0400 /* Enable Mailbox 10 */
-#define MC11 0x0800 /* Enable Mailbox 11 */
-#define MC12 0x1000 /* Enable Mailbox 12 */
-#define MC13 0x2000 /* Enable Mailbox 13 */
-#define MC14 0x4000 /* Enable Mailbox 14 */
-#define MC15 0x8000 /* Enable Mailbox 15 */
-
-/* CAN_MC2 Masks */
-#define MC16 0x0001 /* Enable Mailbox 16 */
-#define MC17 0x0002 /* Enable Mailbox 17 */
-#define MC18 0x0004 /* Enable Mailbox 18 */
-#define MC19 0x0008 /* Enable Mailbox 19 */
-#define MC20 0x0010 /* Enable Mailbox 20 */
-#define MC21 0x0020 /* Enable Mailbox 21 */
-#define MC22 0x0040 /* Enable Mailbox 22 */
-#define MC23 0x0080 /* Enable Mailbox 23 */
-#define MC24 0x0100 /* Enable Mailbox 24 */
-#define MC25 0x0200 /* Enable Mailbox 25 */
-#define MC26 0x0400 /* Enable Mailbox 26 */
-#define MC27 0x0800 /* Enable Mailbox 27 */
-#define MC28 0x1000 /* Enable Mailbox 28 */
-#define MC29 0x2000 /* Enable Mailbox 29 */
-#define MC30 0x4000 /* Enable Mailbox 30 */
-#define MC31 0x8000 /* Enable Mailbox 31 */
-
-/* CAN_MD1 Masks */
-#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
-#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
-#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
-#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
-#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
-#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
-#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
-#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
-#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
-#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
-#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
-#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
-#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
-#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
-#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
-#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
-
-/* CAN_MD2 Masks */
-#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
-#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
-#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
-#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
-#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
-#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
-#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
-#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
-#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
-#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
-#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
-#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
-#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
-#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
-#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
-#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
-
-/* CAN_RMP1 Masks */
-#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
-#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
-#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
-#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
-#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
-#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
-#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
-#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
-#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
-#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
-#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
-#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
-#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
-#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
-#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
-#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
-
-/* CAN_RMP2 Masks */
-#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
-#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
-#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
-#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
-#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
-#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
-#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
-#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
-#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
-#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
-#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
-#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
-#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
-#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
-#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
-#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
-
-/* CAN_RML1 Masks */
-#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
-#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
-#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
-#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
-#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
-#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
-#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
-#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
-#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
-#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
-#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
-#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
-#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
-#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
-#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
-#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
-
-/* CAN_RML2 Masks */
-#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
-#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
-#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
-#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
-#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
-#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
-#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
-#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
-#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
-#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
-#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
-#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
-#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
-#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
-#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
-#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
-
-/* CAN_OPSS1 Masks */
-#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
-#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
-#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
-#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
-#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
-#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
-#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
-#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
-#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
-#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
-#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
-#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
-#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
-#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
-#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
-#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
-
-/* CAN_OPSS2 Masks */
-#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
-#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
-#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
-#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
-#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
-#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
-#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
-#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
-#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
-#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
-#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
-#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
-#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
-#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
-#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
-#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
-
-/* CAN_TRR1 Masks */
-#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
-#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
-#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
-#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
-#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
-#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
-#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
-#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
-#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
-#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
-#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
-#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
-#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
-#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
-#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
-#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
-
-/* CAN_TRR2 Masks */
-#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
-#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
-#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
-#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
-#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
-#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
-#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
-#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
-#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
-#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
-#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
-#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
-#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
-#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
-#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
-#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
-
-/* CAN_TRS1 Masks */
-#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
-#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
-#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
-#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
-#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
-#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
-#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
-#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
-#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
-#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
-#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
-#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
-#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
-#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
-#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
-#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
-
-/* CAN_TRS2 Masks */
-#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
-#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
-#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
-#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
-#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
-#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
-#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
-#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
-#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
-#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
-#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
-#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
-#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
-#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
-#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
-#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
-
-/* CAN_AA1 Masks */
-#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
-#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
-#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
-#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
-#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
-#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
-#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
-#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
-#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
-#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
-#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
-#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
-#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
-#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
-#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
-#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
-
-/* CAN_AA2 Masks */
-#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
-#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
-#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
-#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
-#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
-#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
-#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
-#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
-#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
-#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
-#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
-#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
-#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
-#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
-#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
-#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
-
-/* CAN_TA1 Masks */
-#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
-#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
-#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
-#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
-#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
-#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
-#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
-#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
-#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
-#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
-#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
-#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
-#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
-#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
-#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
-#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
-
-/* CAN_TA2 Masks */
-#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
-#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
-#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
-#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
-#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
-#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
-#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
-#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
-#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
-#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
-#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
-#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
-#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
-#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
-#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
-#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
-
-/* CAN_MBTD Masks */
-#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
-#define TDA 0x0040 /* Temporary Disable Acknowledge */
-#define TDR 0x0080 /* Temporary Disable Request */
-
-/* CAN_RFH1 Masks */
-#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
-#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
-#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
-#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
-#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
-#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
-#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
-#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
-#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
-#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
-#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
-#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
-#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
-#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
-#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
-#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
-
-/* CAN_RFH2 Masks */
-#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
-#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
-#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
-#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
-#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
-#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
-#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
-#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
-#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
-#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
-#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
-#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
-#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
-#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
-#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
-#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
-
-/* CAN_MBTIF1 Masks */
-#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
-#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
-#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
-#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
-#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
-#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
-#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
-#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
-#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
-#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
-#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
-#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
-#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
-#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
-#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
-#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBTIF2 Masks */
-#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
-#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
-#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
-#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
-#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
-#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
-#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
-#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
-#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
-#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
-#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
-#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
-#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
-#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
-#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
-#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBRIF1 Masks */
-#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
-#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
-#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
-#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
-#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
-#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
-#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
-#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
-#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
-#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
-#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
-#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
-#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
-#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
-#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
-#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBRIF2 Masks */
-#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
-#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
-#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
-#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
-#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
-#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
-#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
-#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
-#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
-#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
-#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
-#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
-#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
-#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
-#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
-#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBIM1 Masks */
-#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
-#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
-#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
-#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
-#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
-#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
-#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
-#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
-#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
-#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
-#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
-#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
-#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
-#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
-#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
-#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
-
-/* CAN_MBIM2 Masks */
-#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
-#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
-#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
-#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
-#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
-#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
-#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
-#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
-#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
-#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
-#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
-#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
-#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
-#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
-#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
-#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
-
-/* CAN_GIM Masks */
-#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
-#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
-#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
-#define BOIM 0x0008 /* Enable Bus Off Interrupt */
-#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
-#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
-#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
-#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
-#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
-#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
-#define ADIM 0x0400 /* Enable Access Denied Interrupt */
-
-/* CAN_GIS Masks */
-#define EWTIS 0x0001 /* TX Error Count IRQ Status */
-#define EWRIS 0x0002 /* RX Error Count IRQ Status */
-#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
-#define BOIS 0x0008 /* Bus Off IRQ Status */
-#define WUIS 0x0010 /* Wake-Up IRQ Status */
-#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
-#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
-#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
-#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
-#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
-#define ADIS 0x0400 /* Access Denied IRQ Status */
-
-/* CAN_GIF Masks */
-#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
-#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
-#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
-#define BOIF 0x0008 /* Bus Off IRQ Flag */
-#define WUIF 0x0010 /* Wake-Up IRQ Flag */
-#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
-#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
-#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
-#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
-#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
-#define ADIF 0x0400 /* Access Denied IRQ Flag */
-
-/* CAN_UCCNF Masks */
-#define UCCNF 0x000F /* Universal Counter Mode */
-#define UC_STAMP 0x0001 /* Timestamp Mode */
-#define UC_WDOG 0x0002 /* Watchdog Mode */
-#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
-#define UC_ERROR 0x0006 /* CAN Error Frame Count */
-#define UC_OVER 0x0007 /* CAN Overload Frame Count */
-#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
-#define UC_AA 0x0009 /* TX Abort Count */
-#define UC_TA 0x000A /* TX Successful Count */
-#define UC_REJECT 0x000B /* RX Message Rejected Count */
-#define UC_RML 0x000C /* RX Message Lost Count */
-#define UC_RX 0x000D /* Total Successful RX Messages Count */
-#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
-#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
-#define UCRC 0x0020 /* Universal Counter Reload/Clear */
-#define UCCT 0x0040 /* Universal Counter CAN Trigger */
-#define UCE 0x0080 /* Universal Counter Enable */
-
-/* CAN_ESR Masks */
-#define ACKE 0x0004 /* Acknowledge Error */
-#define SER 0x0008 /* Stuff Error */
-#define CRCE 0x0010 /* CRC Error */
-#define SA0 0x0020 /* Stuck At Dominant Error */
-#define BEF 0x0040 /* Bit Error Flag */
-#define FER 0x0080 /* Form Error Flag */
-
-/* CAN_EWR Masks */
-#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
-#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
deleted file mode 100644
index 6319f4e..0000000
--- a/arch/blackfin/include/asm/bfin_dma.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * bfin_dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_DMA_H__
-#define __ASM_BFIN_DMA_H__
-
-#include <linux/types.h>
-
-/* DMA_CONFIG Masks */
-#define DMAEN 0x0001 /* DMA Channel Enable */
-#define WNR 0x0002 /* Channel Direction (W/R*) */
-#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
-#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
-
-#ifdef CONFIG_BF60x
-
-#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
-#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
-#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
-#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
-#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
-#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
-#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
-#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
-#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
-#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
-#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */
-#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */
-#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */
-#define DI_EN DI_EN_X /* Data Interrupt Enable */
-#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */
-#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */
-#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */
-#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */
-#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */
-#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */
-#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */
-#define NDSIZE 0x00070000 /* Next Descriptor Size */
-#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */
-#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */
-#define DMAFLOW_LARGE DMAFLOW_LIST
-#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */
-#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */
-#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */
-#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */
-#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */
-#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */
-#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */
-
-#else
-
-#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */
-#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */
-#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
-#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
-#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
-#define RESTART 0x0020 /* DMA Buffer Clear */
-#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
-#define DI_EN 0x0080 /* Data Interrupt Enable */
-#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/
-#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/
-#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
-#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
-#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
-#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
-#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
-#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
-#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
-#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
-#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
-#define NDSIZE 0x0f00 /* Next Descriptor Size */
-#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */
-#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
-#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
-#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
-#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
-
-#endif
-#define DMAFLOW 0x7000 /* Flow Control */
-#define DMAFLOW_STOP 0x0000 /* Stop Mode */
-#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
-
-/* DMA_IRQ_STATUS Masks */
-#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
-#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
-#ifdef CONFIG_BF60x
-#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */
-#else
-#define DMA_PIRQ 0
-#endif
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin dma registers layout
- */
-struct bfin_dma_regs {
- u32 next_desc_ptr;
- u32 start_addr;
-#ifdef CONFIG_BF60x
- u32 cfg;
- u32 x_count;
- u32 x_modify;
- u32 y_count;
- u32 y_modify;
- u32 pad1;
- u32 pad2;
- u32 curr_desc_ptr;
- u32 prev_desc_ptr;
- u32 curr_addr;
- u32 irq_status;
- u32 curr_x_count;
- u32 curr_y_count;
- u32 pad3;
- u32 bw_limit_count;
- u32 curr_bw_limit_count;
- u32 bw_monitor_count;
- u32 curr_bw_monitor_count;
-#else
- __BFP(config);
- u32 __pad0;
- __BFP(x_count);
- __BFP(x_modify);
- __BFP(y_count);
- __BFP(y_modify);
- u32 curr_desc_ptr;
- u32 curr_addr;
- __BFP(irq_status);
- __BFP(peripheral_map);
- __BFP(curr_x_count);
- u32 __pad1;
- __BFP(curr_y_count);
- u32 __pad2;
-#endif
-};
-
-#ifndef CONFIG_BF60x
-/*
- * bfin handshake mdma registers layout
- */
-struct bfin_hmdma_regs {
- __BFP(control);
- __BFP(ecinit);
- __BFP(bcinit);
- __BFP(ecurgent);
- __BFP(ecoverflow);
- __BFP(ecount);
- __BFP(bcount);
-};
-#endif
-
-#undef __BFP
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h
deleted file mode 100644
index bf52e1f..0000000
--- a/arch/blackfin/include/asm/bfin_pfmon.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Blackfin Performance Monitor definitions
- *
- * Copyright 2005-2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or GPL-2 (or later).
- */
-
-#ifndef __ASM_BFIN_PFMON_H__
-#define __ASM_BFIN_PFMON_H__
-
-/* PFCTL Masks */
-#define PFMON_MASK 0xff
-#define PFCEN_MASK 0x3
-#define PFCEN_DISABLE 0x0
-#define PFCEN_ENABLE_USER 0x1
-#define PFCEN_ENABLE_SUPV 0x2
-#define PFCEN_ENABLE_ALL (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV)
-
-#define PFPWR_P 0
-#define PEMUSW0_P 2
-#define PFCEN0_P 3
-#define PFMON0_P 5
-#define PEMUSW1_P 13
-#define PFCEN1_P 14
-#define PFMON1_P 16
-#define PFCNT0_P 24
-#define PFCNT1_P 25
-
-#define PFPWR (1 << PFPWR_P)
-#define PEMUSW(n, x) ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P))
-#define PEMUSW0 PEMUSW(0, 1)
-#define PEMUSW1 PEMUSW(1, 1)
-#define PFCEN(n, x) ((x) << ((n) ? PFCEN1_P : PFCEN0_P))
-#define PFCEN0 PFCEN(0, PFCEN_MASK)
-#define PFCEN1 PFCEN(1, PFCEN_MASK)
-#define PFCNT(n, x) ((x) << ((n) ? PFCNT1_P : PFCNT0_P))
-#define PFCNT0 PFCNT(0, 1)
-#define PFCNT1 PFCNT(1, 1)
-#define PFMON(n, x) ((x) << ((n) ? PFMON1_P : PFMON0_P))
-#define PFMON0 PFMON(0, PFMON_MASK)
-#define PFMON1 PFMON(1, PFMON_MASK)
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h
deleted file mode 100644
index a4e872e..0000000
--- a/arch/blackfin/include/asm/bfin_ppi.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * bfin_ppi.h - interface to Blackfin PPIs
- *
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_PPI_H__
-#define __ASM_BFIN_PPI_H__
-
-#include <linux/types.h>
-#include <asm/blackfin.h>
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin ppi registers layout
- */
-struct bfin_ppi_regs {
- __BFP(control);
- __BFP(status);
- __BFP(count);
- __BFP(delay);
- __BFP(frame);
-};
-
-/*
- * bfin eppi registers layout
- */
-struct bfin_eppi_regs {
- __BFP(status);
- __BFP(hcount);
- __BFP(hdelay);
- __BFP(vcount);
- __BFP(vdelay);
- __BFP(frame);
- __BFP(line);
- __BFP(clkdiv);
- u32 control;
- u32 fs1w_hbl;
- u32 fs1p_avpl;
- u32 fs2w_lvb;
- u32 fs2p_lavf;
- u32 clip;
-};
-
-/*
- * bfin eppi3 registers layout
- */
-struct bfin_eppi3_regs {
- u32 stat;
- u32 hcnt;
- u32 hdly;
- u32 vcnt;
- u32 vdly;
- u32 frame;
- u32 line;
- u32 clkdiv;
- u32 ctl;
- u32 fs1_wlhb;
- u32 fs1_paspl;
- u32 fs2_wlvb;
- u32 fs2_palpf;
- u32 imsk;
- u32 oddclip;
- u32 evenclip;
- u32 fs1_dly;
- u32 fs2_dly;
- u32 ctl2;
-};
-
-#undef __BFP
-
-#ifdef EPPI0_CTL2
-#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */
-#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */
-#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */
-#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */
-#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */
-#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */
-#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */
-#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */
-#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */
-#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */
-
-#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */
-
-#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */
-
-#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */
-
-#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */
-
-#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */
-
-#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */
-
-#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */
-
-#define EPPI_CTL_EN 0x00000001 /* PPI Enable */
-#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */
-#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */
-#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */
-#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */
-#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
-#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
-#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */
-#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */
-#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */
-#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */
-#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */
-#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */
-#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */
-#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
-#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */
-#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */
-#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */
-#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */
-#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */
-#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */
-#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */
-#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */
-#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */
-#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */
-#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */
-#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */
-#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */
-#define EPPI_CTL_DLEN 0x00070000 /* Data Length */
-#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */
-#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */
-#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */
-#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */
-#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */
-#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */
-#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */
-#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */
-#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */
-#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */
-#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */
-#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */
-#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */
-#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */
-#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */
-#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */
-#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */
-#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
-#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */
-#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */
-#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
-
-#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
-#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
-#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
-#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
-
-#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */
-#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */
-
-#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */
-#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */
-#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */
-#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */
-#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */
-#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */
-#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */
-#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */
-
-#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000
-#define EPPI_ODDCLIP_LOWODD 0x0000FFFF
-
-#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000
-#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF
-
-#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h
deleted file mode 100644
index a99957e..0000000
--- a/arch/blackfin/include/asm/bfin_sdh.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Blackfin Secure Digital Host (SDH) definitions
- *
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_SDH_H__
-#define __BFIN_SDH_H__
-
-/* Platform resources */
-struct bfin_sd_host {
- int dma_chan;
- int irq_int0;
- int irq_int1;
- u16 pin_req[7];
-};
-
-/* SDH_COMMAND bitmasks */
-#define CMD_IDX 0x3f /* Command Index */
-#define CMD_RSP (1 << 6) /* Response */
-#define CMD_L_RSP (1 << 7) /* Long Response */
-#define CMD_INT_E (1 << 8) /* Command Interrupt */
-#define CMD_PEND_E (1 << 9) /* Command Pending */
-#define CMD_E (1 << 10) /* Command Enable */
-#ifdef RSI_BLKSZ
-#define CMD_CRC_CHECK_D (1 << 11) /* CRC Check is disabled */
-#define CMD_DATA0_BUSY (1 << 12) /* Check for Busy State on the DATA0 pin */
-#endif
-
-/* SDH_PWR_CTL bitmasks */
-#ifndef RSI_BLKSZ
-#define PWR_ON 0x3 /* Power On */
-#define SD_CMD_OD (1 << 6) /* Open Drain Output */
-#define ROD_CTL (1 << 7) /* Rod Control */
-#endif
-
-/* SDH_CLK_CTL bitmasks */
-#define CLKDIV 0xff /* MC_CLK Divisor */
-#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
-#define PWR_SV_E (1 << 9) /* Power Save Enable */
-#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
-#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
-#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
-#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
-#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
-
-/* SDH_RESP_CMD bitmasks */
-#define RESP_CMD 0x3f /* Response Command */
-
-/* SDH_DATA_CTL bitmasks */
-#define DTX_E (1 << 0) /* Data Transfer Enable */
-#define DTX_DIR (1 << 1) /* Data Transfer Direction */
-#define DTX_MODE (1 << 2) /* Data Transfer Mode */
-#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
-#ifndef RSI_BLKSZ
-#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
-#else
-
-/* Bit masks for SDH_BLK_SIZE */
-#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
-#endif
-
-/* SDH_STATUS bitmasks */
-#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
-#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */
-#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */
-#define DAT_TIME_OUT (1 << 3) /* Data Time Out */
-#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */
-#define RX_OVERRUN (1 << 5) /* Receive Overrun */
-#define CMD_RESP_END (1 << 6) /* CMD Response End */
-#define CMD_SENT (1 << 7) /* CMD Sent */
-#define DAT_END (1 << 8) /* Data End */
-#define START_BIT_ERR (1 << 9) /* Start Bit Error */
-#define DAT_BLK_END (1 << 10) /* Data Block End */
-#define CMD_ACT (1 << 11) /* CMD Active */
-#define TX_ACT (1 << 12) /* Transmit Active */
-#define RX_ACT (1 << 13) /* Receive Active */
-#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */
-#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */
-#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */
-#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */
-#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */
-#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */
-#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */
-#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */
-
-/* SDH_STATUS_CLR bitmasks */
-#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */
-#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */
-#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */
-#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */
-#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */
-#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */
-#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */
-#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */
-#define DAT_END_STAT (1 << 8) /* Data End Status */
-#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */
-#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */
-
-/* SDH_MASK0 bitmasks */
-#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */
-#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */
-#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */
-#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */
-#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */
-#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */
-#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */
-#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */
-#define DAT_END_MASK (1 << 8) /* Data End Mask */
-#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */
-#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */
-#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */
-#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */
-#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */
-#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */
-#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */
-#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */
-#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */
-#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */
-#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */
-#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */
-#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */
-
-/* SDH_FIFO_CNT bitmasks */
-#define FIFO_COUNT 0x7fff /* FIFO Count */
-
-/* SDH_E_STATUS bitmasks */
-#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
-#define SD_CARD_DET (1 << 4) /* SD Card Detect */
-#define SD_CARD_BUSYMODE (1 << 31) /* Card is in Busy mode */
-#define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */
-#define SD_CARD_READY (1 << 17) /* Card Ready */
-
-/* SDH_E_MASK bitmasks */
-#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
-#define SCD_MSK (1 << 4) /* Mask Card Detect */
-#define CARD_READY_MSK (1 << 16) /* Mask Card Ready */
-
-/* SDH_CFG bitmasks */
-#define CLKS_EN (1 << 0) /* Clocks Enable */
-#define SD4E (1 << 2) /* SDIO 4-Bit Enable */
-#define MWE (1 << 3) /* Moving Window Enable */
-#define SD_RST (1 << 4) /* SDMMC Reset */
-#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
-#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
-#ifndef RSI_BLKSZ
-#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
-#else
-#define PWR_ON 0x600 /* Power On */
-#define SD_CMD_OD (1 << 11) /* Open Drain Output */
-#define BOOT_EN (1 << 12) /* Boot Enable */
-#define BOOT_MODE (1 << 13) /* Alternate Boot Mode */
-#define BOOT_ACK_EN (1 << 14) /* Boot ACK is expected */
-#endif
-
-/* SDH_RD_WAIT_EN bitmasks */
-#define RWR (1 << 0) /* Read Wait Request */
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
deleted file mode 100644
index b550ada..0000000
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_ASM_SERIAL_H__
-#define __BFIN_ASM_SERIAL_H__
-
-#include <linux/circ_buf.h>
-#include <linux/serial_core.h>
-#include <linux/spinlock.h>
-#include <linux/timer.h>
-#include <linux/workqueue.h>
-#include <mach/anomaly.h>
-#include <mach/bfin_serial.h>
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
- defined(CONFIG_BFIN_UART1_CTSRTS) || \
- defined(CONFIG_BFIN_UART2_CTSRTS) || \
- defined(CONFIG_BFIN_UART3_CTSRTS)
-# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
-# define SERIAL_BFIN_HARD_CTSRTS
-# else
-# define SERIAL_BFIN_CTSRTS
-# endif
-#endif
-
-struct bfin_serial_port {
- struct uart_port port;
- unsigned int old_status;
- int tx_irq;
- int rx_irq;
- int status_irq;
-#ifndef BFIN_UART_BF54X_STYLE
- unsigned int lsr;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_DMA
- int tx_done;
- int tx_count;
- struct circ_buf rx_dma_buf;
- struct timer_list rx_dma_timer;
- int rx_dma_nrows;
- spinlock_t rx_lock;
- unsigned int tx_dma_channel;
- unsigned int rx_dma_channel;
- struct work_struct tx_dma_workqueue;
-#elif ANOMALY_05000363
- unsigned int anomaly_threshold;
-#endif
-#if defined(SERIAL_BFIN_CTSRTS) || \
- defined(SERIAL_BFIN_HARD_CTSRTS)
- int cts_pin;
- int rts_pin;
-#endif
-};
-
-#ifdef BFIN_UART_BF60X_STYLE
-
-/* UART_CTL Masks */
-#define UCEN 0x1 /* Enable UARTx Clocks */
-#define LOOP_ENA 0x2 /* Loopback Mode Enable */
-#define UMOD_MDB 0x10 /* Enable MDB Mode */
-#define UMOD_IRDA 0x20 /* Enable IrDA Mode */
-#define UMOD_MASK 0x30 /* Uart Mode Mask */
-#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
-#define WLS_MASK 0x300 /* Word length Select Mask */
-#define WLS_OFFSET 8 /* Word length Select Offset */
-#define STB 0x1000 /* Stop Bits */
-#define STBH 0x2000 /* Half Stop Bits */
-#define PEN 0x4000 /* Parity Enable */
-#define EPS 0x8000 /* Even Parity Select */
-#define STP 0x10000 /* Stick Parity */
-#define FPE 0x20000 /* Force Parity Error On Transmit */
-#define FFE 0x40000 /* Force Framing Error On Transmit */
-#define SB 0x80000 /* Set Break */
-#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
-#define FCPOL 0x400000 /* Flow Control Pin Polarity */
-#define RPOLC 0x800000 /* IrDA RX Polarity Change */
-#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
-#define MRTS 0x2000000 /* Manual Request To Send */
-#define XOFF 0x4000000 /* Transmitter Off */
-#define ARTS 0x8000000 /* Automatic Request To Send */
-#define ACTS 0x10000000 /* Automatic Clear To Send */
-#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
-#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
-
-/* UART_STAT Masks */
-#define DR 0x01 /* Data Ready */
-#define OE 0x02 /* Overrun Error */
-#define PE 0x04 /* Parity Error */
-#define FE 0x08 /* Framing Error */
-#define BI 0x10 /* Break Interrupt */
-#define THRE 0x20 /* THR Empty */
-#define TEMT 0x80 /* TSR and UART_THR Empty */
-#define TFI 0x100 /* Transmission Finished Indicator */
-
-#define ASTKY 0x200 /* Address Sticky */
-#define ADDR 0x400 /* Address bit status */
-#define RO 0x800 /* Reception Ongoing */
-#define SCTS 0x1000 /* Sticky CTS */
-#define CTS 0x10000 /* Clear To Send */
-#define RFCS 0x20000 /* Receive FIFO Count Status */
-
-/* UART_CLOCK Masks */
-#define EDBO 0x80000000 /* Enable Devide by One */
-
-#else /* BFIN_UART_BF60X_STYLE */
-
-/* UART_LCR Masks */
-#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
-#define WLS_MASK 0x03 /* Word length Select Mask */
-#define WLS_OFFSET 0 /* Word length Select Offset */
-#define STB 0x04 /* Stop Bits */
-#define PEN 0x08 /* Parity Enable */
-#define EPS 0x10 /* Even Parity Select */
-#define STP 0x20 /* Stick Parity */
-#define SB 0x40 /* Set Break */
-#define DLAB 0x80 /* Divisor Latch Access */
-#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
-
-/* UART_LSR Masks */
-#define DR 0x01 /* Data Ready */
-#define OE 0x02 /* Overrun Error */
-#define PE 0x04 /* Parity Error */
-#define FE 0x08 /* Framing Error */
-#define BI 0x10 /* Break Interrupt */
-#define THRE 0x20 /* THR Empty */
-#define TEMT 0x40 /* TSR and UART_THR Empty */
-#define TFI 0x80 /* Transmission Finished Indicator */
-
-/* UART_MCR Masks */
-#define XOFF 0x01 /* Transmitter Off */
-#define MRTS 0x02 /* Manual Request To Send */
-#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
-#define RFRT 0x08 /* Receive FIFO RTS Threshold */
-#define LOOP_ENA 0x10 /* Loopback Mode Enable */
-#define FCPOL 0x20 /* Flow Control Pin Polarity */
-#define ARTS 0x40 /* Automatic Request To Send */
-#define ACTS 0x80 /* Automatic Clear To Send */
-
-/* UART_MSR Masks */
-#define SCTS 0x01 /* Sticky CTS */
-#define CTS 0x10 /* Clear To Send */
-#define RFCS 0x20 /* Receive FIFO Count Status */
-
-/* UART_GCTL Masks */
-#define UCEN 0x01 /* Enable UARTx Clocks */
-#define UMOD_IRDA 0x02 /* Enable IrDA Mode */
-#define UMOD_MASK 0x02 /* Uart Mode Mask */
-#define TPOLC 0x04 /* IrDA TX Polarity Change */
-#define RPOLC 0x08 /* IrDA RX Polarity Change */
-#define FPE 0x10 /* Force Parity Error On Transmit */
-#define FFE 0x20 /* Force Framing Error On Transmit */
-
-#endif /* BFIN_UART_BF60X_STYLE */
-
-/* UART_IER Masks */
-#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
-#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
-#define ELSI 0x04 /* Enable RX Status Interrupt */
-#define EDSSI 0x08 /* Enable Modem Status Interrupt */
-#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
-#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
-#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
-
-#if defined(BFIN_UART_BF60X_STYLE)
-# define OFFSET_REDIV 0x00 /* Version ID Register */
-# define OFFSET_CTL 0x04 /* Control Register */
-# define OFFSET_STAT 0x08 /* Status Register */
-# define OFFSET_SCR 0x0C /* SCR Scratch Register */
-# define OFFSET_CLK 0x10 /* Clock Rate Register */
-# define OFFSET_IER 0x14 /* Interrupt Enable Register */
-# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */
-# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */
-# define OFFSET_RBR 0x20 /* Receive Buffer register */
-# define OFFSET_THR 0x24 /* Transmit Holding register */
-#elif defined(BFIN_UART_BF54X_STYLE)
-# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-# define OFFSET_GCTL 0x08 /* Global Control Register */
-# define OFFSET_LCR 0x0C /* Line Control Register */
-# define OFFSET_MCR 0x10 /* Modem Control Register */
-# define OFFSET_LSR 0x14 /* Line Status Register */
-# define OFFSET_MSR 0x18 /* Modem Status Register */
-# define OFFSET_SCR 0x1C /* SCR Scratch Register */
-# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
-# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
-# define OFFSET_THR 0x28 /* Transmit Holding register */
-# define OFFSET_RBR 0x2C /* Receive Buffer register */
-#else /* BF533 style */
-# define OFFSET_THR 0x00 /* Transmit Holding register */
-# define OFFSET_RBR 0x00 /* Receive Buffer register */
-# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-# define OFFSET_IER 0x04 /* Interrupt Enable Register */
-# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-# define OFFSET_LCR 0x0C /* Line Control Register */
-# define OFFSET_MCR 0x10 /* Modem Control Register */
-# define OFFSET_LSR 0x14 /* Line Status Register */
-# define OFFSET_MSR 0x18 /* Modem Status Register */
-# define OFFSET_SCR 0x1C /* SCR Scratch Register */
-# define OFFSET_GCTL 0x24 /* Global Control Register */
-/* code should not need IIR, so force build error if they use it */
-# undef OFFSET_IIR
-#endif
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-struct bfin_uart_regs {
-#if defined(BFIN_UART_BF60X_STYLE)
- u32 revid;
- u32 ctl;
- u32 stat;
- u32 scr;
- u32 clk;
- u32 ier;
- u32 ier_set;
- u32 ier_clear;
- u32 rbr;
- u32 thr;
- u32 taip;
- u32 tsr;
- u32 rsr;
- u32 txdiv;
- u32 rxdiv;
-#elif defined(BFIN_UART_BF54X_STYLE)
- __BFP(dll);
- __BFP(dlh);
- __BFP(gctl);
- __BFP(lcr);
- __BFP(mcr);
- __BFP(lsr);
- __BFP(msr);
- __BFP(scr);
- __BFP(ier_set);
- __BFP(ier_clear);
- __BFP(thr);
- __BFP(rbr);
-#else
- union {
- u16 dll;
- u16 thr;
- const u16 rbr;
- };
- const u16 __pad0;
- union {
- u16 dlh;
- u16 ier;
- };
- const u16 __pad1;
- const __BFP(iir);
- __BFP(lcr);
- __BFP(mcr);
- __BFP(lsr);
- __BFP(msr);
- __BFP(scr);
- const u32 __pad2;
- __BFP(gctl);
-#endif
-};
-#undef __BFP
-
-#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
-
-/*
-#ifndef port_membase
-# define port_membase(p) 0
-#endif
-*/
-#ifdef BFIN_UART_BF60X_STYLE
-
-#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
-#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
-#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
-#define UART_GET_GCTL(p) UART_GET_CTL(p)
-#define UART_GET_LCR(p) UART_GET_CTL(p)
-#define UART_GET_MCR(p) UART_GET_CTL(p)
-#if ANOMALY_16000030
-#define UART_GET_STAT(p) \
-({ \
- u32 __ret; \
- unsigned long flags; \
- flags = hard_local_irq_save(); \
- __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \
- hard_local_irq_restore(flags); \
- __ret; \
-})
-#else
-#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
-#endif
-#define UART_GET_MSR(p) UART_GET_STAT(p)
-
-#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
-#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
-#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
-#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
-
-#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
-#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
-#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
-
-#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */
-#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */
-
-#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
-#define UART_GET_LSR(p) UART_GET_STAT(p)
-#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
-
-/* This handles hard CTS/RTS */
-#define BFIN_UART_CTSRTS_HARD
-#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
-#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
-#else /* BFIN_UART_BF60X_STYLE */
-
-#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
-#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
-#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
-#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
-#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
-#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
-#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
-#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
-
-#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
-#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
-#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
-#define UART_PUT_CLK(p, v) do \
-{\
-UART_PUT_DLL(p, v & 0xFF); \
-UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
-
-#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
-#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
-#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
-
-#ifdef BFIN_UART_BF54X_STYLE
-
-#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
-#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
-#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
-
-#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
-#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
-
-#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
-#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
-#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
-
-/* This handles hard CTS/RTS */
-#define BFIN_UART_CTSRTS_HARD
-#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
-#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
-#else /* BF533 style */
-
-#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
-#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
-#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
-#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
-
-#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
-#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
-
-#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
-#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
-
-/*
-#ifndef put_lsr_cache
-# define put_lsr_cache(p, v)
-#endif
-#ifndef get_lsr_cache
-# define get_lsr_cache(p) 0
-#endif
-*/
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline void UART_CLEAR_LSR(void *p)
-{
- put_lsr_cache(p, 0);
- bfin_write16(port_membase(p) + OFFSET_LSR, -1);
-}
-static inline unsigned int UART_GET_LSR(void *p)
-{
- unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
- put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
- return lsr | get_lsr_cache(p);
-}
-static inline void UART_PUT_LSR(void *p, uint16_t val)
-{
- put_lsr_cache(p, get_lsr_cache(p) & ~val);
-}
-
-/* This handles soft CTS/RTS */
-#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#endif /* BFIN_UART_BF54X_STYLE */
-
-#endif /* BFIN_UART_BF60X_STYLE */
-
-#ifndef BFIN_UART_TX_FIFO_SIZE
-# define BFIN_UART_TX_FIFO_SIZE 2
-#endif
-
-#endif /* __BFIN_ASM_SERIAL_H__ */
diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h
deleted file mode 100644
index b2d5e73..0000000
--- a/arch/blackfin/include/asm/bfin_simple_timer.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _bfin_simple_timer_h_
-#define _bfin_simple_timer_h_
-
-#include <linux/ioctl.h>
-
-#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
-
-#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2)
-#define BFIN_SIMPLE_TIMER_SET_WIDTH _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 3)
-#define BFIN_SIMPLE_TIMER_SET_MODE _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 4)
-#define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6)
-#define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8)
-#define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
-#define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11)
-
-#define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT 0
-#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT 1
-#define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP 2
-#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ 3
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
deleted file mode 100644
index 50b9dfd..0000000
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * bfin_sport.h - interface to Blackfin SPORTs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __BFIN_SPORT_H__
-#define __BFIN_SPORT_H__
-
-
-#include <linux/types.h>
-#include <uapi/asm/bfin_sport.h>
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-struct sport_register {
- __BFP(tcr1);
- __BFP(tcr2);
- __BFP(tclkdiv);
- __BFP(tfsdiv);
- union {
- u32 tx32;
- u16 tx16;
- };
- u32 __pad_tx;
- union {
- u32 rx32; /* use the anomaly wrapper below */
- u16 rx16;
- };
- u32 __pad_rx;
- __BFP(rcr1);
- __BFP(rcr2);
- __BFP(rclkdiv);
- __BFP(rfsdiv);
- __BFP(stat);
- __BFP(chnl);
- __BFP(mcmc1);
- __BFP(mcmc2);
- u32 mtcs0;
- u32 mtcs1;
- u32 mtcs2;
- u32 mtcs3;
- u32 mrcs0;
- u32 mrcs1;
- u32 mrcs2;
- u32 mrcs3;
-};
-#undef __BFP
-
-struct bfin_snd_platform_data {
- const unsigned short *pin_req;
-};
-
-#define bfin_read_sport_rx32(base) \
-({ \
- struct sport_register *__mmrs = (void *)base; \
- u32 __ret; \
- unsigned long flags; \
- if (ANOMALY_05000473) \
- local_irq_save(flags); \
- __ret = __mmrs->rx32; \
- if (ANOMALY_05000473) \
- local_irq_restore(flags); \
- __ret; \
-})
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_sport3.h b/arch/blackfin/include/asm/bfin_sport3.h
deleted file mode 100644
index d82f5fa..0000000
--- a/arch/blackfin/include/asm/bfin_sport3.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * bfin_sport - Analog Devices BF6XX SPORT registers
- *
- * Copyright (c) 2012 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _BFIN_SPORT3_H_
-#define _BFIN_SPORT3_H_
-
-#include <linux/types.h>
-
-#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */
-#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */
-#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */
-#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */
-#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */
-#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */
-#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */
-#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */
-#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */
-#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */
-#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */
-#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */
-#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */
-#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */
-#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */
-#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */
-#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */
-#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */
-#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */
-#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrupt enable select */
-#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */
-#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */
-#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */
-#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */
-#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */
-#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */
-#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */
-#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */
-#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */
-#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */
-#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */
-#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */
-#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */
-
-#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */
-#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */
-
-#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */
-#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */
-#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */
-#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */
-#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */
-
-#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */
-#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */
-
-#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */
-#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */
-#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */
-#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */
-#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */
-#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */
-
-#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */
-
-#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */
-#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */
-#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */
-
-struct sport_register {
- u32 spctl;
- u32 div;
- u32 spmctl;
- u32 spcs0;
- u32 spcs1;
- u32 spcs2;
- u32 spcs3;
- u32 spcnt;
- u32 sperrctl;
- u32 spmstat;
- u32 spctl2;
- u32 txa;
- u32 rxa;
- u32 txb;
- u32 rxb;
- u32 revid;
-};
-
-struct bfin_snd_platform_data {
- const unsigned short *pin_req;
-};
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
deleted file mode 100644
index 211e9c7..0000000
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * bfin_twi.h - interface to Blackfin TWIs
- *
- * Copyright 2005-2014 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_TWI_H__
-#define __ASM_BFIN_TWI_H__
-
-#include <asm/blackfin.h>
-#include <linux/types.h>
-#include <linux/i2c.h>
-
-/*
- * ADI twi registers layout
- */
-struct bfin_twi_regs {
- u16 clkdiv;
- u16 dummy1;
- u16 control;
- u16 dummy2;
- u16 slave_ctl;
- u16 dummy3;
- u16 slave_stat;
- u16 dummy4;
- u16 slave_addr;
- u16 dummy5;
- u16 master_ctl;
- u16 dummy6;
- u16 master_stat;
- u16 dummy7;
- u16 master_addr;
- u16 dummy8;
- u16 int_stat;
- u16 dummy9;
- u16 int_mask;
- u16 dummy10;
- u16 fifo_ctl;
- u16 dummy11;
- u16 fifo_stat;
- u16 dummy12;
- u32 __pad[20];
- u16 xmt_data8;
- u16 dummy13;
- u16 xmt_data16;
- u16 dummy14;
- u16 rcv_data8;
- u16 dummy15;
- u16 rcv_data16;
- u16 dummy16;
-};
-
-struct bfin_twi_iface {
- int irq;
- spinlock_t lock;
- char read_write;
- u8 command;
- u8 *transPtr;
- int readNum;
- int writeNum;
- int cur_mode;
- int manual_stop;
- int result;
- struct i2c_adapter adap;
- struct completion complete;
- struct i2c_msg *pmsg;
- int msg_num;
- int cur_msg;
- u16 saved_clkdiv;
- u16 saved_control;
- struct bfin_twi_regs __iomem *regs_base;
-};
-
-/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
-#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
-#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
-
-/* TWI_PRESCALE Masks */
-#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
-#define TWI_ENA 0x0080 /* TWI Enable */
-#define SCCB 0x0200 /* SCCB Compatibility Enable */
-
-/* TWI_SLAVE_CTL Masks */
-#define SEN 0x0001 /* Slave Enable */
-#define SADD_LEN 0x0002 /* Slave Address Length */
-#define STDVAL 0x0004 /* Slave Transmit Data Valid */
-#define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */
-#define GEN 0x0010 /* General Call Address Matching Enabled */
-
-/* TWI_SLAVE_STAT Masks */
-#define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */
-#define GCALL 0x0002 /* General Call Indicator */
-
-/* TWI_MASTER_CTL Masks */
-#define MEN 0x0001 /* Master Mode Enable */
-#define MADD_LEN 0x0002 /* Master Address Length */
-#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
-#define FAST 0x0008 /* Use Fast Mode Timing Specs */
-#define STOP 0x0010 /* Issue Stop Condition */
-#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
-#define DCNT 0x3FC0 /* Data Bytes To Transfer */
-#define SDAOVR 0x4000 /* Serial Data Override */
-#define SCLOVR 0x8000 /* Serial Clock Override */
-
-/* TWI_MASTER_STAT Masks */
-#define MPROG 0x0001 /* Master Transfer In Progress */
-#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
-#define ANAK 0x0004 /* Address Not Acknowledged */
-#define DNAK 0x0008 /* Data Not Acknowledged */
-#define BUFRDERR 0x0010 /* Buffer Read Error */
-#define BUFWRERR 0x0020 /* Buffer Write Error */
-#define SDASEN 0x0040 /* Serial Data Sense */
-#define SCLSEN 0x0080 /* Serial Clock Sense */
-#define BUSBUSY 0x0100 /* Bus Busy Indicator */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
-#define SINIT 0x0001 /* Slave Transfer Initiated */
-#define SCOMP 0x0002 /* Slave Transfer Complete */
-#define SERR 0x0004 /* Slave Transfer Error */
-#define SOVF 0x0008 /* Slave Overflow */
-#define MCOMP 0x0010 /* Master Transfer Complete */
-#define MERR 0x0020 /* Master Transfer Error */
-#define XMTSERV 0x0040 /* Transmit FIFO Service */
-#define RCVSERV 0x0080 /* Receive FIFO Service */
-
-/* TWI_FIFO_CTRL Masks */
-#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
-#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
-#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
-#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
-
-/* TWI_FIFO_STAT Masks */
-#define XMTSTAT 0x0003 /* Transmit FIFO Status */
-#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
-#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
-#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
-
-#define RCVSTAT 0x000C /* Receive FIFO Status */
-#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
-#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
-#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
-
-#define DEFINE_TWI_REG(reg_name, reg) \
-static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
- { return bfin_read16(&iface->regs_base->reg); } \
-static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
- { bfin_write16(&iface->regs_base->reg, v); }
-
-DEFINE_TWI_REG(CLKDIV, clkdiv)
-DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
-DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
-DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
-DEFINE_TWI_REG(MASTER_CTL, master_ctl)
-DEFINE_TWI_REG(MASTER_STAT, master_stat)
-DEFINE_TWI_REG(MASTER_ADDR, master_addr)
-DEFINE_TWI_REG(INT_STAT, int_stat)
-DEFINE_TWI_REG(INT_MASK, int_mask)
-DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
-DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
-DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
-#if !ANOMALY_16000030
-DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
-DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
-#else
-static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
-{
- u16 ret;
- unsigned long flags;
-
- flags = hard_local_irq_save();
- ret = bfin_read16(&iface->regs_base->rcv_data8);
- hard_local_irq_restore(flags);
-
- return ret;
-}
-
-static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
-{
- u16 ret;
- unsigned long flags;
-
- flags = hard_local_irq_save();
- ret = bfin_read16(&iface->regs_base->rcv_data16);
- hard_local_irq_restore(flags);
-
- return ret;
-}
-#endif
-
-static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface)
-{
- return bfin_read16(&iface->regs_base->fifo_ctl);
-}
-
-static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v)
-{
- bfin_write16(&iface->regs_base->fifo_ctl, v);
- SSYNC();
-}
-
-static inline u16 read_CONTROL(struct bfin_twi_iface *iface)
-{
- return bfin_read16(&iface->regs_base->control);
-}
-
-static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v)
-{
- SSYNC();
- bfin_write16(&iface->regs_base->control, v);
-}
-#endif
diff --git a/arch/blackfin/include/asm/bfin_watchdog.h b/arch/blackfin/include/asm/bfin_watchdog.h
deleted file mode 100644
index dce0982..0000000
--- a/arch/blackfin/include/asm/bfin_watchdog.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * bfin_watchdog.h - Blackfin watchdog definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_WATCHDOG_H
-#define _BFIN_WATCHDOG_H
-
-/* Bit in SWRST that indicates boot caused by watchdog */
-#define SWRST_RESET_WDOG 0x4000
-
-/* Bit in WDOG_CTL that indicates watchdog has expired (WDR0) */
-#define WDOG_EXPIRED 0x8000
-
-/* Masks for WDEV field in WDOG_CTL register */
-#define ICTL_RESET 0x0
-#define ICTL_NMI 0x2
-#define ICTL_GPI 0x4
-#define ICTL_NONE 0x6
-#define ICTL_MASK 0x6
-
-/* Masks for WDEN field in WDOG_CTL register */
-#define WDEN_MASK 0x0FF0
-#define WDEN_ENABLE 0x0000
-#define WDEN_DISABLE 0x0AD0
-
-#endif
diff --git a/arch/blackfin/include/asm/bfrom.h b/arch/blackfin/include/asm/bfrom.h
deleted file mode 100644
index 9e4be5e5..0000000
--- a/arch/blackfin/include/asm/bfrom.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Blackfin on-chip ROM API
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFROM_H__
-#define __BFROM_H__
-
-#include <linux/types.h>
-
-/* Possible syscontrol action flags */
-#define SYSCTRL_READ 0x00000000 /* read registers */
-#define SYSCTRL_WRITE 0x00000001 /* write registers */
-#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
-#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
-#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
-#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
-#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
-#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
-#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
-#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
-#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
-#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
-#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
-
-typedef struct ADI_SYSCTRL_VALUES {
- uint16_t uwVrCtl;
- uint16_t uwPllCtl;
- uint16_t uwPllDiv;
- uint16_t uwPllLockCnt;
- uint16_t uwPllStat;
-} ADI_SYSCTRL_VALUES;
-
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038;
-
-/* We need a dedicated function since we need to screw with the stack pointer
- * when resetting. The on-chip ROM will save/restore registers on the stack
- * when doing a system reset, so the stack cannot be outside of the chip.
- */
-__attribute__((__noreturn__))
-static inline void bfrom_SoftReset(void *new_stack)
-{
- while (1)
- /*
- * We don't declare the SP as clobbered on purpose, since
- * it confuses the heck out of the compiler, and this function
- * never returns
- */
- __asm__ __volatile__(
- "sp = %[stack];"
- "jump (%[bfrom_syscontrol]);"
- : : [bfrom_syscontrol] "p"(bfrom_SysControl),
- "q0"(SYSCTRL_SOFTRESET),
- "q1"(0),
- "q2"(NULL),
- [stack] "p"(new_stack)
- );
-}
-
-/* OTP Functions */
-static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018;
-static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A;
-static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C;
-
-/* otp command: defines for "command" */
-#define OTP_INIT 0x00000001
-#define OTP_CLOSE 0x00000002
-
-/* otp read/write: defines for "flags" */
-#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
-#define OTP_UPPER_HALF 0x00000001
-#define OTP_NO_ECC 0x00000010 /* do not use ECC */
-#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
-#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
-
-/* Return values for all functions */
-#define OTP_SUCCESS 0x00000000
-#define OTP_MASTER_ERROR 0x001
-#define OTP_WRITE_ERROR 0x003
-#define OTP_READ_ERROR 0x005
-#define OTP_ACC_VIO_ERROR 0x009
-#define OTP_DATA_MULT_ERROR 0x011
-#define OTP_ECC_MULT_ERROR 0x021
-#define OTP_PREV_WR_ERROR 0x041
-#define OTP_DATA_SB_WARN 0x100
-#define OTP_ECC_SB_WARN 0x200
-
-#endif
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
deleted file mode 100644
index b298b65..0000000
--- a/arch/blackfin/include/asm/bitops.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_BITOPS_H
-#define _BLACKFIN_BITOPS_H
-
-#include <linux/compiler.h>
-
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/find.h>
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/const_hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/ext2-atomic.h>
-
-#include <asm/barrier.h>
-
-#ifndef CONFIG_SMP
-#include <linux/irqflags.h>
-/*
- * clear_bit may not imply a memory barrier
- */
-#include <asm-generic/bitops/atomic.h>
-#include <asm-generic/bitops/non-atomic.h>
-#else
-
-#include <asm/byteorder.h> /* swab32 */
-#include <linux/linkage.h>
-
-asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_clear_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_toggle_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_set_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_clear_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_toggle_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_asm(const volatile unsigned long *addr, int nr);
-
-static inline void set_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_set_asm(a, nr & 0x1f);
-}
-
-static inline void clear_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_clear_asm(a, nr & 0x1f);
-}
-
-static inline void change_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_toggle_asm(a, nr & 0x1f);
-}
-
-static inline int test_bit(int nr, const volatile unsigned long *addr)
-{
- volatile const unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_asm(a, nr & 0x1f) != 0;
-}
-
-static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_set_asm(a, nr & 0x1f);
-}
-
-static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_clear_asm(a, nr & 0x1f);
-}
-
-static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_toggle_asm(a, nr & 0x1f);
-}
-
-#define test_bit __skip_test_bit
-#include <asm-generic/bitops/non-atomic.h>
-#undef test_bit
-
-#endif /* CONFIG_SMP */
-
-/* Needs to be after test_bit and friends */
-#include <asm-generic/bitops/le.h>
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-static inline unsigned int __arch_hweight32(unsigned int w)
-{
- unsigned int res;
-
- __asm__ ("%0.l = ONES %1;"
- "%0 = %0.l (Z);"
- : "=d" (res) : "d" (w));
- return res;
-}
-
-static inline unsigned int __arch_hweight64(__u64 w)
-{
- return __arch_hweight32((unsigned int)(w >> 32)) +
- __arch_hweight32((unsigned int)w);
-}
-
-static inline unsigned int __arch_hweight16(unsigned int w)
-{
- return __arch_hweight32(w & 0xffff);
-}
-
-static inline unsigned int __arch_hweight8(unsigned int w)
-{
- return __arch_hweight32(w & 0xff);
-}
-
-#endif /* _BLACKFIN_BITOPS_H */
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
deleted file mode 100644
index f111f36..0000000
--- a/arch/blackfin/include/asm/blackfin.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Common header file for Blackfin family of processors.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_H_
-#define _BLACKFIN_H_
-
-#include <mach/anomaly.h>
-
-#ifndef __ASSEMBLY__
-
-/* SSYNC implementation for C file */
-static inline void SSYNC(void)
-{
- int _tmp;
- if (ANOMALY_05000312 || ANOMALY_05000244)
- __asm__ __volatile__(
- "cli %0;"
- "nop;"
- "nop;"
- "nop;"
- "ssync;"
- "sti %0;"
- : "=d" (_tmp)
- );
- else
- __asm__ __volatile__("ssync;");
-}
-
-/* CSYNC implementation for C file */
-static inline void CSYNC(void)
-{
- int _tmp;
- if (ANOMALY_05000312 || ANOMALY_05000244)
- __asm__ __volatile__(
- "cli %0;"
- "nop;"
- "nop;"
- "nop;"
- "csync;"
- "sti %0;"
- : "=d" (_tmp)
- );
- else
- __asm__ __volatile__("csync;");
-}
-
-#else /* __ASSEMBLY__ */
-
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
-/* SSYNC & CSYNC implementations for assembly files */
-
-#define ssync(x) SSYNC(x)
-#define csync(x) CSYNC(x)
-
-#if ANOMALY_05000312 || ANOMALY_05000244
-#define SSYNC(scratch) \
- cli scratch; \
- nop; nop; nop; \
- SSYNC; \
- sti scratch;
-
-#define CSYNC(scratch) \
- cli scratch; \
- nop; nop; nop; \
- CSYNC; \
- sti scratch;
-
-#else
-#define SSYNC(scratch) SSYNC;
-#define CSYNC(scratch) CSYNC;
-#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm/mem_map.h>
-#include <mach/blackfin.h>
-#include <asm/bfin-global.h>
-
-#endif /* _BLACKFIN_H_ */
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
deleted file mode 100644
index 76b2e82..0000000
--- a/arch/blackfin/include/asm/bug.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_BUG_H
-#define _BLACKFIN_BUG_H
-
-#ifdef CONFIG_BUG
-
-/*
- * This can be any undefined 16-bit opcode, meaning
- * ((opcode & 0xc000) != 0xc000)
- * Anything from 0x0001 to 0x000A (inclusive) will work
- */
-#define BFIN_BUG_OPCODE 0x0001
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-
-#define _BUG_OR_WARN(flags) \
- asm volatile( \
- "1: .hword %0\n" \
- " .section __bug_table,\"aw\", at progbits\n" \
- "2: .long 1b\n" \
- " .long %1\n" \
- " .short %2\n" \
- " .short %3\n" \
- " .org 2b + %4\n" \
- " .previous" \
- : \
- : "i"(BFIN_BUG_OPCODE), "i"(__FILE__), \
- "i"(__LINE__), "i"(flags), \
- "i"(sizeof(struct bug_entry)))
-
-#else
-
-#define _BUG_OR_WARN(flags) \
- asm volatile( \
- "1: .hword %0\n" \
- " .section __bug_table,\"aw\", at progbits\n" \
- "2: .long 1b\n" \
- " .short %1\n" \
- " .org 2b + %2\n" \
- " .previous" \
- : \
- : "i"(BFIN_BUG_OPCODE), "i"(flags), \
- "i"(sizeof(struct bug_entry)))
-
-#endif /* CONFIG_DEBUG_BUGVERBOSE */
-
-#define BUG() \
- do { \
- _BUG_OR_WARN(0); \
- unreachable(); \
- } while (0)
-
-#define WARN_ON(condition) \
- ({ \
- int __ret_warn_on = !!(condition); \
- if (unlikely(__ret_warn_on)) \
- _BUG_OR_WARN(BUGFLAG_WARNING); \
- unlikely(__ret_warn_on); \
- })
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_WARN_ON
-
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
deleted file mode 100644
index 568885a..0000000
--- a/arch/blackfin/include/asm/cache.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CACHE_H
-#define __ARCH_BLACKFIN_CACHE_H
-
-#include <linux/linkage.h> /* for asmlinkage */
-
-/*
- * Bytes per L1 cache line
- * Blackfin loads 32 bytes for cache
- */
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-
-#ifdef CONFIG_SMP
-#define __cacheline_aligned
-#else
-#define ____cacheline_aligned
-
-/*
- * Put cacheline_aliged data to L1 data memory
- */
-#ifdef CONFIG_CACHELINE_ALIGNED_L1
-#define __cacheline_aligned \
- __attribute__((__aligned__(L1_CACHE_BYTES), \
- __section__(".data_l1.cacheline_aligned")))
-#endif
-
-#endif
-
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX 5
-
-#if defined(CONFIG_SMP) && \
- !defined(CONFIG_BFIN_CACHE_COHERENT)
-# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define __ARCH_SYNC_CORE_ICACHE
-# endif
-# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
-# define __ARCH_SYNC_CORE_DCACHE
-# endif
-#ifndef __ASSEMBLY__
-asmlinkage void __raw_smp_mark_barrier_asm(void);
-asmlinkage void __raw_smp_check_barrier_asm(void);
-
-static inline void smp_mark_barrier(void)
-{
- __raw_smp_mark_barrier_asm();
-}
-static inline void smp_check_barrier(void)
-{
- __raw_smp_check_barrier_asm();
-}
-
-void resync_core_dcache(void);
-void resync_core_icache(void);
-#endif
-#endif
-
-
-#endif
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
deleted file mode 100644
index 9a5b2c5..0000000
--- a/arch/blackfin/include/asm/cacheflush.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Blackfin low-level cache routines
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_CACHEFLUSH_H
-#define _BLACKFIN_CACHEFLUSH_H
-
-#include <asm/blackfin.h> /* for SSYNC() */
-#include <asm/sections.h> /* for _ramend */
-#ifdef CONFIG_SMP
-#include <asm/smp.h>
-#endif
-
-extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dflush_page(void *page);
-extern void blackfin_invalidate_entire_dcache(void);
-extern void blackfin_invalidate_entire_icache(void);
-
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr) do { } while (0)
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-
-#ifdef CONFIG_SMP
-#define flush_icache_range_others(start, end) \
- smp_icache_flush_range_others((start), (end))
-#else
-#define flush_icache_range_others(start, end) do { } while (0)
-#endif
-
-static inline void flush_icache_range(unsigned start, unsigned end)
-{
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
- if (end <= physical_mem_end)
- blackfin_dcache_flush_range(start, end);
-#endif
-#if defined(CONFIG_BFIN_L2_WRITEBACK)
- if (start >= L2_START && end <= L2_START + L2_LENGTH)
- blackfin_dcache_flush_range(start, end);
-#endif
-
- /* Make sure all write buffers in the data side of the core
- * are flushed before trying to invalidate the icache. This
- * needs to be after the data flush and before the icache
- * flush so that the SSYNC does the right thing in preventing
- * the instruction prefetcher from hitting things in cached
- * memory@the wrong time -- it runs much further ahead than
- * the pipeline.
- */
- SSYNC();
-#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
- if (end <= physical_mem_end) {
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
- }
-#endif
-#if defined(CONFIG_BFIN_L2_ICACHEABLE)
- if (start >= L2_START && end <= L2_START + L2_LENGTH) {
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
- }
-#endif
-}
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { memcpy(dst, src, len); \
- flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
-} while (0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
-
-#if defined(CONFIG_BFIN_DCACHE)
-# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
-#else
-# define invalidate_dcache_range(start,end) do { } while (0)
-#endif
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
-# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
-#else
-# define flush_dcache_range(start,end) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-# define flush_dcache_page(page) do { } while (0)
-#endif
-
-extern unsigned long reserved_mem_dcache_on;
-extern unsigned long reserved_mem_icache_on;
-
-static inline int bfin_addr_dcacheable(unsigned long addr)
-{
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- if (addr < (_ramend - DMA_UNCACHED_REGION))
- return 1;
-#endif
-
- if (reserved_mem_dcache_on &&
- addr >= _ramend && addr < physical_mem_end)
- return 1;
-
-#ifdef CONFIG_BFIN_L2_DCACHEABLE
- if (addr >= L2_START && addr < L2_START + L2_LENGTH)
- return 1;
-#endif
-
- return 0;
-}
-
-#endif /* _BLACKFIN_ICACHEFLUSH_H */
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
deleted file mode 100644
index 59af63c..0000000
--- a/arch/blackfin/include/asm/cdef_LPBlackfin.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_LPBLACKFIN_H
-#define _CDEF_LPBLACKFIN_H
-
-/*#if !defined(__ADSPLPBLACKFIN__)
-#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
-#endif
-*/
-#include <asm/def_LPBlackfin.h>
-
-/*Cache & SRAM Memory*/
-#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
-#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
-/*
-#define MMR_TIMEOUT 0xFFE00010
-*/
-#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
-#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
-#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
-#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
-#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
-#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
-#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
-#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
-#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
-#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
-#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
-#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
-#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
-#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
-#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
-#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
-/*
-#define DTEST_INDEX 0xFFE00304
-*/
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
-/*
-#define DTEST_DATA2 0xFFE00408
-#define DTEST_DATA3 0xFFE0040C
-*/
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val)
-#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
-#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val)
-#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val)
-#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val)
-#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val)
-#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val)
-#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val)
-#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val)
-#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val)
-#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val)
-#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val)
-#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val)
-#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val)
-#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val)
-#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val)
-#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val)
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val)
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val)
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val)
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val)
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val)
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val)
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val)
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val)
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val)
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val)
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val)
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val)
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val)
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val)
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
-#if 0
-#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
-#endif
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
-
-#if !ANOMALY_05000481
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#endif
-
-/* Event/Interrupt Registers*/
-
-#define bfin_read_EVT0() bfin_read32(EVT0)
-#define bfin_write_EVT0(val) bfin_write32(EVT0,val)
-#define bfin_read_EVT1() bfin_read32(EVT1)
-#define bfin_write_EVT1(val) bfin_write32(EVT1,val)
-#define bfin_read_EVT2() bfin_read32(EVT2)
-#define bfin_write_EVT2(val) bfin_write32(EVT2,val)
-#define bfin_read_EVT3() bfin_read32(EVT3)
-#define bfin_write_EVT3(val) bfin_write32(EVT3,val)
-#define bfin_read_EVT4() bfin_read32(EVT4)
-#define bfin_write_EVT4(val) bfin_write32(EVT4,val)
-#define bfin_read_EVT5() bfin_read32(EVT5)
-#define bfin_write_EVT5(val) bfin_write32(EVT5,val)
-#define bfin_read_EVT6() bfin_read32(EVT6)
-#define bfin_write_EVT6(val) bfin_write32(EVT6,val)
-#define bfin_read_EVT7() bfin_read32(EVT7)
-#define bfin_write_EVT7(val) bfin_write32(EVT7,val)
-#define bfin_read_EVT8() bfin_read32(EVT8)
-#define bfin_write_EVT8(val) bfin_write32(EVT8,val)
-#define bfin_read_EVT9() bfin_read32(EVT9)
-#define bfin_write_EVT9(val) bfin_write32(EVT9,val)
-#define bfin_read_EVT10() bfin_read32(EVT10)
-#define bfin_write_EVT10(val) bfin_write32(EVT10,val)
-#define bfin_read_EVT11() bfin_read32(EVT11)
-#define bfin_write_EVT11(val) bfin_write32(EVT11,val)
-#define bfin_read_EVT12() bfin_read32(EVT12)
-#define bfin_write_EVT12(val) bfin_write32(EVT12,val)
-#define bfin_read_EVT13() bfin_read32(EVT13)
-#define bfin_write_EVT13(val) bfin_write32(EVT13,val)
-#define bfin_read_EVT14() bfin_read32(EVT14)
-#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
-#define bfin_read_EVT15() bfin_read32(EVT15)
-#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
-#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
-#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val)
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val)
-
-/*Core Timer Registers*/
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val)
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val)
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val)
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val)
-
-/*Debug/MP/Emulation Registers*/
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID,val)
-#define bfin_read_DBGCTL() bfin_read32(DBGCTL)
-#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val)
-#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val)
-#define bfin_read_EMUDAT() bfin_read32(EMUDAT)
-#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val)
-
-/*Trace Buffer Registers*/
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val)
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val)
-#define bfin_read_TBUF() bfin_read32(TBUF)
-#define bfin_write_TBUF(val) bfin_write32(TBUF,val)
-
-/*Watch Point Control Registers*/
-#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
-#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val)
-#define bfin_read_WPIA0() bfin_read32(WPIA0)
-#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val)
-#define bfin_read_WPIA1() bfin_read32(WPIA1)
-#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val)
-#define bfin_read_WPIA2() bfin_read32(WPIA2)
-#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val)
-#define bfin_read_WPIA3() bfin_read32(WPIA3)
-#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val)
-#define bfin_read_WPIA4() bfin_read32(WPIA4)
-#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val)
-#define bfin_read_WPIA5() bfin_read32(WPIA5)
-#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val)
-#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
-#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val)
-#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
-#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val)
-#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
-#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val)
-#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
-#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val)
-#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
-#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val)
-#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
-#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val)
-#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
-#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val)
-#define bfin_read_WPDA0() bfin_read32(WPDA0)
-#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val)
-#define bfin_read_WPDA1() bfin_read32(WPDA1)
-#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val)
-#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
-#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val)
-#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
-#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val)
-#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
-#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val)
-
-/*Performance Monitor Registers*/
-#define bfin_read_PFCTL() bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val)
-#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val)
-#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
-
-#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h
deleted file mode 100644
index e7134bf..0000000
--- a/arch/blackfin/include/asm/checksum.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * akbar.hussain at lineo.com
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_CHECKSUM_H
-#define _BFIN_CHECKSUM_H
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __wsum
-__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- unsigned int carry;
-
- __asm__ ("%0 = %0 + %2;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- "%0 = %0 + %3;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- "%0 = %0 + %4;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- : "=d" (sum), "=&d" (carry)
- : "d" (daddr), "d" (saddr), "d" ((len + proto) << 8), "0"(sum)
- : "CC");
-
- return (sum);
-}
-#define csum_tcpudp_nofold __csum_tcpudp_nofold
-
-#include <asm-generic/checksum.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
deleted file mode 100644
index 9b3c85b..0000000
--- a/arch/blackfin/include/asm/clocks.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Common Clock definitions for various kernel files
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_CLOCKS_H
-#define _BFIN_CLOCKS_H
-
-#include <asm/dpmc.h>
-
-#ifdef CONFIG_CCLK_DIV_1
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-# define CONFIG_CCLK_DIV 1
-#endif
-
-#ifdef CONFIG_CCLK_DIV_2
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-# define CONFIG_CCLK_DIV 2
-#endif
-
-#ifdef CONFIG_CCLK_DIV_4
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-# define CONFIG_CCLK_DIV 4
-#endif
-
-#ifdef CONFIG_CCLK_DIV_8
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-# define CONFIG_CCLK_DIV 8
-#endif
-
-#ifndef CONFIG_PLL_BYPASS
-# ifndef CONFIG_CLKIN_HALF
-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-# else
-# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
-# endif
-
-# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
-# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
-
-#else
-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_VCO_MULT 0
-#endif
-
-#include <linux/clk.h>
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk *clk);
- unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk *clk, unsigned long rate);
- int (*enable)(struct clk *clk);
- int (*disable)(struct clk *clk);
-};
-
-struct clk {
- struct clk *parent;
- const char *name;
- unsigned long rate;
- spinlock_t lock;
- u32 flags;
- const struct clk_ops *ops;
- void __iomem *reg;
- u32 mask;
- u32 shift;
-};
-
-int clk_init(void);
-#endif
diff --git a/arch/blackfin/include/asm/cmpxchg.h b/arch/blackfin/include/asm/cmpxchg.h
deleted file mode 100644
index 2539288..0000000
--- a/arch/blackfin/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CMPXCHG__
-#define __ARCH_BLACKFIN_CMPXCHG__
-
-#ifdef CONFIG_SMP
-
-#include <linux/linkage.h>
-
-asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
- int size)
-{
- unsigned long tmp;
-
- switch (size) {
- case 1:
- tmp = __raw_xchg_1_asm(ptr, x);
- break;
- case 2:
- tmp = __raw_xchg_2_asm(ptr, x);
- break;
- case 4:
- tmp = __raw_xchg_4_asm(ptr, x);
- break;
- }
-
- return tmp;
-}
-
-/*
- * Atomic compare and exchange. Compare OLD with MEM, if identical,
- * store NEW in MEM. Return the initial value in MEM. Success is
- * indicated by comparing RETURN with OLD.
- */
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
- unsigned long new, int size)
-{
- unsigned long tmp;
-
- switch (size) {
- case 1:
- tmp = __raw_cmpxchg_1_asm(ptr, new, old);
- break;
- case 2:
- tmp = __raw_cmpxchg_2_asm(ptr, new, old);
- break;
- case 4:
- tmp = __raw_cmpxchg_4_asm(ptr, new, old);
- break;
- }
-
- return tmp;
-}
-#define cmpxchg(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
- (unsigned long)(n), sizeof(*(ptr))))
-
-#else /* !CONFIG_SMP */
-
-#include <mach/blackfin.h>
-#include <asm/irqflags.h>
-
-struct __xchg_dummy {
- unsigned long a[100];
-};
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
- int size)
-{
- unsigned long tmp = 0;
- unsigned long flags;
-
- flags = hard_local_irq_save();
-
- switch (size) {
- case 1:
- __asm__ __volatile__
- ("%0 = b%2 (z);\n\t"
- "b%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- case 2:
- __asm__ __volatile__
- ("%0 = w%2 (z);\n\t"
- "w%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- case 4:
- __asm__ __volatile__
- ("%0 = %2;\n\t"
- "%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- }
- hard_local_irq_restore(flags);
- return tmp;
-}
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
- (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#define cmpxchg(ptr, o, n) cmpxchg_local((ptr), (o), (n))
-#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
-
-#endif /* !CONFIG_SMP */
-
-#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
-
-#endif /* __ARCH_BLACKFIN_CMPXCHG__ */
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
deleted file mode 100644
index 507e7aa..0000000
--- a/arch/blackfin/include/asm/context.S
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/*
- * NOTE! The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/*
- * Code to save processor context.
- * We even save the register which are preserved by a function call
- * - r4, r5, r6, r7, p3, p4, p5
- */
-.macro save_context_with_interrupts
- [--sp] = SYSCFG;
-
- [--sp] = P0; /*orig_p0*/
- [--sp] = R0; /*orig_r0*/
-
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r0; /* Skip IPEND as well. */
- /* Switch to other method of keeping interrupts disabled. */
-#ifdef CONFIG_DEBUG_HWERR
- r0 = 0x3f;
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
-#endif
- [--sp] = RETI; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro save_context_syscall
- [--sp] = SYSCFG;
-
- [--sp] = P0; /*orig_p0*/
- [--sp] = R0; /*orig_r0*/
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r0; /* Skip IPEND as well. */
- [--sp] = RETI; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro save_context_no_interrupts
- [--sp] = SYSCFG;
- [--sp] = P0; /* orig_p0 */
- [--sp] = R0; /* orig_r0 */
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
-#ifdef CONFIG_KGDB
- fp = 0(Z);
- r1 = sp;
- r1 += 60;
- r1 += 60;
- r1 += 60;
- [--sp] = r1;
-#else
- [--sp] = r0; /* Skip reserved */
-#endif
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
-#ifdef CONFIG_DEBUG_KERNEL
- p1.l = lo(IPEND);
- p1.h = hi(IPEND);
- r1 = [p1];
- [--sp] = r1;
-#else
- [--sp] = r0; /* Skip IPEND as well. */
-#endif
- [--sp] = r0; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro restore_context_no_interrupts
- sp += 4; /* Skip orig_pc */
- sp += 4; /* Skip IPEND */
- SEQSTAT = [sp++];
- RETE = [sp++];
- RETN = [sp++];
- RETX = [sp++];
- r0 = [sp++];
- RETI = r0; /* Restore RETI indirectly when in exception */
- RETS = [sp++];
-
- sp += 4; /* Skip Reserved */
-
- ASTAT = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- sp += 4;
- fp = [sp++];
-
- ( R7 : 0, P5 : 0) = [ SP ++ ];
- sp += 8; /* Skip orig_r0/orig_p0 */
- SYSCFG = [sp++];
-.endm
-
-.macro restore_context_with_interrupts
- sp += 4; /* Skip orig_pc */
- sp += 4; /* Skip IPEND */
- SEQSTAT = [sp++];
- RETE = [sp++];
- RETN = [sp++];
- RETX = [sp++];
- RETI = [sp++];
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- sp += -12;
- call _trace_hardirqs_on;
- sp += 12;
-#endif
-
- RETS = [sp++];
-
-#ifdef CONFIG_SMP
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_IRQFLAGS];
-#else
- p0.h = _bfin_irq_flags;
- p0.l = _bfin_irq_flags;
- r0 = [p0];
-#endif
- sti r0;
-
- sp += 4; /* Skip Reserved */
-
- ASTAT = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- sp += 4;
- fp = [sp++];
-
- ( R7 : 0, P5 : 0) = [ SP ++ ];
- sp += 8; /* Skip orig_r0/orig_p0 */
- csync;
- SYSCFG = [sp++];
- csync;
-.endm
-
-.macro save_context_cplb
- [--sp] = (R7:0, P5:0);
- [--sp] = fp;
-
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = RETS;
-.endm
-
-.macro restore_context_cplb
- RETS = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
-
- fp = [sp++];
-
- (R7:0, P5:0) = [SP++];
-.endm
-
-.macro pseudo_long_call func:req, scratch:req
-#ifdef CONFIG_ROMKERNEL
- \scratch\().l = \func;
- \scratch\().h = \func;
- call (\scratch);
-#else
- call \func;
-#endif
-.endm
-
-#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
-# define EX_SCRATCH_REG RETN
-#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
-# define EX_SCRATCH_REG RETE
-#else
-# define EX_SCRATCH_REG CYCLES
-#endif
-
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
deleted file mode 100644
index 5c37f62..0000000
--- a/arch/blackfin/include/asm/cplb.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CPLB_H
-#define _CPLB_H
-
-#include <mach/anomaly.h>
-
-#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
-
-#if ANOMALY_05000158
-#define ANOMALY_05000158_WORKAROUND 0x200
-#else
-#define ANOMALY_05000158_WORKAROUND 0x0
-#endif
-
-#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-
-#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
-#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
-#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
-#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
-#else
-#define SDRAM_DGENERIC (CPLB_COMMON)
-#endif
-
-#define SDRAM_DNON_CHBL (CPLB_COMMON)
-#define SDRAM_EBIU (CPLB_COMMON)
-#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
-
-#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
-
-#ifdef CONFIG_SMP
-#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
-#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
-#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
-
-#else
-#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
-# if defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
-# else
-# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
-# endif
-
-# if defined(CONFIG_BFIN_L2_WRITEBACK)
-# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
-# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
-# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
-# else
-# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
-# endif
-#endif /* CONFIG_SMP */
-
-#define SIZE_1K 0x00000400 /* 1K */
-#define SIZE_4K 0x00001000 /* 4K */
-#define SIZE_1M 0x00100000 /* 1M */
-#define SIZE_4M 0x00400000 /* 4M */
-#define SIZE_16K 0x00004000 /* 16K */
-#define SIZE_64K 0x00010000 /* 64K */
-#define SIZE_16M 0x01000000 /* 16M */
-#define SIZE_64M 0x04000000 /* 64M */
-
-#define MAX_CPLBS 16
-
-#define CPLB_ENABLE_ICACHE_P 0
-#define CPLB_ENABLE_DCACHE_P 1
-#define CPLB_ENABLE_DCACHE2_P 2
-#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
-#define CPLB_ENABLE_ICPLBS_P 4
-#define CPLB_ENABLE_DCPLBS_P 5
-
-#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
- CPLB_ENABLE_ICPLBS | \
- CPLB_ENABLE_DCPLBS
-
-#define CPLB_RELOADED 0x0000
-#define CPLB_NO_UNLOCKED 0x0001
-#define CPLB_NO_ADDR_MATCH 0x0002
-#define CPLB_PROT_VIOL 0x0003
-#define CPLB_UNKNOWN_ERR 0x0004
-
-#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
-#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
-
-#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
-#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
-
-#define FAULT_RW (1 << 16)
-#define FAULT_USERSUPV (1 << 17)
-#define FAULT_CPLBBITS 0x0000ffff
-
-#ifndef __ASSEMBLY__
-
-static inline void _disable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) & ~mask;
- /* CSYNC to ensure load store ordering */
- __builtin_bfin_csync();
- bfin_write32(mmr, ctrl);
- __builtin_bfin_ssync();
-}
-static inline void disable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) & ~mask;
- CSYNC();
- bfin_write32(mmr, ctrl);
- SSYNC();
-}
-#define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
-#define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB)
-#define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB)
-#define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB)
-
-static inline void _enable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) | mask;
- /* CSYNC to ensure load store ordering */
- __builtin_bfin_csync();
- bfin_write32(mmr, ctrl);
- __builtin_bfin_ssync();
-}
-static inline void enable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) | mask;
- CSYNC();
- bfin_write32(mmr, ctrl);
- SSYNC();
-}
-#define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB)
-#define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB)
-#define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB)
-#define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _CPLB_H */
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h
deleted file mode 100644
index f315c83..0000000
--- a/arch/blackfin/include/asm/cplbinit.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Common CPLB definitions for CPLB init
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_CPLBINIT_H__
-#define __ASM_CPLBINIT_H__
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <linux/threads.h>
-
-#ifdef CONFIG_CPLB_SWITCH_TAB_L1
-# define PDT_ATTR __attribute__((l1_data))
-#else
-# define PDT_ATTR
-#endif
-
-struct cplb_entry {
- unsigned long data, addr;
-};
-
-struct cplb_boundary {
- unsigned long eaddr; /* End of this region. */
- unsigned long data; /* CPLB data value. */
-};
-
-extern struct cplb_boundary dcplb_bounds[];
-extern struct cplb_boundary icplb_bounds[];
-extern int dcplb_nr_bounds, icplb_nr_bounds;
-
-extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
-extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
-extern int first_switched_icplb;
-extern int first_switched_dcplb;
-
-extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
-extern int nr_dcplb_prot[], nr_cplb_flush[];
-
-#ifdef CONFIG_MPU
-
-extern int first_mask_dcplb;
-
-extern int page_mask_order;
-extern int page_mask_nelts;
-
-extern unsigned long *current_rwx_mask[NR_CPUS];
-
-extern void flush_switched_cplbs(unsigned int);
-extern void set_mask_dcplbs(unsigned long *, unsigned int);
-
-extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
-
-#endif /* CONFIG_MPU */
-
-extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
-extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
-
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
-extern void generate_cplb_tables_all(void);
-extern void generate_cplb_tables_cpu(unsigned int cpu);
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
deleted file mode 100644
index e349631..0000000
--- a/arch/blackfin/include/asm/cpu.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CPU_H
-#define __ASM_BLACKFIN_CPU_H
-
-#include <linux/percpu.h>
-
-struct blackfin_cpudata {
- struct cpu cpu;
- unsigned int imemctl;
- unsigned int dmemctl;
-#ifdef CONFIG_SMP
- struct task_struct *idle;
-#endif
-};
-
-DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);
-
-#endif
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
deleted file mode 100644
index c5c8d8a..0000000
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ /dev/null
@@ -1,697 +0,0 @@
-/*
- * Blackfin core register bit & address definitions
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or GPL-2 (or later).
- */
-
-#ifndef _DEF_LPBLACKFIN_H
-#define _DEF_LPBLACKFIN_H
-
-#include <mach/anomaly.h>
-
-#define MK_BMSK_(x) (1<<x)
-#define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask))
-#define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask))
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-#if ANOMALY_05000198
-# define NOP_PAD_ANOMALY_05000198 "nop;"
-#else
-# define NOP_PAD_ANOMALY_05000198
-#endif
-
-#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
- u32 __v; \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- "%0 = " #asm_size "[%1]" #asm_ext ";" \
- : "=d" (__v) \
- : "a" (addr) \
- ); \
- __v; })
-#define _bfin_writeX(addr, val, size, asm_size) \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- #asm_size "[%0] = %1;" \
- : \
- : "a" (addr), "d" ((u##size)(val)) \
- : "memory" \
- )
-
-#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
-#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
-#define bfin_read32(addr) _bfin_readX(addr, 32, , )
-#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
-#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
-#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
-
-#define bfin_read(addr) \
-({ \
- sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
- sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
- sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
- ({ BUG(); 0; }); \
-})
-#define bfin_write(addr, val) \
-do { \
- switch (sizeof(*(addr))) { \
- case 1: bfin_write8(addr, val); break; \
- case 2: bfin_write16(addr, val); break; \
- case 4: bfin_write32(addr, val); break; \
- default: BUG(); \
- } \
-} while (0)
-
-#define bfin_write_or(addr, bits) \
-do { \
- typeof(addr) __addr = (addr); \
- bfin_write(__addr, bfin_read(__addr) | (bits)); \
-} while (0)
-
-#define bfin_write_and(addr, bits) \
-do { \
- typeof(addr) __addr = (addr); \
- bfin_write(__addr, bfin_read(__addr) & (bits)); \
-} while (0)
-
-#endif /* __ASSEMBLY__ */
-
-/**************************************************
- * System Register Bits
- **************************************************/
-
-/**************************************************
- * ASTAT register
- **************************************************/
-
-/* definitions of ASTAT bit positions*/
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ_P 0x00000000
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN_P 0x00000001
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC_P 0x00000005
-/*Quotient Bit*/
-#define ASTAT_AQ_P 0x00000006
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD_P 0x00000008
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_P 0x0000000C
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY_P 0x00000002
-/*Result of last ALU1 operation generated a carry*/
-#define ASTAT_AC1_P 0x0000000D
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0_P 0x00000010
-/*Sticky version of ASTAT_AV0 */
-#define ASTAT_AV0S_P 0x00000011
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1_P 0x00000012
-/*Sticky version of ASTAT_AV1 */
-#define ASTAT_AV1S_P 0x00000013
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_P 0x00000018
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_COPY_P 0x00000003
-/*Sticky version of ASTAT_V*/
-#define ASTAT_VS_P 0x00000019
-
-/* Masks */
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
-/*Quotient Bit*/
-#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
-/*Overflow Bit*/
-#define ASTAT_V MK_BMSK_(ASTAT_V_P)
-/*Overflow Bit*/
-#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
-
-/**************************************************
- * SEQSTAT register
- **************************************************/
-
-/* Bit Positions */
-#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
-#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
-#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
-#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
-#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
-#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
-#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
- * set by IDLE instruction.
- */
-#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
- * reset was a software reset
- * (=1)
- */
-#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
-#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
-#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
-#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
-#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
-/* Masks */
-/* Exception cause */
-#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
- 0)
-
-/* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
- 0)
-
-/* Translate bits to something useful */
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE_SHIFT (14)
-#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
-
-/**************************************************
- * SYSCFG register
- **************************************************/
-
-/* Bit Positions */
-#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
- * set it forces an exception
- * for each instruction executed
- */
-#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
-#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
-
-/* Masks */
-
-/* Supervisor single step, when set it forces an exception for each
- *instruction executed
- */
-#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
-/* Enable cycle counter (=1) */
-#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
-/* Self Nesting Interrupt Enable */
-#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
-/* Backward-compatibility for typos in prior releases */
-#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
-#define SYSCFG_CCCEN SYSCFG_CCEN
-
-/****************************************************
- * Core MMR Register Map
- ****************************************************/
-
-/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
-
-#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
- * Buffer Status
- */
-#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
- * Buffer Fault Address
- */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
- * Buffer 0
- */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
- * Buffer 1
- */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
- * Buffer 2
- */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
- * Lookaside Buffer 3
- */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
- * Lookaside Buffer 4
- */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
- * Lookaside Buffer 5
- */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
- * Lookaside Buffer 6
- */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
- * Lookaside Buffer 7
- */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
- * Lookaside Buffer 8
- */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
- * Lookaside Buffer 9
- */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
- * Lookaside Buffer 10
- */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
- * Lookaside Buffer 11
- */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
- * Lookaside Buffer 12
- */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
- * Lookaside Buffer 13
- */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
- * Lookaside Buffer 14
- */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
- * Lookaside Buffer 15
- */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
-
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-
-/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
-
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
-#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
-#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
- * Protection Lookaside Buffer 0
- */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
- * Protection Lookaside Buffer 1
- */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
- * Protection Lookaside Buffer 2
- */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
- * Protection Lookaside Buffer 3
- */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
- * Protection Lookaside Buffer 4
- */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
- * Protection Lookaside Buffer 5
- */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
- * Protection Lookaside Buffer 6
- */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
- * Protection Lookaside Buffer 7
- */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
- * Protection Lookaside Buffer 8
- */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
- * Protection Lookaside Buffer 9
- */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
- * Protection Lookaside Buffer 10
- */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
- * Protection Lookaside Buffer 11
- */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
- * Protection Lookaside Buffer 12
- */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
- * Protection Lookaside Buffer 13
- */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
- * Protection Lookaside Buffer 14
- */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
- * Protection Lookaside Buffer 15
- */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-
-/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
-
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
-
-/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
-
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
-#define DSPID 0xFFE05000 /* DSP Processor ID Register for
- * MP implementations
- */
-
-#define DBGSTAT 0xFFE05008 /* Debug Status Register */
-
-/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
-
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
-
-/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
-
-/* Watchpoint Instruction Address Control Register */
-#define WPIACTL 0xFFE07000
-/* Watchpoint Instruction Address Register 0 */
-#define WPIA0 0xFFE07040
-/* Watchpoint Instruction Address Register 1 */
-#define WPIA1 0xFFE07044
-/* Watchpoint Instruction Address Register 2 */
-#define WPIA2 0xFFE07048
-/* Watchpoint Instruction Address Register 3 */
-#define WPIA3 0xFFE0704C
-/* Watchpoint Instruction Address Register 4 */
-#define WPIA4 0xFFE07050
-/* Watchpoint Instruction Address Register 5 */
-#define WPIA5 0xFFE07054
-/* Watchpoint Instruction Address Count Register 0 */
-#define WPIACNT0 0xFFE07080
-/* Watchpoint Instruction Address Count Register 1 */
-#define WPIACNT1 0xFFE07084
-/* Watchpoint Instruction Address Count Register 2 */
-#define WPIACNT2 0xFFE07088
-/* Watchpoint Instruction Address Count Register 3 */
-#define WPIACNT3 0xFFE0708C
-/* Watchpoint Instruction Address Count Register 4 */
-#define WPIACNT4 0xFFE07090
-/* Watchpoint Instruction Address Count Register 5 */
-#define WPIACNT5 0xFFE07094
-/* Watchpoint Data Address Control Register */
-#define WPDACTL 0xFFE07100
-/* Watchpoint Data Address Register 0 */
-#define WPDA0 0xFFE07140
-/* Watchpoint Data Address Register 1 */
-#define WPDA1 0xFFE07144
-/* Watchpoint Data Address Count Value Register 0 */
-#define WPDACNT0 0xFFE07180
-/* Watchpoint Data Address Count Value Register 1 */
-#define WPDACNT1 0xFFE07184
-/* Watchpoint Status Register */
-#define WPSTAT 0xFFE07200
-
-/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
-
-/* Performance Monitor Control Register */
-#define PFCTL 0xFFE08000
-/* Performance Monitor Counter Register 0 */
-#define PFCNTR0 0xFFE08100
-/* Performance Monitor Counter Register 1 */
-#define PFCNTR1 0xFFE08104
-
-/****************************************************
- * Core MMR Register Bits
- ****************************************************/
-
-/**************************************************
- * EVT registers (ILAT, IMASK, and IPEND).
- **************************************************/
-
-/* Bit Positions */
-#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
-#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
-#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
-#define EVT_EVX_P 0x00000003 /* Exception bit position */
-#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
-#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
-#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
-#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
-#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
-#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
-#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
-#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
-#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
-#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
-#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
-
-/* Masks */
-#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
-#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
-#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
-#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
-#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
-#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
-#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
-#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
-#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
-#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
-#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
-#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
-#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
-#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
-#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
-#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
-
-/**************************************************
- * DMEM_CONTROL Register
- **************************************************/
-/* Bit Positions */
-#define ENDM_P 0x00 /* (doesn't really exist) Enable
- *Data Memory L1
- */
-#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
-
-#define ENDCPLB_P 0x01 /* Enable DCPLBS */
-#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
-#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
-#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
-#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
-#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
-#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
-#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
-#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
-#define RDCHK 0x9 /* Enable L1 Parity Check */
-
-/* Masks */
-#define ENDM 0x00000001 /* (doesn't really exist) Enable
- * Data Memory L1
- */
-#define ENDCPLB 0x00000002 /* Enable DCPLB */
-#define ASRAM_BSRAM 0x00000000
-#define ACACHE_BSRAM 0x00000008
-#define ACACHE_BCACHE 0x0000000C
-#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
-#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
-#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
-
-/* IMEM_CONTROL Register */
-/* Bit Positions */
-#define ENIM_P 0x00 /* Enable L1 Code Memory */
-#define IMCTL_ENIM_P 0x00 /* "" (older define) */
-#define ENICPLB_P 0x01 /* Enable ICPLB */
-#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
-#define IMC_P 0x02 /* Enable */
-#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
- * cache (0=SRAM)
- */
-#define ILOC0_P 0x03 /* Lock Way 0 */
-#define ILOC1_P 0x04 /* Lock Way 1 */
-#define ILOC2_P 0x05 /* Lock Way 2 */
-#define ILOC3_P 0x06 /* Lock Way 3 */
-#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
- * Priority
- */
-/* Masks */
-#define ENIM 0x00000001 /* Enable L1 Code Memory */
-#define ENICPLB 0x00000002 /* Enable ICPLB */
-#define IMC 0x00000004 /* Configure L1 code memory as
- * cache (0=SRAM)
- */
-#define ILOC0 0x00000008 /* Lock Way 0 */
-#define ILOC1 0x00000010 /* Lock Way 1 */
-#define ILOC2 0x00000020 /* Lock Way 2 */
-#define ILOC3 0x00000040 /* Lock Way 3 */
-#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
- * Priority
- */
-
-/* TCNTL Masks */
-#define TMPWR 0x00000001 /* Timer Low Power Control,
- * 0=low power mode, 1=active state
- */
-#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD 0x00000004 /* Timer auto reload */
-#define TINT 0x00000008 /* Timer generated interrupt 0=no
- * interrupt has been generated,
- * 1=interrupt has been generated
- * (sticky)
- */
-
-/* DCPLB_DATA and ICPLB_DATA Registers */
-/* Bit Positions */
-#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
- * locked
- */
-#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
- * allowed (user mode)
- */
-/* Masks */
-#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
- * locked
- */
-#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
- * allowed (user mode)
- */
-
-#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
-#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
-#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
-#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
-#ifdef CONFIG_BF60x
-#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
-#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
-#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
-#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
-#endif
-#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
- * mapped to L1
- */
-#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
- * priority port
- */
-#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
- * in L1
- */
-/* ICPLB_DATA only */
-#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
- * 1=priority for non-replacement
- */
-/* DCPLB_DATA only */
-#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
- * access allowed (user mode)
- */
-#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
- * access allowed (supervisor mode)
- */
-#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
-#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
- * write-through writes,
- * 1= allocate cache lines on
- * write-through writes.
- */
-#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
-
-#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
-
-/* TBUFCTL Masks */
-#define TBUFPWR 0x0001
-#define TBUFEN 0x0002
-#define TBUFOVF 0x0004
-#define TBUFCMPLP_SINGLE 0x0008
-#define TBUFCMPLP_DOUBLE 0x0010
-#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
-
-/* TBUFSTAT Masks */
-#define TBUFCNT 0x001F
-
-/* ITEST_COMMAND and DTEST_COMMAND Registers */
-/* Masks */
-#define TEST_READ 0x00000000 /* Read Access */
-#define TEST_WRITE 0x00000002 /* Write Access */
-#define TEST_TAG 0x00000000 /* Access TAG */
-#define TEST_DATA 0x00000004 /* Access DATA */
-#define TEST_DW0 0x00000000 /* Select Double Word 0 */
-#define TEST_DW1 0x00000008 /* Select Double Word 1 */
-#define TEST_DW2 0x00000010 /* Select Double Word 2 */
-#define TEST_DW3 0x00000018 /* Select Double Word 3 */
-#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
-#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
-#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
-#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
-#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
-#define TEST_WAY0 0x00000000 /* Access Way0 */
-#define TEST_WAY1 0x04000000 /* Access Way1 */
-/* ITEST_COMMAND only */
-#define TEST_WAY2 0x08000000 /* Access Way2 */
-#define TEST_WAY3 0x0C000000 /* Access Way3 */
-/* DTEST_COMMAND only */
-#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
-#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
-
-#endif /* _DEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
deleted file mode 100644
index 171d8de..0000000
--- a/arch/blackfin/include/asm/delay.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * delay.h - delay functions
- *
- * Copyright (c) 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_DELAY_H__
-#define __ASM_DELAY_H__
-
-#include <mach/anomaly.h>
-
-static inline void __delay(unsigned long loops)
-{
-__asm__ __volatile__ (
- "LSETUP(1f, 1f) LC0 = %0;"
- "1: NOP;"
- :
- : "a" (loops)
- : "LT0", "LB0", "LC0"
- );
-}
-
-#include <linux/param.h> /* needed for HZ */
-
-/*
- * close approximation borrowed from m68knommu to avoid 64-bit math
- */
-
-#define HZSCALE (268435456 / (1000000/HZ))
-
-static inline unsigned long __to_delay(unsigned long scale)
-{
- extern unsigned long loops_per_jiffy;
- return (((scale * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6;
-}
-
-static inline void udelay(unsigned long usecs)
-{
- __delay(__to_delay(usecs));
-}
-
-static inline void ndelay(unsigned long nsecs)
-{
- __delay(__to_delay(1) * nsecs / 1000);
-}
-
-#define ndelay ndelay
-
-#endif
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
deleted file mode 100644
index 04254ac..0000000
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_MAPPING_H
-#define _BLACKFIN_DMA_MAPPING_H
-
-#include <asm/cacheflush.h>
-
-extern void
-__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir);
-static inline void
-__dma_sync_inline(dma_addr_t addr, size_t size, enum dma_data_direction dir)
-{
- switch (dir) {
- case DMA_NONE:
- BUG();
- case DMA_TO_DEVICE: /* writeback only */
- flush_dcache_range(addr, addr + size);
- break;
- case DMA_FROM_DEVICE: /* invalidate only */
- case DMA_BIDIRECTIONAL: /* flush and invalidate */
- /* Blackfin has no dedicated invalidate (it includes a flush) */
- invalidate_dcache_range(addr, addr + size);
- break;
- }
-}
-static inline void
-_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir)
-{
- if (__builtin_constant_p(dir))
- __dma_sync_inline(addr, size, dir);
- else
- __dma_sync(addr, size, dir);
-}
-
-extern const struct dma_map_ops bfin_dma_ops;
-
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
-{
- return &bfin_dma_ops;
-}
-
-#endif /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
deleted file mode 100644
index 40e9c2b..0000000
--- a/arch/blackfin/include/asm/dma.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_H_
-#define _BLACKFIN_DMA_H_
-
-#include <linux/interrupt.h>
-#include <mach/dma.h>
-#include <linux/atomic.h>
-#include <asm/blackfin.h>
-#include <asm/page.h>
-#include <asm-generic/dma.h>
-#include <asm/bfin_dma.h>
-
-/*-------------------------
- * config reg bits value
- *-------------------------*/
-#define DATA_SIZE_8 0
-#define DATA_SIZE_16 1
-#define DATA_SIZE_32 2
-#ifdef CONFIG_BF60x
-#define DATA_SIZE_64 3
-#endif
-
-#define DMA_FLOW_STOP 0
-#define DMA_FLOW_AUTO 1
-#ifdef CONFIG_BF60x
-#define DMA_FLOW_LIST 4
-#define DMA_FLOW_ARRAY 5
-#define DMA_FLOW_LIST_DEMAND 6
-#define DMA_FLOW_ARRAY_DEMAND 7
-#else
-#define DMA_FLOW_ARRAY 4
-#define DMA_FLOW_SMALL 6
-#define DMA_FLOW_LARGE 7
-#endif
-
-#define DIMENSION_LINEAR 0
-#define DIMENSION_2D 1
-
-#define DIR_READ 0
-#define DIR_WRITE 1
-
-#define INTR_DISABLE 0
-#ifdef CONFIG_BF60x
-#define INTR_ON_PERI 1
-#endif
-#define INTR_ON_BUF 2
-#define INTR_ON_ROW 3
-
-#define DMA_NOSYNC_KEEP_DMA_BUF 0
-#define DMA_SYNC_RESTART 1
-
-#ifdef DMA_MMR_SIZE_32
-#define DMA_MMR_SIZE_TYPE long
-#define DMA_MMR_READ bfin_read32
-#define DMA_MMR_WRITE bfin_write32
-#else
-#define DMA_MMR_SIZE_TYPE short
-#define DMA_MMR_READ bfin_read16
-#define DMA_MMR_WRITE bfin_write16
-#endif
-
-struct dma_desc_array {
- unsigned long start_addr;
- unsigned DMA_MMR_SIZE_TYPE cfg;
- unsigned DMA_MMR_SIZE_TYPE x_count;
- DMA_MMR_SIZE_TYPE x_modify;
-} __attribute__((packed));
-
-struct dmasg {
- void *next_desc_addr;
- unsigned long start_addr;
- unsigned DMA_MMR_SIZE_TYPE cfg;
- unsigned DMA_MMR_SIZE_TYPE x_count;
- DMA_MMR_SIZE_TYPE x_modify;
- unsigned DMA_MMR_SIZE_TYPE y_count;
- DMA_MMR_SIZE_TYPE y_modify;
-} __attribute__((packed));
-
-struct dma_register {
- void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
- unsigned long start_addr; /* DMA Start address register */
-#ifdef CONFIG_BF60x
- unsigned long cfg; /* DMA Configuration register */
-
- unsigned long x_count; /* DMA x_count register */
-
- long x_modify; /* DMA x_modify register */
-
- unsigned long y_count; /* DMA y_count register */
-
- long y_modify; /* DMA y_modify register */
-
- unsigned long reserved;
- unsigned long reserved2;
-
- void *curr_desc_ptr; /* DMA Current Descriptor Pointer
- register */
- void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer
- register */
- unsigned long curr_addr_ptr; /* DMA Current Address Pointer
- register */
- unsigned long irq_status; /* DMA irq status register */
-
- unsigned long curr_x_count; /* DMA Current x-count register */
-
- unsigned long curr_y_count; /* DMA Current y-count register */
-
- unsigned long reserved3;
-
- unsigned long bw_limit_count; /* DMA band width limit count register */
- unsigned long curr_bw_limit_count; /* DMA Current band width limit
- count register */
- unsigned long bw_monitor_count; /* DMA band width limit count register */
- unsigned long curr_bw_monitor_count; /* DMA Current band width limit
- count register */
-#else
- unsigned short cfg; /* DMA Configuration register */
- unsigned short dummy1; /* DMA Configuration register */
-
- unsigned long reserved;
-
- unsigned short x_count; /* DMA x_count register */
- unsigned short dummy2;
-
- short x_modify; /* DMA x_modify register */
- unsigned short dummy3;
-
- unsigned short y_count; /* DMA y_count register */
- unsigned short dummy4;
-
- short y_modify; /* DMA y_modify register */
- unsigned short dummy5;
-
- void *curr_desc_ptr; /* DMA Current Descriptor Pointer
- register */
- unsigned long curr_addr_ptr; /* DMA Current Address Pointer
- register */
- unsigned short irq_status; /* DMA irq status register */
- unsigned short dummy6;
-
- unsigned short peripheral_map; /* DMA peripheral map register */
- unsigned short dummy7;
-
- unsigned short curr_x_count; /* DMA Current x-count register */
- unsigned short dummy8;
-
- unsigned long reserved2;
-
- unsigned short curr_y_count; /* DMA Current y-count register */
- unsigned short dummy9;
-
- unsigned long reserved3;
-#endif
-
-};
-
-struct dma_channel {
- const char *device_id;
- atomic_t chan_status;
- volatile struct dma_register *regs;
- struct dmasg *sg; /* large mode descriptor */
- unsigned int irq;
- void *data;
-#ifdef CONFIG_PM
- unsigned short saved_peripheral_map;
-#endif
-};
-
-#ifdef CONFIG_PM
-int blackfin_dma_suspend(void);
-void blackfin_dma_resume(void);
-#endif
-
-/*******************************************************************************
-* DMA API's
-*******************************************************************************/
-extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
-extern int channel2irq(unsigned int channel);
-
-static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
-{
- dma_ch[channel].regs->start_addr = addr;
-}
-static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
-{
- dma_ch[channel].regs->next_desc_ptr = addr;
-}
-static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
-{
- dma_ch[channel].regs->curr_desc_ptr = addr;
-}
-static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
-{
- dma_ch[channel].regs->x_count = x_count;
-}
-static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
-{
- dma_ch[channel].regs->y_count = y_count;
-}
-static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
-{
- dma_ch[channel].regs->x_modify = x_modify;
-}
-static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
-{
- dma_ch[channel].regs->y_modify = y_modify;
-}
-static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
-{
- dma_ch[channel].regs->cfg = config;
-}
-static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
-{
- dma_ch[channel].regs->curr_addr_ptr = addr;
-}
-
-#ifdef CONFIG_BF60x
-static inline unsigned long
-set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
- char dma_mode, char mem_width, char syncmode, char peri_width)
-{
- unsigned long config = 0;
-
- switch (intr_mode) {
- case INTR_ON_BUF:
- if (dma_mode == DIMENSION_2D)
- config = DI_EN_Y;
- else
- config = DI_EN_X;
- break;
- case INTR_ON_ROW:
- config = DI_EN_X;
- break;
- case INTR_ON_PERI:
- config = DI_EN_P;
- break;
- };
-
- return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
- (flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
-}
-#endif
-
-static inline unsigned DMA_MMR_SIZE_TYPE
-set_bfin_dma_config(char direction, char flow_mode,
- char intr_mode, char dma_mode, char mem_width, char syncmode)
-{
-#ifdef CONFIG_BF60x
- return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
- mem_width, syncmode, mem_width);
-#else
- return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
- (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
-#endif
-}
-
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
-{
- return dma_ch[channel].regs->irq_status;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_x_count;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_y_count;
-}
-static inline void *get_dma_next_desc_ptr(unsigned int channel)
-{
- return dma_ch[channel].regs->next_desc_ptr;
-}
-static inline void *get_dma_curr_desc_ptr(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_desc_ptr;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
-{
- return dma_ch[channel].regs->cfg;
-}
-static inline unsigned long get_dma_curr_addr(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_addr_ptr;
-}
-
-static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
-{
- /* Make sure the internal data buffers in the core are drained
- * so that the DMA descriptors are completely written when the
- * DMA engine goes to fetch them below.
- */
- SSYNC();
-
- dma_ch[channel].regs->next_desc_ptr = sg;
- dma_ch[channel].regs->cfg =
- (dma_ch[channel].regs->cfg & ~NDSIZE) |
- ((ndsize << NDSIZE_OFFSET) & NDSIZE);
-}
-
-static inline int dma_channel_active(unsigned int channel)
-{
- return atomic_read(&dma_ch[channel].chan_status);
-}
-
-static inline void disable_dma(unsigned int channel)
-{
- dma_ch[channel].regs->cfg &= ~DMAEN;
- SSYNC();
-}
-static inline void enable_dma(unsigned int channel)
-{
- dma_ch[channel].regs->curr_x_count = 0;
- dma_ch[channel].regs->curr_y_count = 0;
- dma_ch[channel].regs->cfg |= DMAEN;
-}
-int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
-
-static inline void dma_disable_irq(unsigned int channel)
-{
- disable_irq(dma_ch[channel].irq);
-}
-static inline void dma_disable_irq_nosync(unsigned int channel)
-{
- disable_irq_nosync(dma_ch[channel].irq);
-}
-static inline void dma_enable_irq(unsigned int channel)
-{
- enable_irq(dma_ch[channel].irq);
-}
-static inline void clear_dma_irqstat(unsigned int channel)
-{
- dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
-}
-
-void *dma_memcpy(void *dest, const void *src, size_t count);
-void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
-void *safe_dma_memcpy(void *dest, const void *src, size_t count);
-void blackfin_dma_early_init(void);
-void early_dma_memcpy(void *dest, const void *src, size_t count);
-void early_dma_memcpy_done(void);
-
-#endif
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
deleted file mode 100644
index 2673b11..0000000
--- a/arch/blackfin/include/asm/dpmc.h
+++ /dev/null
@@ -1,794 +0,0 @@
-/*
- * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
- *
- * Copyright (C) 2004-2009 Analog Device Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BLACKFIN_DPMC_H_
-#define _BLACKFIN_DPMC_H_
-
-#ifdef __ASSEMBLY__
-#define PM_REG0 R7
-#define PM_REG1 R6
-#define PM_REG2 R5
-#define PM_REG3 R4
-#define PM_REG4 R3
-#define PM_REG5 R2
-#define PM_REG6 R1
-#define PM_REG7 R0
-#define PM_REG8 P5
-#define PM_REG9 P4
-#define PM_REG10 P3
-#define PM_REG11 P2
-#define PM_REG12 P1
-#define PM_REG13 P0
-
-#define PM_REGSET0 R7:7
-#define PM_REGSET1 R7:6
-#define PM_REGSET2 R7:5
-#define PM_REGSET3 R7:4
-#define PM_REGSET4 R7:3
-#define PM_REGSET5 R7:2
-#define PM_REGSET6 R7:1
-#define PM_REGSET7 R7:0
-#define PM_REGSET8 R7:0, P5:5
-#define PM_REGSET9 R7:0, P5:4
-#define PM_REGSET10 R7:0, P5:3
-#define PM_REGSET11 R7:0, P5:2
-#define PM_REGSET12 R7:0, P5:1
-#define PM_REGSET13 R7:0, P5:0
-
-#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
-#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
-#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
-#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
-#define PM_PUSH(n, x) PM_REG##n = [FP++];
-#define PM_POP(n, x) [FP--] = PM_REG##n;
-#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
-#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
-#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
-#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
-#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
-#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
-
- .macro bfin_init_pm_bench_cycles
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- R4 = 0;
- CYCLES = R4;
- CYCLES2 = R4;
- R4 = SYSCFG;
- BITSET(R4, 1);
- SYSCFG = R4;
-#endif
- .endm
-
- .macro bfin_cpu_reg_save
- /*
- * Save the core regs early so we can blow them away when
- * saving/restoring MMR states
- */
- [--sp] = (R7:0, P5:0);
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- /* We can't push RETI directly as that'll change IPEND[4] */
- r7 = RETI;
- [--sp] = RETS;
- [--sp] = ASTAT;
-#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- [--sp] = CYCLES;
- [--sp] = CYCLES2;
-#endif
- [--sp] = SYSCFG;
- [--sp] = RETX;
- [--sp] = SEQSTAT;
- [--sp] = r7;
-
- /* Save first func arg in M3 */
- M3 = R0;
- .endm
-
- .macro bfin_cpu_reg_restore
- /* Restore Core Registers */
- RETI = [sp++];
- SEQSTAT = [sp++];
- RETX = [sp++];
- SYSCFG = [sp++];
-#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- CYCLES2 = [sp++];
- CYCLES = [sp++];
-#endif
- ASTAT = [sp++];
- RETS = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- usp = [sp++];
- fp = [sp++];
- (R7:0, P5:0) = [sp++];
-
- .endm
-
- .macro bfin_sys_mmr_save
- /* Save system MMRs */
- FP.H = hi(SYSMMR_BASE);
- FP.L = lo(SYSMMR_BASE);
-#ifdef SIC_IMASK0
- PM_SYS_PUSH(0, SIC_IMASK0)
- PM_SYS_PUSH(1, SIC_IMASK1)
-# ifdef SIC_IMASK2
- PM_SYS_PUSH(2, SIC_IMASK2)
-# endif
-#else
-# ifdef SIC_IMASK
- PM_SYS_PUSH(0, SIC_IMASK)
-# endif
-#endif
-
-#ifdef SIC_IAR0
- PM_SYS_PUSH(3, SIC_IAR0)
- PM_SYS_PUSH(4, SIC_IAR1)
- PM_SYS_PUSH(5, SIC_IAR2)
-#endif
-#ifdef SIC_IAR3
- PM_SYS_PUSH(6, SIC_IAR3)
-#endif
-#ifdef SIC_IAR4
- PM_SYS_PUSH(7, SIC_IAR4)
- PM_SYS_PUSH(8, SIC_IAR5)
- PM_SYS_PUSH(9, SIC_IAR6)
-#endif
-#ifdef SIC_IAR7
- PM_SYS_PUSH(10, SIC_IAR7)
-#endif
-#ifdef SIC_IAR8
- PM_SYS_PUSH(11, SIC_IAR8)
- PM_SYS_PUSH(12, SIC_IAR9)
- PM_SYS_PUSH(13, SIC_IAR10)
-#endif
- PM_PUSH_SYNC(13)
-#ifdef SIC_IAR11
- PM_SYS_PUSH(0, SIC_IAR11)
-#endif
-
-#ifdef SIC_IWR
- PM_SYS_PUSH(1, SIC_IWR)
-#endif
-#ifdef SIC_IWR0
- PM_SYS_PUSH(1, SIC_IWR0)
-#endif
-#ifdef SIC_IWR1
- PM_SYS_PUSH(2, SIC_IWR1)
-#endif
-#ifdef SIC_IWR2
- PM_SYS_PUSH(3, SIC_IWR2)
-#endif
-
-#ifdef PINT0_ASSIGN
- PM_SYS_PUSH(4, PINT0_MASK_SET)
- PM_SYS_PUSH(5, PINT1_MASK_SET)
- PM_SYS_PUSH(6, PINT2_MASK_SET)
- PM_SYS_PUSH(7, PINT3_MASK_SET)
- PM_SYS_PUSH(8, PINT0_ASSIGN)
- PM_SYS_PUSH(9, PINT1_ASSIGN)
- PM_SYS_PUSH(10, PINT2_ASSIGN)
- PM_SYS_PUSH(11, PINT3_ASSIGN)
- PM_SYS_PUSH(12, PINT0_INVERT_SET)
- PM_SYS_PUSH(13, PINT1_INVERT_SET)
- PM_PUSH_SYNC(13)
- PM_SYS_PUSH(0, PINT2_INVERT_SET)
- PM_SYS_PUSH(1, PINT3_INVERT_SET)
- PM_SYS_PUSH(2, PINT0_EDGE_SET)
- PM_SYS_PUSH(3, PINT1_EDGE_SET)
- PM_SYS_PUSH(4, PINT2_EDGE_SET)
- PM_SYS_PUSH(5, PINT3_EDGE_SET)
-#endif
-
-#ifdef SYSCR
- PM_SYS_PUSH16(6, SYSCR)
-#endif
-
-#ifdef EBIU_AMGCTL
- PM_SYS_PUSH16(7, EBIU_AMGCTL)
- PM_SYS_PUSH(8, EBIU_AMBCTL0)
- PM_SYS_PUSH(9, EBIU_AMBCTL1)
-#endif
-#ifdef EBIU_FCTL
- PM_SYS_PUSH(10, EBIU_MBSCTL)
- PM_SYS_PUSH(11, EBIU_MODE)
- PM_SYS_PUSH(12, EBIU_FCTL)
- PM_PUSH_SYNC(12)
-#else
- PM_PUSH_SYNC(9)
-#endif
- .endm
-
-
- .macro bfin_sys_mmr_restore
-/* Restore System MMRs */
- FP.H = hi(SYSMMR_BASE);
- FP.L = lo(SYSMMR_BASE);
-
-#ifdef EBIU_FCTL
- PM_POP_SYNC(12)
- PM_SYS_POP(12, EBIU_FCTL)
- PM_SYS_POP(11, EBIU_MODE)
- PM_SYS_POP(10, EBIU_MBSCTL)
-#else
- PM_POP_SYNC(9)
-#endif
-
-#ifdef EBIU_AMGCTL
- PM_SYS_POP(9, EBIU_AMBCTL1)
- PM_SYS_POP(8, EBIU_AMBCTL0)
- PM_SYS_POP16(7, EBIU_AMGCTL)
-#endif
-
-#ifdef SYSCR
- PM_SYS_POP16(6, SYSCR)
-#endif
-
-#ifdef PINT0_ASSIGN
- PM_SYS_POP(5, PINT3_EDGE_SET)
- PM_SYS_POP(4, PINT2_EDGE_SET)
- PM_SYS_POP(3, PINT1_EDGE_SET)
- PM_SYS_POP(2, PINT0_EDGE_SET)
- PM_SYS_POP(1, PINT3_INVERT_SET)
- PM_SYS_POP(0, PINT2_INVERT_SET)
- PM_POP_SYNC(13)
- PM_SYS_POP(13, PINT1_INVERT_SET)
- PM_SYS_POP(12, PINT0_INVERT_SET)
- PM_SYS_POP(11, PINT3_ASSIGN)
- PM_SYS_POP(10, PINT2_ASSIGN)
- PM_SYS_POP(9, PINT1_ASSIGN)
- PM_SYS_POP(8, PINT0_ASSIGN)
- PM_SYS_POP(7, PINT3_MASK_SET)
- PM_SYS_POP(6, PINT2_MASK_SET)
- PM_SYS_POP(5, PINT1_MASK_SET)
- PM_SYS_POP(4, PINT0_MASK_SET)
-#endif
-
-#ifdef SIC_IWR2
- PM_SYS_POP(3, SIC_IWR2)
-#endif
-#ifdef SIC_IWR1
- PM_SYS_POP(2, SIC_IWR1)
-#endif
-#ifdef SIC_IWR0
- PM_SYS_POP(1, SIC_IWR0)
-#endif
-#ifdef SIC_IWR
- PM_SYS_POP(1, SIC_IWR)
-#endif
-
-#ifdef SIC_IAR11
- PM_SYS_POP(0, SIC_IAR11)
-#endif
- PM_POP_SYNC(13)
-#ifdef SIC_IAR8
- PM_SYS_POP(13, SIC_IAR10)
- PM_SYS_POP(12, SIC_IAR9)
- PM_SYS_POP(11, SIC_IAR8)
-#endif
-#ifdef SIC_IAR7
- PM_SYS_POP(10, SIC_IAR7)
-#endif
-#ifdef SIC_IAR6
- PM_SYS_POP(9, SIC_IAR6)
- PM_SYS_POP(8, SIC_IAR5)
- PM_SYS_POP(7, SIC_IAR4)
-#endif
-#ifdef SIC_IAR3
- PM_SYS_POP(6, SIC_IAR3)
-#endif
-#ifdef SIC_IAR0
- PM_SYS_POP(5, SIC_IAR2)
- PM_SYS_POP(4, SIC_IAR1)
- PM_SYS_POP(3, SIC_IAR0)
-#endif
-#ifdef SIC_IMASK0
-# ifdef SIC_IMASK2
- PM_SYS_POP(2, SIC_IMASK2)
-# endif
- PM_SYS_POP(1, SIC_IMASK1)
- PM_SYS_POP(0, SIC_IMASK0)
-#else
-# ifdef SIC_IMASK
- PM_SYS_POP(0, SIC_IMASK)
-# endif
-#endif
- .endm
-
- .macro bfin_core_mmr_save
- /* Save Core MMRs */
- I0.H = hi(COREMMR_BASE);
- I0.L = lo(COREMMR_BASE);
- I1 = I0;
- I2 = I0;
- I3 = I0;
- B0 = I0;
- B1 = I0;
- B2 = I0;
- B3 = I0;
- I1.L = lo(DCPLB_ADDR0);
- I2.L = lo(DCPLB_DATA0);
- I3.L = lo(ICPLB_ADDR0);
- B0.L = lo(ICPLB_DATA0);
- B1.L = lo(EVT2);
- B2.L = lo(IMASK);
- B3.L = lo(TCNTL);
-
- /* Event Vectors */
- FP = B1;
- PM_PUSH(0, EVT2)
- PM_PUSH(1, EVT3)
- FP += 4; /* EVT4 */
- PM_PUSH(2, EVT5)
- PM_PUSH(3, EVT6)
- PM_PUSH(4, EVT7)
- PM_PUSH(5, EVT8)
- PM_PUSH_SYNC(5)
-
- PM_PUSH(0, EVT9)
- PM_PUSH(1, EVT10)
- PM_PUSH(2, EVT11)
- PM_PUSH(3, EVT12)
- PM_PUSH(4, EVT13)
- PM_PUSH(5, EVT14)
- PM_PUSH(6, EVT15)
-
- /* CEC */
- FP = B2;
- PM_PUSH(7, IMASK)
- FP += 4; /* IPEND */
- PM_PUSH(8, ILAT)
- PM_PUSH(9, IPRIO)
-
- /* Core Timer */
- FP = B3;
- PM_PUSH(10, TCNTL)
- PM_PUSH(11, TPERIOD)
- PM_PUSH(12, TSCALE)
- PM_PUSH(13, TCOUNT)
- PM_PUSH_SYNC(13)
-
- /* Misc non-contiguous registers */
- FP = I0;
- PM_CORE_PUSH(0, DMEM_CONTROL);
- PM_CORE_PUSH(1, IMEM_CONTROL);
- PM_CORE_PUSH(2, TBUFCTL);
- PM_PUSH_SYNC(2)
-
- /* DCPLB Addr */
- FP = I1;
- PM_PUSH(0, DCPLB_ADDR0)
- PM_PUSH(1, DCPLB_ADDR1)
- PM_PUSH(2, DCPLB_ADDR2)
- PM_PUSH(3, DCPLB_ADDR3)
- PM_PUSH(4, DCPLB_ADDR4)
- PM_PUSH(5, DCPLB_ADDR5)
- PM_PUSH(6, DCPLB_ADDR6)
- PM_PUSH(7, DCPLB_ADDR7)
- PM_PUSH(8, DCPLB_ADDR8)
- PM_PUSH(9, DCPLB_ADDR9)
- PM_PUSH(10, DCPLB_ADDR10)
- PM_PUSH(11, DCPLB_ADDR11)
- PM_PUSH(12, DCPLB_ADDR12)
- PM_PUSH(13, DCPLB_ADDR13)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, DCPLB_ADDR14)
- PM_PUSH(1, DCPLB_ADDR15)
-
- /* DCPLB Data */
- FP = I2;
- PM_PUSH(2, DCPLB_DATA0)
- PM_PUSH(3, DCPLB_DATA1)
- PM_PUSH(4, DCPLB_DATA2)
- PM_PUSH(5, DCPLB_DATA3)
- PM_PUSH(6, DCPLB_DATA4)
- PM_PUSH(7, DCPLB_DATA5)
- PM_PUSH(8, DCPLB_DATA6)
- PM_PUSH(9, DCPLB_DATA7)
- PM_PUSH(10, DCPLB_DATA8)
- PM_PUSH(11, DCPLB_DATA9)
- PM_PUSH(12, DCPLB_DATA10)
- PM_PUSH(13, DCPLB_DATA11)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, DCPLB_DATA12)
- PM_PUSH(1, DCPLB_DATA13)
- PM_PUSH(2, DCPLB_DATA14)
- PM_PUSH(3, DCPLB_DATA15)
-
- /* ICPLB Addr */
- FP = I3;
- PM_PUSH(4, ICPLB_ADDR0)
- PM_PUSH(5, ICPLB_ADDR1)
- PM_PUSH(6, ICPLB_ADDR2)
- PM_PUSH(7, ICPLB_ADDR3)
- PM_PUSH(8, ICPLB_ADDR4)
- PM_PUSH(9, ICPLB_ADDR5)
- PM_PUSH(10, ICPLB_ADDR6)
- PM_PUSH(11, ICPLB_ADDR7)
- PM_PUSH(12, ICPLB_ADDR8)
- PM_PUSH(13, ICPLB_ADDR9)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, ICPLB_ADDR10)
- PM_PUSH(1, ICPLB_ADDR11)
- PM_PUSH(2, ICPLB_ADDR12)
- PM_PUSH(3, ICPLB_ADDR13)
- PM_PUSH(4, ICPLB_ADDR14)
- PM_PUSH(5, ICPLB_ADDR15)
-
- /* ICPLB Data */
- FP = B0;
- PM_PUSH(6, ICPLB_DATA0)
- PM_PUSH(7, ICPLB_DATA1)
- PM_PUSH(8, ICPLB_DATA2)
- PM_PUSH(9, ICPLB_DATA3)
- PM_PUSH(10, ICPLB_DATA4)
- PM_PUSH(11, ICPLB_DATA5)
- PM_PUSH(12, ICPLB_DATA6)
- PM_PUSH(13, ICPLB_DATA7)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, ICPLB_DATA8)
- PM_PUSH(1, ICPLB_DATA9)
- PM_PUSH(2, ICPLB_DATA10)
- PM_PUSH(3, ICPLB_DATA11)
- PM_PUSH(4, ICPLB_DATA12)
- PM_PUSH(5, ICPLB_DATA13)
- PM_PUSH(6, ICPLB_DATA14)
- PM_PUSH(7, ICPLB_DATA15)
- PM_PUSH_SYNC(7)
- .endm
-
- .macro bfin_core_mmr_restore
- /* Restore Core MMRs */
- I0.H = hi(COREMMR_BASE);
- I0.L = lo(COREMMR_BASE);
- I1 = I0;
- I2 = I0;
- I3 = I0;
- B0 = I0;
- B1 = I0;
- B2 = I0;
- B3 = I0;
- I1.L = lo(DCPLB_ADDR15);
- I2.L = lo(DCPLB_DATA15);
- I3.L = lo(ICPLB_ADDR15);
- B0.L = lo(ICPLB_DATA15);
- B1.L = lo(EVT15);
- B2.L = lo(IPRIO);
- B3.L = lo(TCOUNT);
-
- /* ICPLB Data */
- FP = B0;
- PM_POP_SYNC(7)
- PM_POP(7, ICPLB_DATA15)
- PM_POP(6, ICPLB_DATA14)
- PM_POP(5, ICPLB_DATA13)
- PM_POP(4, ICPLB_DATA12)
- PM_POP(3, ICPLB_DATA11)
- PM_POP(2, ICPLB_DATA10)
- PM_POP(1, ICPLB_DATA9)
- PM_POP(0, ICPLB_DATA8)
- PM_POP_SYNC(13)
- PM_POP(13, ICPLB_DATA7)
- PM_POP(12, ICPLB_DATA6)
- PM_POP(11, ICPLB_DATA5)
- PM_POP(10, ICPLB_DATA4)
- PM_POP(9, ICPLB_DATA3)
- PM_POP(8, ICPLB_DATA2)
- PM_POP(7, ICPLB_DATA1)
- PM_POP(6, ICPLB_DATA0)
-
- /* ICPLB Addr */
- FP = I3;
- PM_POP(5, ICPLB_ADDR15)
- PM_POP(4, ICPLB_ADDR14)
- PM_POP(3, ICPLB_ADDR13)
- PM_POP(2, ICPLB_ADDR12)
- PM_POP(1, ICPLB_ADDR11)
- PM_POP(0, ICPLB_ADDR10)
- PM_POP_SYNC(13)
- PM_POP(13, ICPLB_ADDR9)
- PM_POP(12, ICPLB_ADDR8)
- PM_POP(11, ICPLB_ADDR7)
- PM_POP(10, ICPLB_ADDR6)
- PM_POP(9, ICPLB_ADDR5)
- PM_POP(8, ICPLB_ADDR4)
- PM_POP(7, ICPLB_ADDR3)
- PM_POP(6, ICPLB_ADDR2)
- PM_POP(5, ICPLB_ADDR1)
- PM_POP(4, ICPLB_ADDR0)
-
- /* DCPLB Data */
- FP = I2;
- PM_POP(3, DCPLB_DATA15)
- PM_POP(2, DCPLB_DATA14)
- PM_POP(1, DCPLB_DATA13)
- PM_POP(0, DCPLB_DATA12)
- PM_POP_SYNC(13)
- PM_POP(13, DCPLB_DATA11)
- PM_POP(12, DCPLB_DATA10)
- PM_POP(11, DCPLB_DATA9)
- PM_POP(10, DCPLB_DATA8)
- PM_POP(9, DCPLB_DATA7)
- PM_POP(8, DCPLB_DATA6)
- PM_POP(7, DCPLB_DATA5)
- PM_POP(6, DCPLB_DATA4)
- PM_POP(5, DCPLB_DATA3)
- PM_POP(4, DCPLB_DATA2)
- PM_POP(3, DCPLB_DATA1)
- PM_POP(2, DCPLB_DATA0)
-
- /* DCPLB Addr */
- FP = I1;
- PM_POP(1, DCPLB_ADDR15)
- PM_POP(0, DCPLB_ADDR14)
- PM_POP_SYNC(13)
- PM_POP(13, DCPLB_ADDR13)
- PM_POP(12, DCPLB_ADDR12)
- PM_POP(11, DCPLB_ADDR11)
- PM_POP(10, DCPLB_ADDR10)
- PM_POP(9, DCPLB_ADDR9)
- PM_POP(8, DCPLB_ADDR8)
- PM_POP(7, DCPLB_ADDR7)
- PM_POP(6, DCPLB_ADDR6)
- PM_POP(5, DCPLB_ADDR5)
- PM_POP(4, DCPLB_ADDR4)
- PM_POP(3, DCPLB_ADDR3)
- PM_POP(2, DCPLB_ADDR2)
- PM_POP(1, DCPLB_ADDR1)
- PM_POP(0, DCPLB_ADDR0)
-
-
- /* Misc non-contiguous registers */
-
- /* icache & dcache will enable later
- drop IMEM_CONTROL, DMEM_CONTROL pop
- */
- FP = I0;
- PM_POP_SYNC(2)
- PM_CORE_POP(2, TBUFCTL)
- PM_CORE_POP(1, IMEM_CONTROL)
- PM_CORE_POP(0, DMEM_CONTROL)
-
- /* Core Timer */
- FP = B3;
- R0 = 0x1;
- [FP - 0xC] = R0;
-
- PM_POP_SYNC(13)
- FP = B3;
- PM_POP(13, TCOUNT)
- PM_POP(12, TSCALE)
- PM_POP(11, TPERIOD)
- PM_POP(10, TCNTL)
-
- /* CEC */
- FP = B2;
- PM_POP(9, IPRIO)
- PM_POP(8, ILAT)
- FP += -4; /* IPEND */
- PM_POP(7, IMASK)
-
- /* Event Vectors */
- FP = B1;
- PM_POP(6, EVT15)
- PM_POP(5, EVT14)
- PM_POP(4, EVT13)
- PM_POP(3, EVT12)
- PM_POP(2, EVT11)
- PM_POP(1, EVT10)
- PM_POP(0, EVT9)
- PM_POP_SYNC(5)
- PM_POP(5, EVT8)
- PM_POP(4, EVT7)
- PM_POP(3, EVT6)
- PM_POP(2, EVT5)
- FP += -4; /* EVT4 */
- PM_POP(1, EVT3)
- PM_POP(0, EVT2)
- .endm
-#endif
-
-#include <mach/pll.h>
-
-/* PLL_CTL Masks */
-#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
-#define PLL_OFF 0x0002 /* PLL Not Powered */
-#define STOPCK 0x0008 /* Core Clock Off */
-#define PDWN 0x0020 /* Enter Deep Sleep Mode */
-#ifdef __ADSPBF539__
-# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */
-#else
-# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
-#endif
-#define BYPASS 0x0100 /* Bypass the PLL */
-#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
-#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
-#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-
-/* PLL_DIV Masks */
-#define SSEL 0x000F /* System Select */
-#define CSEL 0x0030 /* Core Select */
-#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
-#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
-#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
-#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
-
-#define CCLK_DIV1 CSEL_DIV1
-#define CCLK_DIV2 CSEL_DIV2
-#define CCLK_DIV4 CSEL_DIV4
-#define CCLK_DIV8 CSEL_DIV8
-
-#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
-#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
-
-/* PLL_STAT Masks */
-#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
-#define FULL_ON 0x0002 /* Processor In Full On Mode */
-#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
-#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
-
-#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */
-#define CANWS 0x0800 /* CAN Wake-Up Status */
-#define USBWS 0x2000 /* USB Wake-Up Status */
-#define KPADWS 0x4000 /* Keypad Wake-Up Status */
-#define ROTWS 0x8000 /* Rotary Wake-Up Status */
-#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
-
-/* VR_CTL Masks */
-#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
-#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
-#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
-#else
-#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
-#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
-#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
-#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
-#endif
-#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
-
-#define GAIN 0x000C /* Voltage Level Gain */
-#define GAIN_5 0x0000 /* GAIN = 5 */
-#define GAIN_10 0x0004 /* GAIN = 1 */
-#define GAIN_20 0x0008 /* GAIN = 2 */
-#define GAIN_50 0x000C /* GAIN = 5 */
-
-#define VLEV 0x00F0 /* Internal Voltage Level */
-#ifdef __ADSPBF52x__
-#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#else
-#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-#endif
-
-#ifdef CONFIG_BF60x
-#define PA15WE 0x00000001 /* Allow Wake-Up from PA15 */
-#define PB15WE 0x00000002 /* Allow Wake-Up from PB15 */
-#define PC15WE 0x00000004 /* Allow Wake-Up from PC15 */
-#define PD06WE 0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */
-#define PE12WE 0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */
-#define PG04WE 0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */
-#define PG13WE 0x00000040 /* Allow Wake-Up from PG13 */
-#define USBWE 0x00000080 /* Allow Wake-Up from (USB) */
-#else
-#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
-#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
-#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
-#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */
-#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
-#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
-#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
-#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
-#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
-
-#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
-#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
-#else
-#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
-#endif
-#endif
-
-#ifndef __ASSEMBLY__
-
-void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void do_hibernate(int wakeup);
-void set_dram_srfs(void);
-void unset_dram_srfs(void);
-
-#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
-
-#ifdef CONFIG_CPU_FREQ
-#define CPUFREQ_CPU 0
-#endif
-struct bfin_dpmc_platform_data {
- const unsigned int *tuple_tab;
- unsigned short tabsize;
- unsigned short vr_settling_time; /* in us */
-};
-
-#endif
-
-#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/early_printk.h b/arch/blackfin/include/asm/early_printk.h
deleted file mode 100644
index 68a910d..0000000
--- a/arch/blackfin/include/asm/early_printk.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * function prototpyes for early printk
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_EARLY_PRINTK_H__
-#define __ASM_EARLY_PRINTK_H__
-
-#ifdef CONFIG_EARLY_PRINTK
-/* For those that don't include it already */
-#include <linux/console.h>
-
-extern int setup_early_printk(char *);
-extern void enable_shadow_console(void);
-extern int shadow_console_enabled(void);
-extern void mark_shadow_error(void);
-extern void early_shadow_reg(unsigned long reg, unsigned int n);
-extern void early_shadow_write(struct console *con, const char *s,
- unsigned int n) __attribute__((nonnull(2)));
-#define early_shadow_puts(str) early_shadow_write(NULL, str, strlen(str))
-#define early_shadow_stamp() \
- do { \
- early_shadow_puts(__FILE__ " : " __stringify(__LINE__) " ["); \
- early_shadow_puts(__func__); \
- early_shadow_puts("]\n"); \
- } while (0)
-#else
-#define setup_early_printk(fmt) do { } while (0)
-#define enable_shadow_console(fmt) do { } while (0)
-#define early_shadow_stamp() do { } while (0)
-#endif /* CONFIG_EARLY_PRINTK */
-
-#endif /* __ASM_EARLY_PRINTK_H__ */
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
deleted file mode 100644
index d15cb9b..0000000
--- a/arch/blackfin/include/asm/elf.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASMBFIN_ELF_H
-#define __ASMBFIN_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-/* Processor specific flags for the ELF header e_flags field. */
-#define EF_BFIN_PIC 0x00000001 /* -fpic */
-#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */
-#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */
-#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */
-#define EF_BFIN_CODE_IN_L2 0x00000040 /* --code-in-l2 */
-#define EF_BFIN_DATA_IN_L2 0x00000080 /* --data-in-l2 */
-
-#if 1 /* core dumps not supported, but linux/elfcore.h needs these */
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct { } elf_fpregset_t;
-#endif
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
-
-#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
-#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
-
-/* EM_BLACKFIN defined in linux/elf.h */
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2LSB
-#define ELF_ARCH EM_BLACKFIN
-
-#define ELF_PLAT_INIT(_r) _r->p1 = 0
-
-#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \
-do { \
- _regs->r7 = 0; \
- _regs->p0 = _exec_map_addr; \
- _regs->p1 = _interp_map_addr; \
- _regs->p2 = _dynamic_addr; \
-} while(0)
-
-#if 0
-#define CORE_DUMP_USE_REGSET
-#endif
-#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC
-#define ELF_EXEC_PAGESIZE 4096
-
-#define R_BFIN_UNUSED0 0 /* relocation type 0 is not defined */
-#define R_BFIN_PCREL5M2 1 /* LSETUP part a */
-#define R_BFIN_UNUSED1 2 /* relocation type 2 is not defined */
-#define R_BFIN_PCREL10 3 /* type 3, if cc jump <target> */
-#define R_BFIN_PCREL12_JUMP 4 /* type 4, jump <target> */
-#define R_BFIN_RIMM16 5 /* type 0x5, rN = <target> */
-#define R_BFIN_LUIMM16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */
-#define R_BFIN_HUIMM16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */
-#define R_BFIN_PCREL12_JUMP_S 8 /* # 0x8 jump.s <target> */
-#define R_BFIN_PCREL24_JUMP_X 9 /* # 0x9 jump.x <target> */
-#define R_BFIN_PCREL24 10 /* # 0xa call <target> , not expandable */
-#define R_BFIN_UNUSEDB 11 /* # 0xb not generated */
-#define R_BFIN_UNUSEDC 12 /* # 0xc not used */
-#define R_BFIN_PCREL24_JUMP_L 13 /* 0xd jump.l <target> */
-#define R_BFIN_PCREL24_CALL_X 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
-#define R_BFIN_VAR_EQ_SYMB 15 /* 0xf, linker should treat it same as 0x12 */
-#define R_BFIN_BYTE_DATA 16 /* 0x10, .byte var = symbol */
-#define R_BFIN_BYTE2_DATA 17 /* 0x11, .byte2 var = symbol */
-#define R_BFIN_BYTE4_DATA 18 /* 0x12, .byte4 var = symbol and .var var=symbol */
-#define R_BFIN_PCREL11 19 /* 0x13, lsetup part b */
-#define R_BFIN_UNUSED14 20 /* 0x14, undefined */
-#define R_BFIN_UNUSED15 21 /* not generated by VDSP 3.5 */
-
-/* arithmetic relocations */
-#define R_BFIN_PUSH 0xE0
-#define R_BFIN_CONST 0xE1
-#define R_BFIN_ADD 0xE2
-#define R_BFIN_SUB 0xE3
-#define R_BFIN_MULT 0xE4
-#define R_BFIN_DIV 0xE5
-#define R_BFIN_MOD 0xE6
-#define R_BFIN_LSHIFT 0xE7
-#define R_BFIN_RSHIFT 0xE8
-#define R_BFIN_AND 0xE9
-#define R_BFIN_OR 0xEA
-#define R_BFIN_XOR 0xEB
-#define R_BFIN_LAND 0xEC
-#define R_BFIN_LOR 0xED
-#define R_BFIN_LEN 0xEE
-#define R_BFIN_NEG 0xEF
-#define R_BFIN_COMP 0xF0
-#define R_BFIN_PAGE 0xF1
-#define R_BFIN_HWPAGE 0xF2
-#define R_BFIN_ADDR 0xF3
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE 0xD0000000UL
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
- memcpy((char *) &pr_reg, (char *)regs, \
- sizeof(struct pt_regs));
-#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-
-#define ELF_PLATFORM (NULL)
-
-#endif
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
deleted file mode 100644
index 4104d57..0000000
--- a/arch/blackfin/include/asm/entry.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_ENTRY_H
-#define __BFIN_ENTRY_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-#ifdef __ASSEMBLY__
-
-#define LFLUSH_I_AND_D 0x00000808
-#define LSIGTRAP 5
-
-/*
- * NOTE! The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/* This one is used for exceptions, emulation, and NMI. It doesn't push
- RETI and doesn't do cli. */
-#define SAVE_ALL_SYS save_context_no_interrupts
-/* This is used for all normal interrupts. It saves a minimum of registers
- to the stack, loads the IRQ number, and jumps to common code. */
-#ifdef CONFIG_IPIPE
-# define LOAD_IPIPE_IPEND \
- P0.l = lo(IPEND); \
- P0.h = hi(IPEND); \
- R1 = [P0];
-#else
-# define LOAD_IPIPE_IPEND
-#endif
-
-/*
- * Workaround for anomalies 05000283 and 05000315
- */
-#if ANOMALY_05000283 || ANOMALY_05000315
-# define ANOMALY_283_315_WORKAROUND(preg, dreg) \
- cc = dreg == dreg; \
- preg.h = HI(CHIPID); \
- preg.l = LO(CHIPID); \
- if cc jump 1f; \
- dreg.l = W[preg]; \
-1:
-#else
-# define ANOMALY_283_315_WORKAROUND(preg, dreg)
-#endif /* ANOMALY_05000283 || ANOMALY_05000315 */
-
-#ifndef CONFIG_EXACT_HWERR
-/* As a debugging aid - we save IPEND when DEBUG_KERNEL is on,
- * otherwise it is a waste of cycles.
- */
-# ifndef CONFIG_DEBUG_KERNEL
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry;
-# else /* CONFIG_DEBUG_KERNEL */
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry;
-# endif /* CONFIG_DEBUG_KERNEL */
-
-/* For timer interrupts, we need to save IPEND, since the user_mode
- *macro accesses it to determine where to account time.
- */
-#define TIMER_INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- jump __common_int_entry;
-#else /* CONFIG_EXACT_HWERR is defined */
-
-/* if we want hardware error to be exact, we need to do a SSYNC (which forces
- * read/writes to complete to the memory controllers), and check to see that
- * caused a pending HW error condition. If so, we assume it was caused by user
- * space, by setting the same interrupt that we are in (so it goes off again)
- * and context restore, and a RTI (without servicing anything). This should
- * cause the pending HWERR to fire, and when that is done, this interrupt will
- * be re-serviced properly.
- * As you can see by the code - we actually need to do two SSYNCS - one to
- * make sure the read/writes complete, and another to make sure the hardware
- * error is recognized by the core.
- *
- * The extra nop before the SSYNC is to make sure we work around 05000244,
- * since the 283/315 workaround includes a branch to the end
- */
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R1 = ASTAT; \
- ANOMALY_283_315_WORKAROUND(p0, r0) \
- P0.L = LO(ILAT); \
- P0.H = HI(ILAT); \
- NOP; \
- SSYNC; \
- SSYNC; \
- R0 = [P0]; \
- CC = BITTST(R0, EVT_IVHW_P); \
- IF CC JUMP 1f; \
- ASTAT = R1; \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry; \
-1: ASTAT = R1; \
- RAISE N; \
- (R7:0, P5:0) = [SP++]; \
- SP += 0x8; \
- SYSCFG = [SP++]; \
- CSYNC; \
- RTI;
-
-#define TIMER_INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R1 = ASTAT; \
- ANOMALY_283_315_WORKAROUND(p0, r0) \
- P0.L = LO(ILAT); \
- P0.H = HI(ILAT); \
- NOP; \
- SSYNC; \
- SSYNC; \
- R0 = [P0]; \
- CC = BITTST(R0, EVT_IVHW_P); \
- IF CC JUMP 1f; \
- ASTAT = R1; \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- jump __common_int_entry; \
-1: ASTAT = R1; \
- RAISE N; \
- (R7:0, P5:0) = [SP++]; \
- SP += 0x8; \
- SYSCFG = [SP++]; \
- CSYNC; \
- RTI;
-#endif /* CONFIG_EXACT_HWERR */
-
-/* This one pushes RETI without using CLI. Interrupts are enabled. */
-#define SAVE_CONTEXT_SYSCALL save_context_syscall
-#define SAVE_CONTEXT save_context_with_interrupts
-#define SAVE_CONTEXT_CPLB save_context_cplb
-
-#define RESTORE_ALL_SYS restore_context_no_interrupts
-#define RESTORE_CONTEXT restore_context_with_interrupts
-#define RESTORE_CONTEXT_CPLB restore_context_cplb
-
-#endif /* __ASSEMBLY__ */
-#endif /* __BFIN_ENTRY_H */
diff --git a/arch/blackfin/include/asm/exec.h b/arch/blackfin/include/asm/exec.h
deleted file mode 100644
index 54c2e1d..0000000
--- a/arch/blackfin/include/asm/exec.h
+++ /dev/null
@@ -1 +0,0 @@
-/* define arch_align_stack() here */
diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h
deleted file mode 100644
index bc330f0..0000000
--- a/arch/blackfin/include/asm/fixed_code.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file defines the fixed addresses where userspace programs
- * can find atomic code sequences.
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __BFIN_ASM_FIXED_CODE_H__
-#define __BFIN_ASM_FIXED_CODE_H__
-
-#include <uapi/asm/fixed_code.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/linkage.h>
-#include <linux/ptrace.h>
-extern asmlinkage void finish_atomic_sections(struct pt_regs *regs);
-extern char fixed_code_start;
-extern char fixed_code_end;
-extern int atomic_xchg32(void);
-extern int atomic_cas32(void);
-extern int atomic_add32(void);
-extern int atomic_sub32(void);
-extern int atomic_ior32(void);
-extern int atomic_and32(void);
-extern int atomic_xor32(void);
-extern void safe_user_instruction(void);
-extern void sigreturn_stub(void);
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/flat.h b/arch/blackfin/include/asm/flat.h
deleted file mode 100644
index f1d6ba7..0000000
--- a/arch/blackfin/include/asm/flat.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * uClinux flat-format executables
- *
- * Copyright 2003-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __BLACKFIN_FLAT_H__
-#define __BLACKFIN_FLAT_H__
-
-#include <asm/unaligned.h>
-
-#define flat_argvp_envp_on_stack() 0
-#define flat_old_ram_flag(flags) (flags)
-
-extern unsigned long bfin_get_addr_from_rp (u32 *ptr, u32 relval,
- u32 flags, u32 *persistent);
-
-extern void bfin_put_addr_at_rp(u32 *ptr, u32 addr, u32 relval);
-
-/* The amount by which a relocation can exceed the program image limits
- without being regarded as an error. */
-
-#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
-
-static inline int flat_get_addr_from_rp(u32 __user *rp, u32 relval, u32 flags,
- u32 *addr, u32 *persistent)
-{
- *addr = bfin_get_addr_from_rp(rp, relval, flags, persistent);
- return 0;
-}
-
-static inline int flat_put_addr_at_rp(u32 __user *rp, u32 val, u32 relval)
-{
- bfin_put_addr_at_rp(rp, val, relval);
- return 0;
-}
-
-/* Convert a relocation entry into an address. */
-static inline unsigned long
-flat_get_relocate_addr (unsigned long relval)
-{
- return relval & 0x03ffffff; /* Mask out top 6 bits */
-}
-
-static inline int flat_set_persistent(u32 relval, u32 *persistent)
-{
- int type = (relval >> 26) & 7;
- if (type == 3) {
- *persistent = relval << 16;
- return 1;
- }
- return 0;
-}
-
-static inline int flat_addr_absolute(unsigned long relval)
-{
- return (relval & (1 << 29)) != 0;
-}
-
-#endif /* __BLACKFIN_FLAT_H__ */
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h
deleted file mode 100644
index 2f1c3c2..0000000
--- a/arch/blackfin/include/asm/ftrace.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Blackfin ftrace code
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_FTRACE_H__
-#define __ASM_BFIN_FTRACE_H__
-
-#define MCOUNT_INSN_SIZE 6 /* sizeof "[++sp] = rets; call __mcount;" */
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-extern void _mcount(void);
-#define MCOUNT_ADDR ((unsigned long)_mcount)
-
-static inline unsigned long ftrace_call_adjust(unsigned long addr)
-{
- return addr;
-}
-
-struct dyn_arch_ftrace {
- /* No extra data needed for Blackfin */
-};
-
-#endif
-
-#ifdef CONFIG_FRAME_POINTER
-#include <linux/mm.h>
-
-extern inline void *return_address(unsigned int level)
-{
- unsigned long *endstack, *fp, *ret_addr;
- unsigned int current_level = 0;
-
- if (level == 0)
- return __builtin_return_address(0);
-
- fp = (unsigned long *)__builtin_frame_address(0);
- endstack = (unsigned long *)PAGE_ALIGN((unsigned long)&level);
-
- while (((unsigned long)fp & 0x3) == 0 && fp &&
- (fp + 1) < endstack && current_level < level) {
- fp = (unsigned long *)*fp;
- current_level++;
- }
-
- if (((unsigned long)fp & 0x3) == 0 && fp &&
- (fp + 1) < endstack)
- ret_addr = (unsigned long *)*(fp + 1);
- else
- ret_addr = NULL;
-
- return ret_addr;
-}
-
-#else
-
-extern inline void *return_address(unsigned int level)
-{
- return NULL;
-}
-
-#endif /* CONFIG_FRAME_POINTER */
-
-#define ftrace_return_address(n) return_address(n)
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
deleted file mode 100644
index a257932..0000000
--- a/arch/blackfin/include/asm/gpio.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_GPIO_H__
-#define __ARCH_BLACKFIN_GPIO_H__
-
-#define gpio_bank(x) ((x) >> 4)
-#define gpio_bit(x) (1<<((x) & 0xF))
-#define gpio_sub_n(x) ((x) & 0xF)
-
-#define GPIO_BANKSIZE 16
-#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
-
-#include <mach/gpio.h>
-
-#define PERIPHERAL_USAGE 1
-#define GPIO_USAGE 0
-
-#ifndef BFIN_GPIO_PINT
-# define BFIN_GPIO_PINT 0
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifndef CONFIG_PINCTRL
-
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/irq_handler.h>
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-* to Blackfin processor General Purpose
-* Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-void set_gpio_dir(unsigned, unsigned short);
-void set_gpio_inen(unsigned, unsigned short);
-void set_gpio_polar(unsigned, unsigned short);
-void set_gpio_edge(unsigned, unsigned short);
-void set_gpio_both(unsigned, unsigned short);
-void set_gpio_data(unsigned, unsigned short);
-void set_gpio_maska(unsigned, unsigned short);
-void set_gpio_maskb(unsigned, unsigned short);
-void set_gpio_toggle(unsigned);
-void set_gpiop_dir(unsigned, unsigned short);
-void set_gpiop_inen(unsigned, unsigned short);
-void set_gpiop_polar(unsigned, unsigned short);
-void set_gpiop_edge(unsigned, unsigned short);
-void set_gpiop_both(unsigned, unsigned short);
-void set_gpiop_data(unsigned, unsigned short);
-void set_gpiop_maska(unsigned, unsigned short);
-void set_gpiop_maskb(unsigned, unsigned short);
-unsigned short get_gpio_dir(unsigned);
-unsigned short get_gpio_inen(unsigned);
-unsigned short get_gpio_polar(unsigned);
-unsigned short get_gpio_edge(unsigned);
-unsigned short get_gpio_both(unsigned);
-unsigned short get_gpio_maska(unsigned);
-unsigned short get_gpio_maskb(unsigned);
-unsigned short get_gpio_data(unsigned);
-unsigned short get_gpiop_dir(unsigned);
-unsigned short get_gpiop_inen(unsigned);
-unsigned short get_gpiop_polar(unsigned);
-unsigned short get_gpiop_edge(unsigned);
-unsigned short get_gpiop_both(unsigned);
-unsigned short get_gpiop_maska(unsigned);
-unsigned short get_gpiop_maskb(unsigned);
-unsigned short get_gpiop_data(unsigned);
-
-struct gpio_port_t {
- unsigned short data;
- unsigned short dummy1;
- unsigned short data_clear;
- unsigned short dummy2;
- unsigned short data_set;
- unsigned short dummy3;
- unsigned short toggle;
- unsigned short dummy4;
- unsigned short maska;
- unsigned short dummy5;
- unsigned short maska_clear;
- unsigned short dummy6;
- unsigned short maska_set;
- unsigned short dummy7;
- unsigned short maska_toggle;
- unsigned short dummy8;
- unsigned short maskb;
- unsigned short dummy9;
- unsigned short maskb_clear;
- unsigned short dummy10;
- unsigned short maskb_set;
- unsigned short dummy11;
- unsigned short maskb_toggle;
- unsigned short dummy12;
- unsigned short dir;
- unsigned short dummy13;
- unsigned short polar;
- unsigned short dummy14;
- unsigned short edge;
- unsigned short dummy15;
- unsigned short both;
- unsigned short dummy16;
- unsigned short inen;
-};
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
-void bfin_special_gpio_free(unsigned gpio);
-int bfin_special_gpio_request(unsigned gpio, const char *label);
-# ifdef CONFIG_PM
-void bfin_special_gpio_pm_hibernate_restore(void);
-void bfin_special_gpio_pm_hibernate_suspend(void);
-# endif
-#endif
-
-#ifdef CONFIG_PM
-void bfin_gpio_pm_hibernate_restore(void);
-void bfin_gpio_pm_hibernate_suspend(void);
-int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
-int bfin_gpio_pm_standby_ctrl(unsigned ctrl);
-
-static inline int bfin_pm_standby_setup(void)
-{
- return bfin_gpio_pm_standby_ctrl(1);
-}
-
-static inline void bfin_pm_standby_restore(void)
-{
- bfin_gpio_pm_standby_ctrl(0);
-}
-
-
-struct gpio_port_s {
- unsigned short data;
- unsigned short maska;
- unsigned short maskb;
- unsigned short dir;
- unsigned short polar;
- unsigned short edge;
- unsigned short both;
- unsigned short inen;
-
- unsigned short fer;
- unsigned short reserved;
- unsigned short mux;
-};
-#endif /*CONFIG_PM*/
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-int bfin_gpio_irq_request(unsigned gpio, const char *label);
-void bfin_gpio_irq_free(unsigned gpio);
-void bfin_gpio_irq_prepare(unsigned gpio);
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return irq - GPIO_IRQ_BASE;
-}
-
-#else /* CONFIG_PINCTRL */
-
-/*
- * CONFIG_PM is not working with pin control and should probably
- * avoid being selected when pin control is active, but so far,
- * these stubs are here to make allyesconfig and allmodconfig
- * compile properly. These functions are normally backed by the
- * CONFIG_ADI_GPIO custom GPIO implementation.
- */
-
-static inline int bfin_pm_standby_setup(void)
-{
- return 0;
-}
-
-static inline void bfin_pm_standby_restore(void)
-{
-}
-
-#endif /* CONFIG_PINCTRL */
-
-#include <asm/irq.h>
-#include <asm/errno.h>
-
-#include <asm-generic/gpio.h> /* cansleep wrappers */
-
-static inline int gpio_get_value(unsigned int gpio)
-{
- return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned int gpio, int value)
-{
- __gpio_set_value(gpio, value);
-}
-
-static inline int gpio_cansleep(unsigned int gpio)
-{
- return __gpio_cansleep(gpio);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return __gpio_to_irq(gpio);
-}
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
deleted file mode 100644
index 381e3d6..0000000
--- a/arch/blackfin/include/asm/gptimers.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2005 John DeHority
- * Copyright (C) 2006 Hella Aglaia GmbH (awe at aglaia-gmbh.de)
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef _BLACKFIN_TIMERS_H_
-#define _BLACKFIN_TIMERS_H_
-
-#include <linux/types.h>
-#include <asm/blackfin.h>
-
-/*
- * BF51x/BF52x/BF537: 8 timers:
- */
-#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || defined(BF537_FAMILY)
-# define MAX_BLACKFIN_GPTIMERS 8
-# define TIMER0_GROUP_REG TIMER_ENABLE
-#endif
-/*
- * BF54x: 11 timers (BF542: 8 timers):
- */
-#if defined(CONFIG_BF54x)
-# ifdef CONFIG_BF542
-# define MAX_BLACKFIN_GPTIMERS 8
-# else
-# define MAX_BLACKFIN_GPTIMERS 11
-# define TIMER8_GROUP_REG TIMER_ENABLE1
-# define TIMER_GROUP2 1
-# endif
-# define TIMER0_GROUP_REG TIMER_ENABLE0
-#endif
-/*
- * BF561: 12 timers:
- */
-#if defined(CONFIG_BF561)
-# define MAX_BLACKFIN_GPTIMERS 12
-# define TIMER0_GROUP_REG TMRS8_ENABLE
-# define TIMER8_GROUP_REG TMRS4_ENABLE
-# define TIMER_GROUP2 1
-#endif
-/*
- * BF609: 8 timers:
- */
-#if defined(CONFIG_BF60x)
-# define MAX_BLACKFIN_GPTIMERS 8
-# define TIMER0_GROUP_REG TIMER_RUN
-#endif
-/*
- * All others: 3 timers:
- */
-#define TIMER_GROUP1 0
-#if !defined(MAX_BLACKFIN_GPTIMERS)
-# define MAX_BLACKFIN_GPTIMERS 3
-# define TIMER0_GROUP_REG TIMER_ENABLE
-#endif
-
-#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
-#define BFIN_TIMER_OCTET(x) ((x) >> 3)
-
-/* used in masks for timer_enable() and timer_disable() */
-#define TIMER0bit 0x0001 /* 0001b */
-#define TIMER1bit 0x0002 /* 0010b */
-#define TIMER2bit 0x0004 /* 0100b */
-#define TIMER3bit 0x0008
-#define TIMER4bit 0x0010
-#define TIMER5bit 0x0020
-#define TIMER6bit 0x0040
-#define TIMER7bit 0x0080
-#define TIMER8bit 0x0100
-#define TIMER9bit 0x0200
-#define TIMER10bit 0x0400
-#define TIMER11bit 0x0800
-
-#define TIMER0_id 0
-#define TIMER1_id 1
-#define TIMER2_id 2
-#define TIMER3_id 3
-#define TIMER4_id 4
-#define TIMER5_id 5
-#define TIMER6_id 6
-#define TIMER7_id 7
-#define TIMER8_id 8
-#define TIMER9_id 9
-#define TIMER10_id 10
-#define TIMER11_id 11
-
-/* associated timers for ppi framesync: */
-
-#if defined(CONFIG_BF561)
-# define FS0_1_TIMER_ID TIMER8_id
-# define FS0_2_TIMER_ID TIMER9_id
-# define FS1_1_TIMER_ID TIMER10_id
-# define FS1_2_TIMER_ID TIMER11_id
-# define FS0_1_TIMER_BIT TIMER8bit
-# define FS0_2_TIMER_BIT TIMER9bit
-# define FS1_1_TIMER_BIT TIMER10bit
-# define FS1_2_TIMER_BIT TIMER11bit
-# undef FS1_TIMER_ID
-# undef FS2_TIMER_ID
-# undef FS1_TIMER_BIT
-# undef FS2_TIMER_BIT
-#else
-# define FS1_TIMER_ID TIMER0_id
-# define FS2_TIMER_ID TIMER1_id
-# define FS1_TIMER_BIT TIMER0bit
-# define FS2_TIMER_BIT TIMER1bit
-#endif
-
-#ifdef CONFIG_BF60x
-/*
- * Timer Configuration Register Bits
- */
-#define TIMER_EMU_RUN 0x8000
-#define TIMER_BPER_EN 0x4000
-#define TIMER_BWID_EN 0x2000
-#define TIMER_BDLY_EN 0x1000
-#define TIMER_OUT_DIS 0x0800
-#define TIMER_TIN_SEL 0x0400
-#define TIMER_CLK_SEL 0x0300
-#define TIMER_CLK_SCLK 0x0000
-#define TIMER_CLK_ALT_CLK0 0x0100
-#define TIMER_CLK_ALT_CLK1 0x0300
-#define TIMER_PULSE_HI 0x0080
-#define TIMER_SLAVE_TRIG 0x0040
-#define TIMER_IRQ_MODE 0x0030
-#define TIMER_IRQ_ACT_EDGE 0x0000
-#define TIMER_IRQ_DLY 0x0010
-#define TIMER_IRQ_WID_DLY 0x0020
-#define TIMER_IRQ_PER 0x0030
-#define TIMER_MODE 0x000f
-#define TIMER_MODE_WDOG_P 0x0008
-#define TIMER_MODE_WDOG_W 0x0009
-#define TIMER_MODE_PWM_CONT 0x000c
-#define TIMER_MODE_PWM 0x000d
-#define TIMER_MODE_WDTH 0x000a
-#define TIMER_MODE_WDTH_D 0x000b
-#define TIMER_MODE_EXT_CLK 0x000e
-#define TIMER_MODE_PININT 0x000f
-
-/*
- * Timer Status Register Bits
- */
-#define TIMER_STATUS_TIMIL0 0x0001
-#define TIMER_STATUS_TIMIL1 0x0002
-#define TIMER_STATUS_TIMIL2 0x0004
-#define TIMER_STATUS_TIMIL3 0x0008
-#define TIMER_STATUS_TIMIL4 0x0010
-#define TIMER_STATUS_TIMIL5 0x0020
-#define TIMER_STATUS_TIMIL6 0x0040
-#define TIMER_STATUS_TIMIL7 0x0080
-
-#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1 0x0002
-#define TIMER_STATUS_TOVF2 0x0004
-#define TIMER_STATUS_TOVF3 0x0008
-#define TIMER_STATUS_TOVF4 0x0010
-#define TIMER_STATUS_TOVF5 0x0020
-#define TIMER_STATUS_TOVF6 0x0040
-#define TIMER_STATUS_TOVF7 0x0080
-
-/*
- * Timer Slave Enable Status : write 1 to clear
- */
-#define TIMER_STATUS_TRUN0 0x0001
-#define TIMER_STATUS_TRUN1 0x0002
-#define TIMER_STATUS_TRUN2 0x0004
-#define TIMER_STATUS_TRUN3 0x0008
-#define TIMER_STATUS_TRUN4 0x0010
-#define TIMER_STATUS_TRUN5 0x0020
-#define TIMER_STATUS_TRUN6 0x0040
-#define TIMER_STATUS_TRUN7 0x0080
-
-#else
-
-/*
- * Timer Configuration Register Bits
- */
-#define TIMER_ERR 0xC000
-#define TIMER_ERR_OVFL 0x4000
-#define TIMER_ERR_PROG_PER 0x8000
-#define TIMER_ERR_PROG_PW 0xC000
-#define TIMER_EMU_RUN 0x0200
-#define TIMER_TOGGLE_HI 0x0100
-#define TIMER_CLK_SEL 0x0080
-#define TIMER_OUT_DIS 0x0040
-#define TIMER_TIN_SEL 0x0020
-#define TIMER_IRQ_ENA 0x0010
-#define TIMER_PERIOD_CNT 0x0008
-#define TIMER_PULSE_HI 0x0004
-#define TIMER_MODE 0x0003
-#define TIMER_MODE_PWM 0x0001
-#define TIMER_MODE_WDTH 0x0002
-#define TIMER_MODE_EXT_CLK 0x0003
-
-/*
- * Timer Status Register Bits
- */
-#define TIMER_STATUS_TIMIL0 0x0001
-#define TIMER_STATUS_TIMIL1 0x0002
-#define TIMER_STATUS_TIMIL2 0x0004
-#define TIMER_STATUS_TIMIL3 0x00000008
-#define TIMER_STATUS_TIMIL4 0x00010000
-#define TIMER_STATUS_TIMIL5 0x00020000
-#define TIMER_STATUS_TIMIL6 0x00040000
-#define TIMER_STATUS_TIMIL7 0x00080000
-#define TIMER_STATUS_TIMIL8 0x0001
-#define TIMER_STATUS_TIMIL9 0x0002
-#define TIMER_STATUS_TIMIL10 0x0004
-#define TIMER_STATUS_TIMIL11 0x0008
-
-#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1 0x0020
-#define TIMER_STATUS_TOVF2 0x0040
-#define TIMER_STATUS_TOVF3 0x00000080
-#define TIMER_STATUS_TOVF4 0x00100000
-#define TIMER_STATUS_TOVF5 0x00200000
-#define TIMER_STATUS_TOVF6 0x00400000
-#define TIMER_STATUS_TOVF7 0x00800000
-#define TIMER_STATUS_TOVF8 0x0010
-#define TIMER_STATUS_TOVF9 0x0020
-#define TIMER_STATUS_TOVF10 0x0040
-#define TIMER_STATUS_TOVF11 0x0080
-
-/*
- * Timer Slave Enable Status : write 1 to clear
- */
-#define TIMER_STATUS_TRUN0 0x1000
-#define TIMER_STATUS_TRUN1 0x2000
-#define TIMER_STATUS_TRUN2 0x4000
-#define TIMER_STATUS_TRUN3 0x00008000
-#define TIMER_STATUS_TRUN4 0x10000000
-#define TIMER_STATUS_TRUN5 0x20000000
-#define TIMER_STATUS_TRUN6 0x40000000
-#define TIMER_STATUS_TRUN7 0x80000000
-#define TIMER_STATUS_TRUN 0xF000F000
-#define TIMER_STATUS_TRUN8 0x1000
-#define TIMER_STATUS_TRUN9 0x2000
-#define TIMER_STATUS_TRUN10 0x4000
-#define TIMER_STATUS_TRUN11 0x8000
-
-#endif
-
-/* The actual gptimer API */
-
-void set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
-uint32_t get_gptimer_pwidth(unsigned int timer_id);
-void set_gptimer_period(unsigned int timer_id, uint32_t period);
-uint32_t get_gptimer_period(unsigned int timer_id);
-#ifdef CONFIG_BF60x
-void set_gptimer_delay(unsigned int timer_id, uint32_t delay);
-uint32_t get_gptimer_delay(unsigned int timer_id);
-#endif
-uint32_t get_gptimer_count(unsigned int timer_id);
-int get_gptimer_intr(unsigned int timer_id);
-void clear_gptimer_intr(unsigned int timer_id);
-int get_gptimer_over(unsigned int timer_id);
-void clear_gptimer_over(unsigned int timer_id);
-void set_gptimer_config(unsigned int timer_id, uint16_t config);
-uint16_t get_gptimer_config(unsigned int timer_id);
-int get_gptimer_run(unsigned int timer_id);
-void set_gptimer_pulse_hi(unsigned int timer_id);
-void clear_gptimer_pulse_hi(unsigned int timer_id);
-void enable_gptimers(uint16_t mask);
-void disable_gptimers(uint16_t mask);
-void disable_gptimers_sync(uint16_t mask);
-uint16_t get_enabled_gptimers(void);
-uint32_t get_gptimer_status(unsigned int group);
-void set_gptimer_status(unsigned int group, uint32_t value);
-
-static inline void enable_gptimer(unsigned int timer_id)
-{
- enable_gptimers(1 << timer_id);
-}
-
-static inline void disable_gptimer(unsigned int timer_id)
-{
- disable_gptimers(1 << timer_id);
-}
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin timer registers layout
- */
-struct bfin_gptimer_regs {
- __BFP(config);
- u32 counter;
- u32 period;
- u32 width;
-#ifdef CONFIG_BF60x
- u32 delay;
-#endif
-};
-
-/*
- * bfin group timer registers layout
- */
-#ifndef CONFIG_BF60x
-struct bfin_gptimer_group_regs {
- __BFP(enable);
- __BFP(disable);
- u32 status;
-};
-#else
-struct bfin_gptimer_group_regs {
- __BFP(run);
- __BFP(enable);
- __BFP(disable);
- __BFP(stop_cfg);
- __BFP(stop_cfg_set);
- __BFP(stop_cfg_clr);
- __BFP(data_imsk);
- __BFP(stat_imsk);
- __BFP(tr_msk);
- __BFP(tr_ie);
- __BFP(data_ilat);
- __BFP(stat_ilat);
- __BFP(err_status);
- __BFP(bcast_per);
- __BFP(bcast_wid);
- __BFP(bcast_dly);
-
-};
-#endif
-
-#undef __BFP
-
-#endif
diff --git a/arch/blackfin/include/asm/hardirq.h b/arch/blackfin/include/asm/hardirq.h
deleted file mode 100644
index 58b54a6..0000000
--- a/arch/blackfin/include/asm/hardirq.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_HARDIRQ_H
-#define __BFIN_HARDIRQ_H
-
-#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
-
-extern void ack_bad_irq(unsigned int irq);
-#define ack_bad_irq ack_bad_irq
-
-#include <asm-generic/hardirq.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
deleted file mode 100644
index 6abebe8..0000000
--- a/arch/blackfin/include/asm/io.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_IO_H
-#define _BFIN_IO_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <asm/byteorder.h>
-#include <asm/def_LPBlackfin.h>
-
-#define __raw_readb bfin_read8
-#define __raw_readw bfin_read16
-#define __raw_readl bfin_read32
-#define __raw_writeb(val, addr) bfin_write8(addr, val)
-#define __raw_writew(val, addr) bfin_write16(addr, val)
-#define __raw_writel(val, addr) bfin_write32(addr, val)
-
-extern void outsb(unsigned long port, const void *addr, unsigned long count);
-extern void outsw(unsigned long port, const void *addr, unsigned long count);
-extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
-extern void outsl(unsigned long port, const void *addr, unsigned long count);
-#define outsb outsb
-#define outsw outsw
-#define outsl outsl
-
-extern void insb(unsigned long port, void *addr, unsigned long count);
-extern void insw(unsigned long port, void *addr, unsigned long count);
-extern void insw_8(unsigned long port, void *addr, unsigned long count);
-extern void insl(unsigned long port, void *addr, unsigned long count);
-extern void insl_16(unsigned long port, void *addr, unsigned long count);
-#define insb insb
-#define insw insw
-#define insl insl
-
-/**
- * I/O write barrier
- *
- * Ensure ordering of I/O space writes. This will make sure that writes
- * following the barrier will arrive after all previous writes.
- */
-#define mmiowb() do { SSYNC(); wmb(); } while (0)
-
-#include <asm-generic/io.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
deleted file mode 100644
index fe1160f..0000000
--- a/arch/blackfin/include/asm/ipipe.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* -*- linux-c -*-
- * include/asm-blackfin/ipipe.h
- *
- * Copyright (C) 2002-2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __ASM_BLACKFIN_IPIPE_H
-#define __ASM_BLACKFIN_IPIPE_H
-
-#ifdef CONFIG_IPIPE
-
-#include <linux/cpumask.h>
-#include <linux/list.h>
-#include <linux/threads.h>
-#include <linux/irq.h>
-#include <linux/ipipe_percpu.h>
-#include <asm/ptrace.h>
-#include <asm/irq.h>
-#include <asm/bitops.h>
-#include <linux/atomic.h>
-#include <asm/traps.h>
-#include <asm/bitsperlong.h>
-
-#define IPIPE_ARCH_STRING "1.16-01"
-#define IPIPE_MAJOR_NUMBER 1
-#define IPIPE_MINOR_NUMBER 16
-#define IPIPE_PATCH_NUMBER 1
-
-#ifdef CONFIG_SMP
-#error "I-pipe/blackfin: SMP not implemented"
-#else /* !CONFIG_SMP */
-#define ipipe_processor_id() 0
-#endif /* CONFIG_SMP */
-
-#define prepare_arch_switch(next) \
-do { \
- ipipe_schedule_notify(current, next); \
- hard_local_irq_disable(); \
-} while (0)
-
-#define task_hijacked(p) \
- ({ \
- int __x__ = __ipipe_root_domain_p; \
- if (__x__) \
- hard_local_irq_enable(); \
- !__x__; \
- })
-
-struct ipipe_domain;
-
-struct ipipe_sysinfo {
- int sys_nr_cpus; /* Number of CPUs on board */
- int sys_hrtimer_irq; /* hrtimer device IRQ */
- u64 sys_hrtimer_freq; /* hrtimer device frequency */
- u64 sys_hrclock_freq; /* hrclock device frequency */
- u64 sys_cpu_freq; /* CPU frequency (Hz) */
-};
-
-#define ipipe_read_tsc(t) \
- ({ \
- unsigned long __cy2; \
- __asm__ __volatile__ ("1: %0 = CYCLES2\n" \
- "%1 = CYCLES\n" \
- "%2 = CYCLES2\n" \
- "CC = %2 == %0\n" \
- "if ! CC jump 1b\n" \
- : "=d,a" (((unsigned long *)&t)[1]), \
- "=d,a" (((unsigned long *)&t)[0]), \
- "=d,a" (__cy2) \
- : /*no input*/ : "CC"); \
- t; \
- })
-
-#define ipipe_cpu_freq() __ipipe_core_clock
-#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale)
-#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1)
-
-/* Private interface -- Internal use only */
-
-#define __ipipe_check_platform() do { } while (0)
-
-#define __ipipe_init_platform() do { } while (0)
-
-extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
-
-extern unsigned long __ipipe_irq_lvmask;
-
-extern struct ipipe_domain ipipe_root;
-
-/* enable/disable_irqdesc _must_ be used in pairs. */
-
-void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
- unsigned irq);
-
-void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
- unsigned irq);
-
-#define __ipipe_enable_irq(irq) \
- do { \
- struct irq_desc *desc = irq_to_desc(irq); \
- struct irq_chip *chip = get_irq_desc_chip(desc); \
- chip->irq_unmask(&desc->irq_data); \
- } while (0)
-
-#define __ipipe_disable_irq(irq) \
- do { \
- struct irq_desc *desc = irq_to_desc(irq); \
- struct irq_chip *chip = get_irq_desc_chip(desc); \
- chip->irq_mask(&desc->irq_data); \
- } while (0)
-
-static inline int __ipipe_check_tickdev(const char *devname)
-{
- return 1;
-}
-
-void __ipipe_enable_pipeline(void);
-
-#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
-
-void ___ipipe_sync_pipeline(void);
-
-void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
-
-int __ipipe_get_irq_priority(unsigned int irq);
-
-void __ipipe_serial_debug(const char *fmt, ...);
-
-asmlinkage void __ipipe_call_irqtail(unsigned long addr);
-
-DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
-
-extern unsigned long __ipipe_core_clock;
-
-extern unsigned long __ipipe_freq_scale;
-
-extern unsigned long __ipipe_irq_tail_hook;
-
-static inline unsigned long __ipipe_ffnz(unsigned long ul)
-{
- return ffs(ul) - 1;
-}
-
-#define __ipipe_do_root_xirq(ipd, irq) \
- ((ipd)->irqs[irq].handler(irq, raw_cpu_ptr(&__ipipe_tick_regs)))
-
-#define __ipipe_run_irqtail(irq) /* Must be a macro */ \
- do { \
- unsigned long __pending; \
- CSYNC(); \
- __pending = bfin_read_IPEND(); \
- if (__pending & 0x8000) { \
- __pending &= ~0x8010; \
- if (__pending && (__pending & (__pending - 1)) == 0) \
- __ipipe_call_irqtail(__ipipe_irq_tail_hook); \
- } \
- } while (0)
-
-#define __ipipe_syscall_watched_p(p, sc) \
- (ipipe_notifier_enabled_p(p) || (unsigned long)sc >= NR_syscalls)
-
-#ifdef CONFIG_BF561
-#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
-#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
-#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
-#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
-#elif defined(CONFIG_BF54x)
-#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
-#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
-#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
-#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
-#endif
-
-#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
-
-#else /* !CONFIG_IPIPE */
-
-#define task_hijacked(p) 0
-#define ipipe_trap_notify(t, r) 0
-#define __ipipe_root_tick_p(regs) 1
-
-#endif /* !CONFIG_IPIPE */
-
-#ifdef CONFIG_TICKSOURCE_CORETMR
-#define IRQ_SYSTMR IRQ_CORETMR
-#define IRQ_PRIOTMR IRQ_CORETMR
-#else
-#define IRQ_SYSTMR IRQ_TIMER0
-#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
-#endif
-
-#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
-
-#endif /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
deleted file mode 100644
index 84a4ffd..0000000
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* -*- linux-c -*-
- * include/asm-blackfin/ipipe_base.h
- *
- * Copyright (C) 2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __ASM_BLACKFIN_IPIPE_BASE_H
-#define __ASM_BLACKFIN_IPIPE_BASE_H
-
-#ifdef CONFIG_IPIPE
-
-#include <asm/bitsperlong.h>
-#include <mach/irq.h>
-
-#define IPIPE_NR_XIRQS NR_IRQS
-
-/* Blackfin-specific, per-cpu pipeline status */
-#define IPIPE_SYNCDEFER_FLAG 15
-#define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK)
-
- /* Blackfin traps -- i.e. exception vector numbers */
-#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */
-/* Pseudo-vectors used for kernel events */
-#define IPIPE_FIRST_EVENT IPIPE_NR_FAULTS
-#define IPIPE_EVENT_SYSCALL (IPIPE_FIRST_EVENT)
-#define IPIPE_EVENT_SCHEDULE (IPIPE_FIRST_EVENT + 1)
-#define IPIPE_EVENT_SIGWAKE (IPIPE_FIRST_EVENT + 2)
-#define IPIPE_EVENT_SETSCHED (IPIPE_FIRST_EVENT + 3)
-#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4)
-#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5)
-#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6)
-#define IPIPE_EVENT_RETURN (IPIPE_FIRST_EVENT + 7)
-#define IPIPE_LAST_EVENT IPIPE_EVENT_RETURN
-#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1)
-
-#define IPIPE_TIMER_IRQ IRQ_CORETMR
-
-#define __IPIPE_FEATURE_SYSINFO_V2 1
-
-#ifndef __ASSEMBLY__
-
-extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
-
-void __ipipe_stall_root(void);
-
-unsigned long __ipipe_test_and_stall_root(void);
-
-unsigned long __ipipe_test_root(void);
-
-void __ipipe_lock_root(void);
-
-void __ipipe_unlock_root(void);
-
-#endif /* !__ASSEMBLY__ */
-
-#define __IPIPE_FEATURE_SYSINFO_V2 1
-
-#endif /* CONFIG_IPIPE */
-
-#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
deleted file mode 100644
index 89de539..0000000
--- a/arch/blackfin/include/asm/irq.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2003 HuTao
- * 2002 Arcturus Networks Inc. (www.arcturusnetworks.com
- * Ted Ma <mated@sympatico.ca>
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_IRQ_H_
-#define _BFIN_IRQ_H_
-
-#include <linux/irqflags.h>
-
-/* IRQs that may be used by external irq_chip controllers */
-#define NR_SPARE_IRQS 32
-
-#include <mach/anomaly.h>
-
-/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
-#include <mach/irq.h>
-
-#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
-# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
-#else
-# define NOP_PAD_ANOMALY_05000244
-#endif
-
-#define idle_with_irq_disabled() \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000244 \
- ".align 8;" \
- "sti %0;" \
- "idle;" \
- : \
- : "d" (bfin_irq_flags) \
- )
-
-#include <asm-generic/irq.h>
-
-#endif /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
deleted file mode 100644
index d2f90c7..0000000
--- a/arch/blackfin/include/asm/irq_handler.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _IRQ_HANDLER_H
-#define _IRQ_HANDLER_H
-
-#include <linux/types.h>
-#include <linux/linkage.h>
-#include <mach/irq.h>
-
-/* init functions only */
-extern int init_arch_irq(void);
-extern void init_exception_vectors(void);
-extern void program_IAR(void);
-#ifdef init_mach_irq
-extern void init_mach_irq(void);
-#else
-# define init_mach_irq()
-#endif
-
-/* BASE LEVEL interrupt handler routines */
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_evt14(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-asmlinkage void init_exception_buff(void);
-asmlinkage void trap_c(struct pt_regs *fp);
-asmlinkage void ex_replaceable(void);
-asmlinkage void early_trap(void);
-
-extern void *ex_table[];
-extern void return_from_exception(void);
-
-extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
-extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
-
-extern asmlinkage void lower_to_irq14(void);
-extern asmlinkage void bfin_return_from_exception(void);
-extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
-struct irq_data;
-extern void bfin_handle_irq(unsigned irq);
-extern void bfin_ack_noop(struct irq_data *);
-extern void bfin_internal_mask_irq(unsigned int irq);
-extern void bfin_internal_unmask_irq(unsigned int irq);
-
-struct irq_desc;
-extern void bfin_demux_mac_status_irq(struct irq_desc *);
-extern void bfin_demux_gpio_irq(struct irq_desc *);
-
-#endif
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
deleted file mode 100644
index 07aff23..0000000
--- a/arch/blackfin/include/asm/irqflags.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * interface to Blackfin CEC
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_IRQFLAGS_H__
-#define __ASM_BFIN_IRQFLAGS_H__
-
-#include <mach/blackfin.h>
-
-#ifdef CONFIG_SMP
-# include <asm/pda.h>
-# include <asm/processor.h>
-# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
-#else
-extern unsigned long bfin_irq_flags;
-#endif
-
-static inline notrace void bfin_sti(unsigned long flags)
-{
- asm volatile("sti %0;" : : "d" (flags));
-}
-
-static inline notrace unsigned long bfin_cli(void)
-{
- unsigned long flags;
- asm volatile("cli %0;" : "=d" (flags));
- return flags;
-}
-
-#ifdef CONFIG_DEBUG_HWERR
-# define bfin_no_irqs 0x3f
-#else
-# define bfin_no_irqs 0x1f
-#endif
-
-/*****************************************************************************/
-/*
- * Hard, untraced CPU interrupt flag manipulation and access.
- */
-static inline notrace void __hard_local_irq_disable(void)
-{
- bfin_cli();
-}
-
-static inline notrace void __hard_local_irq_enable(void)
-{
- bfin_sti(bfin_irq_flags);
-}
-
-static inline notrace unsigned long hard_local_save_flags(void)
-{
- return bfin_read_IMASK();
-}
-
-static inline notrace unsigned long __hard_local_irq_save(void)
-{
- unsigned long flags;
- flags = bfin_cli();
-#ifdef CONFIG_DEBUG_HWERR
- bfin_sti(0x3f);
-#endif
- return flags;
-}
-
-static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
-{
-#ifdef CONFIG_BF60x
- return (flags & IMASK_IVG11) == 0;
-#else
- return (flags & ~0x3f) == 0;
-#endif
-}
-
-static inline notrace int hard_irqs_disabled(void)
-{
- unsigned long flags = hard_local_save_flags();
- return hard_irqs_disabled_flags(flags);
-}
-
-static inline notrace void __hard_local_irq_restore(unsigned long flags)
-{
- if (!hard_irqs_disabled_flags(flags))
- __hard_local_irq_enable();
-}
-
-/*****************************************************************************/
-/*
- * Interrupt pipe handling.
- */
-#ifdef CONFIG_IPIPE
-
-#include <linux/compiler.h>
-#include <linux/ipipe_trace.h>
-/*
- * Way too many inter-deps between low-level headers in this port, so
- * we redeclare the required bits we cannot pick from
- * <asm/ipipe_base.h> to prevent circular dependencies.
- */
-void __ipipe_stall_root(void);
-void __ipipe_unstall_root(void);
-unsigned long __ipipe_test_root(void);
-unsigned long __ipipe_test_and_stall_root(void);
-void __ipipe_restore_root(unsigned long flags);
-
-#ifdef CONFIG_IPIPE_DEBUG_CONTEXT
-struct ipipe_domain;
-extern struct ipipe_domain ipipe_root;
-void ipipe_check_context(struct ipipe_domain *ipd);
-#define __check_irqop_context(ipd) ipipe_check_context(&ipipe_root)
-#else /* !CONFIG_IPIPE_DEBUG_CONTEXT */
-#define __check_irqop_context(ipd) do { } while (0)
-#endif /* !CONFIG_IPIPE_DEBUG_CONTEXT */
-
-/*
- * Interrupt pipe interface to linux/irqflags.h.
- */
-static inline notrace void arch_local_irq_disable(void)
-{
- __check_irqop_context();
- __ipipe_stall_root();
- barrier();
-}
-
-static inline notrace void arch_local_irq_enable(void)
-{
- barrier();
- __check_irqop_context();
- __ipipe_unstall_root();
-}
-
-static inline notrace unsigned long arch_local_save_flags(void)
-{
- return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
-}
-
-static inline notrace int arch_irqs_disabled_flags(unsigned long flags)
-{
- return flags == bfin_no_irqs;
-}
-
-static inline notrace unsigned long arch_local_irq_save(void)
-{
- unsigned long flags;
-
- __check_irqop_context();
- flags = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags;
- barrier();
-
- return flags;
-}
-
-static inline notrace void arch_local_irq_restore(unsigned long flags)
-{
- __check_irqop_context();
- __ipipe_restore_root(flags == bfin_no_irqs);
-}
-
-static inline notrace unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
-{
- /*
- * Merge virtual and real interrupt mask bits into a single
- * 32bit word.
- */
- return (real & ~(1 << 31)) | ((virt != 0) << 31);
-}
-
-static inline notrace int arch_demangle_irq_bits(unsigned long *x)
-{
- int virt = (*x & (1 << 31)) != 0;
- *x &= ~(1L << 31);
- return virt;
-}
-
-/*
- * Interface to various arch routines that may be traced.
- */
-#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
-static inline notrace void hard_local_irq_disable(void)
-{
- if (!hard_irqs_disabled()) {
- __hard_local_irq_disable();
- ipipe_trace_begin(0x80000000);
- }
-}
-
-static inline notrace void hard_local_irq_enable(void)
-{
- if (hard_irqs_disabled()) {
- ipipe_trace_end(0x80000000);
- __hard_local_irq_enable();
- }
-}
-
-static inline notrace unsigned long hard_local_irq_save(void)
-{
- unsigned long flags = hard_local_save_flags();
- if (!hard_irqs_disabled_flags(flags)) {
- __hard_local_irq_disable();
- ipipe_trace_begin(0x80000001);
- }
- return flags;
-}
-
-static inline notrace void hard_local_irq_restore(unsigned long flags)
-{
- if (!hard_irqs_disabled_flags(flags)) {
- ipipe_trace_end(0x80000001);
- __hard_local_irq_enable();
- }
-}
-
-#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
-# define hard_local_irq_disable() __hard_local_irq_disable()
-# define hard_local_irq_enable() __hard_local_irq_enable()
-# define hard_local_irq_save() __hard_local_irq_save()
-# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
-
-#define hard_local_irq_save_cond() hard_local_irq_save()
-#define hard_local_irq_restore_cond(flags) hard_local_irq_restore(flags)
-
-#else /* !CONFIG_IPIPE */
-
-/*
- * Direct interface to linux/irqflags.h.
- */
-#define arch_local_save_flags() hard_local_save_flags()
-#define arch_local_irq_save() __hard_local_irq_save()
-#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#define arch_local_irq_enable() __hard_local_irq_enable()
-#define arch_local_irq_disable() __hard_local_irq_disable()
-#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags)
-#define arch_irqs_disabled() hard_irqs_disabled()
-
-/*
- * Interface to various arch routines that may be traced.
- */
-#define hard_local_irq_save() __hard_local_irq_save()
-#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#define hard_local_irq_enable() __hard_local_irq_enable()
-#define hard_local_irq_disable() __hard_local_irq_disable()
-#define hard_local_irq_save_cond() hard_local_save_flags()
-#define hard_local_irq_restore_cond(flags) do { (void)(flags); } while (0)
-
-#endif /* !CONFIG_IPIPE */
-
-#ifdef CONFIG_SMP
-#define hard_local_irq_save_smp() hard_local_irq_save()
-#define hard_local_irq_restore_smp(flags) hard_local_irq_restore(flags)
-#else
-#define hard_local_irq_save_smp() hard_local_save_flags()
-#define hard_local_irq_restore_smp(flags) do { (void)(flags); } while (0)
-#endif
-
-/*
- * Remap the arch-neutral IRQ state manipulation macros to the
- * blackfin-specific hard_local_irq_* API.
- */
-#define local_irq_save_hw(flags) \
- do { \
- (flags) = hard_local_irq_save(); \
- } while (0)
-#define local_irq_restore_hw(flags) \
- do { \
- hard_local_irq_restore(flags); \
- } while (0)
-#define local_irq_disable_hw() \
- do { \
- hard_local_irq_disable(); \
- } while (0)
-#define local_irq_enable_hw() \
- do { \
- hard_local_irq_enable(); \
- } while (0)
-#define local_irq_save_hw_notrace(flags) \
- do { \
- (flags) = __hard_local_irq_save(); \
- } while (0)
-#define local_irq_restore_hw_notrace(flags) \
- do { \
- __hard_local_irq_restore(flags); \
- } while (0)
-
-#define irqs_disabled_hw() hard_irqs_disabled()
-
-#endif
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
deleted file mode 100644
index 2703dde..0000000
--- a/arch/blackfin/include/asm/kgdb.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Blackfin KGDB header
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_KGDB_H__
-#define __ASM_BLACKFIN_KGDB_H__
-
-#include <linux/ptrace.h>
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
- * At least NUMREGBYTES*2 are needed for register packets.
- * Longer buffer is needed to list all threads.
- */
-#define BUFMAX 2048
-
-/*
- * Note that this register image is different from
- * the register image that Linux produces at interrupt time.
- *
- * Linux's register image is defined by struct pt_regs in ptrace.h.
- */
-enum regnames {
- /* Core Registers */
- BFIN_R0 = 0,
- BFIN_R1,
- BFIN_R2,
- BFIN_R3,
- BFIN_R4,
- BFIN_R5,
- BFIN_R6,
- BFIN_R7,
- BFIN_P0,
- BFIN_P1,
- BFIN_P2,
- BFIN_P3,
- BFIN_P4,
- BFIN_P5,
- BFIN_SP,
- BFIN_FP,
- BFIN_I0,
- BFIN_I1,
- BFIN_I2,
- BFIN_I3,
- BFIN_M0,
- BFIN_M1,
- BFIN_M2,
- BFIN_M3,
- BFIN_B0,
- BFIN_B1,
- BFIN_B2,
- BFIN_B3,
- BFIN_L0,
- BFIN_L1,
- BFIN_L2,
- BFIN_L3,
- BFIN_A0_DOT_X,
- BFIN_A0_DOT_W,
- BFIN_A1_DOT_X,
- BFIN_A1_DOT_W,
- BFIN_ASTAT,
- BFIN_RETS,
- BFIN_LC0,
- BFIN_LT0,
- BFIN_LB0,
- BFIN_LC1,
- BFIN_LT1,
- BFIN_LB1,
- BFIN_CYCLES,
- BFIN_CYCLES2,
- BFIN_USP,
- BFIN_SEQSTAT,
- BFIN_SYSCFG,
- BFIN_RETI,
- BFIN_RETX,
- BFIN_RETN,
- BFIN_RETE,
-
- /* Pseudo Registers */
- BFIN_PC,
- BFIN_CC,
- BFIN_EXTRA1, /* Address of .text section. */
- BFIN_EXTRA2, /* Address of .data section. */
- BFIN_EXTRA3, /* Address of .bss section. */
- BFIN_FDPIC_EXEC,
- BFIN_FDPIC_INTERP,
-
- /* MMRs */
- BFIN_IPEND,
-
- /* LAST ENTRY SHOULD NOT BE CHANGED. */
- BFIN_NUM_REGS /* The number of all registers. */
-};
-
-/* Number of bytes of registers. */
-#define NUMREGBYTES BFIN_NUM_REGS*4
-
-static inline void arch_kgdb_breakpoint(void)
-{
- asm("EXCPT 2;");
-}
-#define BREAK_INSTR_SIZE 2
-#ifdef CONFIG_SMP
-# define CACHE_FLUSH_IS_SAFE 0
-#else
-# define CACHE_FLUSH_IS_SAFE 1
-#endif
-#define GDB_ADJUSTS_BREAK_OFFSET
-#define GDB_SKIP_HW_WATCH_TEST
-#define HW_INST_WATCHPOINT_NUM 6
-#define HW_WATCHPOINT_NUM 8
-#define TYPE_INST_WATCHPOINT 0
-#define TYPE_DATA_WATCHPOINT 1
-
-/* Instruction watchpoint address control register bits mask */
-#define WPPWR 0x1
-#define WPIREN01 0x2
-#define WPIRINV01 0x4
-#define WPIAEN0 0x8
-#define WPIAEN1 0x10
-#define WPICNTEN0 0x20
-#define WPICNTEN1 0x40
-#define EMUSW0 0x80
-#define EMUSW1 0x100
-#define WPIREN23 0x200
-#define WPIRINV23 0x400
-#define WPIAEN2 0x800
-#define WPIAEN3 0x1000
-#define WPICNTEN2 0x2000
-#define WPICNTEN3 0x4000
-#define EMUSW2 0x8000
-#define EMUSW3 0x10000
-#define WPIREN45 0x20000
-#define WPIRINV45 0x40000
-#define WPIAEN4 0x80000
-#define WPIAEN5 0x100000
-#define WPICNTEN4 0x200000
-#define WPICNTEN5 0x400000
-#define EMUSW4 0x800000
-#define EMUSW5 0x1000000
-#define WPAND 0x2000000
-
-/* Data watchpoint address control register bits mask */
-#define WPDREN01 0x1
-#define WPDRINV01 0x2
-#define WPDAEN0 0x4
-#define WPDAEN1 0x8
-#define WPDCNTEN0 0x10
-#define WPDCNTEN1 0x20
-
-#define WPDSRC0 0xc0
-#define WPDACC0_OFFSET 8
-#define WPDSRC1 0xc00
-#define WPDACC1_OFFSET 12
-
-/* Watchpoint status register bits mask */
-#define STATIA0 0x1
-#define STATIA1 0x2
-#define STATIA2 0x4
-#define STATIA3 0x8
-#define STATIA4 0x10
-#define STATIA5 0x20
-#define STATDA0 0x40
-#define STATDA1 0x80
-
-#endif
diff --git a/arch/blackfin/include/asm/l1layout.h b/arch/blackfin/include/asm/l1layout.h
deleted file mode 100644
index c87e686..0000000
--- a/arch/blackfin/include/asm/l1layout.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Defines a layout of L1 scratchpad memory that userspace can rely on.
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _L1LAYOUT_H_
-#define _L1LAYOUT_H_
-
-#include <asm/blackfin.h>
-
-#ifndef CONFIG_SMP
-#ifndef __ASSEMBLY__
-
-/* Data that is "mapped" into the process VM at the start of the L1 scratch
- memory, so that each process can access it at a fixed address. Used for
- stack checking. */
-struct l1_scratch_task_info
-{
- /* Points to the start of the stack. */
- void *stack_start;
- /* Not updated by the kernel; a user process can modify this to
- keep track of the lowest address of the stack pointer during its
- runtime. */
- void *lowest_sp;
-};
-
-/* A pointer to the structure in memory. */
-#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)\
- get_l1_scratch_start())
-
-#endif
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h
deleted file mode 100644
index f7d6d47..0000000
--- a/arch/blackfin/include/asm/linkage.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .align 4
-#define __ALIGN_STR ".align 4"
-
-#endif
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
deleted file mode 100644
index c865b33..0000000
--- a/arch/blackfin/include/asm/mem_init.h
+++ /dev/null
@@ -1,500 +0,0 @@
-/*
- * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MEM_INIT_H__
-#define __MEM_INIT_H__
-
-#if defined(EBIU_SDGCTL)
-#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
- defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75) || \
- defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
- defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_7
-#define SDRAM_tRAS_num 7
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_6
-#define SDRAM_tRAS_num 6
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_5
-#define SDRAM_tRAS_num 5
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_2
-#define SDRAM_tRAS_num 2
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_1
-#define SDRAM_tRAS_num 1
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#endif
-
-/*
- * The BF526-EZ-Board changed SDRAM chips between revisions,
- * so we use below timings to accommodate both.
- */
-#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_8
-#define SDRAM_tRAS_num 8
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_7
-#define SDRAM_tRAS_num 7
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_6
-#define SDRAM_tRAS_num 6
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_5
-#define SDRAM_tRAS_num 5
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_2
-#define SDRAM_tRAS_num 2
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#endif
-
-#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
- defined(CONFIG_MEM_MT48LC8M32B2B5_7)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_3
-#endif
-
-#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
- defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
- defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_3
-#endif
-
-#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_2
-#endif
-
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-#else
-#define mem_SDRRC CONFIG_MEM_SDRRC
-#define mem_SDGCTL CONFIG_MEM_SDGCTL
-#endif
-#endif
-
-
-#if defined(EBIU_DDRCTL0)
-#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
-#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
-#define DDR_CLK_HZ(x) (1000*1000*1000/x)
-
-#if defined(CONFIG_MEM_MT46V32M16_6T)
-#define DDR_SIZE DEVSZ_512
-#define DDR_WIDTH DEVWD_16
-#define DDR_MAX_tCK 13
-
-#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
-#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
-#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
-#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR DDR_TWTR(1)
-#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
-#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if defined(CONFIG_MEM_MT46V32M16_5B)
-#define DDR_SIZE DEVSZ_512
-#define DDR_WIDTH DEVWD_16
-#define DDR_MAX_tCK 13
-
-#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
-#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
-#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
-#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR DDR_TWTR(2)
-#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
-#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
-# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
-#elif(CONFIG_SCLK_HZ <= 133333333)
-# define DDR_CL CL_2
-#else
-# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
-#endif
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
-#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
-#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
- | DDR_tMRD | DDR_tWR | DDR_tRCD)
-#define mem_DDRCTL2 DDR_CL
-#else
-#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0
-#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1
-#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2
-#endif
-#endif
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF 1
-#else
-#define CLKIN_HALF 0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS 1
-#else
-#define PLL_BYPASS 0
-#endif
-
-#ifdef CONFIG_BF60x
-
-/* DMC status bits */
-#define IDLE 0x1
-#define MEMINITDONE 0x4
-#define SRACK 0x8
-#define PDACK 0x10
-#define DPDACK 0x20
-#define DLLCALDONE 0x2000
-#define PENDREF 0xF0000
-#define PHYRDPHASE 0xF00000
-#define PHYRDPHASE_OFFSET 20
-
-/* DMC control bits */
-#define LPDDR 0x2
-#define INIT 0x4
-#define SRREQ 0x8
-#define PDREQ 0x10
-#define DPDREQ 0x20
-#define PREC 0x40
-#define ADDRMODE 0x100
-#define RDTOWR 0xE00
-#define PPREF 0x1000
-#define DLLCAL 0x2000
-
-/* DMC DLL control bits */
-#define DLLCALRDCNT 0xFF
-#define DATACYC 0xF00
-#define DATACYC_OFFSET 8
-
-/* CGU Divisor bits */
-#define CSEL_OFFSET 0
-#define S0SEL_OFFSET 5
-#define SYSSEL_OFFSET 8
-#define S1SEL_OFFSET 13
-#define DSEL_OFFSET 16
-#define OSEL_OFFSET 22
-#define ALGN 0x20000000
-#define UPDT 0x40000000
-#define LOCK 0x80000000
-
-/* CGU Status bits */
-#define PLLEN 0x1
-#define PLLBP 0x2
-#define PLOCK 0x4
-#define CLKSALGN 0x8
-
-/* CGU Control bits */
-#define MSEL_MASK 0x7F00
-#define DF_MASK 0x1
-
-struct ddr_config {
- u32 ddr_clk;
- u32 dmc_ddrctl;
- u32 dmc_effctl;
- u32 dmc_ddrcfg;
- u32 dmc_ddrtr0;
- u32 dmc_ddrtr1;
- u32 dmc_ddrtr2;
- u32 dmc_ddrmr;
- u32 dmc_ddrmr1;
-};
-
-#if defined(CONFIG_MEM_MT47H64M16)
-static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
- [0] = {
- .ddr_clk = 125,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20705212,
- .dmc_ddrtr1 = 0x201003CF,
- .dmc_ddrtr2 = 0x00320107,
- .dmc_ddrmr = 0x00000422,
- .dmc_ddrmr1 = 0x4,
- },
- [1] = {
- .ddr_clk = 133,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20806313,
- .dmc_ddrtr1 = 0x2013040D,
- .dmc_ddrtr2 = 0x00320108,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [2] = {
- .ddr_clk = 150,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20A07323,
- .dmc_ddrtr1 = 0x20160492,
- .dmc_ddrtr2 = 0x00320209,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [3] = {
- .ddr_clk = 166,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20A07323,
- .dmc_ddrtr1 = 0x2016050E,
- .dmc_ddrtr2 = 0x00320209,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [4] = {
- .ddr_clk = 200,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20a07323,
- .dmc_ddrtr1 = 0x2016050f,
- .dmc_ddrtr2 = 0x00320509,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [5] = {
- .ddr_clk = 225,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20E0A424,
- .dmc_ddrtr1 = 0x302006DB,
- .dmc_ddrtr2 = 0x0032020D,
- .dmc_ddrmr = 0x00000842,
- .dmc_ddrmr1 = 0x4,
- },
- [6] = {
- .ddr_clk = 250,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20E0A424,
- .dmc_ddrtr1 = 0x3020079E,
- .dmc_ddrtr2 = 0x0032050D,
- .dmc_ddrmr = 0x00000842,
- .dmc_ddrmr1 = 0x4,
- },
-};
-#endif
-
-static inline void dmc_enter_self_refresh(void)
-{
- if (bfin_read_DMC0_STAT() & MEMINITDONE) {
- bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
- while (!(bfin_read_DMC0_STAT() & SRACK))
- continue;
- }
-}
-
-static inline void dmc_exit_self_refresh(void)
-{
- if (bfin_read_DMC0_STAT() & MEMINITDONE) {
- bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
- while (bfin_read_DMC0_STAT() & SRACK)
- continue;
- }
-}
-
-static inline void init_cgu(u32 cgu_div, u32 cgu_ctl)
-{
- dmc_enter_self_refresh();
-
- /* Don't set the same value of MSEL and DF to CGU_CTL */
- if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK))
- != cgu_ctl) {
- bfin_write32(CGU0_DIV, cgu_div);
- bfin_write32(CGU0_CTL, cgu_ctl);
- while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) ||
- !(bfin_read32(CGU0_STAT) & PLOCK))
- continue;
- }
-
- bfin_write32(CGU0_DIV, cgu_div | UPDT);
- while (bfin_read32(CGU0_STAT) & CLKSALGN)
- continue;
-
- dmc_exit_self_refresh();
-}
-
-static inline void init_dmc(u32 dmc_clk)
-{
- int i, dlldatacycle, dll_ctl;
-
- for (i = 0; i < 7; i++) {
- if (ddr_config_table[i].ddr_clk == dmc_clk) {
- bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
- bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
- bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
- bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
- bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
- bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
- bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl);
- bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
- break;
- }
- }
-
- while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
- continue;
-
- dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET;
- dll_ctl = bfin_read_DMC0_DLLCTL();
- dll_ctl &= ~DATACYC;
- bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
-
- while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
- continue;
-}
-#endif
-
-#endif /*__MEM_INIT_H__*/
-
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
deleted file mode 100644
index 5e21627..0000000
--- a/arch/blackfin/include/asm/mem_map.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MEM_MAP_H__
-#define __BFIN_MEM_MAP_H__
-
-#include <mach/mem_map.h>
-
-/* Every Blackfin so far has MMRs like this */
-#ifndef COREMMR_BASE
-# define COREMMR_BASE 0xFFE00000
-#endif
-#ifndef SYSMMR_BASE
-# define SYSMMR_BASE 0xFFC00000
-#endif
-
-/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
-#ifndef L1_SCRATCH_START
-# define L1_SCRATCH_START 0xFFB00000
-# define L1_SCRATCH_LENGTH 0x1000
-#endif
-
-/* Most parts lack on-chip L2 SRAM */
-#ifndef L2_START
-# define L2_START 0
-# define L2_LENGTH 0
-#endif
-
-/* Most parts lack on-chip L1 ROM */
-#ifndef L1_ROM_START
-# define L1_ROM_START 0
-# define L1_ROM_LENGTH 0
-#endif
-
-/* Allow wonky SMP ports to override this */
-#ifndef GET_PDA_SAFE
-# define GET_PDA_SAFE(preg) \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda;
-# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
-
-# ifndef __ASSEMBLY__
-
-static inline unsigned long get_l1_scratch_start_cpu(int cpu)
-{
- return L1_SCRATCH_START;
-}
-static inline unsigned long get_l1_code_start_cpu(int cpu)
-{
- return L1_CODE_START;
-}
-static inline unsigned long get_l1_data_a_start_cpu(int cpu)
-{
- return L1_DATA_A_START;
-}
-static inline unsigned long get_l1_data_b_start_cpu(int cpu)
-{
- return L1_DATA_B_START;
-}
-static inline unsigned long get_l1_scratch_start(void)
-{
- return get_l1_scratch_start_cpu(0);
-}
-static inline unsigned long get_l1_code_start(void)
-{
- return get_l1_code_start_cpu(0);
-}
-static inline unsigned long get_l1_data_a_start(void)
-{
- return get_l1_data_a_start_cpu(0);
-}
-static inline unsigned long get_l1_data_b_start(void)
-{
- return get_l1_data_b_start_cpu(0);
-}
-
-# endif /* __ASSEMBLY__ */
-#endif /* !GET_PDA_SAFE */
-
-#endif
diff --git a/arch/blackfin/include/asm/mmu.h b/arch/blackfin/include/asm/mmu.h
deleted file mode 100644
index 26f6b70..0000000
--- a/arch/blackfin/include/asm/mmu.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2002 David McCullough <davidm@snapgear.com>
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef __MMU_H
-#define __MMU_H
-
-struct sram_list_struct {
- struct sram_list_struct *next;
- void *addr;
- size_t length;
-};
-
-typedef struct {
- unsigned long end_brk;
- unsigned long stack_start;
-
- /* Points to the location in SDRAM where the L1 stack is normally
- saved, or NULL if the stack is always in SDRAM. */
- void *l1_stack_save;
-
- struct sram_list_struct *sram_list;
-
-#ifdef CONFIG_BINFMT_ELF_FDPIC
- unsigned long exec_fdpic_loadmap;
- unsigned long interp_fdpic_loadmap;
-#endif
-#ifdef CONFIG_MPU
- unsigned long *page_rwx_mask;
-#endif
-} mm_context_t;
-
-#endif
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
deleted file mode 100644
index 0ce6de8..0000000
--- a/arch/blackfin/include/asm/mmu_context.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_MMU_CONTEXT_H__
-#define __BLACKFIN_MMU_CONTEXT_H__
-
-#include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/mm_types.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/cplbinit.h>
-#include <asm/sections.h>
-
-/* Note: L1 stacks are CPU-private things, so we bluntly disable this
- feature in SMP mode, and use the per-CPU scratch SRAM bank only to
- store the PDA instead. */
-
-extern void *current_l1_stack_save;
-extern int nr_l1stack_tasks;
-extern void *l1_stack_base;
-extern unsigned long l1_stack_len;
-
-extern int l1sram_free(const void*);
-extern void *l1sram_alloc_max(void*);
-
-static inline void free_l1stack(void)
-{
- nr_l1stack_tasks--;
- if (nr_l1stack_tasks == 0) {
- l1sram_free(l1_stack_base);
- l1_stack_base = NULL;
- l1_stack_len = 0;
- }
-}
-
-static inline unsigned long
-alloc_l1stack(unsigned long length, unsigned long *stack_base)
-{
- if (nr_l1stack_tasks == 0) {
- l1_stack_base = l1sram_alloc_max(&l1_stack_len);
- if (!l1_stack_base)
- return 0;
- }
-
- if (l1_stack_len < length) {
- if (nr_l1stack_tasks == 0)
- l1sram_free(l1_stack_base);
- return 0;
- }
- *stack_base = (unsigned long)l1_stack_base;
- nr_l1stack_tasks++;
- return l1_stack_len;
-}
-
-static inline int
-activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
-{
- if (current_l1_stack_save)
- memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
- mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
- memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
- return 1;
-}
-
-#define deactivate_mm(tsk,mm) do { } while (0)
-
-#define activate_mm(prev, next) switch_mm(prev, next, NULL)
-
-static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
- struct task_struct *tsk)
-{
-#ifdef CONFIG_MPU
- unsigned int cpu = smp_processor_id();
-#endif
- if (prev_mm == next_mm)
- return;
-#ifdef CONFIG_MPU
- if (prev_mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
- flush_switched_cplbs(cpu);
- set_mask_dcplbs(next_mm->context.page_rwx_mask, cpu);
- }
-#endif
-
-#ifdef CONFIG_APP_STACK_L1
- /* L1 stack switching. */
- if (!next_mm->context.l1_stack_save)
- return;
- if (next_mm->context.l1_stack_save == current_l1_stack_save)
- return;
- if (current_l1_stack_save) {
- memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
- }
- current_l1_stack_save = next_mm->context.l1_stack_save;
- memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
-#endif
-}
-
-#ifdef CONFIG_IPIPE
-#define lock_mm_switch(flags) flags = hard_local_irq_save_cond()
-#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags)
-#else
-#define lock_mm_switch(flags) do { (void)(flags); } while (0)
-#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
-#endif /* CONFIG_IPIPE */
-
-#ifdef CONFIG_MPU
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- unsigned long flags;
- lock_mm_switch(flags);
- __switch_mm(prev, next, tsk);
- unlock_mm_switch(flags);
-}
-
-static inline void protect_page(struct mm_struct *mm, unsigned long addr,
- unsigned long flags)
-{
- unsigned long *mask = mm->context.page_rwx_mask;
- unsigned long page;
- unsigned long idx;
- unsigned long bit;
-
- if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
- page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12;
- else
- page = addr >> 12;
- idx = page >> 5;
- bit = 1 << (page & 31);
-
- if (flags & VM_READ)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
- mask += page_mask_nelts;
- if (flags & VM_WRITE)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
- mask += page_mask_nelts;
- if (flags & VM_EXEC)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
-}
-
-static inline void update_protections(struct mm_struct *mm)
-{
- unsigned int cpu = smp_processor_id();
- if (mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
- flush_switched_cplbs(cpu);
- set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
- }
-}
-#else /* !CONFIG_MPU */
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- __switch_mm(prev, next, tsk);
-}
-#endif
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-/* Called when creating a new context during fork() or execve(). */
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-#ifdef CONFIG_MPU
- unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
- mm->context.page_rwx_mask = (unsigned long *)p;
- memset(mm->context.page_rwx_mask, 0,
- page_mask_nelts * 3 * sizeof(long));
-#endif
- return 0;
-}
-
-static inline void destroy_context(struct mm_struct *mm)
-{
- struct sram_list_struct *tmp;
-#ifdef CONFIG_MPU
- unsigned int cpu = smp_processor_id();
-#endif
-
-#ifdef CONFIG_APP_STACK_L1
- if (current_l1_stack_save == mm->context.l1_stack_save)
- current_l1_stack_save = 0;
- if (mm->context.l1_stack_save)
- free_l1stack();
-#endif
-
- while ((tmp = mm->context.sram_list)) {
- mm->context.sram_list = tmp->next;
- sram_free(tmp->addr);
- kfree(tmp);
- }
-#ifdef CONFIG_MPU
- if (current_rwx_mask[cpu] == mm->context.page_rwx_mask)
- current_rwx_mask[cpu] = NULL;
- free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
-#endif
-}
-
-#define ipipe_mm_switch_protect(flags) \
- flags = hard_local_irq_save_cond()
-
-#define ipipe_mm_switch_unprotect(flags) \
- hard_local_irq_restore_cond(flags)
-
-#endif
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
deleted file mode 100644
index 231a149..0000000
--- a/arch/blackfin/include/asm/module.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BFIN_MODULE_H
-#define _ASM_BFIN_MODULE_H
-
-#include <asm-generic/module.h>
-
-struct mod_arch_specific {
- Elf_Shdr *text_l1;
- Elf_Shdr *data_a_l1;
- Elf_Shdr *bss_a_l1;
- Elf_Shdr *data_b_l1;
- Elf_Shdr *bss_b_l1;
- Elf_Shdr *text_l2;
- Elf_Shdr *data_l2;
- Elf_Shdr *bss_l2;
-};
-#endif /* _ASM_BFIN_MODULE_H */
diff --git a/arch/blackfin/include/asm/nand.h b/arch/blackfin/include/asm/nand.h
deleted file mode 100644
index 256c50d..0000000
--- a/arch/blackfin/include/asm/nand.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * BF5XX - NAND flash controller platform_device info
- *
- * Copyright 2007-2008 Analog Devices, Inc.
- *
- * Licensed under the GPL-2
- */
-
-/* struct bf5xx_nand_platform
- *
- * define a interface between platform board specific code and
- * bf54x NFC driver.
- *
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
- * partitions = mtd partition list
- */
-
-#define NFC_PG_SIZE_OFFSET 9
-
-#define NFC_NWIDTH_8 0
-#define NFC_NWIDTH_16 1
-#define NFC_NWIDTH_OFFSET 8
-
-#define NFC_RDDLY_OFFSET 4
-#define NFC_WRDLY_OFFSET 0
-
-#define NFC_STAT_NBUSY 1
-
-struct bf5xx_nand_platform {
- /* NAND chip information */
- unsigned short data_width;
-
- /* RD/WR strobe delay timing information, all times in SCLK cycles */
- unsigned short rd_dly;
- unsigned short wr_dly;
-
- /* NAND MTD partition information */
- int nr_partitions;
- struct mtd_partition *partitions;
-};
diff --git a/arch/blackfin/include/asm/nmi.h b/arch/blackfin/include/asm/nmi.h
deleted file mode 100644
index 107d237..0000000
--- a/arch/blackfin/include/asm/nmi.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_NMI_H_
-#define _BFIN_NMI_H_
-
-#include <linux/nmi.h>
-
-extern void arch_touch_nmi_watchdog(void);
-
-#endif
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
deleted file mode 100644
index b93474d..0000000
--- a/arch/blackfin/include/asm/page.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PAGE_H
-#define _BLACKFIN_PAGE_H
-
-#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT)
-#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT)
-
-#define VM_DATA_DEFAULT_FLAGS \
- (VM_READ | VM_WRITE | \
- ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/page.h>
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/page_offset.h b/arch/blackfin/include/asm/page_offset.h
deleted file mode 100644
index d06a89b8..0000000
--- a/arch/blackfin/include/asm/page_offset.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This handles the memory map
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifdef CONFIG_BLACKFIN
-#define PAGE_OFFSET_RAW 0x00000000
-#endif
diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h
deleted file mode 100644
index e6458dd..0000000
--- a/arch/blackfin/include/asm/pci.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Changed from asm-m68k version, Lineo Inc. May 2001 */
-
-#ifndef _ASM_BFIN_PCI_H
-#define _ASM_BFIN_PCI_H
-
-#include <linux/scatterlist.h>
-#include <asm-generic/pci.h>
-
-#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM 0x10000000
-
-#endif /* _ASM_BFIN_PCI_H */
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h
deleted file mode 100644
index 68d6f66..0000000
--- a/arch/blackfin/include/asm/pda.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_PDA_H
-#define _ASM_BLACKFIN_PDA_H
-
-#include <mach/anomaly.h>
-
-#ifndef __ASSEMBLY__
-
-struct blackfin_pda { /* Per-processor Data Area */
-#ifdef CONFIG_SMP
- struct blackfin_pda *next;
-#endif
-
- unsigned long syscfg;
-#ifdef CONFIG_SMP
- unsigned long imask; /* Current IMASK value */
-#endif
-
- unsigned long *ipdt; /* Start of switchable I-CPLB table */
- unsigned long *ipdt_swapcount; /* Number of swaps in ipdt */
- unsigned long *dpdt; /* Start of switchable D-CPLB table */
- unsigned long *dpdt_swapcount; /* Number of swaps in dpdt */
-
- /*
- * Single instructions can have multiple faults, which
- * need to be handled by traps.c, in irq5. We store
- * the exception cause to ensure we don't miss a
- * double fault condition
- */
- unsigned long ex_iptr;
- unsigned long ex_optr;
- unsigned long ex_buf[4];
- unsigned long ex_imask; /* Saved imask from exception */
- unsigned long ex_ipend; /* Saved IPEND from exception */
- unsigned long *ex_stack; /* Exception stack space */
-
-#ifdef ANOMALY_05000261
- unsigned long last_cplb_fault_retx;
-#endif
- unsigned long dcplb_fault_addr;
- unsigned long icplb_fault_addr;
- unsigned long retx;
- unsigned long seqstat;
- unsigned int __nmi_count; /* number of times NMI asserted on this CPU */
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- unsigned long dcplb_doublefault_addr;
- unsigned long icplb_doublefault_addr;
- unsigned long retx_doublefault;
- unsigned long seqstat_doublefault;
-#endif
-};
-
-struct blackfin_initial_pda {
- void *retx;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- void *dcplb_doublefault_addr;
- void *icplb_doublefault_addr;
- void *retx_doublefault;
- unsigned seqstat_doublefault;
-#endif
-};
-
-extern struct blackfin_pda cpu_pda[];
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_BLACKFIN_PDA_H */
diff --git a/arch/blackfin/include/asm/perf_event.h b/arch/blackfin/include/asm/perf_event.h
deleted file mode 100644
index 3d2b171..0000000
--- a/arch/blackfin/include/asm/perf_event.h
+++ /dev/null
@@ -1 +0,0 @@
-#define MAX_HWEVENTS 2
diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h
deleted file mode 100644
index c1ee3d6..0000000
--- a/arch/blackfin/include/asm/pgtable.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PGTABLE_H
-#define _BLACKFIN_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-#include <asm/page.h>
-#include <asm/def_LPBlackfin.h>
-
-typedef pte_t *pte_addr_t;
-/*
-* Trivial page table functions.
-*/
-#define pgd_present(pgd) (1)
-#define pgd_none(pgd) (0)
-#define pgd_bad(pgd) (0)
-#define pgd_clear(pgdp)
-#define kern_addr_valid(addr) (1)
-
-#define pmd_offset(a, b) ((void *)0)
-#define pmd_none(x) (!pmd_val(x))
-#define pmd_present(x) (pmd_val(x))
-#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
-
-#define kern_addr_valid(addr) (1)
-
-#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
-#define pgprot_noncached(prot) (prot)
-
-extern void paging_init(void);
-
-#define __swp_type(x) (0)
-#define __swp_offset(x) (0)
-#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-
-/*
- * Page assess control based on Blackfin CPLB management
- */
-#define _PAGE_RD (CPLB_USER_RD)
-#define _PAGE_WR (CPLB_USER_WR)
-#define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR)
-#define _PAGE_ACCESSED CPLB_ALL_ACCESS
-#define _PAGE_DIRTY (CPLB_DIRTY)
-
-#define PTE_BIT_FUNC(fn, op) \
- static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
-
-PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
-PTE_BIT_FUNC(mkread, |= _PAGE_RD);
-PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
-PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
-PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
-PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
-PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
-PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
-PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
-PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
-extern char empty_zero_page[];
-
-#define swapper_pg_dir ((pgd_t *) 0)
-/*
- * No page table caches to initialise.
- */
-#define pgtable_cache_init() do { } while (0)
-
-/*
- * All 32bit addresses are effectively valid for vmalloc...
- * Sort of meaningless for non-VM targets.
- */
-#define VMALLOC_START 0
-#define VMALLOC_END 0xffffffff
-
-/* provide a special get_unmapped_area for framebuffer mmaps of nommu */
-extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
- unsigned long, unsigned long,
- unsigned long);
-#define HAVE_ARCH_FB_UNMAPPED_AREA
-
-#define pgprot_writecombine pgprot_noncached
-
-#include <asm-generic/pgtable.h>
-
-#endif /* _BLACKFIN_PGTABLE_H */
diff --git a/arch/blackfin/include/asm/pm.h b/arch/blackfin/include/asm/pm.h
deleted file mode 100644
index f72239b..0000000
--- a/arch/blackfin/include/asm/pm.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __PM_H__
-#define __PM_H__
-
-#include <linux/suspend.h>
-
-struct bfin_cpu_pm_fns {
- void (*save)(unsigned long *);
- void (*restore)(unsigned long *);
- int (*valid)(suspend_state_t state);
- void (*enter)(suspend_state_t state);
- int (*prepare)(void);
- void (*finish)(void);
-};
-
-extern struct bfin_cpu_pm_fns *bfin_cpu_pm;
-
-# ifdef CONFIG_BFIN_COREB
-void bfin_coreb_start(void);
-void bfin_coreb_stop(void);
-void bfin_coreb_reset(void);
-# endif
-
-#endif
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
deleted file mode 100644
index c8f0939..0000000
--- a/arch/blackfin/include/asm/portmux.h
+++ /dev/null
@@ -1,1204 +0,0 @@
-/*
- * Common header file for Blackfin family of processors
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _PORTMUX_H_
-#define _PORTMUX_H_
-
-#define P_IDENT(x) ((x) & 0x1FF)
-#define P_FUNCT(x) (((x) & 0x3) << 9)
-#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3)
-#define P_DEFINED 0x8000
-#define P_UNDEF 0x4000
-#define P_MAYSHARE 0x2000
-#define P_DONTCARE 0x1000
-
-#ifdef CONFIG_PINCTRL
-int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
-#define gpio_pint_regs bfin_pint_regs
-#define adi_internal_set_wake bfin_internal_set_wake
-
-#define peripheral_request(per, label) (0)
-#define peripheral_free(per)
-#define peripheral_request_list(per, label) (0)
-#define peripheral_free_list(per)
-#else
-int peripheral_request(unsigned short per, const char *label);
-void peripheral_free(unsigned short per);
-int peripheral_request_list(const unsigned short per[], const char *label);
-void peripheral_free_list(const unsigned short per[]);
-#endif
-
-#include <linux/err.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <mach/portmux.h>
-#include <mach/gpio.h>
-
-#ifndef P_SPORT2_TFS
-#define P_SPORT2_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTSEC
-#define P_SPORT2_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTPRI
-#define P_SPORT2_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_TSCLK
-#define P_SPORT2_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RFS
-#define P_SPORT2_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRSEC
-#define P_SPORT2_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRPRI
-#define P_SPORT2_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RSCLK
-#define P_SPORT2_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TFS
-#define P_SPORT3_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTSEC
-#define P_SPORT3_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTPRI
-#define P_SPORT3_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TSCLK
-#define P_SPORT3_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RFS
-#define P_SPORT3_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRSEC
-#define P_SPORT3_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRPRI
-#define P_SPORT3_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RSCLK
-#define P_SPORT3_RSCLK P_UNDEF
-#endif
-
-#ifndef P_TMR4
-#define P_TMR4 P_UNDEF
-#endif
-
-#ifndef P_TMR5
-#define P_TMR5 P_UNDEF
-#endif
-
-#ifndef P_TMR6
-#define P_TMR6 P_UNDEF
-#endif
-
-#ifndef P_TMR7
-#define P_TMR7 P_UNDEF
-#endif
-
-#ifndef P_TWI1_SCL
-#define P_TWI1_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI1_SDA
-#define P_TWI1_SDA P_UNDEF
-#endif
-
-#ifndef P_UART3_RTS
-#define P_UART3_RTS P_UNDEF
-#endif
-
-#ifndef P_UART3_CTS
-#define P_UART3_CTS P_UNDEF
-#endif
-
-#ifndef P_UART2_TX
-#define P_UART2_TX P_UNDEF
-#endif
-
-#ifndef P_UART2_RX
-#define P_UART2_RX P_UNDEF
-#endif
-
-#ifndef P_UART3_TX
-#define P_UART3_TX P_UNDEF
-#endif
-
-#ifndef P_UART3_RX
-#define P_UART3_RX P_UNDEF
-#endif
-
-#ifndef P_SPI2_SS
-#define P_SPI2_SS P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL1
-#define P_SPI2_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL2
-#define P_SPI2_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL3
-#define P_SPI2_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL4
-#define P_SPI2_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL5
-#define P_SPI2_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL6
-#define P_SPI2_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL7
-#define P_SPI2_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SCK
-#define P_SPI2_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI2_MOSI
-#define P_SPI2_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI2_MISO
-#define P_SPI2_MISO P_UNDEF
-#endif
-
-#ifndef P_TMR0
-#define P_TMR0 P_UNDEF
-#endif
-
-#ifndef P_TMR1
-#define P_TMR1 P_UNDEF
-#endif
-
-#ifndef P_TMR2
-#define P_TMR2 P_UNDEF
-#endif
-
-#ifndef P_TMR3
-#define P_TMR3 P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TFS
-#define P_SPORT0_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTSEC
-#define P_SPORT0_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTPRI
-#define P_SPORT0_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TSCLK
-#define P_SPORT0_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RFS
-#define P_SPORT0_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRSEC
-#define P_SPORT0_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRPRI
-#define P_SPORT0_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RSCLK
-#define P_SPORT0_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SD_D0
-#define P_SD_D0 P_UNDEF
-#endif
-
-#ifndef P_SD_D1
-#define P_SD_D1 P_UNDEF
-#endif
-
-#ifndef P_SD_D2
-#define P_SD_D2 P_UNDEF
-#endif
-
-#ifndef P_SD_D3
-#define P_SD_D3 P_UNDEF
-#endif
-
-#ifndef P_SD_CLK
-#define P_SD_CLK P_UNDEF
-#endif
-
-#ifndef P_SD_CMD
-#define P_SD_CMD P_UNDEF
-#endif
-
-#ifndef P_MMCLK
-#define P_MMCLK P_UNDEF
-#endif
-
-#ifndef P_MBCLK
-#define P_MBCLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_D0
-#define P_PPI1_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D1
-#define P_PPI1_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D2
-#define P_PPI1_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D3
-#define P_PPI1_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D4
-#define P_PPI1_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D5
-#define P_PPI1_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D6
-#define P_PPI1_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D7
-#define P_PPI1_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D8
-#define P_PPI1_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D9
-#define P_PPI1_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D10
-#define P_PPI1_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D11
-#define P_PPI1_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D12
-#define P_PPI1_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D13
-#define P_PPI1_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D14
-#define P_PPI1_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D15
-#define P_PPI1_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D8
-#define P_HOST_D8 P_UNDEF
-#endif
-
-#ifndef P_HOST_D9
-#define P_HOST_D9 P_UNDEF
-#endif
-
-#ifndef P_HOST_D10
-#define P_HOST_D10 P_UNDEF
-#endif
-
-#ifndef P_HOST_D11
-#define P_HOST_D11 P_UNDEF
-#endif
-
-#ifndef P_HOST_D12
-#define P_HOST_D12 P_UNDEF
-#endif
-
-#ifndef P_HOST_D13
-#define P_HOST_D13 P_UNDEF
-#endif
-
-#ifndef P_HOST_D14
-#define P_HOST_D14 P_UNDEF
-#endif
-
-#ifndef P_HOST_D15
-#define P_HOST_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D0
-#define P_HOST_D0 P_UNDEF
-#endif
-
-#ifndef P_HOST_D1
-#define P_HOST_D1 P_UNDEF
-#endif
-
-#ifndef P_HOST_D2
-#define P_HOST_D2 P_UNDEF
-#endif
-
-#ifndef P_HOST_D3
-#define P_HOST_D3 P_UNDEF
-#endif
-
-#ifndef P_HOST_D4
-#define P_HOST_D4 P_UNDEF
-#endif
-
-#ifndef P_HOST_D5
-#define P_HOST_D5 P_UNDEF
-#endif
-
-#ifndef P_HOST_D6
-#define P_HOST_D6 P_UNDEF
-#endif
-
-#ifndef P_HOST_D7
-#define P_HOST_D7 P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TFS
-#define P_SPORT1_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTSEC
-#define P_SPORT1_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTPRI
-#define P_SPORT1_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TSCLK
-#define P_SPORT1_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RFS
-#define P_SPORT1_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRSEC
-#define P_SPORT1_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRPRI
-#define P_SPORT1_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RSCLK
-#define P_SPORT1_RSCLK P_UNDEF
-#endif
-
-#ifndef P_PPI2_D0
-#define P_PPI2_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D1
-#define P_PPI2_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D2
-#define P_PPI2_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D3
-#define P_PPI2_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D4
-#define P_PPI2_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D5
-#define P_PPI2_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D6
-#define P_PPI2_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D7
-#define P_PPI2_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D18
-#define P_PPI0_D18 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D19
-#define P_PPI0_D19 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D20
-#define P_PPI0_D20 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D21
-#define P_PPI0_D21 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D22
-#define P_PPI0_D22 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D23
-#define P_PPI0_D23 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW0
-#define P_KEY_ROW0 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW1
-#define P_KEY_ROW1 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW2
-#define P_KEY_ROW2 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW3
-#define P_KEY_ROW3 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL0
-#define P_KEY_COL0 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL1
-#define P_KEY_COL1 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL2
-#define P_KEY_COL2 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL3
-#define P_KEY_COL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SCK
-#define P_SPI0_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI0_MISO
-#define P_SPI0_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI0_MOSI
-#define P_SPI0_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI0_SS
-#define P_SPI0_SS P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL1
-#define P_SPI0_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL2
-#define P_SPI0_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL3
-#define P_SPI0_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL4
-#define P_SPI0_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL5
-#define P_SPI0_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL6
-#define P_SPI0_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL7
-#define P_SPI0_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_UART0_TX
-#define P_UART0_TX P_UNDEF
-#endif
-
-#ifndef P_UART0_RX
-#define P_UART0_RX P_UNDEF
-#endif
-
-#ifndef P_UART1_RTS
-#define P_UART1_RTS P_UNDEF
-#endif
-
-#ifndef P_UART1_CTS
-#define P_UART1_CTS P_UNDEF
-#endif
-
-#ifndef P_PPI1_CLK
-#define P_PPI1_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS1
-#define P_PPI1_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS2
-#define P_PPI1_FS2 P_UNDEF
-#endif
-
-#ifndef P_TWI0_SCL
-#define P_TWI0_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI0_SDA
-#define P_TWI0_SDA P_UNDEF
-#endif
-
-#ifndef P_KEY_COL7
-#define P_KEY_COL7 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW6
-#define P_KEY_ROW6 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL6
-#define P_KEY_COL6 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW5
-#define P_KEY_ROW5 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL5
-#define P_KEY_COL5 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW4
-#define P_KEY_ROW4 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL4
-#define P_KEY_COL4 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW7
-#define P_KEY_ROW7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D0
-#define P_PPI0_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D1
-#define P_PPI0_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D2
-#define P_PPI0_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D3
-#define P_PPI0_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D4
-#define P_PPI0_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D5
-#define P_PPI0_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D6
-#define P_PPI0_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D7
-#define P_PPI0_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D8
-#define P_PPI0_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D9
-#define P_PPI0_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D10
-#define P_PPI0_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D11
-#define P_PPI0_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D12
-#define P_PPI0_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D13
-#define P_PPI0_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D14
-#define P_PPI0_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D15
-#define P_PPI0_D15 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D0A
-#define P_ATAPI_D0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D1A
-#define P_ATAPI_D1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D2A
-#define P_ATAPI_D2A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D3A
-#define P_ATAPI_D3A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D4A
-#define P_ATAPI_D4A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D5A
-#define P_ATAPI_D5A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D6A
-#define P_ATAPI_D6A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D7A
-#define P_ATAPI_D7A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D8A
-#define P_ATAPI_D8A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D9A
-#define P_ATAPI_D9A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D10A
-#define P_ATAPI_D10A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D11A
-#define P_ATAPI_D11A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D12A
-#define P_ATAPI_D12A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D13A
-#define P_ATAPI_D13A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D14A
-#define P_ATAPI_D14A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D15A
-#define P_ATAPI_D15A P_UNDEF
-#endif
-
-#ifndef P_PPI0_CLK
-#define P_PPI0_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS1
-#define P_PPI0_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS2
-#define P_PPI0_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D16
-#define P_PPI0_D16 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D17
-#define P_PPI0_D17 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL1
-#define P_SPI1_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL2
-#define P_SPI1_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL3
-#define P_SPI1_SSEL3 P_UNDEF
-#endif
-
-
-#ifndef P_SPI1_SSEL4
-#define P_SPI1_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL5
-#define P_SPI1_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL6
-#define P_SPI1_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL7
-#define P_SPI1_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SCK
-#define P_SPI1_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI1_MISO
-#define P_SPI1_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI1_MOSI
-#define P_SPI1_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI1_SS
-#define P_SPI1_SS P_UNDEF
-#endif
-
-#ifndef P_CAN0_TX
-#define P_CAN0_TX P_UNDEF
-#endif
-
-#ifndef P_CAN0_RX
-#define P_CAN0_RX P_UNDEF
-#endif
-
-#ifndef P_CAN1_TX
-#define P_CAN1_TX P_UNDEF
-#endif
-
-#ifndef P_CAN1_RX
-#define P_CAN1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A0A
-#define P_ATAPI_A0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A1A
-#define P_ATAPI_A1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A2A
-#define P_ATAPI_A2A P_UNDEF
-#endif
-
-#ifndef P_HOST_CE
-#define P_HOST_CE P_UNDEF
-#endif
-
-#ifndef P_HOST_RD
-#define P_HOST_RD P_UNDEF
-#endif
-
-#ifndef P_HOST_WR
-#define P_HOST_WR P_UNDEF
-#endif
-
-#ifndef P_MTXONB
-#define P_MTXONB P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS2
-#define P_PPI2_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS1
-#define P_PPI2_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_CLK
-#define P_PPI2_CLK P_UNDEF
-#endif
-
-#ifndef P_CNT_CZM
-#define P_CNT_CZM P_UNDEF
-#endif
-
-#ifndef P_UART1_TX
-#define P_UART1_TX P_UNDEF
-#endif
-
-#ifndef P_UART1_RX
-#define P_UART1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_RESET
-#define P_ATAPI_RESET P_UNDEF
-#endif
-
-#ifndef P_HOST_ADDR
-#define P_HOST_ADDR P_UNDEF
-#endif
-
-#ifndef P_HOST_ACK
-#define P_HOST_ACK P_UNDEF
-#endif
-
-#ifndef P_MTX
-#define P_MTX P_UNDEF
-#endif
-
-#ifndef P_MRX
-#define P_MRX P_UNDEF
-#endif
-
-#ifndef P_MRXONB
-#define P_MRXONB P_UNDEF
-#endif
-
-#ifndef P_A4
-#define P_A4 P_UNDEF
-#endif
-
-#ifndef P_A5
-#define P_A5 P_UNDEF
-#endif
-
-#ifndef P_A6
-#define P_A6 P_UNDEF
-#endif
-
-#ifndef P_A7
-#define P_A7 P_UNDEF
-#endif
-
-#ifndef P_A8
-#define P_A8 P_UNDEF
-#endif
-
-#ifndef P_A9
-#define P_A9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS3
-#define P_PPI1_FS3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS3
-#define P_PPI2_FS3 P_UNDEF
-#endif
-
-#ifndef P_TMR8
-#define P_TMR8 P_UNDEF
-#endif
-
-#ifndef P_TMR9
-#define P_TMR9 P_UNDEF
-#endif
-
-#ifndef P_TMR10
-#define P_TMR10 P_UNDEF
-#endif
-#ifndef P_TMR11
-#define P_TMR11 P_UNDEF
-#endif
-
-#ifndef P_DMAR0
-#define P_DMAR0 P_UNDEF
-#endif
-
-#ifndef P_DMAR1
-#define P_DMAR1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS3
-#define P_PPI0_FS3 P_UNDEF
-#endif
-
-#ifndef P_CNT_CDG
-#define P_CNT_CDG P_UNDEF
-#endif
-
-#ifndef P_CNT_CUD
-#define P_CNT_CUD P_UNDEF
-#endif
-
-#ifndef P_A10
-#define P_A10 P_UNDEF
-#endif
-
-#ifndef P_A11
-#define P_A11 P_UNDEF
-#endif
-
-#ifndef P_A12
-#define P_A12 P_UNDEF
-#endif
-
-#ifndef P_A13
-#define P_A13 P_UNDEF
-#endif
-
-#ifndef P_A14
-#define P_A14 P_UNDEF
-#endif
-
-#ifndef P_A15
-#define P_A15 P_UNDEF
-#endif
-
-#ifndef P_A16
-#define P_A16 P_UNDEF
-#endif
-
-#ifndef P_A17
-#define P_A17 P_UNDEF
-#endif
-
-#ifndef P_A18
-#define P_A18 P_UNDEF
-#endif
-
-#ifndef P_A19
-#define P_A19 P_UNDEF
-#endif
-
-#ifndef P_A20
-#define P_A20 P_UNDEF
-#endif
-
-#ifndef P_A21
-#define P_A21 P_UNDEF
-#endif
-
-#ifndef P_A22
-#define P_A22 P_UNDEF
-#endif
-
-#ifndef P_A23
-#define P_A23 P_UNDEF
-#endif
-
-#ifndef P_A24
-#define P_A24 P_UNDEF
-#endif
-
-#ifndef P_A25
-#define P_A25 P_UNDEF
-#endif
-
-#ifndef P_NOR_CLK
-#define P_NOR_CLK P_UNDEF
-#endif
-
-#ifndef P_TMRCLK
-#define P_TMRCLK P_UNDEF
-#endif
-
-#ifndef P_AMC_ARDY_NOR_WAIT
-#define P_AMC_ARDY_NOR_WAIT P_UNDEF
-#endif
-
-#ifndef P_NAND_CE
-#define P_NAND_CE P_UNDEF
-#endif
-
-#ifndef P_NAND_RB
-#define P_NAND_RB P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOR
-#define P_ATAPI_DIOR P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOW
-#define P_ATAPI_DIOW P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS0
-#define P_ATAPI_CS0 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS1
-#define P_ATAPI_CS1 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMACK
-#define P_ATAPI_DMACK P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMARQ
-#define P_ATAPI_DMARQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_INTRQ
-#define P_ATAPI_INTRQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_IORDY
-#define P_ATAPI_IORDY P_UNDEF
-#endif
-
-#ifndef P_AMC_BR
-#define P_AMC_BR P_UNDEF
-#endif
-
-#ifndef P_AMC_BG
-#define P_AMC_BG P_UNDEF
-#endif
-
-#ifndef P_AMC_BGH
-#define P_AMC_BGH P_UNDEF
-#endif
-
-/* EMAC */
-
-#ifndef P_MII0_ETxD0
-#define P_MII0_ETxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD1
-#define P_MII0_ETxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD2
-#define P_MII0_ETxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD3
-#define P_MII0_ETxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxEN
-#define P_MII0_ETxEN P_UNDEF
-#endif
-
-#ifndef P_MII0_TxCLK
-#define P_MII0_TxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_PHYINT
-#define P_MII0_PHYINT P_UNDEF
-#endif
-
-#ifndef P_MII0_COL
-#define P_MII0_COL P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD0
-#define P_MII0_ERxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD1
-#define P_MII0_ERxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD2
-#define P_MII0_ERxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD3
-#define P_MII0_ERxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxDV
-#define P_MII0_ERxDV P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxCLK
-#define P_MII0_ERxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxER
-#define P_MII0_ERxER P_UNDEF
-#endif
-
-#ifndef P_MII0_CRS
-#define P_MII0_CRS P_UNDEF
-#endif
-
-#ifndef P_RMII0_REF_CLK
-#define P_RMII0_REF_CLK P_UNDEF
-#endif
-
-#ifndef P_RMII0_MDINT
-#define P_RMII0_MDINT P_UNDEF
-#endif
-
-#ifndef P_RMII0_CRS_DV
-#define P_RMII0_CRS_DV P_UNDEF
-#endif
-
-#ifndef P_MDC
-#define P_MDC P_UNDEF
-#endif
-
-#ifndef P_MDIO
-#define P_MDIO P_UNDEF
-#endif
-
-#endif /* _PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
deleted file mode 100644
index dbdbb8a..0000000
--- a/arch/blackfin/include/asm/processor.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_PROCESSOR_H
-#define __ASM_BFIN_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <asm/ptrace.h>
-#include <mach/blackfin.h>
-
-static inline unsigned long rdusp(void)
-{
- unsigned long usp;
-
- __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
- return usp;
-}
-
-static inline void wrusp(unsigned long usp)
-{
- __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
-}
-
-static inline unsigned long __get_SP(void)
-{
- unsigned long sp;
-
- __asm__ __volatile__("%0 = sp;\n\t" : "=da"(sp));
- return sp;
-}
-
-/*
- * User space process size: 1st byte beyond user address space.
- * Fairly meaningless on nommu. Parts of user programs can be scattered
- * in a lot of places, so just disable this by setting it to 0xFFFFFFFF.
- */
-#define TASK_SIZE 0xFFFFFFFF
-
-#ifdef __KERNEL__
-#define STACK_TOP TASK_SIZE
-#endif
-
-#define TASK_UNMAPPED_BASE 0
-
-struct thread_struct {
- unsigned long ksp; /* kernel stack pointer */
- unsigned long usp; /* user stack pointer */
- unsigned short seqstat; /* saved status register */
- unsigned long esp0; /* points to SR of stack frame pt_regs */
- unsigned long pc; /* instruction pointer */
- void * debuggerinfo;
-};
-
-#define INIT_THREAD { \
- sizeof(init_stack) + (unsigned long) init_stack, 0, \
- PS_S, 0, 0 \
-}
-
-extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
- unsigned long new_sp);
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) \
- ({ \
- unsigned long eip = 0; \
- if ((tsk)->thread.esp0 > PAGE_SIZE && \
- MAP_NR((tsk)->thread.esp0) < max_mapnr) \
- eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
- eip; })
-#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-#define cpu_relax() smp_mb()
-
-/* Get the Silicon Revision of the chip */
-static inline uint32_t __pure bfin_revid(void)
-{
- /* Always use CHIPID, to work around ANOMALY_05000234 */
- uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28;
-
-#ifdef _BOOTROM_GET_DXE_ADDRESS_TWI
- /*
- * ANOMALY_05000364
- * Incorrect Revision Number in DSPID Register
- */
- if (ANOMALY_05000364 &&
- bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI) == 0x2796)
- revid = 1;
-#endif
-
- return revid;
-}
-
-static inline uint16_t __pure bfin_cpuid(void)
-{
- return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12;
-}
-
-static inline uint32_t __pure bfin_dspid(void)
-{
- return bfin_read_DSPID();
-}
-
-#define blackfin_core_id() (bfin_dspid() & 0xff)
-
-static inline uint32_t __pure bfin_compiled_revid(void)
-{
-#if defined(CONFIG_BF_REV_0_0)
- return 0;
-#elif defined(CONFIG_BF_REV_0_1)
- return 1;
-#elif defined(CONFIG_BF_REV_0_2)
- return 2;
-#elif defined(CONFIG_BF_REV_0_3)
- return 3;
-#elif defined(CONFIG_BF_REV_0_4)
- return 4;
-#elif defined(CONFIG_BF_REV_0_5)
- return 5;
-#elif defined(CONFIG_BF_REV_0_6)
- return 6;
-#elif defined(CONFIG_BF_REV_ANY)
- return 0xffff;
-#else
- return -1;
-#endif
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/pseudo_instructions.h b/arch/blackfin/include/asm/pseudo_instructions.h
deleted file mode 100644
index b00adfa..0000000
--- a/arch/blackfin/include/asm/pseudo_instructions.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * header file for pseudo instructions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PSEUDO_
-#define _BLACKFIN_PSEUDO_
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-
-extern bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode);
-extern bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode);
-
-#endif
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
deleted file mode 100644
index c004915..0000000
--- a/arch/blackfin/include/asm/ptrace.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef _BFIN_PTRACE_H
-#define _BFIN_PTRACE_H
-
-#include <uapi/asm/ptrace.h>
-
-#ifndef __ASSEMBLY__
-
-/* user_mode returns true if only one bit is set in IPEND, other than the
- master interrupt enable. */
-#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
-
-#define arch_has_single_step() (1)
-/* common code demands this function */
-#define ptrace_disable(child) user_disable_single_step(child)
-#define current_user_stack_pointer() rdusp()
-
-extern int is_user_addr_valid(struct task_struct *child,
- unsigned long start, unsigned long len);
-
-/*
- * Get the address of the live pt_regs for the specified task.
- * These are saved onto the top kernel stack when the process
- * is not running.
- *
- * Note: if a user thread is execve'd from kernel space, the
- * kernel stack will not be empty on entry to the kernel, so
- * ptracing these tasks will fail.
- */
-#define task_pt_regs(task) \
- (struct pt_regs *) \
- ((unsigned long)task_stack_page(task) + \
- (THREAD_SIZE - sizeof(struct pt_regs)))
-
-#include <asm-generic/ptrace.h>
-
-#endif /* __ASSEMBLY__ */
-#endif /* _BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/asm/reboot.h b/arch/blackfin/include/asm/reboot.h
deleted file mode 100644
index ae1e363..0000000
--- a/arch/blackfin/include/asm/reboot.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * reboot.h - shutdown/reboot header
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_REBOOT_H__
-#define __ASM_REBOOT_H__
-
-/* optional board specific hooks */
-extern void native_machine_restart(char *cmd);
-extern void native_machine_halt(void);
-extern void native_machine_power_off(void);
-
-/* common reboot workarounds */
-extern void bfin_reset_boot_spi_cs(unsigned short pin);
-
-#endif
diff --git a/arch/blackfin/include/asm/rwlock.h b/arch/blackfin/include/asm/rwlock.h
deleted file mode 100644
index 98ebc07..0000000
--- a/arch/blackfin/include/asm/rwlock.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_BLACKFIN_RWLOCK_H
-#define _ASM_BLACKFIN_RWLOCK_H
-
-#define RW_LOCK_BIAS 0x01000000
-
-#endif
diff --git a/arch/blackfin/include/asm/scb.h b/arch/blackfin/include/asm/scb.h
deleted file mode 100644
index a294cc0..0000000
--- a/arch/blackfin/include/asm/scb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define SCB_SLOT_OFFSET 24
-#define SCB_MI_MAX_SLOT 32
-
-struct scb_mi_prio {
- unsigned long scb_mi_arbr;
- unsigned long scb_mi_arbw;
- unsigned char scb_mi_slots;
- unsigned char scb_mi_prio[SCB_MI_MAX_SLOT];
-};
-
-extern struct scb_mi_prio scb_data[];
-
-extern void init_scb(void);
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
deleted file mode 100644
index fbd4084..0000000
--- a/arch/blackfin/include/asm/sections.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_SECTIONS_H
-#define _BLACKFIN_SECTIONS_H
-
-/* only used when MTD_UCLINUX */
-extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
-
-extern unsigned long _ramstart, _ramend, _rambase;
-extern unsigned long memory_start, memory_end, physical_mem_end;
-
-/*
- * The weak markings on the lengths might seem weird, but this is required
- * in order to make gcc accept the fact that these may actually have a value
- * of 0 (since they aren't actually addresses, but sizes of sections).
- */
-extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[];
-extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[],
- _data_l1_lma[], __weak _data_l1_len[];
-#ifdef CONFIG_ROMKERNEL
-extern char _data_lma[], _data_len[], _sinitdata[], _einitdata[], _init_data_lma[], _init_data_len[];
-#endif
-extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
- _data_b_l1_lma[], __weak _data_b_l1_len[];
-extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[],
- _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[];
-
-#include <asm/mem_map.h>
-
-/* Blackfin systems have discontinuous memory map and no virtualized memory */
-static inline int arch_is_kernel_text(unsigned long addr)
-{
- return
- (L1_CODE_LENGTH &&
- addr >= (unsigned long)_stext_l1 &&
- addr < (unsigned long)_etext_l1)
- ||
- (L2_LENGTH &&
- addr >= (unsigned long)_stext_l2 &&
- addr < (unsigned long)_etext_l2);
-}
-#define arch_is_kernel_text(addr) arch_is_kernel_text(addr)
-
-static inline int arch_is_kernel_data(unsigned long addr)
-{
- return
- (L1_DATA_A_LENGTH &&
- addr >= (unsigned long)_sdata_l1 &&
- addr < (unsigned long)_ebss_l1)
- ||
- (L1_DATA_B_LENGTH &&
- addr >= (unsigned long)_sdata_b_l1 &&
- addr < (unsigned long)_ebss_b_l1)
- ||
- (L2_LENGTH &&
- addr >= (unsigned long)_sdata_l2 &&
- addr < (unsigned long)_ebss_l2);
-}
-#define arch_is_kernel_data(addr) arch_is_kernel_data(addr)
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/segment.h b/arch/blackfin/include/asm/segment.h
deleted file mode 100644
index f8e1984..0000000
--- a/arch/blackfin/include/asm/segment.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_SEGMENT_H
-#define _BFIN_SEGMENT_H
-
-#define KERNEL_DS (0x5)
-#define USER_DS (0x1)
-
-#endif /* _BFIN_SEGMENT_H */
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h
deleted file mode 100644
index 9631598..0000000
--- a/arch/blackfin/include/asm/smp.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_SMP_H
-#define __ASM_BLACKFIN_SMP_H
-
-#include <linux/kernel.h>
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-#include <linux/cache.h>
-#include <asm/blackfin.h>
-#include <mach/smp.h>
-
-#define raw_smp_processor_id() blackfin_core_id()
-
-extern void bfin_relocate_coreb_l1_mem(void);
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
-
-#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
-asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr);
-extern unsigned long blackfin_iflush_l1_entry[NR_CPUS];
-#endif
-
-struct corelock_slot {
- int lock;
-};
-extern struct corelock_slot corelock;
-
-#ifdef __ARCH_SYNC_CORE_ICACHE
-extern unsigned long icache_invld_count[NR_CPUS];
-#endif
-#ifdef __ARCH_SYNC_CORE_DCACHE
-extern unsigned long dcache_invld_count[NR_CPUS];
-#endif
-
-void smp_icache_flush_range_others(unsigned long start,
- unsigned long end);
-#ifdef CONFIG_HOTPLUG_CPU
-void coreb_die(void);
-void cpu_die(void);
-void platform_cpu_die(void);
-int __cpu_disable(void);
-int __cpu_die(unsigned int cpu);
-#endif
-
-void smp_timer_broadcast(const struct cpumask *mask);
-
-
-#endif /* !__ASM_BLACKFIN_SMP_H */
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
deleted file mode 100644
index 839d144..0000000
--- a/arch/blackfin/include/asm/spinlock.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_SPINLOCK_H
-#define __BFIN_SPINLOCK_H
-
-#ifndef CONFIG_SMP
-# include <asm-generic/spinlock.h>
-#else
-
-#include <linux/atomic.h>
-#include <asm/processor.h>
-#include <asm/barrier.h>
-
-asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
-asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
-asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_read_lock_asm(volatile int *ptr);
-asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_write_lock_asm(volatile int *ptr);
-asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
-
-static inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
- return __raw_spin_is_locked_asm(&lock->lock);
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- __raw_spin_lock_asm(&lock->lock);
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- return __raw_spin_trylock_asm(&lock->lock);
-}
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- __raw_spin_unlock_asm(&lock->lock);
-}
-
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
- __raw_read_lock_asm(&rw->lock);
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *rw)
-{
- return __raw_read_trylock_asm(&rw->lock);
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
- __raw_read_unlock_asm(&rw->lock);
-}
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
- __raw_write_lock_asm(&rw->lock);
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *rw)
-{
- return __raw_write_trylock_asm(&rw->lock);
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
- __raw_write_unlock_asm(&rw->lock);
-}
-
-#endif
-
-#endif /* !__BFIN_SPINLOCK_H */
diff --git a/arch/blackfin/include/asm/spinlock_types.h b/arch/blackfin/include/asm/spinlock_types.h
deleted file mode 100644
index 1a33608..0000000
--- a/arch/blackfin/include/asm/spinlock_types.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_SPINLOCK_TYPES_H
-#define __ASM_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-#include <asm/rwlock.h>
-
-typedef struct {
- volatile unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- volatile unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
-
-#endif
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
deleted file mode 100644
index 423c099..0000000
--- a/arch/blackfin/include/asm/string.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_STRING_H_
-#define _BLACKFIN_STRING_H_
-
-#include <linux/types.h>
-
-#ifdef __KERNEL__ /* only set these up for kernel code */
-
-#define __HAVE_ARCH_STRCPY
-extern char *strcpy(char *dest, const char *src);
-
-#define __HAVE_ARCH_STRNCPY
-extern char *strncpy(char *dest, const char *src, size_t n);
-
-#define __HAVE_ARCH_STRCMP
-extern int strcmp(const char *cs, const char *ct);
-
-#define __HAVE_ARCH_STRNCMP
-extern int strncmp(const char *cs, const char *ct, size_t count);
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, size_t count);
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *d, const void *s, size_t count);
-#define __HAVE_ARCH_MEMCMP
-extern int memcmp(const void *, const void *, __kernel_size_t);
-#define __HAVE_ARCH_MEMCHR
-extern void *memchr(const void *s, int c, size_t n);
-#define __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *dest, const void *src, size_t count);
-
-#endif /*__KERNEL__*/
-#endif /* _BLACKFIN_STRING_H_ */
diff --git a/arch/blackfin/include/asm/switch_to.h b/arch/blackfin/include/asm/switch_to.h
deleted file mode 100644
index aaf671b..0000000
--- a/arch/blackfin/include/asm/switch_to.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * Tony Kou (tonyko at lineo.ca)
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BLACKFIN_SWITCH_TO_H
-#define _BLACKFIN_SWITCH_TO_H
-
-#define prepare_to_switch() do { } while(0)
-
-/*
- * switch_to(n) should switch tasks to task ptr, first checking that
- * ptr isn't the current task, in which case it does nothing.
- */
-
-#include <asm/l1layout.h>
-#include <asm/mem_map.h>
-
-asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
-
-#ifndef CONFIG_SMP
-#define switch_to(prev,next,last) \
-do { \
- memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
- sizeof *L1_SCRATCH_TASK_INFO); \
- memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \
- sizeof *L1_SCRATCH_TASK_INFO); \
- (last) = resume (prev, next); \
-} while (0)
-#else
-#define switch_to(prev, next, last) \
-do { \
- (last) = resume(prev, next); \
-} while (0)
-#endif
-
-#endif /* _BLACKFIN_SWITCH_TO_H */
diff --git a/arch/blackfin/include/asm/syscall.h b/arch/blackfin/include/asm/syscall.h
deleted file mode 100644
index 4921a48..0000000
--- a/arch/blackfin/include/asm/syscall.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Magic syscall break down functions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_SYSCALL_H__
-#define __ASM_BLACKFIN_SYSCALL_H__
-
-/*
- * Blackfin syscalls are simple:
- * enter:
- * p0: syscall number
- * r{0,1,2,3,4,5}: syscall args 0,1,2,3,4,5
- * exit:
- * r0: return/error value
- */
-
-#include <linux/err.h>
-#include <linux/sched.h>
-#include <asm/ptrace.h>
-
-static inline long
-syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
-{
- return regs->p0;
-}
-
-static inline void
-syscall_rollback(struct task_struct *task, struct pt_regs *regs)
-{
- regs->p0 = regs->orig_p0;
-}
-
-static inline long
-syscall_get_error(struct task_struct *task, struct pt_regs *regs)
-{
- return IS_ERR_VALUE(regs->r0) ? regs->r0 : 0;
-}
-
-static inline long
-syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
-{
- return regs->r0;
-}
-
-static inline void
-syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
- int error, long val)
-{
- regs->r0 = error ? -error : val;
-}
-
-/**
- * syscall_get_arguments()
- * @task: unused
- * @regs: the register layout to extract syscall arguments from
- * @i: first syscall argument to extract
- * @n: number of syscall arguments to extract
- * @args: array to return the syscall arguments in
- *
- * args[0] gets i'th argument, args[n - 1] gets the i+n-1'th argument
- */
-static inline void
-syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
- unsigned int i, unsigned int n, unsigned long *args)
-{
- /*
- * Assume the ptrace layout doesn't change -- r5 is first in memory,
- * then r4, ..., then r0. So we simply reverse the ptrace register
- * array in memory to store into the args array.
- */
- long *aregs = ®s->r0 - i;
-
- BUG_ON(i > 5 || i + n > 6);
-
- while (n--)
- *args++ = *aregs--;
-}
-
-/* See syscall_get_arguments() comments */
-static inline void
-syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
- unsigned int i, unsigned int n, const unsigned long *args)
-{
- long *aregs = ®s->r0 - i;
-
- BUG_ON(i > 5 || i + n > 6);
-
- while (n--)
- *aregs-- = *args++;
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
deleted file mode 100644
index a5aeab4..0000000
--- a/arch/blackfin/include/asm/thread_info.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#include <asm/page.h>
-#include <asm/entry.h>
-#include <asm/l1layout.h>
-#include <linux/compiler.h>
-
-#ifdef __KERNEL__
-
-/* Thread Align Mask to reach to the top of the stack
- * for any process
- */
-#define ALIGN_PAGE_MASK 0xffffe000
-
-/*
- * Size of kernel stack for each process. This must be a power of 2...
- */
-#define THREAD_SIZE_ORDER 1
-#define THREAD_SIZE 8192 /* 2 pages */
-#define STACK_WARN (THREAD_SIZE/8)
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned long mm_segment_t;
-
-/*
- * low level task data.
- * If you change this, change the TI_* offsets below to match.
- */
-
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- int cpu; /* cpu we're on */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
- mm_segment_t addr_limit; /* address limit */
-#ifndef CONFIG_SMP
- struct l1_scratch_task_info l1_task_info;
-#endif
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
-}
-
-/* Given a task stack pointer, you can find its corresponding
- * thread_info structure just by masking it to the THREAD_SIZE
- * boundary (currently 8K as you can see above).
- */
-__attribute_const__
-static inline struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
- __asm__("%0 = sp;" : "=da"(ti));
- return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
-}
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_SIGPENDING 1 /* signal pending */
-#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
-#define TIF_MEMDIE 4 /* is terminating due to OOM killer */
-#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
-#define TIF_IRQ_SYNC 7 /* sync pipeline stage */
-#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */
-#define TIF_SINGLESTEP 9
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
-
-#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h
deleted file mode 100644
index 9ca7db8..0000000
--- a/arch/blackfin/include/asm/time.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * asm-blackfin/time.h:
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIME_H
-#define _ASM_BLACKFIN_TIME_H
-
-/*
- * The way that the Blackfin core timer works is:
- * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
- * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
- *
- * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
- * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
- * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
- * to use TSCALE, and program it to zero (which is pass CCLK through).
- * If you feel like using it, try to keep HZ * TIMESCALE to some
- * value that divides easy (like power of 2).
- */
-
-#ifndef CONFIG_CPU_FREQ
-# define TIME_SCALE 1
-#else
-/*
- * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
- * Whenever we change the Core Clock frequency changes we immediately
- * adjust the Core Timer Presale Register. This way we don't lose time.
- */
-#define TIME_SCALE 4
-
-# ifdef CONFIG_CYCLES_CLOCKSOURCE
-extern unsigned long long __bfin_cycles_off;
-extern unsigned int __bfin_cycles_mod;
-# endif
-#endif
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
-extern void bfin_coretmr_init(void);
-extern void bfin_coretmr_clockevent_init(void);
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/timex.h b/arch/blackfin/include/asm/timex.h
deleted file mode 100644
index 248aeb06..0000000
--- a/arch/blackfin/include/asm/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * asm-blackfin/timex.h: cpu cycles!
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIMEX_H
-#define _ASM_BLACKFIN_TIMEX_H
-
-#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
-
-typedef unsigned long long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
- unsigned long tmp, tmp2;
- __asm__ __volatile__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
- return tmp | ((cycles_t)tmp2 << 32);
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/tlb.h b/arch/blackfin/include/asm/tlb.h
deleted file mode 100644
index a74ae08..0000000
--- a/arch/blackfin/include/asm/tlb.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_TLB_H
-#define _BLACKFIN_TLB_H
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it
- * fills up.
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* _BLACKFIN_TLB_H */
diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h
deleted file mode 100644
index 7c36868..0000000
--- a/arch/blackfin/include/asm/tlbflush.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-generic/tlbflush.h>
-#define flush_tlb_kernel_range(s, e) do { } while (0)
diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h
deleted file mode 100644
index 33589a2..0000000
--- a/arch/blackfin/include/asm/trace.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * header file for hardware trace functions
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_TRACE_
-#define _BLACKFIN_TRACE_
-
-/* Normally, we use ON, but you can't turn on software expansion until
- * interrupts subsystem is ready
- */
-
-#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03)
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
-#define BFIN_TRACE_ON (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2))
-#else
-#define BFIN_TRACE_ON (BFIN_TRACE_INIT)
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned long trace_buff_offset;
-extern unsigned long software_trace_buff[];
-#if defined(CONFIG_DEBUG_VERBOSE)
-extern void decode_address(char *buf, unsigned long address);
-extern bool get_instruction(unsigned int *val, unsigned short *address);
-#else
-static inline void decode_address(char *buf, unsigned long address) { }
-static inline bool get_instruction(unsigned int *val, unsigned short *address) { return false; }
-#endif
-
-/* Trace Macros for C files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_init() bfin_write_TBUFCTL(BFIN_TRACE_INIT)
-
-#define trace_buffer_save(x) \
- do { \
- (x) = bfin_read_TBUFCTL(); \
- bfin_write_TBUFCTL((x) & ~TBUFEN); \
- } while (0)
-
-#define trace_buffer_restore(x) \
- do { \
- bfin_write_TBUFCTL((x)); \
- } while (0)
-#else /* DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_save(x)
-#define trace_buffer_restore(x)
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#else
-/* Trace Macros for Assembly files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_stop(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = 0x1; \
- [preg] = dreg;
-
-#define trace_buffer_init(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = BFIN_TRACE_INIT; \
- [preg] = dreg;
-
-#define trace_buffer_save(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = [preg]; \
- [--sp] = dreg; \
- dreg = 0x1; \
- [preg] = dreg;
-
-#define trace_buffer_restore(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = [sp++]; \
- [preg] = dreg;
-
-#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_stop(preg, dreg)
-#define trace_buffer_init(preg, dreg)
-#define trace_buffer_save(preg, dreg)
-#define trace_buffer_restore(preg, dreg)
-
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
-# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
-#else
-# define DEBUG_HWTRACE_SAVE(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg)
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _BLACKFIN_TRACE_ */
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
deleted file mode 100644
index cec771b..0000000
--- a/arch/blackfin/include/asm/traps.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2001 Lineo, Inc
- * Tony Kou
- * 1993 Hamish Macdonald
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_TRAPS_H
-#define _BFIN_TRAPS_H
-
-#define VEC_SYS (0)
-#define VEC_EXCPT01 (1)
-#define VEC_EXCPT02 (2)
-#define VEC_EXCPT03 (3)
-#define VEC_EXCPT04 (4)
-#define VEC_EXCPT05 (5)
-#define VEC_EXCPT06 (6)
-#define VEC_EXCPT07 (7)
-#define VEC_EXCPT08 (8)
-#define VEC_EXCPT09 (9)
-#define VEC_EXCPT10 (10)
-#define VEC_EXCPT11 (11)
-#define VEC_EXCPT12 (12)
-#define VEC_EXCPT13 (13)
-#define VEC_EXCPT14 (14)
-#define VEC_EXCPT15 (15)
-#define VEC_STEP (16)
-#define VEC_OVFLOW (17)
-#define VEC_UNDEF_I (33)
-#define VEC_ILGAL_I (34)
-#define VEC_CPLB_VL (35)
-#define VEC_MISALI_D (36)
-#define VEC_UNCOV (37)
-#define VEC_CPLB_M (38)
-#define VEC_CPLB_MHIT (39)
-#define VEC_WATCH (40)
-#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
-#define VEC_MISALI_I (42)
-#define VEC_CPLB_I_VL (43)
-#define VEC_CPLB_I_M (44)
-#define VEC_CPLB_I_MHIT (45)
-#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
-/* The hardware reserves (63) for future use - we use it to tell our
- * normal exception handling code we have a hardware error
- */
-#define VEC_HWERR (63)
-
-#ifndef __ASSEMBLY__
-
-#define HWC_x2(level) \
- "System MMR Error\n" \
- level " - An error occurred due to an invalid access to an System MMR location\n" \
- level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
- level " or a 16-bit register is accessed with a 32-bit instruction.\n"
-#define HWC_x3(level) \
- "External Memory Addressing Error\n"
-#define EXC_0x04(level) \
- "Unimplmented exception occurred\n" \
- level " - Maybe you forgot to install a custom exception handler?\n"
-#define HWC_x12(level) \
- "Performance Monitor Overflow\n"
-#define HWC_x18(level) \
- "RAISE 5 instruction\n" \
- level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
-#define HWC_default(level) \
- "Reserved\n"
-#define EXC_0x03(level) \
- "Application stack overflow\n" \
- level " - Please increase the stack size of the application using elf2flt -s option,\n" \
- level " and/or reduce the stack use of the application.\n"
-#define EXC_0x10(level) \
- "Single step\n" \
- level " - When the processor is in single step mode, every instruction\n" \
- level " generates an exception. Primarily used for debugging.\n"
-#define EXC_0x11(level) \
- "Exception caused by a trace buffer full condition\n" \
- level " - The processor takes this exception when the trace\n" \
- level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
-#define EXC_0x21(level) \
- "Undefined instruction\n" \
- level " - May be used to emulate instructions that are not defined for\n" \
- level " a particular processor implementation.\n"
-#define EXC_0x22(level) \
- "Illegal instruction combination\n" \
- level " - See section for multi-issue rules in the Blackfin\n" \
- level " Processor Instruction Set Reference.\n"
-#define EXC_0x23(level) \
- "Data access CPLB protection violation\n" \
- level " - Attempted read or write to Supervisor resource,\n" \
- level " or illegal data memory access. \n"
-#define EXC_0x24(level) \
- "Data access misaligned address violation\n" \
- level " - Attempted misaligned data memory or data cache access.\n"
-#define EXC_0x25(level) \
- "Unrecoverable event\n" \
- level " - For example, an exception generated while processing a previous exception.\n"
-#define EXC_0x26(level) \
- "Data access CPLB miss\n" \
- level " - Used by the MMU to signal a CPLB miss on a data access.\n"
-#define EXC_0x27(level) \
- "Data access multiple CPLB hits\n" \
- level " - More than one CPLB entry matches data fetch address.\n"
-#define EXC_0x28(level) \
- "Program Sequencer Exception caused by an emulation watchpoint match\n" \
- level " - There is a watchpoint match, and one of the EMUSW\n" \
- level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
-#define EXC_0x2A(level) \
- "Instruction fetch misaligned address violation\n" \
- level " - Attempted misaligned instruction cache fetch.\n"
-#define EXC_0x2B(level) \
- "CPLB protection violation\n" \
- level " - Illegal instruction fetch access (memory protection violation).\n"
-#define EXC_0x2C(level) \
- "Instruction fetch CPLB miss\n" \
- level " - CPLB miss on an instruction fetch.\n"
-#define EXC_0x2D(level) \
- "Instruction fetch multiple CPLB hits\n" \
- level " - More than one CPLB entry matches instruction fetch address.\n"
-#define EXC_0x2E(level) \
- "Illegal use of supervisor resource\n" \
- level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
- level " Supervisor resources are registers and instructions that are reserved\n" \
- level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
- level " only instructions.\n"
-
-extern void double_fault_c(struct pt_regs *fp);
-
-#endif /* __ASSEMBLY__ */
-#endif /* _BFIN_TRAPS_H */
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
deleted file mode 100644
index 45da4bc..0000000
--- a/arch/blackfin/include/asm/uaccess.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Based on: include/asm-m68knommu/uaccess.h
- */
-
-#ifndef __BLACKFIN_UACCESS_H
-#define __BLACKFIN_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/mm.h>
-#include <linux/string.h>
-
-#include <asm/segment.h>
-#include <asm/sections.h>
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-
-static inline void set_fs(mm_segment_t fs)
-{
- current_thread_info()->addr_limit = fs;
-}
-
-#define segment_eq(a, b) ((a) == (b))
-
-#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- */
-
-#ifndef CONFIG_ACCESS_CHECK
-static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
-#else
-extern int _access_ok(unsigned long addr, unsigned long size);
-#endif
-
-#include <asm/extable.h>
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- */
-
-#define put_user(x, p) \
- ({ \
- int _err = 0; \
- typeof(*(p)) _x = (x); \
- typeof(*(p)) __user *_p = (p); \
- if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\
- _err = -EFAULT; \
- } \
- else { \
- switch (sizeof (*(_p))) { \
- case 1: \
- __put_user_asm(_x, _p, B); \
- break; \
- case 2: \
- __put_user_asm(_x, _p, W); \
- break; \
- case 4: \
- __put_user_asm(_x, _p, ); \
- break; \
- case 8: { \
- long _xl, _xh; \
- _xl = ((__force long *)&_x)[0]; \
- _xh = ((__force long *)&_x)[1]; \
- __put_user_asm(_xl, ((__force long __user *)_p)+0, );\
- __put_user_asm(_xh, ((__force long __user *)_p)+1, );\
- } break; \
- default: \
- _err = __put_user_bad(); \
- break; \
- } \
- } \
- _err; \
- })
-
-#define __put_user(x, p) put_user(x, p)
-static inline int bad_user_access_length(void)
-{
- panic("bad_user_access_length");
- return -1;
-}
-
-#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
- __FILE__, __LINE__, __func__),\
- bad_user_access_length(), (-EFAULT))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#define __ptr(x) ((unsigned long __force *)(x))
-
-#define __put_user_asm(x, p, bhw) \
- __asm__ (#bhw"[%1] = %0;\n\t" \
- : /* no outputs */ \
- :"d" (x), "a" (__ptr(p)) : "memory")
-
-#define get_user(x, ptr) \
-({ \
- int _err = 0; \
- unsigned long _val = 0; \
- const typeof(*(ptr)) __user *_p = (ptr); \
- const size_t ptr_size = sizeof(*(_p)); \
- if (likely(access_ok(VERIFY_READ, _p, ptr_size))) { \
- BUILD_BUG_ON(ptr_size >= 8); \
- switch (ptr_size) { \
- case 1: \
- __get_user_asm(_val, _p, B, (Z)); \
- break; \
- case 2: \
- __get_user_asm(_val, _p, W, (Z)); \
- break; \
- case 4: \
- __get_user_asm(_val, _p, , ); \
- break; \
- } \
- } else \
- _err = -EFAULT; \
- x = (__force typeof(*(ptr)))_val; \
- _err; \
-})
-
-#define __get_user(x, p) get_user(x, p)
-
-#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
-
-#define __get_user_asm(x, ptr, bhw, option) \
-({ \
- __asm__ __volatile__ ( \
- "%0 =" #bhw "[%1]" #option ";" \
- : "=d" (x) \
- : "a" (__ptr(ptr))); \
-})
-
-static inline unsigned long __must_check
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- memcpy(to, (const void __force *)from, n);
- return 0;
-}
-
-static inline unsigned long __must_check
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- memcpy((void __force *)to, from, n);
- SSYNC();
- return 0;
-}
-
-#define INLINE_COPY_FROM_USER
-#define INLINE_COPY_TO_USER
-/*
- * Copy a null terminated string from userspace.
- */
-
-static inline long __must_check
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
- char *tmp;
- if (!access_ok(VERIFY_READ, src, 1))
- return -EFAULT;
- strncpy(dst, (const char __force *)src, count);
- for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
- return (tmp - dst);
-}
-
-/*
- * Get the size of a string in user space.
- * src: The string to measure
- * n: The maximum valid length
- *
- * Get the size of a NUL-terminated string in user space.
- *
- * Returns the size of the string INCLUDING the terminating NUL.
- * On exception, returns 0.
- * If the string is too long, returns a value greater than n.
- */
-static inline long __must_check strnlen_user(const char __user *src, long n)
-{
- if (!access_ok(VERIFY_READ, src, 1))
- return 0;
- return strnlen((const char __force *)src, n) + 1;
-}
-
-/*
- * Zero Userspace
- */
-
-static inline unsigned long __must_check
-__clear_user(void __user *to, unsigned long n)
-{
- if (!access_ok(VERIFY_WRITE, to, n))
- return n;
- memset((void __force *)to, 0, n);
- return 0;
-}
-
-#define clear_user(to, n) __clear_user(to, n)
-
-/* How to interpret these return values:
- * CORE: can be accessed by core load or dma memcpy
- * CORE_ONLY: can only be accessed by core load
- * DMA: can only be accessed by dma memcpy
- * IDMA: can only be accessed by interprocessor dma memcpy (BF561)
- * ITEST: can be accessed by isram memcpy or dma memcpy
- */
-enum {
- BFIN_MEM_ACCESS_CORE = 0,
- BFIN_MEM_ACCESS_CORE_ONLY,
- BFIN_MEM_ACCESS_DMA,
- BFIN_MEM_ACCESS_IDMA,
- BFIN_MEM_ACCESS_ITEST,
-};
-/**
- * bfin_mem_access_type() - what kind of memory access is required
- * @addr: the address to check
- * @size: number of bytes needed
- * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above)
- */
-int bfin_mem_access_type(unsigned long addr, unsigned long size);
-
-#endif /* _BLACKFIN_UACCESS_H */
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
deleted file mode 100644
index c8c8ff9..0000000
--- a/arch/blackfin/include/asm/unistd.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __ASM_BFIN_UNISTD_H
-#define __ASM_BFIN_UNISTD_H
-
-#include <uapi/asm/unistd.h>
-
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_VFORK
-
-#endif /* __ASM_BFIN_UNISTD_H */
diff --git a/arch/blackfin/include/asm/vga.h b/arch/blackfin/include/asm/vga.h
deleted file mode 100644
index 89d82fd..0000000
--- a/arch/blackfin/include/asm/vga.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/vga.h>
diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h
deleted file mode 100644
index af9fc81..0000000
--- a/arch/blackfin/include/mach-common/irq.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Common Blackfin IRQ definitions (i.e. the CEC)
- *
- * Copyright 2005-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_COMMON_IRQ_H_
-#define _MACH_COMMON_IRQ_H_
-
-/*
- * Core events interrupt source definitions
- *
- * Event Source Event Name
- * Emulation EMU 0 (highest priority)
- * Reset RST 1
- * NMI NMI 2
- * Exception EVX 3
- * Reserved -- 4
- * Hardware Error IVHW 5
- * Core Timer IVTMR 6
- * Peripherals IVG7 7
- * Peripherals IVG8 8
- * Peripherals IVG9 9
- * Peripherals IVG10 10
- * Peripherals IVG11 11
- * Peripherals IVG12 12
- * Peripherals IVG13 13
- * Softirq IVG14 14
- * System Call IVG15 15 (lowest priority)
- */
-
-/* The ABSTRACT IRQ definitions */
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-
-#define BFIN_IRQ(x) ((x) + IVG7)
-#define BFIN_SYSIRQ(x) ((x) - IVG7)
-
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h
deleted file mode 100644
index 382178b..0000000
--- a/arch/blackfin/include/mach-common/pll.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_COMMON_PLL_H
-#define _MACH_COMMON_PLL_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-#ifndef bfin_iwr_restore
-static inline void
-bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
-{
-#ifdef SIC_IWR
- bfin_write_SIC_IWR(iwr0);
-#else
- bfin_write_SIC_IWR0(iwr0);
-# ifdef SIC_IWR1
- bfin_write_SIC_IWR1(iwr1);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(iwr2);
-# endif
-#endif
-}
-#endif
-
-#ifndef bfin_iwr_save
-static inline void
-bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
- unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
-#ifdef SIC_IWR
- *iwr0 = bfin_read_SIC_IWR();
-#else
- *iwr0 = bfin_read_SIC_IWR0();
-# ifdef SIC_IWR1
- *iwr1 = bfin_read_SIC_IWR1();
-# endif
-# ifdef SIC_IWR2
- *iwr2 = bfin_read_SIC_IWR2();
-# endif
-#endif
- bfin_iwr_restore(niwr0, niwr1, niwr2);
-}
-#endif
-
-static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
-{
- unsigned long flags, iwr0, iwr1, iwr2;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- flags = hard_local_irq_save();
- /* Enable the PLL Wakeup bit in SIC IWR */
- bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
-
- bfin_write16(addr, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_iwr_restore(iwr0, iwr1, iwr2);
- hard_local_irq_restore(flags);
-}
-
-/* Writing to PLL_CTL initiates a PLL relock sequence */
-static inline void bfin_write_PLL_CTL(unsigned int val)
-{
- _bfin_write_pll_relock(PLL_CTL, val);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence */
-static inline void bfin_write_VR_CTL(unsigned int val)
-{
- _bfin_write_pll_relock(VR_CTL, val);
-}
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h
deleted file mode 100644
index 71bcd74..0000000
--- a/arch/blackfin/include/mach-common/ports-a.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port A Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_A__
-#define __BFIN_PERIPHERAL_PORT_A__
-
-#define PA0 (1 << 0)
-#define PA1 (1 << 1)
-#define PA2 (1 << 2)
-#define PA3 (1 << 3)
-#define PA4 (1 << 4)
-#define PA5 (1 << 5)
-#define PA6 (1 << 6)
-#define PA7 (1 << 7)
-#define PA8 (1 << 8)
-#define PA9 (1 << 9)
-#define PA10 (1 << 10)
-#define PA11 (1 << 11)
-#define PA12 (1 << 12)
-#define PA13 (1 << 13)
-#define PA14 (1 << 14)
-#define PA15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h
deleted file mode 100644
index 8013cc8..0000000
--- a/arch/blackfin/include/mach-common/ports-b.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port B Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_B__
-#define __BFIN_PERIPHERAL_PORT_B__
-
-#define PB0 (1 << 0)
-#define PB1 (1 << 1)
-#define PB2 (1 << 2)
-#define PB3 (1 << 3)
-#define PB4 (1 << 4)
-#define PB5 (1 << 5)
-#define PB6 (1 << 6)
-#define PB7 (1 << 7)
-#define PB8 (1 << 8)
-#define PB9 (1 << 9)
-#define PB10 (1 << 10)
-#define PB11 (1 << 11)
-#define PB12 (1 << 12)
-#define PB13 (1 << 13)
-#define PB14 (1 << 14)
-#define PB15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h
deleted file mode 100644
index 94e7101..0000000
--- a/arch/blackfin/include/mach-common/ports-c.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port C Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_C__
-#define __BFIN_PERIPHERAL_PORT_C__
-
-#define PC0 (1 << 0)
-#define PC1 (1 << 1)
-#define PC2 (1 << 2)
-#define PC3 (1 << 3)
-#define PC4 (1 << 4)
-#define PC5 (1 << 5)
-#define PC6 (1 << 6)
-#define PC7 (1 << 7)
-#define PC8 (1 << 8)
-#define PC9 (1 << 9)
-#define PC10 (1 << 10)
-#define PC11 (1 << 11)
-#define PC12 (1 << 12)
-#define PC13 (1 << 13)
-#define PC14 (1 << 14)
-#define PC15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h
deleted file mode 100644
index ba84a9f..0000000
--- a/arch/blackfin/include/mach-common/ports-d.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port D Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_D__
-#define __BFIN_PERIPHERAL_PORT_D__
-
-#define PD0 (1 << 0)
-#define PD1 (1 << 1)
-#define PD2 (1 << 2)
-#define PD3 (1 << 3)
-#define PD4 (1 << 4)
-#define PD5 (1 << 5)
-#define PD6 (1 << 6)
-#define PD7 (1 << 7)
-#define PD8 (1 << 8)
-#define PD9 (1 << 9)
-#define PD10 (1 << 10)
-#define PD11 (1 << 11)
-#define PD12 (1 << 12)
-#define PD13 (1 << 13)
-#define PD14 (1 << 14)
-#define PD15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h
deleted file mode 100644
index 2264fb5..0000000
--- a/arch/blackfin/include/mach-common/ports-e.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port E Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_E__
-#define __BFIN_PERIPHERAL_PORT_E__
-
-#define PE0 (1 << 0)
-#define PE1 (1 << 1)
-#define PE2 (1 << 2)
-#define PE3 (1 << 3)
-#define PE4 (1 << 4)
-#define PE5 (1 << 5)
-#define PE6 (1 << 6)
-#define PE7 (1 << 7)
-#define PE8 (1 << 8)
-#define PE9 (1 << 9)
-#define PE10 (1 << 10)
-#define PE11 (1 << 11)
-#define PE12 (1 << 12)
-#define PE13 (1 << 13)
-#define PE14 (1 << 14)
-#define PE15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h
deleted file mode 100644
index 2b8ca3a..0000000
--- a/arch/blackfin/include/mach-common/ports-f.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port F Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_F__
-#define __BFIN_PERIPHERAL_PORT_F__
-
-#define PF0 (1 << 0)
-#define PF1 (1 << 1)
-#define PF2 (1 << 2)
-#define PF3 (1 << 3)
-#define PF4 (1 << 4)
-#define PF5 (1 << 5)
-#define PF6 (1 << 6)
-#define PF7 (1 << 7)
-#define PF8 (1 << 8)
-#define PF9 (1 << 9)
-#define PF10 (1 << 10)
-#define PF11 (1 << 11)
-#define PF12 (1 << 12)
-#define PF13 (1 << 13)
-#define PF14 (1 << 14)
-#define PF15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h
deleted file mode 100644
index 11ad917..0000000
--- a/arch/blackfin/include/mach-common/ports-g.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port G Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_G__
-#define __BFIN_PERIPHERAL_PORT_G__
-
-#define PG0 (1 << 0)
-#define PG1 (1 << 1)
-#define PG2 (1 << 2)
-#define PG3 (1 << 3)
-#define PG4 (1 << 4)
-#define PG5 (1 << 5)
-#define PG6 (1 << 6)
-#define PG7 (1 << 7)
-#define PG8 (1 << 8)
-#define PG9 (1 << 9)
-#define PG10 (1 << 10)
-#define PG11 (1 << 11)
-#define PG12 (1 << 12)
-#define PG13 (1 << 13)
-#define PG14 (1 << 14)
-#define PG15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h
deleted file mode 100644
index 511d088..0000000
--- a/arch/blackfin/include/mach-common/ports-h.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port H Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_H__
-#define __BFIN_PERIPHERAL_PORT_H__
-
-#define PH0 (1 << 0)
-#define PH1 (1 << 1)
-#define PH2 (1 << 2)
-#define PH3 (1 << 3)
-#define PH4 (1 << 4)
-#define PH5 (1 << 5)
-#define PH6 (1 << 6)
-#define PH7 (1 << 7)
-#define PH8 (1 << 8)
-#define PH9 (1 << 9)
-#define PH10 (1 << 10)
-#define PH11 (1 << 11)
-#define PH12 (1 << 12)
-#define PH13 (1 << 13)
-#define PH14 (1 << 14)
-#define PH15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h
deleted file mode 100644
index 21bbab16..0000000
--- a/arch/blackfin/include/mach-common/ports-i.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port I Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_I__
-#define __BFIN_PERIPHERAL_PORT_I__
-
-#define PI0 (1 << 0)
-#define PI1 (1 << 1)
-#define PI2 (1 << 2)
-#define PI3 (1 << 3)
-#define PI4 (1 << 4)
-#define PI5 (1 << 5)
-#define PI6 (1 << 6)
-#define PI7 (1 << 7)
-#define PI8 (1 << 8)
-#define PI9 (1 << 9)
-#define PI10 (1 << 10)
-#define PI11 (1 << 11)
-#define PI12 (1 << 12)
-#define PI13 (1 << 13)
-#define PI14 (1 << 14)
-#define PI15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h
deleted file mode 100644
index 96a252b..0000000
--- a/arch/blackfin/include/mach-common/ports-j.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port J Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_J__
-#define __BFIN_PERIPHERAL_PORT_J__
-
-#define PJ0 (1 << 0)
-#define PJ1 (1 << 1)
-#define PJ2 (1 << 2)
-#define PJ3 (1 << 3)
-#define PJ4 (1 << 4)
-#define PJ5 (1 << 5)
-#define PJ6 (1 << 6)
-#define PJ7 (1 << 7)
-#define PJ8 (1 << 8)
-#define PJ9 (1 << 9)
-#define PJ10 (1 << 10)
-#define PJ11 (1 << 11)
-#define PJ12 (1 << 12)
-#define PJ13 (1 << 13)
-#define PJ14 (1 << 14)
-#define PJ15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/uapi/asm/Kbuild b/arch/blackfin/include/uapi/asm/Kbuild
deleted file mode 100644
index 2240b38..0000000
--- a/arch/blackfin/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,25 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += auxvec.h
-generic-y += bitsperlong.h
-generic-y += bpf_perf_event.h
-generic-y += errno.h
-generic-y += ioctl.h
-generic-y += ipcbuf.h
-generic-y += kvm_para.h
-generic-y += mman.h
-generic-y += msgbuf.h
-generic-y += param.h
-generic-y += resource.h
-generic-y += sembuf.h
-generic-y += setup.h
-generic-y += shmbuf.h
-generic-y += shmparam.h
-generic-y += socket.h
-generic-y += sockios.h
-generic-y += statfs.h
-generic-y += termbits.h
-generic-y += termios.h
-generic-y += types.h
-generic-y += ucontext.h
diff --git a/arch/blackfin/include/uapi/asm/bfin_sport.h b/arch/blackfin/include/uapi/asm/bfin_sport.h
deleted file mode 100644
index 86c36a2..0000000
--- a/arch/blackfin/include/uapi/asm/bfin_sport.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * bfin_sport.h - interface to Blackfin SPORTs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__BFIN_SPORT_H__
-#define _UAPI__BFIN_SPORT_H__
-
-/* Sport mode: it can be set to TDM, i2s or others */
-#define NORM_MODE 0x0
-#define TDM_MODE 0x1
-#define I2S_MODE 0x2
-#define NDSO_MODE 0x3
-
-/* Data format, normal, a-law or u-law */
-#define NORM_FORMAT 0x0
-#define ALAW_FORMAT 0x2
-#define ULAW_FORMAT 0x3
-
-/* Function driver which use sport must initialize the structure */
-struct sport_config {
- /* TDM (multichannels), I2S or other mode */
- unsigned int mode:3;
- unsigned int polled; /* use poll instead of irq when set */
-
- /* if TDM mode is selected, channels must be set */
- int channels; /* Must be in 8 units */
- unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
-
- /* I2S mode */
- unsigned int right_first:1; /* Right stereo channel first */
-
- /* In mormal mode, the following item need to be set */
- unsigned int lsb_first:1; /* order of transmit or receive data */
- unsigned int fsync:1; /* Frame sync required */
- unsigned int data_indep:1; /* data independent frame sync generated */
- unsigned int act_low:1; /* Active low TFS */
- unsigned int late_fsync:1; /* Late frame sync */
- unsigned int tckfe:1;
- unsigned int sec_en:1; /* Secondary side enabled */
-
- /* Choose clock source */
- unsigned int int_clk:1; /* Internal or external clock */
-
- /* If external clock is used, the following fields are ignored */
- int serial_clk;
- int fsync_clk;
-
- unsigned int data_format:2; /* Normal, u-law or a-law */
-
- int word_len; /* How length of the word in bits, 3-32 bits */
- int dma_enabled;
-};
-
-/* Userspace interface */
-#define SPORT_IOC_MAGIC 'P'
-#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
-#define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long)
-#define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long)
-
-
-/* SPORT_TCR1 Masks */
-#define TSPEN 0x0001 /* TX enable */
-#define ITCLK 0x0002 /* Internal TX Clock Select */
-#define TDTYPE 0x000C /* TX Data Formatting Select */
-#define DTYPE_NORM 0x0000 /* Data Format Normal */
-#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
-#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
-#define TLSBIT 0x0010 /* TX Bit Order */
-#define ITFS 0x0200 /* Internal TX Frame Sync Select */
-#define TFSR 0x0400 /* TX Frame Sync Required Select */
-#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
-#define LTFS 0x1000 /* Low TX Frame Sync Select */
-#define LATFS 0x2000 /* Late TX Frame Sync Select */
-#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
-
-/* SPORT_TCR2 Masks */
-#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
-#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
-#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
-#define TXSE 0x0100 /* TX Secondary Enable */
-#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
-#define TRFST 0x0400 /* TX Right-First Data Order */
-
-/* SPORT_RCR1 Masks */
-#define RSPEN 0x0001 /* RX enable */
-#define IRCLK 0x0002 /* Internal RX Clock Select */
-#define RDTYPE 0x000C /* RX Data Formatting Select */
-/* DTYPE_* defined above */
-#define RLSBIT 0x0010 /* RX Bit Order */
-#define IRFS 0x0200 /* Internal RX Frame Sync Select */
-#define RFSR 0x0400 /* RX Frame Sync Required Select */
-#define LRFS 0x1000 /* Low RX Frame Sync Select */
-#define LARFS 0x2000 /* Late RX Frame Sync Select */
-#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
-
-/* SPORT_RCR2 Masks */
-/* SLEN defined above */
-#define RXSE 0x0100 /* RX Secondary Enable */
-#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
-#define RRFST 0x0400 /* Right-First Data Order */
-
-/* SPORT_STAT Masks */
-#define RXNE 0x0001 /* RX FIFO Not Empty Status */
-#define RUVF 0x0002 /* RX Underflow Status */
-#define ROVF 0x0004 /* RX Overflow Status */
-#define TXF 0x0008 /* TX FIFO Full Status */
-#define TUVF 0x0010 /* TX Underflow Status */
-#define TOVF 0x0020 /* TX Overflow Status */
-#define TXHRE 0x0040 /* TX Hold Register Empty */
-
-/* SPORT_MCMC1 Masks */
-#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
-#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
-#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
-#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
-#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
-#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
-
-/* SPORT_MCMC2 Masks */
-#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
-#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
-#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
-#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
-#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
-#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
-#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
-#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
-#define MFD 0xF000 /* Multichannel Frame Delay */
-#define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
-#define EX_MFD(x) BFIN_EXTRACT(MFD, x)
-
-#endif /* _UAPI__BFIN_SPORT_H__ */
diff --git a/arch/blackfin/include/uapi/asm/byteorder.h b/arch/blackfin/include/uapi/asm/byteorder.h
deleted file mode 100644
index bcab667..0000000
--- a/arch/blackfin/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI__BFIN_ASM_BYTEORDER_H
-#define _UAPI__BFIN_ASM_BYTEORDER_H
-
-#include <linux/byteorder/little_endian.h>
-
-#endif /* _UAPI__BFIN_ASM_BYTEORDER_H */
diff --git a/arch/blackfin/include/uapi/asm/cachectl.h b/arch/blackfin/include/uapi/asm/cachectl.h
deleted file mode 100644
index b5c86fb..0000000
--- a/arch/blackfin/include/uapi/asm/cachectl.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * based on the mips/cachectl.h
- *
- * Copyright 2010 Analog Devices Inc.
- * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_ASM_CACHECTL
-#define _UAPI_ASM_CACHECTL
-
-/*
- * Options for cacheflush system call
- */
-#define ICACHE (1<<0) /* flush instruction cache */
-#define DCACHE (1<<1) /* writeback and flush data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-#endif /* _UAPI_ASM_CACHECTL */
diff --git a/arch/blackfin/include/uapi/asm/fcntl.h b/arch/blackfin/include/uapi/asm/fcntl.h
deleted file mode 100644
index 0b02954..0000000
--- a/arch/blackfin/include/uapi/asm/fcntl.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_FCNTL_H
-#define _UAPI_BFIN_FCNTL_H
-
-#define O_DIRECTORY 040000 /* must be a directory */
-#define O_NOFOLLOW 0100000 /* don't follow links */
-#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
-#define O_LARGEFILE 0400000
-
-#include <asm-generic/fcntl.h>
-
-#endif /* _UAPI_BFIN_FCNTL_H */
diff --git a/arch/blackfin/include/uapi/asm/fixed_code.h b/arch/blackfin/include/uapi/asm/fixed_code.h
deleted file mode 100644
index 707b921..0000000
--- a/arch/blackfin/include/uapi/asm/fixed_code.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * This file defines the fixed addresses where userspace programs
- * can find atomic code sequences.
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__BFIN_ASM_FIXED_CODE_H__
-#define _UAPI__BFIN_ASM_FIXED_CODE_H__
-
-
-#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
-#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
-#endif
-
-#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
-
-#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
-
-#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
-
-#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
-#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
-#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
-#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
-#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
-#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
-#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
-
-#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
-
-#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
-
-#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
-
-#endif /* _UAPI__BFIN_ASM_FIXED_CODE_H__ */
diff --git a/arch/blackfin/include/uapi/asm/ioctls.h b/arch/blackfin/include/uapi/asm/ioctls.h
deleted file mode 100644
index 422fee3..0000000
--- a/arch/blackfin/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI__ARCH_BFIN_IOCTLS_H__
-#define _UAPI__ARCH_BFIN_IOCTLS_H__
-
-#define FIOQSIZE 0x545E
-#include <asm-generic/ioctls.h>
-
-#endif /* _UAPI__ARCH_BFIN_IOCTLS_H__ */
diff --git a/arch/blackfin/include/uapi/asm/poll.h b/arch/blackfin/include/uapi/asm/poll.h
deleted file mode 100644
index cd2f1a7..0000000
--- a/arch/blackfin/include/uapi/asm/poll.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#ifndef _UAPI__BFIN_POLL_H
-#define _UAPI__BFIN_POLL_H
-
-#define POLLWRNORM POLLOUT
-#define POLLWRBAND 256
-
-#include <asm-generic/poll.h>
-
-#endif /* _UAPI__BFIN_POLL_H */
diff --git a/arch/blackfin/include/uapi/asm/posix_types.h b/arch/blackfin/include/uapi/asm/posix_types.h
deleted file mode 100644
index 8947c75..0000000
--- a/arch/blackfin/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__ARCH_BFIN_POSIX_TYPES_H
-#define _UAPI__ARCH_BFIN_POSIX_TYPES_H
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned int __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned long __kernel_size_t;
-typedef long __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-#define __kernel_size_t __kernel_size_t
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-#define __kernel_old_uid_t __kernel_old_uid_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _UAPI__ARCH_BFIN_POSIX_TYPES_H */
diff --git a/arch/blackfin/include/uapi/asm/ptrace.h b/arch/blackfin/include/uapi/asm/ptrace.h
deleted file mode 100644
index e4423d5..0000000
--- a/arch/blackfin/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_PTRACE_H
-#define _UAPI_BFIN_PTRACE_H
-
-/*
- * GCC defines register number like this:
- * -----------------------------
- * 0 - 7 are data registers R0-R7
- * 8 - 15 are address registers P0-P7
- * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
- * 32 - 33 A registers A0 & A1
- * 34 - status register
- * -----------------------------
- *
- * We follows above, except:
- * 32-33 --- Low 32-bit of A0&1
- * 34-35 --- High 8-bit of A0&1
- */
-
-#ifndef __ASSEMBLY__
-
-struct task_struct;
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-struct pt_regs {
- long orig_pc;
- long ipend;
- long seqstat;
- long rete;
- long retn;
- long retx;
- long pc; /* PC == RETI */
- long rets;
- long reserved; /* Used as scratch during system calls */
- long astat;
- long lb1;
- long lb0;
- long lt1;
- long lt0;
- long lc1;
- long lc0;
- long a1w;
- long a1x;
- long a0w;
- long a0x;
- long b3;
- long b2;
- long b1;
- long b0;
- long l3;
- long l2;
- long l1;
- long l0;
- long m3;
- long m2;
- long m1;
- long m0;
- long i3;
- long i2;
- long i1;
- long i0;
- long usp;
- long fp;
- long p5;
- long p4;
- long p3;
- long p2;
- long p1;
- long p0;
- long r7;
- long r6;
- long r5;
- long r4;
- long r3;
- long r2;
- long r1;
- long r0;
- long orig_r0;
- long orig_p0;
- long syscfg;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13 /* ptrace signal */
-
-#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
-#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
-#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
-
-#define PS_S (0x0002)
-
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-
-#define PT_R0 204
-#define PT_R1 200
-#define PT_R2 196
-#define PT_R3 192
-#define PT_R4 188
-#define PT_R5 184
-#define PT_R6 180
-#define PT_R7 176
-#define PT_P0 172
-#define PT_P1 168
-#define PT_P2 164
-#define PT_P3 160
-#define PT_P4 156
-#define PT_P5 152
-#define PT_FP 148
-#define PT_USP 144
-#define PT_I0 140
-#define PT_I1 136
-#define PT_I2 132
-#define PT_I3 128
-#define PT_M0 124
-#define PT_M1 120
-#define PT_M2 116
-#define PT_M3 112
-#define PT_L0 108
-#define PT_L1 104
-#define PT_L2 100
-#define PT_L3 96
-#define PT_B0 92
-#define PT_B1 88
-#define PT_B2 84
-#define PT_B3 80
-#define PT_A0X 76
-#define PT_A0W 72
-#define PT_A1X 68
-#define PT_A1W 64
-#define PT_LC0 60
-#define PT_LC1 56
-#define PT_LT0 52
-#define PT_LT1 48
-#define PT_LB0 44
-#define PT_LB1 40
-#define PT_ASTAT 36
-#define PT_RESERVED 32
-#define PT_RETS 28
-#define PT_PC 24
-#define PT_RETX 20
-#define PT_RETN 16
-#define PT_RETE 12
-#define PT_SEQSTAT 8
-#define PT_IPEND 4
-
-#define PT_ORIG_R0 208
-#define PT_ORIG_P0 212
-#define PT_SYSCFG 216
-#define PT_TEXT_ADDR 220
-#define PT_TEXT_END_ADDR 224
-#define PT_DATA_ADDR 228
-#define PT_FDPIC_EXEC 232
-#define PT_FDPIC_INTERP 236
-
-#define PT_LAST_PSEUDO PT_FDPIC_INTERP
-
-#endif /* _UAPI_BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/uapi/asm/sigcontext.h b/arch/blackfin/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 66b4d32..0000000
--- a/arch/blackfin/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
-#define _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
-
-/* Add new entries at the end of the structure only. */
-struct sigcontext {
- unsigned long sc_r0;
- unsigned long sc_r1;
- unsigned long sc_r2;
- unsigned long sc_r3;
- unsigned long sc_r4;
- unsigned long sc_r5;
- unsigned long sc_r6;
- unsigned long sc_r7;
- unsigned long sc_p0;
- unsigned long sc_p1;
- unsigned long sc_p2;
- unsigned long sc_p3;
- unsigned long sc_p4;
- unsigned long sc_p5;
- unsigned long sc_usp;
- unsigned long sc_a0w;
- unsigned long sc_a1w;
- unsigned long sc_a0x;
- unsigned long sc_a1x;
- unsigned long sc_astat;
- unsigned long sc_rets;
- unsigned long sc_pc;
- unsigned long sc_retx;
- unsigned long sc_fp;
- unsigned long sc_i0;
- unsigned long sc_i1;
- unsigned long sc_i2;
- unsigned long sc_i3;
- unsigned long sc_m0;
- unsigned long sc_m1;
- unsigned long sc_m2;
- unsigned long sc_m3;
- unsigned long sc_l0;
- unsigned long sc_l1;
- unsigned long sc_l2;
- unsigned long sc_l3;
- unsigned long sc_b0;
- unsigned long sc_b1;
- unsigned long sc_b2;
- unsigned long sc_b3;
- unsigned long sc_lc0;
- unsigned long sc_lc1;
- unsigned long sc_lt0;
- unsigned long sc_lt1;
- unsigned long sc_lb0;
- unsigned long sc_lb1;
- unsigned long sc_seqstat;
-};
-
-#endif /* _UAPI_ASM_BLACKFIN_SIGCONTEXT_H */
diff --git a/arch/blackfin/include/uapi/asm/siginfo.h b/arch/blackfin/include/uapi/asm/siginfo.h
deleted file mode 100644
index 2dd8c9c..0000000
--- a/arch/blackfin/include/uapi/asm/siginfo.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_SIGINFO_H
-#define _UAPI_BFIN_SIGINFO_H
-
-#include <linux/types.h>
-#include <asm-generic/siginfo.h>
-
-#define si_uid16 _sifields._kill._uid
-
-#endif /* _UAPI_BFIN_SIGINFO_H */
diff --git a/arch/blackfin/include/uapi/asm/signal.h b/arch/blackfin/include/uapi/asm/signal.h
deleted file mode 100644
index f8e3b99b..0000000
--- a/arch/blackfin/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_BLACKFIN_SIGNAL_H
-#define _UAPI_BLACKFIN_SIGNAL_H
-
-#define SA_RESTORER 0x04000000
-#include <asm-generic/signal.h>
-
-#endif /* _UAPI_BLACKFIN_SIGNAL_H */
diff --git a/arch/blackfin/include/uapi/asm/stat.h b/arch/blackfin/include/uapi/asm/stat.h
deleted file mode 100644
index 458959d..0000000
--- a/arch/blackfin/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2004-2006 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef _UAPI_BFIN_STAT_H
-#define _UAPI_BFIN_STAT_H
-
-struct stat {
- unsigned short st_dev;
- unsigned short __pad1;
- unsigned long st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned short __pad2;
- unsigned long st_size;
- unsigned long st_blksize;
- unsigned long st_blocks;
- unsigned long st_atime;
- unsigned long __unused1;
- unsigned long st_mtime;
- unsigned long __unused2;
- unsigned long st_ctime;
- unsigned long __unused3;
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
- unsigned long long st_dev;
- unsigned char __pad1[4];
-
-#define STAT64_HAS_BROKEN_ST_INO 1
- unsigned long __st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned long long st_rdev;
- unsigned char __pad2[4];
-
- long long st_size;
- unsigned long st_blksize;
-
- long long st_blocks; /* Number 512-byte blocks allocated. */
-
- unsigned long st_atime;
- unsigned long st_atime_nsec;
-
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
-
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
-
- unsigned long long st_ino;
-};
-
-#endif /* _UAPI_BFIN_STAT_H */
diff --git a/arch/blackfin/include/uapi/asm/swab.h b/arch/blackfin/include/uapi/asm/swab.h
deleted file mode 100644
index d343793..0000000
--- a/arch/blackfin/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BLACKFIN_SWAB_H
-#define _UAPI_BLACKFIN_SWAB_H
-
-#include <linux/types.h>
-#include <asm-generic/swab.h>
-
-#ifdef __GNUC__
-
-static __inline__ __attribute_const__ __u32 __arch_swahb32(__u32 xx)
-{
- __u32 tmp;
- __asm__("%1 = %0 >> 8 (V);\n\t"
- "%0 = %0 << 8 (V);\n\t"
- "%0 = %0 | %1;\n\t"
- : "+d"(xx), "=&d"(tmp));
- return xx;
-}
-#define __arch_swahb32 __arch_swahb32
-
-static __inline__ __attribute_const__ __u32 __arch_swahw32(__u32 xx)
-{
- __u32 rv;
- __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
- return rv;
-}
-#define __arch_swahw32 __arch_swahw32
-
-static __inline__ __attribute_const__ __u32 __arch_swab32(__u32 xx)
-{
- return __arch_swahb32(__arch_swahw32(xx));
-}
-#define __arch_swab32 __arch_swab32
-
-static __inline__ __attribute_const__ __u16 __arch_swab16(__u16 xx)
-{
- __u32 xw = xx;
- __asm__("%0 <<= 8;\n %0.L = %0.L + %0.H (NS);\n": "+d"(xw));
- return (__u16)xw;
-}
-#define __arch_swab16 __arch_swab16
-
-#endif /* __GNUC__ */
-
-#endif /* _UAPI_BLACKFIN_SWAB_H */
diff --git a/arch/blackfin/include/uapi/asm/unistd.h b/arch/blackfin/include/uapi/asm/unistd.h
deleted file mode 100644
index 2d392c0..0000000
--- a/arch/blackfin/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,448 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__ASM_BFIN_UNISTD_H
-#define _UAPI__ASM_BFIN_UNISTD_H
-/*
- * This file contains the system call numbers.
- */
-#define __NR_restart_syscall 0
-#define __NR_exit 1
- /* 2 __NR_fork not supported on nommu */
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
- /* 7 __NR_waitpid obsolete */
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-#define __NR_chown 16
- /* 17 __NR_break obsolete */
- /* 18 __NR_oldstat obsolete */
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
- /* 22 __NR_umount obsolete */
-#define __NR_setuid 23
-#define __NR_getuid 24
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
- /* 28 __NR_oldfstat obsolete */
-#define __NR_pause 29
- /* 30 __NR_utime obsolete */
- /* 31 __NR_stty obsolete */
- /* 32 __NR_gtty obsolete */
-#define __NR_access 33
-#define __NR_nice 34
- /* 35 __NR_ftime obsolete */
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
- /* 44 __NR_prof obsolete */
-#define __NR_brk 45
-#define __NR_setgid 46
-#define __NR_getgid 47
- /* 48 __NR_signal obsolete */
-#define __NR_geteuid 49
-#define __NR_getegid 50
-#define __NR_acct 51
-#define __NR_umount2 52
- /* 53 __NR_lock obsolete */
-#define __NR_ioctl 54
-#define __NR_fcntl 55
- /* 56 __NR_mpx obsolete */
-#define __NR_setpgid 57
- /* 58 __NR_ulimit obsolete */
- /* 59 __NR_oldolduname obsolete */
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
- /* 67 __NR_sigaction obsolete */
-#define __NR_sgetmask 68
-#define __NR_ssetmask 69
-#define __NR_setreuid 70
-#define __NR_setregid 71
- /* 72 __NR_sigsuspend obsolete */
- /* 73 __NR_sigpending obsolete */
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
- /* 76 __NR_old_getrlimit obsolete */
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-#define __NR_getgroups 80
-#define __NR_setgroups 81
- /* 82 __NR_select obsolete */
-#define __NR_symlink 83
- /* 84 __NR_oldlstat obsolete */
-#define __NR_readlink 85
- /* 86 __NR_uselib obsolete */
- /* 87 __NR_swapon obsolete */
-#define __NR_reboot 88
- /* 89 __NR_readdir obsolete */
- /* 90 __NR_mmap obsolete */
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-#define __NR_fchown 95
-#define __NR_getpriority 96
-#define __NR_setpriority 97
- /* 98 __NR_profil obsolete */
-#define __NR_statfs 99
-#define __NR_fstatfs 100
- /* 101 __NR_ioperm */
- /* 102 __NR_socketcall obsolete */
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
- /* 109 __NR_olduname obsolete */
- /* 110 __NR_iopl obsolete */
-#define __NR_vhangup 111
- /* 112 __NR_idle obsolete */
- /* 113 __NR_vm86old */
-#define __NR_wait4 114
- /* 115 __NR_swapoff obsolete */
-#define __NR_sysinfo 116
- /* 117 __NR_ipc oboslete */
-#define __NR_fsync 118
- /* 119 __NR_sigreturn obsolete */
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
- /* 123 __NR_modify_ldt obsolete */
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
- /* 126 __NR_sigprocmask obsolete */
- /* 127 __NR_create_module obsolete */
-#define __NR_init_module 128
-#define __NR_delete_module 129
- /* 130 __NR_get_kernel_syms obsolete */
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
- /* 135 was sysfs */
-#define __NR_personality 136
- /* 137 __NR_afs_syscall */
-#define __NR_setfsuid 138
-#define __NR_setfsgid 139
-#define __NR__llseek 140
-#define __NR_getdents 141
- /* 142 __NR__newselect obsolete */
-#define __NR_flock 143
- /* 144 __NR_msync obsolete */
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
- /* 150 __NR_mlock */
- /* 151 __NR_munlock */
- /* 152 __NR_mlockall */
- /* 153 __NR_munlockall */
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-#define __NR_setresuid 164
-#define __NR_getresuid 165
- /* 166 __NR_vm86 */
- /* 167 __NR_query_module */
- /* 168 __NR_poll */
-#define __NR_nfsservctl 169
-#define __NR_setresgid 170
-#define __NR_getresgid 171
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread 180
-#define __NR_pwrite 181
-#define __NR_lchown 182
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
- /* 188 __NR_getpmsg */
- /* 189 __NR_putpmsg */
-#define __NR_vfork 190
-#define __NR_getrlimit 191
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_chown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_lchown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
- /* 218 __NR_mincore */
- /* 219 __NR_madvise */
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
- /* 222 reserved for TUX */
- /* 223 reserved for TUX */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
- /* 243 __NR_set_thread_area */
- /* 244 __NR_get_thread_area */
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
- /* 250 __NR_alloc_hugepages */
- /* 251 __NR_free_hugepages */
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_bfin_spinlock 254
-
-#define __NR_epoll_create 255
-#define __NR_epoll_ctl 256
-#define __NR_epoll_wait 257
- /* 258 __NR_remap_file_pages */
-#define __NR_set_tid_address 259
-#define __NR_timer_create 260
-#define __NR_timer_settime 261
-#define __NR_timer_gettime 262
-#define __NR_timer_getoverrun 263
-#define __NR_timer_delete 264
-#define __NR_clock_settime 265
-#define __NR_clock_gettime 266
-#define __NR_clock_getres 267
-#define __NR_clock_nanosleep 268
-#define __NR_statfs64 269
-#define __NR_fstatfs64 270
-#define __NR_tgkill 271
-#define __NR_utimes 272
-#define __NR_fadvise64_64 273
- /* 274 __NR_vserver */
- /* 275 __NR_mbind */
- /* 276 __NR_get_mempolicy */
- /* 277 __NR_set_mempolicy */
-#define __NR_mq_open 278
-#define __NR_mq_unlink 279
-#define __NR_mq_timedsend 280
-#define __NR_mq_timedreceive 281
-#define __NR_mq_notify 282
-#define __NR_mq_getsetattr 283
-#define __NR_kexec_load 284
-#define __NR_waitid 285
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_ioprio_set 289
-#define __NR_ioprio_get 290
-#define __NR_inotify_init 291
-#define __NR_inotify_add_watch 292
-#define __NR_inotify_rm_watch 293
- /* 294 __NR_migrate_pages */
-#define __NR_openat 295
-#define __NR_mkdirat 296
-#define __NR_mknodat 297
-#define __NR_fchownat 298
-#define __NR_futimesat 299
-#define __NR_fstatat64 300
-#define __NR_unlinkat 301
-#define __NR_renameat 302
-#define __NR_linkat 303
-#define __NR_symlinkat 304
-#define __NR_readlinkat 305
-#define __NR_fchmodat 306
-#define __NR_faccessat 307
-#define __NR_pselect6 308
-#define __NR_ppoll 309
-#define __NR_unshare 310
-
-/* Blackfin private syscalls */
-#define __NR_sram_alloc 311
-#define __NR_sram_free 312
-#define __NR_dma_memcpy 313
-
-/* socket syscalls */
-#define __NR_accept 314
-#define __NR_bind 315
-#define __NR_connect 316
-#define __NR_getpeername 317
-#define __NR_getsockname 318
-#define __NR_getsockopt 319
-#define __NR_listen 320
-#define __NR_recv 321
-#define __NR_recvfrom 322
-#define __NR_recvmsg 323
-#define __NR_send 324
-#define __NR_sendmsg 325
-#define __NR_sendto 326
-#define __NR_setsockopt 327
-#define __NR_shutdown 328
-#define __NR_socket 329
-#define __NR_socketpair 330
-
-/* sysv ipc syscalls */
-#define __NR_semctl 331
-#define __NR_semget 332
-#define __NR_semop 333
-#define __NR_msgctl 334
-#define __NR_msgget 335
-#define __NR_msgrcv 336
-#define __NR_msgsnd 337
-#define __NR_shmat 338
-#define __NR_shmctl 339
-#define __NR_shmdt 340
-#define __NR_shmget 341
-
-#define __NR_splice 342
-#define __NR_sync_file_range 343
-#define __NR_tee 344
-#define __NR_vmsplice 345
-
-#define __NR_epoll_pwait 346
-#define __NR_utimensat 347
-#define __NR_signalfd 348
-#define __NR_timerfd_create 349
-#define __NR_eventfd 350
-#define __NR_pread64 351
-#define __NR_pwrite64 352
-#define __NR_fadvise64 353
-#define __NR_set_robust_list 354
-#define __NR_get_robust_list 355
-#define __NR_fallocate 356
-#define __NR_semtimedop 357
-#define __NR_timerfd_settime 358
-#define __NR_timerfd_gettime 359
-#define __NR_signalfd4 360
-#define __NR_eventfd2 361
-#define __NR_epoll_create1 362
-#define __NR_dup3 363
-#define __NR_pipe2 364
-#define __NR_inotify_init1 365
-#define __NR_preadv 366
-#define __NR_pwritev 367
-#define __NR_rt_tgsigqueueinfo 368
-#define __NR_perf_event_open 369
-#define __NR_recvmmsg 370
-#define __NR_fanotify_init 371
-#define __NR_fanotify_mark 372
-#define __NR_prlimit64 373
-#define __NR_cacheflush 374
-#define __NR_name_to_handle_at 375
-#define __NR_open_by_handle_at 376
-#define __NR_clock_adjtime 377
-#define __NR_syncfs 378
-#define __NR_setns 379
-#define __NR_sendmmsg 380
-#define __NR_process_vm_readv 381
-#define __NR_process_vm_writev 382
-#define __NR_kcmp 383
-#define __NR_finit_module 384
-#define __NR_sched_setattr 385
-#define __NR_sched_getattr 386
-#define __NR_renameat2 387
-#define __NR_seccomp 388
-#define __NR_getrandom 389
-#define __NR_memfd_create 390
-#define __NR_bpf 391
-#define __NR_execveat 392
-
-#define __NR_syscall 393 /* For internal using, not implemented */
-#define NR_syscalls __NR_syscall
-
-/* Old optional stuff no one actually uses */
-#define __IGNORE_sysfs
-#define __IGNORE_uselib
-
-/* Implement the newer interfaces */
-#define __IGNORE_mmap
-#define __IGNORE_poll
-#define __IGNORE_select
-#define __IGNORE_utime
-
-/* Not relevant on no-mmu */
-#define __IGNORE_swapon
-#define __IGNORE_swapoff
-#define __IGNORE_msync
-#define __IGNORE_mlock
-#define __IGNORE_munlock
-#define __IGNORE_mlockall
-#define __IGNORE_munlockall
-#define __IGNORE_mincore
-#define __IGNORE_madvise
-#define __IGNORE_remap_file_pages
-#define __IGNORE_mbind
-#define __IGNORE_get_mempolicy
-#define __IGNORE_set_mempolicy
-#define __IGNORE_migrate_pages
-#define __IGNORE_move_pages
-#define __IGNORE_getcpu
-
-
-#endif /* _UAPI__ASM_BFIN_UNISTD_H */
diff --git a/arch/blackfin/kernel/.gitignore b/arch/blackfin/kernel/.gitignore
deleted file mode 100644
index c5f676c..0000000
--- a/arch/blackfin/kernel/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-vmlinux.lds
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
deleted file mode 100644
index 1580791..0000000
--- a/arch/blackfin/kernel/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/kernel/Makefile
-#
-
-extra-y := vmlinux.lds
-
-obj-y := \
- entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
- sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
- fixed_code.o reboot.o bfin_dma.o \
- exception.o dumpstack.o
-
-ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
- obj-y += time-ts.o
-else
- obj-y += time.o
-endif
-
-obj-$(CONFIG_GPIO_ADI) += bfin_gpio.o
-obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
-obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
-obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
-CFLAGS_REMOVE_ftrace.o = -pg
-
-obj-$(CONFIG_IPIPE) += ipipe.o
-obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
-obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
-obj-$(CONFIG_MODULES) += module.o
-obj-$(CONFIG_KGDB) += kgdb.o
-obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o
-obj-$(CONFIG_NMI_WATCHDOG) += nmi.o
-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o
-obj-$(CONFIG_STACKTRACE) += stacktrace.o
-obj-$(CONFIG_DEBUG_VERBOSE) += trace.o
-obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o
-obj-$(CONFIG_PERF_EVENTS) += perf_event.o
-
-# the kgdb test puts code into L2 and without linker
-# relaxation, we need to force long calls to/from it
-CFLAGS_kgdb_test.o := -mlong-calls
-
-obj-$(CONFIG_DEBUG_MMRS) += debug-mmrs.o
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
deleted file mode 100644
index 486560a..0000000
--- a/arch/blackfin/kernel/asm-offsets.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * generate definitions needed by assembly language modules
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/stddef.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <linux/ptrace.h>
-#include <linux/hardirq.h>
-#include <linux/irq.h>
-#include <linux/thread_info.h>
-#include <linux/kbuild.h>
-#include <asm/pda.h>
-
-int main(void)
-{
- /* offsets into the task struct */
- DEFINE(TASK_STATE, offsetof(struct task_struct, state));
- DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
- DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
- DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked));
- DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
- DEFINE(TASK_THREAD_INFO, offsetof(struct task_struct, stack));
- DEFINE(TASK_MM, offsetof(struct task_struct, mm));
- DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
- DEFINE(TASK_SIGPENDING, offsetof(struct task_struct, pending));
-
- /* offsets into the irq_cpustat_t struct */
- DEFINE(CPUSTAT_SOFTIRQ_PENDING,
- offsetof(irq_cpustat_t, __softirq_pending));
-
- /* offsets into the thread struct */
- DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
- DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
- DEFINE(THREAD_SR, offsetof(struct thread_struct, seqstat));
- DEFINE(PT_SR, offsetof(struct thread_struct, seqstat));
- DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
- DEFINE(THREAD_PC, offsetof(struct thread_struct, pc));
- DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE);
-
- /* offsets in thread_info struct */
- OFFSET(TI_TASK, thread_info, task);
- OFFSET(TI_FLAGS, thread_info, flags);
- OFFSET(TI_CPU, thread_info, cpu);
- OFFSET(TI_PREEMPT, thread_info, preempt_count);
-
- /* offsets into the pt_regs */
- DEFINE(PT_ORIG_R0, offsetof(struct pt_regs, orig_r0));
- DEFINE(PT_ORIG_P0, offsetof(struct pt_regs, orig_p0));
- DEFINE(PT_ORIG_PC, offsetof(struct pt_regs, orig_pc));
- DEFINE(PT_R0, offsetof(struct pt_regs, r0));
- DEFINE(PT_R1, offsetof(struct pt_regs, r1));
- DEFINE(PT_R2, offsetof(struct pt_regs, r2));
- DEFINE(PT_R3, offsetof(struct pt_regs, r3));
- DEFINE(PT_R4, offsetof(struct pt_regs, r4));
- DEFINE(PT_R5, offsetof(struct pt_regs, r5));
- DEFINE(PT_R6, offsetof(struct pt_regs, r6));
- DEFINE(PT_R7, offsetof(struct pt_regs, r7));
-
- DEFINE(PT_P0, offsetof(struct pt_regs, p0));
- DEFINE(PT_P1, offsetof(struct pt_regs, p1));
- DEFINE(PT_P2, offsetof(struct pt_regs, p2));
- DEFINE(PT_P3, offsetof(struct pt_regs, p3));
- DEFINE(PT_P4, offsetof(struct pt_regs, p4));
- DEFINE(PT_P5, offsetof(struct pt_regs, p5));
-
- DEFINE(PT_FP, offsetof(struct pt_regs, fp));
- DEFINE(PT_USP, offsetof(struct pt_regs, usp));
- DEFINE(PT_I0, offsetof(struct pt_regs, i0));
- DEFINE(PT_I1, offsetof(struct pt_regs, i1));
- DEFINE(PT_I2, offsetof(struct pt_regs, i2));
- DEFINE(PT_I3, offsetof(struct pt_regs, i3));
- DEFINE(PT_M0, offsetof(struct pt_regs, m0));
- DEFINE(PT_M1, offsetof(struct pt_regs, m1));
- DEFINE(PT_M2, offsetof(struct pt_regs, m2));
- DEFINE(PT_M3, offsetof(struct pt_regs, m3));
- DEFINE(PT_L0, offsetof(struct pt_regs, l0));
- DEFINE(PT_L1, offsetof(struct pt_regs, l1));
- DEFINE(PT_L2, offsetof(struct pt_regs, l2));
- DEFINE(PT_L3, offsetof(struct pt_regs, l3));
- DEFINE(PT_B0, offsetof(struct pt_regs, b0));
- DEFINE(PT_B1, offsetof(struct pt_regs, b1));
- DEFINE(PT_B2, offsetof(struct pt_regs, b2));
- DEFINE(PT_B3, offsetof(struct pt_regs, b3));
- DEFINE(PT_A0X, offsetof(struct pt_regs, a0x));
- DEFINE(PT_A0W, offsetof(struct pt_regs, a0w));
- DEFINE(PT_A1X, offsetof(struct pt_regs, a1x));
- DEFINE(PT_A1W, offsetof(struct pt_regs, a1w));
- DEFINE(PT_LC0, offsetof(struct pt_regs, lc0));
- DEFINE(PT_LC1, offsetof(struct pt_regs, lc1));
- DEFINE(PT_LT0, offsetof(struct pt_regs, lt0));
- DEFINE(PT_LT1, offsetof(struct pt_regs, lt1));
- DEFINE(PT_LB0, offsetof(struct pt_regs, lb0));
- DEFINE(PT_LB1, offsetof(struct pt_regs, lb1));
- DEFINE(PT_ASTAT, offsetof(struct pt_regs, astat));
- DEFINE(PT_RESERVED, offsetof(struct pt_regs, reserved));
- DEFINE(PT_RETS, offsetof(struct pt_regs, rets));
- DEFINE(PT_PC, offsetof(struct pt_regs, pc));
- DEFINE(PT_RETX, offsetof(struct pt_regs, retx));
- DEFINE(PT_RETN, offsetof(struct pt_regs, retn));
- DEFINE(PT_RETE, offsetof(struct pt_regs, rete));
- DEFINE(PT_SEQSTAT, offsetof(struct pt_regs, seqstat));
- DEFINE(PT_SYSCFG, offsetof(struct pt_regs, syscfg));
- DEFINE(PT_IPEND, offsetof(struct pt_regs, ipend));
- DEFINE(SIZEOF_PTREGS, sizeof(struct pt_regs));
- DEFINE(PT_TEXT_ADDR, sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_TEXT_END_ADDR, 4 + sizeof(struct pt_regs));/* Needed by gdb */
- DEFINE(PT_DATA_ADDR, 8 + sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_FDPIC_EXEC, 12 + sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_FDPIC_INTERP, 16 + sizeof(struct pt_regs));/* Needed by gdb */
-
- /* signal defines */
- DEFINE(SIGSEGV, SIGSEGV);
- DEFINE(SIGTRAP, SIGTRAP);
-
- /* PDA management (in L1 scratchpad) */
- DEFINE(PDA_SYSCFG, offsetof(struct blackfin_pda, syscfg));
-#ifdef CONFIG_SMP
- DEFINE(PDA_IRQFLAGS, offsetof(struct blackfin_pda, imask));
-#endif
- DEFINE(PDA_IPDT, offsetof(struct blackfin_pda, ipdt));
- DEFINE(PDA_IPDT_SWAPCOUNT, offsetof(struct blackfin_pda, ipdt_swapcount));
- DEFINE(PDA_DPDT, offsetof(struct blackfin_pda, dpdt));
- DEFINE(PDA_DPDT_SWAPCOUNT, offsetof(struct blackfin_pda, dpdt_swapcount));
- DEFINE(PDA_EXIPTR, offsetof(struct blackfin_pda, ex_iptr));
- DEFINE(PDA_EXOPTR, offsetof(struct blackfin_pda, ex_optr));
- DEFINE(PDA_EXBUF, offsetof(struct blackfin_pda, ex_buf));
- DEFINE(PDA_EXIMASK, offsetof(struct blackfin_pda, ex_imask));
- DEFINE(PDA_EXSTACK, offsetof(struct blackfin_pda, ex_stack));
- DEFINE(PDA_EXIPEND, offsetof(struct blackfin_pda, ex_ipend));
-#ifdef ANOMALY_05000261
- DEFINE(PDA_LFRETX, offsetof(struct blackfin_pda, last_cplb_fault_retx));
-#endif
- DEFINE(PDA_DCPLB, offsetof(struct blackfin_pda, dcplb_fault_addr));
- DEFINE(PDA_ICPLB, offsetof(struct blackfin_pda, icplb_fault_addr));
- DEFINE(PDA_RETX, offsetof(struct blackfin_pda, retx));
- DEFINE(PDA_SEQSTAT, offsetof(struct blackfin_pda, seqstat));
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- DEFINE(PDA_DF_DCPLB, offsetof(struct blackfin_pda, dcplb_doublefault_addr));
- DEFINE(PDA_DF_ICPLB, offsetof(struct blackfin_pda, icplb_doublefault_addr));
- DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault));
- DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault));
-#endif
-
- /* PDA initial management */
- DEFINE(PDA_INIT_RETX, offsetof(struct blackfin_initial_pda, retx));
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- DEFINE(PDA_INIT_DF_DCPLB, offsetof(struct blackfin_initial_pda, dcplb_doublefault_addr));
- DEFINE(PDA_INIT_DF_ICPLB, offsetof(struct blackfin_initial_pda, icplb_doublefault_addr));
- DEFINE(PDA_INIT_DF_SEQSTAT, offsetof(struct blackfin_initial_pda, seqstat_doublefault));
- DEFINE(PDA_INIT_DF_RETX, offsetof(struct blackfin_initial_pda, retx_doublefault));
-#endif
-
-#ifdef CONFIG_SMP
- /* Inter-core lock (in L2 SRAM) */
- DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot));
-#endif
-
- return 0;
-}
diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c
deleted file mode 100644
index 9d3eb0c..0000000
--- a/arch/blackfin/kernel/bfin_dma.c
+++ /dev/null
@@ -1,612 +0,0 @@
-/*
- * bfin_dma.c - Blackfin DMA implementation
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/param.h>
-#include <linux/proc_fs.h>
-#include <linux/sched.h>
-#include <linux/seq_file.h>
-#include <linux/spinlock.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <linux/uaccess.h>
-#include <asm/early_printk.h>
-
-/*
- * To make sure we work around 05000119 - we always check DMA_DONE bit,
- * never the DMA_RUN bit
- */
-
-struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-EXPORT_SYMBOL(dma_ch);
-
-static int __init blackfin_dma_init(void)
-{
- int i;
-
- printk(KERN_INFO "Blackfin DMA Controller\n");
-
-
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0111);
-#endif
-
- for (i = 0; i < MAX_DMA_CHANNELS; i++) {
- atomic_set(&dma_ch[i].chan_status, 0);
- dma_ch[i].regs = dma_io_base_addr[i];
- }
-#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
- /* Mark MEMDMA Channel 3 as requested since we're using it internally */
- request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
- request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
-#else
- /* Mark MEMDMA Channel 0 as requested since we're using it internally */
- request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
- request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
-#endif
-
-#if defined(CONFIG_DEB_DMA_URGENT)
- bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
- | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
-#endif
-
- return 0;
-}
-arch_initcall(blackfin_dma_init);
-
-#ifdef CONFIG_PROC_FS
-static int proc_dma_show(struct seq_file *m, void *v)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i)
- if (dma_channel_active(i))
- seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
-
- return 0;
-}
-
-static int proc_dma_open(struct inode *inode, struct file *file)
-{
- return single_open(file, proc_dma_show, NULL);
-}
-
-static const struct file_operations proc_dma_operations = {
- .open = proc_dma_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init proc_dma_init(void)
-{
- proc_create("dma", 0, NULL, &proc_dma_operations);
- return 0;
-}
-late_initcall(proc_dma_init);
-#endif
-
-static void set_dma_peripheral_map(unsigned int channel, const char *device_id)
-{
-#ifdef CONFIG_BF54x
- unsigned int per_map;
-
- switch (channel) {
- case CH_UART2_RX: per_map = 0xC << 12; break;
- case CH_UART2_TX: per_map = 0xD << 12; break;
- case CH_UART3_RX: per_map = 0xE << 12; break;
- case CH_UART3_TX: per_map = 0xF << 12; break;
- default: return;
- }
-
- if (strncmp(device_id, "BFIN_UART", 9) == 0)
- dma_ch[channel].regs->peripheral_map = per_map;
-#endif
-}
-
-/**
- * request_dma - request a DMA channel
- *
- * Request the specific DMA channel from the system if it's available.
- */
-int request_dma(unsigned int channel, const char *device_id)
-{
- pr_debug("request_dma() : BEGIN\n");
-
- if (device_id == NULL)
- printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel);
-
-#if defined(CONFIG_BF561) && ANOMALY_05000182
- if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) {
- if (get_cclk() > 500000000) {
- printk(KERN_WARNING
- "Request IMDMA failed due to ANOMALY 05000182\n");
- return -EFAULT;
- }
- }
-#endif
-
- if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
- pr_debug("DMA CHANNEL IN USE\n");
- return -EBUSY;
- }
-
- set_dma_peripheral_map(channel, device_id);
- dma_ch[channel].device_id = device_id;
- dma_ch[channel].irq = 0;
-
- /* This is to be enabled by putting a restriction -
- * you have to request DMA, before doing any operations on
- * descriptor/channel
- */
- pr_debug("request_dma() : END\n");
- return 0;
-}
-EXPORT_SYMBOL(request_dma);
-
-int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
-{
- int ret;
- unsigned int irq;
-
- BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
- !atomic_read(&dma_ch[channel].chan_status));
-
- irq = channel2irq(channel);
- ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
- if (ret)
- return ret;
-
- dma_ch[channel].irq = irq;
- dma_ch[channel].data = data;
-
- return 0;
-}
-EXPORT_SYMBOL(set_dma_callback);
-
-/**
- * clear_dma_buffer - clear DMA fifos for specified channel
- *
- * Set the Buffer Clear bit in the Configuration register of specific DMA
- * channel. This will stop the descriptor based DMA operation.
- */
-static void clear_dma_buffer(unsigned int channel)
-{
- dma_ch[channel].regs->cfg |= RESTART;
- SSYNC();
- dma_ch[channel].regs->cfg &= ~RESTART;
-}
-
-void free_dma(unsigned int channel)
-{
- pr_debug("freedma() : BEGIN\n");
- BUG_ON(channel >= MAX_DMA_CHANNELS ||
- !atomic_read(&dma_ch[channel].chan_status));
-
- /* Halt the DMA */
- disable_dma(channel);
- clear_dma_buffer(channel);
-
- if (dma_ch[channel].irq)
- free_irq(dma_ch[channel].irq, dma_ch[channel].data);
-
- /* Clear the DMA Variable in the Channel */
- atomic_set(&dma_ch[channel].chan_status, 0);
-
- pr_debug("freedma() : END\n");
-}
-EXPORT_SYMBOL(free_dma);
-
-#ifdef CONFIG_PM
-# ifndef MAX_DMA_SUSPEND_CHANNELS
-# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
-# endif
-# ifndef CONFIG_BF60x
-int blackfin_dma_suspend(void)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- if (dma_ch[i].regs->cfg & DMAEN) {
- printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
- return -EBUSY;
- }
- if (i < MAX_DMA_SUSPEND_CHANNELS)
- dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
- }
-
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0);
-#endif
- return 0;
-}
-
-void blackfin_dma_resume(void)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- dma_ch[i].regs->cfg = 0;
- if (i < MAX_DMA_SUSPEND_CHANNELS)
- dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
- }
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0111);
-#endif
-}
-# else
-int blackfin_dma_suspend(void)
-{
- return 0;
-}
-
-void blackfin_dma_resume(void)
-{
-}
-#endif
-#endif
-
-/**
- * blackfin_dma_early_init - minimal DMA init
- *
- * Setup a few DMA registers so we can safely do DMA transfers early on in
- * the kernel booting process. Really this just means using dma_memcpy().
- */
-void __init blackfin_dma_early_init(void)
-{
- early_shadow_stamp();
- bfin_write_MDMA_S0_CONFIG(0);
- bfin_write_MDMA_S1_CONFIG(0);
-}
-
-void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
- struct dma_register *dst_ch, *src_ch;
-
- early_shadow_stamp();
-
- /* We assume that everything is 4 byte aligned, so include
- * a basic sanity check
- */
- BUG_ON(dst % 4);
- BUG_ON(src % 4);
- BUG_ON(size % 4);
-
- src_ch = 0;
- /* Find an avalible memDMA channel */
- while (1) {
- if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
- dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
- src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
- } else {
- dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
- src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
- }
-
- if (!DMA_MMR_READ(&src_ch->cfg))
- break;
- else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
- DMA_MMR_WRITE(&src_ch->cfg, 0);
- break;
- }
- }
-
- /* Force a sync in case a previous config reset on this channel
- * occurred. This is needed so subsequent writes to DMA registers
- * are not spuriously lost/corrupted.
- */
- __builtin_bfin_ssync();
-
- /* Destination */
- bfin_write32(&dst_ch->start_addr, dst);
- DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
- DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
- DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
-
- /* Source */
- bfin_write32(&src_ch->start_addr, src);
- DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
- DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
- DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
-
- /* Enable */
- DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
- DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
-
- /* Since we are atomic now, don't use the workaround ssync */
- __builtin_bfin_ssync();
-
-#ifdef CONFIG_BF60x
- /* Work around a possible MDMA anomaly. Running 2 MDMA channels to
- * transfer DDR data to L1 SRAM may corrupt data.
- * Should be reverted after this issue is root caused.
- */
- while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
- continue;
-#endif
-}
-
-void __init early_dma_memcpy_done(void)
-{
- early_shadow_stamp();
-
- while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) ||
- (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE)))
- continue;
-
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
- bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR);
- /*
- * Now that DMA is done, we would normally flush cache, but
- * i/d cache isn't running this early, so we don't bother,
- * and just clear out the DMA channel for next time
- */
- bfin_write_MDMA_S0_CONFIG(0);
- bfin_write_MDMA_S1_CONFIG(0);
- bfin_write_MDMA_D0_CONFIG(0);
- bfin_write_MDMA_D1_CONFIG(0);
-
- __builtin_bfin_ssync();
-}
-
-#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
-#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
-#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
-#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
-#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
-#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
-#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
-#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
-#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
-#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
-#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
-#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
-#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
-#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
-#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
-#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
-#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
-#else
-#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
-#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
-#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
-#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
-#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
-#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
-#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
-#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
-#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
-#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
-#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
-#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
-#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
-#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
-#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
-#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
-#endif
-
-/**
- * __dma_memcpy - program the MDMA registers
- *
- * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs
- * while programming registers so that everything is fully configured. Wait
- * for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE
- * check will make sure we don't clobber any existing transfer.
- */
-static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf)
-{
- static DEFINE_SPINLOCK(mdma_lock);
- unsigned long flags;
-
- spin_lock_irqsave(&mdma_lock, flags);
-
- /* Force a sync in case a previous config reset on this channel
- * occurred. This is needed so subsequent writes to DMA registers
- * are not spuriously lost/corrupted. Do it under irq lock and
- * without the anomaly version (because we are atomic already).
- */
- __builtin_bfin_ssync();
-
- if (bfin_read_MDMA_S_CONFIG())
- while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
- continue;
-
- if (conf & DMA2D) {
- /* For larger bit sizes, we've already divided down cnt so it
- * is no longer a multiple of 64k. So we have to break down
- * the limit here so it is a multiple of the incoming size.
- * There is no limitation here in terms of total size other
- * than the hardware though as the bits lost in the shift are
- * made up by MODIFY (== we can hit the whole address space).
- * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4
- */
- u32 shift = abs(dmod) >> 1;
- size_t ycnt = cnt >> (16 - shift);
- cnt = 1 << (16 - shift);
- bfin_write_MDMA_D_Y_COUNT(ycnt);
- bfin_write_MDMA_S_Y_COUNT(ycnt);
- bfin_write_MDMA_D_Y_MODIFY(dmod);
- bfin_write_MDMA_S_Y_MODIFY(smod);
- }
-
- bfin_write_MDMA_D_START_ADDR(daddr);
- bfin_write_MDMA_D_X_COUNT(cnt);
- bfin_write_MDMA_D_X_MODIFY(dmod);
- bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_START_ADDR(saddr);
- bfin_write_MDMA_S_X_COUNT(cnt);
- bfin_write_MDMA_S_X_MODIFY(smod);
- bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_CONFIG(DMAEN | conf);
- if (conf & DMA2D)
- bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
- else
- bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
-
- spin_unlock_irqrestore(&mdma_lock, flags);
-
- SSYNC();
-
- while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
- if (bfin_read_MDMA_S_CONFIG())
- continue;
- else
- return;
-
- bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_CONFIG(0);
- bfin_write_MDMA_D_CONFIG(0);
-}
-
-/**
- * _dma_memcpy - translate C memcpy settings into MDMA settings
- *
- * Handle all the high level steps before we touch the MDMA registers. So
- * handle direction, tweaking of sizes, and formatting of addresses.
- */
-static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- u32 conf, shift;
- s16 mod;
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
-
- if (size == 0)
- return NULL;
-
- if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) {
- conf = WDSIZE_32;
- shift = 2;
- } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) {
- conf = WDSIZE_16;
- shift = 1;
- } else {
- conf = WDSIZE_8;
- shift = 0;
- }
-
- /* If the two memory regions have a chance of overlapping, make
- * sure the memcpy still works as expected. Do this by having the
- * copy run backwards instead.
- */
- mod = 1 << shift;
- if (src < dst) {
- mod *= -1;
- dst += size + mod;
- src += size + mod;
- }
- size >>= shift;
-
-#ifndef DMA_MMR_SIZE_32
- if (size > 0x10000)
- conf |= DMA2D;
-#endif
-
- __dma_memcpy(dst, mod, src, mod, size, conf);
-
- return pdst;
-}
-
-/**
- * dma_memcpy - DMA memcpy under mutex lock
- *
- * Do not check arguments before starting the DMA memcpy. Break the transfer
- * up into two pieces. The first transfer is in multiples of 64k and the
- * second transfer is the piece smaller than 64k.
- */
-void *dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
-
- if (bfin_addr_dcacheable(src))
- blackfin_dcache_flush_range(src, src + size);
-
- if (bfin_addr_dcacheable(dst))
- blackfin_dcache_invalidate_range(dst, dst + size);
-
- return dma_memcpy_nocache(pdst, psrc, size);
-}
-EXPORT_SYMBOL(dma_memcpy);
-
-/**
- * dma_memcpy_nocache - DMA memcpy under mutex lock
- * - No cache flush/invalidate
- *
- * Do not check arguments before starting the DMA memcpy. Break the transfer
- * up into two pieces. The first transfer is in multiples of 64k and the
- * second transfer is the piece smaller than 64k.
- */
-void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
-{
-#ifdef DMA_MMR_SIZE_32
- _dma_memcpy(pdst, psrc, size);
-#else
- size_t bulk, rest;
-
- bulk = size & ~0xffff;
- rest = size - bulk;
- if (bulk)
- _dma_memcpy(pdst, psrc, bulk);
- _dma_memcpy(pdst + bulk, psrc + bulk, rest);
-#endif
- return pdst;
-}
-EXPORT_SYMBOL(dma_memcpy_nocache);
-
-/**
- * safe_dma_memcpy - DMA memcpy w/argument checking
- *
- * Verify arguments are safe before heading to dma_memcpy().
- */
-void *safe_dma_memcpy(void *dst, const void *src, size_t size)
-{
- if (!access_ok(VERIFY_WRITE, dst, size))
- return NULL;
- if (!access_ok(VERIFY_READ, src, size))
- return NULL;
- return dma_memcpy(dst, src, size);
-}
-EXPORT_SYMBOL(safe_dma_memcpy);
-
-static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
- u16 size, u16 dma_size)
-{
- blackfin_dcache_flush_range(buf, buf + len * size);
- __dma_memcpy(addr, 0, buf, size, len, dma_size);
-}
-
-static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
- u16 size, u16 dma_size)
-{
- blackfin_dcache_invalidate_range(buf, buf + len * size);
- __dma_memcpy(buf, size, addr, 0, len, dma_size);
-}
-
-#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
-void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
-{ \
- _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
-} \
-EXPORT_SYMBOL(dma_##io##s##bwl)
-MAKE_DMA_IO(out, b, 1, 8, const);
-MAKE_DMA_IO(in, b, 1, 8, );
-MAKE_DMA_IO(out, w, 2, 16, const);
-MAKE_DMA_IO(in, w, 2, 16, );
-MAKE_DMA_IO(out, l, 4, 32, const);
-MAKE_DMA_IO(in, l, 4, 32, );
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
deleted file mode 100644
index 63da80b..0000000
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ /dev/null
@@ -1,1208 +0,0 @@
-/*
- * GPIO Abstraction Layer
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/gpio/driver.h>
-/* FIXME: consumer API required for gpio_set_value() etc, get rid of this */
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <asm/gpio.h>
-#include <asm/irq_handler.h>
-#include <asm/portmux.h>
-
-#if ANOMALY_05000311 || ANOMALY_05000323
-enum {
- AWA_data = SYSCR,
- AWA_data_clear = SYSCR,
- AWA_data_set = SYSCR,
- AWA_toggle = SYSCR,
- AWA_maska = BFIN_UART_SCR,
- AWA_maska_clear = BFIN_UART_SCR,
- AWA_maska_set = BFIN_UART_SCR,
- AWA_maska_toggle = BFIN_UART_SCR,
- AWA_maskb = BFIN_UART_GCTL,
- AWA_maskb_clear = BFIN_UART_GCTL,
- AWA_maskb_set = BFIN_UART_GCTL,
- AWA_maskb_toggle = BFIN_UART_GCTL,
- AWA_dir = SPORT1_STAT,
- AWA_polar = SPORT1_STAT,
- AWA_edge = SPORT1_STAT,
- AWA_both = SPORT1_STAT,
-#if ANOMALY_05000311
- AWA_inen = TIMER_ENABLE,
-#elif ANOMALY_05000323
- AWA_inen = DMA1_1_CONFIG,
-#endif
-};
- /* Anomaly Workaround */
-#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
-#else
-#define AWA_DUMMY_READ(...) do { } while (0)
-#endif
-
-static struct gpio_port_t * const gpio_array[] = {
-#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
- (struct gpio_port_t *) FIO_FLAG_D,
-#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- (struct gpio_port_t *) PORTFIO,
- (struct gpio_port_t *) PORTGIO,
- (struct gpio_port_t *) PORTHIO,
-#elif defined(BF561_FAMILY)
- (struct gpio_port_t *) FIO0_FLAG_D,
- (struct gpio_port_t *) FIO1_FLAG_D,
- (struct gpio_port_t *) FIO2_FLAG_D,
-#else
-# error no gpio arrays defined
-#endif
-};
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
-static unsigned short * const port_fer[] = {
- (unsigned short *) PORTF_FER,
- (unsigned short *) PORTG_FER,
- (unsigned short *) PORTH_FER,
-};
-
-# if !defined(BF537_FAMILY)
-static unsigned short * const port_mux[] = {
- (unsigned short *) PORTF_MUX,
- (unsigned short *) PORTG_MUX,
- (unsigned short *) PORTH_MUX,
-};
-
-static const
-u8 pmux_offset[][16] = {
-# if defined(CONFIG_BF52x)
- { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
- { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
- { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
-# elif defined(CONFIG_BF51x)
- { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
- { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
- { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
-# endif
-};
-# endif
-
-#elif defined(BF538_FAMILY)
-static unsigned short * const port_fer[] = {
- (unsigned short *) PORTCIO_FER,
- (unsigned short *) PORTDIO_FER,
- (unsigned short *) PORTEIO_FER,
-};
-#endif
-
-#define RESOURCE_LABEL_SIZE 16
-
-static struct str_ident {
- char name[RESOURCE_LABEL_SIZE];
-} str_ident[MAX_RESOURCES];
-
-#if defined(CONFIG_PM)
-static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
-# ifdef BF538_FAMILY
-static unsigned short port_fer_saved[3];
-# endif
-#endif
-
-static void gpio_error(unsigned gpio)
-{
- printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
-}
-
-static void set_label(unsigned short ident, const char *label)
-{
- if (label) {
- strncpy(str_ident[ident].name, label,
- RESOURCE_LABEL_SIZE);
- str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
- }
-}
-
-static char *get_label(unsigned short ident)
-{
- return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
-}
-
-static int cmp_label(unsigned short ident, const char *label)
-{
- if (label == NULL) {
- dump_stack();
- printk(KERN_ERR "Please provide none-null label\n");
- }
-
- if (label)
- return strcmp(str_ident[ident].name, label);
- else
- return -EINVAL;
-}
-
-#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)]
-#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
-#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i))
-#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i))
-#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
-
-DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
-DECLARE_RESERVED_MAP(peri, DIV_ROUND_UP(MAX_RESOURCES, GPIO_BANKSIZE));
-DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
-
-inline int check_gpio(unsigned gpio)
-{
- if (gpio >= MAX_BLACKFIN_GPIOS)
- return -EINVAL;
- return 0;
-}
-
-static void port_setup(unsigned gpio, unsigned short usage)
-{
-#if defined(BF538_FAMILY)
- /*
- * BF538/9 Port C,D and E are special.
- * Inverted PORT_FER polarity on CDE and no PORF_FER on F
- * Regular PORT F GPIOs are handled here, CDE are exclusively
- * managed by GPIOLIB
- */
-
- if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
- return;
-
- gpio -= MAX_BLACKFIN_GPIOS;
-
- if (usage == GPIO_USAGE)
- *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
- else
- *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- SSYNC();
- return;
-#endif
-
- if (check_gpio(gpio))
- return;
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- if (usage == GPIO_USAGE)
- *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- else
- *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
- SSYNC();
-#endif
-}
-
-#ifdef BF537_FAMILY
-static const s8 port_mux[] = {
- [GPIO_PF0] = 3,
- [GPIO_PF1] = 3,
- [GPIO_PF2] = 4,
- [GPIO_PF3] = 4,
- [GPIO_PF4] = 5,
- [GPIO_PF5] = 6,
- [GPIO_PF6] = 7,
- [GPIO_PF7] = 8,
- [GPIO_PF8 ... GPIO_PF15] = -1,
- [GPIO_PG0 ... GPIO_PG7] = -1,
- [GPIO_PG8] = 9,
- [GPIO_PG9] = 9,
- [GPIO_PG10] = 10,
- [GPIO_PG11] = 10,
- [GPIO_PG12] = 10,
- [GPIO_PG13] = 11,
- [GPIO_PG14] = 11,
- [GPIO_PG15] = 11,
- [GPIO_PH0 ... GPIO_PH15] = -1,
- [PORT_PJ0 ... PORT_PJ3] = -1,
- [PORT_PJ4] = 1,
- [PORT_PJ5] = 1,
- [PORT_PJ6 ... PORT_PJ9] = -1,
- [PORT_PJ10] = 0,
- [PORT_PJ11] = 0,
-};
-
-static int portmux_group_check(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- s8 offset = port_mux[ident];
- u16 m, pmux, pfunc, mask;
-
- if (offset < 0)
- return 0;
-
- pmux = bfin_read_PORT_MUX();
- for (m = 0; m < ARRAY_SIZE(port_mux); ++m) {
- if (m == ident)
- continue;
- if (port_mux[m] != offset)
- continue;
- if (!is_reserved(peri, m, 1))
- continue;
-
- if (offset == 1)
- mask = 3;
- else
- mask = 1;
-
- pfunc = (pmux >> offset) & mask;
- if (pfunc != (function & mask)) {
- pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
- ident, function, m, pfunc);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-static void portmux_setup(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- s8 offset = port_mux[ident];
- u16 pmux, mask;
-
- if (offset == -1)
- return;
-
- pmux = bfin_read_PORT_MUX();
- if (offset == 1)
- mask = 3;
- else
- mask = 1;
-
- pmux &= ~(mask << offset);
- pmux |= ((function & mask) << offset);
-
- bfin_write_PORT_MUX(pmux);
-}
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
-static int portmux_group_check(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
- u16 pin, gpiopin, pfunc;
-
- for (pin = 0; pin < GPIO_BANKSIZE; ++pin) {
- if (offset != pmux_offset[gpio_bank(ident)][pin])
- continue;
-
- gpiopin = gpio_bank(ident) * GPIO_BANKSIZE + pin;
- if (gpiopin == ident)
- continue;
- if (!is_reserved(peri, gpiopin, 1))
- continue;
-
- pfunc = *port_mux[gpio_bank(ident)];
- pfunc = (pfunc >> offset) & 3;
- if (pfunc != function) {
- pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
- ident, function, gpiopin, pfunc);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-inline void portmux_setup(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
- u16 pmux;
-
- pmux = *port_mux[gpio_bank(ident)];
- if (((pmux >> offset) & 3) == function)
- return;
- pmux &= ~(3 << offset);
- pmux |= (function & 3) << offset;
- *port_mux[gpio_bank(ident)] = pmux;
- SSYNC();
-}
-#else
-# define portmux_setup(...) do { } while (0)
-static int portmux_group_check(unsigned short per)
-{
- return 0;
-}
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-* to Blackfin processor General Purpose
-* Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-/* Set a specific bit */
-
-#define SET_GPIO(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- flags = hard_local_irq_save(); \
- if (arg) \
- gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
- else \
- gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
-} \
-EXPORT_SYMBOL(set_gpio_ ## name);
-
-SET_GPIO(dir) /* set_gpio_dir() */
-SET_GPIO(inen) /* set_gpio_inen() */
-SET_GPIO(polar) /* set_gpio_polar() */
-SET_GPIO(edge) /* set_gpio_edge() */
-SET_GPIO(both) /* set_gpio_both() */
-
-
-#define SET_GPIO_SC(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- if (arg) \
- gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
- else \
- gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
-} \
-EXPORT_SYMBOL(set_gpio_ ## name);
-
-SET_GPIO_SC(maska)
-SET_GPIO_SC(maskb)
-SET_GPIO_SC(data)
-
-void set_gpio_toggle(unsigned gpio)
-{
- unsigned long flags;
- if (ANOMALY_05000311 || ANOMALY_05000323)
- flags = hard_local_irq_save();
- gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
- if (ANOMALY_05000311 || ANOMALY_05000323) {
- AWA_DUMMY_READ(toggle);
- hard_local_irq_restore(flags);
- }
-}
-EXPORT_SYMBOL(set_gpio_toggle);
-
-
-/*Set current PORT date (16-bit word)*/
-
-#define SET_GPIO_P(name) \
-void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- gpio_array[gpio_bank(gpio)]->name = arg; \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
-} \
-EXPORT_SYMBOL(set_gpiop_ ## name);
-
-SET_GPIO_P(data)
-SET_GPIO_P(dir)
-SET_GPIO_P(inen)
-SET_GPIO_P(polar)
-SET_GPIO_P(edge)
-SET_GPIO_P(both)
-SET_GPIO_P(maska)
-SET_GPIO_P(maskb)
-
-/* Get a specific bit */
-#define GET_GPIO(name) \
-unsigned short get_gpio_ ## name(unsigned gpio) \
-{ \
- unsigned long flags; \
- unsigned short ret; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
- return ret; \
-} \
-EXPORT_SYMBOL(get_gpio_ ## name);
-
-GET_GPIO(data)
-GET_GPIO(dir)
-GET_GPIO(inen)
-GET_GPIO(polar)
-GET_GPIO(edge)
-GET_GPIO(both)
-GET_GPIO(maska)
-GET_GPIO(maskb)
-
-/*Get current PORT date (16-bit word)*/
-
-#define GET_GPIO_P(name) \
-unsigned short get_gpiop_ ## name(unsigned gpio) \
-{ \
- unsigned long flags; \
- unsigned short ret; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- ret = (gpio_array[gpio_bank(gpio)]->name); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
- return ret; \
-} \
-EXPORT_SYMBOL(get_gpiop_ ## name);
-
-GET_GPIO_P(data)
-GET_GPIO_P(dir)
-GET_GPIO_P(inen)
-GET_GPIO_P(polar)
-GET_GPIO_P(edge)
-GET_GPIO_P(both)
-GET_GPIO_P(maska)
-GET_GPIO_P(maskb)
-
-
-#ifdef CONFIG_PM
-DECLARE_RESERVED_MAP(wakeup, GPIO_BANK_NUM);
-
-static const unsigned int sic_iwr_irqs[] = {
-#if defined(BF533_FAMILY)
- IRQ_PROG_INTB
-#elif defined(BF537_FAMILY)
- IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX
-#elif defined(BF538_FAMILY)
- IRQ_PORTF_INTB
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB
-#elif defined(BF561_FAMILY)
- IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB
-#else
-# error no SIC_IWR defined
-#endif
-};
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin PM Setup API
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-* type -
-* PM_WAKE_RISING
-* PM_WAKE_FALLING
-* PM_WAKE_HIGH
-* PM_WAKE_LOW
-* PM_WAKE_BOTH_EDGES
-*
-* DESCRIPTION: Blackfin PM Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
- if (ctrl)
- reserve(wakeup, gpio);
- else
- unreserve(wakeup, gpio);
-
- set_gpio_maskb(gpio, ctrl);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-
-int bfin_gpio_pm_standby_ctrl(unsigned ctrl)
-{
- u16 bank, mask, i;
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- mask = map_entry(wakeup, i);
- bank = gpio_bank(i);
-
- if (mask)
- bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl);
- }
- return 0;
-}
-
-void bfin_gpio_pm_hibernate_suspend(void)
-{
- int i, bank;
-
-#ifdef BF538_FAMILY
- for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
- port_fer_saved[i] = *port_fer[i];
-#endif
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- bank = gpio_bank(i);
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- gpio_bank_saved[bank].fer = *port_fer[bank];
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- gpio_bank_saved[bank].mux = *port_mux[bank];
-#else
- if (bank == 0)
- gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
-#endif
-#endif
- gpio_bank_saved[bank].data = gpio_array[bank]->data;
- gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
- gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
- gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
- gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
- gpio_bank_saved[bank].both = gpio_array[bank]->both;
- gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
- }
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
- bfin_special_gpio_pm_hibernate_suspend();
-#endif
-
- AWA_DUMMY_READ(maska);
-}
-
-void bfin_gpio_pm_hibernate_restore(void)
-{
- int i, bank;
-
-#ifdef BF538_FAMILY
- for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
- *port_fer[i] = port_fer_saved[i];
-#endif
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- bank = gpio_bank(i);
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- *port_mux[bank] = gpio_bank_saved[bank].mux;
-#else
- if (bank == 0)
- bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
-#endif
- *port_fer[bank] = gpio_bank_saved[bank].fer;
-#endif
- gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
- gpio_array[bank]->data_set = gpio_bank_saved[bank].data
- & gpio_bank_saved[bank].dir;
- gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
- gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
- gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
- gpio_array[bank]->both = gpio_bank_saved[bank].both;
- gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
- }
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
- bfin_special_gpio_pm_hibernate_restore();
-#endif
-
- AWA_DUMMY_READ(maska);
-}
-
-
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin Peripheral Resource Allocation
-* and PortMux Setup
-*
-* INPUTS/OUTPUTS:
-* per Peripheral Identifier
-* label String
-*
-* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int peripheral_request(unsigned short per, const char *label)
-{
- unsigned long flags;
- unsigned short ident = P_IDENT(per);
-
- /*
- * Don't cares are pins with only one dedicated function
- */
-
- if (per & P_DONTCARE)
- return 0;
-
- if (!(per & P_DEFINED))
- return -ENODEV;
-
- BUG_ON(ident >= MAX_RESOURCES);
-
- flags = hard_local_irq_save();
-
- /* If a pin can be muxed as either GPIO or peripheral, make
- * sure it is not already a GPIO pin when we request it.
- */
- if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "%s: Peripheral %d is already reserved as GPIO by %s !\n",
- __func__, ident, get_label(ident));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
-
- if (unlikely(is_reserved(peri, ident, 1))) {
-
- /*
- * Pin functions like AMC address strobes my
- * be requested and used by several drivers
- */
-
- if (!(per & P_MAYSHARE)) {
- /*
- * Allow that the identical pin function can
- * be requested from the same driver twice
- */
-
- if (cmp_label(ident, label) == 0)
- goto anyway;
-
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "%s: Peripheral %d function %d is already reserved by %s !\n",
- __func__, ident, P_FUNCT2MUX(per), get_label(ident));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- }
-
- if (unlikely(portmux_group_check(per))) {
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- anyway:
- reserve(peri, ident);
-
- portmux_setup(per);
- port_setup(ident, PERIPHERAL_USAGE);
-
- hard_local_irq_restore(flags);
- set_label(ident, label);
-
- return 0;
-}
-EXPORT_SYMBOL(peripheral_request);
-
-int peripheral_request_list(const unsigned short per[], const char *label)
-{
- u16 cnt;
- int ret;
-
- for (cnt = 0; per[cnt] != 0; cnt++) {
-
- ret = peripheral_request(per[cnt], label);
-
- if (ret < 0) {
- for ( ; cnt > 0; cnt--)
- peripheral_free(per[cnt - 1]);
-
- return ret;
- }
- }
-
- return 0;
-}
-EXPORT_SYMBOL(peripheral_request_list);
-
-void peripheral_free(unsigned short per)
-{
- unsigned long flags;
- unsigned short ident = P_IDENT(per);
-
- if (per & P_DONTCARE)
- return;
-
- if (!(per & P_DEFINED))
- return;
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(peri, ident, 0))) {
- hard_local_irq_restore(flags);
- return;
- }
-
- if (!(per & P_MAYSHARE))
- port_setup(ident, GPIO_USAGE);
-
- unreserve(peri, ident);
-
- set_label(ident, "free");
-
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(peripheral_free);
-
-void peripheral_free_list(const unsigned short per[])
-{
- u16 cnt;
- for (cnt = 0; per[cnt] != 0; cnt++)
- peripheral_free(per[cnt]);
-}
-EXPORT_SYMBOL(peripheral_free_list);
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
-* label String
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int bfin_gpio_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
-
- /*
- * Allow that the identical GPIO can
- * be requested from the same driver twice
- * Do nothing and return -
- */
-
- if (cmp_label(gpio, label) == 0) {
- hard_local_irq_restore(flags);
- return 0;
- }
-
- if (unlikely(is_reserved(gpio, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(peri, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
- printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
- " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
- } else { /* Reset POLAR setting when acquiring a gpio for the first time */
- set_gpio_polar(gpio, 0);
- }
-
- reserve(gpio, gpio);
- set_label(gpio, label);
-
- hard_local_irq_restore(flags);
-
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_request);
-
-void bfin_gpio_free(unsigned gpio)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return;
-
- might_sleep();
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(gpio, gpio);
-
- set_label(gpio, "free");
-
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(bfin_gpio_free);
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
-DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
-
-int bfin_special_gpio_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- flags = hard_local_irq_save();
-
- /*
- * Allow that the identical GPIO can
- * be requested from the same driver twice
- * Do nothing and return -
- */
-
- if (cmp_label(gpio, label) == 0) {
- hard_local_irq_restore(flags);
- return 0;
- }
-
- if (unlikely(is_reserved(special_gpio, gpio, 1))) {
- hard_local_irq_restore(flags);
- printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
- gpio, get_label(gpio));
-
- return -EBUSY;
- }
- if (unlikely(is_reserved(peri, gpio, 1))) {
- hard_local_irq_restore(flags);
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
-
- return -EBUSY;
- }
-
- reserve(special_gpio, gpio);
- reserve(peri, gpio);
-
- set_label(gpio, label);
- hard_local_irq_restore(flags);
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_special_gpio_request);
-
-void bfin_special_gpio_free(unsigned gpio)
-{
- unsigned long flags;
-
- might_sleep();
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(special_gpio, gpio);
- unreserve(peri, gpio);
- set_label(gpio, "free");
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(bfin_special_gpio_free);
-#endif
-
-
-int bfin_gpio_irq_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
-
- if (unlikely(is_reserved(peri, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(gpio, gpio, 1)))
- printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
- "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
- gpio, get_label(gpio));
-
- reserve(gpio_irq, gpio);
- set_label(gpio, label);
-
- hard_local_irq_restore(flags);
-
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-
-void bfin_gpio_irq_free(unsigned gpio)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return;
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(gpio_irq, gpio, 0))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(gpio_irq, gpio);
-
- set_label(gpio, "free");
-
- hard_local_irq_restore(flags);
-}
-
-static inline void __bfin_gpio_direction_input(unsigned gpio)
-{
- gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
- gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
-}
-
-int bfin_gpio_direction_input(unsigned gpio)
-{
- unsigned long flags;
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- gpio_error(gpio);
- return -EINVAL;
- }
-
- flags = hard_local_irq_save();
- __bfin_gpio_direction_input(gpio);
- AWA_DUMMY_READ(inen);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_direction_input);
-
-void bfin_gpio_irq_prepare(unsigned gpio)
-{
- port_setup(gpio, GPIO_USAGE);
-}
-
-void bfin_gpio_set_value(unsigned gpio, int arg)
-{
- if (arg)
- gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
- else
- gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
-}
-EXPORT_SYMBOL(bfin_gpio_set_value);
-
-int bfin_gpio_direction_output(unsigned gpio, int value)
-{
- unsigned long flags;
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- gpio_error(gpio);
- return -EINVAL;
- }
-
- flags = hard_local_irq_save();
-
- gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
- gpio_set_value(gpio, value);
- gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
-
- AWA_DUMMY_READ(dir);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_direction_output);
-
-int bfin_gpio_get_value(unsigned gpio)
-{
- unsigned long flags;
-
- if (unlikely(get_gpio_edge(gpio))) {
- int ret;
- flags = hard_local_irq_save();
- set_gpio_edge(gpio, 0);
- ret = get_gpio_data(gpio);
- set_gpio_edge(gpio, 1);
- hard_local_irq_restore(flags);
- return ret;
- } else
- return get_gpio_data(gpio);
-}
-EXPORT_SYMBOL(bfin_gpio_get_value);
-
-/* If we are booting from SPI and our board lacks a strong enough pull up,
- * the core can reset and execute the bootrom faster than the resistor can
- * pull the signal logically high. To work around this (common) error in
- * board design, we explicitly set the pin back to GPIO mode, force /CS
- * high, and wait for the electrons to do their thing.
- *
- * This function only makes sense to be called from reset code, but it
- * lives here as we need to force all the GPIO states w/out going through
- * BUG() checks and such.
- */
-void bfin_reset_boot_spi_cs(unsigned short pin)
-{
- unsigned short gpio = P_IDENT(pin);
- port_setup(gpio, GPIO_USAGE);
- gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
- AWA_DUMMY_READ(data_set);
- udelay(1);
-}
-
-#if defined(CONFIG_PROC_FS)
-static int gpio_proc_show(struct seq_file *m, void *v)
-{
- int c, irq, gpio;
-
- for (c = 0; c < MAX_RESOURCES; c++) {
- irq = is_reserved(gpio_irq, c, 1);
- gpio = is_reserved(gpio, c, 1);
- if (!check_gpio(c) && (gpio || irq))
- seq_printf(m, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
- get_label(c), (gpio && irq) ? " *" : "",
- get_gpio_dir(c) ? "OUTPUT" : "INPUT");
- else if (is_reserved(peri, c, 1))
- seq_printf(m, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
- else
- continue;
- }
-
- return 0;
-}
-
-static int gpio_proc_open(struct inode *inode, struct file *file)
-{
- return single_open(file, gpio_proc_show, NULL);
-}
-
-static const struct file_operations gpio_proc_ops = {
- .open = gpio_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static __init int gpio_register_proc(void)
-{
- struct proc_dir_entry *proc_gpio;
-
- proc_gpio = proc_create("gpio", 0, NULL, &gpio_proc_ops);
- return proc_gpio == NULL;
-}
-__initcall(gpio_register_proc);
-#endif
-
-#ifdef CONFIG_GPIOLIB
-static int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_direction_input(gpio);
-}
-
-static int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
-{
- return bfin_gpio_direction_output(gpio, level);
-}
-
-static int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- return !!bfin_gpio_get_value(gpio);
-}
-
-static void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- return bfin_gpio_set_value(gpio, value);
-}
-
-static int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_request(gpio, chip->label);
-}
-
-static void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_free(gpio);
-}
-
-static int bfin_gpiolib_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-{
- return gpio + GPIO_IRQ_BASE;
-}
-
-static struct gpio_chip bfin_chip = {
- .label = "BFIN-GPIO",
- .direction_input = bfin_gpiolib_direction_input,
- .get = bfin_gpiolib_get_value,
- .direction_output = bfin_gpiolib_direction_output,
- .set = bfin_gpiolib_set_value,
- .request = bfin_gpiolib_gpio_request,
- .free = bfin_gpiolib_gpio_free,
- .to_irq = bfin_gpiolib_gpio_to_irq,
- .base = 0,
- .ngpio = MAX_BLACKFIN_GPIOS,
-};
-
-static int __init bfin_gpiolib_setup(void)
-{
- return gpiochip_add_data(&bfin_chip, NULL);
-}
-arch_initcall(bfin_gpiolib_setup);
-#endif
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
deleted file mode 100644
index 68096e8..0000000
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * arch/blackfin/kernel/bfin_ksyms.c - exports for random symbols
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/uaccess.h>
-
-#include <asm/cacheflush.h>
-#include <asm/io.h>
-#include <asm/irq_handler.h>
-
-/* Allow people to have their own Blackfin exception handler in a module */
-EXPORT_SYMBOL(bfin_return_from_exception);
-
-/* All the Blackfin cache functions: mach-common/cache.S */
-EXPORT_SYMBOL(blackfin_dcache_invalidate_range);
-EXPORT_SYMBOL(blackfin_icache_flush_range);
-EXPORT_SYMBOL(blackfin_dcache_flush_range);
-EXPORT_SYMBOL(blackfin_dflush_page);
-
-/* The following are special because they're not called
- * explicitly (the C compiler generates them). Fortunately,
- * their interface isn't gonna change any time soon now, so
- * it's OK to leave it out of version control.
- */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-EXPORT_SYMBOL(memcmp);
-EXPORT_SYMBOL(memmove);
-EXPORT_SYMBOL(memchr);
-
-/*
- * Because string functions are both inline and exported functions and
- * folder arch/blackfin/lib is configured as a library path in Makefile,
- * symbols exported in folder lib is not linked into built-in.o but
- * inlined only. In order to export string symbols to kernel module
- * properly, they should be exported here.
- */
-EXPORT_SYMBOL(strcpy);
-EXPORT_SYMBOL(strncpy);
-EXPORT_SYMBOL(strcmp);
-EXPORT_SYMBOL(strncmp);
-
-/*
- * libgcc functions - functions that are used internally by the
- * compiler... (prototypes are not correct though, but that
- * doesn't really matter since they're not versioned).
- */
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __smulsi3_highpart(void);
-extern void __umulsi3_highpart(void);
-extern void __divsi3(void);
-extern void __lshrdi3(void);
-extern void __modsi3(void);
-extern void __muldi3(void);
-extern void __udivsi3(void);
-extern void __umodsi3(void);
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__umulsi3_highpart);
-EXPORT_SYMBOL(__smulsi3_highpart);
-EXPORT_SYMBOL(__divsi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__modsi3);
-EXPORT_SYMBOL(__muldi3);
-EXPORT_SYMBOL(__udivsi3);
-EXPORT_SYMBOL(__umodsi3);
-
-/* Input/output symbols: lib/{in,out}s.S */
-EXPORT_SYMBOL(outsb);
-EXPORT_SYMBOL(insb);
-EXPORT_SYMBOL(outsw);
-EXPORT_SYMBOL(outsw_8);
-EXPORT_SYMBOL(insw);
-EXPORT_SYMBOL(insw_8);
-EXPORT_SYMBOL(outsl);
-EXPORT_SYMBOL(insl);
-EXPORT_SYMBOL(insl_16);
-
-#ifdef CONFIG_SMP
-EXPORT_SYMBOL(__raw_atomic_add_asm);
-EXPORT_SYMBOL(__raw_atomic_xadd_asm);
-EXPORT_SYMBOL(__raw_atomic_and_asm);
-EXPORT_SYMBOL(__raw_atomic_or_asm);
-EXPORT_SYMBOL(__raw_atomic_xor_asm);
-EXPORT_SYMBOL(__raw_atomic_test_asm);
-
-EXPORT_SYMBOL(__raw_xchg_1_asm);
-EXPORT_SYMBOL(__raw_xchg_2_asm);
-EXPORT_SYMBOL(__raw_xchg_4_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_1_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_2_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_4_asm);
-EXPORT_SYMBOL(__raw_spin_is_locked_asm);
-EXPORT_SYMBOL(__raw_spin_lock_asm);
-EXPORT_SYMBOL(__raw_spin_trylock_asm);
-EXPORT_SYMBOL(__raw_spin_unlock_asm);
-EXPORT_SYMBOL(__raw_read_lock_asm);
-EXPORT_SYMBOL(__raw_read_trylock_asm);
-EXPORT_SYMBOL(__raw_read_unlock_asm);
-EXPORT_SYMBOL(__raw_write_lock_asm);
-EXPORT_SYMBOL(__raw_write_trylock_asm);
-EXPORT_SYMBOL(__raw_write_unlock_asm);
-EXPORT_SYMBOL(__raw_bit_set_asm);
-EXPORT_SYMBOL(__raw_bit_clear_asm);
-EXPORT_SYMBOL(__raw_bit_toggle_asm);
-EXPORT_SYMBOL(__raw_bit_test_asm);
-EXPORT_SYMBOL(__raw_bit_test_set_asm);
-EXPORT_SYMBOL(__raw_bit_test_clear_asm);
-EXPORT_SYMBOL(__raw_bit_test_toggle_asm);
-EXPORT_SYMBOL(__raw_uncached_fetch_asm);
-#ifdef __ARCH_SYNC_CORE_DCACHE
-EXPORT_SYMBOL(__raw_smp_mark_barrier_asm);
-EXPORT_SYMBOL(__raw_smp_check_barrier_asm);
-#endif
-#endif
-
-#ifdef CONFIG_FUNCTION_TRACER
-extern void _mcount(void);
-EXPORT_SYMBOL(_mcount);
-#endif
diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile
deleted file mode 100644
index 394d0b1..0000000
--- a/arch/blackfin/kernel/cplb-mpu/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# arch/blackfin/kernel/cplb-nompu/Makefile
-#
-
-obj-y := cplbinit.o cplbmgr.o
-
-CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
- -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
- -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
- -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
deleted file mode 100644
index c15fd05..0000000
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Blackfin CPLB initialization
- *
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mem_map.h>
-
-struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
-struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
-
-int first_switched_icplb, first_switched_dcplb;
-int first_mask_dcplb;
-
-void __init generate_cplb_tables_cpu(unsigned int cpu)
-{
- int i_d, i_i;
- unsigned long addr;
- unsigned long d_data, i_data;
- unsigned long d_cache = 0, i_cache = 0;
-
- printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
-
-#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-#endif
-
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- d_cache = CPLB_L1_CHBL;
-#ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_cache |= CPLB_L1_AOW | CPLB_WT;
-#endif
-#endif
-
- i_d = i_i = 0;
-
- /* Set up the zero page. */
- dcplb_tbl[cpu][i_d].addr = 0;
- dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
-
- icplb_tbl[cpu][i_i].addr = 0;
- icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
-
- /* Cover kernel memory with 4M pages. */
- addr = 0;
- d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
- i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
-
- for (; addr < memory_start; addr += 4 * 1024 * 1024) {
- dcplb_tbl[cpu][i_d].addr = addr;
- dcplb_tbl[cpu][i_d++].data = d_data;
- icplb_tbl[cpu][i_i].addr = addr;
- icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
- }
-
-#ifdef CONFIG_ROMKERNEL
- /* Cover kernel XIP flash area */
- addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
- dcplb_tbl[cpu][i_d].addr = addr;
- dcplb_tbl[cpu][i_d++].data = d_data | CPLB_USER_RD;
- icplb_tbl[cpu][i_i].addr = addr;
- icplb_tbl[cpu][i_i++].data = i_data | CPLB_USER_RD;
-#endif
-
- /* Cover L1 memory. One 4M area for code and data each is enough. */
-#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
- dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
- dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
-#endif
-#if L1_CODE_LENGTH > 0
- icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
- icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
-#endif
-
- /* Cover L2 memory */
-#if L2_LENGTH > 0
- dcplb_tbl[cpu][i_d].addr = L2_START;
- dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
- icplb_tbl[cpu][i_i].addr = L2_START;
- icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
-#endif
-
- first_mask_dcplb = i_d;
- first_switched_dcplb = i_d + (1 << page_mask_order);
- first_switched_icplb = i_i;
-
- while (i_d < MAX_CPLBS)
- dcplb_tbl[cpu][i_d++].data = 0;
- while (i_i < MAX_CPLBS)
- icplb_tbl[cpu][i_i++].data = 0;
-}
-
-void __init generate_cplb_tables_all(void)
-{
-}
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
deleted file mode 100644
index b56bd85..0000000
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * Blackfin CPLB exception handling for when MPU in on
- *
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/mm.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mmu_context.h>
-
-/*
- * WARNING
- *
- * This file is compiled with certain -ffixed-reg options. We have to
- * make sure not to call any functions here that could clobber these
- * registers.
- */
-
-int page_mask_nelts;
-int page_mask_order;
-unsigned long *current_rwx_mask[NR_CPUS];
-
-int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
-int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
-int nr_cplb_flush[NR_CPUS];
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-#define MGR_ATTR __attribute__((l1_text))
-#else
-#define MGR_ATTR
-#endif
-
-/*
- * Given the contents of the status register, return the index of the
- * CPLB that caused the fault.
- */
-static inline int faulting_cplb_index(int status)
-{
- int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
- return 30 - signbits;
-}
-
-/*
- * Given the contents of the status register and the DCPLB_DATA contents,
- * return true if a write access should be permitted.
- */
-static inline int write_permitted(int status, unsigned long data)
-{
- if (status & FAULT_USERSUPV)
- return !!(data & CPLB_SUPV_WR);
- else
- return !!(data & CPLB_USER_WR);
-}
-
-/* Counters to implement round-robin replacement. */
-static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
-
-/*
- * Find an ICPLB entry to be evicted and return its index.
- */
-MGR_ATTR static int evict_one_icplb(unsigned int cpu)
-{
- int i;
- for (i = first_switched_icplb; i < MAX_CPLBS; i++)
- if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
- return i;
- i = first_switched_icplb + icplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_icplb;
- icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
- }
- icplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static int evict_one_dcplb(unsigned int cpu)
-{
- int i;
- for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
- if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
- return i;
- i = first_switched_dcplb + dcplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_dcplb;
- dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
- }
- dcplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static noinline int dcplb_miss(unsigned int cpu)
-{
- unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
- int status = bfin_read_DCPLB_STATUS();
- unsigned long *mask;
- int idx;
- unsigned long d_data;
-
- nr_dcplb_miss[cpu]++;
-
- d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- if (bfin_addr_dcacheable(addr)) {
- d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_data |= CPLB_L1_AOW | CPLB_WT;
-# endif
- }
-#endif
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- d_data = L2_DMEMORY;
- } else if (addr >= physical_mem_end) {
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
-#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
- mask = current_rwx_mask[cpu];
- if (mask) {
- int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- if (mask[idx] & bit)
- d_data |= CPLB_USER_RD;
- }
-#endif
- } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
- && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
- addr &= ~(1 * 1024 * 1024 - 1);
- d_data &= ~PAGE_SIZE_4KB;
- d_data |= PAGE_SIZE_1MB;
- } else
- return CPLB_PROT_VIOL;
- } else if (addr >= _ramend) {
- d_data |= CPLB_USER_RD | CPLB_USER_WR;
- if (reserved_mem_dcache_on)
- d_data |= CPLB_L1_CHBL;
- } else {
- mask = current_rwx_mask[cpu];
- if (mask) {
- int page = addr >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- if (mask[idx] & bit)
- d_data |= CPLB_USER_RD;
-
- mask += page_mask_nelts;
- if (mask[idx] & bit)
- d_data |= CPLB_USER_WR;
- }
- }
- idx = evict_one_dcplb(cpu);
-
- addr &= PAGE_MASK;
- dcplb_tbl[cpu][idx].addr = addr;
- dcplb_tbl[cpu][idx].data = d_data;
-
- _disable_dcplb();
- bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
- bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
- _enable_dcplb();
-
- return 0;
-}
-
-MGR_ATTR static noinline int icplb_miss(unsigned int cpu)
-{
- unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
- int status = bfin_read_ICPLB_STATUS();
- int idx;
- unsigned long i_data;
-
- nr_icplb_miss[cpu]++;
-
- /* If inside the uncached DMA region, fault. */
- if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
- return CPLB_PROT_VIOL;
-
- if (status & FAULT_USERSUPV)
- nr_icplb_supv_miss[cpu]++;
-
- /*
- * First, try to find a CPLB that matches this address. If we
- * find one, then the fact that we're in the miss handler means
- * that the instruction crosses a page boundary.
- */
- for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
- if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
- unsigned long this_addr = icplb_tbl[cpu][idx].addr;
- if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
- addr += PAGE_SIZE;
- break;
- }
- }
- }
-
- i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
-
-#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- /*
- * Normal RAM, and possibly the reserved memory area, are
- * cacheable.
- */
- if (addr < _ramend ||
- (addr < physical_mem_end && reserved_mem_icache_on))
- i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-#endif
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- i_data = L2_IMEMORY;
- } else if (addr >= physical_mem_end) {
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
- if (!(status & FAULT_USERSUPV)) {
- unsigned long *mask = current_rwx_mask[cpu];
-
- if (mask) {
- int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- mask += 2 * page_mask_nelts;
- if (mask[idx] & bit)
- i_data |= CPLB_USER_RD;
- }
- }
- } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
- && (status & FAULT_USERSUPV)) {
- addr &= ~(1 * 1024 * 1024 - 1);
- i_data &= ~PAGE_SIZE_4KB;
- i_data |= PAGE_SIZE_1MB;
- } else
- return CPLB_PROT_VIOL;
- } else if (addr >= _ramend) {
- i_data |= CPLB_USER_RD;
- if (reserved_mem_icache_on)
- i_data |= CPLB_L1_CHBL;
- } else {
- /*
- * Two cases to distinguish - a supervisor access must
- * necessarily be for a module page; we grant it
- * unconditionally (could do better here in the future).
- * Otherwise, check the x bitmap of the current process.
- */
- if (!(status & FAULT_USERSUPV)) {
- unsigned long *mask = current_rwx_mask[cpu];
-
- if (mask) {
- int page = addr >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- mask += 2 * page_mask_nelts;
- if (mask[idx] & bit)
- i_data |= CPLB_USER_RD;
- }
- }
- }
- idx = evict_one_icplb(cpu);
- addr &= PAGE_MASK;
- icplb_tbl[cpu][idx].addr = addr;
- icplb_tbl[cpu][idx].data = i_data;
-
- _disable_icplb();
- bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
- bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
- _enable_icplb();
-
- return 0;
-}
-
-MGR_ATTR static noinline int dcplb_protection_fault(unsigned int cpu)
-{
- int status = bfin_read_DCPLB_STATUS();
-
- nr_dcplb_prot[cpu]++;
-
- if (status & FAULT_RW) {
- int idx = faulting_cplb_index(status);
- unsigned long data = dcplb_tbl[cpu][idx].data;
- if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
- write_permitted(status, data)) {
- data |= CPLB_DIRTY;
- dcplb_tbl[cpu][idx].data = data;
- bfin_write32(DCPLB_DATA0 + idx * 4, data);
- return 0;
- }
- }
- return CPLB_PROT_VIOL;
-}
-
-MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
-{
- int cause = seqstat & 0x3f;
- unsigned int cpu = raw_smp_processor_id();
- switch (cause) {
- case 0x23:
- return dcplb_protection_fault(cpu);
- case 0x2C:
- return icplb_miss(cpu);
- case 0x26:
- return dcplb_miss(cpu);
- default:
- return 1;
- }
-}
-
-void flush_switched_cplbs(unsigned int cpu)
-{
- int i;
- unsigned long flags;
-
- nr_cplb_flush[cpu]++;
-
- flags = hard_local_irq_save();
- _disable_icplb();
- for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
- icplb_tbl[cpu][i].data = 0;
- bfin_write32(ICPLB_DATA0 + i * 4, 0);
- }
- _enable_icplb();
-
- _disable_dcplb();
- for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
- dcplb_tbl[cpu][i].data = 0;
- bfin_write32(DCPLB_DATA0 + i * 4, 0);
- }
- _enable_dcplb();
- hard_local_irq_restore(flags);
-
-}
-
-void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
-{
- int i;
- unsigned long addr = (unsigned long)masks;
- unsigned long d_data;
- unsigned long flags;
-
- if (!masks) {
- current_rwx_mask[cpu] = masks;
- return;
- }
-
- flags = hard_local_irq_save();
- current_rwx_mask[cpu] = masks;
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- d_data = L2_DMEMORY;
- } else {
- d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- d_data |= CPLB_L1_CHBL;
-# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_data |= CPLB_L1_AOW | CPLB_WT;
-# endif
-#endif
- }
-
- _disable_dcplb();
- for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
- dcplb_tbl[cpu][i].addr = addr;
- dcplb_tbl[cpu][i].data = d_data;
- bfin_write32(DCPLB_DATA0 + i * 4, d_data);
- bfin_write32(DCPLB_ADDR0 + i * 4, addr);
- addr += PAGE_SIZE;
- }
- _enable_dcplb();
- hard_local_irq_restore(flags);
-}
diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile
deleted file mode 100644
index 81baa27..0000000
--- a/arch/blackfin/kernel/cplb-nompu/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/kernel/cplb-nompu/Makefile
-#
-
-obj-y := cplbinit.o cplbmgr.o
-
-CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
- -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
- -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
- -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
deleted file mode 100644
index b49a53b..0000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * Blackfin CPLB initialization
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mem_map.h>
-
-struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
-struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
-
-int first_switched_icplb PDT_ATTR;
-int first_switched_dcplb PDT_ATTR;
-
-struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
-struct cplb_boundary icplb_bounds[9] PDT_ATTR;
-
-int icplb_nr_bounds PDT_ATTR;
-int dcplb_nr_bounds PDT_ATTR;
-
-void __init generate_cplb_tables_cpu(unsigned int cpu)
-{
- int i_d, i_i;
- unsigned long addr;
- unsigned long cplb_pageflags, cplb_pagesize;
-
- struct cplb_entry *d_tbl = dcplb_tbl[cpu];
- struct cplb_entry *i_tbl = icplb_tbl[cpu];
-
- printk(KERN_INFO "NOMPU: setting up cplb tables\n");
-
- i_d = i_i = 0;
-
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- /* Set up the zero page. */
- d_tbl[i_d].addr = 0;
- d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
- i_tbl[i_i].addr = 0;
- i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
-#endif
-
- /* Cover kernel memory with 4M pages. */
- addr = 0;
-
-#ifdef PAGE_SIZE_16MB
- cplb_pageflags = PAGE_SIZE_16MB;
- cplb_pagesize = SIZE_16M;
-#else
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
-#endif
-
-
- for (; addr < memory_start; addr += cplb_pagesize) {
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;
- }
-
-#ifdef CONFIG_ROMKERNEL
- /* Cover kernel XIP flash area */
-#ifdef CONFIG_BF60x
- addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1);
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB;
-#else
- addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
-#endif
-#endif
-
- /* Cover L1 memory. One 4M area for code and data each is enough. */
- if (cpu == 0) {
- if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
- d_tbl[i_d].addr = L1_DATA_A_START;
- d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
- }
- i_tbl[i_i].addr = L1_CODE_START;
- i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
- }
-#ifdef CONFIG_SMP
- else {
- if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
- d_tbl[i_d].addr = COREB_L1_DATA_A_START;
- d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
- }
- i_tbl[i_i].addr = COREB_L1_CODE_START;
- i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
- }
-#endif
- first_switched_dcplb = i_d;
- first_switched_icplb = i_i;
-
- BUG_ON(first_switched_dcplb > MAX_CPLBS);
- BUG_ON(first_switched_icplb > MAX_CPLBS);
-
- while (i_d < MAX_CPLBS)
- d_tbl[i_d++].data = 0;
- while (i_i < MAX_CPLBS)
- i_tbl[i_i++].data = 0;
-}
-
-void __init generate_cplb_tables_all(void)
-{
- unsigned long uncached_end;
- int i_d, i_i;
-
- i_d = 0;
- /* Normal RAM, including MTD FS. */
-#ifdef CONFIG_MTD_UCLINUX
- uncached_end = memory_mtd_start + mtd_size;
-#else
- uncached_end = memory_end;
-#endif
- /*
- * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached
- * so that we don't have to use 4kB pages and cause CPLB thrashing
- */
- if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION ||
- ((_ramend - uncached_end) >= 1 * 1024 * 1024))
- dcplb_bounds[i_d].eaddr = uncached_end;
- else
- dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
- dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
- /* DMA uncached region. */
- if (DMA_UNCACHED_REGION) {
- dcplb_bounds[i_d].eaddr = _ramend;
- dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
- }
- if (_ramend != physical_mem_end) {
- /* Reserved memory. */
- dcplb_bounds[i_d].eaddr = physical_mem_end;
- dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
- SDRAM_DGENERIC : SDRAM_DNON_CHBL);
- }
- /* Addressing hole up to the async bank. */
- dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
- dcplb_bounds[i_d++].data = 0;
- /* ASYNC banks. */
- dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
- dcplb_bounds[i_d++].data = SDRAM_EBIU;
- /* Addressing hole up to BootROM. */
- dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
- dcplb_bounds[i_d++].data = 0;
- /* BootROM -- largest one should be less than 1 meg. */
- dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
- dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
- if (L2_LENGTH) {
- /* Addressing hole up to L2 SRAM. */
- dcplb_bounds[i_d].eaddr = L2_START;
- dcplb_bounds[i_d++].data = 0;
- /* L2 SRAM. */
- dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
- dcplb_bounds[i_d++].data = L2_DMEMORY;
- }
- dcplb_nr_bounds = i_d;
- BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));
-
- i_i = 0;
- /* Normal RAM, including MTD FS. */
- icplb_bounds[i_i].eaddr = uncached_end;
- icplb_bounds[i_i++].data = SDRAM_IGENERIC;
- if (_ramend != physical_mem_end) {
- /* DMA uncached region. */
- if (DMA_UNCACHED_REGION) {
- /* Normally this hole is caught by the async below. */
- icplb_bounds[i_i].eaddr = _ramend;
- icplb_bounds[i_i++].data = 0;
- }
- /* Reserved memory. */
- icplb_bounds[i_i].eaddr = physical_mem_end;
- icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
- SDRAM_IGENERIC : SDRAM_INON_CHBL);
- }
- /* Addressing hole up to the async bank. */
- icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
- icplb_bounds[i_i++].data = 0;
- /* ASYNC banks. */
- icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
- icplb_bounds[i_i++].data = SDRAM_EBIU;
- /* Addressing hole up to BootROM. */
- icplb_bounds[i_i].eaddr = BOOT_ROM_START;
- icplb_bounds[i_i++].data = 0;
- /* BootROM -- largest one should be less than 1 meg. */
- icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
- icplb_bounds[i_i++].data = SDRAM_IGENERIC;
-
- if (L2_LENGTH) {
- /* Addressing hole up to L2 SRAM. */
- icplb_bounds[i_i].eaddr = L2_START;
- icplb_bounds[i_i++].data = 0;
- /* L2 SRAM. */
- icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
- icplb_bounds[i_i++].data = L2_IMEMORY;
- }
- icplb_nr_bounds = i_i;
- BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds));
-}
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
deleted file mode 100644
index 79cc0f6..0000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Based on: arch/blackfin/kernel/cplb-mpu/cplbmgr.c
- * Author: Michael McTernan <mmcternan@airvana.com>
- *
- * Description: CPLB miss handler.
- *
- * Modified:
- * Copyright 2008 Airvana Inc.
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-#include <asm/cplb.h>
-#include <asm/mmu_context.h>
-#include <asm/traps.h>
-
-/*
- * WARNING
- *
- * This file is compiled with certain -ffixed-reg options. We have to
- * make sure not to call any functions here that could clobber these
- * registers.
- */
-
-int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
-int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS];
-int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS];
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-#define MGR_ATTR __attribute__((l1_text))
-#else
-#define MGR_ATTR
-#endif
-
-static inline void write_dcplb_data(int cpu, int idx, unsigned long data,
- unsigned long addr)
-{
- _disable_dcplb();
- bfin_write32(DCPLB_DATA0 + idx * 4, data);
- bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
- _enable_dcplb();
-
-#ifdef CONFIG_CPLB_INFO
- dcplb_tbl[cpu][idx].addr = addr;
- dcplb_tbl[cpu][idx].data = data;
-#endif
-}
-
-static inline void write_icplb_data(int cpu, int idx, unsigned long data,
- unsigned long addr)
-{
- _disable_icplb();
- bfin_write32(ICPLB_DATA0 + idx * 4, data);
- bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
- _enable_icplb();
-
-#ifdef CONFIG_CPLB_INFO
- icplb_tbl[cpu][idx].addr = addr;
- icplb_tbl[cpu][idx].data = data;
-#endif
-}
-
-/* Counters to implement round-robin replacement. */
-static int icplb_rr_index[NR_CPUS] PDT_ATTR;
-static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
-
-/*
- * Find an ICPLB entry to be evicted and return its index.
- */
-static int evict_one_icplb(int cpu)
-{
- int i = first_switched_icplb + icplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_icplb;
- icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
- }
- icplb_rr_index[cpu]++;
- return i;
-}
-
-static int evict_one_dcplb(int cpu)
-{
- int i = first_switched_dcplb + dcplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_dcplb;
- dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
- }
- dcplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static int icplb_miss(int cpu)
-{
- unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
- int status = bfin_read_ICPLB_STATUS();
- int idx;
- unsigned long i_data, base, addr1, eaddr;
-
- nr_icplb_miss[cpu]++;
- if (unlikely(status & FAULT_USERSUPV))
- nr_icplb_supv_miss[cpu]++;
-
- base = 0;
- idx = 0;
- do {
- eaddr = icplb_bounds[idx].eaddr;
- if (addr < eaddr)
- break;
- base = eaddr;
- } while (++idx < icplb_nr_bounds);
-
- if (unlikely(idx == icplb_nr_bounds))
- return CPLB_NO_ADDR_MATCH;
-
- i_data = icplb_bounds[idx].data;
- if (unlikely(i_data == 0))
- return CPLB_NO_ADDR_MATCH;
-
- addr1 = addr & ~(SIZE_4M - 1);
- addr &= ~(SIZE_1M - 1);
- i_data |= PAGE_SIZE_1MB;
- if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
- /*
- * This works because
- * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
- */
- i_data |= PAGE_SIZE_4MB;
- addr = addr1;
- }
-
- /* Pick entry to evict */
- idx = evict_one_icplb(cpu);
-
- write_icplb_data(cpu, idx, i_data, addr);
-
- return CPLB_RELOADED;
-}
-
-MGR_ATTR static int dcplb_miss(int cpu)
-{
- unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
- int status = bfin_read_DCPLB_STATUS();
- int idx;
- unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags;
-
- nr_dcplb_miss[cpu]++;
- if (unlikely(status & FAULT_USERSUPV))
- nr_dcplb_supv_miss[cpu]++;
-
- base = 0;
- idx = 0;
- do {
- eaddr = dcplb_bounds[idx].eaddr;
- if (addr < eaddr)
- break;
- base = eaddr;
- } while (++idx < dcplb_nr_bounds);
-
- if (unlikely(idx == dcplb_nr_bounds))
- return CPLB_NO_ADDR_MATCH;
-
- d_data = dcplb_bounds[idx].data;
- if (unlikely(d_data == 0))
- return CPLB_NO_ADDR_MATCH;
-
- addr &= ~(SIZE_1M - 1);
- d_data |= PAGE_SIZE_1MB;
-
- /* BF60x support large than 4M CPLB page size */
-#ifdef PAGE_SIZE_16MB
- cplb_pageflags = PAGE_SIZE_16MB;
- cplb_pagesize = SIZE_16M;
-#else
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
-#endif
-
-find_pagesize:
- addr1 = addr & ~(cplb_pagesize - 1);
- if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) {
- /*
- * This works because
- * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
- */
- d_data |= cplb_pageflags;
- addr = addr1;
- goto found_pagesize;
- } else {
- if (cplb_pagesize > SIZE_4M) {
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
- goto find_pagesize;
- }
- }
-
-found_pagesize:
-#ifdef CONFIG_BF60x
- if ((addr >= ASYNC_BANK0_BASE)
- && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
- d_data |= PAGE_SIZE_64MB;
-#endif
-
- /* Pick entry to evict */
- idx = evict_one_dcplb(cpu);
-
- write_dcplb_data(cpu, idx, d_data, addr);
-
- return CPLB_RELOADED;
-}
-
-MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
-{
- int cause = seqstat & 0x3f;
- unsigned int cpu = raw_smp_processor_id();
- switch (cause) {
- case VEC_CPLB_I_M:
- return icplb_miss(cpu);
- case VEC_CPLB_M:
- return dcplb_miss(cpu);
- default:
- return CPLB_UNKNOWN_ERR;
- }
-}
diff --git a/arch/blackfin/kernel/cplbinfo.c b/arch/blackfin/kernel/cplbinfo.c
deleted file mode 100644
index 5b80d59..0000000
--- a/arch/blackfin/kernel/cplbinfo.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * arch/blackfin/kernel/cplbinfo.c - display CPLB status
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ctype.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/uaccess.h>
-
-#include <asm/cplbinit.h>
-#include <asm/blackfin.h>
-
-static char const page_strtbl[][4] = {
- "1K", "4K", "1M", "4M",
-#ifdef CONFIG_BF60x
- "16K", "64K", "16M", "64M",
-#endif
-};
-#define page(flags) (((flags) & 0x70000) >> 16)
-#define strpage(flags) page_strtbl[page(flags)]
-
-struct cplbinfo_data {
- loff_t pos;
- char cplb_type;
- u32 mem_control;
- struct cplb_entry *tbl;
- int switched;
-};
-
-static void cplbinfo_print_header(struct seq_file *m)
-{
- seq_printf(m, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n");
-}
-
-static int cplbinfo_nomore(struct cplbinfo_data *cdata)
-{
- return cdata->pos >= MAX_CPLBS;
-}
-
-static int cplbinfo_show(struct seq_file *m, void *p)
-{
- struct cplbinfo_data *cdata;
- unsigned long data, addr;
- loff_t pos;
-
- cdata = p;
- pos = cdata->pos;
- addr = cdata->tbl[pos].addr;
- data = cdata->tbl[pos].data;
-
- seq_printf(m,
- "%d\t0x%08lx\t%05lx\t%s\t%c\t%c\t%c\t%c\n",
- (int)pos, addr, data, strpage(data),
- (data & CPLB_USER_RD) ? 'Y' : 'N',
- (data & CPLB_USER_WR) ? 'Y' : 'N',
- (data & CPLB_SUPV_WR) ? 'Y' : 'N',
- pos < cdata->switched ? 'N' : 'Y');
-
- return 0;
-}
-
-static void cplbinfo_seq_init(struct cplbinfo_data *cdata, unsigned int cpu)
-{
- if (cdata->cplb_type == 'I') {
- cdata->mem_control = bfin_read_IMEM_CONTROL();
- cdata->tbl = icplb_tbl[cpu];
- cdata->switched = first_switched_icplb;
- } else {
- cdata->mem_control = bfin_read_DMEM_CONTROL();
- cdata->tbl = dcplb_tbl[cpu];
- cdata->switched = first_switched_dcplb;
- }
-}
-
-static void *cplbinfo_start(struct seq_file *m, loff_t *pos)
-{
- struct cplbinfo_data *cdata = m->private;
-
- if (!*pos) {
- seq_printf(m, "%cCPLBs are %sabled: 0x%x\n", cdata->cplb_type,
- (cdata->mem_control & ENDCPLB ? "en" : "dis"),
- cdata->mem_control);
- cplbinfo_print_header(m);
- } else if (cplbinfo_nomore(cdata))
- return NULL;
-
- get_cpu();
- return cdata;
-}
-
-static void *cplbinfo_next(struct seq_file *m, void *p, loff_t *pos)
-{
- struct cplbinfo_data *cdata = p;
- cdata->pos = ++(*pos);
- if (cplbinfo_nomore(cdata))
- return NULL;
- else
- return cdata;
-}
-
-static void cplbinfo_stop(struct seq_file *m, void *p)
-{
- put_cpu();
-}
-
-static const struct seq_operations cplbinfo_sops = {
- .start = cplbinfo_start,
- .next = cplbinfo_next,
- .stop = cplbinfo_stop,
- .show = cplbinfo_show,
-};
-
-#define CPLBINFO_DCPLB_FLAG 0x80000000
-
-static int cplbinfo_open(struct inode *inode, struct file *file)
-{
- char cplb_type;
- unsigned int cpu = (unsigned long)PDE_DATA(file_inode(file));
- int ret;
- struct seq_file *m;
- struct cplbinfo_data *cdata;
-
- cplb_type = cpu & CPLBINFO_DCPLB_FLAG ? 'D' : 'I';
- cpu &= ~CPLBINFO_DCPLB_FLAG;
-
- if (!cpu_online(cpu))
- return -ENODEV;
-
- ret = seq_open_private(file, &cplbinfo_sops, sizeof(*cdata));
- if (ret)
- return ret;
- m = file->private_data;
- cdata = m->private;
-
- cdata->pos = 0;
- cdata->cplb_type = cplb_type;
- cplbinfo_seq_init(cdata, cpu);
-
- return 0;
-}
-
-static const struct file_operations cplbinfo_fops = {
- .open = cplbinfo_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = seq_release_private,
-};
-
-static int __init cplbinfo_init(void)
-{
- struct proc_dir_entry *cplb_dir, *cpu_dir;
- char buf[10];
- unsigned int cpu;
-
- cplb_dir = proc_mkdir("cplbinfo", NULL);
- if (!cplb_dir)
- return -ENOMEM;
-
- for_each_possible_cpu(cpu) {
- sprintf(buf, "cpu%i", cpu);
- cpu_dir = proc_mkdir(buf, cplb_dir);
- if (!cpu_dir)
- return -ENOMEM;
-
- proc_create_data("icplb", S_IRUGO, cpu_dir, &cplbinfo_fops,
- (void *)cpu);
- proc_create_data("dcplb", S_IRUGO, cpu_dir, &cplbinfo_fops,
- (void *)(cpu | CPLBINFO_DCPLB_FLAG));
- }
-
- return 0;
-}
-late_initcall(cplbinfo_init);
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
deleted file mode 100644
index 194773c..0000000
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ /dev/null
@@ -1,1891 +0,0 @@
-/*
- * debugfs interface to core/system MMRs
- *
- * Copyright 2007-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/debugfs.h>
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/gptimers.h>
-#include <asm/bfin_can.h>
-#include <asm/bfin_dma.h>
-#include <asm/bfin_ppi.h>
-#include <asm/bfin_serial.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_twi.h>
-#include <asm/gpio.h>
-
-/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
-#ifdef BFIN_PORT_MUX
-#undef PORT_MUX
-#define PORT_MUX BFIN_PORT_MUX
-#endif
-
-#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
-#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
-#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
-#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
-
-#define D_RO(name, bits) d_RO(#name, bits, name)
-#define D_WO(name, bits) d_WO(#name, bits, name)
-#define D32(name) d(#name, 32, name)
-#define D16(name) d(#name, 16, name)
-
-#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
-#define __REGS(peri, sname, rname) \
- do { \
- struct bfin_##peri##_regs r; \
- void *addr = (void *)(base + REGS_OFF(peri, rname)); \
- strcpy(_buf, sname); \
- if (sizeof(r.rname) == 2) \
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
- else \
- debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
- } while (0)
-#define REGS_STR_PFX(buf, pfx, num) \
- ({ \
- buf + (num >= 0 ? \
- sprintf(buf, #pfx "%i_", num) : \
- sprintf(buf, #pfx "_")); \
- })
-#define REGS_STR_PFX_C(buf, pfx, num) \
- ({ \
- buf + (num >= 0 ? \
- sprintf(buf, #pfx "%c_", 'A' + num) : \
- sprintf(buf, #pfx "_")); \
- })
-
-/*
- * Core registers (not memory mapped)
- */
-extern u32 last_seqstat;
-
-static int debug_cclk_get(void *data, u64 *val)
-{
- *val = get_cclk();
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
-
-static int debug_sclk_get(void *data, u64 *val)
-{
- *val = get_sclk();
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
-
-#define DEFINE_SYSREG(sr, pre, post) \
-static int sysreg_##sr##_get(void *data, u64 *val) \
-{ \
- unsigned long tmp; \
- pre; \
- __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
- *val = tmp; \
- return 0; \
-} \
-static int sysreg_##sr##_set(void *data, u64 val) \
-{ \
- unsigned long tmp = val; \
- __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
- post; \
- return 0; \
-} \
-DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
-
-DEFINE_SYSREG(cycles, , );
-DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
-DEFINE_SYSREG(emudat, , );
-DEFINE_SYSREG(seqstat, , );
-DEFINE_SYSREG(syscfg, , CSYNC());
-#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
-
-#ifndef CONFIG_BF60x
-/*
- * CAN
- */
-#define CAN_OFF(mmr) REGS_OFF(can, mmr)
-#define __CAN(uname, lname) __REGS(can, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
-{
- static struct dentry *am, *mb;
- int i, j;
- char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
-
- if (!am) {
- am = debugfs_create_dir("am", parent);
- mb = debugfs_create_dir("mb", parent);
- }
-
- __CAN(MC1, mc1);
- __CAN(MD1, md1);
- __CAN(TRS1, trs1);
- __CAN(TRR1, trr1);
- __CAN(TA1, ta1);
- __CAN(AA1, aa1);
- __CAN(RMP1, rmp1);
- __CAN(RML1, rml1);
- __CAN(MBTIF1, mbtif1);
- __CAN(MBRIF1, mbrif1);
- __CAN(MBIM1, mbim1);
- __CAN(RFH1, rfh1);
- __CAN(OPSS1, opss1);
-
- __CAN(MC2, mc2);
- __CAN(MD2, md2);
- __CAN(TRS2, trs2);
- __CAN(TRR2, trr2);
- __CAN(TA2, ta2);
- __CAN(AA2, aa2);
- __CAN(RMP2, rmp2);
- __CAN(RML2, rml2);
- __CAN(MBTIF2, mbtif2);
- __CAN(MBRIF2, mbrif2);
- __CAN(MBIM2, mbim2);
- __CAN(RFH2, rfh2);
- __CAN(OPSS2, opss2);
-
- __CAN(CLOCK, clock);
- __CAN(TIMING, timing);
- __CAN(DEBUG, debug);
- __CAN(STATUS, status);
- __CAN(CEC, cec);
- __CAN(GIS, gis);
- __CAN(GIM, gim);
- __CAN(GIF, gif);
- __CAN(CONTROL, control);
- __CAN(INTR, intr);
- __CAN(VERSION, version);
- __CAN(MBTD, mbtd);
- __CAN(EWR, ewr);
- __CAN(ESR, esr);
- /*__CAN(UCREG, ucreg); no longer exists */
- __CAN(UCCNT, uccnt);
- __CAN(UCRC, ucrc);
- __CAN(UCCNF, uccnf);
- __CAN(VERSION2, version2);
-
- for (i = 0; i < 32; ++i) {
- sprintf(_buf, "AM%02iL", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
- (u16 *)(base + CAN_OFF(msk[i].aml)));
- sprintf(_buf, "AM%02iH", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
- (u16 *)(base + CAN_OFF(msk[i].amh)));
-
- for (j = 0; j < 3; ++j) {
- sprintf(_buf, "MB%02i_DATA%i", i, j);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
- }
- sprintf(_buf, "MB%02i_LENGTH", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].dlc)));
- sprintf(_buf, "MB%02i_TIMESTAMP", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].tsv)));
- sprintf(_buf, "MB%02i_ID0", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].id0)));
- sprintf(_buf, "MB%02i_ID1", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].id1)));
- }
-}
-#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
-
-/*
- * DMA
- */
-#define __DMA(uname, lname) __REGS(dma, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
-{
- char buf[32], *_buf;
-
- if (mdma)
- _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
- else
- _buf = buf + sprintf(buf, "%s%i_", pfx, num);
-
- __DMA(NEXT_DESC_PTR, next_desc_ptr);
- __DMA(START_ADDR, start_addr);
- __DMA(CONFIG, config);
- __DMA(X_COUNT, x_count);
- __DMA(X_MODIFY, x_modify);
- __DMA(Y_COUNT, y_count);
- __DMA(Y_MODIFY, y_modify);
- __DMA(CURR_DESC_PTR, curr_desc_ptr);
- __DMA(CURR_ADDR, curr_addr);
- __DMA(IRQ_STATUS, irq_status);
-#ifndef CONFIG_BF60x
- if (strcmp(pfx, "IMDMA") != 0)
- __DMA(PERIPHERAL_MAP, peripheral_map);
-#endif
- __DMA(CURR_X_COUNT, curr_x_count);
- __DMA(CURR_Y_COUNT, curr_y_count);
-}
-#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
-#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
-#define _MDMA(num, x) \
- do { \
- _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
- _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
- } while (0)
-#define MDMA(num) _MDMA(num, M)
-#define IMDMA(num) _MDMA(num, IM)
-
-/*
- * EPPI
- */
-#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
- __EPPI(STATUS, status);
- __EPPI(HCOUNT, hcount);
- __EPPI(HDELAY, hdelay);
- __EPPI(VCOUNT, vcount);
- __EPPI(VDELAY, vdelay);
- __EPPI(FRAME, frame);
- __EPPI(LINE, line);
- __EPPI(CLKDIV, clkdiv);
- __EPPI(CONTROL, control);
- __EPPI(FS1W_HBL, fs1w_hbl);
- __EPPI(FS1P_AVPL, fs1p_avpl);
- __EPPI(FS2W_LVB, fs2w_lvb);
- __EPPI(FS2P_LAVF, fs2p_lavf);
- __EPPI(CLIP, clip);
-}
-#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
-
-/*
- * General Purpose Timers
- */
-#define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
- __GPTIMER(CONFIG, config);
- __GPTIMER(COUNTER, counter);
- __GPTIMER(PERIOD, period);
- __GPTIMER(WIDTH, width);
-}
-#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
-
-#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
-#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf;
-
- if (num == -1) {
- _buf = buf + sprintf(buf, "TIMER_");
- __GPTIMER_GROUP(ENABLE, enable);
- __GPTIMER_GROUP(DISABLE, disable);
- __GPTIMER_GROUP(STATUS, status);
- } else {
- /* These MMRs are a bit odd as the group # is a suffix */
- _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
- d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
-
- _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
- d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
-
- _buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
- d(buf, 32, base + GPTIMER_GROUP_OFF(status));
- }
-}
-#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
-
-/*
- * Handshake MDMA
- */
-#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
- __HMDMA(CONTROL, control);
- __HMDMA(ECINIT, ecinit);
- __HMDMA(BCINIT, bcinit);
- __HMDMA(ECURGENT, ecurgent);
- __HMDMA(ECOVERFLOW, ecoverflow);
- __HMDMA(ECOUNT, ecount);
- __HMDMA(BCOUNT, bcount);
-}
-#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
-
-/*
- * Peripheral Interrupts (PINT/GPIO)
- */
-#ifdef PINT0_MASK_SET
-#define __PINT(uname, lname) __REGS(pint, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num);
- __PINT(MASK_SET, mask_set);
- __PINT(MASK_CLEAR, mask_clear);
- __PINT(REQUEST, request);
- __PINT(ASSIGN, assign);
- __PINT(EDGE_SET, edge_set);
- __PINT(EDGE_CLEAR, edge_clear);
- __PINT(INVERT_SET, invert_set);
- __PINT(INVERT_CLEAR, invert_clear);
- __PINT(PINSTATE, pinstate);
- __PINT(LATCH, latch);
-}
-#define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num)
-#endif
-
-/*
- * Port/GPIO
- */
-#define bfin_gpio_regs gpio_port_t
-#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf;
-#ifdef __ADSPBF54x__
- _buf = REGS_STR_PFX_C(buf, PORT, num);
- __PORT(FER, port_fer);
- __PORT(SET, data_set);
- __PORT(CLEAR, data_clear);
- __PORT(DIR_SET, dir_set);
- __PORT(DIR_CLEAR, dir_clear);
- __PORT(INEN, inen);
- __PORT(MUX, port_mux);
-#else
- _buf = buf + sprintf(buf, "PORT%cIO_", num);
- __PORT(CLEAR, data_clear);
- __PORT(SET, data_set);
- __PORT(TOGGLE, toggle);
- __PORT(MASKA, maska);
- __PORT(MASKA_CLEAR, maska_clear);
- __PORT(MASKA_SET, maska_set);
- __PORT(MASKA_TOGGLE, maska_toggle);
- __PORT(MASKB, maskb);
- __PORT(MASKB_CLEAR, maskb_clear);
- __PORT(MASKB_SET, maskb_set);
- __PORT(MASKB_TOGGLE, maskb_toggle);
- __PORT(DIR, dir);
- __PORT(POLAR, polar);
- __PORT(EDGE, edge);
- __PORT(BOTH, both);
- __PORT(INEN, inen);
-#endif
- _buf[-1] = '\0';
- d(buf, 16, base + REGS_OFF(gpio, data));
-}
-#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
-
-/*
- * PPI
- */
-#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
- __PPI(CONTROL, control);
- __PPI(STATUS, status);
- __PPI(COUNT, count);
- __PPI(DELAY, delay);
- __PPI(FRAME, frame);
-}
-#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
-
-/*
- * SPI
- */
-#define __SPI(uname, lname) __REGS(spi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
- __SPI(CTL, ctl);
- __SPI(FLG, flg);
- __SPI(STAT, stat);
- __SPI(TDBR, tdbr);
- __SPI(RDBR, rdbr);
- __SPI(BAUD, baud);
- __SPI(SHADOW, shadow);
-}
-#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
-
-/*
- * SPORT
- */
-static inline int sport_width(void *mmr)
-{
- unsigned long lmmr = (unsigned long)mmr;
- if ((lmmr & 0xff) == 0x10)
- /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
- lmmr -= 0xc;
- else
- /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
- lmmr += 0xc;
- /* extract SLEN field from control register 2 and add 1 */
- return (bfin_read16(lmmr) & 0x1f) + 1;
-}
-static int sport_set(void *mmr, u64 val)
-{
- unsigned long flags;
- local_irq_save(flags);
- if (sport_width(mmr) <= 16)
- bfin_write16(mmr, val);
- else
- bfin_write32(mmr, val);
- local_irq_restore(flags);
- return 0;
-}
-static int sport_get(void *mmr, u64 *val)
-{
- unsigned long flags;
- local_irq_save(flags);
- if (sport_width(mmr) <= 16)
- *val = bfin_read16(mmr);
- else
- *val = bfin_read32(mmr);
- local_irq_restore(flags);
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
-/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
-DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
-#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
-#define _D_SPORT(name, perms, fops) \
- do { \
- strcpy(_buf, #name); \
- debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
- } while (0)
-#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
-#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
-#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
-#define __SPORT(name, bits) \
- do { \
- strcpy(_buf, #name); \
- debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
- } while (0)
-static void __init __maybe_unused
-bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
- __SPORT(CHNL, 16);
- __SPORT(MCMC1, 16);
- __SPORT(MCMC2, 16);
- __SPORT(MRCS0, 32);
- __SPORT(MRCS1, 32);
- __SPORT(MRCS2, 32);
- __SPORT(MRCS3, 32);
- __SPORT(MTCS0, 32);
- __SPORT(MTCS1, 32);
- __SPORT(MTCS2, 32);
- __SPORT(MTCS3, 32);
- __SPORT(RCLKDIV, 16);
- __SPORT(RCR1, 16);
- __SPORT(RCR2, 16);
- __SPORT(RFSDIV, 16);
- __SPORT_RW(RX);
- __SPORT(STAT, 16);
- __SPORT(TCLKDIV, 16);
- __SPORT(TCR1, 16);
- __SPORT(TCR2, 16);
- __SPORT(TFSDIV, 16);
- __SPORT_WO(TX);
-}
-#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
-
-/*
- * TWI
- */
-#define __TWI(uname, lname) __REGS(twi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
- __TWI(CLKDIV, clkdiv);
- __TWI(CONTROL, control);
- __TWI(SLAVE_CTL, slave_ctl);
- __TWI(SLAVE_STAT, slave_stat);
- __TWI(SLAVE_ADDR, slave_addr);
- __TWI(MASTER_CTL, master_ctl);
- __TWI(MASTER_STAT, master_stat);
- __TWI(MASTER_ADDR, master_addr);
- __TWI(INT_STAT, int_stat);
- __TWI(INT_MASK, int_mask);
- __TWI(FIFO_CTL, fifo_ctl);
- __TWI(FIFO_STAT, fifo_stat);
- __TWI(XMT_DATA8, xmt_data8);
- __TWI(XMT_DATA16, xmt_data16);
- __TWI(RCV_DATA8, rcv_data8);
- __TWI(RCV_DATA16, rcv_data16);
-}
-#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
-
-/*
- * UART
- */
-#define __UART(uname, lname) __REGS(uart, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
-#ifdef BFIN_UART_BF54X_STYLE
- __UART(DLL, dll);
- __UART(DLH, dlh);
- __UART(GCTL, gctl);
- __UART(LCR, lcr);
- __UART(MCR, mcr);
- __UART(LSR, lsr);
- __UART(MSR, msr);
- __UART(SCR, scr);
- __UART(IER_SET, ier_set);
- __UART(IER_CLEAR, ier_clear);
- __UART(THR, thr);
- __UART(RBR, rbr);
-#else
- __UART(DLL, dll);
- __UART(THR, thr);
- __UART(RBR, rbr);
- __UART(DLH, dlh);
- __UART(IER, ier);
- __UART(IIR, iir);
- __UART(LCR, lcr);
- __UART(MCR, mcr);
- __UART(LSR, lsr);
- __UART(MSR, msr);
- __UART(SCR, scr);
- __UART(GCTL, gctl);
-#endif
-}
-#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
-#endif /* CONFIG_BF60x */
-/*
- * The actual debugfs generation
- */
-static struct dentry *debug_mmrs_dentry;
-
-static int __init bfin_debug_mmrs_init(void)
-{
- struct dentry *top, *parent;
-
- pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
-
- top = debugfs_create_dir("blackfin", NULL);
- if (top == NULL)
- return -1;
-
- parent = debugfs_create_dir("core_regs", top);
- debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
- debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
- debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
- D_SYSREG(cycles);
- D_SYSREG(cycles2);
- D_SYSREG(emudat);
- D_SYSREG(seqstat);
- D_SYSREG(syscfg);
-
- /* Core MMRs */
- parent = debugfs_create_dir("ctimer", top);
- D32(TCNTL);
- D32(TCOUNT);
- D32(TPERIOD);
- D32(TSCALE);
-
- parent = debugfs_create_dir("cec", top);
- D32(EVT0);
- D32(EVT1);
- D32(EVT2);
- D32(EVT3);
- D32(EVT4);
- D32(EVT5);
- D32(EVT6);
- D32(EVT7);
- D32(EVT8);
- D32(EVT9);
- D32(EVT10);
- D32(EVT11);
- D32(EVT12);
- D32(EVT13);
- D32(EVT14);
- D32(EVT15);
- D32(EVT_OVERRIDE);
- D32(IMASK);
- D32(IPEND);
- D32(ILAT);
- D32(IPRIO);
-
- parent = debugfs_create_dir("debug", top);
- D32(DBGSTAT);
- D32(DSPID);
-
- parent = debugfs_create_dir("mmu", top);
- D32(SRAM_BASE_ADDRESS);
- D32(DCPLB_ADDR0);
- D32(DCPLB_ADDR10);
- D32(DCPLB_ADDR11);
- D32(DCPLB_ADDR12);
- D32(DCPLB_ADDR13);
- D32(DCPLB_ADDR14);
- D32(DCPLB_ADDR15);
- D32(DCPLB_ADDR1);
- D32(DCPLB_ADDR2);
- D32(DCPLB_ADDR3);
- D32(DCPLB_ADDR4);
- D32(DCPLB_ADDR5);
- D32(DCPLB_ADDR6);
- D32(DCPLB_ADDR7);
- D32(DCPLB_ADDR8);
- D32(DCPLB_ADDR9);
- D32(DCPLB_DATA0);
- D32(DCPLB_DATA10);
- D32(DCPLB_DATA11);
- D32(DCPLB_DATA12);
- D32(DCPLB_DATA13);
- D32(DCPLB_DATA14);
- D32(DCPLB_DATA15);
- D32(DCPLB_DATA1);
- D32(DCPLB_DATA2);
- D32(DCPLB_DATA3);
- D32(DCPLB_DATA4);
- D32(DCPLB_DATA5);
- D32(DCPLB_DATA6);
- D32(DCPLB_DATA7);
- D32(DCPLB_DATA8);
- D32(DCPLB_DATA9);
- D32(DCPLB_FAULT_ADDR);
- D32(DCPLB_STATUS);
- D32(DMEM_CONTROL);
- D32(DTEST_COMMAND);
- D32(DTEST_DATA0);
- D32(DTEST_DATA1);
-
- D32(ICPLB_ADDR0);
- D32(ICPLB_ADDR1);
- D32(ICPLB_ADDR2);
- D32(ICPLB_ADDR3);
- D32(ICPLB_ADDR4);
- D32(ICPLB_ADDR5);
- D32(ICPLB_ADDR6);
- D32(ICPLB_ADDR7);
- D32(ICPLB_ADDR8);
- D32(ICPLB_ADDR9);
- D32(ICPLB_ADDR10);
- D32(ICPLB_ADDR11);
- D32(ICPLB_ADDR12);
- D32(ICPLB_ADDR13);
- D32(ICPLB_ADDR14);
- D32(ICPLB_ADDR15);
- D32(ICPLB_DATA0);
- D32(ICPLB_DATA1);
- D32(ICPLB_DATA2);
- D32(ICPLB_DATA3);
- D32(ICPLB_DATA4);
- D32(ICPLB_DATA5);
- D32(ICPLB_DATA6);
- D32(ICPLB_DATA7);
- D32(ICPLB_DATA8);
- D32(ICPLB_DATA9);
- D32(ICPLB_DATA10);
- D32(ICPLB_DATA11);
- D32(ICPLB_DATA12);
- D32(ICPLB_DATA13);
- D32(ICPLB_DATA14);
- D32(ICPLB_DATA15);
- D32(ICPLB_FAULT_ADDR);
- D32(ICPLB_STATUS);
- D32(IMEM_CONTROL);
- if (!ANOMALY_05000481) {
- D32(ITEST_COMMAND);
- D32(ITEST_DATA0);
- D32(ITEST_DATA1);
- }
-
- parent = debugfs_create_dir("perf", top);
- D32(PFCNTR0);
- D32(PFCNTR1);
- D32(PFCTL);
-
- parent = debugfs_create_dir("trace", top);
- D32(TBUF);
- D32(TBUFCTL);
- D32(TBUFSTAT);
-
- parent = debugfs_create_dir("watchpoint", top);
- D32(WPIACTL);
- D32(WPIA0);
- D32(WPIA1);
- D32(WPIA2);
- D32(WPIA3);
- D32(WPIA4);
- D32(WPIA5);
- D32(WPIACNT0);
- D32(WPIACNT1);
- D32(WPIACNT2);
- D32(WPIACNT3);
- D32(WPIACNT4);
- D32(WPIACNT5);
- D32(WPDACTL);
- D32(WPDA0);
- D32(WPDA1);
- D32(WPDACNT0);
- D32(WPDACNT1);
- D32(WPSTAT);
-#ifndef CONFIG_BF60x
- /* System MMRs */
-#ifdef ATAPI_CONTROL
- parent = debugfs_create_dir("atapi", top);
- D16(ATAPI_CONTROL);
- D16(ATAPI_DEV_ADDR);
- D16(ATAPI_DEV_RXBUF);
- D16(ATAPI_DEV_TXBUF);
- D16(ATAPI_DMA_TFRCNT);
- D16(ATAPI_INT_MASK);
- D16(ATAPI_INT_STATUS);
- D16(ATAPI_LINE_STATUS);
- D16(ATAPI_MULTI_TIM_0);
- D16(ATAPI_MULTI_TIM_1);
- D16(ATAPI_MULTI_TIM_2);
- D16(ATAPI_PIO_TFRCNT);
- D16(ATAPI_PIO_TIM_0);
- D16(ATAPI_PIO_TIM_1);
- D16(ATAPI_REG_TIM_0);
- D16(ATAPI_SM_STATE);
- D16(ATAPI_STATUS);
- D16(ATAPI_TERMINATE);
- D16(ATAPI_UDMAOUT_TFRCNT);
- D16(ATAPI_ULTRA_TIM_0);
- D16(ATAPI_ULTRA_TIM_1);
- D16(ATAPI_ULTRA_TIM_2);
- D16(ATAPI_ULTRA_TIM_3);
- D16(ATAPI_UMAIN_TFRCNT);
- D16(ATAPI_XFER_LEN);
-#endif
-
-#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
- parent = debugfs_create_dir("can", top);
-# ifdef CAN_MC1
- bfin_debug_mmrs_can(parent, CAN_MC1, -1);
-# endif
-# ifdef CAN0_MC1
- CAN(0);
-# endif
-# ifdef CAN1_MC1
- CAN(1);
-# endif
-#endif
-
-#ifdef CNT_COMMAND
- parent = debugfs_create_dir("counter", top);
- D16(CNT_COMMAND);
- D16(CNT_CONFIG);
- D32(CNT_COUNTER);
- D16(CNT_DEBOUNCE);
- D16(CNT_IMASK);
- D32(CNT_MAX);
- D32(CNT_MIN);
- D16(CNT_STATUS);
-#endif
-
- parent = debugfs_create_dir("dmac", top);
-#ifdef DMAC_TC_CNT
- D16(DMAC_TC_CNT);
- D16(DMAC_TC_PER);
-#endif
-#ifdef DMAC0_TC_CNT
- D16(DMAC0_TC_CNT);
- D16(DMAC0_TC_PER);
-#endif
-#ifdef DMAC1_TC_CNT
- D16(DMAC1_TC_CNT);
- D16(DMAC1_TC_PER);
-#endif
-#ifdef DMAC1_PERIMUX
- D16(DMAC1_PERIMUX);
-#endif
-
-#ifdef __ADSPBF561__
- /* XXX: should rewrite the MMR map */
-# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
-# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
-# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
-# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
-# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
-# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
-# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
-# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
-# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
-# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
-# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
-# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
-# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
-# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
-# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
-# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
-# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
-# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
-# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
-# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
-# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
-# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
-# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
-# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
-#endif
- parent = debugfs_create_dir("dma", top);
- DMA(0);
- DMA(1);
- DMA(1);
- DMA(2);
- DMA(3);
- DMA(4);
- DMA(5);
- DMA(6);
- DMA(7);
-#ifdef DMA8_NEXT_DESC_PTR
- DMA(8);
- DMA(9);
- DMA(10);
- DMA(11);
-#endif
-#ifdef DMA12_NEXT_DESC_PTR
- DMA(12);
- DMA(13);
- DMA(14);
- DMA(15);
- DMA(16);
- DMA(17);
- DMA(18);
- DMA(19);
-#endif
-#ifdef DMA20_NEXT_DESC_PTR
- DMA(20);
- DMA(21);
- DMA(22);
- DMA(23);
-#endif
-
- parent = debugfs_create_dir("ebiu_amc", top);
- D32(EBIU_AMBCTL0);
- D32(EBIU_AMBCTL1);
- D16(EBIU_AMGCTL);
-#ifdef EBIU_MBSCTL
- D16(EBIU_MBSCTL);
- D32(EBIU_ARBSTAT);
- D32(EBIU_MODE);
- D16(EBIU_FCTL);
-#endif
-
-#ifdef EBIU_SDGCTL
- parent = debugfs_create_dir("ebiu_sdram", top);
-# ifdef __ADSPBF561__
- D32(EBIU_SDBCTL);
-# else
- D16(EBIU_SDBCTL);
-# endif
- D32(EBIU_SDGCTL);
- D16(EBIU_SDRRC);
- D16(EBIU_SDSTAT);
-#endif
-
-#ifdef EBIU_DDRACCT
- parent = debugfs_create_dir("ebiu_ddr", top);
- D32(EBIU_DDRACCT);
- D32(EBIU_DDRARCT);
- D32(EBIU_DDRBRC0);
- D32(EBIU_DDRBRC1);
- D32(EBIU_DDRBRC2);
- D32(EBIU_DDRBRC3);
- D32(EBIU_DDRBRC4);
- D32(EBIU_DDRBRC5);
- D32(EBIU_DDRBRC6);
- D32(EBIU_DDRBRC7);
- D32(EBIU_DDRBWC0);
- D32(EBIU_DDRBWC1);
- D32(EBIU_DDRBWC2);
- D32(EBIU_DDRBWC3);
- D32(EBIU_DDRBWC4);
- D32(EBIU_DDRBWC5);
- D32(EBIU_DDRBWC6);
- D32(EBIU_DDRBWC7);
- D32(EBIU_DDRCTL0);
- D32(EBIU_DDRCTL1);
- D32(EBIU_DDRCTL2);
- D32(EBIU_DDRCTL3);
- D32(EBIU_DDRGC0);
- D32(EBIU_DDRGC1);
- D32(EBIU_DDRGC2);
- D32(EBIU_DDRGC3);
- D32(EBIU_DDRMCCL);
- D32(EBIU_DDRMCEN);
- D32(EBIU_DDRQUE);
- D32(EBIU_DDRTACT);
- D32(EBIU_ERRADD);
- D16(EBIU_ERRMST);
- D16(EBIU_RSTCTL);
-#endif
-
-#ifdef EMAC_ADDRHI
- parent = debugfs_create_dir("emac", top);
- D32(EMAC_ADDRHI);
- D32(EMAC_ADDRLO);
- D32(EMAC_FLC);
- D32(EMAC_HASHHI);
- D32(EMAC_HASHLO);
- D32(EMAC_MMC_CTL);
- D32(EMAC_MMC_RIRQE);
- D32(EMAC_MMC_RIRQS);
- D32(EMAC_MMC_TIRQE);
- D32(EMAC_MMC_TIRQS);
- D32(EMAC_OPMODE);
- D32(EMAC_RXC_ALIGN);
- D32(EMAC_RXC_ALLFRM);
- D32(EMAC_RXC_ALLOCT);
- D32(EMAC_RXC_BROAD);
- D32(EMAC_RXC_DMAOVF);
- D32(EMAC_RXC_EQ64);
- D32(EMAC_RXC_FCS);
- D32(EMAC_RXC_GE1024);
- D32(EMAC_RXC_LNERRI);
- D32(EMAC_RXC_LNERRO);
- D32(EMAC_RXC_LONG);
- D32(EMAC_RXC_LT1024);
- D32(EMAC_RXC_LT128);
- D32(EMAC_RXC_LT256);
- D32(EMAC_RXC_LT512);
- D32(EMAC_RXC_MACCTL);
- D32(EMAC_RXC_MULTI);
- D32(EMAC_RXC_OCTET);
- D32(EMAC_RXC_OK);
- D32(EMAC_RXC_OPCODE);
- D32(EMAC_RXC_PAUSE);
- D32(EMAC_RXC_SHORT);
- D32(EMAC_RXC_TYPED);
- D32(EMAC_RXC_UNICST);
- D32(EMAC_RX_IRQE);
- D32(EMAC_RX_STAT);
- D32(EMAC_RX_STKY);
- D32(EMAC_STAADD);
- D32(EMAC_STADAT);
- D32(EMAC_SYSCTL);
- D32(EMAC_SYSTAT);
- D32(EMAC_TXC_1COL);
- D32(EMAC_TXC_ABORT);
- D32(EMAC_TXC_ALLFRM);
- D32(EMAC_TXC_ALLOCT);
- D32(EMAC_TXC_BROAD);
- D32(EMAC_TXC_CRSERR);
- D32(EMAC_TXC_DEFER);
- D32(EMAC_TXC_DMAUND);
- D32(EMAC_TXC_EQ64);
- D32(EMAC_TXC_GE1024);
- D32(EMAC_TXC_GT1COL);
- D32(EMAC_TXC_LATECL);
- D32(EMAC_TXC_LT1024);
- D32(EMAC_TXC_LT128);
- D32(EMAC_TXC_LT256);
- D32(EMAC_TXC_LT512);
- D32(EMAC_TXC_MACCTL);
- D32(EMAC_TXC_MULTI);
- D32(EMAC_TXC_OCTET);
- D32(EMAC_TXC_OK);
- D32(EMAC_TXC_UNICST);
- D32(EMAC_TXC_XS_COL);
- D32(EMAC_TXC_XS_DFR);
- D32(EMAC_TX_IRQE);
- D32(EMAC_TX_STAT);
- D32(EMAC_TX_STKY);
- D32(EMAC_VLAN1);
- D32(EMAC_VLAN2);
- D32(EMAC_WKUP_CTL);
- D32(EMAC_WKUP_FFCMD);
- D32(EMAC_WKUP_FFCRC0);
- D32(EMAC_WKUP_FFCRC1);
- D32(EMAC_WKUP_FFMSK0);
- D32(EMAC_WKUP_FFMSK1);
- D32(EMAC_WKUP_FFMSK2);
- D32(EMAC_WKUP_FFMSK3);
- D32(EMAC_WKUP_FFOFF);
-# ifdef EMAC_PTP_ACCR
- D32(EMAC_PTP_ACCR);
- D32(EMAC_PTP_ADDEND);
- D32(EMAC_PTP_ALARMHI);
- D32(EMAC_PTP_ALARMLO);
- D16(EMAC_PTP_CTL);
- D32(EMAC_PTP_FOFF);
- D32(EMAC_PTP_FV1);
- D32(EMAC_PTP_FV2);
- D32(EMAC_PTP_FV3);
- D16(EMAC_PTP_ID_OFF);
- D32(EMAC_PTP_ID_SNAP);
- D16(EMAC_PTP_IE);
- D16(EMAC_PTP_ISTAT);
- D32(EMAC_PTP_OFFSET);
- D32(EMAC_PTP_PPS_PERIOD);
- D32(EMAC_PTP_PPS_STARTHI);
- D32(EMAC_PTP_PPS_STARTLO);
- D32(EMAC_PTP_RXSNAPHI);
- D32(EMAC_PTP_RXSNAPLO);
- D32(EMAC_PTP_TIMEHI);
- D32(EMAC_PTP_TIMELO);
- D32(EMAC_PTP_TXSNAPHI);
- D32(EMAC_PTP_TXSNAPLO);
-# endif
-#endif
-
-#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
- parent = debugfs_create_dir("eppi", top);
-# ifdef EPPI0_STATUS
- EPPI(0);
-# endif
-# ifdef EPPI1_STATUS
- EPPI(1);
-# endif
-# ifdef EPPI2_STATUS
- EPPI(2);
-# endif
-#endif
-
- parent = debugfs_create_dir("gptimer", top);
-#ifdef TIMER_ENABLE
- GPTIMER_GROUP(TIMER_ENABLE, -1);
-#endif
-#ifdef TIMER_ENABLE0
- GPTIMER_GROUP(TIMER_ENABLE0, 0);
-#endif
-#ifdef TIMER_ENABLE1
- GPTIMER_GROUP(TIMER_ENABLE1, 1);
-#endif
- /* XXX: Should convert BF561 MMR names */
-#ifdef TMRS4_DISABLE
- GPTIMER_GROUP(TMRS4_ENABLE, 0);
- GPTIMER_GROUP(TMRS8_ENABLE, 1);
-#endif
- GPTIMER(0);
- GPTIMER(1);
- GPTIMER(2);
-#ifdef TIMER3_CONFIG
- GPTIMER(3);
- GPTIMER(4);
- GPTIMER(5);
- GPTIMER(6);
- GPTIMER(7);
-#endif
-#ifdef TIMER8_CONFIG
- GPTIMER(8);
- GPTIMER(9);
- GPTIMER(10);
-#endif
-#ifdef TIMER11_CONFIG
- GPTIMER(11);
-#endif
-
-#ifdef HMDMA0_CONTROL
- parent = debugfs_create_dir("hmdma", top);
- HMDMA(0);
- HMDMA(1);
-#endif
-
-#ifdef HOST_CONTROL
- parent = debugfs_create_dir("hostdp", top);
- D16(HOST_CONTROL);
- D16(HOST_STATUS);
- D16(HOST_TIMEOUT);
-#endif
-
-#ifdef IMDMA_S0_CONFIG
- parent = debugfs_create_dir("imdma", top);
- IMDMA(0);
- IMDMA(1);
-#endif
-
-#ifdef KPAD_CTL
- parent = debugfs_create_dir("keypad", top);
- D16(KPAD_CTL);
- D16(KPAD_PRESCALE);
- D16(KPAD_MSEL);
- D16(KPAD_ROWCOL);
- D16(KPAD_STAT);
- D16(KPAD_SOFTEVAL);
-#endif
-
- parent = debugfs_create_dir("mdma", top);
- MDMA(0);
- MDMA(1);
-#ifdef MDMA_D2_CONFIG
- MDMA(2);
- MDMA(3);
-#endif
-
-#ifdef MXVR_CONFIG
- parent = debugfs_create_dir("mxvr", top);
- D16(MXVR_CONFIG);
-# ifdef MXVR_PLL_CTL_0
- D32(MXVR_PLL_CTL_0);
-# endif
- D32(MXVR_STATE_0);
- D32(MXVR_STATE_1);
- D32(MXVR_INT_STAT_0);
- D32(MXVR_INT_STAT_1);
- D32(MXVR_INT_EN_0);
- D32(MXVR_INT_EN_1);
- D16(MXVR_POSITION);
- D16(MXVR_MAX_POSITION);
- D16(MXVR_DELAY);
- D16(MXVR_MAX_DELAY);
- D32(MXVR_LADDR);
- D16(MXVR_GADDR);
- D32(MXVR_AADDR);
- D32(MXVR_ALLOC_0);
- D32(MXVR_ALLOC_1);
- D32(MXVR_ALLOC_2);
- D32(MXVR_ALLOC_3);
- D32(MXVR_ALLOC_4);
- D32(MXVR_ALLOC_5);
- D32(MXVR_ALLOC_6);
- D32(MXVR_ALLOC_7);
- D32(MXVR_ALLOC_8);
- D32(MXVR_ALLOC_9);
- D32(MXVR_ALLOC_10);
- D32(MXVR_ALLOC_11);
- D32(MXVR_ALLOC_12);
- D32(MXVR_ALLOC_13);
- D32(MXVR_ALLOC_14);
- D32(MXVR_SYNC_LCHAN_0);
- D32(MXVR_SYNC_LCHAN_1);
- D32(MXVR_SYNC_LCHAN_2);
- D32(MXVR_SYNC_LCHAN_3);
- D32(MXVR_SYNC_LCHAN_4);
- D32(MXVR_SYNC_LCHAN_5);
- D32(MXVR_SYNC_LCHAN_6);
- D32(MXVR_SYNC_LCHAN_7);
- D32(MXVR_DMA0_CONFIG);
- D32(MXVR_DMA0_START_ADDR);
- D16(MXVR_DMA0_COUNT);
- D32(MXVR_DMA0_CURR_ADDR);
- D16(MXVR_DMA0_CURR_COUNT);
- D32(MXVR_DMA1_CONFIG);
- D32(MXVR_DMA1_START_ADDR);
- D16(MXVR_DMA1_COUNT);
- D32(MXVR_DMA1_CURR_ADDR);
- D16(MXVR_DMA1_CURR_COUNT);
- D32(MXVR_DMA2_CONFIG);
- D32(MXVR_DMA2_START_ADDR);
- D16(MXVR_DMA2_COUNT);
- D32(MXVR_DMA2_CURR_ADDR);
- D16(MXVR_DMA2_CURR_COUNT);
- D32(MXVR_DMA3_CONFIG);
- D32(MXVR_DMA3_START_ADDR);
- D16(MXVR_DMA3_COUNT);
- D32(MXVR_DMA3_CURR_ADDR);
- D16(MXVR_DMA3_CURR_COUNT);
- D32(MXVR_DMA4_CONFIG);
- D32(MXVR_DMA4_START_ADDR);
- D16(MXVR_DMA4_COUNT);
- D32(MXVR_DMA4_CURR_ADDR);
- D16(MXVR_DMA4_CURR_COUNT);
- D32(MXVR_DMA5_CONFIG);
- D32(MXVR_DMA5_START_ADDR);
- D16(MXVR_DMA5_COUNT);
- D32(MXVR_DMA5_CURR_ADDR);
- D16(MXVR_DMA5_CURR_COUNT);
- D32(MXVR_DMA6_CONFIG);
- D32(MXVR_DMA6_START_ADDR);
- D16(MXVR_DMA6_COUNT);
- D32(MXVR_DMA6_CURR_ADDR);
- D16(MXVR_DMA6_CURR_COUNT);
- D32(MXVR_DMA7_CONFIG);
- D32(MXVR_DMA7_START_ADDR);
- D16(MXVR_DMA7_COUNT);
- D32(MXVR_DMA7_CURR_ADDR);
- D16(MXVR_DMA7_CURR_COUNT);
- D16(MXVR_AP_CTL);
- D32(MXVR_APRB_START_ADDR);
- D32(MXVR_APRB_CURR_ADDR);
- D32(MXVR_APTB_START_ADDR);
- D32(MXVR_APTB_CURR_ADDR);
- D32(MXVR_CM_CTL);
- D32(MXVR_CMRB_START_ADDR);
- D32(MXVR_CMRB_CURR_ADDR);
- D32(MXVR_CMTB_START_ADDR);
- D32(MXVR_CMTB_CURR_ADDR);
- D32(MXVR_RRDB_START_ADDR);
- D32(MXVR_RRDB_CURR_ADDR);
- D32(MXVR_PAT_DATA_0);
- D32(MXVR_PAT_EN_0);
- D32(MXVR_PAT_DATA_1);
- D32(MXVR_PAT_EN_1);
- D16(MXVR_FRAME_CNT_0);
- D16(MXVR_FRAME_CNT_1);
- D32(MXVR_ROUTING_0);
- D32(MXVR_ROUTING_1);
- D32(MXVR_ROUTING_2);
- D32(MXVR_ROUTING_3);
- D32(MXVR_ROUTING_4);
- D32(MXVR_ROUTING_5);
- D32(MXVR_ROUTING_6);
- D32(MXVR_ROUTING_7);
- D32(MXVR_ROUTING_8);
- D32(MXVR_ROUTING_9);
- D32(MXVR_ROUTING_10);
- D32(MXVR_ROUTING_11);
- D32(MXVR_ROUTING_12);
- D32(MXVR_ROUTING_13);
- D32(MXVR_ROUTING_14);
-# ifdef MXVR_PLL_CTL_1
- D32(MXVR_PLL_CTL_1);
-# endif
- D16(MXVR_BLOCK_CNT);
-# ifdef MXVR_CLK_CTL
- D32(MXVR_CLK_CTL);
-# endif
-# ifdef MXVR_CDRPLL_CTL
- D32(MXVR_CDRPLL_CTL);
-# endif
-# ifdef MXVR_FMPLL_CTL
- D32(MXVR_FMPLL_CTL);
-# endif
-# ifdef MXVR_PIN_CTL
- D16(MXVR_PIN_CTL);
-# endif
-# ifdef MXVR_SCLK_CNT
- D16(MXVR_SCLK_CNT);
-# endif
-#endif
-
-#ifdef NFC_ADDR
- parent = debugfs_create_dir("nfc", top);
- D_WO(NFC_ADDR, 16);
- D_WO(NFC_CMD, 16);
- D_RO(NFC_COUNT, 16);
- D16(NFC_CTL);
- D_WO(NFC_DATA_RD, 16);
- D_WO(NFC_DATA_WR, 16);
- D_RO(NFC_ECC0, 16);
- D_RO(NFC_ECC1, 16);
- D_RO(NFC_ECC2, 16);
- D_RO(NFC_ECC3, 16);
- D16(NFC_IRQMASK);
- D16(NFC_IRQSTAT);
- D_WO(NFC_PGCTL, 16);
- D_RO(NFC_READ, 16);
- D16(NFC_RST);
- D_RO(NFC_STAT, 16);
-#endif
-
-#ifdef OTP_CONTROL
- parent = debugfs_create_dir("otp", top);
- D16(OTP_CONTROL);
- D16(OTP_BEN);
- D16(OTP_STATUS);
- D32(OTP_TIMING);
- D32(OTP_DATA0);
- D32(OTP_DATA1);
- D32(OTP_DATA2);
- D32(OTP_DATA3);
-#endif
-
-#ifdef PINT0_MASK_SET
- parent = debugfs_create_dir("pint", top);
- PINT(0);
- PINT(1);
- PINT(2);
- PINT(3);
-#endif
-
-#ifdef PIXC_CTL
- parent = debugfs_create_dir("pixc", top);
- D16(PIXC_CTL);
- D16(PIXC_PPL);
- D16(PIXC_LPF);
- D16(PIXC_AHSTART);
- D16(PIXC_AHEND);
- D16(PIXC_AVSTART);
- D16(PIXC_AVEND);
- D16(PIXC_ATRANSP);
- D16(PIXC_BHSTART);
- D16(PIXC_BHEND);
- D16(PIXC_BVSTART);
- D16(PIXC_BVEND);
- D16(PIXC_BTRANSP);
- D16(PIXC_INTRSTAT);
- D32(PIXC_RYCON);
- D32(PIXC_GUCON);
- D32(PIXC_BVCON);
- D32(PIXC_CCBIAS);
- D32(PIXC_TC);
-#endif
-
- parent = debugfs_create_dir("pll", top);
- D16(PLL_CTL);
- D16(PLL_DIV);
- D16(PLL_LOCKCNT);
- D16(PLL_STAT);
- D16(VR_CTL);
- D32(CHIPID); /* it's part of this hardware block */
-
-#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
- parent = debugfs_create_dir("ppi", top);
-# ifdef PPI_CONTROL
- bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
-# endif
-# ifdef PPI0_CONTROL
- PPI(0);
-# endif
-# ifdef PPI1_CONTROL
- PPI(1);
-# endif
-#endif
-
-#ifdef PWM_CTRL
- parent = debugfs_create_dir("pwm", top);
- D16(PWM_CTRL);
- D16(PWM_STAT);
- D16(PWM_TM);
- D16(PWM_DT);
- D16(PWM_GATE);
- D16(PWM_CHA);
- D16(PWM_CHB);
- D16(PWM_CHC);
- D16(PWM_SEG);
- D16(PWM_SYNCWT);
- D16(PWM_CHAL);
- D16(PWM_CHBL);
- D16(PWM_CHCL);
- D16(PWM_LSI);
- D16(PWM_STAT2);
-#endif
-
-#ifdef RSI_CONFIG
- parent = debugfs_create_dir("rsi", top);
- D32(RSI_ARGUMENT);
- D16(RSI_CEATA_CONTROL);
- D16(RSI_CLK_CONTROL);
- D16(RSI_COMMAND);
- D16(RSI_CONFIG);
- D16(RSI_DATA_CNT);
- D16(RSI_DATA_CONTROL);
- D16(RSI_DATA_LGTH);
- D32(RSI_DATA_TIMER);
- D16(RSI_EMASK);
- D16(RSI_ESTAT);
- D32(RSI_FIFO);
- D16(RSI_FIFO_CNT);
- D32(RSI_MASK0);
- D32(RSI_MASK1);
- D16(RSI_PID0);
- D16(RSI_PID1);
- D16(RSI_PID2);
- D16(RSI_PID3);
- D16(RSI_PID4);
- D16(RSI_PID5);
- D16(RSI_PID6);
- D16(RSI_PID7);
- D16(RSI_PWR_CONTROL);
- D16(RSI_RD_WAIT_EN);
- D32(RSI_RESPONSE0);
- D32(RSI_RESPONSE1);
- D32(RSI_RESPONSE2);
- D32(RSI_RESPONSE3);
- D16(RSI_RESP_CMD);
- D32(RSI_STATUS);
- D_WO(RSI_STATUSCL, 16);
-#endif
-
-#ifdef RTC_ALARM
- parent = debugfs_create_dir("rtc", top);
- D32(RTC_ALARM);
- D16(RTC_ICTL);
- D16(RTC_ISTAT);
- D16(RTC_PREN);
- D32(RTC_STAT);
- D16(RTC_SWCNT);
-#endif
-
-#ifdef SDH_CFG
- parent = debugfs_create_dir("sdh", top);
- D32(SDH_ARGUMENT);
- D16(SDH_CFG);
- D16(SDH_CLK_CTL);
- D16(SDH_COMMAND);
- D_RO(SDH_DATA_CNT, 16);
- D16(SDH_DATA_CTL);
- D16(SDH_DATA_LGTH);
- D32(SDH_DATA_TIMER);
- D16(SDH_E_MASK);
- D16(SDH_E_STATUS);
- D32(SDH_FIFO);
- D_RO(SDH_FIFO_CNT, 16);
- D32(SDH_MASK0);
- D32(SDH_MASK1);
- D_RO(SDH_PID0, 16);
- D_RO(SDH_PID1, 16);
- D_RO(SDH_PID2, 16);
- D_RO(SDH_PID3, 16);
- D_RO(SDH_PID4, 16);
- D_RO(SDH_PID5, 16);
- D_RO(SDH_PID6, 16);
- D_RO(SDH_PID7, 16);
- D16(SDH_PWR_CTL);
- D16(SDH_RD_WAIT_EN);
- D_RO(SDH_RESPONSE0, 32);
- D_RO(SDH_RESPONSE1, 32);
- D_RO(SDH_RESPONSE2, 32);
- D_RO(SDH_RESPONSE3, 32);
- D_RO(SDH_RESP_CMD, 16);
- D_RO(SDH_STATUS, 32);
- D_WO(SDH_STATUS_CLR, 16);
-#endif
-
-#ifdef SECURE_CONTROL
- parent = debugfs_create_dir("security", top);
- D16(SECURE_CONTROL);
- D16(SECURE_STATUS);
- D32(SECURE_SYSSWT);
-#endif
-
- parent = debugfs_create_dir("sic", top);
- D16(SWRST);
- D16(SYSCR);
- D16(SIC_RVECT);
- D32(SIC_IAR0);
- D32(SIC_IAR1);
- D32(SIC_IAR2);
-#ifdef SIC_IAR3
- D32(SIC_IAR3);
-#endif
-#ifdef SIC_IAR4
- D32(SIC_IAR4);
- D32(SIC_IAR5);
- D32(SIC_IAR6);
-#endif
-#ifdef SIC_IAR7
- D32(SIC_IAR7);
-#endif
-#ifdef SIC_IAR8
- D32(SIC_IAR8);
- D32(SIC_IAR9);
- D32(SIC_IAR10);
- D32(SIC_IAR11);
-#endif
-#ifdef SIC_IMASK
- D32(SIC_IMASK);
- D32(SIC_ISR);
- D32(SIC_IWR);
-#endif
-#ifdef SIC_IMASK0
- D32(SIC_IMASK0);
- D32(SIC_IMASK1);
- D32(SIC_ISR0);
- D32(SIC_ISR1);
- D32(SIC_IWR0);
- D32(SIC_IWR1);
-#endif
-#ifdef SIC_IMASK2
- D32(SIC_IMASK2);
- D32(SIC_ISR2);
- D32(SIC_IWR2);
-#endif
-#ifdef SICB_RVECT
- D16(SICB_SWRST);
- D16(SICB_SYSCR);
- D16(SICB_RVECT);
- D32(SICB_IAR0);
- D32(SICB_IAR1);
- D32(SICB_IAR2);
- D32(SICB_IAR3);
- D32(SICB_IAR4);
- D32(SICB_IAR5);
- D32(SICB_IAR6);
- D32(SICB_IAR7);
- D32(SICB_IMASK0);
- D32(SICB_IMASK1);
- D32(SICB_ISR0);
- D32(SICB_ISR1);
- D32(SICB_IWR0);
- D32(SICB_IWR1);
-#endif
-
- parent = debugfs_create_dir("spi", top);
-#ifdef SPI0_REGBASE
- SPI(0);
-#endif
-#ifdef SPI1_REGBASE
- SPI(1);
-#endif
-#ifdef SPI2_REGBASE
- SPI(2);
-#endif
-
- parent = debugfs_create_dir("sport", top);
-#ifdef SPORT0_STAT
- SPORT(0);
-#endif
-#ifdef SPORT1_STAT
- SPORT(1);
-#endif
-#ifdef SPORT2_STAT
- SPORT(2);
-#endif
-#ifdef SPORT3_STAT
- SPORT(3);
-#endif
-
-#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
- parent = debugfs_create_dir("twi", top);
-# ifdef TWI_CLKDIV
- bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
-# endif
-# ifdef TWI0_CLKDIV
- TWI(0);
-# endif
-# ifdef TWI1_CLKDIV
- TWI(1);
-# endif
-#endif
-
- parent = debugfs_create_dir("uart", top);
-#ifdef BFIN_UART_DLL
- bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
-#endif
-#ifdef UART0_DLL
- UART(0);
-#endif
-#ifdef UART1_DLL
- UART(1);
-#endif
-#ifdef UART2_DLL
- UART(2);
-#endif
-#ifdef UART3_DLL
- UART(3);
-#endif
-
-#ifdef USB_FADDR
- parent = debugfs_create_dir("usb", top);
- D16(USB_FADDR);
- D16(USB_POWER);
- D16(USB_INTRTX);
- D16(USB_INTRRX);
- D16(USB_INTRTXE);
- D16(USB_INTRRXE);
- D16(USB_INTRUSB);
- D16(USB_INTRUSBE);
- D16(USB_FRAME);
- D16(USB_INDEX);
- D16(USB_TESTMODE);
- D16(USB_GLOBINTR);
- D16(USB_GLOBAL_CTL);
- D16(USB_TX_MAX_PACKET);
- D16(USB_CSR0);
- D16(USB_TXCSR);
- D16(USB_RX_MAX_PACKET);
- D16(USB_RXCSR);
- D16(USB_COUNT0);
- D16(USB_RXCOUNT);
- D16(USB_TXTYPE);
- D16(USB_NAKLIMIT0);
- D16(USB_TXINTERVAL);
- D16(USB_RXTYPE);
- D16(USB_RXINTERVAL);
- D16(USB_TXCOUNT);
- D16(USB_EP0_FIFO);
- D16(USB_EP1_FIFO);
- D16(USB_EP2_FIFO);
- D16(USB_EP3_FIFO);
- D16(USB_EP4_FIFO);
- D16(USB_EP5_FIFO);
- D16(USB_EP6_FIFO);
- D16(USB_EP7_FIFO);
- D16(USB_OTG_DEV_CTL);
- D16(USB_OTG_VBUS_IRQ);
- D16(USB_OTG_VBUS_MASK);
- D16(USB_LINKINFO);
- D16(USB_VPLEN);
- D16(USB_HS_EOF1);
- D16(USB_FS_EOF1);
- D16(USB_LS_EOF1);
- D16(USB_APHY_CNTRL);
- D16(USB_APHY_CALIB);
- D16(USB_APHY_CNTRL2);
- D16(USB_PLLOSC_CTRL);
- D16(USB_SRP_CLKDIV);
- D16(USB_EP_NI0_TXMAXP);
- D16(USB_EP_NI0_TXCSR);
- D16(USB_EP_NI0_RXMAXP);
- D16(USB_EP_NI0_RXCSR);
- D16(USB_EP_NI0_RXCOUNT);
- D16(USB_EP_NI0_TXTYPE);
- D16(USB_EP_NI0_TXINTERVAL);
- D16(USB_EP_NI0_RXTYPE);
- D16(USB_EP_NI0_RXINTERVAL);
- D16(USB_EP_NI0_TXCOUNT);
- D16(USB_EP_NI1_TXMAXP);
- D16(USB_EP_NI1_TXCSR);
- D16(USB_EP_NI1_RXMAXP);
- D16(USB_EP_NI1_RXCSR);
- D16(USB_EP_NI1_RXCOUNT);
- D16(USB_EP_NI1_TXTYPE);
- D16(USB_EP_NI1_TXINTERVAL);
- D16(USB_EP_NI1_RXTYPE);
- D16(USB_EP_NI1_RXINTERVAL);
- D16(USB_EP_NI1_TXCOUNT);
- D16(USB_EP_NI2_TXMAXP);
- D16(USB_EP_NI2_TXCSR);
- D16(USB_EP_NI2_RXMAXP);
- D16(USB_EP_NI2_RXCSR);
- D16(USB_EP_NI2_RXCOUNT);
- D16(USB_EP_NI2_TXTYPE);
- D16(USB_EP_NI2_TXINTERVAL);
- D16(USB_EP_NI2_RXTYPE);
- D16(USB_EP_NI2_RXINTERVAL);
- D16(USB_EP_NI2_TXCOUNT);
- D16(USB_EP_NI3_TXMAXP);
- D16(USB_EP_NI3_TXCSR);
- D16(USB_EP_NI3_RXMAXP);
- D16(USB_EP_NI3_RXCSR);
- D16(USB_EP_NI3_RXCOUNT);
- D16(USB_EP_NI3_TXTYPE);
- D16(USB_EP_NI3_TXINTERVAL);
- D16(USB_EP_NI3_RXTYPE);
- D16(USB_EP_NI3_RXINTERVAL);
- D16(USB_EP_NI3_TXCOUNT);
- D16(USB_EP_NI4_TXMAXP);
- D16(USB_EP_NI4_TXCSR);
- D16(USB_EP_NI4_RXMAXP);
- D16(USB_EP_NI4_RXCSR);
- D16(USB_EP_NI4_RXCOUNT);
- D16(USB_EP_NI4_TXTYPE);
- D16(USB_EP_NI4_TXINTERVAL);
- D16(USB_EP_NI4_RXTYPE);
- D16(USB_EP_NI4_RXINTERVAL);
- D16(USB_EP_NI4_TXCOUNT);
- D16(USB_EP_NI5_TXMAXP);
- D16(USB_EP_NI5_TXCSR);
- D16(USB_EP_NI5_RXMAXP);
- D16(USB_EP_NI5_RXCSR);
- D16(USB_EP_NI5_RXCOUNT);
- D16(USB_EP_NI5_TXTYPE);
- D16(USB_EP_NI5_TXINTERVAL);
- D16(USB_EP_NI5_RXTYPE);
- D16(USB_EP_NI5_RXINTERVAL);
- D16(USB_EP_NI5_TXCOUNT);
- D16(USB_EP_NI6_TXMAXP);
- D16(USB_EP_NI6_TXCSR);
- D16(USB_EP_NI6_RXMAXP);
- D16(USB_EP_NI6_RXCSR);
- D16(USB_EP_NI6_RXCOUNT);
- D16(USB_EP_NI6_TXTYPE);
- D16(USB_EP_NI6_TXINTERVAL);
- D16(USB_EP_NI6_RXTYPE);
- D16(USB_EP_NI6_RXINTERVAL);
- D16(USB_EP_NI6_TXCOUNT);
- D16(USB_EP_NI7_TXMAXP);
- D16(USB_EP_NI7_TXCSR);
- D16(USB_EP_NI7_RXMAXP);
- D16(USB_EP_NI7_RXCSR);
- D16(USB_EP_NI7_RXCOUNT);
- D16(USB_EP_NI7_TXTYPE);
- D16(USB_EP_NI7_TXINTERVAL);
- D16(USB_EP_NI7_RXTYPE);
- D16(USB_EP_NI7_RXINTERVAL);
- D16(USB_EP_NI7_TXCOUNT);
- D16(USB_DMA_INTERRUPT);
- D16(USB_DMA0CONTROL);
- D16(USB_DMA0ADDRLOW);
- D16(USB_DMA0ADDRHIGH);
- D16(USB_DMA0COUNTLOW);
- D16(USB_DMA0COUNTHIGH);
- D16(USB_DMA1CONTROL);
- D16(USB_DMA1ADDRLOW);
- D16(USB_DMA1ADDRHIGH);
- D16(USB_DMA1COUNTLOW);
- D16(USB_DMA1COUNTHIGH);
- D16(USB_DMA2CONTROL);
- D16(USB_DMA2ADDRLOW);
- D16(USB_DMA2ADDRHIGH);
- D16(USB_DMA2COUNTLOW);
- D16(USB_DMA2COUNTHIGH);
- D16(USB_DMA3CONTROL);
- D16(USB_DMA3ADDRLOW);
- D16(USB_DMA3ADDRHIGH);
- D16(USB_DMA3COUNTLOW);
- D16(USB_DMA3COUNTHIGH);
- D16(USB_DMA4CONTROL);
- D16(USB_DMA4ADDRLOW);
- D16(USB_DMA4ADDRHIGH);
- D16(USB_DMA4COUNTLOW);
- D16(USB_DMA4COUNTHIGH);
- D16(USB_DMA5CONTROL);
- D16(USB_DMA5ADDRLOW);
- D16(USB_DMA5ADDRHIGH);
- D16(USB_DMA5COUNTLOW);
- D16(USB_DMA5COUNTHIGH);
- D16(USB_DMA6CONTROL);
- D16(USB_DMA6ADDRLOW);
- D16(USB_DMA6ADDRHIGH);
- D16(USB_DMA6COUNTLOW);
- D16(USB_DMA6COUNTHIGH);
- D16(USB_DMA7CONTROL);
- D16(USB_DMA7ADDRLOW);
- D16(USB_DMA7ADDRHIGH);
- D16(USB_DMA7COUNTLOW);
- D16(USB_DMA7COUNTHIGH);
-#endif
-
-#ifdef WDOG_CNT
- parent = debugfs_create_dir("watchdog", top);
- D32(WDOG_CNT);
- D16(WDOG_CTL);
- D32(WDOG_STAT);
-#endif
-#ifdef WDOGA_CNT
- parent = debugfs_create_dir("watchdog", top);
- D32(WDOGA_CNT);
- D16(WDOGA_CTL);
- D32(WDOGA_STAT);
- D32(WDOGB_CNT);
- D16(WDOGB_CTL);
- D32(WDOGB_STAT);
-#endif
-
- /* BF533 glue */
-#ifdef FIO_FLAG_D
-#define PORTFIO FIO_FLAG_D
-#endif
- /* BF561 glue */
-#ifdef FIO0_FLAG_D
-#define PORTFIO FIO0_FLAG_D
-#endif
-#ifdef FIO1_FLAG_D
-#define PORTGIO FIO1_FLAG_D
-#endif
-#ifdef FIO2_FLAG_D
-#define PORTHIO FIO2_FLAG_D
-#endif
- parent = debugfs_create_dir("port", top);
-#ifdef PORTFIO
- PORT(PORTFIO, 'F');
-#endif
-#ifdef PORTGIO
- PORT(PORTGIO, 'G');
-#endif
-#ifdef PORTHIO
- PORT(PORTHIO, 'H');
-#endif
-
-#ifdef __ADSPBF51x__
- D16(PORTF_FER);
- D16(PORTF_DRIVE);
- D16(PORTF_HYSTERESIS);
- D16(PORTF_MUX);
-
- D16(PORTG_FER);
- D16(PORTG_DRIVE);
- D16(PORTG_HYSTERESIS);
- D16(PORTG_MUX);
-
- D16(PORTH_FER);
- D16(PORTH_DRIVE);
- D16(PORTH_HYSTERESIS);
- D16(PORTH_MUX);
-
- D16(MISCPORT_DRIVE);
- D16(MISCPORT_HYSTERESIS);
-#endif /* BF51x */
-
-#ifdef __ADSPBF52x__
- D16(PORTF_FER);
- D16(PORTF_DRIVE);
- D16(PORTF_HYSTERESIS);
- D16(PORTF_MUX);
- D16(PORTF_SLEW);
-
- D16(PORTG_FER);
- D16(PORTG_DRIVE);
- D16(PORTG_HYSTERESIS);
- D16(PORTG_MUX);
- D16(PORTG_SLEW);
-
- D16(PORTH_FER);
- D16(PORTH_DRIVE);
- D16(PORTH_HYSTERESIS);
- D16(PORTH_MUX);
- D16(PORTH_SLEW);
-
- D16(MISCPORT_DRIVE);
- D16(MISCPORT_HYSTERESIS);
- D16(MISCPORT_SLEW);
-#endif /* BF52x */
-
-#ifdef BF537_FAMILY
- D16(PORTF_FER);
- D16(PORTG_FER);
- D16(PORTH_FER);
- D16(PORT_MUX);
-#endif /* BF534 BF536 BF537 */
-
-#ifdef BF538_FAMILY
- D16(PORTCIO_FER);
- D16(PORTCIO);
- D16(PORTCIO_CLEAR);
- D16(PORTCIO_SET);
- D16(PORTCIO_TOGGLE);
- D16(PORTCIO_DIR);
- D16(PORTCIO_INEN);
-
- D16(PORTDIO);
- D16(PORTDIO_CLEAR);
- D16(PORTDIO_DIR);
- D16(PORTDIO_FER);
- D16(PORTDIO_INEN);
- D16(PORTDIO_SET);
- D16(PORTDIO_TOGGLE);
-
- D16(PORTEIO);
- D16(PORTEIO_CLEAR);
- D16(PORTEIO_DIR);
- D16(PORTEIO_FER);
- D16(PORTEIO_INEN);
- D16(PORTEIO_SET);
- D16(PORTEIO_TOGGLE);
-#endif /* BF538 BF539 */
-
-#ifdef __ADSPBF54x__
- {
- int num;
- unsigned long base;
-
- base = PORTA_FER;
- for (num = 0; num < 10; ++num) {
- PORT(base, num);
- base += sizeof(struct bfin_gpio_regs);
- }
-
- }
-#endif /* BF54x */
-#endif /* CONFIG_BF60x */
- debug_mmrs_dentry = top;
-
- return 0;
-}
-module_init(bfin_debug_mmrs_init);
-
-static void __exit bfin_debug_mmrs_exit(void)
-{
- debugfs_remove_recursive(debug_mmrs_dentry);
-}
-module_exit(bfin_debug_mmrs_exit);
-
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
deleted file mode 100644
index 477bb29..0000000
--- a/arch/blackfin/kernel/dma-mapping.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Dynamic DMA mapping support
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/types.h>
-#include <linux/gfp.h>
-#include <linux/string.h>
-#include <linux/spinlock.h>
-#include <linux/dma-mapping.h>
-#include <linux/scatterlist.h>
-#include <linux/export.h>
-#include <linux/bitmap.h>
-
-static spinlock_t dma_page_lock;
-static unsigned long *dma_page;
-static unsigned int dma_pages;
-static unsigned long dma_base;
-static unsigned long dma_size;
-static unsigned int dma_initialized;
-
-static void dma_alloc_init(unsigned long start, unsigned long end)
-{
- spin_lock_init(&dma_page_lock);
- dma_initialized = 0;
-
- dma_page = (unsigned long *)__get_free_page(GFP_KERNEL);
- memset(dma_page, 0, PAGE_SIZE);
- dma_base = PAGE_ALIGN(start);
- dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start);
- dma_pages = dma_size >> PAGE_SHIFT;
- memset((void *)dma_base, 0, DMA_UNCACHED_REGION);
- dma_initialized = 1;
-
- printk(KERN_INFO "%s: dma_page @ 0x%p - %d pages at 0x%08lx\n", __func__,
- dma_page, dma_pages, dma_base);
-}
-
-static inline unsigned int get_pages(size_t size)
-{
- return ((size - 1) >> PAGE_SHIFT) + 1;
-}
-
-static unsigned long __alloc_dma_pages(unsigned int pages)
-{
- unsigned long ret = 0, flags;
- unsigned long start;
-
- if (dma_initialized == 0)
- dma_alloc_init(_ramend - DMA_UNCACHED_REGION, _ramend);
-
- spin_lock_irqsave(&dma_page_lock, flags);
-
- start = bitmap_find_next_zero_area(dma_page, dma_pages, 0, pages, 0);
- if (start < dma_pages) {
- ret = dma_base + (start << PAGE_SHIFT);
- bitmap_set(dma_page, start, pages);
- }
- spin_unlock_irqrestore(&dma_page_lock, flags);
- return ret;
-}
-
-static void __free_dma_pages(unsigned long addr, unsigned int pages)
-{
- unsigned long page = (addr - dma_base) >> PAGE_SHIFT;
- unsigned long flags;
-
- if ((page + pages) > dma_pages) {
- printk(KERN_ERR "%s: freeing outside range.\n", __func__);
- BUG();
- }
-
- spin_lock_irqsave(&dma_page_lock, flags);
- bitmap_clear(dma_page, page, pages);
- spin_unlock_irqrestore(&dma_page_lock, flags);
-}
-
-static void *bfin_dma_alloc(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
-{
- void *ret;
-
- ret = (void *)__alloc_dma_pages(get_pages(size));
-
- if (ret) {
- memset(ret, 0, size);
- *dma_handle = virt_to_phys(ret);
- }
-
- return ret;
-}
-
-static void bfin_dma_free(struct device *dev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- __free_dma_pages((unsigned long)vaddr, get_pages(size));
-}
-
-/*
- * Streaming DMA mappings
- */
-void __dma_sync(dma_addr_t addr, size_t size,
- enum dma_data_direction dir)
-{
- __dma_sync_inline(addr, size, dir);
-}
-EXPORT_SYMBOL(__dma_sync);
-
-static int bfin_dma_map_sg(struct device *dev, struct scatterlist *sg_list,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sg_list, sg, nents, i) {
- sg->dma_address = (dma_addr_t) sg_virt(sg);
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- continue;
-
- __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
- }
-
- return nents;
-}
-
-static void bfin_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sg_list, int nelems,
- enum dma_data_direction direction)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sg_list, sg, nelems, i) {
- sg->dma_address = (dma_addr_t) sg_virt(sg);
- __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
- }
-}
-
-static dma_addr_t bfin_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, enum dma_data_direction dir,
- unsigned long attrs)
-{
- dma_addr_t handle = (dma_addr_t)(page_address(page) + offset);
-
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- _dma_sync(handle, size, dir);
-
- return handle;
-}
-
-static inline void bfin_dma_sync_single_for_device(struct device *dev,
- dma_addr_t handle, size_t size, enum dma_data_direction dir)
-{
- _dma_sync(handle, size, dir);
-}
-
-const struct dma_map_ops bfin_dma_ops = {
- .alloc = bfin_dma_alloc,
- .free = bfin_dma_free,
-
- .map_page = bfin_dma_map_page,
- .map_sg = bfin_dma_map_sg,
-
- .sync_single_for_device = bfin_dma_sync_single_for_device,
- .sync_sg_for_device = bfin_dma_sync_sg_for_device,
-};
-EXPORT_SYMBOL(bfin_dma_ops);
diff --git a/arch/blackfin/kernel/dumpstack.c b/arch/blackfin/kernel/dumpstack.c
deleted file mode 100644
index 3c992c1..0000000
--- a/arch/blackfin/kernel/dumpstack.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Provide basic stack dumping functions
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <linux/thread_info.h>
-#include <linux/mm.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/sched/debug.h>
-
-#include <asm/trace.h>
-
-/*
- * Checks to see if the address pointed to is either a
- * 16-bit CALL instruction, or a 32-bit CALL instruction
- */
-static bool is_bfin_call(unsigned short *addr)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, addr))
- return false;
-
- if ((opcode >= 0x0060 && opcode <= 0x0067) ||
- (opcode >= 0x0070 && opcode <= 0x0077) ||
- (opcode >= 0xE3000000 && opcode <= 0xE3FFFFFF))
- return true;
-
- return false;
-
-}
-
-void show_stack(struct task_struct *task, unsigned long *stack)
-{
-#ifdef CONFIG_PRINTK
- unsigned int *addr, *endstack, *fp = 0, *frame;
- unsigned short *ins_addr;
- char buf[150];
- unsigned int i, j, ret_addr, frame_no = 0;
-
- /*
- * If we have been passed a specific stack, use that one otherwise
- * if we have been passed a task structure, use that, otherwise
- * use the stack of where the variable "stack" exists
- */
-
- if (stack == NULL) {
- if (task) {
- /* We know this is a kernel stack, so this is the start/end */
- stack = (unsigned long *)task->thread.ksp;
- endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE);
- } else {
- /* print out the existing stack info */
- stack = (unsigned long *)&stack;
- endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
- }
- } else
- endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
-
- printk(KERN_NOTICE "Stack info:\n");
- decode_address(buf, (unsigned int)stack);
- printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
-
- if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) {
- printk(KERN_NOTICE "Invalid stack pointer\n");
- return;
- }
-
- /* First thing is to look for a frame pointer */
- for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) {
- if (*addr & 0x1)
- continue;
- ins_addr = (unsigned short *)*addr;
- ins_addr--;
- if (is_bfin_call(ins_addr))
- fp = addr - 1;
-
- if (fp) {
- /* Let's check to see if it is a frame pointer */
- while (fp >= (addr - 1) && fp < endstack
- && fp && ((unsigned int) fp & 0x3) == 0)
- fp = (unsigned int *)*fp;
- if (fp == 0 || fp == endstack) {
- fp = addr - 1;
- break;
- }
- fp = 0;
- }
- }
- if (fp) {
- frame = fp;
- printk(KERN_NOTICE " FP: (0x%p)\n", fp);
- } else
- frame = 0;
-
- /*
- * Now that we think we know where things are, we
- * walk the stack again, this time printing things out
- * incase there is no frame pointer, we still look for
- * valid return addresses
- */
-
- /* First time print out data, next time, print out symbols */
- for (j = 0; j <= 1; j++) {
- if (j)
- printk(KERN_NOTICE "Return addresses in stack:\n");
- else
- printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack);
-
- fp = frame;
- frame_no = 0;
-
- for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0;
- addr < endstack; addr++, i++) {
-
- ret_addr = 0;
- if (!j && i % 8 == 0)
- printk(KERN_NOTICE "%p:", addr);
-
- /* if it is an odd address, or zero, just skip it */
- if (*addr & 0x1 || !*addr)
- goto print;
-
- ins_addr = (unsigned short *)*addr;
-
- /* Go back one instruction, and see if it is a CALL */
- ins_addr--;
- ret_addr = is_bfin_call(ins_addr);
- print:
- if (!j && stack == (unsigned long *)addr)
- printk("[%08x]", *addr);
- else if (ret_addr)
- if (j) {
- decode_address(buf, (unsigned int)*addr);
- if (frame == addr) {
- printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf);
- continue;
- }
- printk(KERN_NOTICE " address : %s\n", buf);
- } else
- printk("<%08x>", *addr);
- else if (fp == addr) {
- if (j)
- frame = addr+1;
- else
- printk("(%08x)", *addr);
-
- fp = (unsigned int *)*addr;
- frame_no++;
-
- } else if (!j)
- printk(" %08x ", *addr);
- }
- if (!j)
- printk("\n");
- }
-#endif
-}
-EXPORT_SYMBOL(show_stack);
-
-void dump_stack(void)
-{
- unsigned long stack;
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int tflags;
-#endif
- trace_buffer_save(tflags);
- dump_bfin_trace_buffer();
- dump_stack_print_info(KERN_DEFAULT);
- show_stack(current, &stack);
- trace_buffer_restore(tflags);
-}
-EXPORT_SYMBOL(dump_stack);
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c
deleted file mode 100644
index 4b89af9..0000000
--- a/arch/blackfin/kernel/early_printk.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * allow a console to be used for early printk
- * derived from arch/x86/kernel/early_printk.c
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/kernel.h>
-#include <linux/sched/debug.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/console.h>
-#include <linux/string.h>
-#include <linux/reboot.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/early_printk.h>
-
-#ifdef CONFIG_SERIAL_BFIN
-extern struct console *bfin_earlyserial_init(unsigned int port,
- unsigned int cflag);
-#endif
-#ifdef CONFIG_BFIN_JTAG_COMM
-extern struct console *bfin_jc_early_init(void);
-#endif
-
-/* Default console */
-#define DEFAULT_PORT 0
-#define DEFAULT_CFLAG CS8|B57600
-
-/* Default console for early crashes */
-#define DEFAULT_EARLY_PORT "serial,uart0,57600"
-
-#ifdef CONFIG_SERIAL_CORE
-/* What should get here is "0,57600" */
-static struct console * __init earlyserial_init(char *buf)
-{
- int baud, bit;
- char parity;
- unsigned int serial_port = DEFAULT_PORT;
- unsigned int cflag = DEFAULT_CFLAG;
-
- serial_port = simple_strtoul(buf, &buf, 10);
- buf++;
-
- cflag = 0;
- baud = simple_strtoul(buf, &buf, 10);
- switch (baud) {
- case 1200:
- cflag |= B1200;
- break;
- case 2400:
- cflag |= B2400;
- break;
- case 4800:
- cflag |= B4800;
- break;
- case 9600:
- cflag |= B9600;
- break;
- case 19200:
- cflag |= B19200;
- break;
- case 38400:
- cflag |= B38400;
- break;
- case 115200:
- cflag |= B115200;
- break;
- default:
- cflag |= B57600;
- }
-
- parity = buf[0];
- buf++;
- switch (parity) {
- case 'e':
- cflag |= PARENB;
- break;
- case 'o':
- cflag |= PARODD;
- break;
- }
-
- bit = simple_strtoul(buf, &buf, 10);
- switch (bit) {
- case 5:
- cflag |= CS5;
- break;
- case 6:
- cflag |= CS6;
- break;
- case 7:
- cflag |= CS7;
- break;
- default:
- cflag |= CS8;
- }
-
-#ifdef CONFIG_SERIAL_BFIN
- return bfin_earlyserial_init(serial_port, cflag);
-#else
- return NULL;
-#endif
-
-}
-#endif
-
-int __init setup_early_printk(char *buf)
-{
-
- /* Crashing in here would be really bad, so check both the var
- and the pointer before we start using it
- */
- if (!buf)
- return 0;
-
- if (!*buf)
- return 0;
-
- if (early_console != NULL)
- return 0;
-
-#ifdef CONFIG_SERIAL_BFIN
- /* Check for Blackfin Serial */
- if (!strncmp(buf, "serial,uart", 11)) {
- buf += 11;
- early_console = earlyserial_init(buf);
- }
-#endif
-
-#ifdef CONFIG_BFIN_JTAG_COMM
- /* Check for Blackfin JTAG */
- if (!strncmp(buf, "jtag", 4)) {
- buf += 4;
- early_console = bfin_jc_early_init();
- }
-#endif
-
-#ifdef CONFIG_FB
- /* TODO: add framebuffer console support */
-#endif
-
- if (likely(early_console)) {
- early_console->flags |= CON_BOOT;
-
- register_console(early_console);
- printk(KERN_INFO "early printk enabled on %s%d\n",
- early_console->name,
- early_console->index);
- }
-
- return 0;
-}
-
-/*
- * Set up a temporary Event Vector Table, so if something bad happens before
- * the kernel is fully started, it doesn't vector off into somewhere we don't
- * know
- */
-
-asmlinkage void __init init_early_exception_vectors(void)
-{
- u32 evt;
- SSYNC();
-
- /*
- * This starts up the shadow buffer, incase anything crashes before
- * setup arch
- */
- mark_shadow_error();
- early_shadow_puts(linux_banner);
- early_shadow_stamp();
-
- if (CPUID != bfin_cpuid()) {
- early_shadow_puts("Running on wrong machine type, expected");
- early_shadow_reg(CPUID, 16);
- early_shadow_puts(", but running on");
- early_shadow_reg(bfin_cpuid(), 16);
- early_shadow_puts("\n");
- }
-
- /* cannot program in software:
- * evt0 - emulation (jtag)
- * evt1 - reset
- */
- for (evt = EVT2; evt <= EVT15; evt += 4)
- bfin_write32(evt, early_trap);
- CSYNC();
-
- /* Set all the return from interrupt, exception, NMI to a known place
- * so if we do a RETI, RETX or RETN by mistake - we go somewhere known
- * Note - don't change RETS - we are in a subroutine, or
- * RETE - since it might screw up if emulator is attached
- */
- asm("\tRETI = %0; RETX = %0; RETN = %0;\n"
- : : "p"(early_trap));
-
-}
-
-__attribute__((__noreturn__))
-asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr)
-{
- /* This can happen before the uart is initialized, so initialize
- * the UART now (but only if we are running on the processor we think
- * we are compiled for - otherwise we write to MMRs that don't exist,
- * and cause other problems. Nothing comes out the UART, but it does
- * end up in the __buf_log.
- */
- if (likely(early_console == NULL) && CPUID == bfin_cpuid())
- setup_early_printk(DEFAULT_EARLY_PORT);
-
- if (!shadow_console_enabled()) {
- /* crap - we crashed before setup_arch() */
- early_shadow_puts("panic before setup_arch\n");
- early_shadow_puts("IPEND:");
- early_shadow_reg(fp->ipend, 16);
- if (fp->seqstat & SEQSTAT_EXCAUSE) {
- early_shadow_puts("\nEXCAUSE:");
- early_shadow_reg(fp->seqstat & SEQSTAT_EXCAUSE, 8);
- }
- if (fp->seqstat & SEQSTAT_HWERRCAUSE) {
- early_shadow_puts("\nHWERRCAUSE:");
- early_shadow_reg(
- (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14, 8);
- }
- early_shadow_puts("\nErr @");
- if (fp->ipend & EVT_EVX)
- early_shadow_reg(fp->retx, 32);
- else
- early_shadow_reg(fp->pc, 32);
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- early_shadow_puts("\nTrace:");
- if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
- while (bfin_read_TBUFSTAT() & TBUFCNT) {
- early_shadow_puts("\nT :");
- early_shadow_reg(bfin_read_TBUF(), 32);
- early_shadow_puts("\n S :");
- early_shadow_reg(bfin_read_TBUF(), 32);
- }
- }
-#endif
- early_shadow_puts("\nUse bfin-elf-addr2line to determine "
- "function names\n");
- /*
- * We should panic(), but we can't - since panic calls printk,
- * and printk uses memcpy.
- * we want to reboot, but if the machine type is different,
- * can't due to machine specific reboot sequences
- */
- if (CPUID == bfin_cpuid()) {
- early_shadow_puts("Trying to restart\n");
- machine_restart("");
- }
-
- early_shadow_puts("Halting, since it is not safe to restart\n");
- while (1)
- asm volatile ("EMUEXCPT; IDLE;\n");
-
- } else {
- printk(KERN_EMERG "Early panic\n");
- show_regs(fp);
- dump_bfin_trace_buffer();
- }
-
- panic("Died early");
-}
-
-early_param("earlyprintk", setup_early_printk);
diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S
deleted file mode 100644
index 4071265..0000000
--- a/arch/blackfin/kernel/entry.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/errno.h>
-#include <asm/blackfin.h>
-#include <asm/asm-offsets.h>
-
-#include <asm/context.S>
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-.section .l1.text
-#else
-.text
-#endif
-
-ENTRY(_ret_from_fork)
-#ifdef CONFIG_IPIPE
- /*
- * Hw IRQs are off on entry, and we don't want the scheduling tail
- * code to starve high priority domains from interrupts while it
- * runs. Therefore we first stall the root stage to have the
- * virtual interrupt state reflect IMASK.
- */
- p0.l = ___ipipe_root_status;
- p0.h = ___ipipe_root_status;
- r4 = [p0];
- bitset(r4, 0);
- [p0] = r4;
- /*
- * Then we may enable hw IRQs, allowing preemption from high
- * priority domains. schedule_tail() will do local_irq_enable()
- * since Blackfin does not define __ARCH_WANT_UNLOCKED_CTXSW, so
- * there is no need to unstall the root domain by ourselves
- * afterwards.
- */
- p0.l = _bfin_irq_flags;
- p0.h = _bfin_irq_flags;
- r4 = [p0];
- sti r4;
-#endif /* CONFIG_IPIPE */
- SP += -12;
- pseudo_long_call _schedule_tail, p5;
- SP += 12;
- p1 = [sp++];
- r0 = [sp++];
- cc = p1 == 0;
- if cc jump .Lfork;
- sp += -12;
- call (p1);
- sp += 12;
-.Lfork:
- RESTORE_CONTEXT
- rti;
-ENDPROC(_ret_from_fork)
diff --git a/arch/blackfin/kernel/exception.c b/arch/blackfin/kernel/exception.c
deleted file mode 100644
index 9208b5f..0000000
--- a/arch/blackfin/kernel/exception.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Basic functions for adding/removing custom exception handlers
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/module.h>
-#include <asm/irq_handler.h>
-
-int bfin_request_exception(unsigned int exception, void (*handler)(void))
-{
- void (*curr_handler)(void);
-
- if (exception > 0x3F)
- return -EINVAL;
-
- curr_handler = ex_table[exception];
-
- if (curr_handler != ex_replaceable)
- return -EBUSY;
-
- ex_table[exception] = handler;
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_request_exception);
-
-int bfin_free_exception(unsigned int exception, void (*handler)(void))
-{
- void (*curr_handler)(void);
-
- if (exception > 0x3F)
- return -EINVAL;
-
- curr_handler = ex_table[exception];
-
- if (curr_handler != handler)
- return -EBUSY;
-
- ex_table[exception] = ex_replaceable;
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_free_exception);
diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S
deleted file mode 100644
index 0565917..0000000
--- a/arch/blackfin/kernel/fixed_code.S
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * This file contains sequences of code that will be copied to a
- * fixed location, defined in <asm/fixed_code.h>. The interrupt
- * handlers ensure that these sequences appear to be atomic when
- * executed from userspace.
- * These are aligned to 16 bytes, so that we have some space to replace
- * these sequences with something else (e.g. kernel traps if we ever do
- * BF561 SMP).
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <linux/unistd.h>
-#include <asm/entry.h>
-
-__INIT
-
-ENTRY(_fixed_code_start)
-
-.align 16
-ENTRY(_sigreturn_stub)
- P0 = __NR_rt_sigreturn;
- EXCPT 0;
- /* Speculative execution paranoia. */
-0: JUMP.S 0b;
-ENDPROC (_sigreturn_stub)
-
-.align 16
- /*
- * Atomic swap, 8 bit.
- * Inputs: P0: memory address to use
- * R1: value to store
- * Output: R0: old contents of the memory address, zero extended.
- */
-ENTRY(_atomic_xchg32)
- R0 = [P0];
- [P0] = R1;
- rts;
-ENDPROC (_atomic_xchg32)
-
-.align 16
- /*
- * Compare and swap, 32 bit.
- * Inputs: P0: memory address to use
- * R1: compare value
- * R2: new value to store
- * The new value is stored if the contents of the memory
- * address is equal to the compare value.
- * Output: R0: old contents of the memory address.
- */
-ENTRY(_atomic_cas32)
- R0 = [P0];
- CC = R0 == R1;
- IF !CC JUMP 1f;
- [P0] = R2;
-1:
- rts;
-ENDPROC (_atomic_cas32)
-
-.align 16
- /*
- * Atomic add, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to add
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_add32)
- R1 = [P0];
- R0 = R1 + R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_add32)
-
-.align 16
- /*
- * Atomic sub, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to subtract
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_sub32)
- R1 = [P0];
- R0 = R1 - R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_sub32)
-
-.align 16
- /*
- * Atomic ior, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to ior
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_ior32)
- R1 = [P0];
- R0 = R1 | R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_ior32)
-
-.align 16
- /*
- * Atomic and, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to and
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_and32)
- R1 = [P0];
- R0 = R1 & R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_and32)
-
-.align 16
- /*
- * Atomic xor, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to xor
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_xor32)
- R1 = [P0];
- R0 = R1 ^ R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_xor32)
-
-.align 16
- /*
- * safe_user_instruction
- * Four NOPS are enough to allow the pipeline to speculativily load
- * execute anything it wants. After that, things have gone bad, and
- * we are stuck - so panic. Since we might be in user space, we can't
- * call panic, so just cause a unhandled exception, this should cause
- * a dump of the trace buffer so we can tell were we are, and a reboot
- */
-ENTRY(_safe_user_instruction)
- NOP; NOP; NOP; NOP;
- EXCPT 0x4;
-ENDPROC(_safe_user_instruction)
-
-ENTRY(_fixed_code_end)
-
-__FINIT
diff --git a/arch/blackfin/kernel/flat.c b/arch/blackfin/kernel/flat.c
deleted file mode 100644
index 8ebc54d..0000000
--- a/arch/blackfin/kernel/flat.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/mm_types.h>
-#include <linux/flat.h>
-
-#define FLAT_BFIN_RELOC_TYPE_16_BIT 0
-#define FLAT_BFIN_RELOC_TYPE_16H_BIT 1
-#define FLAT_BFIN_RELOC_TYPE_32_BIT 2
-
-unsigned long bfin_get_addr_from_rp(u32 *ptr,
- u32 relval,
- u32 flags,
- u32 *persistent)
-{
- unsigned short *usptr = (unsigned short *)ptr;
- int type = (relval >> 26) & 7;
- u32 val;
-
- switch (type) {
- case FLAT_BFIN_RELOC_TYPE_16_BIT:
- case FLAT_BFIN_RELOC_TYPE_16H_BIT:
- usptr = (unsigned short *)ptr;
- pr_debug("*usptr = %x", get_unaligned(usptr));
- val = get_unaligned(usptr);
- val += *persistent;
- break;
-
- case FLAT_BFIN_RELOC_TYPE_32_BIT:
- pr_debug("*ptr = %x", get_unaligned(ptr));
- val = get_unaligned(ptr);
- break;
-
- default:
- pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", type);
- return 0;
- }
-
- /*
- * Stack-relative relocs contain the offset into the stack, we
- * have to add the stack's start address here and return 1 from
- * flat_addr_absolute to prevent the normal address calculations
- */
- if (relval & (1 << 29))
- return val + current->mm->context.end_brk;
-
- if ((flags & FLAT_FLAG_GOTPIC) == 0)
- val = htonl(val);
- return val;
-}
-EXPORT_SYMBOL(bfin_get_addr_from_rp);
-
-/*
- * Insert the address ADDR into the symbol reference at RP;
- * RELVAL is the raw relocation-table entry from which RP is derived
- */
-void bfin_put_addr_at_rp(u32 *ptr, u32 addr, u32 relval)
-{
- unsigned short *usptr = (unsigned short *)ptr;
- int type = (relval >> 26) & 7;
-
- switch (type) {
- case FLAT_BFIN_RELOC_TYPE_16_BIT:
- put_unaligned(addr, usptr);
- pr_debug("new value %x at %p", get_unaligned(usptr), usptr);
- break;
-
- case FLAT_BFIN_RELOC_TYPE_16H_BIT:
- put_unaligned(addr >> 16, usptr);
- pr_debug("new value %x", get_unaligned(usptr));
- break;
-
- case FLAT_BFIN_RELOC_TYPE_32_BIT:
- put_unaligned(addr, ptr);
- pr_debug("new ptr =%x", get_unaligned(ptr));
- break;
- }
-}
-EXPORT_SYMBOL(bfin_put_addr_at_rp);
diff --git a/arch/blackfin/kernel/ftrace-entry.S b/arch/blackfin/kernel/ftrace-entry.S
deleted file mode 100644
index 3b8bdcb..0000000
--- a/arch/blackfin/kernel/ftrace-entry.S
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * mcount and friends -- ftrace stuff
- *
- * Copyright (C) 2009-2010 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/ftrace.h>
-
-.text
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-/* Simple stub so we can boot the kernel until runtime patching has
- * disabled all calls to this. Then it'll be unused.
- */
-ENTRY(__mcount)
-# if ANOMALY_05000371
- nop; nop; nop; nop;
-# endif
- rts;
-ENDPROC(__mcount)
-
-/* GCC will have called us before setting up the function prologue, so we
- * can clobber the normal scratch registers, but we need to make sure to
- * save/restore the registers used for argument passing (R0-R2) in case
- * the profiled function is using them. With data registers, R3 is the
- * only one we can blow away. With pointer registers, we have P0-P2.
- *
- * Upon entry, the RETS will point to the top of the current profiled
- * function. And since GCC pushed the previous RETS for us, the previous
- * function will be waiting there. mmmm pie.
- */
-ENTRY(_ftrace_caller)
- /* save first/second/third function arg and the return register */
- [--sp] = r2;
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* function_trace_call(unsigned long ip, unsigned long parent_ip):
- * ip: this point was called by ...
- * parent_ip: ... this function
- * the ip itself will need adjusting for the mcount call
- */
- r0 = rets;
- r1 = [sp + 16]; /* skip the 4 local regs on stack */
- r0 += -MCOUNT_INSN_SIZE;
-
-.globl _ftrace_call
-_ftrace_call:
- call _ftrace_stub
-
-# ifdef CONFIG_FUNCTION_GRAPH_TRACER
-.globl _ftrace_graph_call
-_ftrace_graph_call:
- nop; /* jump _ftrace_graph_caller; */
-# endif
-
- /* restore state and get out of dodge */
-.Lfinish_trace:
- rets = [sp++];
- r1 = [sp++];
- r0 = [sp++];
- r2 = [sp++];
-
-.globl _ftrace_stub
-_ftrace_stub:
- rts;
-ENDPROC(_ftrace_caller)
-
-#else
-
-/* See documentation for _ftrace_caller */
-ENTRY(__mcount)
- /* save third function arg early so we can do testing below */
- [--sp] = r2;
-
- /* load the function pointer to the tracer */
- p0.l = _ftrace_trace_function;
- p0.h = _ftrace_trace_function;
- r3 = [p0];
-
- /* optional micro optimization: don't call the stub tracer */
- r2.l = _ftrace_stub;
- r2.h = _ftrace_stub;
- cc = r2 == r3;
- if ! cc jump .Ldo_trace;
-
-# ifdef CONFIG_FUNCTION_GRAPH_TRACER
- /* if the ftrace_graph_return function pointer is not set to
- * the ftrace_stub entry, call prepare_ftrace_return().
- */
- p0.l = _ftrace_graph_return;
- p0.h = _ftrace_graph_return;
- r3 = [p0];
- cc = r2 == r3;
- if ! cc jump _ftrace_graph_caller;
-
- /* similarly, if the ftrace_graph_entry function pointer is not
- * set to the ftrace_graph_entry_stub entry, ...
- */
- p0.l = _ftrace_graph_entry;
- p0.h = _ftrace_graph_entry;
- r2.l = _ftrace_graph_entry_stub;
- r2.h = _ftrace_graph_entry_stub;
- r3 = [p0];
- cc = r2 == r3;
- if ! cc jump _ftrace_graph_caller;
-# endif
-
- r2 = [sp++];
- rts;
-
-.Ldo_trace:
-
- /* save first/second function arg and the return register */
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* setup the tracer function */
- p0 = r3;
-
- /* function_trace_call(unsigned long ip, unsigned long parent_ip):
- * ip: this point was called by ...
- * parent_ip: ... this function
- * the ip itself will need adjusting for the mcount call
- */
- r0 = rets;
- r1 = [sp + 16]; /* skip the 4 local regs on stack */
- r0 += -MCOUNT_INSN_SIZE;
-
- /* call the tracer */
- call (p0);
-
- /* restore state and get out of dodge */
-.Lfinish_trace:
- rets = [sp++];
- r1 = [sp++];
- r0 = [sp++];
- r2 = [sp++];
-
-.globl _ftrace_stub
-_ftrace_stub:
- rts;
-ENDPROC(__mcount)
-
-#endif
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-/* The prepare_ftrace_return() function is similar to the trace function
- * except it takes a pointer to the location of the frompc. This is so
- * the prepare_ftrace_return() can hijack it temporarily for probing
- * purposes.
- */
-ENTRY(_ftrace_graph_caller)
-# ifndef CONFIG_DYNAMIC_FTRACE
- /* save first/second function arg and the return register */
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* prepare_ftrace_return(parent, self_addr, frame_pointer) */
- r0 = sp; /* unsigned long *parent */
- r1 = rets; /* unsigned long self_addr */
-# else
- r0 = sp; /* unsigned long *parent */
- r1 = [sp]; /* unsigned long self_addr */
-# endif
-# ifdef HAVE_FUNCTION_GRAPH_FP_TEST
- r2 = fp; /* unsigned long frame_pointer */
-# endif
- r0 += 16; /* skip the 4 local regs on stack */
- r1 += -MCOUNT_INSN_SIZE;
- call _prepare_ftrace_return;
-
- jump .Lfinish_trace;
-ENDPROC(_ftrace_graph_caller)
-
-/* Undo the rewrite caused by ftrace_graph_caller(). The common function
- * ftrace_return_to_handler() will return the original rets so we can
- * restore it and be on our way.
- */
-ENTRY(_return_to_handler)
- /* make sure original return values are saved */
- [--sp] = p0;
- [--sp] = r0;
- [--sp] = r1;
-
- /* get original return address */
-# ifdef HAVE_FUNCTION_GRAPH_FP_TEST
- r0 = fp; /* Blackfin is sane, so omit this */
-# endif
- call _ftrace_return_to_handler;
- rets = r0;
-
- /* anomaly 05000371 - make sure we have at least three instructions
- * between rets setting and the return
- */
- r1 = [sp++];
- r0 = [sp++];
- p0 = [sp++];
- rts;
-ENDPROC(_return_to_handler)
-#endif
diff --git a/arch/blackfin/kernel/ftrace.c b/arch/blackfin/kernel/ftrace.c
deleted file mode 100644
index 8dad758..0000000
--- a/arch/blackfin/kernel/ftrace.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * ftrace graph code
- *
- * Copyright (C) 2009-2010 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ftrace.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/uaccess.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-static const unsigned char mnop[] = {
- 0x03, 0xc0, 0x00, 0x18, /* MNOP; */
- 0x03, 0xc0, 0x00, 0x18, /* MNOP; */
-};
-
-static void bfin_make_pcrel24(unsigned char *insn, unsigned long src,
- unsigned long dst)
-{
- uint32_t pcrel = (dst - src) >> 1;
- insn[0] = pcrel >> 16;
- insn[1] = 0xe3;
- insn[2] = pcrel;
- insn[3] = pcrel >> 8;
-}
-#define bfin_make_pcrel24(insn, src, dst) bfin_make_pcrel24(insn, src, (unsigned long)(dst))
-
-static int ftrace_modify_code(unsigned long ip, const unsigned char *code,
- unsigned long len)
-{
- int ret = probe_kernel_write((void *)ip, (void *)code, len);
- flush_icache_range(ip, ip + len);
- return ret;
-}
-
-int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
- unsigned long addr)
-{
- /* Turn the mcount call site into two MNOPs as those are 32bit insns */
- return ftrace_modify_code(rec->ip, mnop, sizeof(mnop));
-}
-
-int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
-{
- /* Restore the mcount call site */
- unsigned char call[8];
- call[0] = 0x67; /* [--SP] = RETS; */
- call[1] = 0x01;
- bfin_make_pcrel24(&call[2], rec->ip + 2, addr);
- call[6] = 0x27; /* RETS = [SP++]; */
- call[7] = 0x01;
- return ftrace_modify_code(rec->ip, call, sizeof(call));
-}
-
-int ftrace_update_ftrace_func(ftrace_func_t func)
-{
- unsigned char call[4];
- unsigned long ip = (unsigned long)&ftrace_call;
- bfin_make_pcrel24(call, ip, func);
- return ftrace_modify_code(ip, call, sizeof(call));
-}
-
-int __init ftrace_dyn_arch_init(void)
-{
- return 0;
-}
-
-#endif
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-
-# ifdef CONFIG_DYNAMIC_FTRACE
-
-extern void ftrace_graph_call(void);
-
-int ftrace_enable_ftrace_graph_caller(void)
-{
- unsigned long ip = (unsigned long)&ftrace_graph_call;
- uint16_t jump_pcrel12 = ((unsigned long)&ftrace_graph_caller - ip) >> 1;
- jump_pcrel12 |= 0x2000;
- return ftrace_modify_code(ip, (void *)&jump_pcrel12, sizeof(jump_pcrel12));
-}
-
-int ftrace_disable_ftrace_graph_caller(void)
-{
- return ftrace_modify_code((unsigned long)&ftrace_graph_call, empty_zero_page, 2);
-}
-
-# endif
-
-/*
- * Hook the return address and push it in the stack of return addrs
- * in current thread info.
- */
-void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
- unsigned long frame_pointer)
-{
- struct ftrace_graph_ent trace;
- unsigned long return_hooker = (unsigned long)&return_to_handler;
-
- if (unlikely(atomic_read(¤t->tracing_graph_pause)))
- return;
-
- if (ftrace_push_return_trace(*parent, self_addr, &trace.depth,
- frame_pointer, NULL) == -EBUSY)
- return;
-
- trace.func = self_addr;
-
- /* Only trace if the calling function expects to */
- if (!ftrace_graph_entry(&trace)) {
- current->curr_ret_stack--;
- return;
- }
-
- /* all is well in the world ! hijack RETS ... */
- *parent = return_hooker;
-}
-
-#endif
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
deleted file mode 100644
index d776773..0000000
--- a/arch/blackfin/kernel/gptimers.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * gptimers.c - Blackfin General Purpose Timer core API
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2005 John DeHority
- * Copyright (C) 2006 Hella Aglaia GmbH (awe at aglaia-gmbh.de)
- *
- * Licensed under the GPLv2.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-
-#include <asm/blackfin.h>
-#include <asm/gptimers.h>
-
-#ifdef DEBUG
-# define tassert(expr)
-#else
-# define tassert(expr) \
- if (!(expr)) \
- printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__);
-#endif
-
-#ifndef CONFIG_BF60x
-# define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
-#else
-# define BFIN_TIMER_NUM_GROUP 1
-#endif
-
-static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
-{
- (void *)TIMER0_CONFIG,
- (void *)TIMER1_CONFIG,
- (void *)TIMER2_CONFIG,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- (void *)TIMER3_CONFIG,
- (void *)TIMER4_CONFIG,
- (void *)TIMER5_CONFIG,
- (void *)TIMER6_CONFIG,
- (void *)TIMER7_CONFIG,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- (void *)TIMER8_CONFIG,
- (void *)TIMER9_CONFIG,
- (void *)TIMER10_CONFIG,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- (void *)TIMER11_CONFIG,
-# endif
-# endif
-#endif
-};
-
-static struct bfin_gptimer_group_regs * const group_regs[BFIN_TIMER_NUM_GROUP] =
-{
- (void *)TIMER0_GROUP_REG,
-#if (MAX_BLACKFIN_GPTIMERS > 8)
- (void *)TIMER8_GROUP_REG,
-#endif
-};
-
-static uint32_t const trun_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TRUN0,
- TIMER_STATUS_TRUN1,
- TIMER_STATUS_TRUN2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TRUN3,
- TIMER_STATUS_TRUN4,
- TIMER_STATUS_TRUN5,
- TIMER_STATUS_TRUN6,
- TIMER_STATUS_TRUN7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TRUN8,
- TIMER_STATUS_TRUN9,
- TIMER_STATUS_TRUN10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TRUN11,
-# endif
-# endif
-#endif
-};
-
-static uint32_t const tovf_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TOVF0,
- TIMER_STATUS_TOVF1,
- TIMER_STATUS_TOVF2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TOVF3,
- TIMER_STATUS_TOVF4,
- TIMER_STATUS_TOVF5,
- TIMER_STATUS_TOVF6,
- TIMER_STATUS_TOVF7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TOVF8,
- TIMER_STATUS_TOVF9,
- TIMER_STATUS_TOVF10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TOVF11,
-# endif
-# endif
-#endif
-};
-
-static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TIMIL0,
- TIMER_STATUS_TIMIL1,
- TIMER_STATUS_TIMIL2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TIMIL3,
- TIMER_STATUS_TIMIL4,
- TIMER_STATUS_TIMIL5,
- TIMER_STATUS_TIMIL6,
- TIMER_STATUS_TIMIL7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TIMIL8,
- TIMER_STATUS_TIMIL9,
- TIMER_STATUS_TIMIL10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TIMIL11,
-# endif
-# endif
-#endif
-};
-
-void set_gptimer_pwidth(unsigned int timer_id, uint32_t value)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->width, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_pwidth);
-
-uint32_t get_gptimer_pwidth(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->width);
-}
-EXPORT_SYMBOL(get_gptimer_pwidth);
-
-void set_gptimer_period(unsigned int timer_id, uint32_t period)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->period, period);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_period);
-
-uint32_t get_gptimer_period(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->period);
-}
-EXPORT_SYMBOL(get_gptimer_period);
-
-uint32_t get_gptimer_count(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->counter);
-}
-EXPORT_SYMBOL(get_gptimer_count);
-
-#ifdef CONFIG_BF60x
-void set_gptimer_delay(unsigned int timer_id, uint32_t delay)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->delay, delay);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_delay);
-
-uint32_t get_gptimer_delay(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->delay);
-}
-EXPORT_SYMBOL(get_gptimer_delay);
-#endif
-
-#ifdef CONFIG_BF60x
-int get_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat) & timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_intr);
-
-void clear_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat, timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_intr);
-
-int get_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat) & tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_over);
-
-void clear_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat, tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_over);
-
-int get_gptimer_run(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->run) & trun_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_run);
-
-uint32_t get_gptimer_status(unsigned int group)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- return bfin_read(&group_regs[group]->data_ilat);
-}
-EXPORT_SYMBOL(get_gptimer_status);
-
-void set_gptimer_status(unsigned int group, uint32_t value)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- bfin_write(&group_regs[group]->data_ilat, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_status);
-#else
-uint32_t get_gptimer_status(unsigned int group)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- return bfin_read(&group_regs[group]->status);
-}
-EXPORT_SYMBOL(get_gptimer_status);
-
-void set_gptimer_status(unsigned int group, uint32_t value)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- bfin_write(&group_regs[group]->status, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_status);
-
-static uint32_t read_gptimer_status(unsigned int timer_id)
-{
- return bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status);
-}
-
-int get_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_intr);
-
-void clear_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_intr);
-
-int get_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_over);
-
-void clear_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_over);
-
-int get_gptimer_run(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_run);
-#endif
-
-void set_gptimer_config(unsigned int timer_id, uint16_t config)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->config, config);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_config);
-
-uint16_t get_gptimer_config(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->config);
-}
-EXPORT_SYMBOL(get_gptimer_config);
-
-void enable_gptimers(uint16_t mask)
-{
- int i;
-#ifdef CONFIG_BF60x
- uint16_t imask;
- imask = bfin_read16(TIMER_DATA_IMSK);
- imask &= ~mask;
- bfin_write16(TIMER_DATA_IMSK, imask);
-#endif
- tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
- bfin_write(&group_regs[i]->enable, mask & 0xFF);
- mask >>= 8;
- }
- SSYNC();
-}
-EXPORT_SYMBOL(enable_gptimers);
-
-static void _disable_gptimers(uint16_t mask)
-{
- int i;
- uint16_t m = mask;
- tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
- bfin_write(&group_regs[i]->disable, m & 0xFF);
- m >>= 8;
- }
-}
-
-void disable_gptimers(uint16_t mask)
-{
-#ifndef CONFIG_BF60x
- int i;
- _disable_gptimers(mask);
- for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
- if (mask & (1 << i))
- bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
- SSYNC();
-#else
- _disable_gptimers(mask);
-#endif
-}
-EXPORT_SYMBOL(disable_gptimers);
-
-void disable_gptimers_sync(uint16_t mask)
-{
- _disable_gptimers(mask);
- SSYNC();
-}
-EXPORT_SYMBOL(disable_gptimers_sync);
-
-void set_gptimer_pulse_hi(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write_or(&timer_regs[timer_id]->config, TIMER_PULSE_HI);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_pulse_hi);
-
-void clear_gptimer_pulse_hi(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write_and(&timer_regs[timer_id]->config, ~TIMER_PULSE_HI);
- SSYNC();
-}
-EXPORT_SYMBOL(clear_gptimer_pulse_hi);
-
-uint16_t get_enabled_gptimers(void)
-{
- int i;
- uint16_t result = 0;
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i)
- result |= (bfin_read(&group_regs[i]->enable) << (i << 3));
- return result;
-}
-EXPORT_SYMBOL(get_enabled_gptimers);
-
-MODULE_AUTHOR("Axel Weiss (awe@aglaia-gmbh.de)");
-MODULE_DESCRIPTION("Blackfin General Purpose Timers API");
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
deleted file mode 100644
index f657b38..0000000
--- a/arch/blackfin/kernel/ipipe.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/* -*- linux-c -*-
- * linux/arch/blackfin/kernel/ipipe.c
- *
- * Copyright (C) 2005-2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Architecture-dependent I-pipe support for the Blackfin.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/percpu.h>
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <linux/kthread.h>
-#include <linux/unistd.h>
-#include <linux/io.h>
-#include <linux/atomic.h>
-#include <asm/irq_handler.h>
-
-DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
-
-asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-
-static void __ipipe_no_irqtail(void);
-
-unsigned long __ipipe_irq_tail_hook = (unsigned long)&__ipipe_no_irqtail;
-EXPORT_SYMBOL(__ipipe_irq_tail_hook);
-
-unsigned long __ipipe_core_clock;
-EXPORT_SYMBOL(__ipipe_core_clock);
-
-unsigned long __ipipe_freq_scale;
-EXPORT_SYMBOL(__ipipe_freq_scale);
-
-atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
-
-unsigned long __ipipe_irq_lvmask = bfin_no_irqs;
-EXPORT_SYMBOL(__ipipe_irq_lvmask);
-
-static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc)
-{
- desc->ipipe_ack(irq, desc);
-}
-
-/*
- * __ipipe_enable_pipeline() -- We are running on the boot CPU, hw
- * interrupts are off, and secondary CPUs are still lost in space.
- */
-void __ipipe_enable_pipeline(void)
-{
- unsigned irq;
-
- __ipipe_core_clock = get_cclk(); /* Fetch this once. */
- __ipipe_freq_scale = 1000000000UL / __ipipe_core_clock;
-
- for (irq = 0; irq < NR_IRQS; ++irq)
- ipipe_virtualize_irq(ipipe_root_domain,
- irq,
- (ipipe_irq_handler_t)&asm_do_IRQ,
- NULL,
- &__ipipe_ack_irq,
- IPIPE_HANDLE_MASK | IPIPE_PASS_MASK);
-}
-
-/*
- * __ipipe_handle_irq() -- IPIPE's generic IRQ handler. An optimistic
- * interrupt protection log is maintained here for each domain. Hw
- * interrupts are masked on entry.
- */
-void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
- struct ipipe_domain *this_domain, *next_domain;
- struct list_head *head, *pos;
- struct ipipe_irqdesc *idesc;
- int m_ack, s = -1;
-
- /*
- * Software-triggered IRQs do not need any ack. The contents
- * of the register frame should only be used when processing
- * the timer interrupt, but not for handling any other
- * interrupt.
- */
- m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
- this_domain = __ipipe_current_domain;
- idesc = &this_domain->irqs[irq];
-
- if (unlikely(test_bit(IPIPE_STICKY_FLAG, &idesc->control)))
- head = &this_domain->p_link;
- else {
- head = __ipipe_pipeline.next;
- next_domain = list_entry(head, struct ipipe_domain, p_link);
- idesc = &next_domain->irqs[irq];
- if (likely(test_bit(IPIPE_WIRED_FLAG, &idesc->control))) {
- if (!m_ack && idesc->acknowledge != NULL)
- idesc->acknowledge(irq, irq_to_desc(irq));
- if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
- s = __test_and_set_bit(IPIPE_STALL_FLAG,
- &p->status);
- __ipipe_dispatch_wired(next_domain, irq);
- goto out;
- }
- }
-
- /* Ack the interrupt. */
-
- pos = head;
- while (pos != &__ipipe_pipeline) {
- next_domain = list_entry(pos, struct ipipe_domain, p_link);
- idesc = &next_domain->irqs[irq];
- if (test_bit(IPIPE_HANDLE_FLAG, &idesc->control)) {
- __ipipe_set_irq_pending(next_domain, irq);
- if (!m_ack && idesc->acknowledge != NULL) {
- idesc->acknowledge(irq, irq_to_desc(irq));
- m_ack = 1;
- }
- }
- if (!test_bit(IPIPE_PASS_FLAG, &idesc->control))
- break;
- pos = next_domain->p_link.next;
- }
-
- /*
- * Now walk the pipeline, yielding control to the highest
- * priority domain that has pending interrupt(s) or
- * immediately to the current domain if the interrupt has been
- * marked as 'sticky'. This search does not go beyond the
- * current domain in the pipeline. We also enforce the
- * additional root stage lock (blackfin-specific).
- */
- if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
- s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
-
- /*
- * If the interrupt preempted the head domain, then do not
- * even try to walk the pipeline, unless an interrupt is
- * pending for it.
- */
- if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) &&
- !__ipipe_ipending_p(ipipe_head_cpudom_ptr()))
- goto out;
-
- __ipipe_walk_pipeline(head);
-out:
- if (!s)
- __clear_bit(IPIPE_STALL_FLAG, &p->status);
-}
-
-void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
-{
- struct irq_desc *desc = irq_to_desc(irq);
- int prio = __ipipe_get_irq_priority(irq);
-
- desc->depth = 0;
- if (ipd != &ipipe_root &&
- atomic_inc_return(&__ipipe_irq_lvdepth[prio]) == 1)
- __set_bit(prio, &__ipipe_irq_lvmask);
-}
-EXPORT_SYMBOL(__ipipe_enable_irqdesc);
-
-void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
-{
- int prio = __ipipe_get_irq_priority(irq);
-
- if (ipd != &ipipe_root &&
- atomic_dec_and_test(&__ipipe_irq_lvdepth[prio]))
- __clear_bit(prio, &__ipipe_irq_lvmask);
-}
-EXPORT_SYMBOL(__ipipe_disable_irqdesc);
-
-asmlinkage int __ipipe_syscall_root(struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p;
- void (*hook)(void);
- int ret;
-
- WARN_ON_ONCE(irqs_disabled_hw());
-
- /*
- * We need to run the IRQ tail hook each time we intercept a
- * syscall, because we know that important operations might be
- * pending there (e.g. Xenomai deferred rescheduling).
- */
- hook = (__typeof__(hook))__ipipe_irq_tail_hook;
- hook();
-
- /*
- * This routine either returns:
- * 0 -- if the syscall is to be passed to Linux;
- * >0 -- if the syscall should not be passed to Linux, and no
- * tail work should be performed;
- * <0 -- if the syscall should not be passed to Linux but the
- * tail work has to be performed (for handling signals etc).
- */
-
- if (!__ipipe_syscall_watched_p(current, regs->orig_p0) ||
- !__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL))
- return 0;
-
- ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs);
-
- hard_local_irq_disable();
-
- /*
- * This is the end of the syscall path, so we may
- * safely assume a valid Linux task stack here.
- */
- if (current->ipipe_flags & PF_EVTRET) {
- current->ipipe_flags &= ~PF_EVTRET;
- __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
- }
-
- if (!__ipipe_root_domain_p)
- ret = -1;
- else {
- p = ipipe_root_cpudom_ptr();
- if (__ipipe_ipending_p(p))
- __ipipe_sync_pipeline();
- }
-
- hard_local_irq_enable();
-
- return -ret;
-}
-
-static void __ipipe_no_irqtail(void)
-{
-}
-
-int ipipe_get_sysinfo(struct ipipe_sysinfo *info)
-{
- info->sys_nr_cpus = num_online_cpus();
- info->sys_cpu_freq = ipipe_cpu_freq();
- info->sys_hrtimer_irq = IPIPE_TIMER_IRQ;
- info->sys_hrtimer_freq = __ipipe_core_clock;
- info->sys_hrclock_freq = __ipipe_core_clock;
-
- return 0;
-}
-
-/*
- * ipipe_trigger_irq() -- Push the interrupt at front of the pipeline
- * just like if it has been actually received from a hw source. Also
- * works for virtual interrupts.
- */
-int ipipe_trigger_irq(unsigned irq)
-{
- unsigned long flags;
-
-#ifdef CONFIG_IPIPE_DEBUG
- if (irq >= IPIPE_NR_IRQS ||
- (ipipe_virtual_irq_p(irq)
- && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
- return -EINVAL;
-#endif
-
- flags = hard_local_irq_save();
- __ipipe_handle_irq(irq, NULL);
- hard_local_irq_restore(flags);
-
- return 1;
-}
-
-asmlinkage void __ipipe_sync_root(void)
-{
- void (*irq_tail_hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
- struct ipipe_percpu_domain_data *p;
- unsigned long flags;
-
- BUG_ON(irqs_disabled());
-
- flags = hard_local_irq_save();
-
- if (irq_tail_hook)
- irq_tail_hook();
-
- clear_thread_flag(TIF_IRQ_SYNC);
-
- p = ipipe_root_cpudom_ptr();
- if (__ipipe_ipending_p(p))
- __ipipe_sync_pipeline();
-
- hard_local_irq_restore(flags);
-}
-
-void ___ipipe_sync_pipeline(void)
-{
- if (__ipipe_root_domain_p &&
- test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)))
- return;
-
- __ipipe_sync_stage();
-}
-
-void __ipipe_disable_root_irqs_hw(void)
-{
- /*
- * This code is called by the ins{bwl} routines (see
- * arch/blackfin/lib/ins.S), which are heavily used by the
- * network stack. It masks all interrupts but those handled by
- * non-root domains, so that we keep decent network transfer
- * rates for Linux without inducing pathological jitter for
- * the real-time domain.
- */
- bfin_sti(__ipipe_irq_lvmask);
- __set_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
-}
-
-void __ipipe_enable_root_irqs_hw(void)
-{
- __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
- bfin_sti(bfin_irq_flags);
-}
-
-/*
- * We could use standard atomic bitops in the following root status
- * manipulation routines, but let's prepare for SMP support in the
- * same move, preventing CPU migration as required.
- */
-void __ipipe_stall_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __set_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_stall_root);
-
-unsigned long __ipipe_test_and_stall_root(void)
-{
- unsigned long *p, flags;
- int x;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- x = __test_and_set_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore(flags);
-
- return x;
-}
-EXPORT_SYMBOL(__ipipe_test_and_stall_root);
-
-unsigned long __ipipe_test_root(void)
-{
- const unsigned long *p;
- unsigned long flags;
- int x;
-
- flags = hard_local_irq_save_smp();
- p = &__ipipe_root_status;
- x = test_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore_smp(flags);
-
- return x;
-}
-EXPORT_SYMBOL(__ipipe_test_root);
-
-void __ipipe_lock_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __set_bit(IPIPE_SYNCDEFER_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_lock_root);
-
-void __ipipe_unlock_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __clear_bit(IPIPE_SYNCDEFER_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_unlock_root);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
deleted file mode 100644
index 052cde5..0000000
--- a/arch/blackfin/kernel/irqchip.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/random.h>
-#include <linux/seq_file.h>
-#include <linux/kallsyms.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/seq_file.h>
-#include <asm/irq_handler.h>
-#include <asm/trace.h>
-#include <asm/pda.h>
-
-static atomic_t irq_err_count;
-void ack_bad_irq(unsigned int irq)
-{
- atomic_inc(&irq_err_count);
- printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
-}
-
-static struct irq_desc bad_irq_desc = {
- .handle_irq = handle_bad_irq,
- .lock = __RAW_SPIN_LOCK_UNLOCKED(bad_irq_desc.lock),
-};
-
-#ifdef CONFIG_CPUMASK_OFFSTACK
-/* We are not allocating a variable-sized bad_irq_desc.affinity */
-#error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK."
-#endif
-
-#ifdef CONFIG_PROC_FS
-int arch_show_interrupts(struct seq_file *p, int prec)
-{
- int j;
-
- seq_printf(p, "%*s: ", prec, "NMI");
- for_each_online_cpu(j)
- seq_printf(p, "%10u ", cpu_pda[j].__nmi_count);
- seq_printf(p, " CORE Non Maskable Interrupt\n");
- seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
-static void check_stack_overflow(int irq)
-{
- /* Debugging check for stack overflow: is there less than STACK_WARN free? */
- long sp = __get_SP() & (THREAD_SIZE - 1);
-
- if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
- dump_stack();
- pr_emerg("irq%i: possible stack overflow only %ld bytes free\n",
- irq, sp - sizeof(struct thread_info));
- }
-}
-#else
-static inline void check_stack_overflow(int irq) { }
-#endif
-
-#ifndef CONFIG_IPIPE
-static void maybe_lower_to_irq14(void)
-{
- unsigned short pending, other_ints;
-
- /*
- * If we're the only interrupt running (ignoring IRQ15 which
- * is for syscalls), lower our priority to IRQ14 so that
- * softirqs run at that level. If there's another,
- * lower-level interrupt, irq_exit will defer softirqs to
- * that. If the interrupt pipeline is enabled, we are already
- * running@IRQ14 priority, so we don't need this code.
- */
- CSYNC();
- pending = bfin_read_IPEND() & ~0x8000;
- other_ints = pending & (pending - 1);
- if (other_ints == 0)
- lower_to_irq14();
-}
-#else
-static inline void maybe_lower_to_irq14(void) { }
-#endif
-
-/*
- * do_IRQ handles all hardware IRQs. Decoded IRQs should not
- * come via this function. Instead, they should provide their
- * own 'handler'
- */
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
-{
- struct pt_regs *old_regs = set_irq_regs(regs);
-
- irq_enter();
-
- check_stack_overflow(irq);
-
- /*
- * Some hardware gives randomly wrong interrupts. Rather
- * than crashing, do something sensible.
- */
- if (irq >= NR_IRQS)
- handle_bad_irq(&bad_irq_desc);
- else
- generic_handle_irq(irq);
-
- maybe_lower_to_irq14();
-
- irq_exit();
-
- set_irq_regs(old_regs);
-}
-
-void __init init_IRQ(void)
-{
- init_arch_irq();
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- /* Now that evt_ivhw is set up, turn this on */
- trace_buff_offset = 0;
- bfin_write_TBUFCTL(BFIN_TRACE_ON);
- printk(KERN_INFO "Hardware Trace expanded to %ik\n",
- 1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN);
-#endif
-}
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
deleted file mode 100644
index cf773f0..0000000
--- a/arch/blackfin/kernel/kgdb.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/*
- * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ptrace.h> /* for linux pt_regs struct */
-#include <linux/kgdb.h>
-#include <linux/uaccess.h>
-#include <asm/irq_regs.h>
-
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- gdb_regs[BFIN_R0] = regs->r0;
- gdb_regs[BFIN_R1] = regs->r1;
- gdb_regs[BFIN_R2] = regs->r2;
- gdb_regs[BFIN_R3] = regs->r3;
- gdb_regs[BFIN_R4] = regs->r4;
- gdb_regs[BFIN_R5] = regs->r5;
- gdb_regs[BFIN_R6] = regs->r6;
- gdb_regs[BFIN_R7] = regs->r7;
- gdb_regs[BFIN_P0] = regs->p0;
- gdb_regs[BFIN_P1] = regs->p1;
- gdb_regs[BFIN_P2] = regs->p2;
- gdb_regs[BFIN_P3] = regs->p3;
- gdb_regs[BFIN_P4] = regs->p4;
- gdb_regs[BFIN_P5] = regs->p5;
- gdb_regs[BFIN_SP] = regs->reserved;
- gdb_regs[BFIN_FP] = regs->fp;
- gdb_regs[BFIN_I0] = regs->i0;
- gdb_regs[BFIN_I1] = regs->i1;
- gdb_regs[BFIN_I2] = regs->i2;
- gdb_regs[BFIN_I3] = regs->i3;
- gdb_regs[BFIN_M0] = regs->m0;
- gdb_regs[BFIN_M1] = regs->m1;
- gdb_regs[BFIN_M2] = regs->m2;
- gdb_regs[BFIN_M3] = regs->m3;
- gdb_regs[BFIN_B0] = regs->b0;
- gdb_regs[BFIN_B1] = regs->b1;
- gdb_regs[BFIN_B2] = regs->b2;
- gdb_regs[BFIN_B3] = regs->b3;
- gdb_regs[BFIN_L0] = regs->l0;
- gdb_regs[BFIN_L1] = regs->l1;
- gdb_regs[BFIN_L2] = regs->l2;
- gdb_regs[BFIN_L3] = regs->l3;
- gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
- gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
- gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
- gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
- gdb_regs[BFIN_ASTAT] = regs->astat;
- gdb_regs[BFIN_RETS] = regs->rets;
- gdb_regs[BFIN_LC0] = regs->lc0;
- gdb_regs[BFIN_LT0] = regs->lt0;
- gdb_regs[BFIN_LB0] = regs->lb0;
- gdb_regs[BFIN_LC1] = regs->lc1;
- gdb_regs[BFIN_LT1] = regs->lt1;
- gdb_regs[BFIN_LB1] = regs->lb1;
- gdb_regs[BFIN_CYCLES] = 0;
- gdb_regs[BFIN_CYCLES2] = 0;
- gdb_regs[BFIN_USP] = regs->usp;
- gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
- gdb_regs[BFIN_SYSCFG] = regs->syscfg;
- gdb_regs[BFIN_RETI] = regs->pc;
- gdb_regs[BFIN_RETX] = regs->retx;
- gdb_regs[BFIN_RETN] = regs->retn;
- gdb_regs[BFIN_RETE] = regs->rete;
- gdb_regs[BFIN_PC] = regs->pc;
- gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1;
- gdb_regs[BFIN_EXTRA1] = 0;
- gdb_regs[BFIN_EXTRA2] = 0;
- gdb_regs[BFIN_EXTRA3] = 0;
- gdb_regs[BFIN_IPEND] = regs->ipend;
-}
-
-/*
- * Extracts ebp, esp and eip values understandable by gdb from the values
- * saved by switch_to.
- * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
- * prior to entering switch_to is 8 greater than the value that is saved.
- * If switch_to changes, change following code appropriately.
- */
-void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
-{
- gdb_regs[BFIN_SP] = p->thread.ksp;
- gdb_regs[BFIN_PC] = p->thread.pc;
- gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
-}
-
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- regs->r0 = gdb_regs[BFIN_R0];
- regs->r1 = gdb_regs[BFIN_R1];
- regs->r2 = gdb_regs[BFIN_R2];
- regs->r3 = gdb_regs[BFIN_R3];
- regs->r4 = gdb_regs[BFIN_R4];
- regs->r5 = gdb_regs[BFIN_R5];
- regs->r6 = gdb_regs[BFIN_R6];
- regs->r7 = gdb_regs[BFIN_R7];
- regs->p0 = gdb_regs[BFIN_P0];
- regs->p1 = gdb_regs[BFIN_P1];
- regs->p2 = gdb_regs[BFIN_P2];
- regs->p3 = gdb_regs[BFIN_P3];
- regs->p4 = gdb_regs[BFIN_P4];
- regs->p5 = gdb_regs[BFIN_P5];
- regs->fp = gdb_regs[BFIN_FP];
- regs->i0 = gdb_regs[BFIN_I0];
- regs->i1 = gdb_regs[BFIN_I1];
- regs->i2 = gdb_regs[BFIN_I2];
- regs->i3 = gdb_regs[BFIN_I3];
- regs->m0 = gdb_regs[BFIN_M0];
- regs->m1 = gdb_regs[BFIN_M1];
- regs->m2 = gdb_regs[BFIN_M2];
- regs->m3 = gdb_regs[BFIN_M3];
- regs->b0 = gdb_regs[BFIN_B0];
- regs->b1 = gdb_regs[BFIN_B1];
- regs->b2 = gdb_regs[BFIN_B2];
- regs->b3 = gdb_regs[BFIN_B3];
- regs->l0 = gdb_regs[BFIN_L0];
- regs->l1 = gdb_regs[BFIN_L1];
- regs->l2 = gdb_regs[BFIN_L2];
- regs->l3 = gdb_regs[BFIN_L3];
- regs->a0x = gdb_regs[BFIN_A0_DOT_X];
- regs->a0w = gdb_regs[BFIN_A0_DOT_W];
- regs->a1x = gdb_regs[BFIN_A1_DOT_X];
- regs->a1w = gdb_regs[BFIN_A1_DOT_W];
- regs->rets = gdb_regs[BFIN_RETS];
- regs->lc0 = gdb_regs[BFIN_LC0];
- regs->lt0 = gdb_regs[BFIN_LT0];
- regs->lb0 = gdb_regs[BFIN_LB0];
- regs->lc1 = gdb_regs[BFIN_LC1];
- regs->lt1 = gdb_regs[BFIN_LT1];
- regs->lb1 = gdb_regs[BFIN_LB1];
- regs->usp = gdb_regs[BFIN_USP];
- regs->syscfg = gdb_regs[BFIN_SYSCFG];
- regs->retx = gdb_regs[BFIN_RETX];
- regs->retn = gdb_regs[BFIN_RETN];
- regs->rete = gdb_regs[BFIN_RETE];
- regs->pc = gdb_regs[BFIN_PC];
-
-#if 0 /* can't change these */
- regs->astat = gdb_regs[BFIN_ASTAT];
- regs->seqstat = gdb_regs[BFIN_SEQSTAT];
- regs->ipend = gdb_regs[BFIN_IPEND];
-#endif
-}
-
-static struct hw_breakpoint {
- unsigned int occupied:1;
- unsigned int skip:1;
- unsigned int enabled:1;
- unsigned int type:1;
- unsigned int dataacc:2;
- unsigned short count;
- unsigned int addr;
-} breakinfo[HW_WATCHPOINT_NUM];
-
-static int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
-{
- int breakno;
- int bfin_type;
- int dataacc = 0;
-
- switch (type) {
- case BP_HARDWARE_BREAKPOINT:
- bfin_type = TYPE_INST_WATCHPOINT;
- break;
- case BP_WRITE_WATCHPOINT:
- dataacc = 1;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- case BP_READ_WATCHPOINT:
- dataacc = 2;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- case BP_ACCESS_WATCHPOINT:
- dataacc = 3;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- default:
- return -ENOSPC;
- }
-
- /* Because hardware data watchpoint impelemented in current
- * Blackfin can not trigger an exception event as the hardware
- * instrction watchpoint does, we ignaore all data watch point here.
- * They can be turned on easily after future blackfin design
- * supports this feature.
- */
- for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
- if (bfin_type == breakinfo[breakno].type
- && !breakinfo[breakno].occupied) {
- breakinfo[breakno].occupied = 1;
- breakinfo[breakno].skip = 0;
- breakinfo[breakno].enabled = 1;
- breakinfo[breakno].addr = addr;
- breakinfo[breakno].dataacc = dataacc;
- breakinfo[breakno].count = 0;
- return 0;
- }
-
- return -ENOSPC;
-}
-
-static int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
-{
- int breakno;
- int bfin_type;
-
- switch (type) {
- case BP_HARDWARE_BREAKPOINT:
- bfin_type = TYPE_INST_WATCHPOINT;
- break;
- case BP_WRITE_WATCHPOINT:
- case BP_READ_WATCHPOINT:
- case BP_ACCESS_WATCHPOINT:
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- default:
- return 0;
- }
- for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
- if (bfin_type == breakinfo[breakno].type
- && breakinfo[breakno].occupied
- && breakinfo[breakno].addr == addr) {
- breakinfo[breakno].occupied = 0;
- breakinfo[breakno].enabled = 0;
- }
-
- return 0;
-}
-
-static void bfin_remove_all_hw_break(void)
-{
- int breakno;
-
- memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
-
- for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
- breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
- for (; breakno < HW_WATCHPOINT_NUM; breakno++)
- breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
-}
-
-static void bfin_correct_hw_break(void)
-{
- int breakno;
- unsigned int wpiactl = 0;
- unsigned int wpdactl = 0;
- int enable_wp = 0;
-
- for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
- if (breakinfo[breakno].enabled) {
- enable_wp = 1;
-
- switch (breakno) {
- case 0:
- wpiactl |= WPIAEN0|WPICNTEN0;
- bfin_write_WPIA0(breakinfo[breakno].addr);
- bfin_write_WPIACNT0(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 1:
- wpiactl |= WPIAEN1|WPICNTEN1;
- bfin_write_WPIA1(breakinfo[breakno].addr);
- bfin_write_WPIACNT1(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 2:
- wpiactl |= WPIAEN2|WPICNTEN2;
- bfin_write_WPIA2(breakinfo[breakno].addr);
- bfin_write_WPIACNT2(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 3:
- wpiactl |= WPIAEN3|WPICNTEN3;
- bfin_write_WPIA3(breakinfo[breakno].addr);
- bfin_write_WPIACNT3(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 4:
- wpiactl |= WPIAEN4|WPICNTEN4;
- bfin_write_WPIA4(breakinfo[breakno].addr);
- bfin_write_WPIACNT4(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 5:
- wpiactl |= WPIAEN5|WPICNTEN5;
- bfin_write_WPIA5(breakinfo[breakno].addr);
- bfin_write_WPIACNT5(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 6:
- wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
- wpdactl |= breakinfo[breakno].dataacc
- << WPDACC0_OFFSET;
- bfin_write_WPDA0(breakinfo[breakno].addr);
- bfin_write_WPDACNT0(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 7:
- wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
- wpdactl |= breakinfo[breakno].dataacc
- << WPDACC1_OFFSET;
- bfin_write_WPDA1(breakinfo[breakno].addr);
- bfin_write_WPDACNT1(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- }
- }
-
- /* Should enable WPPWR bit first before set any other
- * WPIACTL and WPDACTL bits */
- if (enable_wp) {
- bfin_write_WPIACTL(WPPWR);
- CSYNC();
- bfin_write_WPIACTL(wpiactl|WPPWR);
- bfin_write_WPDACTL(wpdactl);
- CSYNC();
- }
-}
-
-static void bfin_disable_hw_debug(struct pt_regs *regs)
-{
- /* Disable hardware debugging while we are in kgdb */
- bfin_write_WPIACTL(0);
- bfin_write_WPDACTL(0);
- CSYNC();
-}
-
-#ifdef CONFIG_SMP
-void kgdb_passive_cpu_callback(void *info)
-{
- kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
-}
-
-void kgdb_roundup_cpus(unsigned long flags)
-{
- unsigned int cpu;
-
- for (cpu = cpumask_first(cpu_online_mask); cpu < nr_cpu_ids;
- cpu = cpumask_next(cpu, cpu_online_mask))
- smp_call_function_single(cpu, kgdb_passive_cpu_callback,
- NULL, 0);
-}
-
-void kgdb_roundup_cpu(int cpu, unsigned long flags)
-{
- smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
-}
-#endif
-
-#ifdef CONFIG_IPIPE
-static unsigned long kgdb_arch_imask;
-#endif
-
-int kgdb_arch_handle_exception(int vector, int signo,
- int err_code, char *remcom_in_buffer,
- char *remcom_out_buffer,
- struct pt_regs *regs)
-{
- long addr;
- char *ptr;
- int newPC;
- int i;
-
- switch (remcom_in_buffer[0]) {
- case 'c':
- case 's':
- if (kgdb_contthread && kgdb_contthread != current) {
- strcpy(remcom_out_buffer, "E00");
- break;
- }
-
- kgdb_contthread = NULL;
-
- /* try to read optional parameter, pc unchanged if no parm */
- ptr = &remcom_in_buffer[1];
- if (kgdb_hex2long(&ptr, &addr)) {
- regs->retx = addr;
- }
- newPC = regs->retx;
-
- /* clear the trace bit */
- regs->syscfg &= 0xfffffffe;
-
- /* set the trace bit if we're stepping */
- if (remcom_in_buffer[0] == 's') {
- regs->syscfg |= 0x1;
- kgdb_single_step = regs->ipend;
- kgdb_single_step >>= 6;
- for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
- if (kgdb_single_step & 1)
- break;
- /* i indicate event priority of current stopped instruction
- * user space instruction is 0, IVG15 is 1, IVTMR is 10.
- * kgdb_single_step > 0 means in single step mode
- */
- kgdb_single_step = i + 1;
-
- preempt_disable();
-#ifdef CONFIG_IPIPE
- kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
- cpu_pda[raw_smp_processor_id()].ex_imask = 0;
-#endif
- }
-
- bfin_correct_hw_break();
-
- return 0;
- } /* switch */
- return -1; /* this means that we do not want to exit from the handler */
-}
-
-struct kgdb_arch arch_kgdb_ops = {
- .gdb_bpt_instr = {0xa1},
- .flags = KGDB_HW_BREAKPOINT,
- .set_hw_breakpoint = bfin_set_hw_break,
- .remove_hw_breakpoint = bfin_remove_hw_break,
- .disable_hw_break = bfin_disable_hw_debug,
- .remove_all_hw_break = bfin_remove_all_hw_break,
- .correct_hw_break = bfin_correct_hw_break,
-};
-
-#define IN_MEM(addr, size, l1_addr, l1_size) \
-({ \
- unsigned long __addr = (unsigned long)(addr); \
- (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
-})
-#define ASYNC_BANK_SIZE \
- (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
- ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
-
-int kgdb_validate_break_address(unsigned long addr)
-{
- int cpu = raw_smp_processor_id();
-
- if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
- return 0;
- if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
- return 0;
- if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
- return 0;
-#ifdef CONFIG_SMP
- else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
- return 0;
-#endif
- if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
- return 0;
-
- return -EFAULT;
-}
-
-void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
-{
- regs->retx = ip;
-}
-
-int kgdb_arch_init(void)
-{
- kgdb_single_step = 0;
-#ifdef CONFIG_IPIPE
- kgdb_arch_imask = 0;
-#endif
-
- bfin_remove_all_hw_break();
- return 0;
-}
-
-void kgdb_arch_exit(void)
-{
-}
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
deleted file mode 100644
index b8b785d..0000000
--- a/arch/blackfin/kernel/kgdb_test.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * arch/blackfin/kernel/kgdb_test.c - Blackfin kgdb tests
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-
-#include <asm/current.h>
-#include <linux/uaccess.h>
-
-#include <asm/blackfin.h>
-
-/* Symbols are here for kgdb test to poke directly */
-static char cmdline[256];
-static size_t len;
-
-#ifndef CONFIG_SMP
-static int num1 __attribute__((l1_data));
-
-void kgdb_l1_test(void) __attribute__((l1_text));
-
-void kgdb_l1_test(void)
-{
- pr_alert("L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
- pr_alert("L1 : code function addr = 0x%p\n", kgdb_l1_test);
- num1 = num1 + 10;
- pr_alert("L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
-}
-#endif
-
-#if L2_LENGTH
-
-static int num2 __attribute__((l2));
-void kgdb_l2_test(void) __attribute__((l2));
-
-void kgdb_l2_test(void)
-{
- pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
- pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test);
- num2 = num2 + 20;
- pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
-}
-
-#endif
-
-noinline int kgdb_test(char *name, int len, int count, int z)
-{
- pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z);
- count = z;
- return count;
-}
-
-static ssize_t
-kgdb_test_proc_read(struct file *file, char __user *buf,
- size_t count, loff_t *ppos)
-{
- kgdb_test("hello world!", 12, 0x55, 0x10);
-#ifndef CONFIG_SMP
- kgdb_l1_test();
-#endif
-#if L2_LENGTH
- kgdb_l2_test();
-#endif
-
- return 0;
-}
-
-static ssize_t
-kgdb_test_proc_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *pos)
-{
- len = min_t(size_t, 255, count);
- memcpy(cmdline, buffer, count);
- cmdline[len] = 0;
-
- return len;
-}
-
-static const struct file_operations kgdb_test_proc_fops = {
- .owner = THIS_MODULE,
- .read = kgdb_test_proc_read,
- .write = kgdb_test_proc_write,
- .llseek = noop_llseek,
-};
-
-static int __init kgdbtest_init(void)
-{
- struct proc_dir_entry *entry;
-
-#if L2_LENGTH
- num2 = 0;
-#endif
-
- entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
- if (entry == NULL)
- return -ENOMEM;
-
- return 0;
-}
-
-static void __exit kgdbtest_exit(void)
-{
- remove_proc_entry("kgdbtest", NULL);
-}
-
-module_init(kgdbtest_init);
-module_exit(kgdbtest_exit);
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c
deleted file mode 100644
index 15af576..0000000
--- a/arch/blackfin/kernel/module.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <asm/dma.h>
-#include <asm/cacheflush.h>
-#include <linux/uaccess.h>
-
-#define mod_err(mod, fmt, ...) \
- pr_err("module %s: " fmt, (mod)->name, ##__VA_ARGS__)
-#define mod_debug(mod, fmt, ...) \
- pr_debug("module %s: " fmt, (mod)->name, ##__VA_ARGS__)
-
-/* Transfer the section to the L1 memory */
-int
-module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
- char *secstrings, struct module *mod)
-{
- /*
- * XXX: sechdrs are vmalloced in kernel/module.c
- * and would be vfreed just after module is loaded,
- * so we hack to keep the only information we needed
- * in mod->arch to correctly free L1 I/D sram later.
- * NOTE: this breaks the semantic of mod->arch structure.
- */
- Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
- void *dest;
-
- for (s = sechdrs; s < sechdrs_end; ++s) {
- const char *shname = secstrings + s->sh_name;
-
- if (s->sh_size == 0)
- continue;
-
- if (!strcmp(".l1.text", shname) ||
- (!strcmp(".text", shname) &&
- (hdr->e_flags & EF_BFIN_CODE_IN_L1))) {
-
- dest = l1_inst_sram_alloc(s->sh_size);
- mod->arch.text_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 inst memory allocation failed\n");
- return -1;
- }
- dma_memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.data", shname) ||
- (!strcmp(".data", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {
-
- dest = l1_data_sram_alloc(s->sh_size);
- mod->arch.data_a_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.bss", shname) ||
- (!strcmp(".bss", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {
-
- dest = l1_data_sram_zalloc(s->sh_size);
- mod->arch.bss_a_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
-
- } else if (!strcmp(".l1.data.B", shname)) {
-
- dest = l1_data_B_sram_alloc(s->sh_size);
- mod->arch.data_b_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.bss.B", shname)) {
-
- dest = l1_data_B_sram_alloc(s->sh_size);
- mod->arch.bss_b_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memset(dest, 0, s->sh_size);
-
- } else if (!strcmp(".l2.text", shname) ||
- (!strcmp(".text", shname) &&
- (hdr->e_flags & EF_BFIN_CODE_IN_L2))) {
-
- dest = l2_sram_alloc(s->sh_size);
- mod->arch.text_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l2.data", shname) ||
- (!strcmp(".data", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {
-
- dest = l2_sram_alloc(s->sh_size);
- mod->arch.data_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l2.bss", shname) ||
- (!strcmp(".bss", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {
-
- dest = l2_sram_zalloc(s->sh_size);
- mod->arch.bss_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
-
- } else
- continue;
-
- s->sh_flags &= ~SHF_ALLOC;
- s->sh_addr = (unsigned long)dest;
- }
-
- return 0;
-}
-
-/*************************************************************************/
-/* FUNCTION : apply_relocate_add */
-/* ABSTRACT : Blackfin specific relocation handling for the loadable */
-/* modules. Modules are expected to be .o files. */
-/* Arithmetic relocations are handled. */
-/* We do not expect LSETUP to be split and hence is not */
-/* handled. */
-/* R_BFIN_BYTE and R_BFIN_BYTE2 are also not handled as the */
-/* gas does not generate it. */
-/*************************************************************************/
-int
-apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
- unsigned int symindex, unsigned int relsec,
- struct module *mod)
-{
- unsigned int i;
- Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
- Elf32_Sym *sym;
- unsigned long location, value, size;
-
- mod_debug(mod, "applying relocate section %u to %u\n",
- relsec, sechdrs[relsec].sh_info);
-
- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
- /* This is where to make the change */
- location = sechdrs[sechdrs[relsec].sh_info].sh_addr +
- rel[i].r_offset;
-
- /* This is the symbol it is referring to. Note that all
- undefined symbols have been resolved. */
- sym = (Elf32_Sym *) sechdrs[symindex].sh_addr
- + ELF32_R_SYM(rel[i].r_info);
- value = sym->st_value;
- value += rel[i].r_addend;
-
-#ifdef CONFIG_SMP
- if (location >= COREB_L1_DATA_A_START) {
- mod_err(mod, "cannot relocate in L1: %u (SMP kernel)\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
-#endif
-
- mod_debug(mod, "location is %lx, value is %lx type is %d\n",
- location, value, ELF32_R_TYPE(rel[i].r_info));
-
- switch (ELF32_R_TYPE(rel[i].r_info)) {
-
- case R_BFIN_HUIMM16:
- value >>= 16;
- case R_BFIN_LUIMM16:
- case R_BFIN_RIMM16:
- size = 2;
- break;
- case R_BFIN_BYTE4_DATA:
- size = 4;
- break;
-
- case R_BFIN_PCREL24:
- case R_BFIN_PCREL24_JUMP_L:
- case R_BFIN_PCREL12_JUMP:
- case R_BFIN_PCREL12_JUMP_S:
- case R_BFIN_PCREL10:
- mod_err(mod, "unsupported relocation: %u (no -mlong-calls?)\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
-
- default:
- mod_err(mod, "unknown relocation: %u\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
-
- switch (bfin_mem_access_type(location, size)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- memcpy((void *)location, &value, size);
- break;
- case BFIN_MEM_ACCESS_DMA:
- dma_memcpy((void *)location, &value, size);
- break;
- case BFIN_MEM_ACCESS_ITEST:
- isram_memcpy((void *)location, &value, size);
- break;
- default:
- mod_err(mod, "invalid relocation for %#lx\n", location);
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
-
-int
-module_finalize(const Elf_Ehdr * hdr,
- const Elf_Shdr * sechdrs, struct module *mod)
-{
- unsigned int i, strindex = 0, symindex = 0;
- char *secstrings;
- long err = 0;
-
- secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
-
- for (i = 1; i < hdr->e_shnum; i++) {
- /* Internal symbols and strings. */
- if (sechdrs[i].sh_type == SHT_SYMTAB) {
- symindex = i;
- strindex = sechdrs[i].sh_link;
- }
- }
-
- for (i = 1; i < hdr->e_shnum; i++) {
- const char *strtab = (char *)sechdrs[strindex].sh_addr;
- unsigned int info = sechdrs[i].sh_info;
- const char *shname = secstrings + sechdrs[i].sh_name;
-
- /* Not a valid relocation section? */
- if (info >= hdr->e_shnum)
- continue;
-
- /* Only support RELA relocation types */
- if (sechdrs[i].sh_type != SHT_RELA)
- continue;
-
- if (!strcmp(".rela.l2.text", shname) ||
- !strcmp(".rela.l1.text", shname) ||
- (!strcmp(".rela.text", shname) &&
- (hdr->e_flags & (EF_BFIN_CODE_IN_L1 | EF_BFIN_CODE_IN_L2)))) {
-
- err = apply_relocate_add((Elf_Shdr *) sechdrs, strtab,
- symindex, i, mod);
- if (err < 0)
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
-
-void module_arch_cleanup(struct module *mod)
-{
- l1_inst_sram_free(mod->arch.text_l1);
- l1_data_A_sram_free(mod->arch.data_a_l1);
- l1_data_A_sram_free(mod->arch.bss_a_l1);
- l1_data_B_sram_free(mod->arch.data_b_l1);
- l1_data_B_sram_free(mod->arch.bss_b_l1);
- l2_sram_free(mod->arch.text_l2);
- l2_sram_free(mod->arch.data_l2);
- l2_sram_free(mod->arch.bss_l2);
-}
diff --git a/arch/blackfin/kernel/nmi.c b/arch/blackfin/kernel/nmi.c
deleted file mode 100644
index 8a211d9..0000000
--- a/arch/blackfin/kernel/nmi.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Blackfin nmi_watchdog Driver
- *
- * Originally based on bfin_wdt.c
- * Copyright 2010-2010 Analog Devices Inc.
- * Graff Yang <graf.yang@analog.com>
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/bitops.h>
-#include <linux/hardirq.h>
-#include <linux/syscore_ops.h>
-#include <linux/pm.h>
-#include <linux/nmi.h>
-#include <linux/smp.h>
-#include <linux/timer.h>
-#include <linux/sched/debug.h>
-#include <asm/blackfin.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-#include <asm/bfin_watchdog.h>
-
-#define DRV_NAME "nmi-wdt"
-
-#define NMI_WDT_TIMEOUT 5 /* 5 seconds */
-#define NMI_CHECK_TIMEOUT (4 * HZ) /* 4 seconds in jiffies */
-static int nmi_wdt_cpu = 1;
-
-static unsigned int timeout = NMI_WDT_TIMEOUT;
-static int nmi_active;
-
-static unsigned short wdoga_ctl;
-static unsigned int wdoga_cnt;
-static struct corelock_slot saved_corelock;
-static atomic_t nmi_touched[NR_CPUS];
-static struct timer_list ntimer;
-
-enum {
- COREA_ENTER_NMI = 0,
- COREA_EXIT_NMI,
- COREB_EXIT_NMI,
-
- NMI_EVENT_NR,
-};
-static unsigned long nmi_event __attribute__ ((__section__(".l2.bss")));
-
-/* we are in nmi, non-atomic bit ops is safe */
-static inline void set_nmi_event(int event)
-{
- __set_bit(event, &nmi_event);
-}
-
-static inline void wait_nmi_event(int event)
-{
- while (!test_bit(event, &nmi_event))
- barrier();
- __clear_bit(event, &nmi_event);
-}
-
-static inline void send_corea_nmi(void)
-{
- wdoga_ctl = bfin_read_WDOGA_CTL();
- wdoga_cnt = bfin_read_WDOGA_CNT();
-
- bfin_write_WDOGA_CTL(WDEN_DISABLE);
- bfin_write_WDOGA_CNT(0);
- bfin_write_WDOGA_CTL(WDEN_ENABLE | ICTL_NMI);
-}
-
-static inline void restore_corea_nmi(void)
-{
- bfin_write_WDOGA_CTL(WDEN_DISABLE);
- bfin_write_WDOGA_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE);
-
- bfin_write_WDOGA_CNT(wdoga_cnt);
- bfin_write_WDOGA_CTL(wdoga_ctl);
-}
-
-static inline void save_corelock(void)
-{
- saved_corelock = corelock;
- corelock.lock = 0;
-}
-
-static inline void restore_corelock(void)
-{
- corelock = saved_corelock;
-}
-
-
-static inline void nmi_wdt_keepalive(void)
-{
- bfin_write_WDOGB_STAT(0);
-}
-
-static inline void nmi_wdt_stop(void)
-{
- bfin_write_WDOGB_CTL(WDEN_DISABLE);
-}
-
-/* before calling this function, you must stop the WDT */
-static inline void nmi_wdt_clear(void)
-{
- /* clear TRO bit, disable event generation */
- bfin_write_WDOGB_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE);
-}
-
-static inline void nmi_wdt_start(void)
-{
- bfin_write_WDOGB_CTL(WDEN_ENABLE | ICTL_NMI);
-}
-
-static inline int nmi_wdt_running(void)
-{
- return ((bfin_read_WDOGB_CTL() & WDEN_MASK) != WDEN_DISABLE);
-}
-
-static inline int nmi_wdt_set_timeout(unsigned long t)
-{
- u32 cnt, max_t, sclk;
- int run;
-
- sclk = get_sclk();
- max_t = -1 / sclk;
- cnt = t * sclk;
- if (t > max_t) {
- pr_warning("NMI: timeout value is too large\n");
- return -EINVAL;
- }
-
- run = nmi_wdt_running();
- nmi_wdt_stop();
- bfin_write_WDOGB_CNT(cnt);
- if (run)
- nmi_wdt_start();
-
- timeout = t;
-
- return 0;
-}
-
-int check_nmi_wdt_touched(void)
-{
- unsigned int this_cpu = smp_processor_id();
- unsigned int cpu;
- cpumask_t mask;
-
- cpumask_copy(&mask, cpu_online_mask);
- if (!atomic_read(&nmi_touched[this_cpu]))
- return 0;
-
- atomic_set(&nmi_touched[this_cpu], 0);
-
- cpumask_clear_cpu(this_cpu, &mask);
- for_each_cpu(cpu, &mask) {
- invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]),
- (unsigned long)(&nmi_touched[cpu]));
- if (!atomic_read(&nmi_touched[cpu]))
- return 0;
- atomic_set(&nmi_touched[cpu], 0);
- }
-
- return 1;
-}
-
-static void nmi_wdt_timer(struct timer_list *unused)
-{
- if (check_nmi_wdt_touched())
- nmi_wdt_keepalive();
-
- mod_timer(&ntimer, jiffies + NMI_CHECK_TIMEOUT);
-}
-
-static int __init init_nmi_wdt(void)
-{
- nmi_wdt_set_timeout(timeout);
- nmi_wdt_start();
- nmi_active = true;
-
- timer_setup(&ntimer, nmi_wdt_timer, 0);
- ntimer.expires = jiffies + NMI_CHECK_TIMEOUT;
- add_timer(&ntimer);
-
- pr_info("nmi_wdt: initialized: timeout=%d sec\n", timeout);
- return 0;
-}
-device_initcall(init_nmi_wdt);
-
-void arch_touch_nmi_watchdog(void)
-{
- atomic_set(&nmi_touched[smp_processor_id()], 1);
-}
-
-/* Suspend/resume support */
-#ifdef CONFIG_PM
-static int nmi_wdt_suspend(void)
-{
- nmi_wdt_stop();
- return 0;
-}
-
-static void nmi_wdt_resume(void)
-{
- if (nmi_active)
- nmi_wdt_start();
-}
-
-static struct syscore_ops nmi_syscore_ops = {
- .resume = nmi_wdt_resume,
- .suspend = nmi_wdt_suspend,
-};
-
-static int __init init_nmi_wdt_syscore(void)
-{
- if (nmi_active)
- register_syscore_ops(&nmi_syscore_ops);
-
- return 0;
-}
-late_initcall(init_nmi_wdt_syscore);
-
-#endif /* CONFIG_PM */
-
-
-asmlinkage notrace void do_nmi(struct pt_regs *fp)
-{
- unsigned int cpu = smp_processor_id();
- nmi_enter();
-
- cpu_pda[cpu].__nmi_count += 1;
-
- if (cpu == nmi_wdt_cpu) {
- /* CoreB goes here first */
-
- /* reload the WDOG_STAT */
- nmi_wdt_keepalive();
-
- /* clear nmi interrupt for CoreB */
- nmi_wdt_stop();
- nmi_wdt_clear();
-
- /* trigger NMI interrupt of CoreA */
- send_corea_nmi();
-
- /* waiting CoreB to enter NMI */
- wait_nmi_event(COREA_ENTER_NMI);
-
- /* recover WDOGA's settings */
- restore_corea_nmi();
-
- save_corelock();
-
- /* corelock is save/cleared, CoreA is dummping messages */
-
- wait_nmi_event(COREA_EXIT_NMI);
- } else {
- /* OK, CoreA entered NMI */
- set_nmi_event(COREA_ENTER_NMI);
- }
-
- pr_emerg("\nNMI Watchdog detected LOCKUP, dump for CPU %d\n", cpu);
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_bfin_trace_buffer();
- show_stack(current, (unsigned long *)fp);
-
- if (cpu == nmi_wdt_cpu) {
- pr_emerg("This fault is not recoverable, sorry!\n");
-
- /* CoreA dump finished, restore the corelock */
- restore_corelock();
-
- set_nmi_event(COREB_EXIT_NMI);
- } else {
- /* CoreB dump finished, notice the CoreA we are done */
- set_nmi_event(COREA_EXIT_NMI);
-
- /* synchronize with CoreA */
- wait_nmi_event(COREB_EXIT_NMI);
- }
-
- nmi_exit();
-}
diff --git a/arch/blackfin/kernel/perf_event.c b/arch/blackfin/kernel/perf_event.c
deleted file mode 100644
index 6a9524a..0000000
--- a/arch/blackfin/kernel/perf_event.c
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- * Blackfin performance counters
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Ripped from SuperH version:
- *
- * Copyright (C) 2009 Paul Mundt
- *
- * Heavily based on the x86 and PowerPC implementations.
- *
- * x86:
- * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
- * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
- * Copyright (C) 2009 Jaswinder Singh Rajput
- * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
- * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
- * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
- *
- * ppc:
- * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/perf_event.h>
-#include <asm/bfin_pfmon.h>
-
-/*
- * We have two counters, and each counter can support an event type.
- * The 'o' is PFCNTx=1 and 's' is PFCNTx=0
- *
- * 0x04 o pc invariant branches
- * 0x06 o mispredicted branches
- * 0x09 o predicted branches taken
- * 0x0B o EXCPT insn
- * 0x0C o CSYNC/SSYNC insn
- * 0x0D o Insns committed
- * 0x0E o Interrupts taken
- * 0x0F o Misaligned address exceptions
- * 0x80 o Code memory fetches stalled due to DMA
- * 0x83 o 64bit insn fetches delivered
- * 0x9A o data cache fills (bank a)
- * 0x9B o data cache fills (bank b)
- * 0x9C o data cache lines evicted (bank a)
- * 0x9D o data cache lines evicted (bank b)
- * 0x9E o data cache high priority fills
- * 0x9F o data cache low priority fills
- * 0x00 s loop 0 iterations
- * 0x01 s loop 1 iterations
- * 0x0A s CSYNC/SSYNC stalls
- * 0x10 s DAG read/after write hazards
- * 0x13 s RAW data hazards
- * 0x81 s code TAG stalls
- * 0x82 s code fill stalls
- * 0x90 s processor to memory stalls
- * 0x91 s data memory stalls not hidden by 0x90
- * 0x92 s data store buffer full stalls
- * 0x93 s data memory write buffer full stalls due to high->low priority
- * 0x95 s data memory fill buffer stalls
- * 0x96 s data TAG collision stalls
- * 0x97 s data collision stalls
- * 0x98 s data stalls
- * 0x99 s data stalls sent to processor
- */
-
-static const int event_map[] = {
- /* use CYCLES cpu register */
- [PERF_COUNT_HW_CPU_CYCLES] = -1,
- [PERF_COUNT_HW_INSTRUCTIONS] = 0x0D,
- [PERF_COUNT_HW_CACHE_REFERENCES] = -1,
- [PERF_COUNT_HW_CACHE_MISSES] = 0x83,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x09,
- [PERF_COUNT_HW_BRANCH_MISSES] = 0x06,
- [PERF_COUNT_HW_BUS_CYCLES] = -1,
-};
-
-#define C(x) PERF_COUNT_HW_CACHE_##x
-
-static const int cache_events[PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [C(L1D)] = { /* Data bank A */
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0x9A,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- },
-
- [C(L1I)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0x83,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- },
-
- [C(LL)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(DTLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(ITLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(BPU)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-};
-
-const char *perf_pmu_name(void)
-{
- return "bfin";
-}
-EXPORT_SYMBOL(perf_pmu_name);
-
-int perf_num_counters(void)
-{
- return ARRAY_SIZE(event_map);
-}
-EXPORT_SYMBOL(perf_num_counters);
-
-static u64 bfin_pfmon_read(int idx)
-{
- return bfin_read32(PFCNTR0 + (idx * 4));
-}
-
-static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() & ~PFCEN(idx, PFCEN_MASK));
-}
-
-static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx)
-{
- u32 val, mask;
-
- val = PFPWR;
- if (idx) {
- mask = ~(PFCNT1 | PFMON1 | PFCEN1 | PEMUSW1);
- /* The packed config is for event0, so shift it to event1 slots */
- val |= (hwc->config << (PFMON1_P - PFMON0_P));
- val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P);
- bfin_write_PFCNTR1(0);
- } else {
- mask = ~(PFCNT0 | PFMON0 | PFCEN0 | PEMUSW0);
- val |= hwc->config;
- bfin_write_PFCNTR0(0);
- }
-
- bfin_write_PFCTL((bfin_read_PFCTL() & mask) | val);
-}
-
-static void bfin_pfmon_disable_all(void)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() & ~PFPWR);
-}
-
-static void bfin_pfmon_enable_all(void)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() | PFPWR);
-}
-
-struct cpu_hw_events {
- struct perf_event *events[MAX_HWEVENTS];
- unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
-};
-DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
-
-static int hw_perf_cache_event(int config, int *evp)
-{
- unsigned long type, op, result;
- int ev;
-
- /* unpack config */
- type = config & 0xff;
- op = (config >> 8) & 0xff;
- result = (config >> 16) & 0xff;
-
- if (type >= PERF_COUNT_HW_CACHE_MAX ||
- op >= PERF_COUNT_HW_CACHE_OP_MAX ||
- result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
- return -EINVAL;
-
- ev = cache_events[type][op][result];
- if (ev == 0)
- return -EOPNOTSUPP;
- if (ev == -1)
- return -EINVAL;
- *evp = ev;
- return 0;
-}
-
-static void bfin_perf_event_update(struct perf_event *event,
- struct hw_perf_event *hwc, int idx)
-{
- u64 prev_raw_count, new_raw_count;
- s64 delta;
- int shift = 0;
-
- /*
- * Depending on the counter configuration, they may or may not
- * be chained, in which case the previous counter value can be
- * updated underneath us if the lower-half overflows.
- *
- * Our tactic to handle this is to first atomically read and
- * exchange a new raw count - then add that new-prev delta
- * count to the generic counter atomically.
- *
- * As there is no interrupt associated with the overflow events,
- * this is the simplest approach for maintaining consistency.
- */
-again:
- prev_raw_count = local64_read(&hwc->prev_count);
- new_raw_count = bfin_pfmon_read(idx);
-
- if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
- new_raw_count) != prev_raw_count)
- goto again;
-
- /*
- * Now we have the new raw value and have updated the prev
- * timestamp already. We can now calculate the elapsed delta
- * (counter-)time and add that to the generic counter.
- *
- * Careful, not all hw sign-extends above the physical width
- * of the count.
- */
- delta = (new_raw_count << shift) - (prev_raw_count << shift);
- delta >>= shift;
-
- local64_add(delta, &event->count);
-}
-
-static void bfin_pmu_stop(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (!(event->hw.state & PERF_HES_STOPPED)) {
- bfin_pfmon_disable(hwc, idx);
- cpuc->events[idx] = NULL;
- event->hw.state |= PERF_HES_STOPPED;
- }
-
- if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
- bfin_perf_event_update(event, &event->hw, idx);
- event->hw.state |= PERF_HES_UPTODATE;
- }
-}
-
-static void bfin_pmu_start(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (WARN_ON_ONCE(idx == -1))
- return;
-
- if (flags & PERF_EF_RELOAD)
- WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
-
- cpuc->events[idx] = event;
- event->hw.state = 0;
- bfin_pfmon_enable(hwc, idx);
-}
-
-static void bfin_pmu_del(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
-
- bfin_pmu_stop(event, PERF_EF_UPDATE);
- __clear_bit(event->hw.idx, cpuc->used_mask);
-
- perf_event_update_userpage(event);
-}
-
-static int bfin_pmu_add(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
- int ret = -EAGAIN;
-
- perf_pmu_disable(event->pmu);
-
- if (__test_and_set_bit(idx, cpuc->used_mask)) {
- idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS);
- if (idx == MAX_HWEVENTS)
- goto out;
-
- __set_bit(idx, cpuc->used_mask);
- hwc->idx = idx;
- }
-
- bfin_pfmon_disable(hwc, idx);
-
- event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
- if (flags & PERF_EF_START)
- bfin_pmu_start(event, PERF_EF_RELOAD);
-
- perf_event_update_userpage(event);
- ret = 0;
-out:
- perf_pmu_enable(event->pmu);
- return ret;
-}
-
-static void bfin_pmu_read(struct perf_event *event)
-{
- bfin_perf_event_update(event, &event->hw, event->hw.idx);
-}
-
-static int bfin_pmu_event_init(struct perf_event *event)
-{
- struct perf_event_attr *attr = &event->attr;
- struct hw_perf_event *hwc = &event->hw;
- int config = -1;
- int ret;
-
- if (attr->exclude_hv || attr->exclude_idle)
- return -EPERM;
-
- ret = 0;
- switch (attr->type) {
- case PERF_TYPE_RAW:
- config = PFMON(0, attr->config & PFMON_MASK) |
- PFCNT(0, !(attr->config & 0x100));
- break;
- case PERF_TYPE_HW_CACHE:
- ret = hw_perf_cache_event(attr->config, &config);
- break;
- case PERF_TYPE_HARDWARE:
- if (attr->config >= ARRAY_SIZE(event_map))
- return -EINVAL;
-
- config = event_map[attr->config];
- break;
- }
-
- if (config == -1)
- return -EINVAL;
-
- if (!attr->exclude_kernel)
- config |= PFCEN(0, PFCEN_ENABLE_SUPV);
- if (!attr->exclude_user)
- config |= PFCEN(0, PFCEN_ENABLE_USER);
-
- hwc->config |= config;
-
- return ret;
-}
-
-static void bfin_pmu_enable(struct pmu *pmu)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct perf_event *event;
- struct hw_perf_event *hwc;
- int i;
-
- for (i = 0; i < MAX_HWEVENTS; ++i) {
- event = cpuc->events[i];
- if (!event)
- continue;
- hwc = &event->hw;
- bfin_pfmon_enable(hwc, hwc->idx);
- }
-
- bfin_pfmon_enable_all();
-}
-
-static void bfin_pmu_disable(struct pmu *pmu)
-{
- bfin_pfmon_disable_all();
-}
-
-static struct pmu pmu = {
- .pmu_enable = bfin_pmu_enable,
- .pmu_disable = bfin_pmu_disable,
- .event_init = bfin_pmu_event_init,
- .add = bfin_pmu_add,
- .del = bfin_pmu_del,
- .start = bfin_pmu_start,
- .stop = bfin_pmu_stop,
- .read = bfin_pmu_read,
-};
-
-static int bfin_pmu_prepare_cpu(unsigned int cpu)
-{
- struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
-
- bfin_write_PFCTL(0);
- memset(cpuhw, 0, sizeof(struct cpu_hw_events));
- return 0;
-}
-
-static int __init bfin_pmu_init(void)
-{
- int ret;
-
- /*
- * All of the on-chip counters are "limited", in that they have
- * no interrupts, and are therefore unable to do sampling without
- * further work and timer assistance.
- */
- pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
-
- ret = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
- if (!ret)
- cpuhp_setup_state(CPUHP_PERF_BFIN,"perf/bfin:starting",
- bfin_pmu_prepare_cpu, NULL);
- return ret;
-}
-early_initcall(bfin_pmu_init);
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
deleted file mode 100644
index 8981485..0000000
--- a/arch/blackfin/kernel/process.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- * Blackfin architecture-dependent process handling
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/module.h>
-#include <linux/unistd.h>
-#include <linux/user.h>
-#include <linux/uaccess.h>
-#include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm_types.h>
-#include <linux/tick.h>
-#include <linux/fs.h>
-#include <linux/err.h>
-
-#include <asm/blackfin.h>
-#include <asm/fixed_code.h>
-#include <asm/mem_map.h>
-#include <asm/irq.h>
-
-asmlinkage void ret_from_fork(void);
-
-/* Points to the SDRAM backup memory for the stack that is currently in
- * L1 scratchpad memory.
- */
-void *current_l1_stack_save;
-
-/* The number of tasks currently using a L1 stack area. The SRAM is
- * allocated/deallocated whenever this changes from/to zero.
- */
-int nr_l1stack_tasks;
-
-/* Start and length of the area in L1 scratchpad memory which we've allocated
- * for process stacks.
- */
-void *l1_stack_base;
-unsigned long l1_stack_len;
-
-void (*pm_power_off)(void) = NULL;
-EXPORT_SYMBOL(pm_power_off);
-
-/*
- * The idle loop on BFIN
- */
-#ifdef CONFIG_IDLE_L1
-void arch_cpu_idle(void)__attribute__((l1_text));
-#endif
-
-/*
- * This is our default idle handler. We need to disable
- * interrupts here to ensure we don't miss a wakeup call.
- */
-void arch_cpu_idle(void)
-{
-#ifdef CONFIG_IPIPE
- ipipe_suspend_domain();
-#endif
- hard_local_irq_disable();
- if (!need_resched())
- idle_with_irq_disabled();
-
- hard_local_irq_enable();
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-void arch_cpu_idle_dead(void)
-{
- cpu_die();
-}
-#endif
-
-/*
- * Do necessary setup to start up a newly executed thread.
- *
- * pass the data segment into user programs if it exists,
- * it can't hurt anything as far as I can tell
- */
-void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
-{
- regs->pc = new_ip;
- if (current->mm)
- regs->p5 = current->mm->start_data;
-#ifndef CONFIG_SMP
- task_thread_info(current)->l1_task_info.stack_start =
- (void *)current->mm->context.stack_start;
- task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
- memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
- sizeof(*L1_SCRATCH_TASK_INFO));
-#endif
- wrusp(new_sp);
-}
-EXPORT_SYMBOL_GPL(start_thread);
-
-void flush_thread(void)
-{
-}
-
-asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
-{
-#ifdef __ARCH_SYNC_CORE_DCACHE
- if (current->nr_cpus_allowed == num_possible_cpus())
- set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
-#endif
- if (newsp)
- newsp -= 12;
- return do_fork(clone_flags, newsp, 0, NULL, NULL);
-}
-
-int
-copy_thread(unsigned long clone_flags,
- unsigned long usp, unsigned long topstk,
- struct task_struct *p)
-{
- struct pt_regs *childregs;
- unsigned long *v;
-
- childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
- v = ((unsigned long *)childregs) - 2;
- if (unlikely(p->flags & PF_KTHREAD)) {
- memset(childregs, 0, sizeof(struct pt_regs));
- v[0] = usp;
- v[1] = topstk;
- childregs->orig_p0 = -1;
- childregs->ipend = 0x8000;
- __asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
- p->thread.usp = 0;
- } else {
- *childregs = *current_pt_regs();
- childregs->r0 = 0;
- p->thread.usp = usp ? : rdusp();
- v[0] = v[1] = 0;
- }
-
- p->thread.ksp = (unsigned long)v;
- p->thread.pc = (unsigned long)ret_from_fork;
-
- return 0;
-}
-
-unsigned long get_wchan(struct task_struct *p)
-{
- unsigned long fp, pc;
- unsigned long stack_page;
- int count = 0;
- if (!p || p == current || p->state == TASK_RUNNING)
- return 0;
-
- stack_page = (unsigned long)p;
- fp = p->thread.usp;
- do {
- if (fp < stack_page + sizeof(struct thread_info) ||
- fp >= 8184 + stack_page)
- return 0;
- pc = ((unsigned long *)fp)[1];
- if (!in_sched_functions(pc))
- return pc;
- fp = *(unsigned long *)fp;
- }
- while (count++ < 16);
- return 0;
-}
-
-void finish_atomic_sections (struct pt_regs *regs)
-{
- int __user *up0 = (int __user *)regs->p0;
-
- switch (regs->pc) {
- default:
- /* not in middle of an atomic step, so resume like normal */
- return;
-
- case ATOMIC_XCHG32 + 2:
- put_user(regs->r1, up0);
- break;
-
- case ATOMIC_CAS32 + 2:
- case ATOMIC_CAS32 + 4:
- if (regs->r0 == regs->r1)
- case ATOMIC_CAS32 + 6:
- put_user(regs->r2, up0);
- break;
-
- case ATOMIC_ADD32 + 2:
- regs->r0 = regs->r1 + regs->r0;
- /* fall through */
- case ATOMIC_ADD32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_SUB32 + 2:
- regs->r0 = regs->r1 - regs->r0;
- /* fall through */
- case ATOMIC_SUB32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_IOR32 + 2:
- regs->r0 = regs->r1 | regs->r0;
- /* fall through */
- case ATOMIC_IOR32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_AND32 + 2:
- regs->r0 = regs->r1 & regs->r0;
- /* fall through */
- case ATOMIC_AND32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_XOR32 + 2:
- regs->r0 = regs->r1 ^ regs->r0;
- /* fall through */
- case ATOMIC_XOR32 + 4:
- put_user(regs->r0, up0);
- break;
- }
-
- /*
- * We've finished the atomic section, and the only thing left for
- * userspace is to do a RTS, so we might as well handle that too
- * since we need to update the PC anyways.
- */
- regs->pc = regs->rets;
-}
-
-static inline
-int in_mem(unsigned long addr, unsigned long size,
- unsigned long start, unsigned long end)
-{
- return addr >= start && addr + size <= end;
-}
-static inline
-int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
- unsigned long const_addr, unsigned long const_size)
-{
- return const_size &&
- in_mem(addr, size, const_addr + off, const_addr + const_size);
-}
-static inline
-int in_mem_const(unsigned long addr, unsigned long size,
- unsigned long const_addr, unsigned long const_size)
-{
- return in_mem_const_off(addr, size, 0, const_addr, const_size);
-}
-#ifdef CONFIG_BF60x
-#define ASYNC_ENABLED(bnum, bctlnum) 1
-#else
-#define ASYNC_ENABLED(bnum, bctlnum) \
-({ \
- (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
- bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
- 1; \
-})
-#endif
-/*
- * We can't read EBIU banks that aren't enabled or we end up hanging
- * on the access to the async space. Make sure we validate accesses
- * that cross async banks too.
- * 0 - found, but unusable
- * 1 - found & usable
- * 2 - not found
- */
-static
-int in_async(unsigned long addr, unsigned long size)
-{
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
- if (!ASYNC_ENABLED(0, 0))
- return 0;
- if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
- return 1;
- size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
- addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
- }
- if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
- if (!ASYNC_ENABLED(1, 0))
- return 0;
- if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
- return 1;
- size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
- addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
- }
- if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
- if (!ASYNC_ENABLED(2, 1))
- return 0;
- if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
- return 1;
- size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
- addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
- }
- if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
- if (ASYNC_ENABLED(3, 1))
- return 0;
- if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
- return 1;
- return 0;
- }
-
- /* not within async bounds */
- return 2;
-}
-
-int bfin_mem_access_type(unsigned long addr, unsigned long size)
-{
- int cpu = raw_smp_processor_id();
-
- /* Check that things do not wrap around */
- if (addr > ULONG_MAX - size)
- return -EFAULT;
-
- if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
- return BFIN_MEM_ACCESS_CORE;
-
- if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
- if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
-#ifdef COREB_L1_CODE_START
- if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
- if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
-#endif
- if (in_mem_const(addr, size, L2_START, L2_LENGTH))
- return BFIN_MEM_ACCESS_CORE;
-
- if (addr >= SYSMMR_BASE)
- return BFIN_MEM_ACCESS_CORE_ONLY;
-
- switch (in_async(addr, size)) {
- case 0: return -EFAULT;
- case 1: return BFIN_MEM_ACCESS_CORE;
- case 2: /* fall through */;
- }
-
- if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
- return BFIN_MEM_ACCESS_CORE;
- if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
- return BFIN_MEM_ACCESS_DMA;
-
- return -EFAULT;
-}
-
-#if defined(CONFIG_ACCESS_CHECK)
-#ifdef CONFIG_ACCESS_OK_L1
-__attribute__((l1_text))
-#endif
-/* Return 1 if access to memory range is OK, 0 otherwise */
-int _access_ok(unsigned long addr, unsigned long size)
-{
- int aret;
-
- if (size == 0)
- return 1;
- /* Check that things do not wrap around */
- if (addr > ULONG_MAX - size)
- return 0;
- if (uaccess_kernel())
- return 1;
-#ifdef CONFIG_MTD_UCLINUX
- if (1)
-#else
- if (0)
-#endif
- {
- if (in_mem(addr, size, memory_start, memory_end))
- return 1;
- if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
- return 1;
-# ifndef CONFIG_ROMFS_ON_MTD
- if (0)
-# endif
- /* For XIP, allow user space to use pointers within the ROMFS. */
- if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
- return 1;
- } else {
- if (in_mem(addr, size, memory_start, physical_mem_end))
- return 1;
- }
-
- if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
- return 1;
-
- if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
- return 1;
-#ifdef COREB_L1_CODE_START
- if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
- return 1;
-#endif
-
-#ifndef CONFIG_EXCEPTION_L1_SCRATCH
- if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
- return 1;
-#endif
-
- aret = in_async(addr, size);
- if (aret < 2)
- return aret;
-
- if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
- return 1;
-
- if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
- return 1;
- if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
- return 1;
-
- return 0;
-}
-EXPORT_SYMBOL(_access_ok);
-#endif /* CONFIG_ACCESS_CHECK */
diff --git a/arch/blackfin/kernel/pseudodbg.c b/arch/blackfin/kernel/pseudodbg.c
deleted file mode 100644
index db85bc9..0000000
--- a/arch/blackfin/kernel/pseudodbg.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* The fake debug assert instructions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/ptrace.h>
-
-const char * const greg_names[] = {
- "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
- "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP",
- "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3",
- "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3",
- "A0.X", "A0.W", "A1.X", "A1.W", "<res>", "<res>", "ASTAT", "RETS",
- "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>",
- "LC0", "LT0", "LB0", "LC1", "LT1", "LB1", "CYCLES", "CYCLES2",
- "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT",
-};
-
-static const char *get_allreg_name(int grp, int reg)
-{
- return greg_names[(grp << 3) | reg];
-}
-
-/*
- * Unfortunately, the pt_regs structure is not laid out the same way as the
- * hardware register file, so we need to do some fix ups.
- *
- * CYCLES is not stored in the pt_regs structure - so, we just read it from
- * the hardware.
- *
- * Don't support:
- * - All reserved registers
- * - All in group 7 are (supervisors only)
- */
-
-static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg)
-{
- long *val = &fp->r0;
- unsigned long tmp;
-
- /* Only do Dregs and Pregs for now */
- if (grp == 5 ||
- (grp == 4 && (reg == 4 || reg == 5)) ||
- (grp == 7))
- return false;
-
- if (grp == 0 || (grp == 1 && reg < 6))
- val -= (reg + 8 * grp);
- else if (grp == 1 && reg == 6)
- val = &fp->usp;
- else if (grp == 1 && reg == 7)
- val = &fp->fp;
- else if (grp == 2) {
- val = &fp->i0;
- val -= reg;
- } else if (grp == 3 && reg >= 4) {
- val = &fp->l0;
- val -= (reg - 4);
- } else if (grp == 3 && reg < 4) {
- val = &fp->b0;
- val -= reg;
- } else if (grp == 4 && reg < 4) {
- val = &fp->a0x;
- val -= reg;
- } else if (grp == 4 && reg == 6)
- val = &fp->astat;
- else if (grp == 4 && reg == 7)
- val = &fp->rets;
- else if (grp == 6 && reg < 6) {
- val = &fp->lc0;
- val -= reg;
- } else if (grp == 6 && reg == 6) {
- __asm__ __volatile__("%0 = cycles;\n" : "=d"(tmp));
- val = &tmp;
- } else if (grp == 6 && reg == 7) {
- __asm__ __volatile__("%0 = cycles2;\n" : "=d"(tmp));
- val = &tmp;
- }
-
- *value = *val;
- return true;
-
-}
-
-#define PseudoDbg_Assert_opcode 0xf0000000
-#define PseudoDbg_Assert_expected_bits 0
-#define PseudoDbg_Assert_expected_mask 0xffff
-#define PseudoDbg_Assert_regtest_bits 16
-#define PseudoDbg_Assert_regtest_mask 0x7
-#define PseudoDbg_Assert_grp_bits 19
-#define PseudoDbg_Assert_grp_mask 0x7
-#define PseudoDbg_Assert_dbgop_bits 22
-#define PseudoDbg_Assert_dbgop_mask 0x3
-#define PseudoDbg_Assert_dontcare_bits 24
-#define PseudoDbg_Assert_dontcare_mask 0x7
-#define PseudoDbg_Assert_code_bits 27
-#define PseudoDbg_Assert_code_mask 0x1f
-
-/*
- * DBGA - debug assert
- */
-bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode)
-{
- int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
- int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask);
- int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask);
- int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask);
- long value;
-
- if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode)
- return false;
-
- if (!fix_up_reg(fp, &value, grp, regtest))
- return false;
-
- if (dbgop == 0 || dbgop == 2) {
- /* DBGA ( regs_lo , uimm16 ) */
- /* DBGAL ( regs , uimm16 ) */
- if (expected != (value & 0xFFFF)) {
- pr_notice("DBGA (%s.L,0x%x) failure, got 0x%x\n",
- get_allreg_name(grp, regtest),
- expected, (unsigned int)(value & 0xFFFF));
- return false;
- }
-
- } else if (dbgop == 1 || dbgop == 3) {
- /* DBGA ( regs_hi , uimm16 ) */
- /* DBGAH ( regs , uimm16 ) */
- if (expected != ((value >> 16) & 0xFFFF)) {
- pr_notice("DBGA (%s.H,0x%x) failure, got 0x%x\n",
- get_allreg_name(grp, regtest),
- expected, (unsigned int)((value >> 16) & 0xFFFF));
- return false;
- }
- }
-
- fp->pc += 4;
- return true;
-}
-
-#define PseudoDbg_opcode 0xf8000000
-#define PseudoDbg_reg_bits 0
-#define PseudoDbg_reg_mask 0x7
-#define PseudoDbg_grp_bits 3
-#define PseudoDbg_grp_mask 0x7
-#define PseudoDbg_fn_bits 6
-#define PseudoDbg_fn_mask 0x3
-#define PseudoDbg_code_bits 8
-#define PseudoDbg_code_mask 0xff
-
-/*
- * DBG - debug (dump a register value out)
- */
-bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode)
-{
- int grp, fn, reg;
- long value, value1;
-
- if ((opcode & 0xFF000000) != PseudoDbg_opcode)
- return false;
-
- opcode >>= 16;
- grp = ((opcode >> PseudoDbg_grp_bits) & PseudoDbg_reg_mask);
- fn = ((opcode >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
- reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
-
- if (fn == 3 && (reg == 0 || reg == 1)) {
- if (!fix_up_reg(fp, &value, 4, 2 * reg))
- return false;
- if (!fix_up_reg(fp, &value1, 4, 2 * reg + 1))
- return false;
-
- pr_notice("DBG A%i = %02lx%08lx\n", reg, value & 0xFF, value1);
- fp->pc += 2;
- return true;
-
- } else if (fn == 0) {
- if (!fix_up_reg(fp, &value, grp, reg))
- return false;
-
- pr_notice("DBG %s = %08lx\n", get_allreg_name(grp, reg), value);
- fp->pc += 2;
- return true;
- }
-
- return false;
-}
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
deleted file mode 100644
index a682709..0000000
--- a/arch/blackfin/kernel/ptrace.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
- * these modifications are Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/elf.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/regset.h>
-#include <linux/signal.h>
-#include <linux/tracehook.h>
-#include <linux/uaccess.h>
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/asm-offsets.h>
-#include <asm/dma.h>
-#include <asm/fixed_code.h>
-#include <asm/cacheflush.h>
-#include <asm/mem_map.h>
-#include <asm/mmu_context.h>
-
-/*
- * does not yet catch signals sent when the child dies.
- * in exit.c or in signal.c.
- */
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-static inline long
-get_reg(struct task_struct *task, unsigned long regno,
- unsigned long __user *datap)
-{
- long tmp;
- struct pt_regs *regs = task_pt_regs(task);
-
- if (regno & 3 || regno > PT_LAST_PSEUDO)
- return -EIO;
-
- switch (regno) {
- case PT_TEXT_ADDR:
- tmp = task->mm->start_code;
- break;
- case PT_TEXT_END_ADDR:
- tmp = task->mm->end_code;
- break;
- case PT_DATA_ADDR:
- tmp = task->mm->start_data;
- break;
- case PT_USP:
- tmp = task->thread.usp;
- break;
- default:
- if (regno < sizeof(*regs)) {
- void *reg_ptr = regs;
- tmp = *(long *)(reg_ptr + regno);
- } else
- return -EIO;
- }
-
- return put_user(tmp, datap);
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-static inline int
-put_reg(struct task_struct *task, unsigned long regno, unsigned long data)
-{
- struct pt_regs *regs = task_pt_regs(task);
-
- if (regno & 3 || regno > PT_LAST_PSEUDO)
- return -EIO;
-
- switch (regno) {
- case PT_PC:
- /*********************************************************************/
- /* At this point the kernel is most likely in exception. */
- /* The RETX register will be used to populate the pc of the process. */
- /*********************************************************************/
- regs->retx = data;
- regs->pc = data;
- break;
- case PT_RETX:
- break; /* regs->retx = data; break; */
- case PT_USP:
- regs->usp = data;
- task->thread.usp = data;
- break;
- case PT_SYSCFG: /* don't let userspace screw with this */
- if ((data & ~1) != 0x6)
- pr_warning("ptrace: ignore syscfg write of %#lx\n", data);
- break; /* regs->syscfg = data; break; */
- default:
- if (regno < sizeof(*regs)) {
- void *reg_offset = regs;
- *(long *)(reg_offset + regno) = data;
- }
- /* Ignore writes to pseudo registers */
- }
-
- return 0;
-}
-
-/*
- * check that an address falls within the bounds of the target process's memory mappings
- */
-int
-is_user_addr_valid(struct task_struct *child, unsigned long start, unsigned long len)
-{
- bool valid;
- struct vm_area_struct *vma;
- struct sram_list_struct *sraml;
-
- /* overflow */
- if (start + len < start)
- return -EIO;
-
- down_read(&child->mm->mmap_sem);
- vma = find_vma(child->mm, start);
- valid = vma && start >= vma->vm_start && start + len <= vma->vm_end;
- up_read(&child->mm->mmap_sem);
- if (valid)
- return 0;
-
- for (sraml = child->mm->context.sram_list; sraml; sraml = sraml->next)
- if (start >= (unsigned long)sraml->addr
- && start + len < (unsigned long)sraml->addr + sraml->length)
- return 0;
-
- if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END)
- return 0;
-
-#ifdef CONFIG_APP_STACK_L1
- if (child->mm->context.l1_stack_save)
- if (start >= (unsigned long)l1_stack_base &&
- start + len < (unsigned long)l1_stack_base + l1_stack_len)
- return 0;
-#endif
-
- return -EIO;
-}
-
-/*
- * retrieve the contents of Blackfin userspace general registers
- */
-static int genregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* This sucks ... */
- regs->usp = target->thread.usp;
-
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- regs, 0, sizeof(*regs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- sizeof(*regs), -1);
-}
-
-/*
- * update the contents of the Blackfin userspace general registers
- */
-static int genregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* Don't let people set SYSCFG (it's@the end of pt_regs) */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- regs, 0, PT_SYSCFG);
- if (ret < 0)
- return ret;
-
- /* This sucks ... */
- target->thread.usp = regs->usp;
- /* regs->retx = regs->pc; */
-
- return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- PT_SYSCFG, -1);
-}
-
-/*
- * Define the register sets available on the Blackfin under Linux
- */
-enum bfin_regset {
- REGSET_GENERAL,
-};
-
-static const struct user_regset bfin_regsets[] = {
- [REGSET_GENERAL] = {
- .core_note_type = NT_PRSTATUS,
- .n = sizeof(struct pt_regs) / sizeof(long),
- .size = sizeof(long),
- .align = sizeof(long),
- .get = genregs_get,
- .set = genregs_set,
- },
-};
-
-static const struct user_regset_view user_bfin_native_view = {
- .name = "Blackfin",
- .e_machine = EM_BLACKFIN,
- .regsets = bfin_regsets,
- .n = ARRAY_SIZE(bfin_regsets),
-};
-
-const struct user_regset_view *task_user_regset_view(struct task_struct *task)
-{
- return &user_bfin_native_view;
-}
-
-void user_enable_single_step(struct task_struct *child)
-{
- struct pt_regs *regs = task_pt_regs(child);
- regs->syscfg |= SYSCFG_SSSTEP;
-
- set_tsk_thread_flag(child, TIF_SINGLESTEP);
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- struct pt_regs *regs = task_pt_regs(child);
- regs->syscfg &= ~SYSCFG_SSSTEP;
-
- clear_tsk_thread_flag(child, TIF_SINGLESTEP);
-}
-
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- int ret;
- unsigned long __user *datap = (unsigned long __user *)data;
- void *paddr = (void *)addr;
-
- switch (request) {
- /* when I and D space are separate, these will need to be fixed. */
- case PTRACE_PEEKDATA:
- pr_debug("ptrace: PEEKDATA\n");
- /* fall through */
- case PTRACE_PEEKTEXT: /* read word at location addr. */
- {
- unsigned long tmp = 0;
- int copied = 0, to_copy = sizeof(tmp);
-
- ret = -EIO;
- pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + %i\n", addr, to_copy);
- if (is_user_addr_valid(child, addr, to_copy) < 0)
- break;
- pr_debug("ptrace: user address is valid\n");
-
- switch (bfin_mem_access_type(addr, to_copy)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- copied = ptrace_access_vm(child, addr, &tmp,
- to_copy, FOLL_FORCE);
- if (copied)
- break;
-
- /* hrm, why didn't that work ... maybe no mapping */
- if (addr >= FIXED_CODE_START &&
- addr + to_copy <= FIXED_CODE_END) {
- copy_from_user_page(0, 0, 0, &tmp, paddr, to_copy);
- copied = to_copy;
- } else if (addr >= BOOT_ROM_START) {
- memcpy(&tmp, paddr, to_copy);
- copied = to_copy;
- }
-
- break;
- case BFIN_MEM_ACCESS_DMA:
- if (safe_dma_memcpy(&tmp, paddr, to_copy))
- copied = to_copy;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(&tmp, paddr, to_copy))
- copied = to_copy;
- break;
- default:
- copied = 0;
- break;
- }
-
- pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp);
- if (copied == to_copy)
- ret = put_user(tmp, datap);
- break;
- }
-
- /* when I and D space are separate, this will have to be fixed. */
- case PTRACE_POKEDATA:
- pr_debug("ptrace: PTRACE_PEEKDATA\n");
- /* fall through */
- case PTRACE_POKETEXT: /* write the word at location addr. */
- {
- int copied = 0, to_copy = sizeof(data);
-
- ret = -EIO;
- pr_debug("ptrace: POKETEXT at addr 0x%08lx + %i bytes %lx\n",
- addr, to_copy, data);
- if (is_user_addr_valid(child, addr, to_copy) < 0)
- break;
- pr_debug("ptrace: user address is valid\n");
-
- switch (bfin_mem_access_type(addr, to_copy)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- copied = ptrace_access_vm(child, addr, &data,
- to_copy,
- FOLL_FORCE | FOLL_WRITE);
- break;
- case BFIN_MEM_ACCESS_DMA:
- if (safe_dma_memcpy(paddr, &data, to_copy))
- copied = to_copy;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(paddr, &data, to_copy))
- copied = to_copy;
- break;
- default:
- copied = 0;
- break;
- }
-
- pr_debug("ptrace: copied size %d\n", copied);
- if (copied == to_copy)
- ret = 0;
- break;
- }
-
- case PTRACE_PEEKUSR:
- switch (addr) {
-#ifdef CONFIG_BINFMT_ELF_FDPIC /* backwards compat */
- case PT_FDPIC_EXEC:
- request = PTRACE_GETFDPIC;
- addr = PTRACE_GETFDPIC_EXEC;
- goto case_default;
- case PT_FDPIC_INTERP:
- request = PTRACE_GETFDPIC;
- addr = PTRACE_GETFDPIC_INTERP;
- goto case_default;
-#endif
- default:
- ret = get_reg(child, addr, datap);
- }
- pr_debug("ptrace: PEEKUSR reg %li with %#lx = %i\n", addr, data, ret);
- break;
-
- case PTRACE_POKEUSR:
- ret = put_reg(child, addr, data);
- pr_debug("ptrace: POKEUSR reg %li with %li = %i\n", addr, data, ret);
- break;
-
- case PTRACE_GETREGS:
- pr_debug("ptrace: PTRACE_GETREGS\n");
- return copy_regset_to_user(child, &user_bfin_native_view,
- REGSET_GENERAL,
- 0, sizeof(struct pt_regs),
- datap);
-
- case PTRACE_SETREGS:
- pr_debug("ptrace: PTRACE_SETREGS\n");
- return copy_regset_from_user(child, &user_bfin_native_view,
- REGSET_GENERAL,
- 0, sizeof(struct pt_regs),
- datap);
-
- case_default:
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-asmlinkage int syscall_trace_enter(struct pt_regs *regs)
-{
- int ret = 0;
-
- if (test_thread_flag(TIF_SYSCALL_TRACE))
- ret = tracehook_report_syscall_entry(regs);
-
- return ret;
-}
-
-asmlinkage void syscall_trace_leave(struct pt_regs *regs)
-{
- int step;
-
- step = test_thread_flag(TIF_SINGLESTEP);
- if (step || test_thread_flag(TIF_SYSCALL_TRACE))
- tracehook_report_syscall_exit(regs, step);
-}
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
deleted file mode 100644
index c4f50a3..0000000
--- a/arch/blackfin/kernel/reboot.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
- *
- * Copyright 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/interrupt.h>
-#include <asm/bfin-global.h>
-#include <asm/reboot.h>
-#include <asm/bfrom.h>
-
-/* A system soft reset makes external memory unusable so force
- * this function into L1. We use the compiler ssync here rather
- * than SSYNC() because it's safe (no interrupts and such) and
- * we save some L1. We do not need to force sanity in the SYSCR
- * register as the BMODE selection bit is cleared by the soft
- * reset while the Core B bit (on dual core parts) is cleared by
- * the core reset.
- */
-__attribute__ ((__l1_text__, __noreturn__))
-static void bfin_reset(void)
-{
-#ifndef CONFIG_BF60x
- if (!ANOMALY_05000353 && !ANOMALY_05000386)
- bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
-
- /* Wait for completion of "system" events such as cache line
- * line fills so that we avoid infinite stalls later on as
- * much as possible. This code is in L1, so it won't trigger
- * any such event after this point in time.
- */
- __builtin_bfin_ssync();
-
- /* Initiate System software reset. */
- bfin_write_SWRST(0x7);
-
- /* Due to the way reset is handled in the hardware, we need
- * to delay for 10 SCLKS. The only reliable way to do this is
- * to calculate the CCLK/SCLK ratio and multiply 10. For now,
- * we'll assume worse case which is a 1:15 ratio.
- */
- asm(
- "LSETUP (1f, 1f) LC0 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 10)
- : "LC0", "LB0", "LT0"
- );
-
- /* Clear System software reset */
- bfin_write_SWRST(0);
-
- /* The BF526 ROM will crash during reset */
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
- /* Seems to be fixed with newer parts though ... */
- if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
- bfin_read_SWRST();
-#endif
- /* Wait for the SWRST write to complete. Cannot rely on SSYNC
- * though as the System state is all reset now.
- */
- asm(
- "LSETUP (1f, 1f) LC1 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 1)
- : "LC1", "LB1", "LT1"
- );
-
- while (1)
- /* Issue core reset */
- asm("raise 1");
-#else
- while (1)
- bfin_write_RCU0_CTL(0x1);
-#endif
-}
-
-__attribute__((weak))
-void native_machine_restart(char *cmd)
-{
-}
-
-void machine_restart(char *cmd)
-{
- native_machine_restart(cmd);
- if (smp_processor_id())
- smp_call_function((void *)bfin_reset, 0, 1);
- else
- bfin_reset();
-}
-
-__attribute__((weak))
-void native_machine_halt(void)
-{
- idle_with_irq_disabled();
-}
-
-void machine_halt(void)
-{
- native_machine_halt();
-}
-
-__attribute__((weak))
-void native_machine_power_off(void)
-{
- idle_with_irq_disabled();
-}
-
-void machine_power_off(void)
-{
- native_machine_power_off();
-}
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
deleted file mode 100644
index ad82468..0000000
--- a/arch/blackfin/kernel/setup.c
+++ /dev/null
@@ -1,1468 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/delay.h>
-#include <linux/console.h>
-#include <linux/bootmem.h>
-#include <linux/seq_file.h>
-#include <linux/cpu.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/tty.h>
-#include <linux/pfn.h>
-
-#ifdef CONFIG_MTD_UCLINUX
-#include <linux/mtd/map.h>
-#include <linux/ext2_fs.h>
-#include <uapi/linux/cramfs_fs.h>
-#include <linux/romfs_fs.h>
-#endif
-
-#include <asm/cplb.h>
-#include <asm/cacheflush.h>
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-#include <asm/clocks.h>
-#include <asm/div64.h>
-#include <asm/cpu.h>
-#include <asm/fixed_code.h>
-#include <asm/early_printk.h>
-#include <asm/irq_handler.h>
-#include <asm/pda.h>
-#ifdef CONFIG_BF60x
-#include <mach/pm.h>
-#endif
-#ifdef CONFIG_SCB_PRIORITY
-#include <asm/scb.h>
-#endif
-
-u16 _bfin_swrst;
-EXPORT_SYMBOL(_bfin_swrst);
-
-unsigned long memory_start, memory_end, physical_mem_end;
-unsigned long _rambase, _ramstart, _ramend;
-unsigned long reserved_mem_dcache_on;
-unsigned long reserved_mem_icache_on;
-EXPORT_SYMBOL(memory_start);
-EXPORT_SYMBOL(memory_end);
-EXPORT_SYMBOL(physical_mem_end);
-EXPORT_SYMBOL(_ramend);
-EXPORT_SYMBOL(reserved_mem_dcache_on);
-
-#ifdef CONFIG_MTD_UCLINUX
-extern struct map_info uclinux_ram_map;
-unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
-EXPORT_SYMBOL(memory_mtd_end);
-EXPORT_SYMBOL(memory_mtd_start);
-EXPORT_SYMBOL(mtd_size);
-#endif
-
-char __initdata command_line[COMMAND_LINE_SIZE];
-struct blackfin_initial_pda __initdata initial_pda;
-
-/* boot memmap, for parsing "memmap=" */
-#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
-#define BFIN_MEMMAP_RAM 1
-#define BFIN_MEMMAP_RESERVED 2
-static struct bfin_memmap {
- int nr_map;
- struct bfin_memmap_entry {
- unsigned long long addr; /* start of memory segment */
- unsigned long long size;
- unsigned long type;
- } map[BFIN_MEMMAP_MAX];
-} bfin_memmap __initdata;
-
-/* for memmap sanitization */
-struct change_member {
- struct bfin_memmap_entry *pentry; /* pointer to original entry */
- unsigned long long addr; /* address for this change point */
-};
-static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
-static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
-static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
-static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
-
-DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
-
-static int early_init_clkin_hz(char *buf);
-
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
-void __init generate_cplb_tables(void)
-{
- unsigned int cpu;
-
- generate_cplb_tables_all();
- /* Generate per-CPU I&D CPLB tables */
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
- generate_cplb_tables_cpu(cpu);
-}
-#endif
-
-void bfin_setup_caches(unsigned int cpu)
-{
-#ifdef CONFIG_BFIN_ICACHE
- bfin_icache_init(icplb_tbl[cpu]);
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
- bfin_dcache_init(dcplb_tbl[cpu]);
-#endif
-
- bfin_setup_cpudata(cpu);
-
- /*
- * In cache coherence emulation mode, we need to have the
- * D-cache enabled before running any atomic operation which
- * might involve cache invalidation (i.e. spinlock, rwlock).
- * So printk's are deferred until then.
- */
-#ifdef CONFIG_BFIN_ICACHE
- printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
- printk(KERN_INFO " External memory:"
-# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- " cacheable"
-# else
- " uncacheable"
-# endif
- " in instruction cache\n");
- if (L2_LENGTH)
- printk(KERN_INFO " L2 SRAM :"
-# ifdef CONFIG_BFIN_L2_ICACHEABLE
- " cacheable"
-# else
- " uncacheable"
-# endif
- " in instruction cache\n");
-
-#else
- printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
- printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
- printk(KERN_INFO " External memory:"
-# if defined CONFIG_BFIN_EXTMEM_WRITEBACK
- " cacheable (write-back)"
-# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
- " cacheable (write-through)"
-# else
- " uncacheable"
-# endif
- " in data cache\n");
- if (L2_LENGTH)
- printk(KERN_INFO " L2 SRAM :"
-# if defined CONFIG_BFIN_L2_WRITEBACK
- " cacheable (write-back)"
-# elif defined CONFIG_BFIN_L2_WRITETHROUGH
- " cacheable (write-through)"
-# else
- " uncacheable"
-# endif
- " in data cache\n");
-#else
- printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
-#endif
-}
-
-void bfin_setup_cpudata(unsigned int cpu)
-{
- struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
-
- cpudata->imemctl = bfin_read_IMEM_CONTROL();
- cpudata->dmemctl = bfin_read_DMEM_CONTROL();
-}
-
-void __init bfin_cache_init(void)
-{
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
- generate_cplb_tables();
-#endif
- bfin_setup_caches(0);
-}
-
-void __init bfin_relocate_l1_mem(void)
-{
- unsigned long text_l1_len = (unsigned long)_text_l1_len;
- unsigned long data_l1_len = (unsigned long)_data_l1_len;
- unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
- unsigned long l2_len = (unsigned long)_l2_len;
-
- early_shadow_stamp();
-
- /*
- * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
- * we know that everything about l1 text/data is nice and aligned,
- * so copy by 4 byte chunks, and don't worry about overlapping
- * src/dest.
- *
- * We can't use the dma_memcpy functions, since they can call
- * scheduler functions which might be in L1 :( and core writes
- * into L1 instruction cause bad access errors, so we are stuck,
- * we are required to use DMA, but can't use the common dma
- * functions. We can't use memcpy either - since that might be
- * going to be in the relocated L1
- */
-
- blackfin_dma_early_init();
-
- /* if necessary, copy L1 text to L1 instruction SRAM */
- if (L1_CODE_LENGTH && text_l1_len)
- early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
-
- /* if necessary, copy L1 data to L1 data bank A SRAM */
- if (L1_DATA_A_LENGTH && data_l1_len)
- early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
-
- /* if necessary, copy L1 data B to L1 data bank B SRAM */
- if (L1_DATA_B_LENGTH && data_b_l1_len)
- early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
-
- early_dma_memcpy_done();
-
-#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
- blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1;
-#endif
-
- /* if necessary, copy L2 text/data to L2 SRAM */
- if (L2_LENGTH && l2_len)
- memcpy(_stext_l2, _l2_lma, l2_len);
-}
-
-#ifdef CONFIG_SMP
-void __init bfin_relocate_coreb_l1_mem(void)
-{
- unsigned long text_l1_len = (unsigned long)_text_l1_len;
- unsigned long data_l1_len = (unsigned long)_data_l1_len;
- unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
-
- blackfin_dma_early_init();
-
- /* if necessary, copy L1 text to L1 instruction SRAM */
- if (L1_CODE_LENGTH && text_l1_len)
- early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
- text_l1_len);
-
- /* if necessary, copy L1 data to L1 data bank A SRAM */
- if (L1_DATA_A_LENGTH && data_l1_len)
- early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma,
- data_l1_len);
-
- /* if necessary, copy L1 data B to L1 data bank B SRAM */
- if (L1_DATA_B_LENGTH && data_b_l1_len)
- early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
- data_b_l1_len);
-
- early_dma_memcpy_done();
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
- blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
- (unsigned long)_stext_l1 + COREB_L1_CODE_START;
-#endif
-}
-#endif
-
-#ifdef CONFIG_ROMKERNEL
-void __init bfin_relocate_xip_data(void)
-{
- early_shadow_stamp();
-
- memcpy(_sdata, _data_lma, (unsigned long)_data_len - THREAD_SIZE + sizeof(struct thread_info));
- memcpy(_sinitdata, _init_data_lma, (unsigned long)_init_data_len);
-}
-#endif
-
-/* add_memory_region to memmap */
-static void __init add_memory_region(unsigned long long start,
- unsigned long long size, int type)
-{
- int i;
-
- i = bfin_memmap.nr_map;
-
- if (i == BFIN_MEMMAP_MAX) {
- printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
- return;
- }
-
- bfin_memmap.map[i].addr = start;
- bfin_memmap.map[i].size = size;
- bfin_memmap.map[i].type = type;
- bfin_memmap.nr_map++;
-}
-
-/*
- * Sanitize the boot memmap, removing overlaps.
- */
-static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
-{
- struct change_member *change_tmp;
- unsigned long current_type, last_type;
- unsigned long long last_addr;
- int chgidx, still_changing;
- int overlap_entries;
- int new_entry;
- int old_nr, new_nr, chg_nr;
- int i;
-
- /*
- Visually we're performing the following (1,2,3,4 = memory types)
-
- Sample memory map (w/overlaps):
- ____22__________________
- ______________________4_
- ____1111________________
- _44_____________________
- 11111111________________
- ____________________33__
- ___________44___________
- __________33333_________
- ______________22________
- ___________________2222_
- _________111111111______
- _____________________11_
- _________________4______
-
- Sanitized equivalent (no overlap):
- 1_______________________
- _44_____________________
- ___1____________________
- ____22__________________
- ______11________________
- _________1______________
- __________3_____________
- ___________44___________
- _____________33_________
- _______________2________
- ________________1_______
- _________________4______
- ___________________2____
- ____________________33__
- ______________________4_
- */
- /* if there's only one memory region, don't bother */
- if (*pnr_map < 2)
- return -1;
-
- old_nr = *pnr_map;
-
- /* bail out if we find any unreasonable addresses in memmap */
- for (i = 0; i < old_nr; i++)
- if (map[i].addr + map[i].size < map[i].addr)
- return -1;
-
- /* create pointers for initial change-point information (for sorting) */
- for (i = 0; i < 2*old_nr; i++)
- change_point[i] = &change_point_list[i];
-
- /* record all known change-points (starting and ending addresses),
- omitting those that are for empty memory regions */
- chgidx = 0;
- for (i = 0; i < old_nr; i++) {
- if (map[i].size != 0) {
- change_point[chgidx]->addr = map[i].addr;
- change_point[chgidx++]->pentry = &map[i];
- change_point[chgidx]->addr = map[i].addr + map[i].size;
- change_point[chgidx++]->pentry = &map[i];
- }
- }
- chg_nr = chgidx; /* true number of change-points */
-
- /* sort change-point list by memory addresses (low -> high) */
- still_changing = 1;
- while (still_changing) {
- still_changing = 0;
- for (i = 1; i < chg_nr; i++) {
- /* if <current_addr> > <last_addr>, swap */
- /* or, if current=<start_addr> & last=<end_addr>, swap */
- if ((change_point[i]->addr < change_point[i-1]->addr) ||
- ((change_point[i]->addr == change_point[i-1]->addr) &&
- (change_point[i]->addr == change_point[i]->pentry->addr) &&
- (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
- ) {
- change_tmp = change_point[i];
- change_point[i] = change_point[i-1];
- change_point[i-1] = change_tmp;
- still_changing = 1;
- }
- }
- }
-
- /* create a new memmap, removing overlaps */
- overlap_entries = 0; /* number of entries in the overlap table */
- new_entry = 0; /* index for creating new memmap entries */
- last_type = 0; /* start with undefined memory type */
- last_addr = 0; /* start with 0 as last starting address */
- /* loop through change-points, determining affect on the new memmap */
- for (chgidx = 0; chgidx < chg_nr; chgidx++) {
- /* keep track of all overlapping memmap entries */
- if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
- /* add map entry to overlap list (> 1 entry implies an overlap) */
- overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
- } else {
- /* remove entry from list (order independent, so swap with last) */
- for (i = 0; i < overlap_entries; i++) {
- if (overlap_list[i] == change_point[chgidx]->pentry)
- overlap_list[i] = overlap_list[overlap_entries-1];
- }
- overlap_entries--;
- }
- /* if there are overlapping entries, decide which "type" to use */
- /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
- current_type = 0;
- for (i = 0; i < overlap_entries; i++)
- if (overlap_list[i]->type > current_type)
- current_type = overlap_list[i]->type;
- /* continue building up new memmap based on this information */
- if (current_type != last_type) {
- if (last_type != 0) {
- new_map[new_entry].size =
- change_point[chgidx]->addr - last_addr;
- /* move forward only if the new size was non-zero */
- if (new_map[new_entry].size != 0)
- if (++new_entry >= BFIN_MEMMAP_MAX)
- break; /* no more space left for new entries */
- }
- if (current_type != 0) {
- new_map[new_entry].addr = change_point[chgidx]->addr;
- new_map[new_entry].type = current_type;
- last_addr = change_point[chgidx]->addr;
- }
- last_type = current_type;
- }
- }
- new_nr = new_entry; /* retain count for new entries */
-
- /* copy new mapping into original location */
- memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
- *pnr_map = new_nr;
-
- return 0;
-}
-
-static void __init print_memory_map(char *who)
-{
- int i;
-
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
- bfin_memmap.map[i].addr,
- bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
- switch (bfin_memmap.map[i].type) {
- case BFIN_MEMMAP_RAM:
- printk(KERN_CONT "(usable)\n");
- break;
- case BFIN_MEMMAP_RESERVED:
- printk(KERN_CONT "(reserved)\n");
- break;
- default:
- printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type);
- break;
- }
- }
-}
-
-static __init int parse_memmap(char *arg)
-{
- unsigned long long start_at, mem_size;
-
- if (!arg)
- return -EINVAL;
-
- mem_size = memparse(arg, &arg);
- if (*arg == '@') {
- start_at = memparse(arg+1, &arg);
- add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
- } else if (*arg == '$') {
- start_at = memparse(arg+1, &arg);
- add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
- }
-
- return 0;
-}
-
-/*
- * Initial parsing of the command line. Currently, we support:
- * - Controlling the linux memory size: mem=xxx[KMG]
- * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
- * $ -> reserved memory is dcacheable
- * # -> reserved memory is icacheable
- * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
- * @ from <start> to <start>+<mem>, type RAM
- * $ from <start> to <start>+<mem>, type RESERVED
- */
-static __init void parse_cmdline_early(char *cmdline_p)
-{
- char c = ' ', *to = cmdline_p;
- unsigned int memsize;
- for (;;) {
- if (c == ' ') {
- if (!memcmp(to, "mem=", 4)) {
- to += 4;
- memsize = memparse(to, &to);
- if (memsize)
- _ramend = memsize;
-
- } else if (!memcmp(to, "max_mem=", 8)) {
- to += 8;
- memsize = memparse(to, &to);
- if (memsize) {
- physical_mem_end = memsize;
- if (*to != ' ') {
- if (*to == '$'
- || *(to + 1) == '$')
- reserved_mem_dcache_on = 1;
- if (*to == '#'
- || *(to + 1) == '#')
- reserved_mem_icache_on = 1;
- }
- }
- } else if (!memcmp(to, "clkin_hz=", 9)) {
- to += 9;
- early_init_clkin_hz(to);
-#ifdef CONFIG_EARLY_PRINTK
- } else if (!memcmp(to, "earlyprintk=", 12)) {
- to += 12;
- setup_early_printk(to);
-#endif
- } else if (!memcmp(to, "memmap=", 7)) {
- to += 7;
- parse_memmap(to);
- }
- }
- c = *(to++);
- if (!c)
- break;
- }
-}
-
-/*
- * Setup memory defaults from user config.
- * The physical memory layout looks like:
- *
- * [_rambase, _ramstart]: kernel image
- * [memory_start, memory_end]: dynamic memory managed by kernel
- * [memory_end, _ramend]: reserved memory
- * [memory_mtd_start(memory_end),
- * memory_mtd_start + mtd_size]: rootfs (if any)
- * [_ramend - DMA_UNCACHED_REGION,
- * _ramend]: uncached DMA region
- * [_ramend, physical_mem_end]: memory not managed by kernel
- */
-static __init void memory_setup(void)
-{
-#ifdef CONFIG_MTD_UCLINUX
- unsigned long mtd_phys = 0;
-#endif
- unsigned long max_mem;
-
- _rambase = CONFIG_BOOT_LOAD;
- _ramstart = (unsigned long)_end;
-
- if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
- console_init();
- panic("DMA region exceeds memory limit: %lu.",
- _ramend - _ramstart);
- }
- max_mem = memory_end = _ramend - DMA_UNCACHED_REGION;
-
-#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
- /* Due to a Hardware Anomaly we need to limit the size of usable
- * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
- * 05000263 - Hardware loop corrupted when taking an ICPLB exception
- */
-# if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
- if (max_mem >= 56 * 1024 * 1024)
- max_mem = 56 * 1024 * 1024;
-# else
- if (max_mem >= 60 * 1024 * 1024)
- max_mem = 60 * 1024 * 1024;
-# endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
-#endif /* ANOMALY_05000263 */
-
-
-#ifdef CONFIG_MPU
- /* Round up to multiple of 4MB */
- memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
-#else
- memory_start = PAGE_ALIGN(_ramstart);
-#endif
-
-#if defined(CONFIG_MTD_UCLINUX)
- /* generic memory mapped MTD driver */
- memory_mtd_end = memory_end;
-
- mtd_phys = _ramstart;
- mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
-
-# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
- if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
- mtd_size =
- PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
-# endif
-
-# if defined(CONFIG_CRAMFS)
- if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
- mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
-# endif
-
-# if defined(CONFIG_ROMFS_FS)
- if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
- && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) {
- mtd_size =
- PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
-
- /* ROM_FS is XIP, so if we found it, we need to limit memory */
- if (memory_end > max_mem) {
- pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
- (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- memory_end = max_mem;
- }
- }
-# endif /* CONFIG_ROMFS_FS */
-
- /* Since the default MTD_UCLINUX has no magic number, we just blindly
- * read 8 past the end of the kernel's image, and look at it.
- * When no image is attached, mtd_size is set to a random number
- * Do some basic sanity checks before operating on things
- */
- if (mtd_size == 0 || memory_end <= mtd_size) {
- pr_emerg("Could not find valid ram mtd attached.\n");
- } else {
- memory_end -= mtd_size;
-
- /* Relocate MTD image to the top of memory after the uncached memory area */
- uclinux_ram_map.phys = memory_mtd_start = memory_end;
- uclinux_ram_map.size = mtd_size;
- pr_info("Found mtd parition@0x%p, (len=0x%lx), moving to 0x%p\n",
- _end, mtd_size, (void *)memory_mtd_start);
- dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
- }
-#endif /* CONFIG_MTD_UCLINUX */
-
- /* We need lo limit memory, since everything could have a text section
- * of userspace in it, and expose anomaly 05000263. If the anomaly
- * doesn't exist, or we don't need to - then dont.
- */
- if (memory_end > max_mem) {
- pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
- (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- memory_end = max_mem;
- }
-
-#ifdef CONFIG_MPU
-#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
- page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE -
- ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32;
-#else
- page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
-#endif
- page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
-#endif
-
- init_mm.start_code = (unsigned long)_stext;
- init_mm.end_code = (unsigned long)_etext;
- init_mm.end_data = (unsigned long)_edata;
- init_mm.brk = (unsigned long)0;
-
- printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
-
- printk(KERN_INFO "Memory map:\n"
- " fixedcode = 0x%p-0x%p\n"
- " text = 0x%p-0x%p\n"
- " rodata = 0x%p-0x%p\n"
- " bss = 0x%p-0x%p\n"
- " data = 0x%p-0x%p\n"
- " stack = 0x%p-0x%p\n"
- " init = 0x%p-0x%p\n"
- " available = 0x%p-0x%p\n"
-#ifdef CONFIG_MTD_UCLINUX
- " rootfs = 0x%p-0x%p\n"
-#endif
-#if DMA_UNCACHED_REGION > 0
- " DMA Zone = 0x%p-0x%p\n"
-#endif
- , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
- _stext, _etext,
- __start_rodata, __end_rodata,
- __bss_start, __bss_stop,
- _sdata, _edata,
- (void *)&init_thread_union,
- (void *)((int)(&init_thread_union) + THREAD_SIZE),
- __init_begin, __init_end,
- (void *)_ramstart, (void *)memory_end
-#ifdef CONFIG_MTD_UCLINUX
- , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
-#endif
-#if DMA_UNCACHED_REGION > 0
- , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
-#endif
- );
-}
-
-/*
- * Find the lowest, highest page frame number we have available
- */
-void __init find_min_max_pfn(void)
-{
- int i;
-
- max_pfn = 0;
- min_low_pfn = PFN_DOWN(memory_end);
-
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- unsigned long start, end;
- /* RAM? */
- if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
- continue;
- start = PFN_UP(bfin_memmap.map[i].addr);
- end = PFN_DOWN(bfin_memmap.map[i].addr +
- bfin_memmap.map[i].size);
- if (start >= end)
- continue;
- if (end > max_pfn)
- max_pfn = end;
- if (start < min_low_pfn)
- min_low_pfn = start;
- }
-}
-
-static __init void setup_bootmem_allocator(void)
-{
- int bootmap_size;
- int i;
- unsigned long start_pfn, end_pfn;
- unsigned long curr_pfn, last_pfn, size;
-
- /* mark memory between memory_start and memory_end usable */
- add_memory_region(memory_start,
- memory_end - memory_start, BFIN_MEMMAP_RAM);
- /* sanity check for overlap */
- sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
- print_memory_map("boot memmap");
-
- /* initialize globals in linux/bootmem.h */
- find_min_max_pfn();
- /* pfn of the last usable page frame */
- if (max_pfn > memory_end >> PAGE_SHIFT)
- max_pfn = memory_end >> PAGE_SHIFT;
- /* pfn of last page frame directly mapped by kernel */
- max_low_pfn = max_pfn;
- /* pfn of the first usable page frame after kernel image*/
- if (min_low_pfn < memory_start >> PAGE_SHIFT)
- min_low_pfn = memory_start >> PAGE_SHIFT;
- start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
- end_pfn = memory_end >> PAGE_SHIFT;
-
- /*
- * give all the memory to the bootmap allocator, tell it to put the
- * boot mem_map at the start of memory.
- */
- bootmap_size = init_bootmem_node(NODE_DATA(0),
- memory_start >> PAGE_SHIFT, /* map goes here */
- start_pfn, end_pfn);
-
- /* register the memmap regions with the bootmem allocator */
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- /*
- * Reserve usable memory
- */
- if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
- continue;
- /*
- * We are rounding up the start address of usable memory:
- */
- curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
- if (curr_pfn >= end_pfn)
- continue;
- /*
- * ... and at the end of the usable range downwards:
- */
- last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
- bfin_memmap.map[i].size);
-
- if (last_pfn > end_pfn)
- last_pfn = end_pfn;
-
- /*
- * .. finally, did all the rounding and playing
- * around just make the area go away?
- */
- if (last_pfn <= curr_pfn)
- continue;
-
- size = last_pfn - curr_pfn;
- free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
- }
-
- /* reserve memory before memory_start, including bootmap */
- reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
- memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
- BOOTMEM_DEFAULT);
-}
-
-#define EBSZ_TO_MEG(ebsz) \
-({ \
- int meg = 0; \
- switch (ebsz & 0xf) { \
- case 0x1: meg = 16; break; \
- case 0x3: meg = 32; break; \
- case 0x5: meg = 64; break; \
- case 0x7: meg = 128; break; \
- case 0x9: meg = 256; break; \
- case 0xb: meg = 512; break; \
- } \
- meg; \
-})
-static inline int __init get_mem_size(void)
-{
-#if defined(EBIU_SDBCTL)
-# if defined(BF561_FAMILY)
- int ret = 0;
- u32 sdbctl = bfin_read_EBIU_SDBCTL();
- ret += EBSZ_TO_MEG(sdbctl >> 0);
- ret += EBSZ_TO_MEG(sdbctl >> 8);
- ret += EBSZ_TO_MEG(sdbctl >> 16);
- ret += EBSZ_TO_MEG(sdbctl >> 24);
- return ret;
-# else
- return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
-# endif
-#elif defined(EBIU_DDRCTL1)
- u32 ddrctl = bfin_read_EBIU_DDRCTL1();
- int ret = 0;
- switch (ddrctl & 0xc0000) {
- case DEVSZ_64:
- ret = 64 / 8;
- break;
- case DEVSZ_128:
- ret = 128 / 8;
- break;
- case DEVSZ_256:
- ret = 256 / 8;
- break;
- case DEVSZ_512:
- ret = 512 / 8;
- break;
- }
- switch (ddrctl & 0x30000) {
- case DEVWD_4:
- ret *= 2;
- case DEVWD_8:
- ret *= 2;
- case DEVWD_16:
- break;
- }
- if ((ddrctl & 0xc000) == 0x4000)
- ret *= 2;
- return ret;
-#elif defined(CONFIG_BF60x)
- u32 ddrctl = bfin_read_DMC0_CFG();
- int ret;
- switch (ddrctl & 0xf00) {
- case DEVSZ_64:
- ret = 64 / 8;
- break;
- case DEVSZ_128:
- ret = 128 / 8;
- break;
- case DEVSZ_256:
- ret = 256 / 8;
- break;
- case DEVSZ_512:
- ret = 512 / 8;
- break;
- case DEVSZ_1G:
- ret = 1024 / 8;
- break;
- case DEVSZ_2G:
- ret = 2048 / 8;
- break;
- }
- return ret;
-#endif
- BUG();
-}
-
-__attribute__((weak))
-void __init native_machine_early_platform_add_devices(void)
-{
-}
-
-#ifdef CONFIG_BF60x
-static inline u_long bfin_get_clk(char *name)
-{
- struct clk *clk;
- u_long clk_rate;
-
- clk = clk_get(NULL, name);
- if (IS_ERR(clk))
- return 0;
-
- clk_rate = clk_get_rate(clk);
- clk_put(clk);
- return clk_rate;
-}
-#endif
-
-void __init setup_arch(char **cmdline_p)
-{
- u32 mmr;
- unsigned long sclk, cclk;
-
- native_machine_early_platform_add_devices();
-
- enable_shadow_console();
-
- /* Check to make sure we are running on the right processor */
- mmr = bfin_cpuid();
- if (unlikely(CPUID != bfin_cpuid()))
- printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
- CPU, bfin_cpuid(), bfin_revid());
-
-#ifdef CONFIG_DUMMY_CONSOLE
- conswitchp = &dummy_con;
-#endif
-
-#if defined(CONFIG_CMDLINE_BOOL)
- strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
- command_line[sizeof(command_line) - 1] = 0;
-#endif
-
- /* Keep a copy of command line */
- *cmdline_p = &command_line[0];
- memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
- boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
-
- memset(&bfin_memmap, 0, sizeof(bfin_memmap));
-
-#ifdef CONFIG_BF60x
- /* Should init clock device before parse command early */
- clk_init();
-#endif
- /* If the user does not specify things on the command line, use
- * what the bootloader set things up as
- */
- physical_mem_end = 0;
- parse_cmdline_early(&command_line[0]);
-
- if (_ramend == 0)
- _ramend = get_mem_size() * 1024 * 1024;
-
- if (physical_mem_end == 0)
- physical_mem_end = _ramend;
-
- memory_setup();
-
-#ifndef CONFIG_BF60x
- /* Initialize Async memory banks */
- bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
- bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
- bfin_write_EBIU_AMGCTL(AMGCTLVAL);
-#ifdef CONFIG_EBIU_MBSCTLVAL
- bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
- bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
- bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
-#endif
-#endif
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
- bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
- bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
- bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
- bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
- ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
-#endif
-
- cclk = get_cclk();
- sclk = get_sclk();
-
- if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
- panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
-
-#ifdef BF561_FAMILY
- if (ANOMALY_05000266) {
- bfin_read_IMDMA_D0_IRQ_STATUS();
- bfin_read_IMDMA_D1_IRQ_STATUS();
- }
-#endif
-
- mmr = bfin_read_TBUFCTL();
- printk(KERN_INFO "Hardware Trace %s and %sabled\n",
- (mmr & 0x1) ? "active" : "off",
- (mmr & 0x2) ? "en" : "dis");
-#ifndef CONFIG_BF60x
- mmr = bfin_read_SYSCR();
- printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
-
- /* Newer parts mirror SWRST bits in SYSCR */
-#if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
- defined(CONFIG_BF538) || defined(CONFIG_BF539)
- _bfin_swrst = bfin_read_SWRST();
-#else
- /* Clear boot mode field */
- _bfin_swrst = mmr & ~0xf;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
- bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
-#endif
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
- bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
-#endif
-
-#ifdef CONFIG_SMP
- if (_bfin_swrst & SWRST_DBL_FAULT_A) {
-#else
- if (_bfin_swrst & RESET_DOUBLE) {
-#endif
- printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* We assume the crashing kernel, and the current symbol table match */
- printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
- initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE,
- initial_pda.retx_doublefault);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
- initial_pda.dcplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
- initial_pda.icplb_doublefault_addr);
-#endif
- printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
- initial_pda.retx);
- } else if (_bfin_swrst & RESET_WDOG)
- printk(KERN_INFO "Recovering from Watchdog event\n");
- else if (_bfin_swrst & RESET_SOFTWARE)
- printk(KERN_NOTICE "Reset caused by Software reset\n");
-#endif
- printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
- if (bfin_compiled_revid() == 0xffff)
- printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
- else if (bfin_compiled_revid() == -1)
- printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
- else
- printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
-
- if (likely(CPUID == bfin_cpuid())) {
- if (bfin_revid() != bfin_compiled_revid()) {
- if (bfin_compiled_revid() == -1)
- printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
- bfin_revid());
- else if (bfin_compiled_revid() != 0xffff) {
- printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
- bfin_compiled_revid(), bfin_revid());
- if (bfin_compiled_revid() > bfin_revid())
- panic("Error: you are missing anomaly workarounds for this rev");
- }
- }
- if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
- printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
- CPU, bfin_revid());
- }
-
- printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
-
-#ifdef CONFIG_BF60x
- printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n",
- cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000);
-#else
- printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
- cclk / 1000000, sclk / 1000000);
-#endif
-
- setup_bootmem_allocator();
-
- paging_init();
-
- /* Copy atomic sequences to their fixed location, and sanity check that
- these locations are the ones that we advertise to userspace. */
- memcpy((void *)FIXED_CODE_START, &fixed_code_start,
- FIXED_CODE_END - FIXED_CODE_START);
- BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
- != SIGRETURN_STUB - FIXED_CODE_START);
- BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
- != ATOMIC_XCHG32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
- != ATOMIC_CAS32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
- != ATOMIC_ADD32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
- != ATOMIC_SUB32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
- != ATOMIC_IOR32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
- != ATOMIC_AND32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
- != ATOMIC_XOR32 - FIXED_CODE_START);
- BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
- != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
-
-#ifdef CONFIG_SMP
- platform_init_cpus();
-#endif
- init_exception_vectors();
- bfin_cache_init(); /* Initialize caches for the boot CPU */
-#ifdef CONFIG_SCB_PRIORITY
- init_scb();
-#endif
-}
-
-static int __init topology_init(void)
-{
- unsigned int cpu;
-
- for_each_possible_cpu(cpu) {
- register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
- }
-
- return 0;
-}
-
-subsys_initcall(topology_init);
-
-/* Get the input clock frequency */
-static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
-#ifndef CONFIG_BF60x
-static u_long get_clkin_hz(void)
-{
- return cached_clkin_hz;
-}
-#endif
-static int __init early_init_clkin_hz(char *buf)
-{
- cached_clkin_hz = simple_strtoul(buf, NULL, 0);
-#ifdef BFIN_KERNEL_CLOCK
- if (cached_clkin_hz != CONFIG_CLKIN_HZ)
- panic("cannot change clkin_hz when reprogramming clocks");
-#endif
- return 1;
-}
-early_param("clkin_hz=", early_init_clkin_hz);
-
-#ifndef CONFIG_BF60x
-/* Get the voltage input multiplier */
-static u_long get_vco(void)
-{
- static u_long cached_vco;
- u_long msel, pll_ctl;
-
- /* The assumption here is that VCO never changes at runtime.
- * If, someday, we support that, then we'll have to change this.
- */
- if (cached_vco)
- return cached_vco;
-
- pll_ctl = bfin_read_PLL_CTL();
- msel = (pll_ctl >> 9) & 0x3F;
- if (0 == msel)
- msel = 64;
-
- cached_vco = get_clkin_hz();
- cached_vco >>= (1 & pll_ctl); /* DF bit */
- cached_vco *= msel;
- return cached_vco;
-}
-#endif
-
-/* Get the Core clock */
-u_long get_cclk(void)
-{
-#ifdef CONFIG_BF60x
- return bfin_get_clk("CCLK");
-#else
- static u_long cached_cclk_pll_div, cached_cclk;
- u_long csel, ssel;
-
- if (bfin_read_PLL_STAT() & 0x1)
- return get_clkin_hz();
-
- ssel = bfin_read_PLL_DIV();
- if (ssel == cached_cclk_pll_div)
- return cached_cclk;
- else
- cached_cclk_pll_div = ssel;
-
- csel = ((ssel >> 4) & 0x03);
- ssel &= 0xf;
- if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
- cached_cclk = get_vco() / ssel;
- else
- cached_cclk = get_vco() >> csel;
- return cached_cclk;
-#endif
-}
-EXPORT_SYMBOL(get_cclk);
-
-#ifdef CONFIG_BF60x
-/* Get the bf60x clock of SCLK0 domain */
-u_long get_sclk0(void)
-{
- return bfin_get_clk("SCLK0");
-}
-EXPORT_SYMBOL(get_sclk0);
-
-/* Get the bf60x clock of SCLK1 domain */
-u_long get_sclk1(void)
-{
- return bfin_get_clk("SCLK1");
-}
-EXPORT_SYMBOL(get_sclk1);
-
-/* Get the bf60x DRAM clock */
-u_long get_dclk(void)
-{
- return bfin_get_clk("DCLK");
-}
-EXPORT_SYMBOL(get_dclk);
-#endif
-
-/* Get the default system clock */
-u_long get_sclk(void)
-{
-#ifdef CONFIG_BF60x
- return get_sclk0();
-#else
- static u_long cached_sclk;
- u_long ssel;
-
- /* The assumption here is that SCLK never changes at runtime.
- * If, someday, we support that, then we'll have to change this.
- */
- if (cached_sclk)
- return cached_sclk;
-
- if (bfin_read_PLL_STAT() & 0x1)
- return get_clkin_hz();
-
- ssel = bfin_read_PLL_DIV() & 0xf;
- if (0 == ssel) {
- printk(KERN_WARNING "Invalid System Clock\n");
- ssel = 1;
- }
-
- cached_sclk = get_vco() / ssel;
- return cached_sclk;
-#endif
-}
-EXPORT_SYMBOL(get_sclk);
-
-unsigned long sclk_to_usecs(unsigned long sclk)
-{
- u64 tmp = USEC_PER_SEC * (u64)sclk;
- do_div(tmp, get_sclk());
- return tmp;
-}
-EXPORT_SYMBOL(sclk_to_usecs);
-
-unsigned long usecs_to_sclk(unsigned long usecs)
-{
- u64 tmp = get_sclk() * (u64)usecs;
- do_div(tmp, USEC_PER_SEC);
- return tmp;
-}
-EXPORT_SYMBOL(usecs_to_sclk);
-
-/*
- * Get CPU information for use by the procfs.
- */
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
- char *cpu, *mmu, *fpu, *vendor, *cache;
- uint32_t revid;
- int cpu_num = *(unsigned int *)v;
- u_long sclk, cclk;
- u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
- struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
-
- cpu = CPU;
- mmu = "none";
- fpu = "none";
- revid = bfin_revid();
-
- sclk = get_sclk();
- cclk = get_cclk();
-
- switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
- case 0xca:
- vendor = "Analog Devices";
- break;
- default:
- vendor = "unknown";
- break;
- }
-
- seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
-
- if (CPUID == bfin_cpuid())
- seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
- else
- seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
- CPUID, bfin_cpuid());
-
- seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
- "stepping\t: %d ",
- cpu, cclk/1000000, sclk/1000000,
-#ifdef CONFIG_MPU
- "mpu on",
-#else
- "mpu off",
-#endif
- revid);
-
- if (bfin_revid() != bfin_compiled_revid()) {
- if (bfin_compiled_revid() == -1)
- seq_printf(m, "(Compiled for Rev none)");
- else if (bfin_compiled_revid() == 0xffff)
- seq_printf(m, "(Compiled for Rev any)");
- else
- seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
- }
-
- seq_printf(m, "\ncpu MHz\t\t: %lu.%06lu/%lu.%06lu\n",
- cclk/1000000, cclk%1000000,
- sclk/1000000, sclk%1000000);
- seq_printf(m, "bogomips\t: %lu.%02lu\n"
- "Calibration\t: %lu loops\n",
- (loops_per_jiffy * HZ) / 500000,
- ((loops_per_jiffy * HZ) / 5000) % 100,
- (loops_per_jiffy * HZ));
-
- /* Check Cache configutation */
- switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
- case ACACHE_BSRAM:
- cache = "dbank-A/B\t: cache/sram";
- dcache_size = 16;
- dsup_banks = 1;
- break;
- case ACACHE_BCACHE:
- cache = "dbank-A/B\t: cache/cache";
- dcache_size = 32;
- dsup_banks = 2;
- break;
- case ASRAM_BSRAM:
- cache = "dbank-A/B\t: sram/sram";
- dcache_size = 0;
- dsup_banks = 0;
- break;
- default:
- cache = "unknown";
- dcache_size = 0;
- dsup_banks = 0;
- break;
- }
-
- /* Is it turned on? */
- if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
- dcache_size = 0;
-
- if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
- icache_size = 0;
-
- seq_printf(m, "cache size\t: %d KB(L1 icache) "
- "%d KB(L1 dcache) %d KB(L2 cache)\n",
- icache_size, dcache_size, 0);
- seq_printf(m, "%s\n", cache);
- seq_printf(m, "external memory\t: "
-#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
- "cacheable"
-#else
- "uncacheable"
-#endif
- " in instruction cache\n");
- seq_printf(m, "external memory\t: "
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
- "cacheable (write-back)"
-#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
- "cacheable (write-through)"
-#else
- "uncacheable"
-#endif
- " in data cache\n");
-
- if (icache_size)
- seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
- BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
- else
- seq_printf(m, "icache setup\t: off\n");
-
- seq_printf(m,
- "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
- dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
- BFIN_DLINES);
-#ifdef __ARCH_SYNC_CORE_DCACHE
- seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
-#endif
-#ifdef __ARCH_SYNC_CORE_ICACHE
- seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
-#endif
-
- seq_printf(m, "\n");
-
- if (cpu_num != num_possible_cpus() - 1)
- return 0;
-
- if (L2_LENGTH) {
- seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
- seq_printf(m, "L2 SRAM\t\t: "
-#if defined(CONFIG_BFIN_L2_ICACHEABLE)
- "cacheable"
-#else
- "uncacheable"
-#endif
- " in instruction cache\n");
- seq_printf(m, "L2 SRAM\t\t: "
-#if defined(CONFIG_BFIN_L2_WRITEBACK)
- "cacheable (write-back)"
-#elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
- "cacheable (write-through)"
-#else
- "uncacheable"
-#endif
- " in data cache\n");
- }
- seq_printf(m, "board name\t: %s\n", bfin_board_name);
- seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
- physical_mem_end >> 10, 0ul, physical_mem_end);
- seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
- ((int)memory_end - (int)_rambase) >> 10,
- _rambase, memory_end);
-
- return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- if (*pos == 0)
- *pos = cpumask_first(cpu_online_mask);
- if (*pos >= num_online_cpus())
- return NULL;
-
- return pos;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- *pos = cpumask_next(*pos, cpu_online_mask);
-
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-
-void __init cmdline_init(const char *r0)
-{
- early_shadow_stamp();
- if (r0)
- strlcpy(command_line, r0, COMMAND_LINE_SIZE);
-}
diff --git a/arch/blackfin/kernel/shadow_console.c b/arch/blackfin/kernel/shadow_console.c
deleted file mode 100644
index aeb8343..0000000
--- a/arch/blackfin/kernel/shadow_console.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * manage a small early shadow of the log buffer which we can pass between the
- * bootloader so early crash messages are communicated properly and easily
- *
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/string.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/early_printk.h>
-
-#define SHADOW_CONSOLE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500)
-#define SHADOW_CONSOLE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000)
-#define SHADOW_CONSOLE_MAGIC_LOC (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0)
-#define SHADOW_CONSOLE_MAGIC (0xDEADBEEF)
-
-static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START;
-
-__init void early_shadow_write(struct console *con, const char *s,
- unsigned int n)
-{
- unsigned int i;
- /*
- * save 2 bytes for the double null at the end
- * once we fail on a long line, make sure we don't write a short line afterwards
- */
- if ((shadow_console_buffer + n) <= (char *)(SHADOW_CONSOLE_END - 2)) {
- /* can't use memcpy - it may not be relocated yet */
- for (i = 0; i <= n; i++)
- shadow_console_buffer[i] = s[i];
- shadow_console_buffer += n;
- shadow_console_buffer[0] = 0;
- shadow_console_buffer[1] = 0;
- } else
- shadow_console_buffer = (char *)SHADOW_CONSOLE_END;
-}
-
-static __initdata struct console early_shadow_console = {
- .name = "early_shadow",
- .write = early_shadow_write,
- .flags = CON_BOOT | CON_PRINTBUFFER,
- .index = -1,
- .device = 0,
-};
-
-__init int shadow_console_enabled(void)
-{
- return early_shadow_console.flags & CON_ENABLED;
-}
-
-__init void mark_shadow_error(void)
-{
- int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC;
- loc[0] = SHADOW_CONSOLE_MAGIC;
- loc[1] = SHADOW_CONSOLE_START;
-}
-
-__init void enable_shadow_console(void)
-{
- if (!shadow_console_enabled()) {
- register_console(&early_shadow_console);
- /* for now, assume things are going to fail */
- mark_shadow_error();
- }
-}
-
-static __init int disable_shadow_console(void)
-{
- /*
- * by the time pure_initcall runs, the standard console is enabled,
- * and the early_console is off, so unset the magic numbers
- * unregistering the console is taken care of in common code (See
- * ./kernel/printk:disable_boot_consoles() )
- */
- int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC;
-
- loc[0] = 0;
-
- return 0;
-}
-pure_initcall(disable_shadow_console);
-
-/*
- * since we can't use printk, dump numbers (as hex), n = # bits
- */
-__init void early_shadow_reg(unsigned long reg, unsigned int n)
-{
- /*
- * can't use any "normal" kernel features, since thay
- * may not be relocated to their execute address yet
- */
- int i;
- char ascii[11] = " 0x";
-
- n = n / 4;
- reg = reg << ((8 - n) * 4);
- n += 3;
-
- for (i = 3; i <= n ; i++) {
- ascii[i] = hex_asc_lo(reg >> 28);
- reg <<= 4;
- }
- early_shadow_write(NULL, ascii, n);
-
-}
diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c
deleted file mode 100644
index 5f51727..0000000
--- a/arch/blackfin/kernel/signal.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/signal.h>
-#include <linux/syscalls.h>
-#include <linux/ptrace.h>
-#include <linux/tty.h>
-#include <linux/personality.h>
-#include <linux/binfmts.h>
-#include <linux/uaccess.h>
-#include <linux/tracehook.h>
-#include <linux/sched/task_stack.h>
-
-#include <asm/cacheflush.h>
-#include <asm/ucontext.h>
-#include <asm/fixed_code.h>
-#include <asm/syscall.h>
-
-/* Location of the trace bit in SYSCFG. */
-#define TRACE_BITS 0x0001
-
-struct fdpic_func_descriptor {
- unsigned long text;
- unsigned long GOT;
-};
-
-struct rt_sigframe {
- int sig;
- struct siginfo *pinfo;
- void *puc;
- /* This is no longer needed by the kernel, but unfortunately userspace
- * code expects it to be there. */
- char retcode[8];
- struct siginfo info;
- struct ucontext uc;
-};
-
-static inline int
-rt_restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *pr0)
-{
- unsigned long usp = 0;
- int err = 0;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
-#define RESTORE(x) err |= __get_user(regs->x, &sc->sc_##x)
-
- /* restore passed registers */
- RESTORE(r0); RESTORE(r1); RESTORE(r2); RESTORE(r3);
- RESTORE(r4); RESTORE(r5); RESTORE(r6); RESTORE(r7);
- RESTORE(p0); RESTORE(p1); RESTORE(p2); RESTORE(p3);
- RESTORE(p4); RESTORE(p5);
- err |= __get_user(usp, &sc->sc_usp);
- wrusp(usp);
- RESTORE(a0w); RESTORE(a1w);
- RESTORE(a0x); RESTORE(a1x);
- RESTORE(astat);
- RESTORE(rets);
- RESTORE(pc);
- RESTORE(retx);
- RESTORE(fp);
- RESTORE(i0); RESTORE(i1); RESTORE(i2); RESTORE(i3);
- RESTORE(m0); RESTORE(m1); RESTORE(m2); RESTORE(m3);
- RESTORE(l0); RESTORE(l1); RESTORE(l2); RESTORE(l3);
- RESTORE(b0); RESTORE(b1); RESTORE(b2); RESTORE(b3);
- RESTORE(lc0); RESTORE(lc1);
- RESTORE(lt0); RESTORE(lt1);
- RESTORE(lb0); RESTORE(lb1);
- RESTORE(seqstat);
-
- regs->orig_p0 = -1; /* disable syscall checks */
-
- *pr0 = regs->r0;
- return err;
-}
-
-asmlinkage int sys_rt_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- unsigned long usp = rdusp();
- struct rt_sigframe *frame = (struct rt_sigframe *)(usp);
- sigset_t set;
- int r0;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (rt_restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return r0;
-
- badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-static inline int rt_setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs)
-{
- int err = 0;
-
-#define SETUP(x) err |= __put_user(regs->x, &sc->sc_##x)
-
- SETUP(r0); SETUP(r1); SETUP(r2); SETUP(r3);
- SETUP(r4); SETUP(r5); SETUP(r6); SETUP(r7);
- SETUP(p0); SETUP(p1); SETUP(p2); SETUP(p3);
- SETUP(p4); SETUP(p5);
- err |= __put_user(rdusp(), &sc->sc_usp);
- SETUP(a0w); SETUP(a1w);
- SETUP(a0x); SETUP(a1x);
- SETUP(astat);
- SETUP(rets);
- SETUP(pc);
- SETUP(retx);
- SETUP(fp);
- SETUP(i0); SETUP(i1); SETUP(i2); SETUP(i3);
- SETUP(m0); SETUP(m1); SETUP(m2); SETUP(m3);
- SETUP(l0); SETUP(l1); SETUP(l2); SETUP(l3);
- SETUP(b0); SETUP(b1); SETUP(b2); SETUP(b3);
- SETUP(lc0); SETUP(lc1);
- SETUP(lt0); SETUP(lt1);
- SETUP(lb0); SETUP(lb1);
- SETUP(seqstat);
-
- return err;
-}
-
-static inline void *get_sigframe(struct ksignal *ksig,
- size_t frame_size)
-{
- unsigned long usp = sigsp(rdusp(), ksig);
-
- return (void *)((usp - frame_size) & -8UL);
-}
-
-static int
-setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
-{
- struct rt_sigframe *frame;
- int err = 0;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- err |= __put_user(ksig->sig, &frame->sig);
-
- err |= __put_user(&frame->info, &frame->pinfo);
- err |= __put_user(&frame->uc, &frame->puc);
- err |= copy_siginfo_to_user(&frame->info, &ksig->info);
-
- /* Create the ucontext. */
- err |= __put_user(0, &frame->uc.uc_flags);
- err |= __put_user(0, &frame->uc.uc_link);
- err |= __save_altstack(&frame->uc.uc_stack, rdusp());
- err |= rt_setup_sigcontext(&frame->uc.uc_mcontext, regs);
- err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
-
- if (err)
- return -EFAULT;
-
- /* Set up registers for signal handler */
- if (current->personality & FDPIC_FUNCPTRS) {
- struct fdpic_func_descriptor __user *funcptr =
- (struct fdpic_func_descriptor *) ksig->ka.sa.sa_handler;
- u32 pc, p3;
- err |= __get_user(pc, &funcptr->text);
- err |= __get_user(p3, &funcptr->GOT);
- if (err)
- return -EFAULT;
- regs->pc = pc;
- regs->p3 = p3;
- } else
- regs->pc = (unsigned long)ksig->ka.sa.sa_handler;
- wrusp((unsigned long)frame);
- regs->rets = SIGRETURN_STUB;
-
- regs->r0 = frame->sig;
- regs->r1 = (unsigned long)(&frame->info);
- regs->r2 = (unsigned long)(&frame->uc);
-
- return 0;
-}
-
-static inline void
-handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
-{
- switch (regs->r0) {
- case -ERESTARTNOHAND:
- if (!has_handler)
- goto do_restart;
- regs->r0 = -EINTR;
- break;
-
- case -ERESTARTSYS:
- if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
- regs->r0 = -EINTR;
- break;
- }
- /* fallthrough */
- case -ERESTARTNOINTR:
- do_restart:
- regs->p0 = regs->orig_p0;
- regs->r0 = regs->orig_r0;
- regs->pc -= 2;
- break;
-
- case -ERESTART_RESTARTBLOCK:
- regs->p0 = __NR_restart_syscall;
- regs->pc -= 2;
- break;
- }
-}
-
-/*
- * OK, we're invoking a handler
- */
-static void
-handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-{
- int ret;
-
- /* are we from a system call? to see pt_regs->orig_p0 */
- if (regs->orig_p0 >= 0)
- /* If so, check system call restarting.. */
- handle_restart(regs, &ksig->ka, 1);
-
- /* set up the stack frame */
- ret = setup_rt_frame(ksig, sigmask_to_save(), regs);
-
- signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
-}
-
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- *
- * Note that we go through the signals twice: once to check the signals
- * that the kernel can handle, and then we build all the user-level signal
- * handling stack-frames in one go after that.
- */
-asmlinkage void do_signal(struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- current->thread.esp0 = (unsigned long)regs;
-
- if (get_signal(&ksig)) {
- /* Whee! Actually deliver the signal. */
- handle_signal(&ksig, regs);
- return;
- }
-
- /* Did we come from a system call? */
- if (regs->orig_p0 >= 0)
- /* Restart the system call - no handlers present */
- handle_restart(regs, NULL, 0);
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-}
-
-/*
- * notification of userspace execution resumption
- */
-asmlinkage void do_notify_resume(struct pt_regs *regs)
-{
- if (test_thread_flag(TIF_SIGPENDING))
- do_signal(regs);
-
- if (test_thread_flag(TIF_NOTIFY_RESUME)) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
-}
-
diff --git a/arch/blackfin/kernel/stacktrace.c b/arch/blackfin/kernel/stacktrace.c
deleted file mode 100644
index 17198f3..0000000
--- a/arch/blackfin/kernel/stacktrace.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Blackfin stacktrace code (mostly copied from avr32)
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/stacktrace.h>
-#include <linux/thread_info.h>
-#include <linux/module.h>
-
-register unsigned long current_frame_pointer asm("FP");
-
-struct stackframe {
- unsigned long fp;
- unsigned long rets;
-};
-
-/*
- * Save stack-backtrace addresses into a stack_trace buffer.
- */
-void save_stack_trace(struct stack_trace *trace)
-{
- unsigned long low, high;
- unsigned long fp;
- struct stackframe *frame;
- int skip = trace->skip;
-
- low = (unsigned long)task_stack_page(current);
- high = low + THREAD_SIZE;
- fp = current_frame_pointer;
-
- while (fp >= low && fp <= (high - sizeof(*frame))) {
- frame = (struct stackframe *)fp;
-
- if (skip) {
- skip--;
- } else {
- trace->entries[trace->nr_entries++] = frame->rets;
- if (trace->nr_entries >= trace->max_entries)
- break;
- }
-
- /*
- * The next frame must be at a higher address than the
- * current frame.
- */
- low = fp + sizeof(*frame);
- fp = frame->fp;
- }
-}
-EXPORT_SYMBOL_GPL(save_stack_trace);
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
deleted file mode 100644
index d998383..0000000
--- a/arch/blackfin/kernel/sys_bfin.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * contains various random system calls that have a non-standard
- * calling sequence on the Linux/Blackfin platform.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/spinlock.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/ipc.h>
-#include <linux/unistd.h>
-
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <asm/cachectl.h>
-#include <asm/ptrace.h>
-
-asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags)
-{
- return sram_alloc_with_lsl(size, flags);
-}
-
-asmlinkage int sys_sram_free(const void *addr)
-{
- return sram_free_with_lsl(addr);
-}
-
-asmlinkage void *sys_dma_memcpy(void *dest, const void *src, size_t len)
-{
- return safe_dma_memcpy(dest, src, len);
-}
-
-#if defined(CONFIG_FB) || defined(CONFIG_FB_MODULE)
-#include <linux/fb.h>
-#include <linux/export.h>
-unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr,
- unsigned long len, unsigned long pgoff, unsigned long flags)
-{
- struct fb_info *info = filp->private_data;
- return (unsigned long)info->screen_base;
-}
-EXPORT_SYMBOL(get_fb_unmapped_area);
-#endif
-
-/* Needed for legacy userspace atomic emulation */
-static DEFINE_SPINLOCK(bfin_spinlock_lock);
-
-#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1
-__attribute__((l1_text))
-#endif
-asmlinkage int sys_bfin_spinlock(int *p)
-{
- int ret, tmp = 0;
-
- spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */
- ret = get_user(tmp, p);
- if (likely(ret == 0)) {
- if (unlikely(tmp))
- ret = 1;
- else
- put_user(1, p);
- }
- spin_unlock(&bfin_spinlock_lock);
-
- return ret;
-}
-
-SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len, int, op)
-{
- if (is_user_addr_valid(current, addr, len) != 0)
- return -EINVAL;
-
- if (op & DCACHE)
- blackfin_dcache_flush_range(addr, addr + len);
- if (op & ICACHE)
- blackfin_icache_flush_range(addr, addr + len);
-
- return 0;
-}
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
deleted file mode 100644
index 0135055..0000000
--- a/arch/blackfin/kernel/time-ts.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- * Based on arm clockevents implementation and old bfin time tick.
- *
- * Copyright 2008-2009 Analog Devics Inc.
- * 2008 GeoTechnologies
- * Vitja Makarov
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/module.h>
-#include <linux/profile.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/cpufreq.h>
-
-#include <asm/blackfin.h>
-#include <asm/time.h>
-#include <asm/gptimers.h>
-#include <asm/nmi.h>
-
-
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
-
-static notrace u64 bfin_read_cycles(struct clocksource *cs)
-{
-#ifdef CONFIG_CPU_FREQ
- return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
-#else
- return get_cycles();
-#endif
-}
-
-static struct clocksource bfin_cs_cycles = {
- .name = "bfin_cs_cycles",
- .rating = 400,
- .read = bfin_read_cycles,
- .mask = CLOCKSOURCE_MASK(64),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static inline unsigned long long bfin_cs_cycles_sched_clock(void)
-{
- return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
- bfin_cs_cycles.mult, bfin_cs_cycles.shift);
-}
-
-static int __init bfin_cs_cycles_init(void)
-{
- if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
- panic("failed to register clocksource");
-
- return 0;
-}
-#else
-# define bfin_cs_cycles_init()
-#endif
-
-#ifdef CONFIG_GPTMR0_CLOCKSOURCE
-
-void __init setup_gptimer0(void)
-{
- disable_gptimers(TIMER0bit);
-
-#ifdef CONFIG_BF60x
- bfin_write16(TIMER_DATA_IMSK, 0);
- set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
- | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
-#else
- set_gptimer_config(TIMER0_id, \
- TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
-#endif
- set_gptimer_period(TIMER0_id, -1);
- set_gptimer_pwidth(TIMER0_id, -2);
- SSYNC();
- enable_gptimers(TIMER0bit);
-}
-
-static u64 bfin_read_gptimer0(struct clocksource *cs)
-{
- return bfin_read_TIMER0_COUNTER();
-}
-
-static struct clocksource bfin_cs_gptimer0 = {
- .name = "bfin_cs_gptimer0",
- .rating = 350,
- .read = bfin_read_gptimer0,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
-{
- return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
- bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
-}
-
-static int __init bfin_cs_gptimer0_init(void)
-{
- setup_gptimer0();
-
- if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
- panic("failed to register clocksource");
-
- return 0;
-}
-#else
-# define bfin_cs_gptimer0_init()
-#endif
-
-#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
-/* prefer to use cycles since it has higher rating */
-notrace unsigned long long sched_clock(void)
-{
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
- return bfin_cs_cycles_sched_clock();
-#else
- return bfin_cs_gptimer0_sched_clock();
-#endif
-}
-#endif
-
-#if defined(CONFIG_TICKSOURCE_GPTMR0)
-static int bfin_gptmr0_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
-
- /* it starts counting three SCLK cycles after the TIMENx bit is set */
- set_gptimer_pwidth(TIMER0_id, cycles - 3);
- enable_gptimers(TIMER0bit);
- return 0;
-}
-
-static int bfin_gptmr0_set_periodic(struct clock_event_device *evt)
-{
-#ifndef CONFIG_BF60x
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_IRQ_ENA |
- TIMER_PERIOD_CNT | TIMER_MODE_PWM);
-#else
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_MODE_PWM_CONT |
- TIMER_PULSE_HI | TIMER_IRQ_PER);
-#endif
-
- set_gptimer_period(TIMER0_id, get_sclk() / HZ);
- set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
- enable_gptimers(TIMER0bit);
- return 0;
-}
-
-static int bfin_gptmr0_set_oneshot(struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
-#ifndef CONFIG_BF60x
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
-#else
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_MODE_PWM | TIMER_PULSE_HI |
- TIMER_IRQ_WID_DLY);
-#endif
-
- set_gptimer_period(TIMER0_id, 0);
- return 0;
-}
-
-static int bfin_gptmr0_shutdown(struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
- return 0;
-}
-
-static void bfin_gptmr0_ack(void)
-{
- clear_gptimer_intr(TIMER0_id);
-}
-
-static void __init bfin_gptmr0_init(void)
-{
- disable_gptimers(TIMER0bit);
-}
-
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
- smp_mb();
- /*
- * We want to ACK before we handle so that we can handle smaller timer
- * intervals. This way if the timer expires again while we're handling
- * things, we're more likely to see that 2nd int rather than swallowing
- * it by ACKing the int@the end of this handler.
- */
- bfin_gptmr0_ack();
- evt->event_handler(evt);
- return IRQ_HANDLED;
-}
-
-static struct irqaction gptmr0_irq = {
- .name = "Blackfin GPTimer0",
- .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
- .handler = bfin_gptmr0_interrupt,
-};
-
-static struct clock_event_device clockevent_gptmr0 = {
- .name = "bfin_gptimer0",
- .rating = 300,
- .irq = IRQ_TIMER0,
- .shift = 32,
- .features = CLOCK_EVT_FEAT_PERIODIC |
- CLOCK_EVT_FEAT_ONESHOT,
- .set_next_event = bfin_gptmr0_set_next_event,
- .set_state_shutdown = bfin_gptmr0_shutdown,
- .set_state_periodic = bfin_gptmr0_set_periodic,
- .set_state_oneshot = bfin_gptmr0_set_oneshot,
-};
-
-static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
-{
- unsigned long clock_tick;
-
- clock_tick = get_sclk();
- evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
- evt->max_delta_ns = clockevent_delta2ns(-1, evt);
- evt->max_delta_ticks = (unsigned long)-1;
- evt->min_delta_ns = clockevent_delta2ns(100, evt);
- evt->min_delta_ticks = 100;
-
- evt->cpumask = cpumask_of(0);
-
- clockevents_register_device(evt);
-}
-#endif /* CONFIG_TICKSOURCE_GPTMR0 */
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
-/* per-cpu local core timer */
-DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
-
-static int bfin_coretmr_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TCOUNT(cycles);
- CSYNC();
- bfin_write_TCNTL(TMPWR | TMREN);
- return 0;
-}
-
-static int bfin_coretmr_set_periodic(struct clock_event_device *evt)
-{
- unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
-
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(tcount);
- bfin_write_TCOUNT(tcount);
- CSYNC();
- bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
- return 0;
-}
-
-static int bfin_coretmr_set_oneshot(struct clock_event_device *evt)
-{
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(0);
- bfin_write_TCOUNT(0);
- return 0;
-}
-
-static int bfin_coretmr_shutdown(struct clock_event_device *evt)
-{
- bfin_write_TCNTL(0);
- CSYNC();
- return 0;
-}
-
-void bfin_coretmr_init(void)
-{
- /* power up the timer, but don't enable it just yet */
- bfin_write_TCNTL(TMPWR);
- CSYNC();
-
- /* the TSCALE prescaler counter. */
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(0);
- bfin_write_TCOUNT(0);
-
- CSYNC();
-}
-
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-
-irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
-{
- int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
-
- smp_mb();
- evt->event_handler(evt);
-
- touch_nmi_watchdog();
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction coretmr_irq = {
- .name = "Blackfin CoreTimer",
- .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
- .handler = bfin_coretmr_interrupt,
-};
-
-void bfin_coretmr_clockevent_init(void)
-{
- unsigned long clock_tick;
- unsigned int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
-
-#ifdef CONFIG_SMP
- evt->broadcast = smp_timer_broadcast;
-#endif
-
- evt->name = "bfin_core_timer";
- evt->rating = 350;
- evt->irq = -1;
- evt->shift = 32;
- evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- evt->set_next_event = bfin_coretmr_set_next_event;
- evt->set_state_shutdown = bfin_coretmr_shutdown;
- evt->set_state_periodic = bfin_coretmr_set_periodic;
- evt->set_state_oneshot = bfin_coretmr_set_oneshot;
-
- clock_tick = get_cclk() / TIME_SCALE;
- evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
- evt->max_delta_ns = clockevent_delta2ns(-1, evt);
- evt->max_delta_ticks = (unsigned long)-1;
- evt->min_delta_ns = clockevent_delta2ns(100, evt);
- evt->min_delta_ticks = 100;
-
- evt->cpumask = cpumask_of(cpu);
-
- clockevents_register_device(evt);
-}
-#endif /* CONFIG_TICKSOURCE_CORETMR */
-
-
-void read_persistent_clock(struct timespec *ts)
-{
- time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
- ts->tv_sec = secs_since_1970;
- ts->tv_nsec = 0;
-}
-
-void __init time_init(void)
-{
-
-#ifdef CONFIG_RTC_DRV_BFIN
- /* [#2663] hack to filter junk RTC values that would cause
- * userspace to have to deal with time values greater than
- * 2^31 seconds (which uClibc cannot cope with yet)
- */
- if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
- printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
- bfin_write_RTC_STAT(0);
- }
-#endif
-
- bfin_cs_cycles_init();
- bfin_cs_gptimer0_init();
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
- bfin_coretmr_init();
- setup_irq(IRQ_CORETMR, &coretmr_irq);
- bfin_coretmr_clockevent_init();
-#endif
-
-#if defined(CONFIG_TICKSOURCE_GPTMR0)
- bfin_gptmr0_init();
- setup_irq(IRQ_TIMER0, &gptmr0_irq);
- gptmr0_irq.dev_id = &clockevent_gptmr0;
- bfin_gptmr0_clockevent_init(&clockevent_gptmr0);
-#endif
-
-#if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0)
-# error at least one clock event device is required
-#endif
-}
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
deleted file mode 100644
index 3126b92..0000000
--- a/arch/blackfin/kernel/time.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * arch/blackfin/kernel/time.c
- *
- * This file contains the Blackfin-specific time handling details.
- * Most of the stuff is located in the machine specific files.
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/profile.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/sched.h>
-
-#include <asm/blackfin.h>
-#include <asm/time.h>
-#include <asm/gptimers.h>
-
-/* This is an NTP setting */
-#define TICK_SIZE (tick_nsec / 1000)
-
-static struct irqaction bfin_timer_irq = {
- .name = "Blackfin Timer Tick",
-};
-
-#if defined(CONFIG_IPIPE)
-void __init setup_system_timer0(void)
-{
- /* Power down the core timer, just to play safe. */
- bfin_write_TCNTL(0);
-
- disable_gptimers(TIMER0bit);
- set_gptimer_status(0, TIMER_STATUS_TRUN0);
- while (get_gptimer_status(0) & TIMER_STATUS_TRUN0)
- udelay(10);
-
- set_gptimer_config(0, 0x59); /* IRQ enable, periodic, PWM_OUT, SCLKed, OUT PAD disabled */
- set_gptimer_period(TIMER0_id, get_sclk() / HZ);
- set_gptimer_pwidth(TIMER0_id, 1);
- SSYNC();
- enable_gptimers(TIMER0bit);
-}
-#else
-void __init setup_core_timer(void)
-{
- u32 tcount;
-
- /* power up the timer, but don't enable it just yet */
- bfin_write_TCNTL(TMPWR);
- CSYNC();
-
- /* the TSCALE prescaler counter */
- bfin_write_TSCALE(TIME_SCALE - 1);
-
- tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
- bfin_write_TPERIOD(tcount);
- bfin_write_TCOUNT(tcount);
-
- /* now enable the timer */
- CSYNC();
-
- bfin_write_TCNTL(TAUTORLD | TMREN | TMPWR);
-}
-#endif
-
-static void __init
-time_sched_init(irqreturn_t(*timer_routine) (int, void *))
-{
-#if defined(CONFIG_IPIPE)
- setup_system_timer0();
- bfin_timer_irq.handler = timer_routine;
- setup_irq(IRQ_TIMER0, &bfin_timer_irq);
-#else
- setup_core_timer();
- bfin_timer_irq.handler = timer_routine;
- setup_irq(IRQ_CORETMR, &bfin_timer_irq);
-#endif
-}
-
-#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
-/*
- * Should return useconds since last timer tick
- */
-static u32 blackfin_gettimeoffset(void)
-{
- unsigned long offset;
- unsigned long clocks_per_jiffy;
-
-#if defined(CONFIG_IPIPE)
- clocks_per_jiffy = bfin_read_TIMER0_PERIOD();
- offset = bfin_read_TIMER0_COUNTER() / \
- (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
-
- if ((get_gptimer_status(0) & TIMER_STATUS_TIMIL0) && offset < (100000 / HZ / 2))
- offset += (USEC_PER_SEC / HZ);
-#else
- clocks_per_jiffy = bfin_read_TPERIOD();
- offset = (clocks_per_jiffy - bfin_read_TCOUNT()) / \
- (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
-
- /* Check if we just wrapped the counters and maybe missed a tick */
- if ((bfin_read_ILAT() & (1 << IRQ_CORETMR))
- && (offset < (100000 / HZ / 2)))
- offset += (USEC_PER_SEC / HZ);
-#endif
- return offset;
-}
-#endif
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-irqreturn_t timer_interrupt(int irq, void *dummy)
-{
- xtime_update(1);
-
-#ifdef CONFIG_IPIPE
- update_root_process_times(get_irq_regs());
-#else
- update_process_times(user_mode(get_irq_regs()));
-#endif
- profile_tick(CPU_PROFILING);
-
- return IRQ_HANDLED;
-}
-
-void read_persistent_clock(struct timespec *ts)
-{
- time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
- ts->tv_sec = secs_since_1970;
- ts->tv_nsec = 0;
-}
-
-void __init time_init(void)
-{
-#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
- arch_gettimeoffset = blackfin_gettimeoffset;
-#endif
-
-#ifdef CONFIG_RTC_DRV_BFIN
- /* [#2663] hack to filter junk RTC values that would cause
- * userspace to have to deal with time values greater than
- * 2^31 seconds (which uClibc cannot cope with yet)
- */
- if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
- printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
- bfin_write_RTC_STAT(0);
- }
-#endif
-
- time_sched_init(timer_interrupt);
-}
diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
deleted file mode 100644
index 151f221..0000000
--- a/arch/blackfin/kernel/trace.c
+++ /dev/null
@@ -1,988 +0,0 @@
-/* provide some functions which dump the trace buffer, in a nice way for people
- * to read it, and understand what is going on
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <linux/hardirq.h>
-#include <linux/thread_info.h>
-#include <linux/mm.h>
-#include <linux/oom.h>
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/err.h>
-#include <linux/fs.h>
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/trace.h>
-#include <asm/fixed_code.h>
-#include <asm/traps.h>
-#include <asm/irq_handler.h>
-#include <asm/pda.h>
-
-void decode_address(char *buf, unsigned long address)
-{
- struct task_struct *p;
- struct mm_struct *mm;
- unsigned long offset;
- struct rb_node *n;
-
-#ifdef CONFIG_KALLSYMS
- unsigned long symsize;
- const char *symname;
- char *modname;
- char *delim = ":";
- char namebuf[128];
-#endif
-
- buf += sprintf(buf, "<0x%08lx> ", address);
-
-#ifdef CONFIG_KALLSYMS
- /* look up the address and see if we are in kernel space */
- symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
-
- if (symname) {
- /* yeah! kernel space! */
- if (!modname)
- modname = delim = "";
- sprintf(buf, "{ %s%s%s%s + 0x%lx }",
- delim, modname, delim, symname,
- (unsigned long)offset);
- return;
- }
-#endif
-
- if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
- /* Problem in fixed code section? */
- strcat(buf, "/* Maybe fixed code section */");
- return;
-
- } else if (address < CONFIG_BOOT_LOAD) {
- /* Problem somewhere before the kernel start address */
- strcat(buf, "/* Maybe null pointer? */");
- return;
-
- } else if (address >= COREMMR_BASE) {
- strcat(buf, "/* core mmrs */");
- return;
-
- } else if (address >= SYSMMR_BASE) {
- strcat(buf, "/* system mmrs */");
- return;
-
- } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
- strcat(buf, "/* on-chip L1 ROM */");
- return;
-
- } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) {
- strcat(buf, "/* on-chip scratchpad */");
- return;
-
- } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) {
- strcat(buf, "/* unconnected memory */");
- return;
-
- } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
- strcat(buf, "/* reserved memory */");
- return;
-
- } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) {
- strcat(buf, "/* on-chip Data Bank A */");
- return;
-
- } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) {
- strcat(buf, "/* on-chip Data Bank B */");
- return;
- }
-
- /*
- * Don't walk any of the vmas if we are oopsing, it has been known
- * to cause problems - corrupt vmas (kernel crashes) cause double faults
- */
- if (oops_in_progress) {
- strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
- return;
- }
-
- /* looks like we're off in user-land, so let's walk all the
- * mappings of all our processes and see if we can't be a whee
- * bit more specific
- */
- read_lock(&tasklist_lock);
- for_each_process(p) {
- struct task_struct *t;
-
- t = find_lock_task_mm(p);
- if (!t)
- continue;
-
- mm = t->mm;
- if (!down_read_trylock(&mm->mmap_sem))
- goto __continue;
-
- for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
- struct vm_area_struct *vma;
-
- vma = rb_entry(n, struct vm_area_struct, vm_rb);
-
- if (address >= vma->vm_start && address < vma->vm_end) {
- char _tmpbuf[256];
- char *name = t->comm;
- struct file *file = vma->vm_file;
-
- if (file) {
- char *d_name = file_path(file, _tmpbuf,
- sizeof(_tmpbuf));
- if (!IS_ERR(d_name))
- name = d_name;
- }
-
- /* FLAT does not have its text aligned to the start of
- * the map while FDPIC ELF does ...
- */
-
- /* before we can check flat/fdpic, we need to
- * make sure current is valid
- */
- if ((unsigned long)current >= FIXED_CODE_START &&
- !((unsigned long)current & 0x3)) {
- if (current->mm &&
- (address > current->mm->start_code) &&
- (address < current->mm->end_code))
- offset = address - current->mm->start_code;
- else
- offset = (address - vma->vm_start) +
- (vma->vm_pgoff << PAGE_SHIFT);
-
- sprintf(buf, "[ %s + 0x%lx ]", name, offset);
- } else
- sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
- name, vma->vm_start, vma->vm_end);
-
- up_read(&mm->mmap_sem);
- task_unlock(t);
-
- if (buf[0] == '\0')
- sprintf(buf, "[ %s ] dynamic memory", name);
-
- goto done;
- }
- }
-
- up_read(&mm->mmap_sem);
-__continue:
- task_unlock(t);
- }
-
- /*
- * we were unable to find this address anywhere,
- * or some MMs were skipped because they were in use.
- */
- sprintf(buf, "/* kernel dynamic memory */");
-
-done:
- read_unlock(&tasklist_lock);
-}
-
-#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
-
-/*
- * Similar to get_user, do some address checking, then dereference
- * Return true on success, false on bad address
- */
-bool get_mem16(unsigned short *val, unsigned short *address)
-{
- unsigned long addr = (unsigned long)address;
-
- /* Check for odd addresses */
- if (addr & 0x1)
- return false;
-
- switch (bfin_mem_access_type(addr, 2)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- *val = *address;
- return true;
- case BFIN_MEM_ACCESS_DMA:
- dma_memcpy(val, address, 2);
- return true;
- case BFIN_MEM_ACCESS_ITEST:
- isram_memcpy(val, address, 2);
- return true;
- default: /* invalid access */
- return false;
- }
-}
-
-bool get_instruction(unsigned int *val, unsigned short *address)
-{
- unsigned long addr = (unsigned long)address;
- unsigned short opcode0, opcode1;
-
- /* Check for odd addresses */
- if (addr & 0x1)
- return false;
-
- /* MMR region will never have instructions */
- if (addr >= SYSMMR_BASE)
- return false;
-
- /* Scratchpad will never have instructions */
- if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH)
- return false;
-
- /* Data banks will never have instructions */
- if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START)
- return false;
-
- if (!get_mem16(&opcode0, address))
- return false;
-
- /* was this a 32-bit instruction? If so, get the next 16 bits */
- if ((opcode0 & 0xc000) == 0xc000) {
- if (!get_mem16(&opcode1, address + 1))
- return false;
- *val = (opcode0 << 16) + opcode1;
- } else
- *val = opcode0;
-
- return true;
-}
-
-#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
-/*
- * decode the instruction if we are printing out the trace, as it
- * makes things easier to follow, without running it through objdump
- * Decode the change of flow, and the common load/store instructions
- * which are the main cause for faults, and discontinuities in the trace
- * buffer.
- */
-
-#define ProgCtrl_opcode 0x0000
-#define ProgCtrl_poprnd_bits 0
-#define ProgCtrl_poprnd_mask 0xf
-#define ProgCtrl_prgfunc_bits 4
-#define ProgCtrl_prgfunc_mask 0xf
-#define ProgCtrl_code_bits 8
-#define ProgCtrl_code_mask 0xff
-
-static void decode_ProgCtrl_0(unsigned int opcode)
-{
- int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
- int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
-
- if (prgfunc == 0 && poprnd == 0)
- pr_cont("NOP");
- else if (prgfunc == 1 && poprnd == 0)
- pr_cont("RTS");
- else if (prgfunc == 1 && poprnd == 1)
- pr_cont("RTI");
- else if (prgfunc == 1 && poprnd == 2)
- pr_cont("RTX");
- else if (prgfunc == 1 && poprnd == 3)
- pr_cont("RTN");
- else if (prgfunc == 1 && poprnd == 4)
- pr_cont("RTE");
- else if (prgfunc == 2 && poprnd == 0)
- pr_cont("IDLE");
- else if (prgfunc == 2 && poprnd == 3)
- pr_cont("CSYNC");
- else if (prgfunc == 2 && poprnd == 4)
- pr_cont("SSYNC");
- else if (prgfunc == 2 && poprnd == 5)
- pr_cont("EMUEXCPT");
- else if (prgfunc == 3)
- pr_cont("CLI R%i", poprnd);
- else if (prgfunc == 4)
- pr_cont("STI R%i", poprnd);
- else if (prgfunc == 5)
- pr_cont("JUMP (P%i)", poprnd);
- else if (prgfunc == 6)
- pr_cont("CALL (P%i)", poprnd);
- else if (prgfunc == 7)
- pr_cont("CALL (PC + P%i)", poprnd);
- else if (prgfunc == 8)
- pr_cont("JUMP (PC + P%i", poprnd);
- else if (prgfunc == 9)
- pr_cont("RAISE %i", poprnd);
- else if (prgfunc == 10)
- pr_cont("EXCPT %i", poprnd);
- else
- pr_cont("0x%04x", opcode);
-
-}
-
-#define BRCC_opcode 0x1000
-#define BRCC_offset_bits 0
-#define BRCC_offset_mask 0x3ff
-#define BRCC_B_bits 10
-#define BRCC_B_mask 0x1
-#define BRCC_T_bits 11
-#define BRCC_T_mask 0x1
-#define BRCC_code_bits 12
-#define BRCC_code_mask 0xf
-
-static void decode_BRCC_0(unsigned int opcode)
-{
- int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
- int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
-
- pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : "");
-}
-
-#define CALLa_opcode 0xe2000000
-#define CALLa_addr_bits 0
-#define CALLa_addr_mask 0xffffff
-#define CALLa_S_bits 24
-#define CALLa_S_mask 0x1
-#define CALLa_code_bits 25
-#define CALLa_code_mask 0x7f
-
-static void decode_CALLa_0(unsigned int opcode)
-{
- int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
-
- if (S)
- pr_cont("CALL pcrel");
- else
- pr_cont("JUMP.L");
-}
-
-#define LoopSetup_opcode 0xe0800000
-#define LoopSetup_eoffset_bits 0
-#define LoopSetup_eoffset_mask 0x3ff
-#define LoopSetup_dontcare_bits 10
-#define LoopSetup_dontcare_mask 0x3
-#define LoopSetup_reg_bits 12
-#define LoopSetup_reg_mask 0xf
-#define LoopSetup_soffset_bits 16
-#define LoopSetup_soffset_mask 0xf
-#define LoopSetup_c_bits 20
-#define LoopSetup_c_mask 0x1
-#define LoopSetup_rop_bits 21
-#define LoopSetup_rop_mask 0x3
-#define LoopSetup_code_bits 23
-#define LoopSetup_code_mask 0x1ff
-
-static void decode_LoopSetup_0(unsigned int opcode)
-{
- int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask);
- int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
- int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask);
-
- pr_cont("LSETUP <> LC%i", c);
- if ((rop & 1) == 1)
- pr_cont("= P%i", reg);
- if ((rop & 2) == 2)
- pr_cont(" >> 0x1");
-}
-
-#define DspLDST_opcode 0x9c00
-#define DspLDST_reg_bits 0
-#define DspLDST_reg_mask 0x7
-#define DspLDST_i_bits 3
-#define DspLDST_i_mask 0x3
-#define DspLDST_m_bits 5
-#define DspLDST_m_mask 0x3
-#define DspLDST_aop_bits 7
-#define DspLDST_aop_mask 0x3
-#define DspLDST_W_bits 9
-#define DspLDST_W_mask 0x1
-#define DspLDST_code_bits 10
-#define DspLDST_code_mask 0x3f
-
-static void decode_dspLDST_0(unsigned int opcode)
-{
- int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask);
- int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask);
- int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask);
- int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask);
- int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask);
-
- if (W == 0) {
- pr_cont("R%i", reg);
- switch (m) {
- case 0:
- pr_cont(" = ");
- break;
- case 1:
- pr_cont(".L = ");
- break;
- case 2:
- pr_cont(".W = ");
- break;
- }
- }
-
- pr_cont("[ I%i", i);
-
- switch (aop) {
- case 0:
- pr_cont("++ ]");
- break;
- case 1:
- pr_cont("-- ]");
- break;
- }
-
- if (W == 1) {
- pr_cont(" = R%i", reg);
- switch (m) {
- case 1:
- pr_cont(".L = ");
- break;
- case 2:
- pr_cont(".W = ");
- break;
- }
- }
-}
-
-#define LDST_opcode 0x9000
-#define LDST_reg_bits 0
-#define LDST_reg_mask 0x7
-#define LDST_ptr_bits 3
-#define LDST_ptr_mask 0x7
-#define LDST_Z_bits 6
-#define LDST_Z_mask 0x1
-#define LDST_aop_bits 7
-#define LDST_aop_mask 0x3
-#define LDST_W_bits 9
-#define LDST_W_mask 0x1
-#define LDST_sz_bits 10
-#define LDST_sz_mask 0x3
-#define LDST_code_bits 12
-#define LDST_code_mask 0xf
-
-static void decode_LDST_0(unsigned int opcode)
-{
- int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask);
- int W = ((opcode >> LDST_W_bits) & LDST_W_mask);
- int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask);
- int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask);
- int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask);
- int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask);
-
- if (W == 0)
- pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
- switch (sz) {
- case 1:
- pr_cont("W");
- break;
- case 2:
- pr_cont("B");
- break;
- }
-
- pr_cont("[P%i", ptr);
-
- switch (aop) {
- case 0:
- pr_cont("++");
- break;
- case 1:
- pr_cont("--");
- break;
- }
- pr_cont("]");
-
- if (W == 1)
- pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
- if (sz) {
- if (Z)
- pr_cont(" (X)");
- else
- pr_cont(" (Z)");
- }
-}
-
-#define LDSTii_opcode 0xa000
-#define LDSTii_reg_bit 0
-#define LDSTii_reg_mask 0x7
-#define LDSTii_ptr_bit 3
-#define LDSTii_ptr_mask 0x7
-#define LDSTii_offset_bit 6
-#define LDSTii_offset_mask 0xf
-#define LDSTii_op_bit 10
-#define LDSTii_op_mask 0x3
-#define LDSTii_W_bit 12
-#define LDSTii_W_mask 0x1
-#define LDSTii_code_bit 13
-#define LDSTii_code_mask 0x7
-
-static void decode_LDSTii_0(unsigned int opcode)
-{
- int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask);
- int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
- int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask);
- int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask);
- int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask);
-
- if (W == 0) {
- pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg,
- op == 1 || op == 2 ? "" : "W", ptr, offset);
- if (op == 2)
- pr_cont("(Z)");
- if (op == 3)
- pr_cont("(X)");
- } else {
- pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr,
- offset, op == 3 ? "P" : "R", reg);
- }
-}
-
-#define LDSTidxI_opcode 0xe4000000
-#define LDSTidxI_offset_bits 0
-#define LDSTidxI_offset_mask 0xffff
-#define LDSTidxI_reg_bits 16
-#define LDSTidxI_reg_mask 0x7
-#define LDSTidxI_ptr_bits 19
-#define LDSTidxI_ptr_mask 0x7
-#define LDSTidxI_sz_bits 22
-#define LDSTidxI_sz_mask 0x3
-#define LDSTidxI_Z_bits 24
-#define LDSTidxI_Z_mask 0x1
-#define LDSTidxI_W_bits 25
-#define LDSTidxI_W_mask 0x1
-#define LDSTidxI_code_bits 26
-#define LDSTidxI_code_mask 0x3f
-
-static void decode_LDSTidxI_0(unsigned int opcode)
-{
- int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask);
- int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask);
- int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask);
- int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask);
- int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask);
- int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
-
- if (W == 0)
- pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg);
-
- if (sz == 1)
- pr_cont("W");
- if (sz == 2)
- pr_cont("B");
-
- pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "",
- (offset & 0x1f) << 2);
-
- if (W == 0 && sz != 0) {
- if (Z)
- pr_cont("(X)");
- else
- pr_cont("(Z)");
- }
-
- if (W == 1)
- pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
-}
-
-static void decode_opcode(unsigned int opcode)
-{
-#ifdef CONFIG_BUG
- if (opcode == BFIN_BUG_OPCODE)
- pr_cont("BUG");
- else
-#endif
- if ((opcode & 0xffffff00) == ProgCtrl_opcode)
- decode_ProgCtrl_0(opcode);
- else if ((opcode & 0xfffff000) == BRCC_opcode)
- decode_BRCC_0(opcode);
- else if ((opcode & 0xfffff000) == 0x2000)
- pr_cont("JUMP.S");
- else if ((opcode & 0xfe000000) == CALLa_opcode)
- decode_CALLa_0(opcode);
- else if ((opcode & 0xff8000C0) == LoopSetup_opcode)
- decode_LoopSetup_0(opcode);
- else if ((opcode & 0xfffffc00) == DspLDST_opcode)
- decode_dspLDST_0(opcode);
- else if ((opcode & 0xfffff000) == LDST_opcode)
- decode_LDST_0(opcode);
- else if ((opcode & 0xffffe000) == LDSTii_opcode)
- decode_LDSTii_0(opcode);
- else if ((opcode & 0xfc000000) == LDSTidxI_opcode)
- decode_LDSTidxI_0(opcode);
- else if (opcode & 0xffff0000)
- pr_cont("0x%08x", opcode);
- else
- pr_cont("0x%04x", opcode);
-}
-
-#define BIT_MULTI_INS 0x08000000
-static void decode_instruction(unsigned short *address)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, address))
- return;
-
- decode_opcode(opcode);
-
- /* If things are a 32-bit instruction, it has the possibility of being
- * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions)
- * This test collidates with the unlink instruction, so disallow that
- */
- if ((opcode & 0xc0000000) == 0xc0000000 &&
- (opcode & BIT_MULTI_INS) &&
- (opcode & 0xe8000000) != 0xe8000000) {
- pr_cont(" || ");
- if (!get_instruction(&opcode, address + 2))
- return;
- decode_opcode(opcode);
- pr_cont(" || ");
- if (!get_instruction(&opcode, address + 3))
- return;
- decode_opcode(opcode);
- }
-}
-#endif
-
-void dump_bfin_trace_buffer(void)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int tflags, i = 0, fault = 0;
- char buf[150];
- unsigned short *addr;
- unsigned int cpu = raw_smp_processor_id();
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- int j, index;
-#endif
-
- trace_buffer_save(tflags);
-
- pr_notice("Hardware Trace:\n");
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n");
-#endif
-
- if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
- for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice("%4i Target : %s\n", i, buf);
- /* Normally, the faulting instruction doesn't go into
- * the trace buffer, (since it doesn't commit), so
- * we print out the fault address here
- */
- if (!fault && addr == ((unsigned short *)evt_ivhw)) {
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice(" FAULT : %s ", buf);
- decode_instruction(addr);
- pr_cont("\n");
- fault = 1;
- continue;
- }
- if (!fault && addr == (unsigned short *)trap &&
- (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) {
- decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
- pr_notice(" FAULT : %s ", buf);
- decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr);
- pr_cont("\n");
- fault = 1;
- }
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice(" Source : %s ", buf);
- decode_instruction(addr);
- pr_cont("\n");
- }
- }
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- if (trace_buff_offset)
- index = trace_buff_offset / 4;
- else
- index = EXPAND_LEN;
-
- j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
- while (j) {
- decode_address(buf, software_trace_buff[index]);
- pr_notice("%4i Target : %s\n", i, buf);
- index -= 1;
- if (index < 0)
- index = EXPAND_LEN;
- decode_address(buf, software_trace_buff[index]);
- pr_notice(" Source : %s ", buf);
- decode_instruction((unsigned short *)software_trace_buff[index]);
- pr_cont("\n");
- index -= 1;
- if (index < 0)
- index = EXPAND_LEN;
- j--;
- i++;
- }
-#endif
-
- trace_buffer_restore(tflags);
-#endif
-}
-EXPORT_SYMBOL(dump_bfin_trace_buffer);
-
-void dump_bfin_process(struct pt_regs *fp)
-{
- /* We should be able to look@fp->ipend, but we don't push it on the
- * stack all the time, so do this until we fix that */
- unsigned int context = bfin_read_IPEND();
-
- if (oops_in_progress)
- pr_emerg("Kernel OOPS in progress\n");
-
- if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
- pr_notice("HW Error context\n");
- else if (context & 0x0020)
- pr_notice("Deferred Exception context\n");
- else if (context & 0x3FC0)
- pr_notice("Interrupt context\n");
- else if (context & 0x4000)
- pr_notice("Deferred Interrupt context\n");
- else if (context & 0x8000)
- pr_notice("Kernel process context\n");
-
- /* Because we are crashing, and pointers could be bad, we check things
- * pretty closely before we use them
- */
- if ((unsigned long)current >= FIXED_CODE_START &&
- !((unsigned long)current & 0x3) && current->pid) {
- pr_notice("CURRENT PROCESS:\n");
- if (current->comm >= (char *)FIXED_CODE_START)
- pr_notice("COMM=%s PID=%d",
- current->comm, current->pid);
- else
- pr_notice("COMM= invalid");
-
- pr_cont(" CPU=%d\n", current_thread_info()->cpu);
- if (!((unsigned long)current->mm & 0x3) &&
- (unsigned long)current->mm >= FIXED_CODE_START) {
- pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n",
- (void *)current->mm->start_code,
- (void *)current->mm->end_code,
- (void *)current->mm->start_data,
- (void *)current->mm->end_data);
- pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
- (void *)current->mm->end_data,
- (void *)current->mm->brk,
- (void *)current->mm->start_stack);
- } else
- pr_notice("invalid mm\n");
- } else
- pr_notice("No Valid process in current context\n");
-}
-
-void dump_bfin_mem(struct pt_regs *fp)
-{
- unsigned short *addr, *erraddr, val = 0, err = 0;
- char sti = 0, buf[6];
-
- erraddr = (void *)fp->pc;
-
- pr_notice("return address: [0x%p]; contents of:", erraddr);
-
- for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
- addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
- addr++) {
- if (!((unsigned long)addr & 0xF))
- pr_notice("0x%p: ", addr);
-
- if (!get_mem16(&val, addr)) {
- val = 0;
- sprintf(buf, "????");
- } else
- sprintf(buf, "%04x", val);
-
- if (addr == erraddr) {
- pr_cont("[%s]", buf);
- err = val;
- } else
- pr_cont(" %s ", buf);
-
- /* Do any previous instructions turn on interrupts? */
- if (addr <= erraddr && /* in the past */
- ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
- val == 0x017b)) /* [SP++] = RETI */
- sti = 1;
- }
-
- pr_cont("\n");
-
- /* Hardware error interrupts can be deferred */
- if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
- oops_in_progress)){
- pr_notice("Looks like this was a deferred error - sorry\n");
-#ifndef CONFIG_DEBUG_HWERR
- pr_notice("The remaining message may be meaningless\n");
- pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
-#else
- /* If we are handling only one peripheral interrupt
- * and current mm and pid are valid, and the last error
- * was in that user space process's text area
- * print it out - because that is where the problem exists
- */
- if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
- (current->pid && current->mm)) {
- /* And the last RETI points to the current userspace context */
- if ((fp + 1)->pc >= current->mm->start_code &&
- (fp + 1)->pc <= current->mm->end_code) {
- pr_notice("It might be better to look around here :\n");
- pr_notice("-------------------------------------------\n");
- show_regs(fp + 1);
- pr_notice("-------------------------------------------\n");
- }
- }
-#endif
- }
-}
-
-void show_regs(struct pt_regs *fp)
-{
- char buf[150];
- struct irqaction *action;
- unsigned int i;
- unsigned long flags = 0;
- unsigned int cpu = raw_smp_processor_id();
- unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
-
- pr_notice("\n");
- show_regs_print_info(KERN_NOTICE);
-
- if (CPUID != bfin_cpuid())
- pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
- "but running on:0x%04x (Rev %d)\n",
- CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
-
- pr_notice("ADSP-%s-0.%d",
- CPU, bfin_compiled_revid());
-
- if (bfin_compiled_revid() != bfin_revid())
- pr_cont("(Detected 0.%d)", bfin_revid());
-
- pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
- get_cclk()/1000000, get_sclk()/1000000,
-#ifdef CONFIG_MPU
- "mpu on"
-#else
- "mpu off"
-#endif
- );
-
- pr_notice("%s", linux_banner);
-
- pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
- pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
- (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
- if (fp->ipend & EVT_IRPTEN)
- pr_notice(" Global Interrupts Disabled (IPEND[4])\n");
- if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
- EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
- pr_notice(" Peripheral interrupts masked off\n");
- if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
- pr_notice(" Kernel interrupts masked off\n");
- if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
- pr_notice(" HWERRCAUSE: 0x%lx\n",
- (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
-#ifdef EBIU_ERRMST
- /* If the error was from the EBIU, print it out */
- if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
- pr_notice(" EBIU Error Reason : 0x%04x\n",
- bfin_read_EBIU_ERRMST());
- pr_notice(" EBIU Error Address : 0x%08x\n",
- bfin_read_EBIU_ERRADD());
- }
-#endif
- }
- pr_notice(" EXCAUSE : 0x%lx\n",
- fp->seqstat & SEQSTAT_EXCAUSE);
- for (i = 2; i <= 15 ; i++) {
- if (fp->ipend & (1 << i)) {
- if (i != 4) {
- decode_address(buf, bfin_read32(EVT0 + 4*i));
- pr_notice(" physical IVG%i asserted : %s\n", i, buf);
- } else
- pr_notice(" interrupts disabled\n");
- }
- }
-
- /* if no interrupts are going off, don't print this out */
- if (fp->ipend & ~0x3F) {
- for (i = 0; i < (NR_IRQS - 1); i++) {
- struct irq_desc *desc = irq_to_desc(i);
- if (!in_atomic)
- raw_spin_lock_irqsave(&desc->lock, flags);
-
- action = desc->action;
- if (!action)
- goto unlock;
-
- decode_address(buf, (unsigned int)action->handler);
- pr_notice(" logical irq %3d mapped : %s", i, buf);
- for (action = action->next; action; action = action->next) {
- decode_address(buf, (unsigned int)action->handler);
- pr_cont(", %s", buf);
- }
- pr_cont("\n");
-unlock:
- if (!in_atomic)
- raw_spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-
- decode_address(buf, fp->rete);
- pr_notice(" RETE: %s\n", buf);
- decode_address(buf, fp->retn);
- pr_notice(" RETN: %s\n", buf);
- decode_address(buf, fp->retx);
- pr_notice(" RETX: %s\n", buf);
- decode_address(buf, fp->rets);
- pr_notice(" RETS: %s\n", buf);
- decode_address(buf, fp->pc);
- pr_notice(" PC : %s\n", buf);
-
- if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
- (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
- decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
- pr_notice("DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
- pr_notice("ICPLB_FAULT_ADDR: %s\n", buf);
- }
-
- pr_notice("PROCESSOR STATE:\n");
- pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
- fp->r0, fp->r1, fp->r2, fp->r3);
- pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
- fp->r4, fp->r5, fp->r6, fp->r7);
- pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
- fp->p0, fp->p1, fp->p2, fp->p3);
- pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
- fp->p4, fp->p5, fp->fp, (long)fp);
- pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
- fp->lb0, fp->lt0, fp->lc0);
- pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
- fp->lb1, fp->lt1, fp->lc1);
- pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
- fp->b0, fp->l0, fp->m0, fp->i0);
- pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
- fp->b1, fp->l1, fp->m1, fp->i1);
- pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
- fp->b2, fp->l2, fp->m2, fp->i2);
- pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
- fp->b3, fp->l3, fp->m3, fp->i3);
- pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- pr_notice("USP : %08lx ASTAT: %08lx\n",
- rdusp(), fp->astat);
-
- pr_notice("\n");
-}
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
deleted file mode 100644
index a323a40..0000000
--- a/arch/blackfin/kernel/traps.c
+++ /dev/null
@@ -1,585 +0,0 @@
-/*
- * Main exception handling logic.
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/bug.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <asm/traps.h>
-#include <asm/cplb.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <linux/irq.h>
-#include <asm/trace.h>
-#include <asm/fixed_code.h>
-#include <asm/pseudo_instructions.h>
-#include <asm/pda.h>
-#include <asm/asm-offsets.h>
-
-#ifdef CONFIG_KGDB
-# include <linux/kgdb.h>
-
-# define CHK_DEBUGGER_TRAP() \
- do { \
- kgdb_handle_exception(trapnr, sig, info.si_code, fp); \
- } while (0)
-# define CHK_DEBUGGER_TRAP_MAYBE() \
- do { \
- if (kgdb_connected) \
- CHK_DEBUGGER_TRAP(); \
- } while (0)
-#else
-# define CHK_DEBUGGER_TRAP() do { } while (0)
-# define CHK_DEBUGGER_TRAP_MAYBE() do { } while (0)
-#endif
-
-
-#ifdef CONFIG_DEBUG_VERBOSE
-#define verbose_printk(fmt, arg...) \
- printk(fmt, ##arg)
-#else
-#define verbose_printk(fmt, arg...) \
- ({ if (0) printk(fmt, ##arg); 0; })
-#endif
-
-#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE)
-u32 last_seqstat;
-#ifdef CONFIG_DEBUG_MMRS_MODULE
-EXPORT_SYMBOL(last_seqstat);
-#endif
-#endif
-
-/* Initiate the event table handler */
-void __init trap_init(void)
-{
- CSYNC();
- bfin_write_EVT3(trap);
- CSYNC();
-}
-
-static int kernel_mode_regs(struct pt_regs *regs)
-{
- return regs->ipend & 0xffc0;
-}
-
-asmlinkage notrace void trap_c(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int j;
-#endif
-#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
- int opcode;
-#endif
- unsigned int cpu = raw_smp_processor_id();
- const char *strerror = NULL;
- int sig = 0;
- siginfo_t info;
- unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE;
-
- trace_buffer_save(j);
-#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE)
- last_seqstat = (u32)fp->seqstat;
-#endif
-
- /* Important - be very careful dereferncing pointers - will lead to
- * double faults if the stack has become corrupt
- */
-
- /* trap_c() will be called for exceptions. During exceptions
- * processing, the pc value should be set with retx value.
- * With this change we can cleanup some code in signal.c- TODO
- */
- fp->orig_pc = fp->retx;
- /* printk("exception: 0x%x, ipend=%x, reti=%x, retx=%x\n",
- trapnr, fp->ipend, fp->pc, fp->retx); */
-
- /* send the appropriate signal to the user program */
- switch (trapnr) {
-
- /* This table works in conjunction with the one in ./mach-common/entry.S
- * Some exceptions are handled there (in assembly, in exception space)
- * Some are handled here, (in C, in interrupt space)
- * Some, like CPLB, are handled in both, where the normal path is
- * handled in assembly/exception space, and the error path is handled
- * here
- */
-
- /* 0x00 - Linux Syscall, getting here is an error */
- /* 0x01 - userspace gdb breakpoint, handled here */
- case VEC_EXCPT01:
- info.si_code = TRAP_ILLTRAP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a breakpoint in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
- /* 0x03 - User Defined, userspace stack overflow */
- case VEC_EXCPT03:
- info.si_code = SEGV_STACKFLOW;
- sig = SIGSEGV;
- strerror = KERN_NOTICE EXC_0x03(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x02 - KGDB initial connection and break signal trap */
- case VEC_EXCPT02:
-#ifdef CONFIG_KGDB
- info.si_code = TRAP_ILLTRAP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP();
- goto traps_done;
-#endif
- /* 0x04 - User Defined */
- /* 0x05 - User Defined */
- /* 0x06 - User Defined */
- /* 0x07 - User Defined */
- /* 0x08 - User Defined */
- /* 0x09 - User Defined */
- /* 0x0A - User Defined */
- /* 0x0B - User Defined */
- /* 0x0C - User Defined */
- /* 0x0D - User Defined */
- /* 0x0E - User Defined */
- /* 0x0F - User Defined */
- /* If we got here, it is most likely that someone was trying to use a
- * custom exception handler, and it is not actually installed properly
- */
- case VEC_EXCPT04 ... VEC_EXCPT15:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x04(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x10 HW Single step, handled here */
- case VEC_STEP:
- info.si_code = TRAP_STEP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a single step in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
- /* 0x11 - Trace Buffer Full, handled here */
- case VEC_OVFLOW:
- info.si_code = TRAP_TRACEFLOW;
- sig = SIGTRAP;
- strerror = KERN_NOTICE EXC_0x11(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x12 - Reserved, Caught by default */
- /* 0x13 - Reserved, Caught by default */
- /* 0x14 - Reserved, Caught by default */
- /* 0x15 - Reserved, Caught by default */
- /* 0x16 - Reserved, Caught by default */
- /* 0x17 - Reserved, Caught by default */
- /* 0x18 - Reserved, Caught by default */
- /* 0x19 - Reserved, Caught by default */
- /* 0x1A - Reserved, Caught by default */
- /* 0x1B - Reserved, Caught by default */
- /* 0x1C - Reserved, Caught by default */
- /* 0x1D - Reserved, Caught by default */
- /* 0x1E - Reserved, Caught by default */
- /* 0x1F - Reserved, Caught by default */
- /* 0x20 - Reserved, Caught by default */
- /* 0x21 - Undefined Instruction, handled here */
- case VEC_UNDEF_I:
-#ifdef CONFIG_BUG
- if (kernel_mode_regs(fp)) {
- switch (report_bug(fp->pc, fp)) {
- case BUG_TRAP_TYPE_NONE:
- break;
- case BUG_TRAP_TYPE_WARN:
- dump_bfin_trace_buffer();
- fp->pc += 2;
- goto traps_done;
- case BUG_TRAP_TYPE_BUG:
- /* call to panic() will dump trace, and it is
- * off at this point, so it won't be clobbered
- */
- panic("BUG()");
- }
- }
-#endif
-#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
- /*
- * Support for the fake instructions, if the instruction fails,
- * then just execute a illegal opcode failure (like normal).
- * Don't support these instructions inside the kernel
- */
- if (!kernel_mode_regs(fp) && get_instruction(&opcode, (unsigned short *)fp->pc)) {
- if (execute_pseudodbg_assert(fp, opcode))
- goto traps_done;
- if (execute_pseudodbg(fp, opcode))
- goto traps_done;
- }
-#endif
- info.si_code = ILL_ILLOPC;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x21(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x22 - Illegal Instruction Combination, handled here */
- case VEC_ILGAL_I:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x22(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x23 - Data CPLB protection violation, handled here */
- case VEC_CPLB_VL:
- info.si_code = ILL_CPLB_VI;
- sig = SIGSEGV;
- strerror = KERN_NOTICE EXC_0x23(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x24 - Data access misaligned, handled here */
- case VEC_MISALI_D:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x24(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x25 - Unrecoverable Event, handled here */
- case VEC_UNCOV:
- info.si_code = ILL_ILLEXCPT;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x25(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr,
- error case is handled here */
- case VEC_CPLB_M:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x26(KERN_NOTICE);
- break;
- /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */
- case VEC_CPLB_MHIT:
- info.si_code = ILL_CPLB_MULHIT;
- sig = SIGSEGV;
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- if (cpu_pda[cpu].dcplb_fault_addr < FIXED_CODE_START)
- strerror = KERN_NOTICE "NULL pointer access\n";
- else
-#endif
- strerror = KERN_NOTICE EXC_0x27(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x28 - Emulation Watchpoint, handled here */
- case VEC_WATCH:
- info.si_code = TRAP_WATCHPT;
- sig = SIGTRAP;
- pr_debug(EXC_0x28(KERN_DEBUG));
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a watchpoint in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
-#ifdef CONFIG_BF535
- /* 0x29 - Instruction fetch access error (535 only) */
- case VEC_ISTRU_VL: /* ADSP-BF535 only (MH) */
- info.si_code = BUS_OPFETCH;
- sig = SIGBUS;
- strerror = KERN_NOTICE "BF535: VEC_ISTRU_VL\n";
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
-#else
- /* 0x29 - Reserved, Caught by default */
-#endif
- /* 0x2A - Instruction fetch misaligned, handled here */
- case VEC_MISALI_I:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2A(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2B - Instruction CPLB protection violation, handled here */
- case VEC_CPLB_I_VL:
- info.si_code = ILL_CPLB_VI;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2B(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */
- case VEC_CPLB_I_M:
- info.si_code = ILL_CPLB_MISS;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2C(KERN_NOTICE);
- break;
- /* 0x2D - Instruction CPLB Multiple Hits, handled here */
- case VEC_CPLB_I_MHIT:
- info.si_code = ILL_CPLB_MULHIT;
- sig = SIGSEGV;
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- if (cpu_pda[cpu].icplb_fault_addr < FIXED_CODE_START)
- strerror = KERN_NOTICE "Jump to NULL address\n";
- else
-#endif
- strerror = KERN_NOTICE EXC_0x2D(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2E - Illegal use of Supervisor Resource, handled here */
- case VEC_ILL_RES:
- info.si_code = ILL_PRVOPC;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x2E(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2F - Reserved, Caught by default */
- /* 0x30 - Reserved, Caught by default */
- /* 0x31 - Reserved, Caught by default */
- /* 0x32 - Reserved, Caught by default */
- /* 0x33 - Reserved, Caught by default */
- /* 0x34 - Reserved, Caught by default */
- /* 0x35 - Reserved, Caught by default */
- /* 0x36 - Reserved, Caught by default */
- /* 0x37 - Reserved, Caught by default */
- /* 0x38 - Reserved, Caught by default */
- /* 0x39 - Reserved, Caught by default */
- /* 0x3A - Reserved, Caught by default */
- /* 0x3B - Reserved, Caught by default */
- /* 0x3C - Reserved, Caught by default */
- /* 0x3D - Reserved, Caught by default */
- /* 0x3E - Reserved, Caught by default */
- /* 0x3F - Reserved, Caught by default */
- case VEC_HWERR:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- switch (fp->seqstat & SEQSTAT_HWERRCAUSE) {
- /* System MMR Error */
- case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR):
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE HWC_x2(KERN_NOTICE);
- break;
- /* External Memory Addressing Error */
- case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
- if (ANOMALY_05000310) {
- static unsigned long anomaly_rets;
-
- if ((fp->pc >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
- (fp->pc < (L1_CODE_START + L1_CODE_LENGTH))) {
- /*
- * A false hardware error will happen while fetching at
- * the L1 instruction SRAM boundary. Ignore it.
- */
- anomaly_rets = fp->rets;
- goto traps_done;
- } else if (fp->rets == anomaly_rets) {
- /*
- * While boundary code returns to a function, at the ret
- * point, a new false hardware error might occur too based
- * on tests. Ignore it too.
- */
- goto traps_done;
- } else if ((fp->rets >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
- (fp->rets < (L1_CODE_START + L1_CODE_LENGTH))) {
- /*
- * If boundary code calls a function,@the entry point,
- * a new false hardware error maybe happen based on tests.
- * Ignore it too.
- */
- goto traps_done;
- } else
- anomaly_rets = 0;
- }
-
- info.si_code = BUS_ADRERR;
- sig = SIGBUS;
- strerror = KERN_NOTICE HWC_x3(KERN_NOTICE);
- break;
- /* Performance Monitor Overflow */
- case (SEQSTAT_HWERRCAUSE_PERF_FLOW):
- strerror = KERN_NOTICE HWC_x12(KERN_NOTICE);
- break;
- /* RAISE 5 instruction */
- case (SEQSTAT_HWERRCAUSE_RAISE_5):
- printk(KERN_NOTICE HWC_x18(KERN_NOTICE));
- break;
- default: /* Reserved */
- printk(KERN_NOTICE HWC_default(KERN_NOTICE));
- break;
- }
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /*
- * We should be handling all known exception types above,
- * if we get here we hit a reserved one, so panic
- */
- default:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- verbose_printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n",
- (fp->seqstat & SEQSTAT_EXCAUSE));
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- }
-
- BUG_ON(sig == 0);
-
- /* If the fault was caused by a kernel thread, or interrupt handler
- * we will kernel panic, so the system reboots.
- */
- if (kernel_mode_regs(fp) || (current && !current->mm)) {
- console_verbose();
- oops_in_progress = 1;
- }
-
- if (sig != SIGTRAP) {
- if (strerror)
- verbose_printk(strerror);
-
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
-
- /* Print out the trace buffer if it makes sense */
-#ifndef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
- if (trapnr == VEC_CPLB_I_M || trapnr == VEC_CPLB_M)
- verbose_printk(KERN_NOTICE "No trace since you do not have "
- "CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE enabled\n\n");
- else
-#endif
- dump_bfin_trace_buffer();
-
- if (oops_in_progress) {
- /* Dump the current kernel stack */
- verbose_printk(KERN_NOTICE "Kernel Stack\n");
- show_stack(current, NULL);
- print_modules();
-#ifndef CONFIG_ACCESS_CHECK
- verbose_printk(KERN_EMERG "Please turn on "
- "CONFIG_ACCESS_CHECK\n");
-#endif
- panic("Kernel exception");
- } else {
-#ifdef CONFIG_DEBUG_VERBOSE
- unsigned long *stack;
- /* Dump the user space stack */
- stack = (unsigned long *)rdusp();
- verbose_printk(KERN_NOTICE "Userspace Stack\n");
- show_stack(NULL, stack);
-#endif
- }
- }
-
-#ifdef CONFIG_IPIPE
- if (!ipipe_trap_notify(fp->seqstat & 0x3f, fp))
-#endif
- {
- info.si_signo = sig;
- info.si_errno = 0;
- switch (trapnr) {
- case VEC_CPLB_VL:
- case VEC_MISALI_D:
- case VEC_CPLB_M:
- case VEC_CPLB_MHIT:
- info.si_addr = (void __user *)cpu_pda[cpu].dcplb_fault_addr;
- break;
- default:
- info.si_addr = (void __user *)fp->pc;
- break;
- }
- force_sig_info(sig, &info, current);
- }
-
- if ((ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) ||
- (ANOMALY_05000281 && trapnr == VEC_HWERR) ||
- (ANOMALY_05000189 && (trapnr == VEC_CPLB_I_VL || trapnr == VEC_CPLB_VL)))
- fp->pc = SAFE_USER_INSTRUCTION;
-
- traps_done:
- trace_buffer_restore(j);
-}
-
-asmlinkage void double_fault_c(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int j;
- trace_buffer_save(j);
-#endif
-
- console_verbose();
- oops_in_progress = 1;
-#ifdef CONFIG_DEBUG_VERBOSE
- printk(KERN_EMERG "Double Fault\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
- if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) {
- unsigned int cpu = raw_smp_processor_id();
- char buf[150];
- decode_address(buf, cpu_pda[cpu].retx_doublefault);
- printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
- (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf);
- decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf);
-
- decode_address(buf, fp->retx);
- printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf);
- } else
-#endif
- {
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_bfin_trace_buffer();
- }
-#endif
- panic("Double Fault - unrecoverable event");
-
-}
-
-
-void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
-{
- switch (cplb_panic) {
- case CPLB_NO_UNLOCKED:
- printk(KERN_EMERG "All CPLBs are locked\n");
- break;
- case CPLB_PROT_VIOL:
- return;
- case CPLB_NO_ADDR_MATCH:
- return;
- case CPLB_UNKNOWN_ERR:
- printk(KERN_EMERG "Unknown CPLB Exception\n");
- break;
- }
-
- oops_in_progress = 1;
-
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_stack();
- panic("Unrecoverable event");
-}
-
-#ifdef CONFIG_BUG
-int is_valid_bugaddr(unsigned long addr)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, (unsigned short *)addr))
- return 0;
-
- return opcode == BFIN_BUG_OPCODE;
-}
-#endif
-
-/* stub this out */
-#ifndef CONFIG_DEBUG_VERBOSE
-void show_regs(struct pt_regs *fp)
-{
-
-}
-#endif
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
deleted file mode 100644
index 334ef81..0000000
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/mem_map.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
-
-OUTPUT_FORMAT("elf32-bfin")
-ENTRY(__start)
-_jiffies = _jiffies_64;
-
-SECTIONS
-{
-#ifdef CONFIG_RAMKERNEL
- . = CONFIG_BOOT_LOAD;
-#else
- . = CONFIG_ROM_BASE;
-#endif
-
- /* Neither the text, ro_data or bss section need to be aligned
- * So pack them back to back
- */
- .text :
- {
- __text = .;
- _text = .;
- __stext = .;
- TEXT_TEXT
-#ifndef CONFIG_SCHEDULE_L1
- SCHED_TEXT
-#endif
- CPUIDLE_TEXT
- LOCK_TEXT
- IRQENTRY_TEXT
- SOFTIRQENTRY_TEXT
- KPROBES_TEXT
-#ifdef CONFIG_ROMKERNEL
- __sinittext = .;
- INIT_TEXT
- __einittext = .;
- EXIT_TEXT
-#endif
- *(.text.*)
- *(.fixup)
-
-#if !L1_CODE_LENGTH
- *(.l1.text)
-#endif
- __etext = .;
- }
-
- EXCEPTION_TABLE(4)
- NOTES
-
- /* Just in case the first read only is a 32-bit access */
- RO_DATA(4)
- __rodata_end = .;
-
-#ifdef CONFIG_ROMKERNEL
- . = CONFIG_BOOT_LOAD;
- .bss : AT(__rodata_end)
-#else
- .bss :
-#endif
- {
- . = ALIGN(4);
- ___bss_start = .;
- *(.bss .bss.*)
- *(COMMON)
-#if !L1_DATA_A_LENGTH
- *(.l1.bss)
-#endif
-#if !L1_DATA_B_LENGTH
- *(.l1.bss.B)
-#endif
- . = ALIGN(4);
- ___bss_stop = .;
- }
-
-#if defined(CONFIG_ROMKERNEL)
- .data : AT(LOADADDR(.bss) + SIZEOF(.bss))
-#else
- .data :
-#endif
- {
- __sdata = .;
- /* This gets done first, so the glob doesn't suck it in */
- CACHELINE_ALIGNED_DATA(32)
-
-#if !L1_DATA_A_LENGTH
- . = ALIGN(32);
- *(.data_l1.cacheline_aligned)
- *(.l1.data)
-#endif
-#if !L1_DATA_B_LENGTH
- *(.l1.data.B)
-#endif
-#if !L2_LENGTH
- . = ALIGN(32);
- *(.data_l2.cacheline_aligned)
- *(.l2.data)
-#endif
-
- DATA_DATA
- CONSTRUCTORS
-
- INIT_TASK_DATA(THREAD_SIZE)
-
- __edata = .;
- }
- __data_lma = LOADADDR(.data);
- __data_len = SIZEOF(.data);
-
- BUG_TABLE
-
- /* The init section should be last, so when we free it, it goes into
- * the general memory pool, and (hopefully) will decrease fragmentation
- * a tiny bit. The init section has a _requirement_ that it be
- * PAGE_SIZE aligned
- */
- . = ALIGN(PAGE_SIZE);
- ___init_begin = .;
-
-#ifdef CONFIG_RAMKERNEL
- INIT_TEXT_SECTION(PAGE_SIZE)
-
- /* We have to discard exit text and such at runtime, not link time, to
- * handle embedded cross-section references (alt instructions, bug
- * table, eh_frame, etc...). We need all of our .text up front and
- * .data after it for PCREL call issues.
- */
- .exit.text :
- {
- EXIT_TEXT
- }
-
- . = ALIGN(16);
- INIT_DATA_SECTION(16)
- PERCPU_SECTION(32)
-
- .exit.data :
- {
- EXIT_DATA
- }
-
- .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data))
-#else
- .init.data : AT(__data_lma + __data_len + 32)
- {
- __sinitdata = .;
- INIT_DATA
- INIT_SETUP(16)
- INIT_CALLS
- CON_INITCALL
- SECURITY_INITCALL
- INIT_RAM_FS
-
- . = ALIGN(PAGE_SIZE);
- ___per_cpu_load = .;
- PERCPU_INPUT(32)
-
- EXIT_DATA
- __einitdata = .;
- }
- __init_data_lma = LOADADDR(.init.data);
- __init_data_len = SIZEOF(.init.data);
- __init_data_end = .;
-
- .text_l1 L1_CODE_START : AT(__init_data_lma + __init_data_len)
-#endif
- {
- . = ALIGN(4);
- __stext_l1 = .;
- *(.l1.text.head)
- *(.l1.text)
-#ifdef CONFIG_SCHEDULE_L1
- SCHED_TEXT
-#endif
- . = ALIGN(4);
- __etext_l1 = .;
- }
- __text_l1_lma = LOADADDR(.text_l1);
- __text_l1_len = SIZEOF(.text_l1);
- ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!")
-
- .data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len)
- {
- . = ALIGN(4);
- __sdata_l1 = .;
- *(.l1.data)
- __edata_l1 = .;
-
- . = ALIGN(32);
- *(.data_l1.cacheline_aligned)
-
- . = ALIGN(4);
- __sbss_l1 = .;
- *(.l1.bss)
- . = ALIGN(4);
- __ebss_l1 = .;
- }
- __data_l1_lma = LOADADDR(.data_l1);
- __data_l1_len = SIZEOF(.data_l1);
- ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!")
-
- .data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len)
- {
- . = ALIGN(4);
- __sdata_b_l1 = .;
- *(.l1.data.B)
- __edata_b_l1 = .;
-
- . = ALIGN(4);
- __sbss_b_l1 = .;
- *(.l1.bss.B)
- . = ALIGN(4);
- __ebss_b_l1 = .;
- }
- __data_b_l1_lma = LOADADDR(.data_b_l1);
- __data_b_l1_len = SIZEOF(.data_b_l1);
- ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!")
-
- .text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len)
- {
- . = ALIGN(4);
- __stext_l2 = .;
- *(.l2.text)
- . = ALIGN(4);
- __etext_l2 = .;
-
- . = ALIGN(4);
- __sdata_l2 = .;
- *(.l2.data)
- __edata_l2 = .;
-
- . = ALIGN(32);
- *(.data_l2.cacheline_aligned)
-
- . = ALIGN(4);
- __sbss_l2 = .;
- *(.l2.bss)
- . = ALIGN(4);
- __ebss_l2 = .;
- }
- __l2_lma = LOADADDR(.text_data_l2);
- __l2_len = SIZEOF(.text_data_l2);
- ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!")
-
- /* Force trailing alignment of our init section so that when we
- * free our init memory, we don't leave behind a partial page.
- */
-#ifdef CONFIG_RAMKERNEL
- . = __l2_lma + __l2_len;
-#else
- . = __init_data_end;
-#endif
- . = ALIGN(PAGE_SIZE);
- ___init_end = .;
-
- __end =.;
-
- STABS_DEBUG
-
- DWARF_DEBUG
-
- DISCARDS
-}
diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile
deleted file mode 100644
index 74ddde0..0000000
--- a/arch/blackfin/lib/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/lib/Makefile
-#
-
-lib-y := \
- ashldi3.o ashrdi3.o lshrdi3.o \
- muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \
- memcpy.o memset.o memcmp.o memchr.o memmove.o \
- strcmp.o strcpy.o strncmp.o strncpy.o \
- umulsi3_highpart.o smulsi3_highpart.o \
- ins.o outs.o
diff --git a/arch/blackfin/lib/ashldi3.c b/arch/blackfin/lib/ashldi3.c
deleted file mode 100644
index ab69d87..0000000
--- a/arch/blackfin/lib/ashldi3.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __ashldi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __ashldi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- w.s.low = 0;
- w.s.high = (USItype) uu.s.low << -bm;
- } else {
- USItype carries = (USItype) uu.s.low >> bm;
- w.s.low = (USItype) uu.s.low << b;
- w.s.high = ((USItype) uu.s.high << b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/blackfin/lib/ashrdi3.c b/arch/blackfin/lib/ashrdi3.c
deleted file mode 100644
index b5b351e..0000000
--- a/arch/blackfin/lib/ashrdi3.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __ashrdi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __ashrdi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- /* w.s.high = 1..1 or 0..0 */
- w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1);
- w.s.low = uu.s.high >> -bm;
- } else {
- USItype carries = (USItype) uu.s.high << bm;
- w.s.high = uu.s.high >> b;
- w.s.low = ((USItype) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/blackfin/lib/divsi3.S b/arch/blackfin/lib/divsi3.S
deleted file mode 100644
index ef2cd99..0000000
--- a/arch/blackfin/lib/divsi3.S
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- *
- * 16 / 32 bit signed division.
- * Special cases :
- * 1) If(numerator == 0)
- * return 0
- * 2) If(denominator ==0)
- * return positive max = 0x7fffffff
- * 3) If(numerator == denominator)
- * return 1
- * 4) If(denominator ==1)
- * return numerator
- * 5) If(denominator == -1)
- * return -numerator
- *
- * Operand : R0 - Numerator (i)
- * R1 - Denominator (i)
- * R0 - Quotient (o)
- * Registers Used : R2-R7,P0-P2
- *
- */
-
-.global ___divsi3;
-.type ___divsi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2;
-___divsi3 :
-
-
- R3 = R0 ^ R1;
- R0 = ABS R0;
-
- CC = V;
-
- r3 = rot r3 by -1;
- r1 = abs r1; /* now both positive, r3.30 means "negate result",
- ** r3.31 means overflow, add one to result
- */
- cc = r0 < r1;
- if cc jump .Lret_zero;
- r2 = r1 >> 15;
- cc = r2;
- if cc jump .Lidents;
- r2 = r1 << 16;
- cc = r2 <= r0;
- if cc jump .Lidents;
-
- DIVS(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
-
- R0 = R0.L (Z);
- r1 = r3 >> 31; /* add overflow issue back in */
- r0 = r0 + r1;
- r1 = -r0;
- cc = bittst(r3, 30);
- if cc r0 = r1;
- RTS;
-
-/* Can't use the primitives. Test common identities.
-** If the identity is true, return the value in R2.
-*/
-
-.Lidents:
- CC = R1 == 0; /* check for divide by zero */
- IF CC JUMP .Lident_return;
-
- CC = R0 == 0; /* check for division of zero */
- IF CC JUMP .Lzero_return;
-
- CC = R0 == R1; /* check for identical operands */
- IF CC JUMP .Lident_return;
-
- CC = R1 == 1; /* check for divide by 1 */
- IF CC JUMP .Lident_return;
-
- R2.L = ONES R1;
- R2 = R2.L (Z);
- CC = R2 == 1;
- IF CC JUMP .Lpower_of_two;
-
- /* Identities haven't helped either.
- ** Perform the full division process.
- */
-
- P1 = 31; /* Set loop counter */
-
- [--SP] = (R7:5); /* Push registers R5-R7 */
- R2 = -R1;
- [--SP] = R2;
- R2 = R0 << 1; /* R2 lsw of dividend */
- R6 = R0 ^ R1; /* Get sign */
- R5 = R6 >> 31; /* Shift sign to LSB */
-
- R0 = 0 ; /* Clear msw partial remainder */
- R2 = R2 | R5; /* Shift quotient bit */
- R6 = R0 ^ R1; /* Get new quotient bit */
-
- LSETUP(.Llst,.Llend) LC0 = P1; /* Setup loop */
-.Llst: R7 = R2 >> 31; /* record copy of carry from R2 */
- R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */
- R0 = R0 << 1 || R5 = [SP];
- R0 = R0 | R7; /* and add carry */
- CC = R6 < 0; /* Check quotient(AQ) */
- /* we might be subtracting divisor (AQ==0) */
- IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/
- R0 = R0 + R5; /* do add or subtract, as indicated by AQ */
- R6 = R0 ^ R1; /* Generate next quotient bit */
- R5 = R6 >> 31;
- /* Assume AQ==1, shift in zero */
- BITTGL(R5,0); /* tweak AQ to be what we want to shift in */
-.Llend: R2 = R2 + R5; /* and then set shifted-in value to
- ** tweaked AQ.
- */
- r1 = r3 >> 31;
- r2 = r2 + r1;
- cc = bittst(r3,30);
- r0 = -r2;
- if !cc r0 = r2;
- SP += 4;
- (R7:5)= [SP++]; /* Pop registers R6-R7 */
- RTS;
-
-.Lident_return:
- CC = R1 == 0; /* check for divide by zero => 0x7fffffff */
- R2 = -1 (X);
- R2 >>= 1;
- IF CC JUMP .Ltrue_ident_return;
-
- CC = R0 == R1; /* check for identical operands => 1 */
- R2 = 1 (Z);
- IF CC JUMP .Ltrue_ident_return;
-
- R2 = R0; /* assume divide by 1 => numerator */
- /*FALLTHRU*/
-
-.Ltrue_ident_return:
- R0 = R2; /* Return an identity value */
- R2 = -R2;
- CC = bittst(R3,30);
- IF CC R0 = R2;
-.Lzero_return:
- RTS; /* ...including zero */
-
-.Lpower_of_two:
- /* Y has a single bit set, which means it's a power of two.
- ** That means we can perform the division just by shifting
- ** X to the right the appropriate number of bits
- */
-
- /* signbits returns the number of sign bits, minus one.
- ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need
- ** to shift right n-signbits spaces. It also means 0x80000000
- ** is a special case, because that *also* gives a signbits of 0
- */
-
- R2 = R0 >> 31;
- CC = R1 < 0;
- IF CC JUMP .Ltrue_ident_return;
-
- R1.l = SIGNBITS R1;
- R1 = R1.L (Z);
- R1 += -30;
- R0 = LSHIFT R0 by R1.L;
- r1 = r3 >> 31;
- r0 = r0 + r1;
- R2 = -R0; // negate result if necessary
- CC = bittst(R3,30);
- IF CC R0 = R2;
- RTS;
-
-.Lret_zero:
- R0 = 0;
- RTS;
-
-.size ___divsi3, .-___divsi3
diff --git a/arch/blackfin/lib/gcclib.h b/arch/blackfin/lib/gcclib.h
deleted file mode 100644
index 724f07f..0000000
--- a/arch/blackfin/lib/gcclib.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define BITS_PER_UNIT 8
-#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
-
-typedef unsigned int UQItype __attribute__ ((mode(QI)));
-typedef int SItype __attribute__ ((mode(SI)));
-typedef unsigned int USItype __attribute__ ((mode(SI)));
-typedef int DItype __attribute__ ((mode(DI)));
-typedef int word_type __attribute__ ((mode(__word__)));
-typedef unsigned int UDItype __attribute__ ((mode(DI)));
-
-struct DIstruct {
- SItype low, high;
-};
-
-typedef union {
- struct DIstruct s;
- DItype ll;
-} DIunion;
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
deleted file mode 100644
index d59608d..0000000
--- a/arch/blackfin/lib/ins.S
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-.align 2
-
-#ifdef CONFIG_IPIPE
-# define DO_CLI \
- [--sp] = rets; \
- [--sp] = (P5:0); \
- sp += -12; \
- call ___ipipe_disable_root_irqs_hw; \
- sp += 12; \
- (P5:0) = [sp++];
-# define CLI_INNER_NOP
-#else
-# define DO_CLI cli R3;
-# define CLI_INNER_NOP nop; nop; nop;
-#endif
-
-#ifdef CONFIG_IPIPE
-# define DO_STI \
- sp += -12; \
- call ___ipipe_enable_root_irqs_hw; \
- sp += 12; \
-2: rets = [sp++];
-#else
-# define DO_STI 2: sti R3;
-#endif
-
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-# define CLI_OUTER DO_CLI;
-# define STI_OUTER DO_STI;
-# define CLI_INNER 1:
-# if ANOMALY_05000416
-# define STI_INNER nop; 2: nop;
-# else
-# define STI_INNER 2:
-# endif
-#else
-# define CLI_OUTER
-# define STI_OUTER
-# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
-# define STI_INNER DO_STI;
-#endif
-
-/*
- * Reads on the Blackfin are speculative. In Blackfin terms, this means they
- * can be interrupted at any time (even after they have been issued on to the
- * external bus), and re-issued after the interrupt occurs.
- *
- * If a FIFO is sitting on the end of the read, it will see two reads,
- * when the core only sees one. The FIFO receives the read which is cancelled,
- * and not delivered to the core.
- *
- * To solve this, interrupts are turned off before reads occur to I/O space.
- * There are 3 versions of all these functions
- * - turns interrupts off every read (higher overhead, but lower latency)
- * - turns interrupts off every loop (low overhead, but longer latency)
- * - DMA version, which do not suffer from this issue. DMA versions have
- * different name (prefixed by dma_ ), and are located in
- * ../kernel/bfin_dma.c
- * Using the dma related functions are recommended for transferring large
- * buffers in/out of FIFOs.
- */
-
-#define COMMON_INS(func, ops) \
-ENTRY(_ins##func) \
- P0 = R0; /* P0 = port */ \
- CLI_OUTER; /* 3 instructions before first read access */ \
- P1 = R1; /* P1 = address */ \
- P2 = R2; /* P2 = count */ \
- SSYNC; \
- \
- LSETUP(1f, 2f) LC0 = P2; \
- CLI_INNER; \
- ops; \
- STI_INNER; \
- \
- STI_OUTER; \
- RTS; \
-ENDPROC(_ins##func)
-
-COMMON_INS(l, \
- R0 = [P0]; \
- [P1++] = R0; \
-)
-
-COMMON_INS(w, \
- R0 = W[P0]; \
- W[P1++] = R0; \
-)
-
-COMMON_INS(w_8, \
- R0 = W[P0]; \
- B[P1++] = R0; \
- R0 = R0 >> 8; \
- B[P1++] = R0; \
-)
-
-COMMON_INS(b, \
- R0 = B[P0]; \
- B[P1++] = R0; \
-)
-
-COMMON_INS(l_16, \
- R0 = [P0]; \
- W[P1++] = R0; \
- R0 = R0 >> 16; \
- W[P1++] = R0; \
-)
diff --git a/arch/blackfin/lib/lshrdi3.c b/arch/blackfin/lib/lshrdi3.c
deleted file mode 100644
index 53f1741..0000000
--- a/arch/blackfin/lib/lshrdi3.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __lshrdi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __lshrdi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- w.s.high = 0;
- w.s.low = (USItype) uu.s.high >> -bm;
- } else {
- USItype carries = (USItype) uu.s.high << bm;
- w.s.high = (USItype) uu.s.high >> b;
- w.s.low = ((USItype) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/blackfin/lib/memchr.S b/arch/blackfin/lib/memchr.S
deleted file mode 100644
index bcfc8a1..0000000
--- a/arch/blackfin/lib/memchr.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *memchr(const void *s, int c, size_t n);
- * R0 = address (s)
- * R1 = sought byte (c)
- * R2 = count (n)
- *
- * Returns pointer to located character.
- */
-
-.text
-
-.align 2
-
-ENTRY(_memchr)
- P0 = R0; /* P0 = address */
- P2 = R2; /* P2 = count */
- R1 = R1.B(Z);
- CC = R2 == 0;
- IF CC JUMP .Lfailed;
-
-.Lbytes:
- LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2;
-
-.Lbyte_loop_s:
- R3 = B[P0++](Z);
- CC = R3 == R1;
- IF CC JUMP .Lfound;
-.Lbyte_loop_e:
- NOP;
-
-.Lfailed:
- R0=0;
- RTS;
-
-.Lfound:
- R0 = P0;
- R0 += -1;
- RTS;
-
-ENDPROC(_memchr)
diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S
deleted file mode 100644
index 2e1c947..0000000
--- a/arch/blackfin/lib/memcmp.S
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* int memcmp(const void *s1, const void *s2, size_t n);
- * R0 = First Address (s1)
- * R1 = Second Address (s2)
- * R2 = count (n)
- *
- * Favours word aligned data.
- */
-
-.text
-
-.align 2
-
-ENTRY(_memcmp)
- I1 = P3;
- P0 = R0; /* P0 = s1 address */
- P3 = R1; /* P3 = s2 Address */
- P2 = R2 ; /* P2 = count */
- CC = R2 <= 7(IU);
- IF CC JUMP .Ltoo_small;
- I0 = R1; /* s2 */
- R1 = R1 | R0; /* OR addresses together */
- R1 <<= 30; /* check bottom two bits */
- CC = AZ; /* AZ set if zero. */
- IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned. */
-
- P1 = P2 >> 2; /* count = n/4 */
- R3 = 3;
- R2 = R2 & R3; /* remainder */
- P2 = R2; /* set remainder */
-
- LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1;
-.Lquad_loop_s:
-#if ANOMALY_05000202
- R0 = [P0++];
- R1 = [I0++];
-#else
- MNOP || R0 = [P0++] || R1 = [I0++];
-#endif
- CC = R0 == R1;
- IF !CC JUMP .Lquad_different;
-.Lquad_loop_e:
- NOP;
-
- P3 = I0; /* s2 */
-.Ltoo_small:
- CC = P2 == 0; /* Check zero count*/
- IF CC JUMP .Lfinished; /* very unlikely*/
-
-.Lbytes:
- LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2;
-.Lbyte_loop_s:
- R1 = B[P3++](Z); /* *s2 */
- R0 = B[P0++](Z); /* *s1 */
- CC = R0 == R1;
- IF !CC JUMP .Ldifferent;
-.Lbyte_loop_e:
- NOP;
-
-.Ldifferent:
- R0 = R0 - R1;
- P3 = I1;
- RTS;
-
-.Lquad_different:
- /* We've read two quads which don't match.
- * Can't just compare them, because we're
- * a little-endian machine, so the MSBs of
- * the regs occur at later addresses in the
- * string.
- * Arrange to re-read those two quads again,
- * byte-by-byte.
- */
- P0 += -4; /* back up to the start of the */
- P3 = I0; /* quads, and increase the*/
- P2 += 4; /* remainder count*/
- P3 += -4;
- JUMP .Lbytes;
-
-.Lfinished:
- R0 = 0;
- P3 = I1;
- RTS;
-
-ENDPROC(_memcmp)
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
deleted file mode 100644
index 53cb369..0000000
--- a/arch/blackfin/lib/memcpy.S
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * internal version of memcpy(), issued by the compiler to copy blocks of
- * data around. This is really memmove() - it has to be able to deal with
- * possible overlaps, because that ambiguity is when the compiler gives up
- * and calls a function. We have our own, internal version so that we get
- * something we trust, even if the user has redefined the normal symbol.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *memcpy(void *dest, const void *src, size_t n);
- * R0 = To Address (dest) (leave unchanged to form result)
- * R1 = From Address (src)
- * R2 = count
- *
- * Note: Favours word alignment
- */
-
-#ifdef CONFIG_MEMCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_memcpy)
- CC = R2 <= 0; /* length not positive? */
- IF CC JUMP .L_P1L2147483647; /* Nothing to do */
-
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
- P2 = R2 ; /* length */
-
- /* check for overlapping data */
- CC = R1 < R0; /* src < dst */
- IF !CC JUMP .Lno_overlap;
- R3 = R1 + R2;
- CC = R0 < R3; /* and dst < src+len */
- IF CC JUMP .Lhas_overlap;
-
-.Lno_overlap:
- /* Check for aligned data.*/
-
- R3 = R1 | R0;
- R1 = 0x3;
- R3 = R3 & R1;
- CC = R3; /* low bits set on either address? */
- IF CC JUMP .Lnot_aligned;
-
- /* Both addresses are word-aligned, so we can copy
- at least part of the data using word copies.*/
- P2 = P2 >> 2;
- CC = P2 <= 2;
- IF !CC JUMP .Lmore_than_seven;
- /* less than eight bytes... */
- P2 = R2;
- LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
-.Lthree_start:
- R3 = B[P1++] (X);
-.Lthree_end:
- B[P0++] = R3;
-
- RTS;
-
-.Lmore_than_seven:
- /* There's@least eight bytes to copy. */
- P2 += -1; /* because we unroll one iteration */
- LSETUP(.Lword_loops, .Lword_loope) LC0=P2;
- I1 = P1;
- R3 = [I1++];
-#if ANOMALY_05000202
-.Lword_loops:
- [P0++] = R3;
-.Lword_loope:
- R3 = [I1++];
-#else
-.Lword_loops:
-.Lword_loope:
- MNOP || [P0++] = R3 || R3 = [I1++];
-#endif
- [P0++] = R3;
- /* Any remaining bytes to copy? */
- R3 = 0x3;
- R3 = R2 & R3;
- CC = R3 == 0;
- P1 = I1; /* in case there's something left, */
- IF !CC JUMP .Lbytes_left;
- RTS;
-.Lbytes_left: P2 = R3;
-.Lnot_aligned:
- /* From here, we're copying byte-by-byte. */
- LSETUP (.Lbyte_start, .Lbyte_end) LC0=P2;
-.Lbyte_start:
- R1 = B[P1++] (X);
-.Lbyte_end:
- B[P0++] = R1;
-
-.L_P1L2147483647:
- RTS;
-
-.Lhas_overlap:
- /* Need to reverse the copying, because the
- * dst would clobber the src.
- * Don't bother to work out alignment for
- * the reverse case.
- */
- P0 = P0 + P2;
- P0 += -1;
- P1 = P1 + P2;
- P1 += -1;
- LSETUP(.Lover_start, .Lover_end) LC0=P2;
-.Lover_start:
- R1 = B[P1--] (X);
-.Lover_end:
- B[P0--] = R1;
-
- RTS;
-
-ENDPROC(_memcpy)
diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S
deleted file mode 100644
index e0b7820..0000000
--- a/arch/blackfin/lib/memmove.S
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-/*
- * C Library function MEMMOVE
- * R0 = To Address (leave unchanged to form result)
- * R1 = From Address
- * R2 = count
- * Data may overlap
- */
-
-ENTRY(_memmove)
- I1 = P3;
- P0 = R0; /* P0 = To address */
- P3 = R1; /* P3 = From Address */
- P2 = R2; /* P2 = count */
- CC = P2 == 0; /* Check zero count*/
- IF CC JUMP .Lfinished; /* very unlikely */
-
- CC = R1 < R0 (IU); /* From < To */
- IF !CC JUMP .Lno_overlap;
- R3 = R1 + R2;
- CC = R0 <= R3 (IU); /* (From+len) >= To */
- IF CC JUMP .Loverlap;
-.Lno_overlap:
- R3 = 11;
- CC = R2 <= R3;
- IF CC JUMP .Lbytes;
- R3 = R1 | R0; /* OR addresses together */
- R3 <<= 30; /* check bottom two bits */
- CC = AZ; /* AZ set if zero.*/
- IF !CC JUMP .Lbytes; /* Jump if addrs not aligned.*/
-
- I0 = P3;
- P1 = P2 >> 2; /* count = n/4 */
- P1 += -1;
- R3 = 3;
- R2 = R2 & R3; /* remainder */
- P2 = R2; /* set remainder */
- R1 = [I0++];
-
- LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1;
-#if ANOMALY_05000202
-.Lquad_loops:
- [P0++] = R1;
-.Lquad_loope:
- R1 = [I0++];
-#else
-.Lquad_loops:
-.Lquad_loope:
- MNOP || [P0++] = R1 || R1 = [I0++];
-#endif
- [P0++] = R1;
-
- CC = P2 == 0; /* any remaining bytes? */
- P3 = I0; /* Amend P3 to updated ptr. */
- IF !CC JUMP .Lbytes;
- P3 = I1;
- RTS;
-
-.Lbytes: LSETUP (.Lbyte2_s, .Lbyte2_e) LC0=P2;
-.Lbyte2_s: R1 = B[P3++](Z);
-.Lbyte2_e: B[P0++] = R1;
-
-.Lfinished: P3 = I1;
- RTS;
-
-.Loverlap:
- P2 += -1;
- P0 = P0 + P2;
- P3 = P3 + P2;
- R1 = B[P3--] (Z);
- CC = P2 == 0;
- IF CC JUMP .Lno_loop;
-#if ANOMALY_05000245
- NOP;
- NOP;
-#endif
- LSETUP (.Lol_s, .Lol_e) LC0 = P2;
-.Lol_s: B[P0--] = R1;
-.Lol_e: R1 = B[P3--] (Z);
-.Lno_loop: B[P0] = R1;
- P3 = I1;
- RTS;
-
-ENDPROC(_memmove)
diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S
deleted file mode 100644
index cdcf914..0000000
--- a/arch/blackfin/lib/memset.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-#ifdef CONFIG_MEMSET_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/*
- * C Library function MEMSET
- * R0 = address (leave unchanged to form result)
- * R1 = filler byte
- * R2 = count
- * Favours word aligned data.
- * The strncpy assumes that I0 and I1 are not used in this function
- */
-
-ENTRY(_memset)
- P0 = R0 ; /* P0 = address */
- P2 = R2 ; /* P2 = count */
- R3 = R0 + R2; /* end */
- CC = R2 <= 7(IU);
- IF CC JUMP .Ltoo_small;
- R1 = R1.B (Z); /* R1 = fill char */
- R2 = 3;
- R2 = R0 & R2; /* addr bottom two bits */
- CC = R2 == 0; /* AZ set if zero. */
- IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */
-
-.Laligned:
- P1 = P2 >> 2; /* count = n/4 */
- R2 = R1 << 8; /* create quad filler */
- R2.L = R2.L + R1.L(NS);
- R2.H = R2.L + R1.H(NS);
- P2 = R3;
-
- LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
-.Lquad_loop:
- [P0++] = R2;
-
- CC = P0 == P2;
- IF !CC JUMP .Lbytes_left;
- RTS;
-
-.Lbytes_left:
- R2 = R3; /* end point */
- R3 = P0; /* current position */
- R2 = R2 - R3; /* bytes left */
- P2 = R2;
-
-.Ltoo_small:
- CC = P2 == 0; /* Check zero count */
- IF CC JUMP .Lfinished; /* Unusual */
-
-.Lbytes:
- LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
-.Lbyte_loop:
- B[P0++] = R1;
-
-.Lfinished:
- RTS;
-
-.Lforce_align:
- CC = BITTST (R0, 0); /* odd byte */
- R0 = 4;
- R0 = R0 - R2;
- P1 = R0;
- R0 = P0; /* Recover return address */
- IF !CC JUMP .Lskip1;
- B[P0++] = R1;
-.Lskip1:
- CC = R2 <= 2; /* 2 bytes */
- P2 -= P1; /* reduce count */
- IF !CC JUMP .Laligned;
- B[P0++] = R1;
- B[P0++] = R1;
- JUMP .Laligned;
-
-ENDPROC(_memset)
diff --git a/arch/blackfin/lib/modsi3.S b/arch/blackfin/lib/modsi3.S
deleted file mode 100644
index f7026ce..0000000
--- a/arch/blackfin/lib/modsi3.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This program computes 32 bit signed remainder. It calls div32 function
- * for quotient estimation.
- * Registers in: R0, R1 = Numerator/ Denominator
- * Registers out: R0 = Remainder
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.global ___modsi3;
-.type ___modsi3, STT_FUNC;
-.extern ___divsi3;
-.type ___divsi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___modsi3:
-
- CC=R0==0;
- IF CC JUMP .LRETURN_R0; /* Return 0, if numerator == 0 */
- CC=R1==0;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 0 */
- CC=R0==R1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if numerator == denominator */
- CC = R1 == 1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 1 */
- CC = R1 == -1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == -1 */
-
- /* Valid input. Use __divsi3() to compute the quotient, and then
- * derive the remainder from that. */
-
- [--SP] = (R7:6); /* Push R7 and R6 */
- [--SP] = RETS; /* and return address */
- R7 = R0; /* Copy of R0 */
- R6 = R1; /* Save for later */
- SP += -12; /* Should always provide this space */
- CALL ___divsi3; /* Compute signed quotient using ___divsi3()*/
- SP += 12;
- R0 *= R6; /* Quotient * divisor */
- R0 = R7 - R0; /* Dividend - (quotient * divisor) */
- RETS = [SP++]; /* Get back return address */
- (R7:6) = [SP++]; /* Pop registers R7 and R4 */
- RTS; /* Store remainder */
-
-.LRETURN_ZERO:
- R0 = 0;
-.LRETURN_R0:
- RTS;
-
-.size ___modsi3, .-___modsi3
diff --git a/arch/blackfin/lib/muldi3.S b/arch/blackfin/lib/muldi3.S
deleted file mode 100644
index abf9b2a..0000000
--- a/arch/blackfin/lib/muldi3.S
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___muldi3;
-.type ___muldi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/*
- R1:R0 * R3:R2
- = R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l
-[X] = (R1.h * R3.h) * 2^96
-[X] + (R1.h * R3.l + R1.l * R3.h) * 2^80
-[X] + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64
-[T1] + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48
-[T2] + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32
-[T3] + (R0.l * R2.h + R2.l * R0.h) * 2^16
-[T4] + (R0.l * R2.l)
-
- We can discard the first three lines marked "X" since we produce
- only a 64 bit result. So, we need ten 16-bit multiplies.
-
- Individual mul-acc results:
-[E1] = R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h
-[E2] = R1.l * R2.l + R3.l * R0.l + R0.h * R2.h
-[E3] = R0.l * R2.h + R2.l * R0.h
-[E4] = R0.l * R2.l
-
- We also need to add high parts from lower-level results to higher ones:
- E[n]c = E[n] + (E[n+1]c >> 16), where E4c := E4
-
- One interesting property is that all parts of the result that depend
- on the sign of the multiplication are discarded. Those would be the
- multiplications involving R1.h and R3.h, but only the top 16 bit of
- the 32 bit result depend on the sign, and since R1.h and R3.h only
- occur in E1, the top half of these results is cut off.
- So, we can just use FU mode for all of the 16-bit multiplies, and
- ignore questions of when to use mixed mode. */
-
-___muldi3:
- /* [SP] technically is part of the caller's frame, but we can
- use it as scratch space. */
- A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
- A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
- A0 += A1; /* E1 */
- R4 = A0.w;
- A0 = R0.l * R3.l (FU); /* E2 */
- A0 += R2.l * R1.l (FU); /* E2 */
-
- A1 = R2.L * R0.L (FU); /* E4 */
- R3 = A1.w;
- A1 = A1 >> 16; /* E3c */
- A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
- A1 += R0.L * R2.H (FU); /* E3c */
- R0 = A1.w;
- A1 = A1 >> 16; /* E2c */
- A0 += A1; /* E2c */
- R1 = A0.w;
-
- /* low(result) = low(E3c):low(E4) */
- R0 = PACK (R0.l, R3.l);
- /* high(result) = E2c + (E1 << 16) */
- R1.h = R1.h + R4.l (NS) || R4 = [SP];
- RTS;
-
-.size ___muldi3, .-___muldi3
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
deleted file mode 100644
index 06a5e67..0000000
--- a/arch/blackfin/lib/outs.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- * 2005 BuyWays BV
- * Bas Vermeulen <bas@buyways.nl>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-ENTRY(_outsl)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
-.Llong_loop_s: R0 = [P1++];
-.Llong_loop_e: [P0] = R0;
-1: RTS;
-ENDPROC(_outsl)
-
-ENTRY(_outsw)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
-.Lword_loop_s: R0 = W[P1++];
-.Lword_loop_e: W[P0] = R0;
-1: RTS;
-ENDPROC(_outsw)
-
-ENTRY(_outsb)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
-.Lbyte_loop_s: R0 = B[P1++];
-.Lbyte_loop_e: B[P0] = R0;
-1: RTS;
-ENDPROC(_outsb)
-
-ENTRY(_outsw_8)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
-.Lword8_loop_s: R1 = B[P1++];
- R0 = B[P1++];
- R0 = R0 << 8;
- R0 = R0 + R1;
-.Lword8_loop_e: W[P0] = R0;
-1: RTS;
-ENDPROC(_outsw_8)
diff --git a/arch/blackfin/lib/smulsi3_highpart.S b/arch/blackfin/lib/smulsi3_highpart.S
deleted file mode 100644
index e50d6c4..0000000
--- a/arch/blackfin/lib/smulsi3_highpart.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___smulsi3_highpart;
-.type ___smulsi3_highpart, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___smulsi3_highpart:
- R2 = R1.L * R0.L (FU);
- R3 = R1.H * R0.L (IS,M);
- R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);
-
- R1.L = R2.H + R1.L;
- cc = ac0;
- R2 = cc;
-
- R1.L = R1.L + R3.L;
- cc = ac0;
- R1 >>>= 16;
- R3 >>>= 16;
- R1 = R1 + R3;
- R1 = R1 + R2;
- R2 = cc;
- R1 = R1 + R2;
-
- R0 = R0 + R1;
- RTS;
-
-.size ___smulsi3_highpart, .-___smulsi3_highpart
diff --git a/arch/blackfin/lib/strcmp.S b/arch/blackfin/lib/strcmp.S
deleted file mode 100644
index 9c8b986..0000000
--- a/arch/blackfin/lib/strcmp.S
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strcmp(char *s1, const char *s2);
- * R0 = address (s1)
- * R1 = address (s2)
- *
- * Returns an integer less than, equal to, or greater than zero if s1
- * (or the first n bytes thereof) is found, respectively, to be less
- * than, to match, or be greater than s2.
- */
-
-#ifdef CONFIG_STRCMP_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strcmp)
- P0 = R0 ; /* s1 */
- P1 = R1 ; /* s2 */
-
-1:
- R0 = B[P0++] (Z); /* get *s1 */
- R1 = B[P1++] (Z); /* get *s2 */
- CC = R0 == R1; /* compare a byte */
- if ! cc jump 2f; /* not equal, break out */
- CC = R0; /* at end of s1? */
- if cc jump 1b (bp); /* no, keep going */
- jump.s 3f; /* strings are equal */
-2:
- R0 = R0 - R1; /* *s1 - *s2 */
-3:
- RTS;
-
-ENDPROC(_strcmp)
diff --git a/arch/blackfin/lib/strcpy.S b/arch/blackfin/lib/strcpy.S
deleted file mode 100644
index 9495aa7..0000000
--- a/arch/blackfin/lib/strcpy.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strcpy(char *dest, const char *src);
- * R0 = address (dest)
- * R1 = address (src)
- *
- * Returns a pointer to the destination string dest
- */
-
-#ifdef CONFIG_STRCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strcpy)
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
-
-1:
- R1 = B [P1++] (Z);
- B [P0++] = R1;
- CC = R1;
- if cc jump 1b (bp);
- RTS;
-
-ENDPROC(_strcpy)
diff --git a/arch/blackfin/lib/strncmp.S b/arch/blackfin/lib/strncmp.S
deleted file mode 100644
index 3bfaedc..0000000
--- a/arch/blackfin/lib/strncmp.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strncpy(char *s1, const char *s2, size_t n);
- * R0 = address (dest)
- * R1 = address (src)
- * R2 = size (n)
- * Returns a pointer to the destination string dest
- */
-
-#ifdef CONFIG_STRNCMP_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strncmp)
- CC = R2 == 0;
- if CC JUMP 5f;
-
- P0 = R0 ; /* s1 */
- P1 = R1 ; /* s2 */
-1:
- R0 = B[P0++] (Z); /* get *s1 */
- R1 = B[P1++] (Z); /* get *s2 */
- CC = R0 == R1; /* compare a byte */
- if ! cc jump 3f; /* not equal, break out */
- CC = R0; /* at end of s1? */
- if ! cc jump 4f; /* yes, all done */
- R2 += -1; /* no, adjust count */
- CC = R2 == 0;
- if ! cc jump 1b (bp); /* more to do, keep going */
-2:
- R0 = 0; /* strings are equal */
- jump.s 4f;
-3:
- R0 = R0 - R1; /* *s1 - *s2 */
-4:
- RTS;
-
-5:
- R0 = 0;
- RTS;
-
-ENDPROC(_strncmp)
diff --git a/arch/blackfin/lib/strncpy.S b/arch/blackfin/lib/strncpy.S
deleted file mode 100644
index 92fd182..0000000
--- a/arch/blackfin/lib/strncpy.S
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-#include <asm/context.S>
-
-/* void *strncpy(char *dest, const char *src, size_t n);
- * R0 = address (dest)
- * R1 = address (src)
- * R2 = size
- * Returns a pointer (R0) to the destination string dest
- * we do this by not changing R0
- */
-
-#ifdef CONFIG_STRNCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strncpy)
- CC = R2 == 0;
- if CC JUMP 6f;
-
- P2 = R2 ; /* size */
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
-
- LSETUP (1f, 2f) LC0 = P2;
-1:
- R1 = B [P1++] (Z);
- B [P0++] = R1;
- CC = R1 == 0;
-2:
- if CC jump 3f;
-
- RTS;
-
- /* if src is shorter than n, we need to null pad bytes in dest
- * but, we can get here when the last byte is zero, and we don't
- * want to copy an extra byte at the end, so we need to check
- */
-3:
- R2 = LC0;
- CC = R2
- if ! CC jump 6f;
-
- /* if the required null padded portion is small, do it here, rather than
- * handling the overhead of memset (which is OK when things are big).
- */
- R3 = 0x20;
- CC = R2 < R3;
- IF CC jump 4f;
-
- R2 += -1;
-
- /* Set things up for memset
- * R0 = address
- * R1 = filler byte (this case it's zero, set above)
- * R2 = count (set above)
- */
-
- I1 = R0;
- R0 = RETS;
- I0 = R0;
- R0 = P0;
- pseudo_long_call _memset, p0;
- R0 = I0;
- RETS = R0;
- R0 = I1;
- RTS;
-
-4:
- LSETUP(5f, 5f) LC0;
-5:
- B [P0++] = R1;
-6:
- RTS;
-
-ENDPROC(_strncpy)
diff --git a/arch/blackfin/lib/udivsi3.S b/arch/blackfin/lib/udivsi3.S
deleted file mode 100644
index 90bfa80..0000000
--- a/arch/blackfin/lib/udivsi3.S
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-#define CARRY AC0
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-
-ENTRY(___udivsi3)
-
- CC = R0 < R1 (IU); /* If X < Y, always return 0 */
- IF CC JUMP .Lreturn_ident;
-
- R2 = R1 << 16;
- CC = R2 <= R0 (IU);
- IF CC JUMP .Lidents;
-
- R2 = R0 >> 31; /* if X is a 31-bit number */
- R3 = R1 >> 15; /* and Y is a 15-bit number */
- R2 = R2 | R3; /* then it's okay to use the DIVQ builtins (fallthrough to fast)*/
- CC = R2;
- IF CC JUMP .Ly_16bit;
-
-/* METHOD 1: FAST DIVQ
- We know we have a 31-bit dividend, and 15-bit divisor so we can use the
- simple divq approach (first setting AQ to 0 - implying unsigned division,
- then 16 DIVQ's).
-*/
-
- AQ = CC; /* Clear AQ (CC==0) */
-
-/* ISR States: When dividing two integers (32.0/16.0) using divide primitives,
- we need to shift the dividend one bit to the left.
- We have already checked that we have a 31-bit number so we are safe to do
- that.
-*/
- R0 <<= 1;
- DIVQ(R0, R1); // 1
- DIVQ(R0, R1); // 2
- DIVQ(R0, R1); // 3
- DIVQ(R0, R1); // 4
- DIVQ(R0, R1); // 5
- DIVQ(R0, R1); // 6
- DIVQ(R0, R1); // 7
- DIVQ(R0, R1); // 8
- DIVQ(R0, R1); // 9
- DIVQ(R0, R1); // 10
- DIVQ(R0, R1); // 11
- DIVQ(R0, R1); // 12
- DIVQ(R0, R1); // 13
- DIVQ(R0, R1); // 14
- DIVQ(R0, R1); // 15
- DIVQ(R0, R1); // 16
- R0 = R0.L (Z);
- RTS;
-
-.Ly_16bit:
- /* We know that the upper 17 bits of Y might have bits set,
- ** or that the sign bit of X might have a bit. If Y is a
- ** 16-bit number, but not bigger, then we can use the builtins
- ** with a post-divide correction.
- ** R3 currently holds Y>>15, which means R3's LSB is the
- ** bit we're interested in.
- */
-
- /* According to the ISR, to use the Divide primitives for
- ** unsigned integer divide, the useable range is 31 bits
- */
- CC = ! BITTST(R0, 31);
-
- /* IF condition is true we can scale our inputs and use the divide primitives,
- ** with some post-adjustment
- */
- R3 += -1; /* if so, Y is 0x00008nnn */
- CC &= AZ;
-
- /* If condition is true we can scale our inputs and use the divide primitives,
- ** with some post-adjustment
- */
- R3 = R1 >> 1; /* Pre-scaled divisor for primitive case */
- R2 = R0 >> 16;
-
- R2 = R3 - R2; /* shifted divisor < upper 16 bits of dividend */
- CC &= CARRY;
- IF CC JUMP .Lshift_and_correct;
-
- /* Fall through to the identities */
-
-/* METHOD 2: identities and manual calculation
- We are not able to use the divide primites, but may still catch some special
- cases.
-*/
-.Lidents:
- /* Test for common identities. Value to be returned is placed in R2. */
- CC = R0 == 0; /* 0/Y => 0 */
- IF CC JUMP .Lreturn_r0;
- CC = R0 == R1; /* X==Y => 1 */
- IF CC JUMP .Lreturn_ident;
- CC = R1 == 1; /* X/1 => X */
- IF CC JUMP .Lreturn_ident;
-
- R2.L = ONES R1;
- R2 = R2.L (Z);
- CC = R2 == 1;
- IF CC JUMP .Lpower_of_two;
-
- [--SP] = (R7:5); /* Push registers R5-R7 */
-
- /* Idents don't match. Go for the full operation. */
-
-
- R6 = 2; /* assume we'll shift two */
- R3 = 1;
-
- P2 = R1;
- /* If either R0 or R1 have sign set, */
- /* divide them by two, and note it's */
- /* been done. */
- CC = R1 < 0;
- R2 = R1 >> 1;
- IF CC R1 = R2; /* Possibly-shifted R1 */
- IF !CC R6 = R3; /* R1 doesn't, so at most 1 shifted */
-
- P0 = 0;
- R3 = -R1;
- [--SP] = R3;
- R2 = R0 >> 1;
- R2 = R0 >> 1;
- CC = R0 < 0;
- IF CC P0 = R6; /* Number of values divided */
- IF !CC R2 = R0; /* Shifted R0 */
-
- /* P0 is 0, 1 (NR/=2) or 2 (NR/=2, DR/=2) */
-
- /* r2 holds Copy dividend */
- R3 = 0; /* Clear partial remainder */
- R7 = 0; /* Initialise quotient bit */
-
- P1 = 32; /* Set loop counter */
- LSETUP(.Lulst, .Lulend) LC0 = P1; /* Set loop counter */
-.Lulst: R6 = R2 >> 31; /* R6 = sign bit of R2, for carry */
- R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */
- R3 = R3 << 1 || R5 = [SP];
- R3 = R3 | R6; /* Include any carry */
- CC = R7 < 0; /* Check quotient(AQ) */
- /* If AQ==0, we'll sub divisor */
- IF CC R5 = R1; /* and if AQ==1, we'll add it. */
- R3 = R3 + R5; /* Add/sub divisor to partial remainder */
- R7 = R3 ^ R1; /* Generate next quotient bit */
-
- R5 = R7 >> 31; /* Get AQ */
- BITTGL(R5, 0); /* Invert it, to get what we'll shift */
-.Lulend: R2 = R2 + R5; /* and "shift" it in. */
-
- CC = P0 == 0; /* Check how many inputs we shifted */
- IF CC JUMP .Lno_mult; /* if none... */
- R6 = R2 << 1;
- CC = P0 == 1;
- IF CC R2 = R6; /* if 1, Q = Q*2 */
- IF !CC R1 = P2; /* if 2, restore stored divisor */
-
- R3 = R2; /* Copy of R2 */
- R3 *= R1; /* Q * divisor */
- R5 = R0 - R3; /* Z = (dividend - Q * divisor) */
- CC = R1 <= R5 (IU); /* Check if divisor <= Z? */
- R6 = CC; /* if yes, R6 = 1 */
- R2 = R2 + R6; /* if yes, add one to quotient(Q) */
-.Lno_mult:
- SP += 4;
- (R7:5) = [SP++]; /* Pop registers R5-R7 */
- R0 = R2; /* Store quotient */
- RTS;
-
-.Lreturn_ident:
- CC = R0 < R1 (IU); /* If X < Y, always return 0 */
- R2 = 0;
- IF CC JUMP .Ltrue_return_ident;
- R2 = -1 (X); /* X/0 => 0xFFFFFFFF */
- CC = R1 == 0;
- IF CC JUMP .Ltrue_return_ident;
- R2 = -R2; /* R2 now 1 */
- CC = R0 == R1; /* X==Y => 1 */
- IF CC JUMP .Ltrue_return_ident;
- R2 = R0; /* X/1 => X */
- /*FALLTHRU*/
-
-.Ltrue_return_ident:
- R0 = R2;
-.Lreturn_r0:
- RTS;
-
-.Lpower_of_two:
- /* Y has a single bit set, which means it's a power of two.
- ** That means we can perform the division just by shifting
- ** X to the right the appropriate number of bits
- */
-
- /* signbits returns the number of sign bits, minus one.
- ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need
- ** to shift right n-signbits spaces. It also means 0x80000000
- ** is a special case, because that *also* gives a signbits of 0
- */
-
- R2 = R0 >> 31;
- CC = R1 < 0;
- IF CC JUMP .Ltrue_return_ident;
-
- R1.l = SIGNBITS R1;
- R1 = R1.L (Z);
- R1 += -30;
- R0 = LSHIFT R0 by R1.L;
- RTS;
-
-/* METHOD 3: PRESCALE AND USE THE DIVIDE PRIMITIVES WITH SOME POST-CORRECTION
- Two scaling operations are required to use the divide primitives with a
- divisor > 0x7FFFF.
- Firstly (as in method 1) we need to shift the dividend 1 to the left for
- integer division.
- Secondly we need to shift both the divisor and dividend 1 to the right so
- both are in range for the primitives.
- The left/right shift of the dividend does nothing so we can skip it.
-*/
-.Lshift_and_correct:
- R2 = R0;
- // R3 is already R1 >> 1
- CC=!CC;
- AQ = CC; /* Clear AQ, got here with CC = 0 */
- DIVQ(R2, R3); // 1
- DIVQ(R2, R3); // 2
- DIVQ(R2, R3); // 3
- DIVQ(R2, R3); // 4
- DIVQ(R2, R3); // 5
- DIVQ(R2, R3); // 6
- DIVQ(R2, R3); // 7
- DIVQ(R2, R3); // 8
- DIVQ(R2, R3); // 9
- DIVQ(R2, R3); // 10
- DIVQ(R2, R3); // 11
- DIVQ(R2, R3); // 12
- DIVQ(R2, R3); // 13
- DIVQ(R2, R3); // 14
- DIVQ(R2, R3); // 15
- DIVQ(R2, R3); // 16
-
- /* According to the Instruction Set Reference:
- To divide by a divisor > 0x7FFF,
- 1. prescale and perform divide to obtain quotient (Q) (done above),
- 2. multiply quotient by unscaled divisor (result M)
- 3. subtract the product from the divident to get an error (E = X - M)
- 4. if E < divisor (Y) subtract 1, if E > divisor (Y) add 1, else return quotient (Q)
- */
- R3 = R2.L (Z); /* Q = X' / Y' */
- R2 = R3; /* Preserve Q */
- R2 *= R1; /* M = Q * Y */
- R2 = R0 - R2; /* E = X - M */
- R0 = R3; /* Copy Q into result reg */
-
-/* Correction: If result of the multiply is negative, we overflowed
- and need to correct the result by subtracting 1 from the result.*/
- R3 = 0xFFFF (Z);
- R2 = R2 >> 16; /* E >> 16 */
- CC = R2 == R3;
- R3 = 1 ;
- R1 = R0 - R3;
- IF CC R0 = R1;
- RTS;
-
-ENDPROC(___udivsi3)
diff --git a/arch/blackfin/lib/umodsi3.S b/arch/blackfin/lib/umodsi3.S
deleted file mode 100644
index 3794c00..0000000
--- a/arch/blackfin/lib/umodsi3.S
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * libgcc1 routines for Blackfin 5xx
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.extern ___udivsi3;
-.type ___udivsi3, STT_FUNC;
-.globl ___umodsi3
-.type ___umodsi3, STT_FUNC;
-___umodsi3:
-
- CC=R0==0;
- IF CC JUMP .LRETURN_R0; /* Return 0, if NR == 0 */
- CC= R1==0;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 0 */
- CC=R0==R1;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if NR == DR */
- CC = R1 == 1;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 1 */
- CC = R0<R1 (IU);
- IF CC JUMP .LRETURN_R0; /* Return dividend (R0),IF NR<DR */
-
- [--SP] = (R7:6); /* Push registers and */
- [--SP] = RETS; /* Return address */
- R7 = R0; /* Copy of R0 */
- R6 = R1;
- SP += -12; /* Should always provide this space */
- CALL ___udivsi3; /* Compute unsigned quotient using ___udiv32()*/
- SP += 12;
- R0 *= R6; /* Quotient * divisor */
- R0 = R7 - R0; /* Dividend - (quotient * divisor) */
- RETS = [SP++]; /* Pop return address */
- ( R7:6) = [SP++]; /* And registers */
- RTS; /* Return remainder */
-.LRETURN_ZERO_VAL:
- R0 = 0;
-.LRETURN_R0:
- RTS;
-
-.size ___umodsi3, .-___umodsi3
diff --git a/arch/blackfin/lib/umulsi3_highpart.S b/arch/blackfin/lib/umulsi3_highpart.S
deleted file mode 100644
index 0dcace9..0000000
--- a/arch/blackfin/lib/umulsi3_highpart.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___umulsi3_highpart;
-.type ___umulsi3_highpart, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___umulsi3_highpart:
- R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
- R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU);
- R0 >>= 16;
- /* Unsigned multiplication has the nice property that we can
- ignore carry on this first addition. */
- R0 = R0 + R3;
- R0 = R0 + R1;
- cc = ac0;
- R1 = cc;
- R1 = PACK(R1.l,R0.h);
- R0 = R1 + R2;
- RTS;
-
-.size ___umulsi3_highpart, .-___umulsi3_highpart
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
deleted file mode 100644
index 4731f6b..0000000
--- a/arch/blackfin/mach-bf518/Kconfig
+++ /dev/null
@@ -1,320 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF51x
- def_bool y
- depends on (BF512 || BF514 || BF516 || BF518)
-
-if (BF51x)
-
-source "arch/blackfin/mach-bf518/boards/Kconfig"
-
-menu "BF518 Specific Configuration"
-
-comment "Alternative Multiplexing Scheme"
-
-choice
- prompt "PWM Channel Pins"
- default BF518_PWM_ALL_PORTF
- help
- Select pins used for the PWM channels:
- PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_ALL_PORTF
- bool "PF1 - PF6"
- help
- PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL}
-
-config BF518_PWM_PORTF_PORTG
- bool "PF11 - PF14 / PG1 - PG2"
- help
- PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL}
- PG{1,2} <-> PWM_{CH,CL}
-
-endchoice
-
-choice
- prompt "PWM Sync Pin"
- default BF518_PWM_SYNC_PF7
- help
- Select the pin used for PWM_SYNC.
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_SYNC_PF7
- bool "PF7"
-config BF518_PWM_SYNC_PF15
- bool "PF15"
-endchoice
-
-choice
- prompt "PWM Trip B Pin"
- default BF518_PWM_TRIPB_PG10
- help
- Select the pin used for PWM_TRIPB.
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_TRIPB_PG10
- bool "PG10"
-config BF518_PWM_TRIPB_PG14
- bool "PG14"
-endchoice
-
-choice
- prompt "PPI / Timer Pins"
- default BF518_PPI_TMR_PG5
- help
- Select pins used for PPI/Timer:
- PPICLK PPIFS1 PPIFS2
- TMRCLK TMR0 TMR1
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PPI_TMR_PG5
- bool "PG5 - PG7"
- help
- PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
-
-config BF518_PPI_TMR_PG12
- bool "PG12 - PG14"
- help
- PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
-
-endchoice
-
-comment "Hysteresis/Schmitt Trigger Control"
-config BFIN_HYSTERESIS_CONTROL
- bool "Enable Hysteresis Control"
- help
- The ADSP-BF51x allows to control input hysteresis for Port F,
- Port G and Port H and other processor signal inputs.
- The Schmitt trigger enables can be set only for pin groups.
- Saying Y will overwrite the default reset or boot loader
- initialization.
-
-menu "PORT F"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTF_0_7
- bool "Enable Hysteresis on PORTF {0...7}"
-config GPIO_HYST_PORTF_8_9
- bool "Enable Hysteresis on PORTF {8, 9}"
-config GPIO_HYST_PORTF_10
- bool "Enable Hysteresis on PORTF 10"
-config GPIO_HYST_PORTF_11
- bool "Enable Hysteresis on PORTF 11"
-config GPIO_HYST_PORTF_12_13
- bool "Enable Hysteresis on PORTF {12, 13}"
-config GPIO_HYST_PORTF_14_15
- bool "Enable Hysteresis on PORTF {14, 15}"
-endmenu
-
-menu "PORT G"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTG_0
- bool "Enable Hysteresis on PORTG 0"
-config GPIO_HYST_PORTG_1_4
- bool "Enable Hysteresis on PORTG {1...4}"
-config GPIO_HYST_PORTG_5_6
- bool "Enable Hysteresis on PORTG {5, 6}"
-config GPIO_HYST_PORTG_7_8
- bool "Enable Hysteresis on PORTG {7, 8}"
-config GPIO_HYST_PORTG_9
- bool "Enable Hysteresis on PORTG 9"
-config GPIO_HYST_PORTG_10
- bool "Enable Hysteresis on PORTG 10"
-config GPIO_HYST_PORTG_11_13
- bool "Enable Hysteresis on PORTG {11...13}"
-config GPIO_HYST_PORTG_14_15
- bool "Enable Hysteresis on PORTG {14, 15}"
-endmenu
-
-menu "PORT H"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTH_0_7
- bool "Enable Hysteresis on PORTH {0...7}"
-
-endmenu
-
-menu "None-GPIO"
- depends on BFIN_HYSTERESIS_CONTROL
-config NONEGPIO_HYST_NMI_RST_BMODE
- bool "Enable Hysteresis on {NMI, RESET, BMODE}"
-config NONEGPIO_HYST_JTAG
- bool "Enable Hysteresis on JTAG"
-endmenu
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_DMAR0_BLK
- int "IRQ_DMAR0_BLK"
- default 7
-config IRQ_DMAR1_BLK
- int "IRQ_DMAR1_BLK"
- default 7
-config IRQ_DMAR0_OVR
- int "IRQ_DMAR0_OVR"
- default 7
-config IRQ_DMAR1_OVR
- int "IRQ_DMAR1_OVR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_MAC_ERROR
- int "IRQ_MAC_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_PTP_ERROR
- int "IRQ_PTP_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI0
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_OPTSEC
- int "IRQ_OPTSEC"
- default 11
-config IRQ_CNT
- int "IRQ_CNT"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_PORTH_INTA
- int "IRQ_PORTH_INTA"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX/NFC"
- default 11
-config IRQ_PORTH_INTB
- int "IRQ_PORTH_INTB"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PORTG_INTA
- int "IRQ_PORTG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 13
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 13
-config IRQ_SPI0_ERROR
- int "IRQ_SPI0_ERROR"
- default 7
-config IRQ_SPI1_ERROR
- int "IRQ_SPI1_ERROR"
- default 7
-config IRQ_RSI_INT0
- int "IRQ_RSI_INT0"
- default 7
-config IRQ_RSI_INT1
- int "IRQ_RSI_INT1"
- default 7
-config IRQ_PWM_TRIP
- int "IRQ_PWM_TRIP"
- default 10
-config IRQ_PWM_SYNC
- int "IRQ_PWM_SYNC"
- default 10
-config IRQ_PTP_STAT
- int "IRQ_PTP_STAT"
- default 10
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf518/Makefile b/arch/blackfin/mach-bf518/Makefile
deleted file mode 100644
index 168a193..0000000
--- a/arch/blackfin/mach-bf518/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf518/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf518/boards/Kconfig b/arch/blackfin/mach-bf518/boards/Kconfig
deleted file mode 100644
index f7b93b9..0000000
--- a/arch/blackfin/mach-bf518/boards/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN518F_EZBRD
- help
- Select your board!
-
-config BFIN518F_EZBRD
- bool "BF518F-EZBRD"
- help
- BF518-EZBRD board support.
-
-config BFIN518F_TCM
- bool "Bluetechnix TCM-BF518"
- help
- Bluetechnix TCM-BF518 board support.
-
-endchoice
diff --git a/arch/blackfin/mach-bf518/boards/Makefile b/arch/blackfin/mach-bf518/boards/Makefile
deleted file mode 100644
index a9ef25c..0000000
--- a/arch/blackfin/mach-bf518/boards/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# arch/blackfin/mach-bf518/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN518F_EZBRD) += ezbrd.o
-obj-$(CONFIG_BFIN518F_TCM) += tcm-bf518.o
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
deleted file mode 100644
index c51d1b8..0000000
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ /dev/null
@@ -1,794 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sdh.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF518F-EZBRD";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezbrd_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezbrd_flash_data = {
- .width = 2,
- .parts = ezbrd_partitions,
- .nr_parts = ARRAY_SIZE(ezbrd_partitions),
-};
-
-static struct resource ezbrd_flash_resource = {
- .start = 0x20000000,
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- .end = 0x202fffff,
-#else
- .end = 0x203fffff,
-#endif
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezbrd_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezbrd_flash_data,
- },
- .num_resources = 1,
- .resource = &ezbrd_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = {
- P_MII0_ETxD0,
- P_MII0_ETxD1,
- P_MII0_ETxEN,
- P_MII0_ERxD0,
- P_MII0_ERxD1,
- P_MII0_TxCLK,
- P_MII0_PHYINT,
- P_MII0_CRS,
- P_MII0_MDC,
- P_MII0_MDIO,
- 0
-};
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
- .vlan1_mask = 1,
- .vlan2_mask = 2,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-/* SPI controller data */
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-
-/* SPI (1) */
-static struct bfin5xx_spi_master bfin_spi1_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi1_device = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bfin_spi1_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bf51x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
- &bfin_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf51x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezbrd_flash_device,
-#endif
-};
-
-static int __init ezbrd_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
- peripheral_request(P_AMS2, "ParaFlash");
-#if !IS_ENABLED(CONFIG_SPI_BFIN5XX)
- peripheral_request(P_AMS3, "ParaFlash");
-#endif
- return 0;
-}
-
-arch_initcall(ezbrd_init);
-
-static struct platform_device *ezbrd_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezbrd_early_devices,
- ARRAY_SIZE(ezbrd_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
deleted file mode 100644
index 37d8680..0000000
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ /dev/null
@@ -1,739 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sdh.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix TCM-BF518";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition tcm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- },
- {
- .name = "linux(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data tcm_flash_data = {
- .width = 2,
- .parts = tcm_partitions,
- .nr_parts = ARRAY_SIZE(tcm_partitions),
-};
-
-static struct resource tcm_flash_resource = {
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device tcm_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &tcm_flash_data,
- },
- .num_resources = 1,
- .resource = &tcm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* SPI0_SSEL2 */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-/* SPI controller data */
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-
-/* SPI (1) */
-static struct bfin5xx_spi_master bfin_spi1_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi1_device = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bfin_spi1_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bf51x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *tcm_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
- &bfin_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf51x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &tcm_flash_device,
-#endif
-};
-
-static int __init tcm_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(tcm_devices, ARRAY_SIZE(tcm_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(tcm_init);
-
-static struct platform_device *tcm_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tcm_early_devices,
- ARRAY_SIZE(tcm_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c
deleted file mode 100644
index bcd1fbc..0000000
--- a/arch/blackfin/mach-bf518/dma.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
deleted file mode 100644
index 46cb882..0000000
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF518 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
-/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
-#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* Incorrect L1 Instruction Bank B Memory Map Location */
-#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-/* PWM_TRIPB Signal Not Available on PG10 */
-#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
-/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
-#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem@Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (0)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bf518.h b/arch/blackfin/mach-bf518/include/mach/bf518.h
deleted file mode 100644
index 6906dee..0000000
--- a/arch/blackfin/mach-bf518/include/mach/bf518.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF518_H__
-#define __MACH_BF518_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-/**************************** Hysteresis Settings ****************************/
-
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-#ifdef CONFIG_GPIO_HYST_PORTF_0_7
-#define HYST_PORTF_0_7 (1 << 0)
-#else
-#define HYST_PORTF_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_8_9
-#define HYST_PORTF_8_9 (1 << 2)
-#else
-#define HYST_PORTF_8_9 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_10
-#define HYST_PORTF_10 (1 << 4)
-#else
-#define HYST_PORTF_10 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_11
-#define HYST_PORTF_11 (1 << 6)
-#else
-#define HYST_PORTF_11 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_12_13
-#define HYST_PORTF_12_13 (1 << 8)
-#else
-#define HYST_PORTF_12_13 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_14_15
-#define HYST_PORTF_14_15 (1 << 10)
-#else
-#define HYST_PORTF_14_15 (0 << 10)
-#endif
-
-#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
- HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTG_0
-#define HYST_PORTG_0 (1 << 0)
-#else
-#define HYST_PORTG_0 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_1_4
-#define HYST_PORTG_1_4 (1 << 2)
-#else
-#define HYST_PORTG_1_4 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_5_6
-#define HYST_PORTG_5_6 (1 << 4)
-#else
-#define HYST_PORTG_5_6 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_7_8
-#define HYST_PORTG_7_8 (1 << 6)
-#else
-#define HYST_PORTG_7_8 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_9
-#define HYST_PORTG_9 (1 << 8)
-#else
-#define HYST_PORTG_9 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_10
-#define HYST_PORTG_10 (1 << 10)
-#else
-#define HYST_PORTG_10 (0 << 10)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_11_13
-#define HYST_PORTG_11_13 (1 << 12)
-#else
-#define HYST_PORTG_11_13 (0 << 12)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_14_15
-#define HYST_PORTG_14_15 (1 << 14)
-#else
-#define HYST_PORTG_14_15 (0 << 14)
-#endif
-
-#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
- HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
- HYST_PORTG_11_13 | HYST_PORTG_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTH_0_7
-#define HYST_PORTH_0_7 (1 << 0)
-#else
-#define HYST_PORTH_0_7 (0 << 0)
-#endif
-
-#define HYST_PORTH_0_15 (HYST_PORTH_0_7)
-
-#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
-#define HYST_NMI_RST_BMODE (1 << 2)
-#else
-#define HYST_NMI_RST_BMODE (0 << 2)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_JTAG
-#define HYST_JTAG (1 << 4)
-#else
-#define HYST_JTAG (0 << 4)
-#endif
-
-#define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG)
-#define HYST_NONEGPIO_MASK (0x3C)
-#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
-
-#ifdef CONFIG_BF518
-#define CPU "BF518"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF516
-#define CPU "BF516"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF514
-#define CPU "BF514"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF512
-#define CPU "BF512"
-#define CPUID 0x27e8
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF518_H__ */
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
deleted file mode 100644
index 00c603f..0000000
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
deleted file mode 100644
index a882886..0000000
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf518.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF512
-# include "defBF512.h"
-#endif
-#ifdef CONFIG_BF514
-# include "defBF514.h"
-#endif
-#ifdef CONFIG_BF516
-# include "defBF516.h"
-#endif
-#ifdef CONFIG_BF518
-# include "defBF518.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF512
-# include "cdefBF512.h"
-# endif
-# ifdef CONFIG_BF514
-# include "cdefBF514.h"
-# endif
-# ifdef CONFIG_BF516
-# include "cdefBF516.h"
-# endif
-# ifdef CONFIG_BF518
-# include "cdefBF518.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
deleted file mode 100644
index 1c03ad4..0000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ /dev/null
@@ -1,1043 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF512_H
-#define _CDEF_BF512_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
-#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-#endif /* _CDEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
deleted file mode 100644
index 861221d..0000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF514_H
-#define _CDEF_BF514_H
-
-/* BF514 is BF512 + RSI */
-#include "cdefBF512.h"
-
-/* Removable Storage Interface Registers */
-
-#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
-#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
-#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
-#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
-#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
-#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
-#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
-#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
-
-#endif /* _CDEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
deleted file mode 100644
index cc9bf0d..0000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF516_H
-#define _CDEF_BF516_H
-
-/* BF516 is BF514 + EMAC */
-#include "cdefBF514.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* _CDEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
deleted file mode 100644
index 96a82fd..0000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF518_H
-#define _CDEF_BF518_H
-
-/* BF518 is BF516 + IEEE-1588 */
-#include "cdefBF516.h"
-
-/* PTP TSYNC Registers */
-
-#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL)
-#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
-#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE)
-#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
-#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT)
-#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
-#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF)
-#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
-#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1)
-#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
-#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2)
-#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val)
-#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3)
-#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val)
-#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND)
-#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
-#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR)
-#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val)
-#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET)
-#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
-#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO)
-#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
-#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI)
-#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
-#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO)
-#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI)
-#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO)
-#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI)
-#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO)
-#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
-#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI)
-#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
-#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF)
-#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
-#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP)
-#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
-#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI)
-#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
-#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
-#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
-
-#endif /* _CDEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
deleted file mode 100644
index e6a017f..0000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF512_H
-#define _DEF_BF512_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */
-/* ************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Device ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI0_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI0_STAT 0xFFC00508 /* SPI Status register */
-#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */
-#define SPI1_REGBASE 0xFFC03400
-#define SPI1_CTL 0xFFC03400 /* SPI Control Register */
-#define SPI1_FLG 0xFFC03404 /* SPI Flag register */
-#define SPI1_STAT 0xFFC03408 /* SPI Status register */
-#define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */
-#define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
-#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-
-#if 0
-#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
-
-#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
-#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
-#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
-#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
-#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
-
-#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
-#define IRQ_TWI 0x00000200 /* TWI Interrupt */
-#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
-#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
-#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
-#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
-#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
-#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
-
-#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
-#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
-#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
-#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
-#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
-#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
-#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
-#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
-#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
-#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
-
-#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
-#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
-#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
-#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
-#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
-#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
-#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
-#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
-#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
-#endif
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
-#define HOST_STATUS 0xffc03404 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc03500 /* Configuration Register */
-#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc03508 /* Status Register */
-#define CNT_COMMAND 0xffc0350c /* Command Register */
-#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
-#define CNT_COUNTER 0xffc03514 /* Counter Register */
-#define CNT_MAX 0xffc03518 /* Maximal Count Register */
-#define CNT_MIN 0xffc0351c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc03624 /* Secure Control */
-#define SECURE_STATUS 0xffc03628 /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Motor Control PWM Registers */
-
-#define PWM_CTRL 0xffc03700 /* PWM Control Register */
-#define PWM_STAT 0xffc03704 /* PWM Status Register */
-#define PWM_TM 0xffc03708 /* PWM Period Register */
-#define PWM_DT 0xffc0370c /* PWM Dead Time Register */
-#define PWM_GATE 0xffc03710 /* PWM Chopping Control */
-#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */
-#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */
-#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */
-#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */
-#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
-#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */
-#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */
-#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */
-#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */
-#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
-#define HOST_CNTR_nHOST_EN 0x0
-#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
-#define HOST_CNTR_nHOST_END 0x0
-#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
-#define HOST_CNTR_nDATA_SIZE 0x0
-#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
-#define HOST_CNTR_nHOST_RST 0x0
-#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
-#define HOST_CNTR_nHRDY_OVR 0x0
-#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
-#define HOST_CNTR_nINT_MODE 0x0
-#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
-#define HOST_CNTR_ nBT_EN 0x0
-#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
-#define HOST_CNTR_nEHW 0x0
-#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
-#define HOST_CNTR_nEHR 0x0
-#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
-#define HOST_CNTR_nBDR 0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define HOST_STAT_READY 0x1 /* DMA Ready */
-#define HOST_STAT_nREADY 0x0
-#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
-#define HOST_STAT_nFIFOFULL 0x0
-#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
-#define HOST_STAT_nFIFOEMPTY 0x0
-#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
-#define HOST_STAT_nCOMPLETE 0x0
-#define HOST_STAT_HSHK 0x10 /* Host Handshake */
-#define HOST_STAT_nHSHK 0x0
-#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
-#define HOST_STAT_nTIMEOUT 0x0
-#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
-#define HOST_STAT_nHIRQ 0x0
-#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define HOST_STAT_nALLOW_CNFG 0x0
-#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
-#define HOST_STAT_nDMA_DIR 0x0
-#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
-#define HOST_STAT_nBTE 0x0
-#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
-#define HOST_STAT_nHOSTRD_DONE 0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define nEMUDABL 0x0
-#define RSTDABL 0x2 /* Reset Disable */
-#define nRSTDABL 0x0
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define nDMA0OVR 0x0
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define nDMA1OVR 0x0
-#define EMUOVR 0x4000 /* Emulation Override */
-#define nEMUOVR 0x0
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define nOTPSEN 0x0
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define nSECURE0 0x0
-#define SECURE1 0x2 /* SECURE 1 */
-#define nSECURE1 0x0
-#define SECURE2 0x4 /* SECURE 2 */
-#define nSECURE2 0x0
-#define SECURE3 0x8 /* SECURE 3 */
-#define nSECURE3 0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define nNMI 0x0
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define nAFVALID 0x0
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define nAFEXIT 0x0
-#define SECSTAT 0xe0 /* Secure Status */
-
-#endif /* _DEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
deleted file mode 100644
index 97feaa6..0000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF514_H
-#define _DEF_BF514_H
-
-/* BF514 is BF512 + RSI */
-#include "defBF512.h"
-
-/* Removable Storage Interface Registers */
-
-#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
-#define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */
-
-#endif /* _DEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
deleted file mode 100644
index 7c79cb6..0000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF516.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF516_H
-#define _DEF_BF516_H
-
-/* BF516 is BF514 + EMAC */
-#include "defBF514.h"
-
-/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
deleted file mode 100644
index 12042ff..0000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF518.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF518_H
-#define _DEF_BF518_H
-
-/* BF518 is BF516 + IEEE-1588 */
-#include "defBF516.h"
-
-/* PTP TSYNC Registers */
-
-#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
-#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
-#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
-#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
-#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
-#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
-#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
-#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
-#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
-#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
-#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
-#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
-#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
-#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
-#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
-#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
-#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
-#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
-#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
-#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
-#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
-#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
-#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
-
-/* Bit masks for EMAC_PTP_CTL */
-
-#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */
-#define TL 0x2 /* Timestamp lock control */
-#define ASEN 0x10 /* Auxiliary snapshot control */
-#define PPSEN 0x80 /* Pulse-per-second (PPS) control */
-#define CKOEN 0x2000 /* Clock output control */
-
-/* Bit masks for EMAC_PTP_IE */
-
-#define ALIE 0x1 /* Alarm interrupt enable */
-#define RXEIE 0x2 /* Receive event interrupt enable */
-#define RXGIE 0x4 /* Receive general interrupt enable */
-#define TXIE 0x8 /* Transmit interrupt enable */
-#define RXOVE 0x10 /* Receive overrun error interrupt enable */
-#define TXOVE 0x20 /* Transmit overrun error interrupt enable */
-#define ASIE 0x40 /* Auxiliary snapshot interrupt enable */
-
-/* Bit masks for EMAC_PTP_ISTAT */
-
-#define ALS 0x1 /* Alarm status */
-#define RXEL 0x2 /* Receive event interrupt status */
-#define RXGL 0x4 /* Receive general interrupt status */
-#define TXTL 0x8 /* Transmit snapshot status */
-#define RXOV 0x10 /* Receive snapshot overrun status */
-#define TXOV 0x20 /* Transmit snapshot overrun status */
-#define ASL 0x40 /* Auxiliary snapshot interrupt status */
-
-#endif /* _DEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/dma.h b/arch/blackfin/mach-bf518/include/mach/dma.h
deleted file mode 100644
index bbd33c1..0000000
--- a/arch/blackfin/mach-bf518/include/mach/dma.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0 /* PPI receive/transmit */
-#define CH_EMAC_RX 1 /* Ethernet MAC receive */
-#define CH_EMAC_TX 2 /* Ethernet MAC transmit */
-#define CH_SPORT0_RX 3 /* SPORT0 receive */
-#define CH_SPORT0_TX 4 /* SPORT0 transmit */
-#define CH_RSI 4 /* RSI */
-#define CH_SPORT1_RX 5 /* SPORT1 receive */
-#define CH_SPI1 5 /* SPI1 transmit/receive */
-#define CH_SPORT1_TX 6 /* SPORT1 transmit */
-#define CH_SPI0 7 /* SPI0 transmit/receive */
-#define CH_UART0_RX 8 /* UART0 receive */
-#define CH_UART0_TX 9 /* UART0 transmit */
-#define CH_UART1_RX 10 /* UART1 receive */
-#define CH_UART1_TX 11 /* UART1 transmit */
-
-#define CH_MEM_STREAM0_SRC 12 /* RX */
-#define CH_MEM_STREAM0_DEST 13 /* TX */
-#define CH_MEM_STREAM1_SRC 14 /* RX */
-#define CH_MEM_STREAM1_DEST 15 /* TX */
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h
deleted file mode 100644
index b480705..0000000
--- a/arch/blackfin/mach-bf518/include/mach/gpio.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 41
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
deleted file mode 100644
index edf8efd..0000000
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF518_IRQ_H_
-#define _BF518_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
-#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
-#define IRQ_PTP_ERROR BFIN_IRQ(10) /* PTP Error Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
-#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
-#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
-#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
-#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
-#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
-#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
-#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
-#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
-#define IRQ_SPI0_ERROR BFIN_IRQ(47) /* SPI0 Status */
-#define IRQ_SPI1_ERROR BFIN_IRQ(48) /* SPI1 Error */
-#define IRQ_RSI_INT0 BFIN_IRQ(51) /* RSI Interrupt0 */
-#define IRQ_RSI_INT1 BFIN_IRQ(52) /* RSI Interrupt1 */
-#define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */
-#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
-#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS 0
-#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_PTP_ERROR_POS 8
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS 0
-#define IRQ_SPORT0_TX_POS 4
-#define IRQ_RSI_POS 4
-#define IRQ_SPORT1_RX_POS 8
-#define IRQ_SPI1_POS 8
-#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
-#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
-#define IRQ_PORTH_INTB_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_TIMER3_POS 12
-#define IRQ_TIMER4_POS 16
-#define IRQ_TIMER5_POS 20
-#define IRQ_TIMER6_POS 24
-#define IRQ_TIMER7_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS 0
-#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
-#define IRQ_PORTF_INTA_POS 20
-#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI0_ERROR_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_SPI1_ERROR_POS 0
-#define IRQ_RSI_INT0_POS 12
-#define IRQ_RSI_INT1_POS 16
-#define IRQ_PWM_TRIP_POS 20
-#define IRQ_PWM_SYNC_POS 24
-#define IRQ_PTP_STAT_POS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/mem_map.h b/arch/blackfin/mach-bf518/include/mach/mem_map.h
deleted file mode 100644
index 073b5d7..0000000
--- a/arch/blackfin/mach-bf518/include/mach/mem_map.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * BF51x memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF518/6/4/2 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16 * 1024)
-#else
-#define BFIN_ICACHESIZE (0)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0x8000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16 * 1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32 * 1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE 0
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE */
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h
deleted file mode 100644
index 94cca67..0000000
--- a/arch/blackfin/mach-bf518/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
deleted file mode 100644
index b3b806f..0000000
--- a/arch/blackfin/mach-bf518/include/mach/portmux.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-/* EMAC MII/RMII Port Mux */
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-
-#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#ifndef CONFIG_BF518_PPI_TMR_PG12
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#else
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#endif
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-/* SPORT Port Mux */
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-
-/* UART Port Mux */
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-
-/* Timer */
-#ifndef CONFIG_BF518_PPI_TMR_PG12
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#else
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#endif
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-
-/* DMA */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-
-/* TWI */
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-
-/* PWM */
-#ifndef CONFIG_BF518_PWM_PORTF_PORTG
-#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#else
-#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#endif
-
-#ifndef CONFIG_BF518_PWM_SYNC_PF15
-#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#else
-#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#endif
-
-#ifndef CONFIG_BF518_PWM_TRIPB_PG14
-#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
-#else
-#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#endif
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-
-/* AMS */
-#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf518/ints-priority.c b/arch/blackfin/mach-bf518/ints-priority.c
deleted file mode 100644
index bb05bef..0000000
--- a/arch/blackfin/mach-bf518/ints-priority.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
- ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
- ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
- ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
-
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_PTP_ERROR - 7) << IRQ_PTP_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
- ((CONFIG_IRQ_RSI_INT0 - 7) << IRQ_RSI_INT0_POS) |
- ((CONFIG_IRQ_RSI_INT1 - 7) << IRQ_RSI_INT1_POS) |
- ((CONFIG_IRQ_PWM_TRIP - 7) << IRQ_PWM_TRIP_POS) |
- ((CONFIG_IRQ_PWM_SYNC - 7) << IRQ_PWM_SYNC_POS) |
- ((CONFIG_IRQ_PTP_STAT - 7) << IRQ_PTP_STAT_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
deleted file mode 100644
index 6df20f9..0000000
--- a/arch/blackfin/mach-bf527/Kconfig
+++ /dev/null
@@ -1,325 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF52x
- def_bool y
- depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
-
-if (BF52x)
-
-source "arch/blackfin/mach-bf527/boards/Kconfig"
-
-menu "BF527 Specific Configuration"
-
-comment "Alternative Multiplexing Scheme"
-
-choice
- prompt "SPORT0"
- default BF527_SPORT0_PORTG
- help
- Select PORT used for SPORT0. See Hardware Reference Manual
-
-config BF527_SPORT0_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_SPORT0_PORTG
- bool "PORT G"
- help
- PORT G
-endchoice
-
-choice
- prompt "SPORT0 TSCLK Location"
- depends on BF527_SPORT0_PORTG
- default BF527_SPORT0_TSCLK_PG10
- help
- Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
-
-config BF527_SPORT0_TSCLK_PG10
- bool "PORT PG10"
- help
- PORT PG10
-
-config BF527_SPORT0_TSCLK_PG14
- bool "PORT PG14"
- help
- PORT PG14
-endchoice
-
-choice
- prompt "UART1"
- default BF527_UART1_PORTF
- help
- Select PORT used for UART1. See Hardware Reference Manual
-
-config BF527_UART1_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_UART1_PORTG
- bool "PORT G"
- help
- PORT G
-endchoice
-
-choice
- prompt "NAND (NFC) Data"
- default BF527_NAND_D_PORTH
- help
- Select PORT used for NAND Data Bus. See Hardware Reference Manual
-
-config BF527_NAND_D_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_NAND_D_PORTH
- bool "PORT H"
- help
- PORT H
-endchoice
-
-comment "Hysteresis/Schmitt Trigger Control"
-config BFIN_HYSTERESIS_CONTROL
- bool "Enable Hysteresis Control"
- help
- The ADSP-BF52x allows to control input hysteresis for Port F,
- Port G and Port H and other processor signal inputs.
- The Schmitt trigger enables can be set only for pin groups.
- Saying Y will overwrite the default reset or boot loader
- initialization.
-
-menu "PORT F"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTF_0_7
- bool "Enable Hysteresis on PORTF {0...7}"
-config GPIO_HYST_PORTF_8_9
- bool "Enable Hysteresis on PORTF {8, 9}"
-config GPIO_HYST_PORTF_10
- bool "Enable Hysteresis on PORTF 10"
-config GPIO_HYST_PORTF_11
- bool "Enable Hysteresis on PORTF 11"
-config GPIO_HYST_PORTF_12_13
- bool "Enable Hysteresis on PORTF {12, 13}"
-config GPIO_HYST_PORTF_14_15
- bool "Enable Hysteresis on PORTF {14, 15}"
-endmenu
-
-menu "PORT G"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTG_0
- bool "Enable Hysteresis on PORTG 0"
-config GPIO_HYST_PORTG_1_4
- bool "Enable Hysteresis on PORTG {1...4}"
-config GPIO_HYST_PORTG_5_6
- bool "Enable Hysteresis on PORTG {5, 6}"
-config GPIO_HYST_PORTG_7_8
- bool "Enable Hysteresis on PORTG {7, 8}"
-config GPIO_HYST_PORTG_9
- bool "Enable Hysteresis on PORTG 9"
-config GPIO_HYST_PORTG_10
- bool "Enable Hysteresis on PORTG 10"
-config GPIO_HYST_PORTG_11_13
- bool "Enable Hysteresis on PORTG {11...13}"
-config GPIO_HYST_PORTG_14_15
- bool "Enable Hysteresis on PORTG {14, 15}"
-endmenu
-
-menu "PORT H"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTH_0_7
- bool "Enable Hysteresis on PORTH {0...7}"
-config GPIO_HYST_PORTH_8
- bool "Enable Hysteresis on PORTH 8"
-config GPIO_HYST_PORTH_9_15
- bool "Enable Hysteresis on PORTH {9...15}"
-endmenu
-
-menu "None-GPIO"
- depends on BFIN_HYSTERESIS_CONTROL
-config NONEGPIO_HYST_TMR0_FS1_PPICLK
- bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
-config NONEGPIO_HYST_NMI_RST_BMODE
- bool "Enable Hysteresis on {NMI, RESET, BMODE}"
-config NONEGPIO_HYST_JTAG
- bool "Enable Hysteresis on JTAG"
-endmenu
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_DMAR0_BLK
- int "IRQ_DMAR0_BLK"
- default 7
-config IRQ_DMAR1_BLK
- int "IRQ_DMAR1_BLK"
- default 7
-config IRQ_DMAR0_OVR
- int "IRQ_DMAR0_OVR"
- default 7
-config IRQ_DMAR1_OVR
- int "IRQ_DMAR1_OVR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_MAC_ERROR
- int "IRQ_MAC_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_OPTSEC
- int "IRQ_OPTSEC"
- default 11
-config IRQ_CNT
- int "IRQ_CNT"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_PORTH_INTA
- int "IRQ_PORTH_INTA"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX/NFC"
- default 11
-config IRQ_PORTH_INTB
- int "IRQ_PORTH_INTB"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PORTG_INTA
- int "IRQ_PORTG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 13
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 13
-config IRQ_SPI_ERROR
- int "IRQ_SPI_ERROR"
- default 7
-config IRQ_NFC_ERROR
- int "IRQ_NFC_ERROR"
- default 7
-config IRQ_HDMA_ERROR
- int "IRQ_HDMA_ERROR"
- default 7
-config IRQ_HDMA
- int "IRQ_HDMA"
- default 7
-config IRQ_USB_EINT
- int "IRQ_USB_EINT"
- default 10
-config IRQ_USB_INT0
- int "IRQ_USB_INT0"
- default 10
-config IRQ_USB_INT1
- int "IRQ_USB_INT1"
- default 10
-config IRQ_USB_INT2
- int "IRQ_USB_INT2"
- default 10
-config IRQ_USB_DMA
- int "IRQ_USB_DMA"
- default 10
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile
deleted file mode 100644
index 4a6cdaf..0000000
--- a/arch/blackfin/mach-bf527/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf527/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig
deleted file mode 100644
index a76f02fa..0000000
--- a/arch/blackfin/mach-bf527/boards/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN527_EZKIT
- help
- Select your board!
-
-config BFIN527_EZKIT
- bool "BF527-EZKIT"
- help
- BF527-EZKIT-LITE board support.
-
-config BFIN527_EZKIT_V2
- bool "BF527-EZKIT-V2"
- help
- BF527-EZKIT-LITE V2.1+ board support.
-
-config BFIN527_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF527"
- help
- CM-BF527 support for EVAL- and DEV-Board.
-
-config BFIN526_EZBRD
- bool "BF526-EZBRD"
- help
- BF526-EZBRD/EZKIT Lite board support.
-
-config BFIN527_AD7160EVAL
- bool "BF527-AD7160-EVAL"
- help
- BF527-AD7160-EVAL board support.
-
-config BFIN527_TLL6527M
- bool "The Learning Labs TLL6527M"
- help
- TLL6527M V1.0 platform support
-
-endchoice
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
deleted file mode 100644
index 6ada153..0000000
--- a/arch/blackfin/mach-bf527/boards/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf527/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o
-obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
-obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
-obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o
-obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
deleted file mode 100644
index 68f2a8a..0000000
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ /dev/null
@@ -1,868 +0,0 @@
-/*
- * Copyright 2004-20010 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
-static struct resource bf52x_ra158z_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf52x_ra158z_device = {
- .name = "bfin-ra158z",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf52x_ra158z_resources),
- .resource = bf52x_ra158z_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ad7160eval_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ad7160eval_flash_data = {
- .width = 2,
- .parts = ad7160eval_partitions,
- .nr_parts = ARRAY_SIZE(ad7160eval_partitions),
-};
-
-static struct resource ad7160eval_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ad7160eval_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ad7160eval_flash_data,
- },
- .num_resources = 1,
- .resource = &ad7160eval_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = GPIO_PH3 + MAX_CTRL_CS,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
-#include <linux/input/ad7160.h>
-static const struct ad7160_platform_data bfin_ad7160_ts_info = {
- .sensor_x_res = 854,
- .sensor_y_res = 480,
- .pressure = 100,
- .filter_coef = 3,
- .coord_pref = AD7160_ORIG_TOP_LEFT,
- .first_touch_window = 5,
- .move_window = 3,
- .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
- AD7160_EMIT_ABS_MT_PRESSURE |
- AD7160_TRACKING_ID_ASCENDING,
- .finger_act_ctrl = 0x64,
- .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
- AD7160_HAPTIC_SLOT_A_LVL_HIGH |
- AD7160_HAPTIC_SLOT_B(60) |
- AD7160_HAPTIC_SLOT_B_LVL_LOW,
-
- .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
- AD7160_HAPTIC_SLOT_A_LVL_HIGH |
- AD7160_HAPTIC_SLOT_B(80) |
- AD7160_HAPTIC_SLOT_B_LVL_LOW |
- AD7160_HAPTIC_SLOT_C(120) |
- AD7160_HAPTIC_SLOT_C_LVL_HIGH |
- AD7160_HAPTIC_SLOT_D(30) |
- AD7160_HAPTIC_SLOT_D_LVL_LOW,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
- {
- I2C_BOARD_INFO("ad7160", 0x33),
- .irq = IRQ_PH1,
- .platform_data = (void *)&bfin_ad7160_ts_info,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static const u16 per_cnt[] = {
- P_CNT_CUD,
- P_CNT_CDG,
- P_CNT_CZM,
- 0
-};
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
- .pin_list = per_cnt,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
- &bf52x_ra158z_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ad7160eval_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-};
-
-static int __init ad7160eval_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ad7160eval_init);
-
-static struct platform_device *ad7160eval_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ad7160eval_early_devices,
- ARRAY_SIZE(ad7160eval_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
deleted file mode 100644
index b1004b3..0000000
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ /dev/null
@@ -1,992 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/etherdevice.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM-BF527";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PF11,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB804,
- .end = 0x203FB804 + 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF14, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cmbf527_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init cm_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(cm_init);
-
-static struct platform_device *cmbf527_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cmbf527_early_devices,
- ARRAY_SIZE(cmbf527_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
deleted file mode 100644
index 80bcfd1..0000000
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ /dev/null
@@ -1,891 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF526-EZBRD";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezbrd_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezbrd_flash_data = {
- .width = 2,
- .parts = ezbrd_partitions,
- .nr_parts = ARRAY_SIZE(ezbrd_partitions),
-};
-
-static struct resource ezbrd_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezbrd_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezbrd_flash_data,
- },
- .num_resources = 1,
- .resource = &ezbrd_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x40000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "sst25wf040",
-};
-
-/* SPI flash chip (sst25wf040) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PG0,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG0,
- .end = GPIO_PG0,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 1,
- .gpio_bl = GPIO_PG12,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezbrd_flash_device,
-#endif
-};
-
-static int __init ezbrd_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezbrd_init);
-
-static struct platform_device *ezbrd_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezbrd_early_devices,
- ARRAY_SIZE(ezbrd_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
deleted file mode 100644
index 571edfd..0000000
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ /dev/null
@@ -1,1335 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-#include <asm/bfin_sport.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-#ifdef CONFIG_BFIN527_EZKIT_V2
-const char bfin_board_name[] = "ADI BF527-EZKIT V2";
-#else
-const char bfin_board_name[] = "ADI BF527-EZKIT";
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
-
-static struct resource bf52x_t350mcqb_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf52x_t350mcqb_device = {
- .name = "bfin-t350mcqb",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf52x_t350mcqb_resources),
- .resource = bf52x_t350mcqb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_8_BIT_PPI,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x40000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB800 + 4,
- .end = 0x203FB800 + 5,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 0, /* Export GPIO to gpiolib */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-
-static const u16 bfin_snd_pin[][7] = {
- {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0},
- {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0},
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836",
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 7,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
-#include <linux/mfd/adp5520.h>
-
- /*
- * ADP5520/5501 LEDs Data
- */
-
-static struct led_info adp5520_leds[] = {
- {
- .name = "adp5520-led1",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
- },
-};
-
-static struct adp5520_leds_platform_data adp5520_leds_data = {
- .num_leds = ARRAY_SIZE(adp5520_leds),
- .leds = adp5520_leds,
- .fade_in = ADP5520_FADE_T_600ms,
- .fade_out = ADP5520_FADE_T_600ms,
- .led_on_time = ADP5520_LED_ONT_600ms,
-};
-
- /*
- * ADP5520 Keypad Data
- */
-
-static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
- [ADP5520_KEY(3, 3)] = KEY_1,
- [ADP5520_KEY(2, 3)] = KEY_2,
- [ADP5520_KEY(1, 3)] = KEY_3,
- [ADP5520_KEY(0, 3)] = KEY_UP,
- [ADP5520_KEY(3, 2)] = KEY_4,
- [ADP5520_KEY(2, 2)] = KEY_5,
- [ADP5520_KEY(1, 2)] = KEY_6,
- [ADP5520_KEY(0, 2)] = KEY_DOWN,
- [ADP5520_KEY(3, 1)] = KEY_7,
- [ADP5520_KEY(2, 1)] = KEY_8,
- [ADP5520_KEY(1, 1)] = KEY_9,
- [ADP5520_KEY(0, 1)] = KEY_DOT,
- [ADP5520_KEY(3, 0)] = KEY_BACKSPACE,
- [ADP5520_KEY(2, 0)] = KEY_0,
- [ADP5520_KEY(1, 0)] = KEY_HELP,
- [ADP5520_KEY(0, 0)] = KEY_ENTER,
-};
-
-static struct adp5520_keys_platform_data adp5520_keys_data = {
- .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
- .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
- .keymap = adp5520_keymap,
- .keymapsize = ARRAY_SIZE(adp5520_keymap),
- .repeat = 0,
-};
-
- /*
- * ADP5520/5501 Multifunction Device Init Data
- */
-
-static struct adp5520_platform_data adp5520_pdev_data = {
- .leds = &adp5520_leds_data,
- .keys = &adp5520_keys_data,
-};
-
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2C),
- .irq = IRQ_PF8,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
- {
- I2C_BOARD_INFO("pmic-adp5520", 0x32),
- .irq = IRQ_PF9,
- .platform_data = (void *)&adp5520_pdev_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
- {
- I2C_BOARD_INFO("adau1373", 0x1A),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static const u16 per_cnt[] = {
- P_CNT_CUD,
- P_CNT_CDG,
- P_CNT_CZM,
- 0
-};
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
- .pin_list = per_cnt,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
- &bf52x_t350mcqb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
deleted file mode 100644
index ce5488e..0000000
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ /dev/null
@@ -1,946 +0,0 @@
-/* File: arch/blackfin/mach-bf527/boards/tll6527m.c
- * Based on: arch/blackfin/mach-bf527/boards/ezkit.c
- * Author: Ashish Gupta
- *
- * Copyright: 2010 - The Learning Labs Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-#define LCD_BACKLIGHT_GPIO 0x40
-/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
- * LCD Backlight Enable
- */
-#endif
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "TLL6527M";
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- /*.gpio_vrsel = GPIO_PG13,*/
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 1,
- .gpio_bl = LCD_BACKLIGHT_GPIO,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition tll6527m_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0xA0000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0xD00000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data tll6527m_flash_data = {
- .width = 2,
- .parts = tll6527m_partitions,
- .nr_parts = ARRAY_SIZE(tll6527m_partitions),
-};
-
-static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
-
-static struct resource tll6527m_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)tll6527m_flash_gpios,
- .end = ARRAY_SIZE(tll6527m_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device tll6527m_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &tll6527m_flash_data,
- },
- .num_resources = ARRAY_SIZE(tll6527m_flash_resource),
- .resource = tll6527m_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_DECODER)
-/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
- * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
- * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
- * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
- */
-#include <linux/gpio-decoder.h>
-#define EXP_GPIO_SPISEL_BASE 0x64
-static unsigned gpio_addr_inputs[] = {
- GPIO_PG1, GPIO_PH9, GPIO_PH10
-};
-
-static struct gpio_decoder_platform_data spi_decoded_cs = {
- .base = EXP_GPIO_SPISEL_BASE,
- .input_addrs = gpio_addr_inputs,
- .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
- .default_output = 0,
-/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
-};
-
-static struct platform_device spi_decoded_gpio = {
- .name = "gpio-decoder",
- .id = 0,
- .dev = {
- .platform_data = &spi_decoded_cs,
- },
-};
-
-#else
-#define EXP_GPIO_SPISEL_BASE 0x0
-
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl345_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 2,
- .inactivity_time = 2,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
- .ev_code_act_inactivity = KEY_A, /* EV_KEY */
- .use_int2 = 1,
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3,
- /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1,
- /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* configure AUX as GPIO output*/
- .gpio_base = LCD_BACKLIGHT_GPIO,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-#include <linux/spi/mcp23s08.h>
-static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
- .spi_present_mask = BIT(0),
- .base = 0x30,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
- .spi_present_mask = BIT(2),
- .base = 0x38,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
- /* Can be connected to TLL6527M GPIO connector */
- /* Either SPI_ADC or M25P80 FLASH can be installed at a time */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
-/*
- * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
- * SPI buffer limitations
- */
- .max_speed_hz = 10000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PH14,
- .max_speed_hz = 5000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 10000000,
- /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
- {
- .modalias = "mcp23s08",
- .platform_data = &bfin_mcp23s08_sys_gpio_info,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
- {
- .modalias = "mcp23s08",
- .platform_data = &bfin_mcp23s08_usr_gpio_info,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
- /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2C),
- .irq = IRQ_PH14,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
- {
- I2C_BOARD_INFO("adm1192", 0x2e),
- },
-
- {
- I2C_BOARD_INFO("ltc3576", 0x09),
- },
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PH13,
- .platform_data = (void *)&adxl345_info,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *tll6527m_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &tll6527m_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_DECODER)
- &spi_decoded_gpio,
-#endif
-};
-
-static int __init tll6527m_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(tll6527m_init);
-
-static struct platform_device *tll6527m_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tll6527m_early_devices,
- ARRAY_SIZE(tll6527m_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags,
- u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
deleted file mode 100644
index 1fabdef..0000000
--- a/arch/blackfin/mach-bf527/dma.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * This file contains the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
deleted file mode 100644
index 2f9cc33..0000000
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 0
-# error will not work on BF526/BF527 silicon version
-#endif
-
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-# define ANOMALY_BF526 1
-#else
-# define ANOMALY_BF526 0
-#endif
-#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
-# define ANOMALY_BF527 1
-#else
-# define ANOMALY_BF527 0
-#endif
-
-#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
-#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
-#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches@the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
-/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0xE510
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
-/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Incorrect Default CSEL Value in PLL_DIV */
-#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
-/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
-/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
-/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
-#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
-/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
-#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
-/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Default Internal Voltage Regulator Setting */
-#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* DEB2_URGENT Bit Not Functional */
-#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
-#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
-/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
-#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
-#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
-/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
-#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Internal Voltage Regulator Not Trimmed */
-#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
-#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
-/* IFLUSH Instruction@End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
-/* The CODEC Zero-Cross Detect Feature is not Functional */
-#define ANOMALY_05000487 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
deleted file mode 100644
index 8ff155b..0000000
--- a/arch/blackfin/mach-bf527/include/mach/bf527.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF527_H__
-#define __MACH_BF527_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-/**************************** Hysteresis Settings ****************************/
-
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-#ifdef CONFIG_GPIO_HYST_PORTF_0_7
-#define HYST_PORTF_0_7 (1 << 0)
-#else
-#define HYST_PORTF_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_8_9
-#define HYST_PORTF_8_9 (1 << 2)
-#else
-#define HYST_PORTF_8_9 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_10
-#define HYST_PORTF_10 (1 << 4)
-#else
-#define HYST_PORTF_10 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_11
-#define HYST_PORTF_11 (1 << 6)
-#else
-#define HYST_PORTF_11 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_12_13
-#define HYST_PORTF_12_13 (1 << 8)
-#else
-#define HYST_PORTF_12_13 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_14_15
-#define HYST_PORTF_14_15 (1 << 10)
-#else
-#define HYST_PORTF_14_15 (0 << 10)
-#endif
-
-#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
- HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTG_0
-#define HYST_PORTG_0 (1 << 0)
-#else
-#define HYST_PORTG_0 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_1_4
-#define HYST_PORTG_1_4 (1 << 2)
-#else
-#define HYST_PORTG_1_4 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_5_6
-#define HYST_PORTG_5_6 (1 << 4)
-#else
-#define HYST_PORTG_5_6 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_7_8
-#define HYST_PORTG_7_8 (1 << 6)
-#else
-#define HYST_PORTG_7_8 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_9
-#define HYST_PORTG_9 (1 << 8)
-#else
-#define HYST_PORTG_9 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_10
-#define HYST_PORTG_10 (1 << 10)
-#else
-#define HYST_PORTG_10 (0 << 10)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_11_13
-#define HYST_PORTG_11_13 (1 << 12)
-#else
-#define HYST_PORTG_11_13 (0 << 12)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_14_15
-#define HYST_PORTG_14_15 (1 << 14)
-#else
-#define HYST_PORTG_14_15 (0 << 14)
-#endif
-
-#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
- HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
- HYST_PORTG_11_13 | HYST_PORTG_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTH_0_7
-#define HYST_PORTH_0_7 (1 << 0)
-#else
-#define HYST_PORTH_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTH_8
-#define HYST_PORTH_8 (1 << 2)
-#else
-#define HYST_PORTH_8 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTH_9_15
-#define HYST_PORTH_9_15 (1 << 4)
-#else
-#define HYST_PORTH_9_15 (0 << 4)
-#endif
-
-#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
-
-#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
-#define HYST_TMR0_FS1_PPICLK (1 << 0)
-#else
-#define HYST_TMR0_FS1_PPICLK (0 << 0)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
-#define HYST_NMI_RST_BMODE (1 << 2)
-#else
-#define HYST_NMI_RST_BMODE (0 << 2)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_JTAG
-#define HYST_JTAG (1 << 4)
-#else
-#define HYST_JTAG (0 << 4)
-#endif
-
-#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
-#define HYST_NONEGPIO_MASK (0x3F)
-#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
-
-#ifdef CONFIG_BF527
-#define CPU "BF527"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF526
-#define CPU "BF526"
-#define CPUID 0x27e4
-#endif
-#ifdef CONFIG_BF525
-#define CPU "BF525"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF524
-#define CPU "BF524"
-#define CPUID 0x27e4
-#endif
-#ifdef CONFIG_BF523
-#define CPU "BF523"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF522
-#define CPU "BF522"
-#define CPUID 0x27e4
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF527_H__ */
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
deleted file mode 100644
index 00c603f..0000000
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
deleted file mode 100644
index e1d2792..0000000
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf527.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
-# include "defBF522.h"
-#endif
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-# include "defBF525.h"
-#endif
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-# include "defBF527.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-# include <asm/cdef_LPBlackfin.h>
-# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
-# include "cdefBF522.h"
-# endif
-# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-# include "cdefBF525.h"
-# endif
-# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-# include "cdefBF527.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
deleted file mode 100644
index 2c12e87..0000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ /dev/null
@@ -1,1095 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF522_H
-#define _CDEF_BF522_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
-#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-
-#endif /* _CDEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
deleted file mode 100644
index bd04531..0000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF525_H
-#define _CDEF_BF525_H
-
-/* BF525 is BF522 + USB */
-#include "cdefBF522.h"
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endpoint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endpoint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-
-/* USB Endpoint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-
-/* USB Endpoint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-
-/* USB Endpoint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-
-/* USB Endpoint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-
-/* USB Endpoint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-
-/* USB Endpoint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-
-/* USB Endpoint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-#endif /* _CDEF_BF525_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
deleted file mode 100644
index eb22f586..0000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF527_H
-#define _CDEF_BF527_H
-
-/* BF527 is BF525 + EMAC */
-#include "cdefBF525.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* _CDEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
deleted file mode 100644
index e007017..0000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ /dev/null
@@ -1,1309 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF522_H
-#define _DEF_BF522_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
-/* ************************************************************** */
-
-/* ==== begin from defBF534.h ==== */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
-#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-
-#if 0
-#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
-
-#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
-#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
-#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
-#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
-#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
-
-#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
-#define IRQ_TWI 0x00000200 /* TWI Interrupt */
-#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
-#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
-#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
-#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
-#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
-#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
-
-#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
-#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
-#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
-#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
-#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
-#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
-#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
-#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
-#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
-#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
-
-#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
-#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
-#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
-#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
-#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
-#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
-#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
-#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
-#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
-#endif
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* Omit CAN masks from defBF534.h */
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-
-/* ==== end from defBF534.h ==== */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
-#define HOST_STATUS 0xffc03404 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc03500 /* Configuration Register */
-#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc03508 /* Status Register */
-#define CNT_COMMAND 0xffc0350c /* Command Register */
-#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
-#define CNT_COUNTER 0xffc03514 /* Counter Register */
-#define CNT_MAX 0xffc03518 /* Maximal Count Register */
-#define CNT_MIN 0xffc0351c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc03624 /* Secure Control */
-#define SECURE_STATUS 0xffc03628 /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* NFC Registers */
-
-#define NFC_CTL 0xffc03700 /* NAND Control Register */
-#define NFC_STAT 0xffc03704 /* NAND Status Register */
-#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
-#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
-#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
-#define NFC_READ 0xffc0372c /* NAND Read Data Register */
-#define NFC_ADDR 0xffc03740 /* NAND Address Register */
-#define NFC_CMD 0xffc03744 /* NAND Command Register */
-#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
-#define HOST_CNTR_nHOST_EN 0x0
-#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
-#define HOST_CNTR_nHOST_END 0x0
-#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
-#define HOST_CNTR_nDATA_SIZE 0x0
-#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
-#define HOST_CNTR_nHOST_RST 0x0
-#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
-#define HOST_CNTR_nHRDY_OVR 0x0
-#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
-#define HOST_CNTR_nINT_MODE 0x0
-#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
-#define HOST_CNTR_ nBT_EN 0x0
-#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
-#define HOST_CNTR_nEHW 0x0
-#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
-#define HOST_CNTR_nEHR 0x0
-#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
-#define HOST_CNTR_nBDR 0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define HOST_STAT_READY 0x1 /* DMA Ready */
-#define HOST_STAT_nREADY 0x0
-#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
-#define HOST_STAT_nFIFOFULL 0x0
-#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
-#define HOST_STAT_nFIFOEMPTY 0x0
-#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
-#define HOST_STAT_nCOMPLETE 0x0
-#define HOST_STAT_HSHK 0x10 /* Host Handshake */
-#define HOST_STAT_nHSHK 0x0
-#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
-#define HOST_STAT_nTIMEOUT 0x0
-#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
-#define HOST_STAT_nHIRQ 0x0
-#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define HOST_STAT_nALLOW_CNFG 0x0
-#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
-#define HOST_STAT_nDMA_DIR 0x0
-#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
-#define HOST_STAT_nBTE 0x0
-#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
-#define HOST_STAT_nHOSTRD_DONE 0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define nEMUDABL 0x0
-#define RSTDABL 0x2 /* Reset Disable */
-#define nRSTDABL 0x0
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define nDMA0OVR 0x0
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define nDMA1OVR 0x0
-#define EMUOVR 0x4000 /* Emulation Override */
-#define nEMUOVR 0x0
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define nOTPSEN 0x0
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define nSECURE0 0x0
-#define SECURE1 0x2 /* SECURE 1 */
-#define nSECURE1 0x0
-#define SECURE2 0x4 /* SECURE 2 */
-#define nSECURE2 0x0
-#define SECURE3 0x8 /* SECURE 3 */
-#define nSECURE3 0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define nNMI 0x0
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define nAFVALID 0x0
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define nAFEXIT 0x0
-#define SECSTAT 0xe0 /* Secure Status */
-
-#endif /* _DEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
deleted file mode 100644
index 591e00f..0000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ /dev/null
@@ -1,678 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF525_H
-#define _DEF_BF525_H
-
-/* BF525 is BF522 + USB */
-#include "defBF522.h"
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03800 /* Function address register */
-#define USB_POWER 0xffc03804 /* Power management register */
-#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03820 /* USB frame number */
-#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
-
-#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define nENABLE_SUSPENDM 0x0
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define nSUSPEND_MODE 0x0
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define nRESUME_MODE 0x0
-#define RESET 0x8 /* Reset indicator */
-#define nRESET 0x0
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define nHS_MODE 0x0
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define nHS_ENABLE 0x0
-#define SOFT_CONN 0x40 /* Soft connect */
-#define nSOFT_CONN 0x0
-#define ISO_UPDATE 0x80 /* Isochronous update */
-#define nISO_UPDATE 0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define nEP0_TX 0x0
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define nEP1_TX 0x0
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define nEP2_TX 0x0
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define nEP3_TX 0x0
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define nEP4_TX 0x0
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define nEP5_TX 0x0
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define nEP6_TX 0x0
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-#define nEP7_TX 0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define nEP1_RX 0x0
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define nEP2_RX 0x0
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define nEP3_RX 0x0
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define nEP4_RX 0x0
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define nEP5_RX 0x0
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define nEP6_RX 0x0
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-#define nEP7_RX 0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define nEP0_TX_E 0x0
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define nEP1_TX_E 0x0
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define nEP2_TX_E 0x0
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define nEP3_TX_E 0x0
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define nEP4_TX_E 0x0
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define nEP5_TX_E 0x0
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define nEP6_TX_E 0x0
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-#define nEP7_TX_E 0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define nEP1_RX_E 0x0
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define nEP2_RX_E 0x0
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define nEP3_RX_E 0x0
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define nEP4_RX_E 0x0
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define nEP5_RX_E 0x0
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define nEP6_RX_E 0x0
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-#define nEP7_RX_E 0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define nSUSPEND_B 0x0
-#define RESUME_B 0x2 /* Resume indicator */
-#define nRESUME_B 0x0
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define nRESET_OR_BABLE_B 0x0
-#define SOF_B 0x8 /* Start of frame */
-#define nSOF_B 0x0
-#define CONN_B 0x10 /* Connection indicator */
-#define nCONN_B 0x0
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define nDISCON_B 0x0
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define nSESSION_REQ_B 0x0
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-#define nVBUS_ERROR_B 0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define nSUSPEND_BE 0x0
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define nRESUME_BE 0x0
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define nRESET_OR_BABLE_BE 0x0
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define nSOF_BE 0x0
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define nCONN_BE 0x0
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define nDISCON_BE 0x0
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define nSESSION_REQ_BE 0x0
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-#define nVBUS_ERROR_BE 0x0
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define nGLOBAL_ENA 0x0
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define nEP1_TX_ENA 0x0
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define nEP2_TX_ENA 0x0
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define nEP3_TX_ENA 0x0
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define nEP4_TX_ENA 0x0
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define nEP5_TX_ENA 0x0
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define nEP6_TX_ENA 0x0
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define nEP7_TX_ENA 0x0
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define nEP1_RX_ENA 0x0
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define nEP2_RX_ENA 0x0
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define nEP3_RX_ENA 0x0
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define nEP4_RX_ENA 0x0
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define nEP5_RX_ENA 0x0
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define nEP6_RX_ENA 0x0
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-#define nEP7_RX_ENA 0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define nSESSION 0x0
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define nHOST_REQ 0x0
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define nHOST_MODE 0x0
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define nVBUS0 0x0
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define nVBUS1 0x0
-#define LSDEV 0x20 /* Low-speed indicator */
-#define nLSDEV 0x0
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define nFSDEV 0x0
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-#define nB_DEVICE 0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define nDRIVE_VBUS_ON 0x0
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define nDRIVE_VBUS_OFF 0x0
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define nCHRG_VBUS_START 0x0
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define nCHRG_VBUS_END 0x0
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define nDISCHRG_VBUS_START 0x0
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-#define nDISCHRG_VBUS_END 0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define nDRIVE_VBUS_ON_ENA 0x0
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define nDRIVE_VBUS_OFF_ENA 0x0
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define nCHRG_VBUS_START_ENA 0x0
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define nCHRG_VBUS_END_ENA 0x0
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define nDISCHRG_VBUS_START_ENA 0x0
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-#define nDISCHRG_VBUS_END_ENA 0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define nRXPKTRDY 0x0
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define nTXPKTRDY 0x0
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define nSTALL_SENT 0x0
-#define DATAEND 0x8 /* Data end indicator */
-#define nDATAEND 0x0
-#define SETUPEND 0x10 /* Setup end */
-#define nSETUPEND 0x0
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define nSENDSTALL 0x0
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define nSERVICED_RXPKTRDY 0x0
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define nSERVICED_SETUPEND 0x0
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define nFLUSHFIFO 0x0
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define nSTALL_RECEIVED_H 0x0
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define nSETUPPKT_H 0x0
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define nERROR_H 0x0
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define nREQPKT_H 0x0
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define nSTATUSPKT_H 0x0
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-#define nNAK_TIMEOUT_H 0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define nTXPKTRDY_T 0x0
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define nFIFO_NOT_EMPTY_T 0x0
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define nUNDERRUN_T 0x0
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define nFLUSHFIFO_T 0x0
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define nSTALL_SEND_T 0x0
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define nSTALL_SENT_T 0x0
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_T 0x0
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define nINCOMPTX_T 0x0
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_T 0x0
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define nFORCE_DATATOGGLE_T 0x0
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_T 0x0
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define nISO_T 0x0
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOSET_T 0x0
-#define ERROR_TH 0x4 /* error condition host mode */
-#define nERROR_TH 0x0
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_TH 0x0
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-#define nNAK_TIMEOUT_TH 0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define nRXPKTRDY_R 0x0
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define nFIFO_FULL_R 0x0
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define nOVERRUN_R 0x0
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define nDATAERROR_R 0x0
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define nFLUSHFIFO_R 0x0
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define nSTALL_SEND_R 0x0
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define nSTALL_SENT_R 0x0
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_R 0x0
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define nINCOMPRX_R 0x0
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_R 0x0
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define nDISNYET_R 0x0
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_R 0x0
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define nISO_R 0x0
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOCLEAR_R 0x0
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define nERROR_RH 0x0
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define nREQPKT_RH 0x0
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_RH 0x0
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define nINCOMPRX_RH 0x0
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define nDMAREQMODE_RH 0x0
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-#define nAUTOREQ_RH 0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define nDMA0_INT 0x0
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define nDMA1_INT 0x0
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define nDMA2_INT 0x0
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define nDMA3_INT 0x0
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define nDMA4_INT 0x0
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define nDMA5_INT 0x0
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define nDMA6_INT 0x0
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-#define nDMA7_INT 0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define nDMA_ENA 0x0
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define nDIRECTION 0x0
-#define MODE 0x4 /* DMA Bus error */
-#define nMODE 0x0
-#define INT_ENA 0x8 /* Interrupt enable */
-#define nINT_ENA 0x0
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-#define nBUSERROR 0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF525_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
deleted file mode 100644
index aeb8479..0000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF527_H
-#define _DEF_BF527_H
-
-/* BF527 is BF525 + EMAC */
-#include "defBF525.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/dma.h b/arch/blackfin/mach-bf527/include/mach/dma.h
deleted file mode 100644
index eb287da..0000000
--- a/arch/blackfin/mach-bf527/include/mach/dma.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0 /* PPI receive/transmit or NFC */
-#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
-#define CH_SPORT0_RX 3 /* SPORT0 receive */
-#define CH_SPORT0_TX 4 /* SPORT0 transmit */
-#define CH_SPORT1_RX 5 /* SPORT1 receive */
-#define CH_SPORT1_TX 6 /* SPORT1 transmit */
-#define CH_SPI 7 /* SPI transmit/receive */
-#define CH_UART0_RX 8 /* UART0 receive */
-#define CH_UART0_TX 9 /* UART0 transmit */
-#define CH_UART1_RX 10 /* UART1 receive */
-#define CH_UART1_TX 11 /* UART1 transmit */
-
-#define CH_MEM_STREAM0_DEST 12 /* TX */
-#define CH_MEM_STREAM0_SRC 13 /* RX */
-#define CH_MEM_STREAM1_DEST 14 /* TX */
-#define CH_MEM_STREAM1_SRC 15 /* RX */
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
deleted file mode 100644
index fba606b..0000000
--- a/arch/blackfin/mach-bf527/include/mach/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
deleted file mode 100644
index ed7310f..0000000
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF527_IRQ_H_
-#define _BF527_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
-#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
-#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
-#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
-#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
-#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
-#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
-#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
-#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
-#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
-#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
-#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
-#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
-#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
-#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
-#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS 0
-#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS 0
-#define IRQ_SPORT0_TX_POS 4
-#define IRQ_SPORT1_RX_POS 8
-#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
-#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
-#define IRQ_PORTH_INTB_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_TIMER3_POS 12
-#define IRQ_TIMER4_POS 16
-#define IRQ_TIMER5_POS 20
-#define IRQ_TIMER6_POS 24
-#define IRQ_TIMER7_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS 0
-#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
-#define IRQ_PORTF_INTA_POS 20
-#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI_ERROR_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_NFC_ERROR_POS 0
-#define IRQ_HDMA_ERROR_POS 4
-#define IRQ_HDMA_POS 8
-#define IRQ_USB_EINT_POS 12
-#define IRQ_USB_INT0_POS 16
-#define IRQ_USB_INT1_POS 20
-#define IRQ_USB_INT2_POS 24
-#define IRQ_USB_DMA_POS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h
deleted file mode 100644
index d96e894..0000000
--- a/arch/blackfin/mach-bf527/include/mach/mem_map.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * BF52x memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE */
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
deleted file mode 100644
index 94cca67..0000000
--- a/arch/blackfin/mach-bf527/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h
deleted file mode 100644
index 08bae42..0000000
--- a/arch/blackfin/mach-bf527/include/mach/portmux.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#if defined(CONFIG_BF527_SPORT0_PORTF)
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_PORTG)
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#endif
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#endif
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_UART1_PORTF)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_UART1_PORTG)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#endif
-
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
-
-#define P_HWAIT (P_DONTCARE)
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#endif
-
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c
deleted file mode 100644
index 44ca215..0000000
--- a/arch/blackfin/mach-bf527/ints-priority.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
- ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
- ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
- ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
-
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_NFC_ERROR - 7) << IRQ_NFC_ERROR_POS) |
- ((CONFIG_IRQ_HDMA_ERROR - 7) << IRQ_HDMA_ERROR_POS) |
- ((CONFIG_IRQ_HDMA - 7) << IRQ_HDMA_POS) |
- ((CONFIG_IRQ_USB_EINT - 7) << IRQ_USB_EINT_POS) |
- ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
- ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
- ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
- ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig
deleted file mode 100644
index 4e1a05b..0000000
--- a/arch/blackfin/mach-bf533/Kconfig
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF533 || BF532 || BF531)
-
-source "arch/blackfin/mach-bf533/boards/Kconfig"
-
-menu "BF533/2/1 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config UART_ERROR
- int "UART ERROR"
- default 7
-config SPORT0_ERROR
- int "SPORT0 ERROR"
- default 7
-config SPI_ERROR
- int "SPI ERROR"
- default 7
-config SPORT1_ERROR
- int "SPORT1 ERROR"
- default 7
-config PPI_ERROR
- int "PPI ERROR"
- default 7
-config DMA_ERROR
- int "DMA ERROR"
- default 7
-config PLLWAKE_ERROR
- int "PLL WAKEUP ERROR"
- default 7
-
-config RTC_ERROR
- int "RTC ERROR"
- default 8
-config DMA0_PPI
- int "DMA0 PPI"
- default 8
-
-config DMA1_SPORT0RX
- int "DMA1 (SPORT0 RX)"
- default 9
-config DMA2_SPORT0TX
- int "DMA2 (SPORT0 TX)"
- default 9
-config DMA3_SPORT1RX
- int "DMA3 (SPORT1 RX)"
- default 9
-config DMA4_SPORT1TX
- int "DMA4 (SPORT1 TX)"
- default 9
-config DMA5_SPI
- int "DMA5 (SPI)"
- default 10
-config DMA6_UARTRX
- int "DMA6 (UART0 RX)"
- default 10
-config DMA7_UARTTX
- int "DMA7 (UART0 TX)"
- default 10
-config TIMER0
- int "TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config TIMER1
- int "TIMER1"
- default 11
-config TIMER2
- int "TIMER2"
- default 11
-config PFA
- int "PF Interrupt A"
- default 12
-config PFB
- int "PF Interrupt B"
- default 12
-config MEMDMA0
- int "MEMORY DMA0"
- default 13
-config MEMDMA1
- int "MEMORY DMA1"
- default 13
-config WDTIMER
- int "WATCH DOG TIMER"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile
deleted file mode 100644
index 874840f..0000000
--- a/arch/blackfin/mach-bf533/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf533/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
deleted file mode 100644
index 01300f4..0000000
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ /dev/null
@@ -1,452 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2007-2008 HV Sistemas S.L.
- * Javier Herrero <jherrero@hvsistemas.es>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "HV Sistemas H8606";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
-* Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x20300000,
- .end = 0x20300002,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x20300004,
- .end = 0x20300006,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
- IORESOURCE_IRQ_SHAREABLE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .id = 0,
- .name = "dm9000",
- .resource = dm9000_resources,
- .num_resources = ARRAY_SIZE(dm9000_resources),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PROG_INTB,
- .end = IRQ_PROG_INTB,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader (spi)",
- .size = 0x40000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "fpga (spi)",
- .size = 0x30000,
- .offset = 0x40000
- }, {
- .name = "linux kernel (spi)",
- .size = 0x150000,
- .offset = 0x70000
- }, {
- .name = "jffs2 root file system (spi)",
- .size = 0x640000,
- .offset = 0x1c0000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-/* Notice: for blackfin, the speed_hz is the value of register
- * SPI_BAUD, not the real baudrate */
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- /* this value is the baudrate divisor */
- .max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 16,
- .bus_num = 1,
- .chip_select = 4,
- },
-#endif
-
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_8250)
-
-#include <linux/serial_8250.h>
-#include <linux/serial.h>
-
-/*
- * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010.
- * running at half system clock, both with interrupt output or-ed to PF8. Change to
- * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus
- */
-
-static struct plat_serial8250_port serial8250_platform_data [] = {
- {
- .membase = (void *)0x20200000,
- .mapbase = 0x20200000,
- .irq = IRQ_PF8,
- .irqflags = IRQF_TRIGGER_HIGH,
- .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = 66666667,
- }, {
- .membase = (void *)0x20200010,
- .mapbase = 0x20200010,
- .irq = IRQ_PF8,
- .irqflags = IRQF_TRIGGER_HIGH,
- .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = 66666667,
- }, {
- }
-};
-
-static struct platform_device serial8250_device = {
- .id = PLAT8250_DEV_PLATFORM,
- .name = "serial8250",
- .dev = {
- .platform_data = serial8250_platform_data,
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES)
-
-/*
- * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030,
- * interrupt output wired to PF9. Change to suit different FPGA configuration
- */
-
-static struct resource opencores_kbd_resources[] = {
- [0] = {
- .start = 0x20200030,
- .end = 0x20300030 + 2,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static struct platform_device opencores_kbd_device = {
- .id = -1,
- .name = "opencores-kbd",
- .resource = opencores_kbd_resources,
- .num_resources = ARRAY_SIZE(opencores_kbd_resources),
-};
-#endif
-
-static struct platform_device *h8606_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_8250)
- &serial8250_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES)
- &opencores_kbd_device,
-#endif
-};
-
-static int __init H8606_init(void)
-{
- printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(H8606_init);
-
-static struct platform_device *H8606_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(H8606_early_devices,
- ARRAY_SIZE(H8606_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/Kconfig b/arch/blackfin/mach-bf533/boards/Kconfig
deleted file mode 100644
index 3fde0df..0000000
--- a/arch/blackfin/mach-bf533/boards/Kconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN533_STAMP
- help
- Select your board!
-
-config BFIN533_EZKIT
- bool "BF533-EZKIT"
- help
- BF533-EZKIT-LITE board support.
-
-config BFIN533_STAMP
- bool "BF533-STAMP"
- help
- BF533-STAMP board support.
-
-config BLACKSTAMP
- bool "BlackStamp"
- help
- Support for the BlackStamp board. Hardware info available at
- http://blackfin.uclinux.org/gf/project/blackstamp/
-
-config BFIN533_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF533"
- depends on (BF533)
- help
- CM-BF533 support for EVAL- and DEV-Board.
-
-config H8606_HVSISTEMAS
- bool "HV Sistemas H8606"
- depends on (BF532)
- help
- HV Sistemas H8606 board support.
-
-config BFIN532_IP0X
- bool "IP04/IP08 IP-PBX"
- depends on (BF532)
- help
- Core support for IP04/IP04 open hardware IP-PBX.
-
-endchoice
diff --git a/arch/blackfin/mach-bf533/boards/Makefile b/arch/blackfin/mach-bf533/boards/Makefile
deleted file mode 100644
index 35256d2..0000000
--- a/arch/blackfin/mach-bf533/boards/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf533/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN533_STAMP) += stamp.o
-obj-$(CONFIG_BFIN532_IP0X) += ip0x.o
-obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o
-obj-$(CONFIG_BLACKSTAMP) += blackstamp.o
-obj-$(CONFIG_H8606_HVSISTEMAS) += H8606.o
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
deleted file mode 100644
index fab69c7..0000000
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ /dev/null
@@ -1,523 +0,0 @@
-/*
- * Board Info File for the BlackStamp
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * 2008 Benjamin Matthews <bmat@lle.rochester.edu>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * More info about the BlackStamp at:
- * http://blackfin.uclinux.org/gf/project/blackstamp/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "BlackStamp";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF3,
- .end = IRQ_PF3,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 7,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF4, 0, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF5, 0, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF6, 0, "gpio-keys: BTN2"},
-}; /* Mapped to the first three PF Test Points */
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF8, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF9, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 40,
-}; /* This hasn't actually been used these pins
- * are (currently) free pins on the expansion connector */
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-};
-
-static int __init blackstamp_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
-
- ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- /*
- * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
- * the bfin-async-map driver takes care of flipping between
- * flash and ethernet when necessary.
- */
- ret = gpio_request(GPIO_PF0, "enet_cpld");
- if (!ret) {
- gpio_direction_output(GPIO_PF0, 1);
- gpio_free(GPIO_PF0);
- }
-#endif
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(blackstamp_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
deleted file mode 100644
index 4ef2fb0..0000000
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/mmc_spi.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF533";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x20308000,
- .end = 0x20308000 + 0xFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF6,
- .end = IRQ_PF6,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux+rootfs(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = ¶_flash_data,
- },
- .num_resources = 1,
- .resource = ¶_flash_resource,
-};
-#endif
-
-
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf533_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- ¶_flash_device,
-#endif
-};
-
-static int __init cm_bf533_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(cm_bf533_init);
-
-static struct platform_device *cm_bf533_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf533_early_devices,
- ARRAY_SIZE(cm_bf533_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
deleted file mode 100644
index d64d270..0000000
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ /dev/null
@@ -1,551 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF533-EZKIT";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20310300,
- .end = 0x20310300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions_a[] = {
- {
- .name = "bootloader(nor a)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor a)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data ezkit_flash_data_a = {
- .width = 2,
- .parts = ezkit_partitions_a,
- .nr_parts = ARRAY_SIZE(ezkit_partitions_a),
-};
-
-static struct resource ezkit_flash_resource_a = {
- .start = 0x20000000,
- .end = 0x200fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device_a = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data_a,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource_a,
-};
-
-static struct mtd_partition ezkit_partitions_b[] = {
- {
- .name = "file system(nor b)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data ezkit_flash_data_b = {
- .width = 2,
- .parts = ezkit_partitions_b,
- .nr_parts = ARRAY_SIZE(ezkit_partitions_b),
-};
-
-static struct resource ezkit_flash_resource_b = {
- .start = 0x20100000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device_b = {
- .name = "physmap-flash",
- .id = 4,
- .dev = {
- .platform_data = &ezkit_flash_data_b,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource_b,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
-static struct platdata_mtd_ram sram_data_a = {
- .mapname = "Flash A SRAM",
- .bankwidth = 2,
-};
-
-static struct resource sram_resource_a = {
- .start = 0x20240000,
- .end = 0x2024ffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device sram_device_a = {
- .name = "mtd-ram",
- .id = 8,
- .dev = {
- .platform_data = &sram_data_a,
- },
- .num_resources = 1,
- .resource = &sram_resource_a,
-};
-
-static struct platdata_mtd_ram sram_data_b = {
- .mapname = "Flash B SRAM",
- .bankwidth = 2,
-};
-
-static struct resource sram_resource_b = {
- .start = 0x202c0000,
- .end = 0x202cffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device sram_device_b = {
- .name = "mtd-ram",
- .id = 9,
- .dev = {
- .platform_data = &sram_data_b,
- },
- .num_resources = 1,
- .resource = &sram_resource_b,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF7, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF8, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF9, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF10, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 40,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device_a,
- &ezkit_flash_device_b,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
- &sram_device_a,
- &sram_device_b,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
deleted file mode 100644
index 39c8e85..0000000
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2007 David Rowe
- * 2006 Intratrade Ltd.
- * Ivan Danov <idanov@gmail.com>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "IP04/IP08";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if defined(CONFIG_BFIN532_IP0X)
-#if IS_ENABLED(CONFIG_DM9000)
-
-#include <linux/dm9000.h>
-
-static struct resource dm9000_resource1[] = {
- {
- .start = 0x20100000,
- .end = 0x20100000 + 1,
- .flags = IORESOURCE_MEM
- },{
- .start = 0x20100000 + 2,
- .end = 0x20100000 + 3,
- .flags = IORESOURCE_MEM
- },{
- .start = IRQ_PF15,
- .end = IRQ_PF15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
- }
-};
-
-static struct resource dm9000_resource2[] = {
- {
- .start = 0x20200000,
- .end = 0x20200000 + 1,
- .flags = IORESOURCE_MEM
- },{
- .start = 0x20200000 + 2,
- .end = 0x20200000 + 3,
- .flags = IORESOURCE_MEM
- },{
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
- }
-};
-
-/*
-* for the moment we limit ourselves to 16bit IO until some
-* better IO routines can be written and tested
-*/
-static struct dm9000_plat_data dm9000_platdata1 = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-static struct platform_device dm9000_device1 = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm9000_resource1),
- .resource = dm9000_resource1,
- .dev = {
- .platform_data = &dm9000_platdata1,
- }
-};
-
-static struct dm9000_plat_data dm9000_platdata2 = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-static struct platform_device dm9000_device2 = {
- .name = "dm9000",
- .id = 1,
- .num_resources = ARRAY_SIZE(dm9000_resource2),
- .resource = dm9000_resource2,
- .dev = {
- .platform_data = &dm9000_platdata2,
- }
-};
-
-#endif
-#endif
-
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0, /* if 1 - block!!! */
-};
-#endif
-
-/* Notice: for blackfin, the speed_hz is the value of register
- * SPI_BAUD, not the real baudrate */
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 2,
- .bus_num = 1,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- },
-#endif
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
-};
-
-static struct platform_device spi_bfin_master_device = {
- .name = "bfin-spi-master",
- .id = 1, /* Bus number */
- .dev = {
- .platform_data = &spi_bfin_master_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 1,
- .flags = IORESOURCE_MEM,
- },{
- .start = 0x20300000 + 2,
- .end = 0x20300000 + 3,
- .flags = IORESOURCE_MEM,
- },{
- .start = IRQ_PF11,
- .end = IRQ_PF11,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0, /* external OC */
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-
-static struct platform_device *ip0x_devices[] __initdata = {
-#if defined(CONFIG_BFIN532_IP0X)
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device1,
- &dm9000_device2,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &spi_bfin_master_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-};
-
-static int __init ip0x_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ip0x_init);
-
-static struct platform_device *ip0x_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ip0x_early_devices,
- ARRAY_SIZE(ip0x_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
deleted file mode 100644
index 27cbf2f..0000000
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ /dev/null
@@ -1,919 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/mmc_spi.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF533-STAMP";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC)
-static struct mtd_partition stamp_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data stamp_flash_data = {
- .width = 2,
- .parts = stamp_partitions,
- .nr_parts = ARRAY_SIZE(stamp_partitions),
-};
-
-static struct resource stamp_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x7BB07BB0, /* AMBCTL0 setting when accessing flash */
- .end = 0x7BB07BB0, /* AMBCTL1 setting when accessing flash */
- .flags = IORESOURCE_MEM,
- }, {
- .start = GPIO_PF0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device stamp_flash_device = {
- .name = "bfin-async-flash",
- .id = 0,
- .dev = {
- .platform_data = &stamp_flash_data,
- },
- .num_resources = ARRAY_SIZE(stamp_flash_resource),
- .resource = stamp_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
-static int bfin_mmc_spi_init(struct device *dev,
- irqreturn_t (*detect_int)(int, void *), void *data)
-{
- return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
- IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
- "mmc-spi-detect", data);
-}
-
-static void bfin_mmc_spi_exit(struct device *dev, void *data)
-{
- free_irq(MMC_SPI_CARD_DETECT_INT, data);
-}
-
-static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
- .init = bfin_mmc_spi_init,
- .exit = bfin_mmc_spi_exit,
- .detect_delay = 100, /* msecs */
-};
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
- .pio_interrupt = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- {
- .modalias = "ad1836",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = &bfin_mmc_spi_pdata,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF5, 0, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF6, 0, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF8, 0, "gpio-keys: BTN2"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF2, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF3, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 10,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_JOYSTICK_AD7142)
- {
- I2C_BOARD_INFO("ad7142_joystick", 0x2C),
- .irq = 39,
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = 39,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#include <asm/bfin_sport.h>
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static const unsigned ad73311_gpio[] = {
- GPIO_PF4,
-};
-
-static struct platform_device bfin_ad73311_machine = {
- .name = "bfin-snd-ad73311",
- .id = 1,
- .dev = {
- .platform_data = (void *)ad73311_gpio,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD74111)
-static struct platform_device bfin_ad74111_codec_device = {
- .name = "ad74111",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources =
- ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources =
- ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC)
- &stamp_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
- &bfin_ad73311_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
- &bfin_ad73311_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD74111)
- &bfin_ad74111_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
- &bfin_ac97,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */
- ret = gpio_request(GPIO_PF0, "net2272");
- if (ret)
- return ret;
-
- ret = gpio_request(GPIO_PF1, "net2272");
- if (ret) {
- gpio_free(GPIO_PF0);
- return ret;
- }
-
- ret = gpio_request(GPIO_PF11, "net2272");
- if (ret) {
- gpio_free(GPIO_PF0);
- gpio_free(GPIO_PF1);
- return ret;
- }
-
- gpio_direction_output(GPIO_PF0, 0);
- gpio_direction_output(GPIO_PF1, 1);
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF11, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF11, 1);
-#endif
-
- return 0;
-}
-
-static int __init stamp_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
-
- ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- /*
- * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
- * the bfin-async-map driver takes care of flipping between
- * flash and ethernet when necessary.
- */
- ret = gpio_request(GPIO_PF0, "enet_cpld");
- if (!ret) {
- gpio_direction_output(GPIO_PF0, 1);
- gpio_free(GPIO_PF0);
- }
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(stamp_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround pull up on cpld / flash pin not being strong enough */
- gpio_request(GPIO_PF0, "flash_cpld");
- gpio_direction_output(GPIO_PF0, 0);
-}
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
deleted file mode 100644
index 1f5988d..0000000
--- a/arch/blackfin/mach-bf533/dma.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
deleted file mode 100644
index 0e754ef..0000000
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 or 0.2 silicon - sorry */
-#if __SILICON_REVISION__ < 3
-# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
-#endif
-
-#if defined(__ADSPBF531__)
-# define ANOMALY_BF531 1
-#else
-# define ANOMALY_BF531 0
-#endif
-#if defined(__ADSPBF532__)
-# define ANOMALY_BF532 1
-#else
-# define ANOMALY_BF532 0
-#endif
-#if defined(__ADSPBF533__)
-# define ANOMALY_BF533 1
-#else
-# define ANOMALY_BF533 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated@the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
-#define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
-#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
-/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
-#define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event@Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Data CPLBs Should Prevent False Hardware Errors */
-#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
-/* Spontaneous Reset of Internal Voltage Regulator */
-#define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (1)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
-#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
-/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
-/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem@Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Internal voltage regulator can't be modified via register writes */
-#define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
-/* Watchpoints (Hardware Breakpoints) are not supported */
-#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
-/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
-#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
-/* Writing FIO_DIR can corrupt a programmable flag's data */
-#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
-/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
-#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
-/* Internal Clocking Modes on SPORT0 not supported */
-#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
-/* Internal voltage regulator does not wake up from an RTC wakeup */
-#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
-/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
-#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
-/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
-#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
-/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
-#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
-/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
-#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
-/* 32-bit SPORT DMA will be word reversed */
-#define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
-/* Incorrect status in the UART_IIR register */
-#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
-/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
-#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
-/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
-#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
-/* Incorrect Value Written to the Cycle Counters */
-#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
-/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
-#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
-/* Programmable Flag (PF3) functionality not supported in all PPI modes */
-#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
-/* Data store can be lost when targeting a cache line fill */
-#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
-/* Reserved Bits in SYSCFG Register Not Set@Power-On */
-#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
-/* Infinite Core Stall */
-#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
-/* PPI_FSx may glitch when generated by the on chip Timers. */
-#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
-#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
-/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
-#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
-/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
-#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up@CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* SPI clock polarity and phase bits incorrect during booting */
-#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> Is Not Set on Reset */
-#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
-/* SPI boot will not complete if there is a zero fill block in the loader file */
-#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
-/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
-#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
-#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
-#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
-#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
-/* Internal Voltage Regulator may not start up */
-#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h
deleted file mode 100644
index e3e05f8..0000000
--- a/arch/blackfin/mach-bf533/include/mach/bf533.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF533_H__
-#define __MACH_BF533_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_BIT 0x0FFFFFFF
-#define UART_ERROR_BIT 0xF0FFFFFF
-#define SPORT1_ERROR_BIT 0xFF0FFFFF
-#define SPI_ERROR_BIT 0xFFF0FFFF
-#define SPORT0_ERROR_BIT 0xFFFF0FFF
-#define PPI_ERROR_BIT 0xFFFFF0FF
-#define DMA_ERROR_BIT 0xFFFFFF0F
-#define PLLWAKE_ERROR_BIT 0xFFFFFFFF
-
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_BIT 0x0FFFFFFF
-#define DMA6_UARTRX_BIT 0xF0FFFFFF
-#define DMA5_SPI_BIT 0xFF0FFFFF
-#define DMA4_SPORT1TX_BIT 0xFFF0FFFF
-#define DMA3_SPORT1RX_BIT 0xFFFF0FFF
-#define DMA2_SPORT0TX_BIT 0xFFFFF0FF
-#define DMA1_SPORT0RX_BIT 0xFFFFFF0F
-#define DMA0_PPI_BIT 0xFFFFFFFF
-
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_BIT 0x0FFFFFFF
-#define MEMDMA1_BIT 0xF0FFFFFF
-#define MEMDMA0_BIT 0xFF0FFFFF
-#define PFB_BIT 0xFFF0FFFF
-#define PFA_BIT 0xFFFF0FFF
-#define TIMER2_BIT 0xFFFFF0FF
-#define TIMER1_BIT 0xFFFFFF0F
-#define TIMER0_BIT 0xFFFFFFFF
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF533
-#define CPU "BF533"
-#define CPUID 0x27a5
-#endif
-#ifdef CONFIG_BF532
-#define CPU "BF532"
-#define CPUID 0x27a5
-#endif
-#ifdef CONFIG_BF531
-#define CPU "BF531"
-#define CPUID 0x27a5
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF533_H__ */
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
deleted file mode 100644
index 08072c8..0000000
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 1
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
deleted file mode 100644
index e366207..0000000
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF533_FAMILY
-
-#include "bf533.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#include "defBF532.h"
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# include "cdefBF532.h"
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
deleted file mode 100644
index fd0cbe4..0000000
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ /dev/null
@@ -1,682 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF532_H
-#define _CDEF_BF532_H
-
-/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-
-/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
-
-/* DMA Traffic controls */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
-
-/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
-#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
-#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
-#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
-#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
-#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
-#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
-#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
-#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
-#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
-#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
-#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
-#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
-#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
-#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
-#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
-#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
-#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
-#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
-#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
-#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
-#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
-#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
-#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
-#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
-#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
-#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
-
-#if ANOMALY_05000311
-/* Keep at the CPP expansion to avoid circular header dependency loops */
-#define BFIN_WRITE_FIO_FLAG(name, val) \
- do { \
- unsigned long __flags; \
- __flags = hard_local_irq_save(); \
- bfin_write16(FIO_FLAG_##name, val); \
- bfin_read_CHIPID(); \
- hard_local_irq_restore(__flags); \
- } while (0)
-#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val)
-#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val)
-#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val)
-#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val)
-
-#define BFIN_READ_FIO_FLAG(name) \
- ({ \
- unsigned long __flags; \
- u16 __ret; \
- __flags = hard_local_irq_save(); \
- __ret = bfin_read16(FIO_FLAG_##name); \
- bfin_read_CHIPID(); \
- hard_local_irq_restore(__flags); \
- __ret; \
- })
-#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D)
-#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C)
-#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S)
-#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T)
-
-#else
-#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
-#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
-#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
-#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
-#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
-#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
-#endif
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
-
-/* UART Controller */
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
-/*
-#define UART_MSR
-*/
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
-
-/* SPI Controller */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* TIMER 0, 1, 2 Registers */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
-
-/* SPORT0 Controller */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-
-/* Parallel Peripheral Interface (PPI) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
-
-#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
deleted file mode 100644
index d438150..0000000
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ /dev/null
@@ -1,831 +0,0 @@
-/*
- * System & MMR bit and Address definitions for ADSP-BF532
- *
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF532_H
-#define _DEF_BF532_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR 0xFFC00104 /* System Configuration registe */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART_*.
- */
-#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
-#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
-#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
-#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
-#if 0
-#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
-#endif
-#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
-
-/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
-
-#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
-#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
-#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
-#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
-#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic controls */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-
-#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-
-#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
-
-#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-
-#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
- /* SIC_IAR0 Masks */
-
-#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Masks */
-
-#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Masks */
-#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x00000001 /* PPI Port Enable */
-#define PORT_DIR 0x00000002 /* PPI Port Direction */
-#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
-#define PORT_CFG 0x00000030 /* PPI Port Configuration */
-#define FLD_SEL 0x00000040 /* PPI Active Field Select */
-#define PACK_EN 0x00000080 /* PPI Packing Mode */
-#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x00003800 /* PPI Data Length */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#define POL 0x0000C000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x00000400 /* Field Indicator */
-#define FT_ERR 0x00000800 /* Frame Track Error */
-#define OVR 0x00001000 /* FIFO Overflow Error */
-#define UNDR 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET 0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
-
-/* ********** DMA CONTROLLER MASKS *********************8 */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
-#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
-#define PMAP 0x00007000 /* DMA Peripheral Map Field */
-
-#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
-#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
-#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001
-#define TIMEN1 0x0002
-#define TIMEN2 0x0004
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001
-#define TIMDIS1 0x0002
-#define TIMDIS2 0x0004
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x0001
-#define TIMIL1 0x0002
-#define TIMIL2 0x0004
-#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
-#define TRUN0 0x1000
-#define TRUN1 0x2000
-#define TRUN2 0x4000
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#define ERR_TYP(x) ((x & 0x03) << 14)
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN 0x00000001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
-#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
-#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-
-/* SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-
-#endif /* _DEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h
deleted file mode 100644
index fb34934..0000000
--- a/arch/blackfin/mach-bf533/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 12
-
-#define CH_PPI 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT0_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT1_TX 4
-#define CH_SPI 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_MEM_STREAM0_DEST 8 /* TX */
-#define CH_MEM_STREAM0_SRC 9 /* RX */
-#define CH_MEM_STREAM1_DEST 10 /* TX */
-#define CH_MEM_STREAM1_SRC 11 /* RX */
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h
deleted file mode 100644
index cce4f8f..0000000
--- a/arch/blackfin/mach-bf533/include/mach/gpio.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-
-#define PORT_F GPIO_PF0
-
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
deleted file mode 100644
index 7097337..0000000
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF533_IRQ_H_
-#define _BF533_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS 24
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
-#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
-#define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI BFIN_IRQ(13) /* DMA5 Interrupt (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */
-#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
-#define IRQ_PROG_INTA BFIN_IRQ(19) /* Programmable Flags A (8) */
-#define IRQ_PROG_INTB BFIN_IRQ(20) /* Programmable Flags B (8) */
-#define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */
-#define IRQ_WATCH BFIN_IRQ(23) /* Watch Dog Timer */
-
-#define SYS_IRQS 31
-
-#define IRQ_PF0 33
-#define IRQ_PF1 34
-#define IRQ_PF2 35
-#define IRQ_PF3 36
-#define IRQ_PF4 37
-#define IRQ_PF5 38
-#define IRQ_PF6 39
-#define IRQ_PF7 40
-#define IRQ_PF8 41
-#define IRQ_PF9 42
-#define IRQ_PF10 43
-#define IRQ_PF11 44
-#define IRQ_PF12 45
-#define IRQ_PF13 46
-#define IRQ_PF14 47
-#define IRQ_PF15 48
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF15 + 1)
-
-/* IAR0 BIT FIELDS */
-#define RTC_ERROR_POS 28
-#define UART_ERROR_POS 24
-#define SPORT1_ERROR_POS 20
-#define SPI_ERROR_POS 16
-#define SPORT0_ERROR_POS 12
-#define PPI_ERROR_POS 8
-#define DMA_ERROR_POS 4
-#define PLLWAKE_ERROR_POS 0
-
-/* IAR1 BIT FIELDS */
-#define DMA7_UARTTX_POS 28
-#define DMA6_UARTRX_POS 24
-#define DMA5_SPI_POS 20
-#define DMA4_SPORT1TX_POS 16
-#define DMA3_SPORT1RX_POS 12
-#define DMA2_SPORT0TX_POS 8
-#define DMA1_SPORT0RX_POS 4
-#define DMA0_PPI_POS 0
-
-/* IAR2 BIT FIELDS */
-#define WDTIMER_POS 28
-#define MEMDMA1_POS 24
-#define MEMDMA0_POS 20
-#define PFB_POS 16
-#define PFA_POS 12
-#define TIMER2_POS 8
-#define TIMER1_POS 4
-#define TIMER0_POS 0
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h
deleted file mode 100644
index 197af1a..0000000
--- a/arch/blackfin/mach-bf533/include/mach/mem_map.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * BF533 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x400
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF533 processors */
-
-#ifdef CONFIG_BF533
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0x14000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF532 processors */
-
-#ifdef CONFIG_BF532
-#define L1_CODE_START 0xFFA08000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0xC000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0xC000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF531 processors */
-
-#ifdef CONFIG_BF531
-#define L1_CODE_START 0xFFA08000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-#define L1_CODE_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x0000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h
deleted file mode 100644
index 94cca67..0000000
--- a/arch/blackfin/mach-bf533/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf533/include/mach/portmux.h b/arch/blackfin/mach-bf533/include/mach/portmux.h
deleted file mode 100644
index 96f5d91..0000000
--- a/arch/blackfin/mach-bf533/include/mach/portmux.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-
-#define P_SPORT1_TSCLK (P_DONTCARE)
-#define P_SPORT1_RSCLK (P_DONTCARE)
-#define P_SPORT0_TSCLK (P_DONTCARE)
-#define P_SPORT0_RSCLK (P_DONTCARE)
-#define P_UART0_RX (P_DONTCARE)
-#define P_UART0_TX (P_DONTCARE)
-#define P_SPORT1_DRSEC (P_DONTCARE)
-#define P_SPORT1_RFS (P_DONTCARE)
-#define P_SPORT1_DTPRI (P_DONTCARE)
-#define P_SPORT1_DTSEC (P_DONTCARE)
-#define P_SPORT1_TFS (P_DONTCARE)
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DONTCARE)
-#define P_SPORT0_RFS (P_DONTCARE)
-#define P_SPORT0_DTPRI (P_DONTCARE)
-#define P_SPORT0_DTSEC (P_DONTCARE)
-#define P_SPORT0_TFS (P_DONTCARE)
-#define P_SPORT0_DRPRI (P_DONTCARE)
-
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#define P_TMR2 (P_DONTCARE)
-#define P_TMR1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf533/ints-priority.c b/arch/blackfin/mach-bf533/ints-priority.c
deleted file mode 100644
index 8f714cf..0000000
--- a/arch/blackfin/mach-bf533/ints-priority.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_PLLWAKE_ERROR - 7) << PLLWAKE_ERROR_POS) |
- ((CONFIG_DMA_ERROR - 7) << DMA_ERROR_POS) |
- ((CONFIG_PPI_ERROR - 7) << PPI_ERROR_POS) |
- ((CONFIG_SPORT0_ERROR - 7) << SPORT0_ERROR_POS) |
- ((CONFIG_SPI_ERROR - 7) << SPI_ERROR_POS) |
- ((CONFIG_SPORT1_ERROR - 7) << SPORT1_ERROR_POS) |
- ((CONFIG_UART_ERROR - 7) << UART_ERROR_POS) |
- ((CONFIG_RTC_ERROR - 7) << RTC_ERROR_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_DMA0_PPI - 7) << DMA0_PPI_POS) |
- ((CONFIG_DMA1_SPORT0RX - 7) << DMA1_SPORT0RX_POS) |
- ((CONFIG_DMA2_SPORT0TX - 7) << DMA2_SPORT0TX_POS) |
- ((CONFIG_DMA3_SPORT1RX - 7) << DMA3_SPORT1RX_POS) |
- ((CONFIG_DMA4_SPORT1TX - 7) << DMA4_SPORT1TX_POS) |
- ((CONFIG_DMA5_SPI - 7) << DMA5_SPI_POS) |
- ((CONFIG_DMA6_UARTRX - 7) << DMA6_UARTRX_POS) |
- ((CONFIG_DMA7_UARTTX - 7) << DMA7_UARTTX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_TIMER0 - 7) << TIMER0_POS) |
- ((CONFIG_TIMER1 - 7) << TIMER1_POS) |
- ((CONFIG_TIMER2 - 7) << TIMER2_POS) |
- ((CONFIG_PFA - 7) << PFA_POS) |
- ((CONFIG_PFB - 7) << PFB_POS) |
- ((CONFIG_MEMDMA0 - 7) << MEMDMA0_POS) |
- ((CONFIG_MEMDMA1 - 7) << MEMDMA1_POS) |
- ((CONFIG_WDTIMER - 7) << WDTIMER_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
deleted file mode 100644
index 1d69b04..0000000
--- a/arch/blackfin/mach-bf537/Kconfig
+++ /dev/null
@@ -1,118 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF537 || BF534 || BF536)
-
-source "arch/blackfin/mach-bf537/boards/Kconfig"
-
-menu "BF537 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA_ERROR
- int "IRQ_DMA_ERROR Generic"
- default 7
-config IRQ_ERROR
- int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
- default 11
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_CAN_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PROG_INTA
- int "IRQ_PROG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile
deleted file mode 100644
index 56994b6..0000000
--- a/arch/blackfin/mach-bf537/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf537/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
deleted file mode 100644
index 60b7b29..0000000
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN537_STAMP
- help
- Select your board!
-
-config BFIN537_STAMP
- bool "BF537-STAMP"
- help
- BF537-STAMP board support.
-
-config BFIN537_BLUETECHNIX_CM_E
- bool "Bluetechnix CM-BF537E"
- depends on (BF537)
- help
- CM-BF537E support for EVAL- and DEV-Board.
-
-config BFIN537_BLUETECHNIX_CM_U
- bool "Bluetechnix CM-BF537U"
- depends on (BF537)
- help
- CM-BF537U support for EVAL- and DEV-Board.
-
-config BFIN537_BLUETECHNIX_TCM
- bool "Bluetechnix TCM-BF537"
- depends on (BF537)
- help
- TCM-BF537 support for EVAL- and DEV-Board.
-
-config PNAV10
- bool "PNAV board"
- depends on (BF537)
- help
- PNAV board support.
-
-config CAMSIG_MINOTAUR
- bool "Cambridge Signal Processing LTD Minotaur"
- depends on (BF537)
- help
- Board supply package for CSP Minotaur
-
-config DNP5370
- bool "SSV Dil/NetPC DNP/5370"
- depends on (BF537)
- help
- Board supply package for DNP/5370 DIL64 module
-
-endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
deleted file mode 100644
index 47a1acc..0000000
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf537/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN537_STAMP) += stamp.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_E) += cm_bf537e.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
-obj-$(CONFIG_PNAV10) += pnav10.o
-obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
-obj-$(CONFIG_DNP5370) += dnp5370.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
deleted file mode 100644
index 1e1014d..0000000
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF537E";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
-
-/* SPORT SPI controller data */
-static struct bfin5xx_spi_master bfin_sport_spi0_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
- P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
-};
-
-static struct resource bfin_sport_spi0_resource[] = {
- [0] = {
- .start = SPORT0_TCR1,
- .end = SPORT0_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi0_device = {
- .name = "bfin-sport-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
- .resource = bfin_sport_spi0_resource,
- .dev = {
- .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bfin_sport_spi1_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
-};
-
-static struct resource bfin_sport_spi1_resource[] = {
- [0] = {
- .start = SPORT1_TCR1,
- .end = SPORT1_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi1_device = {
- .name = "bfin-sport-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
- .resource = bfin_sport_spi1_resource,
- .dev = {
- .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
- },
-};
-
-#endif /* sport spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG13,
- .end = IRQ_PG13,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PF4 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
-|| IS_ENABLED(CONFIG_BFIN_SPORT)
-unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
-};
-#endif
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537e_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
- &bfin_sport0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
- &bfin_sport_spi0_device,
- &bfin_sport_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PG14, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PG14 */
- gpio_direction_output(GPIO_PG14, 0);
- mdelay(2);
- gpio_set_value(GPIO_PG14, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf537e_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf537e_init);
-
-static struct platform_device *cm_bf537e_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537e_early_devices,
- ARRAY_SIZE(cm_bf537e_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
deleted file mode 100644
index d056db9..0000000
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ /dev/null
@@ -1,802 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/mmc_spi.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF537U";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20200000,
- .end = 0x20200000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PH14,
- .end = IRQ_PH14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PH0 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537u_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PH15, driver_name);
- if (ret)
- return ret;
-
- ret = gpio_request(GPIO_PH13, "net2272");
- if (ret) {
- gpio_free(GPIO_PH15);
- return ret;
- }
-
- /* Set PH15 Low make /AMS2 work properly */
- gpio_direction_output(GPIO_PH15, 0);
-
- /* enable CLKBUF output */
- bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PH13, 0);
- mdelay(2);
- gpio_set_value(GPIO_PH13, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf537u_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf537u_init);
-
-static struct platform_device *cm_bf537u_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537u_early_devices,
- ARRAY_SIZE(cm_bf537u_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
deleted file mode 100644
index c4a8ffb..0000000
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * This is the configuration for SSV Dil/NetPC DNP/5370 board.
- *
- * DIL module: http://www.dilnetpc.com/dnp0086.htm
- * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
- *
- * Copyright 2010 3ality Digital Systems
- * Copyright 2005 National ICT Australia (NICTA)
- * Copyright 2004-2006 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/spi/mmc_spi.h>
-#include <linux/phy.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "DNP/5370";
-#define FLASH_MAC 0x202f0000
-#define CONFIG_MTD_PHYSMAP_LEN 0x300000
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition asmb_flash_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x30000,
- .offset = 0,
- }, {
- .name = "linux kernel and rootfs(nor)",
- .size = 0x300000 - 0x30000 - 0x10000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "MAC address(nor)",
- .size = 0x10000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = MTD_WRITEABLE,
- }
-};
-
-static struct physmap_flash_data asmb_flash_data = {
- .width = 1,
- .parts = asmb_flash_partitions,
- .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
-};
-
-static struct resource asmb_flash_resource = {
- .start = 0x20000000,
- .end = 0x202fffff,
- .flags = IORESOURCE_MEM,
-};
-
-/* 4 MB NOR flash attached to async memory banks 0-2,
- * therefore only 3 MB visible.
- */
-static struct platform_device asmb_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &asmb_flash_data,
- },
- .num_resources = 1,
- .resource = &asmb_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0, /* use no dma transfer with this chip*/
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-/* This mapping is for at45db642 it has 1056 page size,
- * partition size and offset should be page aligned
- */
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "JFFS2 dataflash(nor)",
-#ifdef CONFIG_MTD_PAGESIZE_1024
- .offset = 0x40000,
- .size = 0x7C0000,
-#else
- .offset = 0x0,
- .size = 0x840000,
-#endif
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "mtd_dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
- .type = "mtd_dataflash",
-};
-
-static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
- .enable_dma = 0, /* use no dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-/* SD/MMC card reader at SPI bus */
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-/* 8 Megabyte Atmel NOR flash chip at SPI bus */
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- {
- .modalias = "mtd_dataflash",
- .max_speed_hz = 16700000,
- .bus_num = 0,
- .chip_select = 2,
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &spi_dataflash_chip_info,
- .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
- },
-#endif
-};
-
-/* SPI controller data */
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct bfin5xx_spi_master spi_bfin_master_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device spi_bfin_master_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &spi_bfin_master_info, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct platform_device *dnp5370_devices[] __initdata = {
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &asmb_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &spi_bfin_master_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-};
-
-static int __init dnp5370_init(void)
-{
- printk(KERN_INFO "DNP/5370: registering device resources\n");
- platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
- printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
- ARRAY_SIZE(bfin_spi_board_info));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
- return 0;
-}
-arch_initcall(dnp5370_init);
-
-/*
- * Currently the MAC address is saved in Flash by U-Boot
- */
-int bfin_get_ether_addr(char *addr)
-{
- *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
- *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
deleted file mode 100644
index dd7bda0..0000000
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ /dev/null
@@ -1,585 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Cambridge Signal Processing
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/sl811.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "CamSig Minotaur BF537";
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = IRQ_PF6, /* Card Detect PF6 */
- .end = IRQ_PF6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-
-/* Partition sizes */
-#define FLASH_SIZE 0x00400000
-#define PSIZE_UBOOT 0x00030000
-#define PSIZE_INITRAMFS 0x00240000
-
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = PSIZE_UBOOT,
- .offset = 0x000000,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "initramfs(spi)",
- .size = PSIZE_INITRAMFS,
- .offset = PSIZE_UBOOT
- }, {
- .name = "opt(spi)",
- .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
- .offset = PSIZE_UBOOT + PSIZE_INITRAMFS,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-static struct platform_device *minotaur_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-};
-
-static int __init minotaur_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(minotaur_init);
-
-static struct platform_device *minotaur_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(minotaur_early_devices,
- ARRAY_SIZE(minotaur_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
deleted file mode 100644
index 06a50dd..0000000
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI PNAV-1.0";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-{
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF2,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
-},
-#endif
-
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
-static struct platform_device bfin_fb_device = {
- .name = "bf537-lq035",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- &bfin_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-};
-
-static int __init pnav_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(pnav_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
deleted file mode 100644
index 400e669..0000000
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ /dev/null
@@ -1,3019 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/i2c.h>
-#include <linux/platform_data/adp5588.h>
-#include <linux/etherdevice.h>
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/sl811.h>
-#include <linux/spi/mmc_spi.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
-#include <linux/regulator/fixed.h>
-#endif
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <linux/regulator/userspace-consumer.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF537-STAMP";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB804,
- .end = 0x203FB804 + 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_SL811_HCD)
-static struct resource sl811_hcd_resources[] = {
- {
- .start = 0x20340000,
- .end = 0x20340000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20340004,
- .end = 0x20340004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
-void sl811_port_power(struct device *dev, int is_on)
-{
- gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
- gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
-}
-#endif
-
-static struct sl811_platform_data sl811_priv = {
- .potpg = 10,
- .power = 250, /* == 500mA */
-#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
- .port_power = &sl811_port_power,
-#endif
-};
-
-static struct platform_device sl811_hcd_device = {
- .name = "sl811-hcd",
- .id = 0,
- .dev = {
- .platform_data = &sl811_priv,
- },
- .num_resources = ARRAY_SIZE(sl811_hcd_resources),
- .resource = sl811_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20360000,
- .end = 0x20360000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20360004,
- .end = 0x20360004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF3,
- .end = IRQ_PF3,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN_RX,
- .end = IRQ_CAN_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_TX,
- .end = IRQ_CAN_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_ERROR,
- .end = IRQ_CAN_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
-const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
-
-static struct mtd_partition bfin_plat_nand_partitions[] = {
- {
- .name = "linux kernel(nand)",
- .size = 0x400000,
- .offset = 0,
- }, {
- .name = "file system(nand)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-#define BFIN_NAND_PLAT_CLE 2
-#define BFIN_NAND_PLAT_ALE 1
-static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
- else
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
-}
-
-#define BFIN_NAND_PLAT_READY GPIO_PF3
-static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(BFIN_NAND_PLAT_READY);
-}
-
-static struct platform_nand_data bfin_plat_nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_delay = 30,
- .part_probe_types = part_probes,
- .partitions = bfin_plat_nand_partitions,
- .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
- },
- .ctrl = {
- .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
- .dev_ready = bfin_plat_nand_dev_ready,
- },
-};
-
-#define MAX(x, y) (x > y ? x : y)
-static struct resource bfin_plat_nand_resources = {
- .start = 0x20212000,
- .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device bfin_async_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_plat_nand_resources,
- .dev = {
- .platform_data = &bfin_plat_nand_data,
- },
-};
-
-static void bfin_plat_nand_init(void)
-{
- gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
- gpio_direction_input(BFIN_NAND_PLAT_READY);
-}
-#else
-static void bfin_plat_nand_init(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition stamp_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x400000 - 0x40000 - 0x180000 - 0x10000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "MAC Address(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x3F0000,
- .mask_flags = MTD_WRITEABLE,
- }
-};
-
-static struct physmap_flash_data stamp_flash_data = {
- .width = 2,
- .parts = stamp_partitions,
- .nr_parts = ARRAY_SIZE(stamp_partitions),
-#ifdef CONFIG_ROMKERNEL
- .probe_type = "map_rom",
-#endif
-};
-
-static struct resource stamp_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device stamp_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &stamp_flash_data,
- },
- .num_resources = 1,
- .resource = &stamp_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- /* .type = "m25p64", */
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
-#include <linux/input/ad714x.h>
-
-static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
- {
- .start_stage = 0,
- .end_stage = 7,
- .max_coord = 128,
- },
-};
-
-static struct ad714x_button_plat ad7147_spi_button_plat[] = {
- {
- .keycode = BTN_FORWARD,
- .l_mask = 0,
- .h_mask = 0x600,
- },
- {
- .keycode = BTN_LEFT,
- .l_mask = 0,
- .h_mask = 0x500,
- },
- {
- .keycode = BTN_MIDDLE,
- .l_mask = 0,
- .h_mask = 0x800,
- },
- {
- .keycode = BTN_RIGHT,
- .l_mask = 0x100,
- .h_mask = 0x400,
- },
- {
- .keycode = BTN_BACK,
- .l_mask = 0x200,
- .h_mask = 0x400,
- },
-};
-static struct ad714x_platform_data ad7147_spi_platform_data = {
- .slider_num = 1,
- .button_num = 5,
- .slider = ad7147_spi_slider_plat,
- .button = ad7147_spi_button_plat,
- .stage_cfg_reg = {
- {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
- {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600},
- {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150},
- {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150},
- {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300},
- {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150},
- },
- .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
-#include <linux/input/ad714x.h>
-static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
- {
- .keycode = BTN_1,
- .l_mask = 0,
- .h_mask = 0x1,
- },
- {
- .keycode = BTN_2,
- .l_mask = 0,
- .h_mask = 0x2,
- },
- {
- .keycode = BTN_3,
- .l_mask = 0,
- .h_mask = 0x4,
- },
- {
- .keycode = BTN_4,
- .l_mask = 0x0,
- .h_mask = 0x8,
- },
-};
-static struct ad714x_platform_data ad7142_i2c_platform_data = {
- .button_num = 4,
- .button = ad7142_i2c_button_plat,
- .stage_cfg_reg = {
- /* fixme: figure out right setting for all comoponent according
- * to hardware feature of EVAL-AD7142EB board */
- {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- },
- .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S90)
-static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1200)
-static unsigned short ad2s1200_platform_data[] = {
- /* used as SAMPLE and RDVEL */
- GPIO_PF5, GPIO_PF6, 0
-};
-
-static struct bfin5xx_spi_chip ad2s1200_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1210)
-static unsigned short ad2s1210_platform_data[] = {
- /* use as SAMPLE, A0, A1 */
- GPIO_PF7, GPIO_PF8, GPIO_PF9,
-# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
- /* the RES0 and RES1 pins */
- GPIO_PF4, GPIO_PF5,
-# endif
- 0,
-};
-
-static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_AD7314)
-static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7816)
-static unsigned short ad7816_platform_data[] = {
- GPIO_PF4, /* rdwr_pin */
- GPIO_PF5, /* convert_pin */
- GPIO_PF7, /* busy_pin */
- 0,
-};
-
-static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7310)
-static unsigned long adt7310_platform_data[3] = {
-/* INT bound temperature alarm event. line 1 */
- IRQ_PG4, IRQF_TRIGGER_LOW,
-/* CT bound temperature alarm event irq_flags. line 0 */
- IRQF_TRIGGER_LOW,
-};
-
-static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7298)
-static unsigned short ad7298_platform_data[] = {
- GPIO_PF7, /* busy_pin */
- 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_SPI)
-static unsigned long adt7316_spi_data[2] = {
- IRQF_TRIGGER_LOW, /* interrupt flags */
- GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
-};
-
-static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
-
-static int bfin_mmc_spi_init(struct device *dev,
- irqreturn_t (*detect_int)(int, void *), void *data)
-{
- return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
- IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
-}
-
-static void bfin_mmc_spi_exit(struct device *dev, void *data)
-{
- free_irq(MMC_SPI_CARD_DETECT_INT, data);
-}
-
-static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
- .init = bfin_mmc_spi_init,
- .exit = bfin_mmc_spi_exit,
- .detect_delay = 100, /* msecs */
-};
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
- .pio_interrupt = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-#include <linux/spi/ad7877.h>
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ENC28J60)
-static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
- .enable_dma = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADF702X)
-#include <linux/spi/adf702x.h>
-#define TXREG 0x0160A470
-static const u32 adf7021_regs[] = {
- 0x09608FA0,
- 0x00575011,
- 0x00A7F092,
- 0x2B141563,
- 0x81F29E94,
- 0x00003155,
- 0x050A4F66,
- 0x00000007,
- 0x00000008,
- 0x000231E9,
- 0x3296354A,
- 0x891A2B3B,
- 0x00000D9C,
- 0x0000000D,
- 0x0000000E,
- 0x0000000F,
-};
-
-static struct adf702x_platform_data adf7021_platform_data = {
- .regs_base = (void *)SPORT1_TCR1,
- .dma_ch_rx = CH_SPORT1_RX,
- .dma_ch_tx = CH_SPORT1_TX,
- .irq_sport_err = IRQ_SPORT1_ERROR,
- .gpio_int_rfs = GPIO_PF8,
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0},
- .adf702x_model = MODEL_ADF7021,
- .adf702x_regs = adf7021_regs,
- .tx_reg = TXREG,
-};
-static inline void adf702x_mac_init(void)
-{
- eth_random_addr(adf7021_platform_data.mac_addr);
-}
-#else
-static inline void adf702x_mac_init(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
-#include <linux/spi/ads7846.h>
-static int ads7873_get_pendown_state(void)
-{
- return gpio_get_value(GPIO_PF6);
-}
-
-static struct ads7846_platform_data __initdata ad7873_pdata = {
- .model = 7873, /* AD7873 */
- .x_max = 0xfff,
- .y_max = 0xfff,
- .x_plate_ohms = 620,
- .debounce_max = 1,
- .debounce_rep = 0,
- .debounce_tol = (~0),
- .get_pendown_state = ads7873_get_pendown_state,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "SPI Dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
-};
-
-/* DataFlash chip */
-static struct bfin5xx_spi_chip data_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7476)
-static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- { /* DataFlash chip */
- .modalias = "mtd_dataflash",
- .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &data_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- {
- .modalias = "ad1836",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-
-#ifdef CONFIG_SND_SOC_AD193X_SPI
- {
- .modalias = "ad193x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
- {
- .modalias = "adav801",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
- {
- .modalias = "ad714x_captouch",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .irq = IRQ_PF4,
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_3,
- .platform_data = &ad7147_spi_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S90)
- {
- .modalias = "ad2s90",
- .bus_num = 0,
- .chip_select = 3, /* change it for your board */
- .mode = SPI_MODE_3,
- .platform_data = NULL,
- .controller_data = &ad2s90_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1200)
- {
- .modalias = "ad2s1200",
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad2s1200_platform_data,
- .controller_data = &ad2s1200_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1210)
- {
- .modalias = "ad2s1210",
- .max_speed_hz = 8192000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad2s1210_platform_data,
- .controller_data = &ad2s1210_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_AD7314)
- {
- .modalias = "ad7314",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .controller_data = &ad7314_spi_chip_info,
- .mode = SPI_MODE_1,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7816)
- {
- .modalias = "ad7818",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad7816_platform_data,
- .controller_data = &ad7816_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7310)
- {
- .modalias = "adt7310",
- .max_speed_hz = 1000000,
- .irq = IRQ_PG5, /* CT alarm event. Line 0 */
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = adt7310_platform_data,
- .controller_data = &adt7310_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7298)
- {
- .modalias = "ad7298",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad7298_platform_data,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_SPI)
- {
- .modalias = "adt7316",
- .max_speed_hz = 1000000,
- .irq = IRQ_PG5, /* interrupt line */
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = adt7316_spi_data,
- .controller_data = &adt7316_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = &bfin_mmc_spi_pdata,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF6,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF7,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_ENC28J60)
- {
- .modalias = "enc28j60",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .irq = IRQ_PF6,
- .bus_num = 0,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .controller_data = &enc28j60_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PF6,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADF702X)
- {
- .modalias = "adf702x",
- .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .platform_data = &adf7021_platform_data,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
- {
- .modalias = "ads7846",
- .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .irq = IRQ_PF6,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .platform_data = &ad7873_pdata,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_AD7476)
- {
- .modalias = "ad7476", /* Name of spi_driver for this device */
- .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. */
- .platform_data = NULL, /* No spi_driver specific config */
- .controller_data = &spi_ad7476_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7753)
- {
- .modalias = "ade7753",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7754)
- {
- .modalias = "ade7754",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7758)
- {
- .modalias = "ade7758",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7759)
- {
- .modalias = "ade7759",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7854_SPI)
- {
- .modalias = "ade7854",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16060)
- {
- .modalias = "adis16060_r",
- .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_0,
- },
- {
- .modalias = "adis16060_w",
- .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2, /* CS for write, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16130)
- {
- .modalias = "adis16130",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS for read, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16201)
- {
- .modalias = "adis16201",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16203)
- {
- .modalias = "adis16203",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16204)
- {
- .modalias = "adis16204",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16209)
- {
- .modalias = "adis16209",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16220)
- {
- .modalias = "adis16220",
- .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16240)
- {
- .modalias = "adis16240",
- .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16260)
- {
- .modalias = "adis16260",
- .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16261)
- {
- .modalias = "adis16261",
- .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16300)
- {
- .modalias = "adis16300",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16350)
- {
- .modalias = "adis16364",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16400)
- {
- .modalias = "adis16400",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
-
-/* SPORT SPI controller data */
-static struct bfin5xx_spi_master bfin_sport_spi0_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
- P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
-};
-
-static struct resource bfin_sport_spi0_resource[] = {
- [0] = {
- .start = SPORT0_TCR1,
- .end = SPORT0_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi0_device = {
- .name = "bfin-sport-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
- .resource = bfin_sport_spi0_resource,
- .dev = {
- .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bfin_sport_spi1_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
-};
-
-static struct resource bfin_sport_spi1_resource[] = {
- [0] = {
- .start = SPORT1_TCR1,
- .end = SPORT1_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi1_device = {
- .name = "bfin-sport-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
- .resource = bfin_sport_spi1_resource,
- .dev = {
- .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
- },
-};
-
-#endif /* sport spi master and devices */
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
-static struct platform_device bfin_fb_device = {
- .name = "bf537_lq035",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 0, /* let something else control the LCD Blacklight */
- .gpio_bl = GPIO_PF7,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_PPI,
- .dma_ch = CH_PPI,
- .irq_err = IRQ_PPI_ERROR,
- .base = (void __iomem *)PPI_CONTROL,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PF10;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF537",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | XFR_TYPE | 0x0020),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG7,
- .end = GPIO_PG7,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PG6,
- .end = GPIO_PG6,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
-static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
- [0] = KEY_GRAVE,
- [1] = KEY_1,
- [2] = KEY_2,
- [3] = KEY_3,
- [4] = KEY_4,
- [5] = KEY_5,
- [6] = KEY_6,
- [7] = KEY_7,
- [8] = KEY_8,
- [9] = KEY_9,
- [10] = KEY_0,
- [11] = KEY_MINUS,
- [12] = KEY_EQUAL,
- [13] = KEY_BACKSLASH,
- [15] = KEY_KP0,
- [16] = KEY_Q,
- [17] = KEY_W,
- [18] = KEY_E,
- [19] = KEY_R,
- [20] = KEY_T,
- [21] = KEY_Y,
- [22] = KEY_U,
- [23] = KEY_I,
- [24] = KEY_O,
- [25] = KEY_P,
- [26] = KEY_LEFTBRACE,
- [27] = KEY_RIGHTBRACE,
- [29] = KEY_KP1,
- [30] = KEY_KP2,
- [31] = KEY_KP3,
- [32] = KEY_A,
- [33] = KEY_S,
- [34] = KEY_D,
- [35] = KEY_F,
- [36] = KEY_G,
- [37] = KEY_H,
- [38] = KEY_J,
- [39] = KEY_K,
- [40] = KEY_L,
- [41] = KEY_SEMICOLON,
- [42] = KEY_APOSTROPHE,
- [43] = KEY_BACKSLASH,
- [45] = KEY_KP4,
- [46] = KEY_KP5,
- [47] = KEY_KP6,
- [48] = KEY_102ND,
- [49] = KEY_Z,
- [50] = KEY_X,
- [51] = KEY_C,
- [52] = KEY_V,
- [53] = KEY_B,
- [54] = KEY_N,
- [55] = KEY_M,
- [56] = KEY_COMMA,
- [57] = KEY_DOT,
- [58] = KEY_SLASH,
- [60] = KEY_KPDOT,
- [61] = KEY_KP7,
- [62] = KEY_KP8,
- [63] = KEY_KP9,
- [64] = KEY_SPACE,
- [65] = KEY_BACKSPACE,
- [66] = KEY_TAB,
- [67] = KEY_KPENTER,
- [68] = KEY_ENTER,
- [69] = KEY_ESC,
- [70] = KEY_DELETE,
- [74] = KEY_KPMINUS,
- [76] = KEY_UP,
- [77] = KEY_DOWN,
- [78] = KEY_RIGHT,
- [79] = KEY_LEFT,
-};
-
-static struct adp5588_kpad_platform_data adp5588_kpad_data = {
- .rows = 8,
- .cols = 10,
- .keymap = adp5588_keymap,
- .keymapsize = ARRAY_SIZE(adp5588_keymap),
- .repeat = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
-#include <linux/mfd/adp5520.h>
-
- /*
- * ADP5520/5501 Backlight Data
- */
-
-static struct adp5520_backlight_platform_data adp5520_backlight_data = {
- .fade_in = ADP5520_FADE_T_1200ms,
- .fade_out = ADP5520_FADE_T_1200ms,
- .fade_led_law = ADP5520_BL_LAW_LINEAR,
- .en_ambl_sens = 1,
- .abml_filt = ADP5520_BL_AMBL_FILT_640ms,
- .l1_daylight_max = ADP5520_BL_CUR_mA(15),
- .l1_daylight_dim = ADP5520_BL_CUR_mA(0),
- .l2_office_max = ADP5520_BL_CUR_mA(7),
- .l2_office_dim = ADP5520_BL_CUR_mA(0),
- .l3_dark_max = ADP5520_BL_CUR_mA(3),
- .l3_dark_dim = ADP5520_BL_CUR_mA(0),
- .l2_trip = ADP5520_L2_COMP_CURR_uA(700),
- .l2_hyst = ADP5520_L2_COMP_CURR_uA(50),
- .l3_trip = ADP5520_L3_COMP_CURR_uA(80),
- .l3_hyst = ADP5520_L3_COMP_CURR_uA(20),
-};
-
- /*
- * ADP5520/5501 LEDs Data
- */
-
-static struct led_info adp5520_leds[] = {
- {
- .name = "adp5520-led1",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
- },
-#ifdef ADP5520_EN_ALL_LEDS
- {
- .name = "adp5520-led2",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1,
- },
- {
- .name = "adp5520-led3",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2,
- },
-#endif
-};
-
-static struct adp5520_leds_platform_data adp5520_leds_data = {
- .num_leds = ARRAY_SIZE(adp5520_leds),
- .leds = adp5520_leds,
- .fade_in = ADP5520_FADE_T_600ms,
- .fade_out = ADP5520_FADE_T_600ms,
- .led_on_time = ADP5520_LED_ONT_600ms,
-};
-
- /*
- * ADP5520 GPIO Data
- */
-
-static struct adp5520_gpio_platform_data adp5520_gpio_data = {
- .gpio_start = 50,
- .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
- .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
-};
-
- /*
- * ADP5520 Keypad Data
- */
-
-static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
- [ADP5520_KEY(0, 0)] = KEY_GRAVE,
- [ADP5520_KEY(0, 1)] = KEY_1,
- [ADP5520_KEY(0, 2)] = KEY_2,
- [ADP5520_KEY(0, 3)] = KEY_3,
- [ADP5520_KEY(1, 0)] = KEY_4,
- [ADP5520_KEY(1, 1)] = KEY_5,
- [ADP5520_KEY(1, 2)] = KEY_6,
- [ADP5520_KEY(1, 3)] = KEY_7,
- [ADP5520_KEY(2, 0)] = KEY_8,
- [ADP5520_KEY(2, 1)] = KEY_9,
- [ADP5520_KEY(2, 2)] = KEY_0,
- [ADP5520_KEY(2, 3)] = KEY_MINUS,
- [ADP5520_KEY(3, 0)] = KEY_EQUAL,
- [ADP5520_KEY(3, 1)] = KEY_BACKSLASH,
- [ADP5520_KEY(3, 2)] = KEY_BACKSPACE,
- [ADP5520_KEY(3, 3)] = KEY_ENTER,
-};
-
-static struct adp5520_keys_platform_data adp5520_keys_data = {
- .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
- .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
- .keymap = adp5520_keymap,
- .keymapsize = ARRAY_SIZE(adp5520_keymap),
- .repeat = 0,
-};
-
- /*
- * ADP5520/5501 Multifunction Device Init Data
- */
-
-static struct adp5520_platform_data adp5520_pdev_data = {
- .backlight = &adp5520_backlight_data,
- .leds = &adp5520_leds_data,
- .gpio = &adp5520_gpio_data,
- .keys = &adp5520_keys_data,
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_ADP5588)
-static struct adp5588_gpio_platform_data adp5588_gpio_data = {
- .gpio_start = 50,
- .pullup_dis_mask = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
-#include <linux/platform_data/adp8870.h>
-static struct led_info adp8870_leds[] = {
- {
- .name = "adp8870-led7",
- .default_trigger = "none",
- .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms,
- },
-};
-
-
-static struct adp8870_backlight_platform_data adp8870_pdata = {
- .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 |
- ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */
- .pwm_assign = 0, /* 1 = Enables PWM mode */
-
- .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */
- .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */
- .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
-
- .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
- .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */
-
- .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
-
- .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
- .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
- .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
- .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
- .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */
- .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */
-
- .leds = adp8870_leds,
- .num_leds = ARRAY_SIZE(adp8870_leds),
- .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
- .led_fade_in = ADP8870_FADE_T_600ms,
- .led_fade_out = ADP8870_FADE_T_600ms,
- .led_on_time = ADP8870_LED_ONT_200ms,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
-#include <linux/platform_data/adp8860.h>
-static struct led_info adp8860_leds[] = {
- {
- .name = "adp8860-led7",
- .default_trigger = "none",
- .flags = ADP8860_LED_D7 | ADP8860_LED_OFFT_600ms,
- },
-};
-
-static struct adp8860_backlight_platform_data adp8860_pdata = {
- .bl_led_assign = ADP8860_BL_D1 | ADP8860_BL_D2 | ADP8860_BL_D3 |
- ADP8860_BL_D4 | ADP8860_BL_D5 | ADP8860_BL_D6, /* 1 = Backlight 0 = Individual LED */
-
- .bl_fade_in = ADP8860_FADE_T_1200ms, /* Backlight Fade-In Timer */
- .bl_fade_out = ADP8860_FADE_T_1200ms, /* Backlight Fade-Out Timer */
- .bl_fade_law = ADP8860_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
-
- .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
- .abml_filt = ADP8860_BL_AMBL_FILT_320ms, /* Light sensor filter time */
-
- .l1_daylight_max = ADP8860_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l1_daylight_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_office_max = ADP8860_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_office_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_dark_max = ADP8860_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_dark_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
-
- .l2_trip = ADP8860_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l2_hyst = ADP8860_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l3_trip = ADP8860_L3_COMP_CURR_uA(43), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */
- .l3_hyst = ADP8860_L3_COMP_CURR_uA(11), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */
-
- .leds = adp8860_leds,
- .num_leds = ARRAY_SIZE(adp8860_leds),
- .led_fade_law = ADP8860_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
- .led_fade_in = ADP8860_FADE_T_600ms,
- .led_fade_out = ADP8860_FADE_T_600ms,
- .led_on_time = ADP8860_LED_ONT_200ms,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
-static struct regulator_consumer_supply ad5398_consumer = {
- .supply = "current",
-};
-
-static struct regulator_init_data ad5398_regulator_data = {
- .constraints = {
- .name = "current range",
- .max_uA = 120000,
- .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &ad5398_consumer,
-};
-
-#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
-static struct platform_device ad5398_virt_consumer_device = {
- .name = "reg-virt-consumer",
- .id = 0,
- .dev = {
- .platform_data = "current", /* Passed to driver */
- },
-};
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-static struct regulator_bulk_data ad5398_bulk_data = {
- .supply = "current",
-};
-
-static struct regulator_userspace_consumer_data ad5398_userspace_comsumer_data = {
- .name = "ad5398",
- .num_supplies = 1,
- .supplies = &ad5398_bulk_data,
-};
-
-static struct platform_device ad5398_userspace_consumer_device = {
- .name = "reg-userspace-consumer",
- .id = 0,
- .dev = {
- .platform_data = &ad5398_userspace_comsumer_data,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7410)
-/* INT bound temperature alarm event. line 1 */
-static unsigned long adt7410_platform_data[2] = {
- IRQ_PG4, IRQF_TRIGGER_LOW,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_I2C)
-/* INT bound temperature alarm event. line 1 */
-static unsigned long adt7316_i2c_data[2] = {
- IRQF_TRIGGER_LOW, /* interrupt flags */
- GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#ifdef CONFIG_SND_SOC_AD193X_I2C
- {
- I2C_BOARD_INFO("ad1937", 0x04),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
- {
- I2C_BOARD_INFO("adav803", 0x10),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
- {
- I2C_BOARD_INFO("ad7142_captouch", 0x2C),
- .irq = IRQ_PG5,
- .platform_data = (void *)&ad7142_i2c_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7150)
- {
- I2C_BOARD_INFO("ad7150", 0x48),
- .irq = IRQ_PG5, /* fixme: use real interrupt number */
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7152)
- {
- I2C_BOARD_INFO("ad7152", 0x48),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD774X)
- {
- I2C_BOARD_INFO("ad774x", 0x48),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADE7854_I2C)
- {
- I2C_BOARD_INFO("ade7854", 0x38),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_LM75)
- {
- I2C_BOARD_INFO("adt75", 0x9),
- .irq = IRQ_PG5,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7410)
- {
- I2C_BOARD_INFO("adt7410", 0x48),
- /* CT critical temperature event. line 0 */
- .irq = IRQ_PG5,
- .platform_data = (void *)&adt7410_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7291)
- {
- I2C_BOARD_INFO("ad7291", 0x20),
- .irq = IRQ_PG5,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_I2C)
- {
- I2C_BOARD_INFO("adt7316", 0x48),
- .irq = IRQ_PG6,
- .platform_data = (void *)&adt7316_i2c_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PG6,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2F),
- .irq = IRQ_PG5,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
- {
- I2C_BOARD_INFO("adp5588-keys", 0x34),
- .irq = IRQ_PG0,
- .platform_data = (void *)&adp5588_kpad_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
- {
- I2C_BOARD_INFO("pmic-adp5520", 0x32),
- .irq = IRQ_PG0,
- .platform_data = (void *)&adp5520_pdev_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PG3,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_GPIO_ADP5588)
- {
- I2C_BOARD_INFO("adp5588-gpio", 0x34),
- .platform_data = (void *)&adp5588_gpio_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- {
- I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F),
- },
-#endif
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
- {
- I2C_BOARD_INFO("adp8870", 0x2B),
- .platform_data = (void *)&adp8870_pdata,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1371)
- {
- I2C_BOARD_INFO("adau1371", 0x1A),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
- {
- I2C_BOARD_INFO("adau1761", 0x38),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1361)
- {
- I2C_BOARD_INFO("adau1361", 0x38),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1701)
- {
- I2C_BOARD_INFO("adau1701", 0x34),
- },
-#endif
-#if IS_ENABLED(CONFIG_AD525X_DPOT)
- {
- I2C_BOARD_INFO("ad5258", 0x18),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
- {
- I2C_BOARD_INFO("ad5398", 0xC),
- .platform_data = (void *)&ad5398_regulator_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
- {
- I2C_BOARD_INFO("adp8860", 0x2A),
- .platform_data = (void *)&adp8860_pdata,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
- {
- I2C_BOARD_INFO("adau1373", 0x1A),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2e),
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
-|| IS_ENABLED(CONFIG_BFIN_SPORT)
-unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
-};
-#endif
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
-/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
-
-#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE
-#define PATA_INT IRQ_PF5
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 1,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x20314020,
- .end = 0x2031403F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2031401C,
- .end = 0x2031401F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-#elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE)
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 0,
-};
-/* CompactFlash Storage Card Memory Mapped Addressing
- * /REG = A11 = 1
- */
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x20211800,
- .end = 0x20211807,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2021180E, /* Device Ctl */
- .end = 0x2021180E,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static const unsigned ad73311_gpio[] = {
- GPIO_PF4,
-};
-
-static struct platform_device bfin_ad73311_machine = {
- .name = "bfin-snd-ad73311",
- .id = 1,
- .dev = {
- .platform_data = (void *)ad73311_gpio,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
-static struct platform_device bfin_eval_adav801_device = {
- .name = "bfin-eval-adav801",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
-#define REGULATOR_ADP122 "adp122"
-#define REGULATOR_ADP122_UV 2500000
-
-static struct regulator_consumer_supply adp122_consumers = {
- .supply = REGULATOR_ADP122,
-};
-
-static struct regulator_init_data adp_switch_regulator_data = {
- .constraints = {
- .name = REGULATOR_ADP122,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .min_uV = REGULATOR_ADP122_UV,
- .max_uV = REGULATOR_ADP122_UV,
- .min_uA = 0,
- .max_uA = 300000,
- },
- .num_consumer_supplies = 1, /* only 1 */
- .consumer_supplies = &adp122_consumers,
-};
-
-static struct fixed_voltage_config adp_switch_pdata = {
- .supply_name = REGULATOR_ADP122,
- .microvolts = REGULATOR_ADP122_UV,
- .gpio = GPIO_PF2,
- .enable_high = 1,
- .enabled_at_boot = 0,
- .init_data = &adp_switch_regulator_data,
-};
-
-static struct platform_device adp_switch_device = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &adp_switch_pdata,
- },
-};
-
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-static struct regulator_bulk_data adp122_bulk_data = {
- .supply = REGULATOR_ADP122,
-};
-
-static struct regulator_userspace_consumer_data adp122_userspace_comsumer_data = {
- .name = REGULATOR_ADP122,
- .num_supplies = 1,
- .supplies = &adp122_bulk_data,
-};
-
-static struct platform_device adp122_userspace_consumer_device = {
- .name = "reg-userspace-consumer",
- .id = 0,
- .dev = {
- .platform_data = &adp122_userspace_comsumer_data,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
-
-static struct resource iio_gpio_trigger_resources[] = {
- [0] = {
- .start = IRQ_PF5,
- .end = IRQ_PF5,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct platform_device iio_gpio_trigger = {
- .name = "iio_gpio_trigger",
- .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources),
- .resource = iio_gpio_trigger_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
-static struct platform_device bf5xx_adau1373_device = {
- .name = "bfin-eval-adau1373",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
-static struct platform_device bf5xx_adau1701_device = {
- .name = "bfin-eval-adau1701",
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
- &bfin_sport0_device,
-#endif
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_SL811_HCD)
- &sl811_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
- &bfin_sport_spi0_device,
- &bfin_sport_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- &bfin_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
- &bfin_async_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &stamp_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
- &bfin_ad73311_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
- &bfin_ad73311_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
- &bfin_ac97,
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
-#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
- &ad5398_virt_consumer_device,
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
- &ad5398_userspace_consumer_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
- &adp_switch_device,
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
- &adp122_userspace_consumer_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
- &iio_gpio_trigger,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
- &bf5xx_adau1373_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
- &bf5xx_adau1701_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
- &bfin_eval_adav801_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF6, "net2272");
- if (ret)
- return ret;
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF6, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF6, 1);
-#endif
-
- return 0;
-}
-
-static int __init stamp_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- bfin_plat_nand_init();
- adf702x_mac_init();
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(stamp_init);
-
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-/*
- * Currently the MAC address is saved in Flash by U-Boot
- */
-#define FLASH_MAC 0x203f0000
-int bfin_get_ether_addr(char *addr)
-{
- *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
- *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
deleted file mode 100644
index ed309c9..0000000
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ /dev/null
@@ -1,792 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/mmc_spi.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix TCM BF537";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG13,
- .end = IRQ_PG13,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PF4, GPIO_PF5 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PG14, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PG14 */
- gpio_direction_output(GPIO_PG14, 0);
- mdelay(2);
- gpio_set_value(GPIO_PG14, 1);
-#endif
-
- return 0;
-}
-
-static int __init tcm_bf537_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(tcm_bf537_init);
-
-static struct platform_device *cm_bf537_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537_early_devices,
- ARRAY_SIZE(cm_bf537_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
deleted file mode 100644
index 5c62e99..0000000
--- a/arch/blackfin/mach-bf537/dma.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * This file contains the simple DMA Implementation for Blackfin
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
deleted file mode 100644
index 2bc70c5..0000000
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF537 silicon version 0.0 or 0.1
-#endif
-
-#if defined(__ADSPBF534__)
-# define ANOMALY_BF534 1
-#else
-# define ANOMALY_BF534 0
-#endif
-#if defined(__ADSPBF536__)
-# define ANOMALY_BF536 1
-#else
-# define ANOMALY_BF536 0
-#endif
-#if defined(__ADSPBF537__)
-# define ANOMALY_BF537 1
-#else
-# define ANOMALY_BF537 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
-/* EMAC TX DMA Error After an Early Frame Abort */
-#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
-/* EMAC MDIO Input Latched on Wrong MDC Edge */
-#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
-#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
-/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
-#define ANOMALY_05000280 (1)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
-/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
-#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
-/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
-#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
-#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
-#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode@10-Base-T Speed: RX Frames Not Received Properly */
-#define ANOMALY_05000322 (1)
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
-/* UART Gets Disabled after UART Boot */
-#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000359 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
-#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
-/* Buffered CLKIN Output Is Disabled by Default */
-#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h
deleted file mode 100644
index 8b29141..0000000
--- a/arch/blackfin/mach-bf537/include/mach/bf537.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * System MMR Register and memory map for ADSP-BF537
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF537_H__
-#define __MACH_BF537_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF537
-#define CPU "BF537"
-#define CPUID 0x27c8
-#endif
-#ifdef CONFIG_BF536
-#define CPU "BF536"
-#define CPUID 0x27c8
-#endif
-#ifdef CONFIG_BF534
-#define CPU "BF534"
-#define CPUID 0x27c6
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF537_H__ */
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
deleted file mode 100644
index 00c603f..0000000
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
deleted file mode 100644
index baa096f..0000000
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF537_FAMILY
-
-#include "bf537.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF534
-# include "defBF534.h"
-#endif
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-# include "defBF537.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF534
-# include "cdefBF534.h"
-# endif
-# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-# include "cdefBF537.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
deleted file mode 100644
index 563ede9..0000000
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ /dev/null
@@ -1,1736 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF534_H
-#define _CDEF_BF534_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS,val)
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO,val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR,val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET,val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA,val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR,val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET,val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB,val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR,val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET,val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR,val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR,val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE,val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH,val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN,val)
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR,val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR,val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT,val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT,val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS,val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG,val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR,val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT,val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT,val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY,val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY,val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR,val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR,val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT,val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT,val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG,val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR,val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT,val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT,val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY,val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY,val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR,val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR,val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT,val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT,val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS,val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO,val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR,val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET,val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA,val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR,val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET,val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB,val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR,val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET,val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR,val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR,val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE,val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH,val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN,val)
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO,val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR,val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET,val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA,val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR,val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET,val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB,val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR,val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET,val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR,val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR,val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE,val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH,val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN,val)
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR,val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL,val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER,val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH,val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR,val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR,val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR,val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR,val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR,val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR,val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL,val)
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1,val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1,val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1,val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1,val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1,val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1,val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1,val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1,val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1,val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1,val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1,val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1,val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1,val)
-
-/* For Mailboxes 16-31 */
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2,val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2,val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2,val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2,val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2,val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2,val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2,val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2,val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2,val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2,val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2,val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2,val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2,val)
-
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK,val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING,val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG,val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS,val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC,val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS,val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM,val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF,val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL,val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR,val)
-#define bfin_read_CAN_SFCMVER() bfin_read16(CAN_SFCMVER)
-#define bfin_write_CAN_SFCMVER(val) bfin_write16(CAN_SFCMVER,val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD,val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR,val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR,val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG,val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT,val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
-
-/* Mailbox Acceptance Masks */
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L,val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H,val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L,val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H,val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L,val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H,val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L,val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H,val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L,val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H,val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L,val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H,val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L,val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H,val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L,val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H,val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L,val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H,val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L,val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H,val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L,val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H,val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L,val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H,val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L,val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H,val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L,val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H,val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L,val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H,val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L,val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H,val)
-
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L,val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H,val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L,val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H,val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L,val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H,val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L,val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H,val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L,val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H,val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L,val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H,val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L,val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H,val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L,val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H,val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L,val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H,val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L,val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H,val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L,val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H,val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L,val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H,val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L,val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H,val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L,val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H,val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L,val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H,val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L,val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H,val)
-
-/* CAN Acceptance Mask Area Macros */
-#define bfin_read_CAN_AM_L(x)() bfin_read16(CAN_AM_L(x))
-#define bfin_write_CAN_AM_L(x)(val) bfin_write16(CAN_AM_L(x),val)
-#define bfin_read_CAN_AM_H(x)() bfin_read16(CAN_AM_H(x))
-#define bfin_write_CAN_AM_H(x)(val) bfin_write16(CAN_AM_H(x),val)
-
-/* Mailbox Registers */
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1,val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0,val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP,val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH,val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3,val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2,val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1,val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0,val)
-
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1,val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0,val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP,val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH,val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3,val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2,val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1,val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0,val)
-
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1,val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0,val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP,val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH,val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3,val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2,val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1,val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0,val)
-
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1,val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0,val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP,val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH,val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3,val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2,val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1,val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0,val)
-
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1,val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0,val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP,val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH,val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3,val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2,val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1,val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0,val)
-
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1,val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0,val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP,val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH,val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3,val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2,val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1,val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0,val)
-
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1,val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0,val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP,val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH,val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3,val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2,val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1,val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0,val)
-
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1,val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0,val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP,val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH,val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3,val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2,val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1,val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0,val)
-
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1,val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0,val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP,val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH,val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3,val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2,val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1,val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0,val)
-
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1,val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0,val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP,val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH,val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3,val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2,val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1,val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0,val)
-
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1,val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0,val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP,val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH,val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3,val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2,val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1,val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0,val)
-
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1,val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0,val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP,val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH,val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3,val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2,val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1,val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0,val)
-
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1,val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0,val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP,val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH,val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3,val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2,val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1,val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0,val)
-
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1,val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0,val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP,val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH,val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3,val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2,val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1,val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0,val)
-
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1,val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0,val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP,val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH,val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3,val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2,val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1,val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0,val)
-
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1,val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0,val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP,val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH,val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3,val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2,val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1,val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0,val)
-
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1,val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0,val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP,val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH,val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3,val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2,val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1,val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0,val)
-
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1,val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0,val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP,val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH,val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3,val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2,val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1,val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0,val)
-
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1,val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0,val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP,val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH,val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3,val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2,val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1,val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0,val)
-
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1,val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0,val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP,val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH,val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3,val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2,val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1,val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0,val)
-
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1,val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0,val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP,val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH,val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3,val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2,val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1,val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0,val)
-
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1,val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0,val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP,val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH,val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3,val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2,val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1,val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0,val)
-
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1,val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0,val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP,val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH,val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3,val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2,val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1,val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0,val)
-
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1,val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0,val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP,val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH,val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3,val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2,val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1,val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0,val)
-
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1,val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0,val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP,val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH,val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3,val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2,val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1,val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0,val)
-
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1,val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0,val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP,val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH,val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3,val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2,val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1,val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0,val)
-
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1,val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0,val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP,val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH,val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3,val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2,val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1,val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0,val)
-
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1,val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0,val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP,val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH,val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3,val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2,val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1,val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0,val)
-
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1,val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0,val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP,val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH,val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3,val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2,val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1,val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0,val)
-
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1,val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0,val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP,val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH,val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3,val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2,val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1,val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0,val)
-
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1,val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0,val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP,val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH,val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3,val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2,val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1,val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0,val)
-
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1,val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0,val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP,val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH,val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3,val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2,val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1,val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0,val)
-
-/* CAN Mailbox Area Macros */
-#define bfin_read_CAN_MB_ID1(x)() bfin_read16(CAN_MB_ID1(x))
-#define bfin_write_CAN_MB_ID1(x)(val) bfin_write16(CAN_MB_ID1(x),val)
-#define bfin_read_CAN_MB_ID0(x)() bfin_read16(CAN_MB_ID0(x))
-#define bfin_write_CAN_MB_ID0(x)(val) bfin_write16(CAN_MB_ID0(x),val)
-#define bfin_read_CAN_MB_TIMESTAMP(x)() bfin_read16(CAN_MB_TIMESTAMP(x))
-#define bfin_write_CAN_MB_TIMESTAMP(x)(val) bfin_write16(CAN_MB_TIMESTAMP(x),val)
-#define bfin_read_CAN_MB_LENGTH(x)() bfin_read16(CAN_MB_LENGTH(x))
-#define bfin_write_CAN_MB_LENGTH(x)(val) bfin_write16(CAN_MB_LENGTH(x),val)
-#define bfin_read_CAN_MB_DATA3(x)() bfin_read16(CAN_MB_DATA3(x))
-#define bfin_write_CAN_MB_DATA3(x)(val) bfin_write16(CAN_MB_DATA3(x),val)
-#define bfin_read_CAN_MB_DATA2(x)() bfin_read16(CAN_MB_DATA2(x))
-#define bfin_write_CAN_MB_DATA2(x)(val) bfin_write16(CAN_MB_DATA2(x),val)
-#define bfin_read_CAN_MB_DATA1(x)() bfin_read16(CAN_MB_DATA1(x))
-#define bfin_write_CAN_MB_DATA1(x)(val) bfin_write16(CAN_MB_DATA1(x),val)
-#define bfin_read_CAN_MB_DATA0(x)() bfin_read16(CAN_MB_DATA0(x))
-#define bfin_write_CAN_MB_DATA0(x)(val) bfin_write16(CAN_MB_DATA0(x),val)
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER,val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER,val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER,val)
-#define bfin_read_PORT_MUX() bfin_read16(BFIN_PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(BFIN_PORT_MUX,val)
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL,val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT,val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT,val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT,val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW,val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT,val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT,val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL,val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT,val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT,val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT,val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW,val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT,val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
-
-#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
deleted file mode 100644
index 19ec21e..0000000
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF537_H
-#define _CDEF_BF537_H
-
-/* Include MMRs Common to BF534 */
-#include "cdefBF534.h"
-
-/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL,val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0,val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1,val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2,val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3,val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD,val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF,val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0,val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT,val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT,val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY,val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE,val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT,val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY,val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE,val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL,val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS,val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE,val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE,val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK,val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS,val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN,val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET,val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF,val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST,val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI,val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD,val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI,val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO,val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG,val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL,val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE,val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE,val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM,val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT,val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED,val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256,val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512,val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024,val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024,val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK,val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL,val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL,val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET,val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER,val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL,val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL,val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND,val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR,val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST,val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI,val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD,val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR,val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL,val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM,val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT,val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64,val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128,val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256,val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512,val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024,val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024,val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT,val)
-
-#endif /* _CDEF_BF537_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
deleted file mode 100644
index ef6a98c..0000000
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ /dev/null
@@ -1,1470 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF534_H
-#define _DEF_BF534_H
-
-/************************************************************************************
-** System MMR Register Map
-*************************************************************************************/
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
-#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
-
-/* For Mailboxes 16-31 */
-#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
-#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
-
-/* CAN Configuration, Control, and Status Registers */
-#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
-#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
-#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
-
-#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
-#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
-#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
-
-/* Mailbox Acceptance Masks */
-#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-
-#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-
-/* CAN Acceptance Mask Macros */
-#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers */
-#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
-
-#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
-
-#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
-
-#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
-
-#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
-
-#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
-
-#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
-
-#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
-
-#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
-
-#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
-
-#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
-
-#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
-
-#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
-
-#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
-
-#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
-
-#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
-
-#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
-
-#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
-
-#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
-
-#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
-
-#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
-
-#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
-
-#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
-
-#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
-
-#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
-
-#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
-
-#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
-
-#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
-
-#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
-
-#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
-
-#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
-
-#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
-
-/* CAN Mailbox Area Macros */
-#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-#endif /* _DEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
deleted file mode 100644
index e10332c..0000000
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF537_H
-#define _DEF_BF537_H
-
-/* Include all MMR and bit defines common to BF534 */
-#include "defBF534.h"
-
-/************************************************************************************
-** Define EMAC Section Unique to BF536/BF537
-*************************************************************************************/
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-/* EMAC_OPMODE Masks */
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF537_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/dma.h b/arch/blackfin/mach-bf537/include/mach/dma.h
deleted file mode 100644
index 5ae83b1..0000000
--- a/arch/blackfin/mach-bf537/include/mach/dma.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0
-#define CH_EMAC_RX 1
-#define CH_EMAC_TX 2
-#define CH_SPORT0_RX 3
-#define CH_SPORT0_TX 4
-#define CH_SPORT1_RX 5
-#define CH_SPORT1_TX 6
-#define CH_SPI 7
-#define CH_UART0_RX 8
-#define CH_UART0_TX 9
-#define CH_UART1_RX 10
-#define CH_UART1_TX 11
-
-#define CH_MEM_STREAM0_DEST 12 /* TX */
-#define CH_MEM_STREAM0_SRC 13 /* RX */
-#define CH_MEM_STREAM1_DEST 14 /* TX */
-#define CH_MEM_STREAM1_SRC 15 /* RX */
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
deleted file mode 100644
index fba606b..0000000
--- a/arch/blackfin/mach-bf537/include/mach/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
deleted file mode 100644
index b6ed823..0000000
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF537_IRQ_H_
-#define _BF537_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS 32
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
-#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */
-#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */
-#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */
-#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
-#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
-#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
-#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
-#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
-#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
-#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
-#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
-
-#define SYS_IRQS 39
-
-#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
-#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
-#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
-#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
-#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
-#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
-
-#define IRQ_PF0 50
-#define IRQ_PF1 51
-#define IRQ_PF2 52
-#define IRQ_PF3 53
-#define IRQ_PF4 54
-#define IRQ_PF5 55
-#define IRQ_PF6 56
-#define IRQ_PF7 57
-#define IRQ_PF8 58
-#define IRQ_PF9 59
-#define IRQ_PF10 60
-#define IRQ_PF11 61
-#define IRQ_PF12 62
-#define IRQ_PF13 63
-#define IRQ_PF14 64
-#define IRQ_PF15 65
-
-#define IRQ_PG0 66
-#define IRQ_PG1 67
-#define IRQ_PG2 68
-#define IRQ_PG3 69
-#define IRQ_PG4 70
-#define IRQ_PG5 71
-#define IRQ_PG6 72
-#define IRQ_PG7 73
-#define IRQ_PG8 74
-#define IRQ_PG9 75
-#define IRQ_PG10 76
-#define IRQ_PG11 77
-#define IRQ_PG12 78
-#define IRQ_PG13 79
-#define IRQ_PG14 80
-#define IRQ_PG15 81
-
-#define IRQ_PH0 82
-#define IRQ_PH1 83
-#define IRQ_PH2 84
-#define IRQ_PH3 85
-#define IRQ_PH4 86
-#define IRQ_PH5 87
-#define IRQ_PH6 88
-#define IRQ_PH7 89
-#define IRQ_PH8 90
-#define IRQ_PH9 91
-#define IRQ_PH10 92
-#define IRQ_PH11 93
-#define IRQ_PH12 94
-#define IRQ_PH13 95
-#define IRQ_PH14 96
-#define IRQ_PH15 97
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
-
-#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
-#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
-
-#if 0 /* No Interrupt B support (yet) */
-#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
-#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
-#else
-#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
-#endif
-
-#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
-#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
-
-#if 0 /* No Interrupt B support (yet) */
-#define IRQ_WATCH 112 /* Watchdog Timer */
-#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
-#else
-#define IRQ_WATCH IRQ_PF_INTB_WATCH
-#endif
-
-#define NR_MACH_IRQS (113 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA_ERROR_POS 4
-#define IRQ_ERROR_POS 8
-#define IRQ_RTC_POS 12
-#define IRQ_PPI_POS 16
-#define IRQ_SPORT0_RX_POS 20
-#define IRQ_SPORT0_TX_POS 24
-#define IRQ_SPORT1_RX_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT1_TX_POS 0
-#define IRQ_TWI_POS 4
-#define IRQ_SPI_POS 8
-#define IRQ_UART0_RX_POS 12
-#define IRQ_UART0_TX_POS 16
-#define IRQ_UART1_RX_POS 20
-#define IRQ_UART1_TX_POS 24
-#define IRQ_CAN_RX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MAC_RX_POS 4
-#define IRQ_MAC_TX_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_PROG_INTA_POS 12
-#define IRQ_PORTG_INTB_POS 16
-#define IRQ_MEM_DMA0_POS 20
-#define IRQ_MEM_DMA1_POS 24
-#define IRQ_WATCH_POS 28
-
-#define init_mach_irq init_mach_irq
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h
deleted file mode 100644
index 942f08d..0000000
--- a/arch/blackfin/mach-bf537/include/mach/mem_map.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * BF537 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x800
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF537 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-
-#ifdef CONFIG_BF537
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif /*CONFIG_BF537*/
-
-/* Memory Map for ADSP-BF536 processors */
-
-#ifdef CONFIG_BF536
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-
-#define L1_CODE_LENGTH 0xC000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-/* Memory Map for ADSP-BF534 processors */
-
-#ifdef CONFIG_BF534
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
deleted file mode 100644
index 94cca67..0000000
--- a/arch/blackfin/mach-bf537/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf537/include/mach/portmux.h b/arch/blackfin/mach-bf537/include/mach/portmux.h
deleted file mode 100644
index 71d9eae..0000000
--- a/arch/blackfin/mach-bf537/include/mach/portmux.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
-
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-
-#define PORT_PJ0 (GPIO_PH15 + 1)
-#define PORT_PJ1 (GPIO_PH15 + 2)
-#define PORT_PJ2 (GPIO_PH15 + 3)
-#define PORT_PJ3 (GPIO_PH15 + 4)
-#define PORT_PJ4 (GPIO_PH15 + 5)
-#define PORT_PJ5 (GPIO_PH15 + 6)
-#define PORT_PJ6 (GPIO_PH15 + 7)
-#define PORT_PJ7 (GPIO_PH15 + 8)
-#define PORT_PJ8 (GPIO_PH15 + 9)
-#define PORT_PJ9 (GPIO_PH15 + 10)
-#define PORT_PJ10 (GPIO_PH15 + 11)
-#define PORT_PJ11 (GPIO_PH15 + 12)
-
-#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
-#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
-#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
-#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
-#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
deleted file mode 100644
index a48baae..0000000
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-#include <asm/irq_handler.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_sport.h>
-#include <asm/bfin_can.h>
-#include <asm/bfin_dma.h>
-#include <asm/dpmc.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) |
- ((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
-
- SSYNC();
-}
-
-#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
-#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
-#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
-#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
-#define UART_ERR_MASK (0x6) /* UART_IIR */
-#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
-
-static int error_int_mask;
-
-static void bf537_generic_error_mask_irq(struct irq_data *d)
-{
- error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
- if (!error_int_mask)
- bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
-}
-
-static void bf537_generic_error_unmask_irq(struct irq_data *d)
-{
- bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
- error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
-}
-
-static struct irq_chip bf537_generic_error_irqchip = {
- .name = "ERROR",
- .irq_ack = bfin_ack_noop,
- .irq_mask_ack = bf537_generic_error_mask_irq,
- .irq_mask = bf537_generic_error_mask_irq,
- .irq_unmask = bf537_generic_error_unmask_irq,
-};
-
-static void bf537_demux_error_irq(struct irq_desc *inta_desc)
-{
- int irq = 0;
-
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
- irq = IRQ_MAC_ERROR;
- else
-#endif
- if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT0_ERROR;
- else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT1_ERROR;
- else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
- irq = IRQ_PPI_ERROR;
- else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
- irq = IRQ_CAN_ERROR;
- else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
- irq = IRQ_SPI_ERROR;
- else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART0_ERROR;
- else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART1_ERROR;
-
- if (irq) {
- if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
- bfin_handle_irq(irq);
- else {
-
- switch (irq) {
- case IRQ_PPI_ERROR:
- bfin_write_PPI_STATUS(PPI_ERR_MASK);
- break;
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- case IRQ_MAC_ERROR:
- bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
- break;
-#endif
- case IRQ_SPORT0_ERROR:
- bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_SPORT1_ERROR:
- bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_CAN_ERROR:
- bfin_write_CAN_GIS(CAN_ERR_MASK);
- break;
-
- case IRQ_SPI_ERROR:
- bfin_write_SPI_STAT(SPI_ERR_MASK);
- break;
-
- default:
- break;
- }
-
- pr_debug("IRQ %d:"
- " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
- irq);
- }
- } else
- pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
- __func__);
-
-}
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-static int mac_rx_int_mask;
-
-static void bf537_mac_rx_mask_irq(struct irq_data *d)
-{
- mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
- if (!mac_rx_int_mask)
- bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
-}
-
-static void bf537_mac_rx_unmask_irq(struct irq_data *d)
-{
- bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
- mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
-}
-
-static struct irq_chip bf537_mac_rx_irqchip = {
- .name = "ERROR",
- .irq_ack = bfin_ack_noop,
- .irq_mask_ack = bf537_mac_rx_mask_irq,
- .irq_mask = bf537_mac_rx_mask_irq,
- .irq_unmask = bf537_mac_rx_unmask_irq,
-};
-
-static void bf537_demux_mac_rx_irq(struct irq_desc *desc)
-{
- if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
- bfin_handle_irq(IRQ_MAC_RX);
- else
- bfin_demux_gpio_irq(desc);
-}
-#endif
-
-void __init init_mach_irq(void)
-{
- int irq;
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
- /* Clear EMAC Interrupt Status bits so we can demux it later */
- bfin_write_EMAC_SYSTAT(-1);
-#endif
-
- irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
- for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
- irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
- handle_level_irq);
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
- irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
- irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
- irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
-
- irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
-#endif
-}
diff --git a/arch/blackfin/mach-bf538/Kconfig b/arch/blackfin/mach-bf538/Kconfig
deleted file mode 100644
index 4aea85e..0000000
--- a/arch/blackfin/mach-bf538/Kconfig
+++ /dev/null
@@ -1,166 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF538 || BF539)
-
-source "arch/blackfin/mach-bf538/boards/Kconfig"
-
-menu "BF538 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_SPI0_ERROR
- int "IRQ_SPI0_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_SPI0
- int "IRQ_SPI0"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 11
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 11
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 12
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 12
-config IRQ_MEM0_DMA0
- int "IRQ_MEM0_DMA0"
- default 13
-config IRQ_MEM0_DMA1
- int "IRQ_MEM0_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_DMA1_ERROR
- int "IRQ_DMA1_ERROR"
- default 7
-config IRQ_SPORT2_ERROR
- int "IRQ_SPORT2_ERROR"
- default 7
-config IRQ_SPORT3_ERROR
- int "IRQ_SPORT3_ERROR"
- default 7
-config IRQ_SPI1_ERROR
- int "IRQ_SPI1_ERROR"
- default 7
-config IRQ_SPI2_ERROR
- int "IRQ_SPI2_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_UART2_ERROR
- int "IRQ_UART2_ERROR"
- default 7
-config IRQ_CAN_ERROR
- int "IRQ_CAN_ERROR"
- default 7
-config IRQ_SPORT2_RX
- int "IRQ_SPORT2_RX"
- default 9
-config IRQ_SPORT2_TX
- int "IRQ_SPORT2_TX"
- default 9
-config IRQ_SPORT3_RX
- int "IRQ_SPORT3_RX"
- default 9
-config IRQ_SPORT3_TX
- int "IRQ_SPORT3_TX"
- default 9
-config IRQ_SPI1
- int "IRQ_SPI1"
- default 10
-config IRQ_SPI2
- int "IRQ_SPI2"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_UART2_RX
- int "IRQ_UART2_RX"
- default 10
-config IRQ_UART2_TX
- int "IRQ_UART2_TX"
- default 10
-config IRQ_TWI0
- int "IRQ_TWI0"
- default 11
-config IRQ_TWI1
- int "IRQ_TWI1"
- default 11
-config IRQ_CAN_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MEM1_DMA0
- int "IRQ_MEM1_DMA0"
- default 13
-config IRQ_MEM1_DMA1
- int "IRQ_MEM1_DMA1"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf538/Makefile b/arch/blackfin/mach-bf538/Makefile
deleted file mode 100644
index c0be54f..0000000
--- a/arch/blackfin/mach-bf538/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# arch/blackfin/mach-bf538/Makefile
-#
-
-obj-y := ints-priority.o dma.o
-obj-$(CONFIG_GPIOLIB) += ext-gpio.o
diff --git a/arch/blackfin/mach-bf538/boards/Kconfig b/arch/blackfin/mach-bf538/boards/Kconfig
deleted file mode 100644
index 114cff4..0000000
--- a/arch/blackfin/mach-bf538/boards/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN538_EZKIT
- help
- Select your board!
-
-config BFIN538_EZKIT
- bool "BF538-EZKIT"
- help
- BF538-EZKIT-LITE board support.
-
-endchoice
diff --git a/arch/blackfin/mach-bf538/boards/Makefile b/arch/blackfin/mach-bf538/boards/Makefile
deleted file mode 100644
index 6143b32..0000000
--- a/arch/blackfin/mach-bf538/boards/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf538/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN538_EZKIT) += ezkit.o
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
deleted file mode 100644
index 1b6a52a..0000000
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ /dev/null
@@ -1,987 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/input.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF538-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif /* CONFIG_RTC_DRV_BFIN */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG7,
- .end = GPIO_PG7,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PG6,
- .end = GPIO_PG6,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART0 */
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART1 */
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_THR,
- .end = UART2_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART2 */
-#endif /* CONFIG_SERIAL_BFIN */
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif /* CONFIG_BFIN_SIR0 */
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif /* CONFIG_BFIN_SIR1 */
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif /* CONFIG_BFIN_SIR2 */
-#endif /* CONFIG_BFIN_SIR */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
-#endif /* CONFIG_SERIAL_BFIN_SPORT */
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN_RX,
- .end = IRQ_CAN_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_TX,
- .end = IRQ_CAN_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_ERROR,
- .end = IRQ_CAN_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_CAN_BFIN */
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20310300,
- .end = 0x20310300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif /* CONFIG_SMC91X */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x1c0000,
- .offset = 0x40000
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif /* CONFIG_MTD_M25P80 */
-#endif /* CONFIG_SPI_BFIN5XX */
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif /* CONFIG_TOUCHSCREEN_AD7879 */
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 0, /* let something else control the LCD Blacklight */
- .gpio_bl = GPIO_PF7,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif /* CONFIG_FB_BFIN_LQ035Q1 */
-
-static struct spi_board_info bf538_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif /* CONFIG_MTD_M25P80 */
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF3,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif /* CONFIG_FB_BFIN_LQ035Q1 */
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif /* CONFIG_SPI_SPIDEV */
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (2) */
-static struct resource bfin_spi2_resource[] = {
- [0] = {
- .start = SPI2_REGBASE,
- .end = SPI2_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI2,
- .end = CH_SPI2,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI2,
- .end = IRQ_SPI2,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf538_spi_master_info0 = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf538_spi_master_info1 = {
- .num_chipselect = 2,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info1, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf538_spi_master_info2 = {
- .num_chipselect = 2,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master2 = {
- .name = "bfin-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi2_resource),
- .resource = bfin_spi2_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info2, /* Passed to driver */
- },
-};
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
-};
-#endif /* CONFIG_I2C_BLACKFIN_TWI */
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF538SBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_100, 150000000),
- VRPAIR(VLEV_100, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
-#if IS_ENABLED(CONFIG_SMC91X)
- .end = 0x202fffff,
-#else
- .end = 0x203fffff,
-#endif
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-static struct platform_device *cm_bf538_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf538_spi_master0,
- &bf538_spi_master1,
- &bf538_spi_master2,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
- &i2c_bfin_twi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bf538_spi_board_info,
- ARRAY_SIZE(bf538_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf538/dma.c b/arch/blackfin/mach-bf538/dma.c
deleted file mode 100644
index cce8ef5..0000000
--- a/arch/blackfin/mach-bf538/dma.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_UART2_RX:
- ret_irq = IRQ_UART2_RX;
- break;
-
- case CH_UART2_TX:
- ret_irq = IRQ_UART2_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
-
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
-
- case CH_SPORT3_RX:
- ret_irq = IRQ_SPORT3_RX;
- break;
-
- case CH_SPORT3_TX:
- ret_irq = IRQ_SPORT3_TX;
- break;
-
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
-
- case CH_SPI1:
- ret_irq = IRQ_SPI1;
- break;
-
- case CH_SPI2:
- ret_irq = IRQ_SPI2;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM0_DMA0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM0_DMA1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MEM1_DMA0;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MEM1_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c
deleted file mode 100644
index 48c1002..0000000
--- a/arch/blackfin/mach-bf538/ext-gpio.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
- *
- * Copyright 2009-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-#define DEFINE_REG(reg, off) \
-static inline u16 read_##reg(void __iomem *port) \
- { return bfin_read16(port + off); } \
-static inline void write_##reg(void __iomem *port, u16 v) \
- { bfin_write16(port + off, v); }
-
-DEFINE_REG(PORTIO, 0x00)
-DEFINE_REG(PORTIO_CLEAR, 0x10)
-DEFINE_REG(PORTIO_SET, 0x20)
-DEFINE_REG(PORTIO_DIR, 0x40)
-DEFINE_REG(PORTIO_INEN, 0x50)
-
-static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip)
-{
- switch (chip->base) {
- default: /* not really needed, but keeps gcc happy */
- case GPIO_PC0: return (void __iomem *)PORTCIO;
- case GPIO_PD0: return (void __iomem *)PORTDIO;
- case GPIO_PE0: return (void __iomem *)PORTEIO;
- }
-}
-
-static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- return !!(read_PORTIO(port) & (1u << gpio));
-}
-
-static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- if (value)
- write_PORTIO_SET(port, (1u << gpio));
- else
- write_PORTIO_CLEAR(port, (1u << gpio));
-}
-
-static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio));
- write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio));
- return 0;
-}
-
-static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio));
- bf538_gpio_set_value(port, gpio, value);
- write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio));
- return 0;
-}
-
-static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_special_gpio_request(chip->base + gpio, chip->label);
-}
-
-static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_special_gpio_free(chip->base + gpio);
-}
-
-/* We don't set the irq fields as these banks cannot generate interrupts */
-
-static struct gpio_chip bf538_portc_chip = {
- .label = "GPIO-PC",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PC0,
- .ngpio = GPIO_PC9 - GPIO_PC0 + 1,
-};
-
-static struct gpio_chip bf538_portd_chip = {
- .label = "GPIO-PD",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PD0,
- .ngpio = GPIO_PD13 - GPIO_PD0 + 1,
-};
-
-static struct gpio_chip bf538_porte_chip = {
- .label = "GPIO-PE",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PE0,
- .ngpio = GPIO_PE15 - GPIO_PE0 + 1,
-};
-
-static int __init bf538_extgpio_setup(void)
-{
- return gpiochip_add_data(&bf538_portc_chip, NULL) |
- gpiochip_add_data(&bf538_portd_chip, NULL) |
- gpiochip_add_data(&bf538_porte_chip, NULL);
-}
-arch_initcall(bf538_extgpio_setup);
-
-#ifdef CONFIG_PM
-static struct {
- u16 data, dir, inen;
-} gpio_bank_saved[3];
-
-static void __iomem * const port_bases[3] = {
- (void *)PORTCIO,
- (void *)PORTDIO,
- (void *)PORTEIO,
-};
-
-void bfin_special_gpio_pm_hibernate_suspend(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
- gpio_bank_saved[i].data = read_PORTIO(port_bases[i]);
- gpio_bank_saved[i].inen = read_PORTIO_INEN(port_bases[i]);
- gpio_bank_saved[i].dir = read_PORTIO_DIR(port_bases[i]);
- }
-}
-
-void bfin_special_gpio_pm_hibernate_restore(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
- write_PORTIO_INEN(port_bases[i], gpio_bank_saved[i].inen);
- write_PORTIO_SET(port_bases[i],
- gpio_bank_saved[i].data & gpio_bank_saved[i].dir);
- write_PORTIO_DIR(port_bases[i], gpio_bank_saved[i].dir);
- }
-}
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
deleted file mode 100644
index eaac269..0000000
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 4
-# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
-#endif
-
-#if defined(__ADSPBF538__)
-# define ANOMALY_BF538 1
-#else
-# define ANOMALY_BF538 0
-#endif
-#if defined(__ADSPBF539__)
-# define ANOMALY_BF539 1
-#else
-# define ANOMALY_BF539 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (1)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (ANOMALY_BF538)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
-/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
-#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
-/* Hibernate Leakage Current Is Higher Than Specified */
-#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000294 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
-/* False Hardware Errors Caused by Fetches@the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
-/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
-#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */
-/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
-#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
-/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
-#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
-/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
-#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Specific GPIO Pins May Change State when Entering Hibernate */
-#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bf538.h b/arch/blackfin/mach-bf538/include/mach/bf538.h
deleted file mode 100644
index 0cf5bf8..0000000
--- a/arch/blackfin/mach-bf538/include/mach/bf538.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF538
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF538_H__
-#define __MACH_BF538_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF538
-#define CPU "BF538"
-#define CPUID 0x27C4
-#endif
-#ifdef CONFIG_BF539
-#define CPU "BF539"
-#define CPUID 0x27C4 /* FXIME:? */
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF538_H__ */
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
deleted file mode 100644
index c66e276..0000000
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 3
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
deleted file mode 100644
index 791d084..0000000
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF538_FAMILY
-
-#include "bf538.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF538
-# include "defBF538.h"
-#endif
-#ifdef CONFIG_BF539
-# include "defBF539.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF538
-# include "cdefBF538.h"
-# endif
-# ifdef CONFIG_BF539
-# include "cdefBF539.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
deleted file mode 100644
index f6a5679..0000000
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ /dev/null
@@ -1,1960 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF538_H
-#define _CDEF_BF538_H
-
-#define bfin_writePTR(addr, val) bfin_write32(addr, val)
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT() bfin_readPTR(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
-#define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
-#define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_IER() bfin_read16(UART2_IER)
-#define bfin_write_UART2_IER(val) bfin_write16(UART2_IER, val)
-#define bfin_read_UART2_IIR() bfin_read16(UART2_IIR)
-#define bfin_write_UART2_IIR(val) bfin_write16(UART2_IIR, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_PORTCIO_FER() bfin_read16(PORTCIO_FER)
-#define bfin_write_PORTCIO_FER(val) bfin_write16(PORTCIO_FER, val)
-#define bfin_read_PORTCIO() bfin_read16(PORTCIO)
-#define bfin_write_PORTCIO(val) bfin_write16(PORTCIO, val)
-#define bfin_read_PORTCIO_CLEAR() bfin_read16(PORTCIO_CLEAR)
-#define bfin_write_PORTCIO_CLEAR(val) bfin_write16(PORTCIO_CLEAR, val)
-#define bfin_read_PORTCIO_SET() bfin_read16(PORTCIO_SET)
-#define bfin_write_PORTCIO_SET(val) bfin_write16(PORTCIO_SET, val)
-#define bfin_read_PORTCIO_TOGGLE() bfin_read16(PORTCIO_TOGGLE)
-#define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val)
-#define bfin_read_PORTCIO_DIR() bfin_read16(PORTCIO_DIR)
-#define bfin_write_PORTCIO_DIR(val) bfin_write16(PORTCIO_DIR, val)
-#define bfin_read_PORTCIO_INEN() bfin_read16(PORTCIO_INEN)
-#define bfin_write_PORTCIO_INEN(val) bfin_write16(PORTCIO_INEN, val)
-#define bfin_read_PORTDIO_FER() bfin_read16(PORTDIO_FER)
-#define bfin_write_PORTDIO_FER(val) bfin_write16(PORTDIO_FER, val)
-#define bfin_read_PORTDIO() bfin_read16(PORTDIO)
-#define bfin_write_PORTDIO(val) bfin_write16(PORTDIO, val)
-#define bfin_read_PORTDIO_CLEAR() bfin_read16(PORTDIO_CLEAR)
-#define bfin_write_PORTDIO_CLEAR(val) bfin_write16(PORTDIO_CLEAR, val)
-#define bfin_read_PORTDIO_SET() bfin_read16(PORTDIO_SET)
-#define bfin_write_PORTDIO_SET(val) bfin_write16(PORTDIO_SET, val)
-#define bfin_read_PORTDIO_TOGGLE() bfin_read16(PORTDIO_TOGGLE)
-#define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val)
-#define bfin_read_PORTDIO_DIR() bfin_read16(PORTDIO_DIR)
-#define bfin_write_PORTDIO_DIR(val) bfin_write16(PORTDIO_DIR, val)
-#define bfin_read_PORTDIO_INEN() bfin_read16(PORTDIO_INEN)
-#define bfin_write_PORTDIO_INEN(val) bfin_write16(PORTDIO_INEN, val)
-#define bfin_read_PORTEIO_FER() bfin_read16(PORTEIO_FER)
-#define bfin_write_PORTEIO_FER(val) bfin_write16(PORTEIO_FER, val)
-#define bfin_read_PORTEIO() bfin_read16(PORTEIO)
-#define bfin_write_PORTEIO(val) bfin_write16(PORTEIO, val)
-#define bfin_read_PORTEIO_CLEAR() bfin_read16(PORTEIO_CLEAR)
-#define bfin_write_PORTEIO_CLEAR(val) bfin_write16(PORTEIO_CLEAR, val)
-#define bfin_read_PORTEIO_SET() bfin_read16(PORTEIO_SET)
-#define bfin_write_PORTEIO_SET(val) bfin_write16(PORTEIO_SET, val)
-#define bfin_read_PORTEIO_TOGGLE() bfin_read16(PORTEIO_TOGGLE)
-#define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val)
-#define bfin_read_PORTEIO_DIR() bfin_read16(PORTEIO_DIR)
-#define bfin_write_PORTEIO_DIR(val) bfin_write16(PORTEIO_DIR, val)
-#define bfin_read_PORTEIO_INEN() bfin_read16(PORTEIO_INEN)
-#define bfin_write_PORTEIO_INEN(val) bfin_write16(PORTEIO_INEN, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
deleted file mode 100644
index acc15f3..0000000
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF539_H
-#define _CDEF_BF539_H
-
-/* Include MMRs Common to BF538 */
-#include "cdefBF538.h"
-
-#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0)
-#define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val)
-#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
-#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
-#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
-#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
-#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
-#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
-#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
-#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
-#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
-#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
-#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
-#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
-#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
-#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
-#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
-#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
-#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
-#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
-#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
-#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
-#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
-#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-#define bfin_read_MXVR_PLL_CTL_1() bfin_read32(MXVR_PLL_CTL_1)
-#define bfin_write_MXVR_PLL_CTL_1(val) bfin_write32(MXVR_PLL_CTL_1, val)
-#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-
-#endif /* _CDEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h
deleted file mode 100644
index 876a770..0000000
--- a/arch/blackfin/mach-bf538/include/mach/defBF538.h
+++ /dev/null
@@ -1,1749 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF538_H
-#define _DEF_BF538_H
-
-/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR 0xFFC00104 /* System Configuration registe */
-#define SIC_RVECT 0xFFC00108
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
-#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
-#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
-#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
-#define SPI0_REGBASE SPI0_CTL
-
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
-
-
-/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
-#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
-#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
-#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
-#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
-#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-/* Asynchronous Memory Controller */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-
-
-/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
-
-#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */
-
-
-
-/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
-
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-#define TWI0_REGBASE TWI0_CLKDIV
-
-/* the following are for backwards compatibility */
-#define TWI0_PRESCALE TWI0_CONTROL
-#define TWI0_INT_SRC TWI0_INT_STAT
-#define TWI0_INT_ENABLE TWI0_INT_MASK
-
-
-/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
-
-/* GPIO Port C Register Names */
-#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
-#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
-#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
-#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
-#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
-#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
-#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
-
-/* GPIO Port D Register Names */
-#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
-#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
-#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
-#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
-#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
-#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
-#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
-
-/* GPIO Port E Register Names */
-#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
-#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
-#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
-#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
-#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
-#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
-#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
-
-/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
-
-#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */
-
-
-
-/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
-#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
-
-#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
-
-#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
-
-#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
-
-#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
-
-#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
-
-#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
-
-#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
-
-#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
-
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */
-
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
-#define UART2_THR 0xFFC02100 /* Transmit Holding register */
-#define UART2_RBR 0xFFC02100 /* Receive Buffer register */
-#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
-#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
-#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
-#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
-#define UART2_LCR 0xFFC0210C /* Line Control Register */
-#define UART2_MCR 0xFFC02110 /* Modem Control Register */
-#define UART2_LSR 0xFFC02114 /* Line Status Register */
-#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */
-#define UART2_GCTL 0xFFC02124 /* Global Control Register */
-
-
-/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
-#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
-#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
-#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
-#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
-#define TWI1_REGBASE TWI1_CLKDIV
-
-
-/* the following are for backwards compatibility */
-#define TWI1_PRESCALE TWI1_CONTROL
-#define TWI1_INT_SRC TWI1_INT_STAT
-#define TWI1_INT_ENABLE TWI1_INT_MASK
-
-
-/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
-#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */
-#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */
-#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */
-#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */
-#define SPI1_REGBASE SPI1_CTL
-
-/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
-#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */
-#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */
-#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */
-#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */
-#define SPI2_REGBASE SPI2_CTL
-
-/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
-#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */
-#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */
-#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */
-#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */
-#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */
-#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */
-#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
-#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
-#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
-#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */
-#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */
-#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */
-#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */
-#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */
-#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */
-#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
-#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
-#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
-
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
-#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
-
-/* For Mailboxes 16-31 */
-#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
-#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
-
-#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
-
-#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
-/* the following is for backwards compatibility */
-#define CAN_CNF CAN_DEBUG
-
-#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
-#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
-#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
-
-/* Mailbox Acceptance Masks */
-#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-
-#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-
-/* CAN Acceptance Mask Macros */
-#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers */
-#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
-
-#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
-
-#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
-
-#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
-
-#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
-
-#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
-
-#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
-
-#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
-
-#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
-
-#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
-
-#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
-
-#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
-
-#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
-
-#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
-
-#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
-
-#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
-
-#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
-
-#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
-
-#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
-
-#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
-
-#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
-
-#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
-
-#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
-
-#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
-
-#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
-
-#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
-
-#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
-
-#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
-
-#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
-
-#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
-
-#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
-
-#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
-
-/* CAN Mailbox Area Macros */
-#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
-
-
-/*********************************************************************************** */
-/* System MMR Register Bits and Macros */
-/******************************************************************************* */
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
-#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
-#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
-#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
-#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
-#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
-#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
-#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
-#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
-#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
-#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
-#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
-#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
-#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
-#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
-#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
-#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
-#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
-#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
-#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
-#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
-#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
-#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
-#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
-#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
-#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
-#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
-#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
-#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */
-#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
-#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
-#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
-#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
-
-/* the following are for backwards compatibility */
-#define DMA0_ERR_IRQ DMAC0_ERR_IRQ
-#define DMA1_ERR_IRQ DMAC1_ERR_IRQ
-
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
-#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
-#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
-#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
-#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
-#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
-#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
-#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
-#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
-#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
-#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
-#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
-#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
-#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
-#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
-#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
-#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
-#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
-#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
-#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
-#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */
-#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */
-#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */
-
-/* the following are for backwards compatibility */
-#define MDMA0_IRQ MDMA1_0_IRQ
-#define MDMA1_IRQ MDMA1_1_IRQ
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* SIC_IMASKx Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
-#else
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWRx Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-#endif /* _MISRA_RULES */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#ifdef _MISRA_RULES
-#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#else
-#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#endif /* _MISRA_RULES */
-#define POL 0xC000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ********** DMA CONTROLLER MASKS ***********************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x0040 /* DMA Channel Type Indicator */
-#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x0400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x0800 /* DMA Read Operation Indicator */
-#define PMAP 0xF000 /* DMA Peripheral Map Field */
-
-/* PMAP Encodings For DMA Controller 0 */
-#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */
-#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */
-#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */
-
-/* PMAP Encodings For DMA Controller 1 */
-#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */
-#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */
-#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */
-#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */
-#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */
-#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */
-#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */
-#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */
-#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
-#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
-
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-/* PWM Timer bit definitions */
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001 /* Disable Timer 0 */
-#define TIMDIS1 0x0002 /* Disable Timer 1 */
-#define TIMDIS2 0x0004 /* Disable Timer 2 */
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x0001 /* Timer 0 Interrupt */
-#define TIMIL1 0x0002 /* Timer 1 Interrupt */
-#define TIMIL2 0x0004 /* Timer 2 Interrupt */
-#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
-#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#ifdef _MISRA_RULES
-#define ERR_TYP(x) (((x) & 0x03u) << 14)
-#else
-#define ERR_TYP(x) (((x) & 0x03) << 14)
-#endif /* _MISRA_RULES */
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */
-
-/* EBIU_AMGCTL Bit Positions */
-#define AMCKEN_P 0x0000 /* Enable CLKOUT */
-#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
deleted file mode 100644
index 199e871..0000000
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF539_H
-#define _DEF_BF539_H
-
-#include "defBF538.h"
-
-/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */
-
-#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */
-#define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */
-
-#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */
-#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */
-
-#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */
-
-#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */
-
-#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */
-
-#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
-
-#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */
-#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */
-#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */
-
-#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */
-
-#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */
-#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */
-#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */
-
-#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */
-#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */
-#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */
-
-#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */
-#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */
-#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */
-
-#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */
-#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */
-#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */
-
-#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */
-#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */
-#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */
-
-#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */
-#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */
-#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */
-
-#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */
-#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */
-#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */
-
-#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */
-#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */
-#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */
-
-#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
-
-#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
-
-#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
-
-#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */
-
-#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */
-
-#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */
-
-#define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */
-#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */
-#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */
-
-#endif /* _DEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/dma.h b/arch/blackfin/mach-bf538/include/mach/dma.h
deleted file mode 100644
index eb05cac..0000000
--- a/arch/blackfin/mach-bf538/include/mach/dma.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_PPI 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT0_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT1_TX 4
-#define CH_SPI0 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_SPORT2_RX 8
-#define CH_SPORT2_TX 9
-#define CH_SPORT3_RX 10
-#define CH_SPORT3_TX 11
-#define CH_SPI1 14
-#define CH_SPI2 15
-#define CH_UART1_RX 16
-#define CH_UART1_TX 17
-#define CH_UART2_RX 18
-#define CH_UART2_TX 19
-
-#define CH_MEM_STREAM0_DEST 20
-#define CH_MEM_STREAM0_SRC 21
-#define CH_MEM_STREAM1_DEST 22
-#define CH_MEM_STREAM1_SRC 23
-#define CH_MEM_STREAM2_DEST 24
-#define CH_MEM_STREAM2_SRC 25
-#define CH_MEM_STREAM3_DEST 26
-#define CH_MEM_STREAM3_SRC 27
-
-#define MAX_DMA_CHANNELS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
deleted file mode 100644
index 3561c7d..0000000
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-#ifdef CONFIG_GPIOLIB
-/* We only use the special logic with GPIOLIB devices */
-#define BFIN_SPECIAL_GPIO_BANKS 3
-#endif
-
-#define GPIO_PF0 0 /* PF */
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PC0 16 /* PC */
-#define GPIO_PC1 17
-#define GPIO_PC4 20
-#define GPIO_PC5 21
-#define GPIO_PC6 22
-#define GPIO_PC7 23
-#define GPIO_PC8 24
-#define GPIO_PC9 25
-#define GPIO_PD0 32 /* PD */
-#define GPIO_PD1 33
-#define GPIO_PD2 34
-#define GPIO_PD3 35
-#define GPIO_PD4 36
-#define GPIO_PD5 37
-#define GPIO_PD6 38
-#define GPIO_PD7 39
-#define GPIO_PD8 40
-#define GPIO_PD9 41
-#define GPIO_PD10 42
-#define GPIO_PD11 43
-#define GPIO_PD12 44
-#define GPIO_PD13 45
-#define GPIO_PE0 48 /* PE */
-#define GPIO_PE1 49
-#define GPIO_PE2 50
-#define GPIO_PE3 51
-#define GPIO_PE4 52
-#define GPIO_PE5 53
-#define GPIO_PE6 54
-#define GPIO_PE7 55
-#define GPIO_PE8 56
-#define GPIO_PE9 57
-#define GPIO_PE10 58
-#define GPIO_PE11 59
-#define GPIO_PE12 60
-#define GPIO_PE13 61
-#define GPIO_PE14 62
-#define GPIO_PE15 63
-
-#define PORT_F GPIO_PF0
-#define PORT_C GPIO_PC0
-#define PORT_D GPIO_PD0
-#define PORT_E GPIO_PE0
-
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
deleted file mode 100644
index 07ca069..0000000
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF538_IRQ_H_
-#define _BF538_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */
-#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC */
-#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */
-#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */
-#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
-#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */
-#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */
-#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */
-#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */
-#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */
-#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */
-#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */
-#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */
-#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */
-#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */
-#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */
-#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */
-#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */
-#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */
-#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */
-#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */
-#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */
-#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */
-#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */
-#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */
-#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */
-#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */
-#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */
-#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF15 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_PPI_ERROR_POS 8
-#define IRQ_SPORT0_ERROR_POS 12
-#define IRQ_SPORT1_ERROR_POS 16
-#define IRQ_SPI0_ERROR_POS 20
-#define IRQ_UART0_ERROR_POS 24
-#define IRQ_RTC_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_PPI_POS 0
-#define IRQ_SPORT0_RX_POS 4
-#define IRQ_SPORT0_TX_POS 8
-#define IRQ_SPORT1_RX_POS 12
-#define IRQ_SPORT1_TX_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_PORTF_INTA_POS 12
-#define IRQ_PORTF_INTB_POS 16
-#define IRQ_MEM0_DMA0_POS 20
-#define IRQ_MEM0_DMA1_POS 24
-#define IRQ_WATCH_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA1_ERROR_POS 0
-#define IRQ_SPORT2_ERROR_POS 4
-#define IRQ_SPORT3_ERROR_POS 8
-#define IRQ_SPI1_ERROR_POS 16
-#define IRQ_SPI2_ERROR_POS 20
-#define IRQ_UART1_ERROR_POS 24
-#define IRQ_UART2_ERROR_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_CAN_ERROR_POS 0
-#define IRQ_SPORT2_RX_POS 4
-#define IRQ_SPORT2_TX_POS 8
-#define IRQ_SPORT3_RX_POS 12
-#define IRQ_SPORT3_TX_POS 16
-#define IRQ_SPI1_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_SPI2_POS 0
-#define IRQ_UART1_RX_POS 4
-#define IRQ_UART1_TX_POS 8
-#define IRQ_UART2_RX_POS 12
-#define IRQ_UART2_TX_POS 16
-#define IRQ_TWI0_POS 20
-#define IRQ_TWI1_POS 24
-#define IRQ_CAN_RX_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MEM1_DMA0_POS 4
-#define IRQ_MEM1_DMA1_POS 8
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/mem_map.h b/arch/blackfin/mach-bf538/include/mach/mem_map.h
deleted file mode 100644
index aff00f4..0000000
--- a/arch/blackfin/mach-bf538/include/mach/mem_map.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * BF538 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x400
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF538/9 processors */
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0x14000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h
deleted file mode 100644
index 94cca67..0000000
--- a/arch/blackfin/mach-bf538/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h
deleted file mode 100644
index b773c5f..0000000
--- a/arch/blackfin/mach-bf538/include/mach/portmux.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES 64
-
-#define P_TMR2 (P_DONTCARE)
-#define P_TMR1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_TWI1_SCL (P_DONTCARE)
-#define P_TWI1_SDA (P_DONTCARE)
-
-#define P_SPORT1_TSCLK (P_DONTCARE)
-#define P_SPORT1_RSCLK (P_DONTCARE)
-#define P_SPORT0_TSCLK (P_DONTCARE)
-#define P_SPORT0_RSCLK (P_DONTCARE)
-#define P_SPORT1_DRSEC (P_DONTCARE)
-#define P_SPORT1_RFS (P_DONTCARE)
-#define P_SPORT1_DTPRI (P_DONTCARE)
-#define P_SPORT1_DTSEC (P_DONTCARE)
-#define P_SPORT1_TFS (P_DONTCARE)
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DONTCARE)
-#define P_SPORT0_RFS (P_DONTCARE)
-#define P_SPORT0_DTPRI (P_DONTCARE)
-#define P_SPORT0_DTSEC (P_DONTCARE)
-#define P_SPORT0_TFS (P_DONTCARE)
-#define P_SPORT0_DRPRI (P_DONTCARE)
-
-#define P_UART0_RX (P_DONTCARE)
-#define P_UART0_TX (P_DONTCARE)
-
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
-
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
-
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
-
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf538/ints-priority.c b/arch/blackfin/mach-bf538/ints-priority.c
deleted file mode 100644
index 1fa793c..0000000
--- a/arch/blackfin/mach-bf538/ints-priority.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
-
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
- ((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
- ((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) |
- ((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) |
- ((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
- ((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) |
- ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
- ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
- ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
- ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
- ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) |
- ((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) |
- ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
- ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
- ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
- ((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) |
- ((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
deleted file mode 100644
index 71c2a76..0000000
--- a/arch/blackfin/mach-bf548/Kconfig
+++ /dev/null
@@ -1,383 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF542
- def_bool y
- depends on BF542_std || BF542M
-config BF544
- def_bool y
- depends on BF544_std || BF544M
-config BF547
- def_bool y
- depends on BF547_std || BF547M
-config BF548
- def_bool y
- depends on BF548_std || BF548M
-config BF549
- def_bool y
- depends on BF549_std || BF549M
-
-config BF54xM
- def_bool y
- depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
-
-config BF54x
- def_bool y
- depends on (BF542 || BF544 || BF547 || BF548 || BF549)
-
-if (BF54x)
-
-source "arch/blackfin/mach-bf548/boards/Kconfig"
-
-menu "BF548 Specific Configuration"
-
-config DEB_DMA_URGENT
- bool "DMA has priority over core for ext. accesses"
- depends on BF54x
- default y
- help
- Treat any DEB1, DEB2 and DEB3 request as Urgent
-
-config BF548_ATAPI_ALTERNATIVE_PORT
- bool "BF548 ATAPI alternative port via GPIO"
- help
- BF548 ATAPI data and address PINs can be routed through
- async address or GPIO port F and G. Select y to route it
- to GPIO.
-
-choice
- prompt "UART2 DMA channel selection"
- depends on SERIAL_BFIN_UART2
- default UART2_DMA_RX_ON_DMA18
- help
- UART2 DMA channel selection
- RX -> DMA18
- TX -> DMA19
- or
- RX -> DMA13
- TX -> DMA14
-
-config UART2_DMA_RX_ON_DMA18
- bool "UART2 DMA RX -> DMA18 TX -> DMA19"
- help
- UART2 DMA channel assignment
- RX -> DMA18
- TX -> DMA19
- use SPORT2 default DMA channel
-
-config UART2_DMA_RX_ON_DMA13
- bool "UART2 DMA RX -> DMA13 TX -> DMA14"
- help
- UART2 DMA channel assignment
- RX -> DMA13
- TX -> DMA14
- use EPPI1 EPPI2 default DMA channel
-endchoice
-
-choice
- prompt "UART3 DMA channel selection"
- depends on SERIAL_BFIN_UART3
- default UART3_DMA_RX_ON_DMA20
- help
- UART3 DMA channel selection
- RX -> DMA20
- TX -> DMA21
- or
- RX -> DMA15
- TX -> DMA16
-
-config UART3_DMA_RX_ON_DMA20
- bool "UART3 DMA RX -> DMA20 TX -> DMA21"
- help
- UART3 DMA channel assignment
- RX -> DMA20
- TX -> DMA21
- use SPORT3 default DMA channel
-
-config UART3_DMA_RX_ON_DMA15
- bool "UART3 DMA RX -> DMA15 TX -> DMA16"
- help
- UART3 DMA channel assignment
- RX -> DMA15
- TX -> DMA16
- use PIXC default DMA channel
-
-endchoice
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMAC0_ERR
- int "IRQ_DMAC0_ERR"
- default 7
-config IRQ_EPPI0_ERR
- int "IRQ_EPPI0_ERR"
- default 7
-config IRQ_SPORT0_ERR
- int "IRQ_SPORT0_ERR"
- default 7
-config IRQ_SPORT1_ERR
- int "IRQ_SPORT1_ERR"
- default 7
-config IRQ_SPI0_ERR
- int "IRQ_SPI0_ERR"
- default 7
-config IRQ_UART0_ERR
- int "IRQ_UART0_ERR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_EPPI0
- int "IRQ_EPPI0"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_SPI0
- int "IRQ_SPI0"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_TIMER8
- int "IRQ_TIMER8"
- default 11
-config IRQ_TIMER9
- int "IRQ_TIMER9"
- default 11
-config IRQ_TIMER10
- int "IRQ_TIMER10"
- default 11
-config IRQ_PINT0
- int "IRQ_PINT0"
- default 12
-config IRQ_PINT1
- int "IRQ_PINT0"
- default 12
-config IRQ_MDMAS0
- int "IRQ_MDMAS0"
- default 13
-config IRQ_MDMAS1
- int "IRQ_DMDMAS1"
- default 13
-config IRQ_WATCHDOG
- int "IRQ_WATCHDOG"
- default 13
-config IRQ_DMAC1_ERR
- int "IRQ_DMAC1_ERR"
- default 7
-config IRQ_SPORT2_ERR
- int "IRQ_SPORT2_ERR"
- default 7
-config IRQ_SPORT3_ERR
- int "IRQ_SPORT3_ERR"
- default 7
-config IRQ_MXVR_DATA
- int "IRQ MXVR Data"
- default 7
-config IRQ_SPI1_ERR
- int "IRQ_SPI1_ERR"
- default 7
-config IRQ_SPI2_ERR
- int "IRQ_SPI2_ERR"
- default 7
-config IRQ_UART1_ERR
- int "IRQ_UART1_ERR"
- default 7
-config IRQ_UART2_ERR
- int "IRQ_UART2_ERR"
- default 7
-config IRQ_CAN0_ERR
- int "IRQ_CAN0_ERR"
- default 7
-config IRQ_SPORT2_RX
- int "IRQ_SPORT2_RX"
- default 9
-config IRQ_SPORT2_TX
- int "IRQ_SPORT2_TX"
- default 9
-config IRQ_SPORT3_RX
- int "IRQ_SPORT3_RX"
- default 9
-config IRQ_SPORT3_TX
- int "IRQ_SPORT3_TX"
- default 9
-config IRQ_EPPI1
- int "IRQ_EPPI1"
- default 9
-config IRQ_EPPI2
- int "IRQ_EPPI2"
- default 9
-config IRQ_SPI1
- int "IRQ_SPI1"
- default 10
-config IRQ_SPI2
- int "IRQ_SPI2"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_ATAPI_RX
- int "IRQ_ATAPI_RX"
- default 10
-config IRQ_ATAPI_TX
- int "IRQ_ATAPI_TX"
- default 10
-config IRQ_TWI0
- int "IRQ_TWI0"
- default 11
-config IRQ_TWI1
- int "IRQ_TWI1"
- default 11
-config IRQ_CAN0_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN0_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MDMAS2
- int "IRQ_MDMAS2"
- default 13
-config IRQ_MDMAS3
- int "IRQ_DMMAS3"
- default 13
-config IRQ_MXVR_ERR
- int "IRQ_MXVR_ERR"
- default 11
-config IRQ_MXVR_MSG
- int "IRQ_MXVR_MSG"
- default 11
-config IRQ_MXVR_PKT
- int "IRQ_MXVR_PKT"
- default 11
-config IRQ_EPPI1_ERR
- int "IRQ_EPPI1_ERR"
- default 7
-config IRQ_EPPI2_ERR
- int "IRQ_EPPI2_ERR"
- default 7
-config IRQ_UART3_ERR
- int "IRQ_UART3_ERR"
- default 7
-config IRQ_HOST_ERR
- int "IRQ_HOST_ERR"
- default 7
-config IRQ_PIXC_ERR
- int "IRQ_PIXC_ERR"
- default 7
-config IRQ_NFC_ERR
- int "IRQ_NFC_ERR"
- default 7
-config IRQ_ATAPI_ERR
- int "IRQ_ATAPI_ERR"
- default 7
-config IRQ_CAN1_ERR
- int "IRQ_CAN1_ERR"
- default 7
-config IRQ_HS_DMA_ERR
- int "IRQ Handshake DMA Status"
- default 7
-config IRQ_PIXC_IN0
- int "IRQ PIXC IN0"
- default 8
-config IRQ_PIXC_IN1
- int "IRQ PIXC IN1"
- default 8
-config IRQ_PIXC_OUT
- int "IRQ PIXC OUT"
- default 8
-config IRQ_SDH
- int "IRQ SDH"
- default 8
-config IRQ_CNT
- int "IRQ CNT"
- default 8
-config IRQ_KEY
- int "IRQ KEY"
- default 8
-config IRQ_CAN1_RX
- int "IRQ CAN1 RX"
- default 11
-config IRQ_CAN1_TX
- int "IRQ_CAN1_TX"
- default 11
-config IRQ_SDH_MASK0
- int "IRQ_SDH_MASK0"
- default 11
-config IRQ_SDH_MASK1
- int "IRQ_SDH_MASK1"
- default 11
-config IRQ_USB_INT0
- int "IRQ USB INT0"
- default 11
-config IRQ_USB_INT1
- int "IRQ USB INT1"
- default 11
-config IRQ_USB_INT2
- int "IRQ USB INT2"
- default 11
-config IRQ_USB_DMA
- int "IRQ USB DMA"
- default 11
-config IRQ_OTPSEC
- int "IRQ OPTSEC"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 11
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 11
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 11
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 11
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 11
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 11
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 11
-config IRQ_PINT2
- int "IRQ_PIN2"
- default 11
-config IRQ_PINT3
- int "IRQ_PIN3"
- default 11
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
deleted file mode 100644
index 56994b6..0000000
--- a/arch/blackfin/mach-bf548/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf537/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf548/boards/Kconfig b/arch/blackfin/mach-bf548/boards/Kconfig
deleted file mode 100644
index e8ce579..0000000
--- a/arch/blackfin/mach-bf548/boards/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN548_EZKIT
- help
- Select your board!
-
-config BFIN548_EZKIT
- bool "BF548-EZKIT"
- help
- BFIN548-EZKIT board support.
-
-config BFIN548_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF548"
- depends on (BF548)
- help
- CM-BF548 support for DEV-Board.
-
-endchoice
diff --git a/arch/blackfin/mach-bf548/boards/Makefile b/arch/blackfin/mach-bf548/boards/Makefile
deleted file mode 100644
index 319ef54..0000000
--- a/arch/blackfin/mach-bf548/boards/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# arch/blackfin/mach-bf548/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN548_BLUETECHNIX_CM) += cm_bf548.o
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
deleted file mode 100644
index 120c994..0000000
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ /dev/null
@@ -1,1268 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <mach/bf54x_keys.h>
-#include <asm/dpmc.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM-BF548";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
-
-#include <mach/bf54x-lq043.h>
-
-static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
- .width = 480,
- .height = 272,
- .xres = {480, 480, 480},
- .yres = {272, 272, 272},
- .bpp = {24, 24, 24},
- .disp = GPIO_PE3,
-};
-
-static struct resource bf54x_lq043_resources[] = {
- {
- .start = IRQ_EPPI0_ERR,
- .end = IRQ_EPPI0_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_lq043_device = {
- .name = "bf54x-lq043",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
- .resource = bf54x_lq043_resources,
- .dev = {
- .platform_data = &bf54x_lq043_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
-static unsigned int bf548_keymap[] = {
- KEYVAL(0, 0, KEY_ENTER),
- KEYVAL(0, 1, KEY_HELP),
- KEYVAL(0, 2, KEY_0),
- KEYVAL(0, 3, KEY_BACKSPACE),
- KEYVAL(1, 0, KEY_TAB),
- KEYVAL(1, 1, KEY_9),
- KEYVAL(1, 2, KEY_8),
- KEYVAL(1, 3, KEY_7),
- KEYVAL(2, 0, KEY_DOWN),
- KEYVAL(2, 1, KEY_6),
- KEYVAL(2, 2, KEY_5),
- KEYVAL(2, 3, KEY_4),
- KEYVAL(3, 0, KEY_UP),
- KEYVAL(3, 1, KEY_3),
- KEYVAL(3, 2, KEY_2),
- KEYVAL(3, 3, KEY_1),
-};
-
-static struct bfin_kpad_platform_data bf54x_kpad_data = {
- .rows = 4,
- .cols = 4,
- .keymap = bf548_keymap,
- .keymapsize = ARRAY_SIZE(bf548_keymap),
- .repeat = 0,
- .debounce_time = 5000, /* ns (5ms) */
- .coldrive_time = 1000, /* ns (1ms) */
- .keyup_test_interval = 50, /* ms (50ms) */
-};
-
-static struct resource bf54x_kpad_resources[] = {
- {
- .start = IRQ_KEY,
- .end = IRQ_KEY,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_kpad_device = {
- .name = "bf54x-keys",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
- .resource = bf54x_kpad_resources,
- .dev = {
- .platform_data = &bf54x_kpad_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_DLL,
- .end = UART0_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_DLL,
- .end = UART1_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PE10,
- .end = GPIO_PE10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PE9,
- .end = GPIO_PE9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_DLL,
- .end = UART2_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-static struct resource bfin_uart3_resources[] = {
- {
- .start = UART3_DLL,
- .end = UART3_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_TX,
- .end = IRQ_UART3_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_ERROR,
- .end = IRQ_UART3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_TX,
- .end = CH_UART3_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PB3,
- .end = GPIO_PB3,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PB2,
- .end = GPIO_PB2,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart3_peripherals[] = {
- P_UART3_TX, P_UART3_RX,
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- P_UART3_RTS, P_UART3_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart3_device = {
- .name = "bfin-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_uart3_resources),
- .resource = bfin_uart3_resources,
- .dev = {
- .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR3
-static struct resource bfin_sir3_resources[] = {
- {
- .start = 0xFFC03100,
- .end = 0xFFC031FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir3_device = {
- .name = "bfin_sir",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sir3_resources),
- .resource = bfin_sir3_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24000000,
- .end = 0x24000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE6,
- .end = IRQ_PE6,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFC03C00,
- .end = 0xFFC040FF,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PH6,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
-static struct resource bfin_atapi_resources[] = {
- {
- .start = 0xFFC03800,
- .end = 0xFFC0386F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_ATAPI_ERR,
- .end = IRQ_ATAPI_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_atapi_device = {
- .name = "pata-bf54x",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_atapi_resources),
- .resource = bfin_atapi_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = 4 * 1024 * 1024,
- .size = (256 - 4) * 1024 * 1024,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_SDH,
- .irq_int0 = IRQ_SDH_MASK0,
- .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
-};
-
-static struct platform_device bf54x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_ERROR,
- .end = IRQ_CAN0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = ¶_flash_data,
- },
- .num_resources = 1,
- .resource = ¶_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x1c0000,
- .offset = 0x40000
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bf54x_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-{
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PJ11,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
-},
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
- .num_chipselect = 4,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
- .num_chipselect = 4,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf548_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#ifdef CONFIG_BFIN_SIR3
- &bfin_sir3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
- &bf54x_lq043_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
- &bfin_atapi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf54x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf54x_spi_master0,
- &bf54x_spi_master1,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
- &bf54x_kpad_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- ¶_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-};
-
-static int __init cm_bf548_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices));
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bf54x_spi_board_info,
- ARRAY_SIZE(bf54x_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(cm_bf548_init);
-
-static struct platform_device *cm_bf548_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf548_early_devices,
- ARRAY_SIZE(cm_bf548_early_devices));
-}
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
deleted file mode 100644
index 3cdd483..0000000
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ /dev/null
@@ -1,2199 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-adi2.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <mach/bf54x_keys.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF548-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0C0000,
- .end = 0x2C0C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PG7,
- .end = IRQ_PG7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
-
-#include <mach/bf54x-lq043.h>
-
-static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
- .width = 95,
- .height = 54,
- .xres = {480, 480, 480},
- .yres = {272, 272, 272},
- .bpp = {24, 24, 24},
- .disp = GPIO_PE3,
-};
-
-static struct resource bf54x_lq043_resources[] = {
- {
- .start = IRQ_EPPI0_ERR,
- .end = IRQ_EPPI0_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_lq043_device = {
- .name = "bf54x-lq043",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
- .resource = bf54x_lq043_resources,
- .dev = {
- .platform_data = &bf54x_lq043_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
-static const unsigned int bf548_keymap[] = {
- KEYVAL(0, 0, KEY_ENTER),
- KEYVAL(0, 1, KEY_HELP),
- KEYVAL(0, 2, KEY_0),
- KEYVAL(0, 3, KEY_BACKSPACE),
- KEYVAL(1, 0, KEY_TAB),
- KEYVAL(1, 1, KEY_9),
- KEYVAL(1, 2, KEY_8),
- KEYVAL(1, 3, KEY_7),
- KEYVAL(2, 0, KEY_DOWN),
- KEYVAL(2, 1, KEY_6),
- KEYVAL(2, 2, KEY_5),
- KEYVAL(2, 3, KEY_4),
- KEYVAL(3, 0, KEY_UP),
- KEYVAL(3, 1, KEY_3),
- KEYVAL(3, 2, KEY_2),
- KEYVAL(3, 3, KEY_1),
-};
-
-static struct bfin_kpad_platform_data bf54x_kpad_data = {
- .rows = 4,
- .cols = 4,
- .keymap = bf548_keymap,
- .keymapsize = ARRAY_SIZE(bf548_keymap),
- .repeat = 0,
- .debounce_time = 5000, /* ns (5ms) */
- .coldrive_time = 1000, /* ns (1ms) */
- .keyup_test_interval = 50, /* ms (50ms) */
-};
-
-static struct resource bf54x_kpad_resources[] = {
- {
- .start = IRQ_KEY,
- .end = IRQ_KEY,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_kpad_device = {
- .name = "bf54x-keys",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
- .resource = bf54x_kpad_resources,
- .dev = {
- .platform_data = &bf54x_kpad_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_DLL,
- .end = UART0_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTE_FER,
- .end = PORTE_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_DLL,
- .end = UART1_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTH_FER,
- .end = PORTH_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PE10,
- .end = GPIO_PE10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PE9,
- .end = GPIO_PE9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_DLL,
- .end = UART2_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTB_FER,
- .end = PORTB_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-static struct resource bfin_uart3_resources[] = {
- {
- .start = UART3_DLL,
- .end = UART3_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTB_FER,
- .end = PORTB_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART3_TX,
- .end = IRQ_UART3_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_ERROR,
- .end = IRQ_UART3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_TX,
- .end = CH_UART3_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PB3,
- .end = GPIO_PB3,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PB2,
- .end = GPIO_PB2,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart3_peripherals[] = {
- P_UART3_TX, P_UART3_RX,
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- P_UART3_RTS, P_UART3_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart3_device = {
- .name = "bfin-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_uart3_resources),
- .resource = bfin_uart3_resources,
- .dev = {
- .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR3
-static struct resource bfin_sir3_resources[] = {
- {
- .start = 0xFFC03100,
- .end = 0xFFC031FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir3_device = {
- .name = "bfin_sir",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sir3_resources),
- .resource = bfin_sir3_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24000000,
- .end = 0x24000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE8,
- .end = IRQ_PE8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_32BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFC03C00,
- .end = 0xFFC040FF,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PE7,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-
-static unsigned short bfin_can0_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can0_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_ERROR,
- .end = IRQ_CAN0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can0_device = {
- .name = "bfin_can",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_can0_resources),
- .resource = bfin_can0_resources,
- .dev = {
- .platform_data = &bfin_can0_peripherals, /* Passed to driver */
- },
-};
-
-static unsigned short bfin_can1_peripherals[] = {
- P_CAN1_RX, P_CAN1_TX, 0
-};
-
-static struct resource bfin_can1_resources[] = {
- {
- .start = 0xFFC03200,
- .end = 0xFFC037FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN1_RX,
- .end = IRQ_CAN1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN1_TX,
- .end = IRQ_CAN1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN1_ERROR,
- .end = IRQ_CAN1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can1_device = {
- .name = "bfin_can",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_can1_resources),
- .resource = bfin_can1_resources,
- .dev = {
- .platform_data = &bfin_can1_peripherals, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
-static struct resource bfin_atapi_resources[] = {
- {
- .start = 0xFFC03800,
- .end = 0xFFC0386F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_ATAPI_ERR,
- .end = IRQ_ATAPI_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_atapi_device = {
- .name = "pata-bf54x",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_atapi_resources),
- .resource = bfin_atapi_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x80000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_SDH,
- .irq_int0 = IRQ_SDH_MASK0,
- .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
-};
-
-static struct platform_device bf54x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x80000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x400000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "config(nor)",
- .size = 0x8000 * 3,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "u-boot env(nor)",
- .size = 0x8000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x21ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00080000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_ADI2
-
-# define ADI_PINT_DEVNAME "adi-gpio-pint"
-# define ADI_GPIO_DEVNAME "adi-gpio"
-# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
-
-static struct platform_device bfin_pinctrl_device = {
- .name = ADI_PINCTRL_DEVNAME,
- .id = 0,
-};
-
-static struct resource bfin_pint0_resources[] = {
- {
- .start = PINT0_MASK_SET,
- .end = PINT0_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT0,
- .end = IRQ_PINT0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint0_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_pint0_resources),
- .resource = bfin_pint0_resources,
-};
-
-static struct resource bfin_pint1_resources[] = {
- {
- .start = PINT1_MASK_SET,
- .end = PINT1_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT1,
- .end = IRQ_PINT1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint1_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_pint1_resources),
- .resource = bfin_pint1_resources,
-};
-
-static struct resource bfin_pint2_resources[] = {
- {
- .start = PINT2_MASK_SET,
- .end = PINT2_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT2,
- .end = IRQ_PINT2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint2_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_pint2_resources),
- .resource = bfin_pint2_resources,
-};
-
-static struct resource bfin_pint3_resources[] = {
- {
- .start = PINT3_MASK_SET,
- .end = PINT3_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT3,
- .end = IRQ_PINT3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint3_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_pint3_resources),
- .resource = bfin_pint3_resources,
-};
-
-static struct resource bfin_gpa_resources[] = {
- {
- .start = PORTA_FER,
- .end = PORTA_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- { /* optional */
- .start = IRQ_PA0,
- .end = IRQ_PA0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
- .port_gpio_base = GPIO_PA0, /* Optional */
- .port_pin_base = GPIO_PA0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0, /* PINT0 */
- .pint_assign = true, /* PINT upper 16 bit */
- .pint_map = 0, /* mapping mask in PINT */
-};
-
-static struct platform_device bfin_gpa_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_gpa_resources),
- .resource = bfin_gpa_resources,
- .dev = {
- .platform_data = &bfin_gpa_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpb_resources[] = {
- {
- .start = PORTB_FER,
- .end = PORTB_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PB0,
- .end = IRQ_PB0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
- .port_gpio_base = GPIO_PB0,
- .port_pin_base = GPIO_PB0,
- .port_width = 15,
- .pint_id = 0,
- .pint_assign = true,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpb_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_gpb_resources),
- .resource = bfin_gpb_resources,
- .dev = {
- .platform_data = &bfin_gpb_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpc_resources[] = {
- {
- .start = PORTC_FER,
- .end = PORTC_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PC0,
- .end = IRQ_PC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
- .port_gpio_base = GPIO_PC0,
- .port_pin_base = GPIO_PC0,
- .port_width = 14,
- .pint_id = 2,
- .pint_assign = true,
- .pint_map = 0,
-};
-
-static struct platform_device bfin_gpc_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_gpc_resources),
- .resource = bfin_gpc_resources,
- .dev = {
- .platform_data = &bfin_gpc_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpd_resources[] = {
- {
- .start = PORTD_FER,
- .end = PORTD_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PD0,
- .end = IRQ_PD0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
- .port_gpio_base = GPIO_PD0,
- .port_pin_base = GPIO_PD0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 2,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpd_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_gpd_resources),
- .resource = bfin_gpd_resources,
- .dev = {
- .platform_data = &bfin_gpd_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpe_resources[] = {
- {
- .start = PORTE_FER,
- .end = PORTE_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE0,
- .end = IRQ_PE0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
- .port_gpio_base = GPIO_PE0,
- .port_pin_base = GPIO_PE0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = true,
- .pint_map = 2,
-};
-
-static struct platform_device bfin_gpe_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_gpe_resources),
- .resource = bfin_gpe_resources,
- .dev = {
- .platform_data = &bfin_gpe_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpf_resources[] = {
- {
- .start = PORTF_FER,
- .end = PORTF_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
- .port_gpio_base = GPIO_PF0,
- .port_pin_base = GPIO_PF0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = false,
- .pint_map = 3,
-};
-
-static struct platform_device bfin_gpf_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_gpf_resources),
- .resource = bfin_gpf_resources,
- .dev = {
- .platform_data = &bfin_gpf_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpg_resources[] = {
- {
- .start = PORTG_FER,
- .end = PORTG_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PG0,
- .end = IRQ_PG0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
- .port_gpio_base = GPIO_PG0,
- .port_pin_base = GPIO_PG0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpg_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 6,
- .num_resources = ARRAY_SIZE(bfin_gpg_resources),
- .resource = bfin_gpg_resources,
- .dev = {
- .platform_data = &bfin_gpg_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gph_resources[] = {
- {
- .start = PORTH_FER,
- .end = PORTH_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PH0,
- .end = IRQ_PH0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = {
- .port_gpio_base = GPIO_PH0,
- .port_pin_base = GPIO_PH0,
- .port_width = 14,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gph_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 7,
- .num_resources = ARRAY_SIZE(bfin_gph_resources),
- .resource = bfin_gph_resources,
- .dev = {
- .platform_data = &bfin_gph_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpi_resources[] = {
- {
- .start = PORTI_FER,
- .end = PORTI_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PI0,
- .end = IRQ_PI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = {
- .port_gpio_base = GPIO_PI0,
- .port_pin_base = GPIO_PI0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpi_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 8,
- .num_resources = ARRAY_SIZE(bfin_gpi_resources),
- .resource = bfin_gpi_resources,
- .dev = {
- .platform_data = &bfin_gpi_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpj_resources[] = {
- {
- .start = PORTJ_FER,
- .end = PORTJ_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PJ0,
- .end = IRQ_PJ0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = {
- .port_gpio_base = GPIO_PJ0,
- .port_pin_base = GPIO_PJ0,
- .port_width = 14,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpj_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 9,
- .num_resources = ARRAY_SIZE(bfin_gpj_resources),
- .resource = bfin_gpj_resources,
- .dev = {
- .platform_data = &bfin_gpj_pdata, /* Passed to driver */
- },
-};
-
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PC5,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
- .mode = SPI_MODE_3,
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
- P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
- P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI,
- .dma_ch = CH_EPPI1,
- .irq_err = IRQ_EPPI1_ERROR,
- .base = (void __iomem *)EPPI1_STATUS,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PG6;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF548",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20),
- .int_mask = 0xFFFFFFFF, /* disable error interrupt on eppi */
- .blank_clocks = 8, /* 8 clocks as SAV and EAV */
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = 212,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PC5,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
- SPORT_REQ(2),
- SPORT_REQ(3),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
- {
- .pin_req = &bfin_snd_pin[2][0],
- },
- {
- .pin_req = &bfin_snd_pin[3][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
- BFIN_SND_RES(2),
- BFIN_SND_RES(3),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
-static struct platform_device bfin_ad1980_codec_device = {
- .name = "ad1980",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-#if defined(CONFIG_PINCTRL_ADI2)
- &bfin_pinctrl_device,
- &bfin_pint0_device,
- &bfin_pint1_device,
- &bfin_pint2_device,
- &bfin_pint3_device,
- &bfin_gpa_device,
- &bfin_gpb_device,
- &bfin_gpc_device,
- &bfin_gpd_device,
- &bfin_gpe_device,
- &bfin_gpf_device,
- &bfin_gpg_device,
- &bfin_gph_device,
- &bfin_gpi_device,
- &bfin_gpj_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#ifdef CONFIG_BFIN_SIR3
- &bfin_sir3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
- &bf54x_lq043_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can0_device,
- &bfin_can1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
- &bfin_atapi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf54x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf54x_spi_master0,
- &bf54x_spi_master1,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
- &bf54x_kpad_device,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
- &bfin_ad1980_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-};
-
-/* Pin control settings */
-static struct pinctrl_map __initdata bfin_pinmux_map[] = {
- /* per-device maps */
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"),
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"),
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
- PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", "keys_4x4grp", "keys"),
- PIN_MAP_MUX_GROUP("bf54x-keys", "4bit", "pinctrl-adi2.0", "keys_4x4grp", "keys"),
- PIN_MAP_MUX_GROUP("bf54x-keys", "8bit", "pinctrl-adi2.0", "keys_8x8grp", "keys"),
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- /* Initialize pinmuxing */
- pinctrl_register_mappings(bfin_pinmux_map,
- ARRAY_SIZE(bfin_pinmux_map));
-
- i2c_register_board_info(0, bfin_i2c_board_info0,
- ARRAY_SIZE(bfin_i2c_board_info0));
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
- i2c_register_board_info(1, bfin_i2c_board_info1,
- ARRAY_SIZE(bfin_i2c_board_info1));
-#endif
-
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
deleted file mode 100644
index 69ead33..0000000
--- a/arch/blackfin/mach-bf548/dma.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) DMA20_NEXT_DESC_PTR,
- (struct dma_register *) DMA21_NEXT_DESC_PTR,
- (struct dma_register *) DMA22_NEXT_DESC_PTR,
- (struct dma_register *) DMA23_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
- case CH_SPI1:
- ret_irq = IRQ_SPI1;
- break;
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
- case CH_EPPI0:
- ret_irq = IRQ_EPPI0;
- break;
- case CH_EPPI1:
- ret_irq = IRQ_EPPI1;
- break;
- case CH_EPPI2:
- ret_irq = IRQ_EPPI2;
- break;
- case CH_PIXC_IMAGE:
- ret_irq = IRQ_PIXC_IN0;
- break;
- case CH_PIXC_OVERLAY:
- ret_irq = IRQ_PIXC_IN1;
- break;
- case CH_PIXC_OUTPUT:
- ret_irq = IRQ_PIXC_OUT;
- break;
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
- case CH_SPORT3_RX:
- ret_irq = IRQ_SPORT3_RX;
- break;
- case CH_SPORT3_TX:
- ret_irq = IRQ_SPORT3_TX;
- break;
- case CH_SDH:
- ret_irq = IRQ_SDH;
- break;
- case CH_SPI2:
- ret_irq = IRQ_SPI2;
- break;
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MDMAS0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MDMAS1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MDMAS2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MDMAS3;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
deleted file mode 100644
index 098fad6..0000000
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.0 or 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF548 silicon version 0.0, or 0.1
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* False Hardware Errors Caused by Fetches@the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* FIFO Boot Mode Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-/*
- * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
- * shows that the fix itself does not cover all cases.
- */
-#define ANOMALY_05000353 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* External Memory Read Access Hangs Core With PLL Bypass */
-#define ANOMALY_05000360 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000365 (1)
-/* Addressing Conflict between Boot ROM and Asynchronous Memory */
-#define ANOMALY_05000369 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
-/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
-/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
-#define ANOMALY_05000379 (1)
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
-#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
-/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
-#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
-#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
-#define ANOMALY_05000446 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
-/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
-#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
-/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
-#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem@Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
-/* USB DMA RX Data Corruption */
-#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
-/* USB TX DMA Hang */
-#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
-#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
-#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
-#define ANOMALY_05000500 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
-#define ANOMALY_05000502 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0x5411
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
-/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
-#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
-/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
-#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
-/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
-#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
-/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
-#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
-/* Changed Meaning of BCODE Field in SYSCR Register */
-#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
-/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
-#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
deleted file mode 100644
index 751e5e1..0000000
--- a/arch/blackfin/mach-bf548/include/mach/bf548.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF548_H__
-#define __MACH_BF548_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF542)
-# define CPU "BF542"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF544)
-# define CPU "BF544"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF547)
-# define CPU "BF547"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF548)
-# define CPU "BF548"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF549)
-# define CPU "BF549"
-# define CPUID 0x27de
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF48_H__ */
diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h b/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h
deleted file mode 100644
index 8821efe..0000000
--- a/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef BF54X_LQ043_H
-#define BF54X_LQ043_H
-
-struct bfin_bf54xfb_val {
- unsigned int defval;
- unsigned int min;
- unsigned int max;
-};
-
-struct bfin_bf54xfb_mach_info {
- unsigned char fixed_syncs; /* do not update sync/border */
-
- /* LCD types */
- int type;
-
- /* Screen size */
- int width;
- int height;
-
- /* Screen info */
- struct bfin_bf54xfb_val xres;
- struct bfin_bf54xfb_val yres;
- struct bfin_bf54xfb_val bpp;
-
- /* GPIOs */
- unsigned short disp;
-
-};
-
-#endif /* BF54X_LQ043_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h b/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h
deleted file mode 100644
index 49338ae..0000000
--- a/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_KPAD_H
-#define _BFIN_KPAD_H
-
-struct bfin_kpad_platform_data {
- int rows;
- int cols;
- const unsigned int *keymap;
- unsigned short keymapsize;
- unsigned short repeat;
- u32 debounce_time; /* in ns */
- u32 coldrive_time; /* in ns */
- u32 keyup_test_interval; /* in ms */
-};
-
-#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val))
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
deleted file mode 100644
index a77109f..0000000
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 4
-
-#define BFIN_UART_BF54X_STYLE
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
deleted file mode 100644
index 72da721..0000000
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf548.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF542
-# include "defBF542.h"
-#endif
-#ifdef CONFIG_BF544
-# include "defBF544.h"
-#endif
-#ifdef CONFIG_BF547
-# include "defBF547.h"
-#endif
-#ifdef CONFIG_BF548
-# include "defBF548.h"
-#endif
-#ifdef CONFIG_BF549
-# include "defBF549.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF542
-# include "cdefBF542.h"
-# endif
-# ifdef CONFIG_BF544
-# include "cdefBF544.h"
-# endif
-# ifdef CONFIG_BF547
-# include "cdefBF547.h"
-# endif
-# ifdef CONFIG_BF548
-# include "cdefBF548.h"
-# endif
-# ifdef CONFIG_BF549
-# include "cdefBF549.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
deleted file mode 100644
index 9163479..0000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
+++ /dev/null
@@ -1,554 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF542_H
-#define _CDEF_BF542_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-
-#endif /* _CDEF_BF542_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
deleted file mode 100644
index 33ec810..0000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
+++ /dev/null
@@ -1,913 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF544_H
-#define _CDEF_BF544_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF544_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
deleted file mode 100644
index be83f64..0000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
+++ /dev/null
@@ -1,796 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF547_H
-#define _CDEF_BF547_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2 Registers */
-
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
deleted file mode 100644
index bae67a6..0000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
+++ /dev/null
@@ -1,761 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF548_H
-#define _CDEF_BF548_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The BF548 is like the BF547, but has additional CANs */
-#include "cdefBF547.h"
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-
-#endif /* _CDEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
deleted file mode 100644
index 002136a..0000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF549_H
-#define _CDEF_BF549_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The BF549 is like the BF544, but has MXVR */
-#include "cdefBF547.h"
-
-/* MXVR Registers */
-
-#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
-
-/* MXVR Allocation Table Registers */
-
-#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
-
-/* MXVR Channel Assign Registers */
-
-#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-
-/* MXVR DMA0 Registers */
-
-#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR() bfin_read32(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR)
-#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_read32(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR)
-#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-
-/* MXVR DMA1 Registers */
-
-#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR() bfin_read32(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR)
-#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_read32(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR)
-#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-
-/* MXVR DMA2 Registers */
-
-#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR() bfin_read32(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR)
-#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_read32(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR)
-#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-
-/* MXVR DMA3 Registers */
-
-#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR() bfin_read32(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR)
-#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_read32(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR)
-#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-
-/* MXVR DMA4 Registers */
-
-#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR() bfin_read32(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR)
-#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_read32(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR)
-#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-
-/* MXVR DMA5 Registers */
-
-#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR() bfin_read32(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR)
-#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_read32(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR)
-#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-
-/* MXVR DMA6 Registers */
-
-#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR() bfin_read32(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR)
-#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_read32(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR)
-#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-
-/* MXVR DMA7 Registers */
-
-#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR() bfin_read32(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR)
-#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_read32(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR)
-#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-
-/* MXVR Asynch Packet Registers */
-
-#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR() bfin_read32(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR)
-#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_read32(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR)
-#define bfin_read_MXVR_APTB_START_ADDR() bfin_read32(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR)
-#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_read32(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR)
-
-/* MXVR Control Message Registers */
-
-#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR() bfin_read32(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR)
-#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_read32(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR)
-#define bfin_read_MXVR_CMTB_START_ADDR() bfin_read32(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR)
-#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_read32(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR)
-
-/* MXVR Remote Read Registers */
-
-#define bfin_read_MXVR_RRDB_START_ADDR() bfin_read32(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR)
-#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_read32(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR)
-
-/* MXVR Pattern Data Registers */
-
-#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
-
-/* MXVR Frame Counter Registers */
-
-#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-
-/* MXVR Routing Table Registers */
-
-#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
-#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
-#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL)
-#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
-#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL)
-#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
-#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL)
-#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
-#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
-#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
-
-#endif /* _CDEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
deleted file mode 100644
index 50c89c8..0000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ /dev/null
@@ -1,2633 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF54X_H
-#define _CDEF_BF54X_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-/* SIC Registers */
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-
-/* Watchdog Timer Registers */
-
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-
-/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPORT1 Registers */
-
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-/* Asynchronous Memory Control Registers */
-
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
-
-/* DDR Memory Control Registers */
-
-#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-
-/* DMAC0 Registers */
-
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-
-/* MDMA Stream 0 Registers */
-
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers */
-
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-
-/* EPPI1 Registers */
-
-#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA() bfin_read16(PORTA)
-#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-
-/* Port B Registers */
-
-#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB() bfin_read16(PORTB)
-#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-
-/* Port C Registers */
-
-#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC() bfin_read16(PORTC)
-#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-
-/* Port D Registers */
-
-#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD() bfin_read16(PORTD)
-#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-
-/* Port E Registers */
-
-#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE() bfin_read16(PORTE)
-#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-
-/* Port F Registers */
-
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF() bfin_read16(PORTF)
-#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-
-/* Port G Registers */
-
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG() bfin_read16(PORTG)
-#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-
-/* Port H Registers */
-
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH() bfin_read16(PORTH)
-#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-
-/* Port I Registers */
-
-#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI() bfin_read16(PORTI)
-#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-
-/* Port J Registers */
-
-#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ() bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-
-/* PWM Timer Registers */
-
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-/* Timer Groubfin_read_() of 8 */
-
-#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-
-/* DMAC1 Registers */
-
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-
-/* DMA Channel 21 Registers */
-
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-
-/* DMA Channel 22 Registers */
-
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-
-/* DMA Channel 23 Registers */
-
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-
-/* MDMA Stream 2 Registers */
-
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers */
-
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-
-/* SPORT2 Registers */
-
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-
-/* SPORT3 Registers */
-
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-
-/* EPPI2 Registers */
-
-#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-
-/* UART3 Registers */
-
-#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-/* DMA Peribfin_read_()heral Mux Register */
-
-#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
-
-#endif /* _CDEF_BF54X_H */
-
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
deleted file mode 100644
index ae4b889..0000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ /dev/null
@@ -1,763 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF542_H
-#define _DEF_BF542_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
-#define SDH_COMMAND 0xffc0390c /* SDH Command */
-#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
-#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
-#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
-#define SDH_STATUS 0xffc03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
-#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
-#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
-#define SDH_CFG 0xffc039c8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
-#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03c00 /* Function address register */
-#define USB_POWER 0xffc03c04 /* Power management register */
-#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03c20 /* USB frame number */
-#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for KPAD_CTL */
-
-#define KPAD_EN 0x1 /* Keypad Enable */
-#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
-#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
-#define KPAD_COLEN 0xe000 /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define DBON_SCALE 0xff /* Debounce Scale Value */
-#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define KPAD_ROW 0xff /* Rows Pressed */
-#define KPAD_COL 0xff00 /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
-#define KPAD_PRESSED 0x8 /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define XFER_DIR 0x8 /* Transfer Direction */
-#define IORDY_EN 0x10 /* IORDY Enable */
-#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define SOFT_RST 0x40 /* Soft Reset */
-#define DEV_RST 0x80 /* Device Reset */
-#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define DEV_ADDR 0x1f /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define ATAPI_ADDR 0x70 /* ATAPI address line status */
-#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define PIO_CSTATE 0xf /* PIO mode state machine current state */
-#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
-#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
-#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define T2_REG 0xff /* End of cycle time for register access transfers */
-#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
-#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
-#define T4_REG 0xf000 /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
-#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define TKW 0xff /* Selects DIOW negated pulsewidth */
-#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define TH 0xff /* Selects DIOW data hold */
-#define TEOC 0xff00 /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define TACK 0xff /* Selects setup and hold times for TACK */
-#define TENV 0xff00 /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define TDVS 0xff /* Selects data valid setup time */
-#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define TMLI 0xff00 /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define TZAH 0xff /* Selects minimum delay required for output */
-#define READY_PAUSE 0xff00 /* Selects ready to pause */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define RESET 0x8 /* Reset indicator */
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define SOFT_CONN 0x40 /* Soft connect */
-#define ISO_UPDATE 0x80 /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define RESUME_B 0x2 /* Resume indicator */
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define SOF_B 0x8 /* Start of frame */
-#define CONN_B 0x10 /* Connection indicator */
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define LSDEV 0x20 /* Low-speed indicator */
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define DATAEND 0x8 /* Data end indicator */
-#define SETUPEND 0x10 /* Setup end */
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_TH 0x4 /* error condition host mode */
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define MODE 0x4 /* DMA Bus error */
-#define INT_ENA 0x8 /* Interrupt enable */
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-
-/* ******************************************* */
-/* MULTI BIT MACRO ENUMERATIONS */
-/* ******************************************* */
-
-
-#endif /* _DEF_BF542_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
deleted file mode 100644
index 018ebfc..0000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF544_H
-#define _DEF_BF544_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
-
-/* EPPI0 Registers */
-
-#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define TWI1_REGBASE 0xffc02200
-#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
-#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define IMG_FORM 0x8 /* Image Data Format */
-#define OVR_FORM 0x10 /* Overlay Data Format */
-#define OUT_FORM 0x20 /* Output Data Format */
-#define UDS_MOD 0x40 /* Resampling Mode */
-#define TC_EN 0x80 /* Transparent Color Enable */
-#define IMG_STAT 0x300 /* Image FIFO Status */
-#define OVR_STAT 0xc00 /* Overlay FIFO Status */
-#define WM_LVL 0x3000 /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define A_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define A_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define A_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define A_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define A_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define B_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define B_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define B_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define B_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define B_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
-#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define A11 0x3ff /* A11 in the Coefficient Matrix */
-#define A12 0xffc00 /* A12 in the Coefficient Matrix */
-#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
-#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define A21 0x3ff /* A21 in the Coefficient Matrix */
-#define A22 0xffc00 /* A22 in the Coefficient Matrix */
-#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
-#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define A31 0x3ff /* A31 in the Coefficient Matrix */
-#define A32 0xffc00 /* A32 in the Coefficient Matrix */
-#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
-#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define A14 0x3ff /* A14 in the Bias Vector */
-#define A24 0xffc00 /* A24 in the Bias Vector */
-#define A34 0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
-#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
-#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define TIMEN8 0x1 /* Timer 8 Enable */
-#define TIMEN9 0x2 /* Timer 9 Enable */
-#define TIMEN10 0x4 /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define TIMDIS10 0x4 /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-#endif /* _DEF_BF544_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
deleted file mode 100644
index 7cc7928..0000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ /dev/null
@@ -1,1034 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF547_H
-#define _DEF_BF547_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
-
-/* Timer Registers */
-
-#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
-#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
-#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
-#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
-#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
-#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
-#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
-#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
-#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
-#define UART2_GCTL 0xffc02108 /* Global Control Register */
-#define UART2_LCR 0xffc0210c /* Line Control Register */
-#define UART2_MCR 0xffc02110 /* Modem Control Register */
-#define UART2_LSR 0xffc02114 /* Line Status Register */
-#define UART2_MSR 0xffc02118 /* Modem Status Register */
-#define UART2_SCR 0xffc0211c /* Scratch Register */
-#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
-#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
-#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define TWI1_REGBASE 0xffc02200
-#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2 Registers */
-
-#define SPI2_REGBASE 0xffc02400
-#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
-#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
-#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
-#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
-
-/* ATAPI Registers */
-
-#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
-#define SDH_COMMAND 0xffc0390c /* SDH Command */
-#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
-#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
-#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
-#define SDH_STATUS 0xffc03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
-#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
-#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
-#define SDH_CFG 0xffc039c8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
-#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
-#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03c00 /* Function address register */
-#define USB_POWER 0xffc03c04 /* Power management register */
-#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03c20 /* USB frame number */
-#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03fe0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03fe8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define IMG_FORM 0x8 /* Image Data Format */
-#define OVR_FORM 0x10 /* Overlay Data Format */
-#define OUT_FORM 0x20 /* Output Data Format */
-#define UDS_MOD 0x40 /* Resampling Mode */
-#define TC_EN 0x80 /* Transparent Color Enable */
-#define IMG_STAT 0x300 /* Image FIFO Status */
-#define OVR_STAT 0xc00 /* Overlay FIFO Status */
-#define WM_LVL 0x3000 /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define A_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define A_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define A_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define A_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define A_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define B_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define B_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define B_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define B_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define B_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define FRM_INT_EN 0x2 /* Interrupt@End of Frame */
-#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define A11 0x3ff /* A11 in the Coefficient Matrix */
-#define A12 0xffc00 /* A12 in the Coefficient Matrix */
-#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
-#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define A21 0x3ff /* A21 in the Coefficient Matrix */
-#define A22 0xffc00 /* A22 in the Coefficient Matrix */
-#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
-#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define A31 0x3ff /* A31 in the Coefficient Matrix */
-#define A32 0xffc00 /* A32 in the Coefficient Matrix */
-#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
-#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define A14 0x3ff /* A14 in the Bias Vector */
-#define A24 0xffc00 /* A24 in the Bias Vector */
-#define A34 0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
-#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
-#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
-
-/* Bit masks for KPAD_CTL */
-
-#define KPAD_EN 0x1 /* Keypad Enable */
-#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
-#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
-#define KPAD_COLEN 0xe000 /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define DBON_SCALE 0xff /* Debounce Scale Value */
-#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define KPAD_ROW 0xff /* Rows Pressed */
-#define KPAD_COL 0xff00 /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
-#define KPAD_PRESSED 0x8 /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define XFER_DIR 0x8 /* Transfer Direction */
-#define IORDY_EN 0x10 /* IORDY Enable */
-#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define SOFT_RST 0x40 /* Soft Reset */
-#define DEV_RST 0x80 /* Device Reset */
-#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define DEV_ADDR 0x1f /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define ATAPI_ADDR 0x70 /* ATAPI address line status */
-#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define PIO_CSTATE 0xf /* PIO mode state machine current state */
-#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
-#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
-#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define T2_REG 0xff /* End of cycle time for register access transfers */
-#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
-#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
-#define T4_REG 0xf000 /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
-#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define TKW 0xff /* Selects DIOW negated pulsewidth */
-#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define TH 0xff /* Selects DIOW data hold */
-#define TEOC 0xff00 /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define TACK 0xff /* Selects setup and hold times for TACK */
-#define TENV 0xff00 /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define TDVS 0xff /* Selects data valid setup time */
-#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define TMLI 0xff00 /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define TZAH 0xff /* Selects minimum delay required for output */
-#define READY_PAUSE 0xff00 /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define TIMEN8 0x1 /* Timer 8 Enable */
-#define TIMEN9 0x2 /* Timer 9 Enable */
-#define TIMEN10 0x4 /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define TIMDIS10 0x4 /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define RESET 0x8 /* Reset indicator */
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define SOFT_CONN 0x40 /* Soft connect */
-#define ISO_UPDATE 0x80 /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define RESUME_B 0x2 /* Resume indicator */
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define SOF_B 0x8 /* Start of frame */
-#define CONN_B 0x10 /* Connection indicator */
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define LSDEV 0x20 /* Low-speed indicator */
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define DATAEND 0x8 /* Data end indicator */
-#define SETUPEND 0x10 /* Setup end */
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_TH 0x4 /* error condition host mode */
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define MODE 0x4 /* DMA Bus error */
-#define INT_ENA 0x8 /* Interrupt enable */
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
deleted file mode 100644
index 27f2948..0000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ /dev/null
@@ -1,399 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF548_H
-#define _DEF_BF548_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The BF548 is like the BF547, but has additional CANs */
-#include "defBF547.h"
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-#endif /* _DEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
deleted file mode 100644
index ac569fc..0000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF549_H
-#define _DEF_BF549_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The BF549 is like the BF544, but has MXVR */
-#include "defBF547.h"
-
-/* MXVR Registers */
-
-#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */
-#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */
-#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */
-#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */
-#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */
-#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */
-#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */
-#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */
-#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */
-#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */
-
-/* MXVR Allocation Table Registers */
-
-#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */
-
-/* MXVR Channel Assign Registers */
-
-#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-/* MXVR DMA0 Registers */
-
-#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */
-#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */
-#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */
-
-/* MXVR DMA1 Registers */
-
-#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */
-#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */
-#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */
-
-/* MXVR DMA2 Registers */
-
-#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */
-#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */
-#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */
-
-/* MXVR DMA3 Registers */
-
-#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */
-#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */
-#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */
-
-/* MXVR DMA4 Registers */
-
-#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */
-#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */
-#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */
-
-/* MXVR DMA5 Registers */
-
-#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */
-#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */
-#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */
-
-/* MXVR DMA6 Registers */
-
-#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
-#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */
-#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */
-
-/* MXVR DMA7 Registers */
-
-#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */
-#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */
-#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */
-
-/* MXVR Asynch Packet Registers */
-
-#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */
-
-/* MXVR Control Message Registers */
-
-#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */
-
-/* MXVR Remote Read Registers */
-
-#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */
-
-/* MXVR Pattern Data Registers */
-
-#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */
-
-/* MXVR Frame Counter Registers */
-
-#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */
-
-/* MXVR Routing Table Registers */
-
-#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */
-#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */
-#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */
-#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */
-#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
-#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
-
-#endif /* _DEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
deleted file mode 100644
index 8f6e192..0000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ /dev/null
@@ -1,2294 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF54X_H
-#define _DEF_BF54X_H
-
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define PLL_CTL 0xffc00000 /* PLL Control Register */
-#define PLL_DIV 0xffc00004 /* PLL Divisor Register */
-#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xffc0000c /* PLL Status Register */
-#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define CHIPID 0xffc00014
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
-
-#define SWRST 0xffc00100 /* Software Reset Register */
-#define SYSCR 0xffc00104 /* System Configuration register */
-
-/* SIC Registers */
-
-#define SIC_RVECT 0xffc00108
-#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
-#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
-
-/* Watchdog Timer Registers */
-
-#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */
-
-/* RTC Registers */
-
-#define RTC_STAT 0xffc00300 /* RTC Status Register */
-#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */
-#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */
-
-/* UART0 Registers */
-
-#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */
-#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */
-#define UART0_GCTL 0xffc00408 /* Global Control Register */
-#define UART0_LCR 0xffc0040c /* Line Control Register */
-#define UART0_MCR 0xffc00410 /* Modem Control Register */
-#define UART0_LSR 0xffc00414 /* Line Status Register */
-#define UART0_MSR 0xffc00418 /* Modem Status Register */
-#define UART0_SCR 0xffc0041c /* Scratch Register */
-#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
-#define UART0_THR 0xffc00428 /* Transmit Hold Register */
-#define UART0_RBR 0xffc0042c /* Receive Buffer Register */
-
-/* SPI0 Registers */
-
-#define SPI0_REGBASE 0xffc00500
-#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
-#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
-#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */
-
-/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-#define TWI0_REGBASE 0xffc00700
-#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
-#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPORT1 Registers */
-
-#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */
-#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */
-
-/* Asynchronous Memory Control Registers */
-
-#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */
-
-/* DDR Memory Control Registers */
-
-#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */
-#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */
-#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */
-
-/* DDR BankRead and Write Count Registers */
-
-#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */
-
-/* DMAC0 Registers */
-
-#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
-
-/* DMA Channel 0 Registers */
-
-#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */
-
-/* DMA Channel 1 Registers */
-
-#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */
-
-/* DMA Channel 2 Registers */
-
-#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */
-
-/* DMA Channel 3 Registers */
-
-#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */
-
-/* DMA Channel 4 Registers */
-
-#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */
-
-/* DMA Channel 5 Registers */
-
-#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */
-
-/* DMA Channel 6 Registers */
-
-#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */
-
-/* DMA Channel 7 Registers */
-
-#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */
-
-/* DMA Channel 8 Registers */
-
-#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */
-
-/* DMA Channel 9 Registers */
-
-#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */
-
-/* DMA Channel 10 Registers */
-
-#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */
-
-/* DMA Channel 11 Registers */
-
-#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */
-
-/* MDMA Stream 0 Registers */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
-
-/* MDMA Stream 1 Registers */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
-
-/* UART3 Registers */
-
-#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xffc03108 /* Global Control Register */
-#define UART3_LCR 0xffc0310c /* Line Control Register */
-#define UART3_MCR 0xffc03110 /* Modem Control Register */
-#define UART3_LSR 0xffc03114 /* Line Status Register */
-#define UART3_MSR 0xffc03118 /* Modem Status Register */
-#define UART3_SCR 0xffc0311c /* Scratch Register */
-#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xffc03128 /* Transmit Hold Register */
-#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
-
-/* EPPI1 Registers */
-
-#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */
-
-/* Port Interrupt 0 Registers (32-bit) */
-
-#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
-
-/* Port Interrupt 1 Registers (32-bit) */
-
-#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
-
-/* Port Interrupt 2 Registers (32-bit) */
-
-#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
-
-/* Port Interrupt 3 Registers (32-bit) */
-
-#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
-
-/* Port A Registers */
-
-#define PORTA_FER 0xffc014c0 /* Function Enable Register */
-#define PORTA 0xffc014c4 /* GPIO Data Register */
-#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */
-#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */
-#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */
-#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */
-#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */
-
-/* Port B Registers */
-
-#define PORTB_FER 0xffc014e0 /* Function Enable Register */
-#define PORTB 0xffc014e4 /* GPIO Data Register */
-#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */
-#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */
-#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */
-#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */
-#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */
-
-/* Port C Registers */
-
-#define PORTC_FER 0xffc01500 /* Function Enable Register */
-#define PORTC 0xffc01504 /* GPIO Data Register */
-#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */
-#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */
-#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */
-
-/* Port D Registers */
-
-#define PORTD_FER 0xffc01520 /* Function Enable Register */
-#define PORTD 0xffc01524 /* GPIO Data Register */
-#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */
-#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */
-#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */
-
-/* Port E Registers */
-
-#define PORTE_FER 0xffc01540 /* Function Enable Register */
-#define PORTE 0xffc01544 /* GPIO Data Register */
-#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */
-#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */
-#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */
-
-/* Port F Registers */
-
-#define PORTF_FER 0xffc01560 /* Function Enable Register */
-#define PORTF 0xffc01564 /* GPIO Data Register */
-#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */
-#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */
-#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */
-
-/* Port G Registers */
-
-#define PORTG_FER 0xffc01580 /* Function Enable Register */
-#define PORTG 0xffc01584 /* GPIO Data Register */
-#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */
-#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */
-#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */
-
-/* Port H Registers */
-
-#define PORTH_FER 0xffc015a0 /* Function Enable Register */
-#define PORTH 0xffc015a4 /* GPIO Data Register */
-#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */
-#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */
-#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */
-#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */
-#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */
-
-/* Port I Registers */
-
-#define PORTI_FER 0xffc015c0 /* Function Enable Register */
-#define PORTI 0xffc015c4 /* GPIO Data Register */
-#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */
-#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */
-#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */
-#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */
-#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */
-
-/* Port J Registers */
-
-#define PORTJ_FER 0xffc015e0 /* Function Enable Register */
-#define PORTJ 0xffc015e4 /* GPIO Data Register */
-#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */
-#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */
-
-/* PWM Timer Registers */
-
-#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */
-#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */
-
-/* Timer Group of 8 */
-
-#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */
-
-/* DMAC1 Registers */
-
-#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
-
-/* DMA Channel 12 Registers */
-
-#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */
-
-/* DMA Channel 13 Registers */
-
-#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */
-
-/* DMA Channel 14 Registers */
-
-#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */
-
-/* DMA Channel 15 Registers */
-
-#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */
-
-/* DMA Channel 16 Registers */
-
-#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */
-
-/* DMA Channel 17 Registers */
-
-#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */
-
-/* DMA Channel 18 Registers */
-
-#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */
-
-/* DMA Channel 19 Registers */
-
-#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */
-
-/* DMA Channel 20 Registers */
-
-#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */
-
-/* DMA Channel 21 Registers */
-
-#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */
-
-/* DMA Channel 22 Registers */
-
-#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */
-
-/* DMA Channel 23 Registers */
-
-#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */
-
-/* MDMA Stream 2 Registers */
-
-#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
-
-/* MDMA Stream 3 Registers */
-
-#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
-
-/* UART1 Registers */
-
-#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */
-#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */
-#define UART1_GCTL 0xffc02008 /* Global Control Register */
-#define UART1_LCR 0xffc0200c /* Line Control Register */
-#define UART1_MCR 0xffc02010 /* Modem Control Register */
-#define UART1_LSR 0xffc02014 /* Line Status Register */
-#define UART1_MSR 0xffc02018 /* Modem Status Register */
-#define UART1_SCR 0xffc0201c /* Scratch Register */
-#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
-#define UART1_THR 0xffc02028 /* Transmit Hold Register */
-#define UART1_RBR 0xffc0202c /* Receive Buffer Register */
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPI1 Registers */
-
-#define SPI1_REGBASE 0xffc02300
-#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
-#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
-#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */
-
-/* SPORT2 Registers */
-
-#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */
-#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */
-#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */
-
-/* SPORT3 Registers */
-
-#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */
-#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */
-#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */
-#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */
-
-/* EPPI2 Registers */
-
-#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 0 Clock/Interrupt/Counter Registers */
-
-#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */
-
-/* UART3 Registers */
-
-#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xffc03108 /* Global Control Register */
-#define UART3_LCR 0xffc0310c /* Line Control Register */
-#define UART3_MCR 0xffc03110 /* Modem Control Register */
-#define UART3_LSR 0xffc03114 /* Line Status Register */
-#define UART3_MSR 0xffc03118 /* Modem Status Register */
-#define UART3_SCR 0xffc0311c /* Scratch Register */
-#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xffc03128 /* Transmit Hold Register */
-#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
-
-/* NFC Registers */
-
-#define NFC_CTL 0xffc03b00 /* NAND Control Register */
-#define NFC_STAT 0xffc03b04 /* NAND Status Register */
-#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */
-#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */
-#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */
-#define NFC_READ 0xffc03b2c /* NAND Read Data Register */
-#define NFC_ADDR 0xffc03b40 /* NAND Address Register */
-#define NFC_CMD 0xffc03b44 /* NAND Command Register */
-#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc04200 /* Configuration Register */
-#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc04208 /* Status Register */
-#define CNT_COMMAND 0xffc0420c /* Command Register */
-#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */
-#define CNT_COUNTER 0xffc04214 /* Counter Register */
-#define CNT_MAX 0xffc04218 /* Maximal Count Register */
-#define CNT_MIN 0xffc0421c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc04324 /* Secure Control */
-#define SECURE_STATUS 0xffc04328 /* Secure Status */
-
-/* DMA Peripheral Mux Register */
-
-#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* Bit masks for SIC_IAR0 */
-
-#define PLL_WAKEUP 0x1 /* PLL Wakeup */
-
-/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
-
-#define DMA0_ERR 0x2 /* DMA Controller 0 Error */
-#define EPPI0_ERR 0x4 /* EPPI0 Error */
-#define SPORT0_ERR 0x8 /* SPORT0 Error */
-#define SPORT1_ERR 0x10 /* SPORT1 Error */
-#define SPI0_ERR 0x20 /* SPI0 Error */
-#define UART0_ERR 0x40 /* UART0 Error */
-#define RTC 0x80 /* Real-Time Clock */
-#define DMA12 0x100 /* DMA Channel 12 */
-#define DMA0 0x200 /* DMA Channel 0 */
-#define DMA1 0x400 /* DMA Channel 1 */
-#define DMA2 0x800 /* DMA Channel 2 */
-#define DMA3 0x1000 /* DMA Channel 3 */
-#define DMA4 0x2000 /* DMA Channel 4 */
-#define DMA6 0x4000 /* DMA Channel 6 */
-#define DMA7 0x8000 /* DMA Channel 7 */
-#define PINT0 0x80000 /* Pin Interrupt 0 */
-#define PINT1 0x100000 /* Pin Interrupt 1 */
-#define MDMA0 0x200000 /* Memory DMA Stream 0 */
-#define MDMA1 0x400000 /* Memory DMA Stream 1 */
-#define WDOG 0x800000 /* Watchdog Timer */
-#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
-#define SPORT2_ERR 0x2000000 /* SPORT2 Error */
-#define SPORT3_ERR 0x4000000 /* SPORT3 Error */
-#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
-#define SPI1_ERR 0x10000000 /* SPI1 Error */
-#define SPI2_ERR 0x20000000 /* SPI2 Error */
-#define UART1_ERR 0x40000000 /* UART1 Error */
-#define UART2_ERR 0x80000000 /* UART2 Error */
-
-/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
-
-#define CAN0_ERR 0x1 /* CAN0 Error */
-#define DMA18 0x2 /* DMA Channel 18 */
-#define DMA19 0x4 /* DMA Channel 19 */
-#define DMA20 0x8 /* DMA Channel 20 */
-#define DMA21 0x10 /* DMA Channel 21 */
-#define DMA13 0x20 /* DMA Channel 13 */
-#define DMA14 0x40 /* DMA Channel 14 */
-#define DMA5 0x80 /* DMA Channel 5 */
-#define DMA23 0x100 /* DMA Channel 23 */
-#define DMA8 0x200 /* DMA Channel 8 */
-#define DMA9 0x400 /* DMA Channel 9 */
-#define DMA10 0x800 /* DMA Channel 10 */
-#define DMA11 0x1000 /* DMA Channel 11 */
-#define TWI0 0x2000 /* TWI0 */
-#define TWI1 0x4000 /* TWI1 */
-#define CAN0_RX 0x8000 /* CAN0 Receive */
-#define CAN0_TX 0x10000 /* CAN0 Transmit */
-#define MDMA2 0x20000 /* Memory DMA Stream 0 */
-#define MDMA3 0x40000 /* Memory DMA Stream 1 */
-#define MXVR_STAT 0x80000 /* MXVR Status */
-#define MXVR_CM 0x100000 /* MXVR Control Message */
-#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
-#define EPPI1_ERR 0x400000 /* EPPI1 Error */
-#define EPPI2_ERR 0x800000 /* EPPI2 Error */
-#define UART3_ERR 0x1000000 /* UART3 Error */
-#define HOST_ERR 0x2000000 /* Host DMA Port Error */
-#define USB_ERR 0x4000000 /* USB Error */
-#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
-#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
-#define ATAPI_ERR 0x20000000 /* ATAPI Error */
-#define CAN1_ERR 0x40000000 /* CAN1 Error */
-#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
-#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
-#define DMAR0 0x80000000 /* DMAR0 Block */
-#define DMAR1 0x80000000 /* DMAR1 Block */
-
-/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
-
-#define DMA15 0x1 /* DMA Channel 15 */
-#define DMA16 0x2 /* DMA Channel 16 */
-#define DMA17 0x4 /* DMA Channel 17 */
-#define DMA22 0x8 /* DMA Channel 22 */
-#define CNT 0x10 /* Counter */
-#define KEY 0x20 /* Keypad */
-#define CAN1_RX 0x40 /* CAN1 Receive */
-#define CAN1_TX 0x80 /* CAN1 Transmit */
-#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
-#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
-#define USB_EINT 0x400 /* USB Exception */
-#define USB_INT0 0x800 /* USB Interrupt 0 */
-#define USB_INT1 0x1000 /* USB Interrupt 1 */
-#define USB_INT2 0x2000 /* USB Interrupt 2 */
-#define USB_DMAINT 0x4000 /* USB DMA */
-#define OTPSEC 0x8000 /* OTP Access Complete */
-#define TIMER0 0x400000 /* Timer 0 */
-#define TIMER1 0x800000 /* Timer 1 */
-#define TIMER2 0x1000000 /* Timer 2 */
-#define TIMER3 0x2000000 /* Timer 3 */
-#define TIMER4 0x4000000 /* Timer 4 */
-#define TIMER5 0x8000000 /* Timer 5 */
-#define TIMER6 0x10000000 /* Timer 6 */
-#define TIMER7 0x20000000 /* Timer 7 */
-#define PINT2 0x40000000 /* Pin Interrupt 2 */
-#define PINT3 0x80000000 /* Pin Interrupt 3 */
-
-/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define CTYPE 0x40 /* DMA Channel Type */
-#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
-
-/* Bit masks for DMACx_TC_PER */
-
-#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
-#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
-#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
-#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
-
-/* Bit masks for DMACx_TC_CNT */
-
-#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
-#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
-#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */
-#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */
-
-/* Bit masks for DMAC1_PERIMUX */
-
-#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-
-/* Bit masks for EBIU_AMBCTL0 */
-
-#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
-#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
-#define B0TT 0xc /* Bank 0 transition time */
-#define B0ST 0x30 /* Bank 0 Setup time */
-#define B0HT 0xc0 /* Bank 0 Hold time */
-#define B0RAT 0xf00 /* Bank 0 Read access time */
-#define B0WAT 0xf000 /* Bank 0 write access time */
-#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
-#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
-#define B1TT 0xc0000 /* Bank 1 transition time */
-#define B1ST 0x300000 /* Bank 1 Setup time */
-#define B1HT 0xc00000 /* Bank 1 Hold time */
-#define B1RAT 0xf000000 /* Bank 1 Read access time */
-#define B1WAT 0xf0000000 /* Bank 1 write access time */
-
-/* Bit masks for EBIU_AMBCTL1 */
-
-#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
-#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
-#define B2TT 0xc /* Bank 2 transition time */
-#define B2ST 0x30 /* Bank 2 Setup time */
-#define B2HT 0xc0 /* Bank 2 Hold time */
-#define B2RAT 0xf00 /* Bank 2 Read access time */
-#define B2WAT 0xf000 /* Bank 2 write access time */
-#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
-#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
-#define B3TT 0xc0000 /* Bank 3 transition time */
-#define B3ST 0x300000 /* Bank 3 Setup time */
-#define B3HT 0xc00000 /* Bank 3 Hold time */
-#define B3RAT 0xf000000 /* Bank 3 Read access time */
-#define B3WAT 0xf0000000 /* Bank 3 write access time */
-
-/* Bit masks for EBIU_MBSCTL */
-
-#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
-#define AMSB1CTL 0xc /* Async Memory Bank 1 select */
-#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
-#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
-
-/* Bit masks for EBIU_MODE */
-
-#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
-#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
-#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
-#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
-
-/* Bit masks for EBIU_FCTL */
-
-#define TESTSETLOCK 0x1 /* Test set lock */
-#define BCLK 0x6 /* Burst clock frequency */
-#define PGWS 0x38 /* Page wait states */
-#define PGSZ 0x40 /* Page size */
-#define RDDL 0x380 /* Read data delay */
-
-/* Bit masks for EBIU_ARBSTAT */
-
-#define ARBSTAT 0x1 /* Arbitration status */
-#define BGSTAT 0x2 /* Bus grant status */
-
-/* Bit masks for EBIU_DDRCTL0 */
-
-#define TREFI 0x3fff /* Refresh Interval */
-#define TRFC 0x3c000 /* Auto-refresh command period */
-#define TRP 0x3c0000 /* Pre charge-to-active command period */
-#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
-#define TRC 0x3c000000 /* Active-to-active time */
-#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
-#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
-#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
-#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
-#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
-
-/* Bit masks for EBIU_DDRCTL1 */
-
-#define TRCD 0xf /* Active-to-Read/write delay */
-#define TMRD 0xf0 /* Mode register set to active */
-#define TWR 0x300 /* Write Recovery time */
-#define DDRDATWIDTH 0x3000 /* DDR data width */
-#define EXTBANKS 0xc000 /* External banks */
-#define DDRDEVWIDTH 0x30000 /* DDR device width */
-#define DDRDEVSIZE 0xc0000 /* DDR device size */
-#define TWTR 0xf0000000 /* Write-to-read delay */
-#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
-#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
-#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
-#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
-#define DDR_DATWIDTH 0x2000 /* DDR data width */
-#define EXTBANK_1 0 /* 1 external bank */
-#define EXTBANK_2 0x4000 /* 2 external banks */
-#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
-#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
-#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
-#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
-#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
-#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
-#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
-
-/* Bit masks for EBIU_DDRCTL2 */
-
-#define BURSTLENGTH 0x7 /* Burst length */
-#define CASLATENCY 0x70 /* CAS latency */
-#define DLLRESET 0x100 /* DLL Reset */
-#define REGE 0x1000 /* Register mode enable */
-#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
-#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
-#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
-#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
-
-/* Bit masks for EBIU_DDRCTL3 */
-
-#define PASR 0x7 /* Partial array self-refresh */
-
-/* Bit masks for EBIU_DDRQUE */
-
-#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
-#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
-#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
-#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
-#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
-#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
-#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
-
-/* Bit masks for EBIU_ERRMST */
-
-#define DEB1_ERROR 0x1 /* DEB1 Error */
-#define DEB2_ERROR 0x2 /* DEB2 Error */
-#define DEB3_ERROR 0x4 /* DEB3 Error */
-#define CORE_ERROR 0x8 /* Core error */
-#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
-#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
-#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
-#define CORE_MERROR 0x80 /* Core Error (2nd) */
-
-/* Bit masks for EBIU_RSTCTL */
-
-#define DDRSRESET 0x1 /* DDR soft reset */
-#define PFTCHSRESET 0x4 /* DDR prefetch reset */
-#define SRREQ 0x8 /* Self-refresh request */
-#define SRACK 0x10 /* Self-refresh acknowledge */
-#define MDDRENABLE 0x20 /* Mobile DDR enable */
-
-/* Bit masks for EBIU_DDRMCEN */
-
-#define B0WCENABLE 0x1 /* Bank 0 write count enable */
-#define B1WCENABLE 0x2 /* Bank 1 write count enable */
-#define B2WCENABLE 0x4 /* Bank 2 write count enable */
-#define B3WCENABLE 0x8 /* Bank 3 write count enable */
-#define B4WCENABLE 0x10 /* Bank 4 write count enable */
-#define B5WCENABLE 0x20 /* Bank 5 write count enable */
-#define B6WCENABLE 0x40 /* Bank 6 write count enable */
-#define B7WCENABLE 0x80 /* Bank 7 write count enable */
-#define B0RCENABLE 0x100 /* Bank 0 read count enable */
-#define B1RCENABLE 0x200 /* Bank 1 read count enable */
-#define B2RCENABLE 0x400 /* Bank 2 read count enable */
-#define B3RCENABLE 0x800 /* Bank 3 read count enable */
-#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
-#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
-#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
-#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
-#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
-#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
-#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
-#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
-#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
-#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
-#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
-#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
-
-/* Bit masks for EBIU_DDRMCCL */
-
-#define CB0WCOUNT 0x1 /* Clear write count 0 */
-#define CB1WCOUNT 0x2 /* Clear write count 1 */
-#define CB2WCOUNT 0x4 /* Clear write count 2 */
-#define CB3WCOUNT 0x8 /* Clear write count 3 */
-#define CB4WCOUNT 0x10 /* Clear write count 4 */
-#define CB5WCOUNT 0x20 /* Clear write count 5 */
-#define CB6WCOUNT 0x40 /* Clear write count 6 */
-#define CB7WCOUNT 0x80 /* Clear write count 7 */
-#define CBRCOUNT 0x100 /* Clear read count 0 */
-#define CB1RCOUNT 0x200 /* Clear read count 1 */
-#define CB2RCOUNT 0x400 /* Clear read count 2 */
-#define CB3RCOUNT 0x800 /* Clear read count 3 */
-#define CB4RCOUNT 0x1000 /* Clear read count 4 */
-#define CB5RCOUNT 0x2000 /* Clear read count 5 */
-#define CB6RCOUNT 0x4000 /* Clear read count 6 */
-#define CB7RCOUNT 0x8000 /* Clear read count 7 */
-#define CRACOUNT 0x10000 /* Clear row activation count */
-#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
-#define CARCOUNT 0x40000 /* Clear auto-refresh count */
-#define CG0COUNT 0x100000 /* Clear grant count 0 */
-#define CG1COUNT 0x200000 /* Clear grant count 1 */
-#define CG2COUNT 0x400000 /* Clear grant count 2 */
-#define CG3COUNT 0x800000 /* Clear grant count 3 */
-
-/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
-
-#define Px0 0x1 /* GPIO 0 */
-#define Px1 0x2 /* GPIO 1 */
-#define Px2 0x4 /* GPIO 2 */
-#define Px3 0x8 /* GPIO 3 */
-#define Px4 0x10 /* GPIO 4 */
-#define Px5 0x20 /* GPIO 5 */
-#define Px6 0x40 /* GPIO 6 */
-#define Px7 0x80 /* GPIO 7 */
-#define Px8 0x100 /* GPIO 8 */
-#define Px9 0x200 /* GPIO 9 */
-#define Px10 0x400 /* GPIO 10 */
-#define Px11 0x800 /* GPIO 11 */
-#define Px12 0x1000 /* GPIO 12 */
-#define Px13 0x2000 /* GPIO 13 */
-#define Px14 0x4000 /* GPIO 14 */
-#define Px15 0x8000 /* GPIO 15 */
-
-/* Bit masks for PORTA_MUX - PORTJ_MUX */
-
-#define PxM0 0x3 /* GPIO Mux 0 */
-#define PxM1 0xc /* GPIO Mux 1 */
-#define PxM2 0x30 /* GPIO Mux 2 */
-#define PxM3 0xc0 /* GPIO Mux 3 */
-#define PxM4 0x300 /* GPIO Mux 4 */
-#define PxM5 0xc00 /* GPIO Mux 5 */
-#define PxM6 0x3000 /* GPIO Mux 6 */
-#define PxM7 0xc000 /* GPIO Mux 7 */
-#define PxM8 0x30000 /* GPIO Mux 8 */
-#define PxM9 0xc0000 /* GPIO Mux 9 */
-#define PxM10 0x300000 /* GPIO Mux 10 */
-#define PxM11 0xc00000 /* GPIO Mux 11 */
-#define PxM12 0x3000000 /* GPIO Mux 12 */
-#define PxM13 0xc000000 /* GPIO Mux 13 */
-#define PxM14 0x30000000 /* GPIO Mux 14 */
-#define PxM15 0xc0000000 /* GPIO Mux 15 */
-
-
-/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
-
-#define IB0 0x1 /* Interrupt Bit 0 */
-#define IB1 0x2 /* Interrupt Bit 1 */
-#define IB2 0x4 /* Interrupt Bit 2 */
-#define IB3 0x8 /* Interrupt Bit 3 */
-#define IB4 0x10 /* Interrupt Bit 4 */
-#define IB5 0x20 /* Interrupt Bit 5 */
-#define IB6 0x40 /* Interrupt Bit 6 */
-#define IB7 0x80 /* Interrupt Bit 7 */
-#define IB8 0x100 /* Interrupt Bit 8 */
-#define IB9 0x200 /* Interrupt Bit 9 */
-#define IB10 0x400 /* Interrupt Bit 10 */
-#define IB11 0x800 /* Interrupt Bit 11 */
-#define IB12 0x1000 /* Interrupt Bit 12 */
-#define IB13 0x2000 /* Interrupt Bit 13 */
-#define IB14 0x4000 /* Interrupt Bit 14 */
-#define IB15 0x8000 /* Interrupt Bit 15 */
-
-/* Bit masks for TIMERx_CONFIG */
-
-#define TMODE 0x3 /* Timer Mode */
-#define PULSE_HI 0x4 /* Pulse Polarity */
-#define PERIOD_CNT 0x8 /* Period Count */
-#define IRQ_ENA 0x10 /* Interrupt Request Enable */
-#define TIN_SEL 0x20 /* Timer Input Select */
-#define OUT_DIS 0x40 /* Output Pad Disable */
-#define CLK_SEL 0x80 /* Timer Clock Select */
-#define TOGGLE_HI 0x100 /* Toggle Mode */
-#define EMU_RUN 0x200 /* Emulation Behavior Select */
-#define ERR_TYP 0xc000 /* Error Type */
-
-/* Bit masks for TIMER_ENABLE0 */
-
-#define TIMEN0 0x1 /* Timer 0 Enable */
-#define TIMEN1 0x2 /* Timer 1 Enable */
-#define TIMEN2 0x4 /* Timer 2 Enable */
-#define TIMEN3 0x8 /* Timer 3 Enable */
-#define TIMEN4 0x10 /* Timer 4 Enable */
-#define TIMEN5 0x20 /* Timer 5 Enable */
-#define TIMEN6 0x40 /* Timer 6 Enable */
-#define TIMEN7 0x80 /* Timer 7 Enable */
-
-/* Bit masks for TIMER_DISABLE0 */
-
-#define TIMDIS0 0x1 /* Timer 0 Disable */
-#define TIMDIS1 0x2 /* Timer 1 Disable */
-#define TIMDIS2 0x4 /* Timer 2 Disable */
-#define TIMDIS3 0x8 /* Timer 3 Disable */
-#define TIMDIS4 0x10 /* Timer 4 Disable */
-#define TIMDIS5 0x20 /* Timer 5 Disable */
-#define TIMDIS6 0x40 /* Timer 6 Disable */
-#define TIMDIS7 0x80 /* Timer 7 Disable */
-
-/* Bit masks for TIMER_STATUS0 */
-
-#define TIMIL0 0x1 /* Timer 0 Interrupt */
-#define TIMIL1 0x2 /* Timer 1 Interrupt */
-#define TIMIL2 0x4 /* Timer 2 Interrupt */
-#define TIMIL3 0x8 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
-#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x10000 /* Timer 4 Interrupt */
-#define TIMIL5 0x20000 /* Timer 5 Interrupt */
-#define TIMIL6 0x40000 /* Timer 6 Interrupt */
-#define TIMIL7 0x80000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define RSTDABL 0x2 /* Reset Disable */
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define EMUOVR 0x4000 /* Emulation Override */
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define SECURE1 0x2 /* SECURE 1 */
-#define SECURE2 0x4 /* SECURE 2 */
-#define SECURE3 0x8 /* SECURE 3 */
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define SECSTAT 0xe0 /* Secure Status */
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* Bit masks for EPPIx_STATUS */
-
-#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
-#define YFIFO_ERR 0x2 /* Luma FIFO Error */
-#define LTERR_OVR 0x4 /* Line Track Overflow */
-#define LTERR_UNDR 0x8 /* Line Track Underflow */
-#define FTERR_OVR 0x10 /* Frame Track Overflow */
-#define FTERR_UNDR 0x20 /* Frame Track Underflow */
-#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
-#define DMA1URQ 0x80 /* DMA1 Urgent Request */
-#define DMA0URQ 0x100 /* DMA0 Urgent Request */
-#define ERR_DET 0x4000 /* Preamble Error Detected */
-#define FLD 0x8000 /* Field */
-
-/* Bit masks for EPPIx_CONTROL */
-
-#define EPPI_EN 0x1 /* Enable */
-#define EPPI_DIR 0x2 /* Direction */
-#define XFR_TYPE 0xc /* Operating Mode */
-#define FS_CFG 0x30 /* Frame Sync Configuration */
-#define FLD_SEL 0x40 /* Field Select/Trigger */
-#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
-#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
-#define ICLKGEN 0x200 /* Internal Clock Generation */
-#define IFSGEN 0x400 /* Internal Frame Sync Generation */
-#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
-#define POLS 0x6000 /* Frame Sync Polarity */
-#define DLENGTH 0x38000 /* Data Length */
-#define SKIP_EN 0x40000 /* Skip Enable */
-#define SKIP_EO 0x80000 /* Skip Even or Odd */
-#define PACKEN 0x100000 /* Packing/Unpacking Enable */
-#define SWAPEN 0x200000 /* Swap Enable */
-#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
-#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
-#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
-#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
-#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
-#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
-#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
-
-#define DLEN_8 (0 << 15) /* 000 - 8 bits */
-#define DLEN_10 (1 << 15) /* 001 - 10 bits */
-#define DLEN_12 (2 << 15) /* 010 - 12 bits */
-#define DLEN_14 (3 << 15) /* 011 - 14 bits */
-#define DLEN_16 (4 << 15) /* 100 - 16 bits */
-#define DLEN_18 (5 << 15) /* 101 - 18 bits */
-#define DLEN_24 (6 << 15) /* 110 - 24 bits */
-
-
-/* Bit masks for EPPIx_FS2W_LVB */
-
-#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */
-#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */
-#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */
-#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
-
-/* Bit masks for EPPIx_FS2W_LAVF */
-
-#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */
-#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
-
-/* Bit masks for EPPIx_CLIP */
-
-#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */
-#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */
-#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
-#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
-
-
-/* ******************************************* */
-/* MULTI BIT MACRO ENUMERATIONS */
-/* ******************************************* */
-
-/* BCODE bit field options (SYSCFG register) */
-
-#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
-#define BCODE_FULLBOOT 0x0010 /* always perform full boot */
-#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
-#define BCODE_NOBOOT 0x0030 /* always perform full boot */
-
-/* TMODE in TIMERx_CONFIG bit field options */
-
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-
-/* PINTx Register Bit Definitions */
-
-#define PIQ0 0x00000001
-#define PIQ1 0x00000002
-#define PIQ2 0x00000004
-#define PIQ3 0x00000008
-
-#define PIQ4 0x00000010
-#define PIQ5 0x00000020
-#define PIQ6 0x00000040
-#define PIQ7 0x00000080
-
-#define PIQ8 0x00000100
-#define PIQ9 0x00000200
-#define PIQ10 0x00000400
-#define PIQ11 0x00000800
-
-#define PIQ12 0x00001000
-#define PIQ13 0x00002000
-#define PIQ14 0x00004000
-#define PIQ15 0x00008000
-
-#define PIQ16 0x00010000
-#define PIQ17 0x00020000
-#define PIQ18 0x00040000
-#define PIQ19 0x00080000
-
-#define PIQ20 0x00100000
-#define PIQ21 0x00200000
-#define PIQ22 0x00400000
-#define PIQ23 0x00800000
-
-#define PIQ24 0x01000000
-#define PIQ25 0x02000000
-#define PIQ26 0x04000000
-#define PIQ27 0x08000000
-
-#define PIQ28 0x10000000
-#define PIQ29 0x20000000
-#define PIQ30 0x40000000
-#define PIQ31 0x80000000
-
-/* Port Muxing Bit Fields for PORTx_MUX Registers */
-
-#define MUX0 0x00000003
-#define MUX0_0 0x00000000
-#define MUX0_1 0x00000001
-#define MUX0_2 0x00000002
-#define MUX0_3 0x00000003
-
-#define MUX1 0x0000000C
-#define MUX1_0 0x00000000
-#define MUX1_1 0x00000004
-#define MUX1_2 0x00000008
-#define MUX1_3 0x0000000C
-
-#define MUX2 0x00000030
-#define MUX2_0 0x00000000
-#define MUX2_1 0x00000010
-#define MUX2_2 0x00000020
-#define MUX2_3 0x00000030
-
-#define MUX3 0x000000C0
-#define MUX3_0 0x00000000
-#define MUX3_1 0x00000040
-#define MUX3_2 0x00000080
-#define MUX3_3 0x000000C0
-
-#define MUX4 0x00000300
-#define MUX4_0 0x00000000
-#define MUX4_1 0x00000100
-#define MUX4_2 0x00000200
-#define MUX4_3 0x00000300
-
-#define MUX5 0x00000C00
-#define MUX5_0 0x00000000
-#define MUX5_1 0x00000400
-#define MUX5_2 0x00000800
-#define MUX5_3 0x00000C00
-
-#define MUX6 0x00003000
-#define MUX6_0 0x00000000
-#define MUX6_1 0x00001000
-#define MUX6_2 0x00002000
-#define MUX6_3 0x00003000
-
-#define MUX7 0x0000C000
-#define MUX7_0 0x00000000
-#define MUX7_1 0x00004000
-#define MUX7_2 0x00008000
-#define MUX7_3 0x0000C000
-
-#define MUX8 0x00030000
-#define MUX8_0 0x00000000
-#define MUX8_1 0x00010000
-#define MUX8_2 0x00020000
-#define MUX8_3 0x00030000
-
-#define MUX9 0x000C0000
-#define MUX9_0 0x00000000
-#define MUX9_1 0x00040000
-#define MUX9_2 0x00080000
-#define MUX9_3 0x000C0000
-
-#define MUX10 0x00300000
-#define MUX10_0 0x00000000
-#define MUX10_1 0x00100000
-#define MUX10_2 0x00200000
-#define MUX10_3 0x00300000
-
-#define MUX11 0x00C00000
-#define MUX11_0 0x00000000
-#define MUX11_1 0x00400000
-#define MUX11_2 0x00800000
-#define MUX11_3 0x00C00000
-
-#define MUX12 0x03000000
-#define MUX12_0 0x00000000
-#define MUX12_1 0x01000000
-#define MUX12_2 0x02000000
-#define MUX12_3 0x03000000
-
-#define MUX13 0x0C000000
-#define MUX13_0 0x00000000
-#define MUX13_1 0x04000000
-#define MUX13_2 0x08000000
-#define MUX13_3 0x0C000000
-
-#define MUX14 0x30000000
-#define MUX14_0 0x00000000
-#define MUX14_1 0x10000000
-#define MUX14_2 0x20000000
-#define MUX14_3 0x30000000
-
-#define MUX15 0xC0000000
-#define MUX15_0 0x00000000
-#define MUX15_1 0x40000000
-#define MUX15_2 0x80000000
-#define MUX15_3 0xC0000000
-
-#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
- ((((b15)&3) << 30) | \
- (((b14)&3) << 28) | \
- (((b13)&3) << 26) | \
- (((b12)&3) << 24) | \
- (((b11)&3) << 22) | \
- (((b10)&3) << 20) | \
- (((b9) &3) << 18) | \
- (((b8) &3) << 16) | \
- (((b7) &3) << 14) | \
- (((b6) &3) << 12) | \
- (((b5) &3) << 10) | \
- (((b4) &3) << 8) | \
- (((b3) &3) << 6) | \
- (((b2) &3) << 4) | \
- (((b1) &3) << 2) | \
- (((b0) &3)))
-
-/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
-
-#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */
-#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
-#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
-#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */
-#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
-#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
-#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */
-#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
-#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
-#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */
-#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
-#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
-
-/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
-
-#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
-#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
-#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
-#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
-#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
-#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
-#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
-#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
-
-#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
-#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
-#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
-#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
-#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
-#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
-#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
-#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
-
-#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
-#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
-#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
-#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
-#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
-#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
-#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
-#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
-
-#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
-#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
-#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
-#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
-#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
-#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
-#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
-#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
-
-#endif /* _DEF_BF54X_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h
deleted file mode 100644
index 1a1091b..0000000
--- a/arch/blackfin/mach-bf548/include/mach/dma.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_RX 0
-#define CH_SPORT0_TX 1
-#define CH_SPORT1_RX 2
-#define CH_SPORT1_TX 3
-#define CH_SPI0 4
-#define CH_SPI1 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_UART1_RX 8
-#define CH_UART1_TX 9
-#define CH_ATAPI_RX 10
-#define CH_ATAPI_TX 11
-#define CH_EPPI0 12
-#define CH_EPPI1 13
-#define CH_EPPI2 14
-#define CH_PIXC_IMAGE 15
-#define CH_PIXC_OVERLAY 16
-#define CH_PIXC_OUTPUT 17
-#define CH_SPORT2_RX 18
-#define CH_SPORT2_TX 19
-#define CH_SPORT3_RX 20
-#define CH_SPORT3_TX 21
-#define CH_SDH 22
-#define CH_NFC 22
-#define CH_SPI2 23
-
-#if defined(CONFIG_UART2_DMA_RX_ON_DMA13)
-#define CH_UART2_RX 13
-#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */
-#define CH_UART2_TX 14
-#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */
-#else /* Default USE SPORT2's DMA Channel */
-#define CH_UART2_RX 18
-#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
-#define CH_UART2_TX 19
-#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
-#endif
-
-#if defined(CONFIG_UART3_DMA_RX_ON_DMA15)
-#define CH_UART3_RX 15
-#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */
-#define CH_UART3_TX 16
-#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */
-#else /* Default USE SPORT3's DMA Channel */
-#define CH_UART3_RX 20
-#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
-#define CH_UART3_TX 21
-#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
-#endif
-
-#define CH_MEM_STREAM0_DEST 24
-#define CH_MEM_STREAM0_SRC 25
-#define CH_MEM_STREAM1_DEST 26
-#define CH_MEM_STREAM1_SRC 27
-#define CH_MEM_STREAM2_DEST 28
-#define CH_MEM_STREAM2_SRC 29
-#define CH_MEM_STREAM3_DEST 30
-#define CH_MEM_STREAM3_SRC 31
-
-#define MAX_DMA_CHANNELS 32
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
deleted file mode 100644
index 006da1e..0000000
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define GPIO_PA0 0
-#define GPIO_PA1 1
-#define GPIO_PA2 2
-#define GPIO_PA3 3
-#define GPIO_PA4 4
-#define GPIO_PA5 5
-#define GPIO_PA6 6
-#define GPIO_PA7 7
-#define GPIO_PA8 8
-#define GPIO_PA9 9
-#define GPIO_PA10 10
-#define GPIO_PA11 11
-#define GPIO_PA12 12
-#define GPIO_PA13 13
-#define GPIO_PA14 14
-#define GPIO_PA15 15
-#define GPIO_PB0 16
-#define GPIO_PB1 17
-#define GPIO_PB2 18
-#define GPIO_PB3 19
-#define GPIO_PB4 20
-#define GPIO_PB5 21
-#define GPIO_PB6 22
-#define GPIO_PB7 23
-#define GPIO_PB8 24
-#define GPIO_PB9 25
-#define GPIO_PB10 26
-#define GPIO_PB11 27
-#define GPIO_PB12 28
-#define GPIO_PB13 29
-#define GPIO_PB14 30
-#define GPIO_PB15 31 /* N/A */
-#define GPIO_PC0 32
-#define GPIO_PC1 33
-#define GPIO_PC2 34
-#define GPIO_PC3 35
-#define GPIO_PC4 36
-#define GPIO_PC5 37
-#define GPIO_PC6 38
-#define GPIO_PC7 39
-#define GPIO_PC8 40
-#define GPIO_PC9 41
-#define GPIO_PC10 42
-#define GPIO_PC11 43
-#define GPIO_PC12 44
-#define GPIO_PC13 45
-#define GPIO_PC14 46 /* N/A */
-#define GPIO_PC15 47 /* N/A */
-#define GPIO_PD0 48
-#define GPIO_PD1 49
-#define GPIO_PD2 50
-#define GPIO_PD3 51
-#define GPIO_PD4 52
-#define GPIO_PD5 53
-#define GPIO_PD6 54
-#define GPIO_PD7 55
-#define GPIO_PD8 56
-#define GPIO_PD9 57
-#define GPIO_PD10 58
-#define GPIO_PD11 59
-#define GPIO_PD12 60
-#define GPIO_PD13 61
-#define GPIO_PD14 62
-#define GPIO_PD15 63
-#define GPIO_PE0 64
-#define GPIO_PE1 65
-#define GPIO_PE2 66
-#define GPIO_PE3 67
-#define GPIO_PE4 68
-#define GPIO_PE5 69
-#define GPIO_PE6 70
-#define GPIO_PE7 71
-#define GPIO_PE8 72
-#define GPIO_PE9 73
-#define GPIO_PE10 74
-#define GPIO_PE11 75
-#define GPIO_PE12 76
-#define GPIO_PE13 77
-#define GPIO_PE14 78
-#define GPIO_PE15 79
-#define GPIO_PF0 80
-#define GPIO_PF1 81
-#define GPIO_PF2 82
-#define GPIO_PF3 83
-#define GPIO_PF4 84
-#define GPIO_PF5 85
-#define GPIO_PF6 86
-#define GPIO_PF7 87
-#define GPIO_PF8 88
-#define GPIO_PF9 89
-#define GPIO_PF10 90
-#define GPIO_PF11 91
-#define GPIO_PF12 92
-#define GPIO_PF13 93
-#define GPIO_PF14 94
-#define GPIO_PF15 95
-#define GPIO_PG0 96
-#define GPIO_PG1 97
-#define GPIO_PG2 98
-#define GPIO_PG3 99
-#define GPIO_PG4 100
-#define GPIO_PG5 101
-#define GPIO_PG6 102
-#define GPIO_PG7 103
-#define GPIO_PG8 104
-#define GPIO_PG9 105
-#define GPIO_PG10 106
-#define GPIO_PG11 107
-#define GPIO_PG12 108
-#define GPIO_PG13 109
-#define GPIO_PG14 110
-#define GPIO_PG15 111
-#define GPIO_PH0 112
-#define GPIO_PH1 113
-#define GPIO_PH2 114
-#define GPIO_PH3 115
-#define GPIO_PH4 116
-#define GPIO_PH5 117
-#define GPIO_PH6 118
-#define GPIO_PH7 119
-#define GPIO_PH8 120
-#define GPIO_PH9 121
-#define GPIO_PH10 122
-#define GPIO_PH11 123
-#define GPIO_PH12 124
-#define GPIO_PH13 125
-#define GPIO_PH14 126 /* N/A */
-#define GPIO_PH15 127 /* N/A */
-#define GPIO_PI0 128
-#define GPIO_PI1 129
-#define GPIO_PI2 130
-#define GPIO_PI3 131
-#define GPIO_PI4 132
-#define GPIO_PI5 133
-#define GPIO_PI6 134
-#define GPIO_PI7 135
-#define GPIO_PI8 136
-#define GPIO_PI9 137
-#define GPIO_PI10 138
-#define GPIO_PI11 139
-#define GPIO_PI12 140
-#define GPIO_PI13 141
-#define GPIO_PI14 142
-#define GPIO_PI15 143
-#define GPIO_PJ0 144
-#define GPIO_PJ1 145
-#define GPIO_PJ2 146
-#define GPIO_PJ3 147
-#define GPIO_PJ4 148
-#define GPIO_PJ5 149
-#define GPIO_PJ6 150
-#define GPIO_PJ7 151
-#define GPIO_PJ8 152
-#define GPIO_PJ9 153
-#define GPIO_PJ10 154
-#define GPIO_PJ11 155
-#define GPIO_PJ12 156
-#define GPIO_PJ13 157
-#define GPIO_PJ14 158 /* N/A */
-#define GPIO_PJ15 159 /* N/A */
-
-#define MAX_BLACKFIN_GPIOS 160
-
-#define BFIN_GPIO_PINT 1
-#define NR_PINT_SYS_IRQS 4
-#define NR_PINTS 160
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
- unsigned short port_fer;
- unsigned short dummy1;
- unsigned short data;
- unsigned short dummy2;
- unsigned short data_set;
- unsigned short dummy3;
- unsigned short data_clear;
- unsigned short dummy4;
- unsigned short dir_set;
- unsigned short dummy5;
- unsigned short dir_clear;
- unsigned short dummy6;
- unsigned short inen;
- unsigned short dummy7;
- unsigned int port_mux;
-};
-
-#endif
-
-#include <mach-common/ports-a.h>
-#include <mach-common/ports-b.h>
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-#include <mach-common/ports-i.h>
-#include <mach-common/ports-j.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
deleted file mode 100644
index cf7cb72..0000000
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ /dev/null
@@ -1,454 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF548_IRQ_H_
-#define _BF548_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (3 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
-#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
-#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
-#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
-#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
-#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
-#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
-#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
-#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
-#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
-#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
-#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
-#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
-#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
-#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
-#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
-#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
-#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
-#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
-#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
-#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
-#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
-#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
-#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
-#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
-#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
-#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
-#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
-#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
-#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
-#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
-#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
-#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
-#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
-#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
-#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
-#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
-#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
-#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
-#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
-#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
-#define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
-#define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
-#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
-#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
-#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
-#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */
-#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */
-#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
-#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
-#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
-#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
-#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
-#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
-#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
-#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
-#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
-#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
-#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
-#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
-#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
-#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
-#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
-#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
-#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
-#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
-#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
-
-#define SYS_IRQS IRQ_PINT3
-
-#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
-#define IRQ_PA0 BFIN_PA_IRQ(0)
-#define IRQ_PA1 BFIN_PA_IRQ(1)
-#define IRQ_PA2 BFIN_PA_IRQ(2)
-#define IRQ_PA3 BFIN_PA_IRQ(3)
-#define IRQ_PA4 BFIN_PA_IRQ(4)
-#define IRQ_PA5 BFIN_PA_IRQ(5)
-#define IRQ_PA6 BFIN_PA_IRQ(6)
-#define IRQ_PA7 BFIN_PA_IRQ(7)
-#define IRQ_PA8 BFIN_PA_IRQ(8)
-#define IRQ_PA9 BFIN_PA_IRQ(9)
-#define IRQ_PA10 BFIN_PA_IRQ(10)
-#define IRQ_PA11 BFIN_PA_IRQ(11)
-#define IRQ_PA12 BFIN_PA_IRQ(12)
-#define IRQ_PA13 BFIN_PA_IRQ(13)
-#define IRQ_PA14 BFIN_PA_IRQ(14)
-#define IRQ_PA15 BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
-#define IRQ_PB0 BFIN_PB_IRQ(0)
-#define IRQ_PB1 BFIN_PB_IRQ(1)
-#define IRQ_PB2 BFIN_PB_IRQ(2)
-#define IRQ_PB3 BFIN_PB_IRQ(3)
-#define IRQ_PB4 BFIN_PB_IRQ(4)
-#define IRQ_PB5 BFIN_PB_IRQ(5)
-#define IRQ_PB6 BFIN_PB_IRQ(6)
-#define IRQ_PB7 BFIN_PB_IRQ(7)
-#define IRQ_PB8 BFIN_PB_IRQ(8)
-#define IRQ_PB9 BFIN_PB_IRQ(9)
-#define IRQ_PB10 BFIN_PB_IRQ(10)
-#define IRQ_PB11 BFIN_PB_IRQ(11)
-#define IRQ_PB12 BFIN_PB_IRQ(12)
-#define IRQ_PB13 BFIN_PB_IRQ(13)
-#define IRQ_PB14 BFIN_PB_IRQ(14)
-#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
-
-#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
-#define IRQ_PC0 BFIN_PC_IRQ(0)
-#define IRQ_PC1 BFIN_PC_IRQ(1)
-#define IRQ_PC2 BFIN_PC_IRQ(2)
-#define IRQ_PC3 BFIN_PC_IRQ(3)
-#define IRQ_PC4 BFIN_PC_IRQ(4)
-#define IRQ_PC5 BFIN_PC_IRQ(5)
-#define IRQ_PC6 BFIN_PC_IRQ(6)
-#define IRQ_PC7 BFIN_PC_IRQ(7)
-#define IRQ_PC8 BFIN_PC_IRQ(8)
-#define IRQ_PC9 BFIN_PC_IRQ(9)
-#define IRQ_PC10 BFIN_PC_IRQ(10)
-#define IRQ_PC11 BFIN_PC_IRQ(11)
-#define IRQ_PC12 BFIN_PC_IRQ(12)
-#define IRQ_PC13 BFIN_PC_IRQ(13)
-#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
-#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
-
-#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
-#define IRQ_PD0 BFIN_PD_IRQ(0)
-#define IRQ_PD1 BFIN_PD_IRQ(1)
-#define IRQ_PD2 BFIN_PD_IRQ(2)
-#define IRQ_PD3 BFIN_PD_IRQ(3)
-#define IRQ_PD4 BFIN_PD_IRQ(4)
-#define IRQ_PD5 BFIN_PD_IRQ(5)
-#define IRQ_PD6 BFIN_PD_IRQ(6)
-#define IRQ_PD7 BFIN_PD_IRQ(7)
-#define IRQ_PD8 BFIN_PD_IRQ(8)
-#define IRQ_PD9 BFIN_PD_IRQ(9)
-#define IRQ_PD10 BFIN_PD_IRQ(10)
-#define IRQ_PD11 BFIN_PD_IRQ(11)
-#define IRQ_PD12 BFIN_PD_IRQ(12)
-#define IRQ_PD13 BFIN_PD_IRQ(13)
-#define IRQ_PD14 BFIN_PD_IRQ(14)
-#define IRQ_PD15 BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
-#define IRQ_PE0 BFIN_PE_IRQ(0)
-#define IRQ_PE1 BFIN_PE_IRQ(1)
-#define IRQ_PE2 BFIN_PE_IRQ(2)
-#define IRQ_PE3 BFIN_PE_IRQ(3)
-#define IRQ_PE4 BFIN_PE_IRQ(4)
-#define IRQ_PE5 BFIN_PE_IRQ(5)
-#define IRQ_PE6 BFIN_PE_IRQ(6)
-#define IRQ_PE7 BFIN_PE_IRQ(7)
-#define IRQ_PE8 BFIN_PE_IRQ(8)
-#define IRQ_PE9 BFIN_PE_IRQ(9)
-#define IRQ_PE10 BFIN_PE_IRQ(10)
-#define IRQ_PE11 BFIN_PE_IRQ(11)
-#define IRQ_PE12 BFIN_PE_IRQ(12)
-#define IRQ_PE13 BFIN_PE_IRQ(13)
-#define IRQ_PE14 BFIN_PE_IRQ(14)
-#define IRQ_PE15 BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
-#define IRQ_PF0 BFIN_PF_IRQ(0)
-#define IRQ_PF1 BFIN_PF_IRQ(1)
-#define IRQ_PF2 BFIN_PF_IRQ(2)
-#define IRQ_PF3 BFIN_PF_IRQ(3)
-#define IRQ_PF4 BFIN_PF_IRQ(4)
-#define IRQ_PF5 BFIN_PF_IRQ(5)
-#define IRQ_PF6 BFIN_PF_IRQ(6)
-#define IRQ_PF7 BFIN_PF_IRQ(7)
-#define IRQ_PF8 BFIN_PF_IRQ(8)
-#define IRQ_PF9 BFIN_PF_IRQ(9)
-#define IRQ_PF10 BFIN_PF_IRQ(10)
-#define IRQ_PF11 BFIN_PF_IRQ(11)
-#define IRQ_PF12 BFIN_PF_IRQ(12)
-#define IRQ_PF13 BFIN_PF_IRQ(13)
-#define IRQ_PF14 BFIN_PF_IRQ(14)
-#define IRQ_PF15 BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
-#define IRQ_PG0 BFIN_PG_IRQ(0)
-#define IRQ_PG1 BFIN_PG_IRQ(1)
-#define IRQ_PG2 BFIN_PG_IRQ(2)
-#define IRQ_PG3 BFIN_PG_IRQ(3)
-#define IRQ_PG4 BFIN_PG_IRQ(4)
-#define IRQ_PG5 BFIN_PG_IRQ(5)
-#define IRQ_PG6 BFIN_PG_IRQ(6)
-#define IRQ_PG7 BFIN_PG_IRQ(7)
-#define IRQ_PG8 BFIN_PG_IRQ(8)
-#define IRQ_PG9 BFIN_PG_IRQ(9)
-#define IRQ_PG10 BFIN_PG_IRQ(10)
-#define IRQ_PG11 BFIN_PG_IRQ(11)
-#define IRQ_PG12 BFIN_PG_IRQ(12)
-#define IRQ_PG13 BFIN_PG_IRQ(13)
-#define IRQ_PG14 BFIN_PG_IRQ(14)
-#define IRQ_PG15 BFIN_PG_IRQ(15)
-
-#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1)
-#define IRQ_PH0 BFIN_PH_IRQ(0)
-#define IRQ_PH1 BFIN_PH_IRQ(1)
-#define IRQ_PH2 BFIN_PH_IRQ(2)
-#define IRQ_PH3 BFIN_PH_IRQ(3)
-#define IRQ_PH4 BFIN_PH_IRQ(4)
-#define IRQ_PH5 BFIN_PH_IRQ(5)
-#define IRQ_PH6 BFIN_PH_IRQ(6)
-#define IRQ_PH7 BFIN_PH_IRQ(7)
-#define IRQ_PH8 BFIN_PH_IRQ(8)
-#define IRQ_PH9 BFIN_PH_IRQ(9)
-#define IRQ_PH10 BFIN_PH_IRQ(10)
-#define IRQ_PH11 BFIN_PH_IRQ(11)
-#define IRQ_PH12 BFIN_PH_IRQ(12)
-#define IRQ_PH13 BFIN_PH_IRQ(13)
-#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */
-#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */
-
-#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1)
-#define IRQ_PI0 BFIN_PI_IRQ(0)
-#define IRQ_PI1 BFIN_PI_IRQ(1)
-#define IRQ_PI2 BFIN_PI_IRQ(2)
-#define IRQ_PI3 BFIN_PI_IRQ(3)
-#define IRQ_PI4 BFIN_PI_IRQ(4)
-#define IRQ_PI5 BFIN_PI_IRQ(5)
-#define IRQ_PI6 BFIN_PI_IRQ(6)
-#define IRQ_PI7 BFIN_PI_IRQ(7)
-#define IRQ_PI8 BFIN_PI_IRQ(8)
-#define IRQ_PI9 BFIN_PI_IRQ(9)
-#define IRQ_PI10 BFIN_PI_IRQ(10)
-#define IRQ_PI11 BFIN_PI_IRQ(11)
-#define IRQ_PI12 BFIN_PI_IRQ(12)
-#define IRQ_PI13 BFIN_PI_IRQ(13)
-#define IRQ_PI14 BFIN_PI_IRQ(14)
-#define IRQ_PI15 BFIN_PI_IRQ(15)
-
-#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1)
-#define IRQ_PJ0 BFIN_PJ_IRQ(0)
-#define IRQ_PJ1 BFIN_PJ_IRQ(1)
-#define IRQ_PJ2 BFIN_PJ_IRQ(2)
-#define IRQ_PJ3 BFIN_PJ_IRQ(3)
-#define IRQ_PJ4 BFIN_PJ_IRQ(4)
-#define IRQ_PJ5 BFIN_PJ_IRQ(5)
-#define IRQ_PJ6 BFIN_PJ_IRQ(6)
-#define IRQ_PJ7 BFIN_PJ_IRQ(7)
-#define IRQ_PJ8 BFIN_PJ_IRQ(8)
-#define IRQ_PJ9 BFIN_PJ_IRQ(9)
-#define IRQ_PJ10 BFIN_PJ_IRQ(10)
-#define IRQ_PJ11 BFIN_PJ_IRQ(11)
-#define IRQ_PJ12 BFIN_PJ_IRQ(12)
-#define IRQ_PJ13 BFIN_PJ_IRQ(13)
-#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
-#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
-
-#define GPIO_IRQ_BASE IRQ_PA0
-
-#define NR_MACH_IRQS (IRQ_PJ15 + 1)
-
-/* For compatibility reasons with existing code */
-
-#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
-#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
-#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
-#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
-#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
-#define IRQ_UART0_ERR IRQ_UART0_ERROR
-#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
-#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
-#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
-#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
-#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
-#define IRQ_UART1_ERR IRQ_UART1_ERROR
-#define IRQ_UART2_ERR IRQ_UART2_ERROR
-#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
-#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
-#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
-#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
-#define IRQ_UART3_ERR IRQ_UART3_ERROR
-#define IRQ_HOST_ERR IRQ_HOST_ERROR
-#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
-#define IRQ_NFC_ERR IRQ_NFC_ERROR
-#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
-#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
-#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMAC0_ERR_POS 4
-#define IRQ_EPPI0_ERR_POS 8
-#define IRQ_SPORT0_ERR_POS 12
-#define IRQ_SPORT1_ERR_POS 16
-#define IRQ_SPI0_ERR_POS 20
-#define IRQ_UART0_ERR_POS 24
-#define IRQ_RTC_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_EPPI0_POS 0
-#define IRQ_SPORT0_RX_POS 4
-#define IRQ_SPORT0_TX_POS 8
-#define IRQ_SPORT1_RX_POS 12
-#define IRQ_SPORT1_TX_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_TIMER8_POS 0
-#define IRQ_TIMER9_POS 4
-#define IRQ_TIMER10_POS 8
-#define IRQ_PINT0_POS 12
-#define IRQ_PINT1_POS 16
-#define IRQ_MDMAS0_POS 20
-#define IRQ_MDMAS1_POS 24
-#define IRQ_WATCH_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMAC1_ERR_POS 0
-#define IRQ_SPORT2_ERR_POS 4
-#define IRQ_SPORT3_ERR_POS 8
-#define IRQ_MXVR_DATA_POS 12
-#define IRQ_SPI1_ERR_POS 16
-#define IRQ_SPI2_ERR_POS 20
-#define IRQ_UART1_ERR_POS 24
-#define IRQ_UART2_ERR_POS 28
-
-/* IAR4 BIT FILEDS */
-#define IRQ_CAN0_ERR_POS 0
-#define IRQ_SPORT2_RX_POS 4
-#define IRQ_UART2_RX_POS 4
-#define IRQ_SPORT2_TX_POS 8
-#define IRQ_UART2_TX_POS 8
-#define IRQ_SPORT3_RX_POS 12
-#define IRQ_UART3_RX_POS 12
-#define IRQ_SPORT3_TX_POS 16
-#define IRQ_UART3_TX_POS 16
-#define IRQ_EPPI1_POS 20
-#define IRQ_EPPI2_POS 24
-#define IRQ_SPI1_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_SPI2_POS 0
-#define IRQ_UART1_RX_POS 4
-#define IRQ_UART1_TX_POS 8
-#define IRQ_ATAPI_RX_POS 12
-#define IRQ_ATAPI_TX_POS 16
-#define IRQ_TWI0_POS 20
-#define IRQ_TWI1_POS 24
-#define IRQ_CAN0_RX_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_CAN0_TX_POS 0
-#define IRQ_MDMAS2_POS 4
-#define IRQ_MDMAS3_POS 8
-#define IRQ_MXVR_ERR_POS 12
-#define IRQ_MXVR_MSG_POS 16
-#define IRQ_MXVR_PKT_POS 20
-#define IRQ_EPPI1_ERR_POS 24
-#define IRQ_EPPI2_ERR_POS 28
-
-/* IAR7 BIT FIELDS */
-#define IRQ_UART3_ERR_POS 0
-#define IRQ_HOST_ERR_POS 4
-#define IRQ_PIXC_ERR_POS 12
-#define IRQ_NFC_ERR_POS 16
-#define IRQ_ATAPI_ERR_POS 20
-#define IRQ_CAN1_ERR_POS 24
-#define IRQ_HS_DMA_ERR_POS 28
-
-/* IAR8 BIT FIELDS */
-#define IRQ_PIXC_IN0_POS 0
-#define IRQ_PIXC_IN1_POS 4
-#define IRQ_PIXC_OUT_POS 8
-#define IRQ_SDH_POS 12
-#define IRQ_CNT_POS 16
-#define IRQ_KEY_POS 20
-#define IRQ_CAN1_RX_POS 24
-#define IRQ_CAN1_TX_POS 28
-
-/* IAR9 BIT FIELDS */
-#define IRQ_SDH_MASK0_POS 0
-#define IRQ_SDH_MASK1_POS 4
-#define IRQ_USB_INT0_POS 12
-#define IRQ_USB_INT1_POS 16
-#define IRQ_USB_INT2_POS 20
-#define IRQ_USB_DMA_POS 24
-#define IRQ_OTPSEC_POS 28
-
-/* IAR10 BIT FIELDS */
-#define IRQ_TIMER0_POS 24
-#define IRQ_TIMER1_POS 28
-
-/* IAR11 BIT FIELDS */
-#define IRQ_TIMER2_POS 0
-#define IRQ_TIMER3_POS 4
-#define IRQ_TIMER4_POS 8
-#define IRQ_TIMER5_POS 12
-#define IRQ_TIMER6_POS 16
-#define IRQ_TIMER7_POS 20
-#define IRQ_PINT2_POS 24
-#define IRQ_PINT3_POS 28
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-/*
- * gpio pint registers layout
- */
-struct bfin_pint_regs {
- u32 mask_set;
- u32 mask_clear;
- u32 request;
- u32 assign;
- u32 edge_set;
- u32 edge_clear;
- u32 invert_set;
- u32 invert_clear;
- u32 pinstate;
- u32 latch;
- u32 __pad0[2];
-};
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h
deleted file mode 100644
index caac2df..0000000
--- a/arch/blackfin/mach-bf548/include/mach/mem_map.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * BF548 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x1000
-
-/* L1 Instruction ROM */
-
-#define L1_ROM_START 0xFFA14000
-#define L1_ROM_LENGTH 0x10000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF548 processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#define L2_START 0xFEB00000
-#if defined(CONFIG_BF542)
-# define L2_LENGTH 0
-#elif defined(CONFIG_BF544)
-# define L2_LENGTH 0x10000
-#else
-# define L2_LENGTH 0x20000
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
deleted file mode 100644
index 94cca67..0000000
--- a/arch/blackfin/mach-bf548/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h
deleted file mode 100644
index d9f8632..0000000
--- a/arch/blackfin/mach-bf548/include/mach/portmux.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-
-#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
-#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
-
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
-#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
-#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
-#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-
-#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
-
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
-#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
-#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
-#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
-#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
-#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
-#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
-#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
-#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
-#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
-#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
-#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
-#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
-#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
-#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
-#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
-#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#else
-# define P_ATAPI_D0A (P_DONTCARE)
-# define P_ATAPI_D1A (P_DONTCARE)
-# define P_ATAPI_D2A (P_DONTCARE)
-# define P_ATAPI_D3A (P_DONTCARE)
-# define P_ATAPI_D4A (P_DONTCARE)
-# define P_ATAPI_D5A (P_DONTCARE)
-# define P_ATAPI_D6A (P_DONTCARE)
-# define P_ATAPI_D7A (P_DONTCARE)
-# define P_ATAPI_D8A (P_DONTCARE)
-# define P_ATAPI_D9A (P_DONTCARE)
-# define P_ATAPI_D10A (P_DONTCARE)
-# define P_ATAPI_D11A (P_DONTCARE)
-# define P_ATAPI_D12A (P_DONTCARE)
-# define P_ATAPI_D13A (P_DONTCARE)
-# define P_ATAPI_D14A (P_DONTCARE)
-# define P_ATAPI_D15A (P_DONTCARE)
-#endif
-
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#else
-# define P_ATAPI_A0A (P_DONTCARE)
-# define P_ATAPI_A1A (P_DONTCARE)
-# define P_ATAPI_A2A (P_DONTCARE)
-#endif
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-
-#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
-#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
-#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
-#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
-#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
-#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
-#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
-#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
-#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
-#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
-#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
-#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
-#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
-#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
-#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
-#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
-#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
-
-#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
-#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
-#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
-#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
-#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
-#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
-#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
-#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
-#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
-#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
-#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
-#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
-
-
-#define P_NAND_D0 (P_DONTCARE)
-#define P_NAND_D1 (P_DONTCARE)
-#define P_NAND_D2 (P_DONTCARE)
-#define P_NAND_D3 (P_DONTCARE)
-#define P_NAND_D4 (P_DONTCARE)
-#define P_NAND_D5 (P_DONTCARE)
-#define P_NAND_D6 (P_DONTCARE)
-#define P_NAND_D7 (P_DONTCARE)
-#define P_NAND_WE (P_DONTCARE)
-#define P_NAND_RE (P_DONTCARE)
-#define P_NAND_CLE (P_DONTCARE)
-#define P_NAND_ALE (P_DONTCARE)
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
deleted file mode 100644
index 48dd3a4..0000000
--- a/arch/blackfin/mach-bf548/ints-priority.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
- ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
- ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
- ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
- ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
- ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
- ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
- ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
- ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
- ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
- ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
- ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
- ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
- ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
- ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
- ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
- ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
- ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
- ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
- ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
- ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
- ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
- ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
- ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
- ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
- ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
- ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
- ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
- ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
- ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
- ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
- ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
- ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
- ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
- ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
- ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
- ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
-
- bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
- ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
- ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
- ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
- ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
- ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
- ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
-
- bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
- ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
- ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
- ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
- ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
- ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
-
- bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
- ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
- ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
- ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
- ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
- ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
- ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
-
- bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
-
- bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
- ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig
deleted file mode 100644
index 059c3cb..0000000
--- a/arch/blackfin/mach-bf561/Kconfig
+++ /dev/null
@@ -1,213 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF561)
-
-source "arch/blackfin/mach-bf561/boards/Kconfig"
-
-menu "BF561 Specific Configuration"
-
-if (!SMP)
-
-comment "Core B Support"
-
-config BF561_COREB
- bool "Enable Core B loader"
- default y
-
-endif
-
-comment "Interrupt Priority Assignment"
-
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "PLL Wakeup Interrupt"
- default 7
-config IRQ_DMA1_ERROR
- int "DMA1 Error (generic)"
- default 7
-config IRQ_DMA2_ERROR
- int "DMA2 Error (generic)"
- default 7
-config IRQ_IMDMA_ERROR
- int "IMDMA Error (generic)"
- default 7
-config IRQ_PPI0_ERROR
- int "PPI0 Error Interrupt"
- default 7
-config IRQ_PPI1_ERROR
- int "PPI1 Error Interrupt"
- default 7
-config IRQ_SPORT0_ERROR
- int "SPORT0 Error Interrupt"
- default 7
-config IRQ_SPORT1_ERROR
- int "SPORT1 Error Interrupt"
- default 7
-config IRQ_SPI_ERROR
- int "SPI Error Interrupt"
- default 7
-config IRQ_UART_ERROR
- int "UART Error Interrupt"
- default 7
-config IRQ_RESERVED_ERROR
- int "Reserved Interrupt"
- default 7
-config IRQ_DMA1_0
- int "DMA1 0 Interrupt(PPI1)"
- default 8
-config IRQ_DMA1_1
- int "DMA1 1 Interrupt(PPI2)"
- default 8
-config IRQ_DMA1_2
- int "DMA1 2 Interrupt"
- default 8
-config IRQ_DMA1_3
- int "DMA1 3 Interrupt"
- default 8
-config IRQ_DMA1_4
- int "DMA1 4 Interrupt"
- default 8
-config IRQ_DMA1_5
- int "DMA1 5 Interrupt"
- default 8
-config IRQ_DMA1_6
- int "DMA1 6 Interrupt"
- default 8
-config IRQ_DMA1_7
- int "DMA1 7 Interrupt"
- default 8
-config IRQ_DMA1_8
- int "DMA1 8 Interrupt"
- default 8
-config IRQ_DMA1_9
- int "DMA1 9 Interrupt"
- default 8
-config IRQ_DMA1_10
- int "DMA1 10 Interrupt"
- default 8
-config IRQ_DMA1_11
- int "DMA1 11 Interrupt"
- default 8
-config IRQ_DMA2_0
- int "DMA2 0 (SPORT0 RX)"
- default 9
-config IRQ_DMA2_1
- int "DMA2 1 (SPORT0 TX)"
- default 9
-config IRQ_DMA2_2
- int "DMA2 2 (SPORT1 RX)"
- default 9
-config IRQ_DMA2_3
- int "DMA2 3 (SPORT2 TX)"
- default 9
-config IRQ_DMA2_4
- int "DMA2 4 (SPI)"
- default 9
-config IRQ_DMA2_5
- int "DMA2 5 (UART RX)"
- default 9
-config IRQ_DMA2_6
- int "DMA2 6 (UART TX)"
- default 9
-config IRQ_DMA2_7
- int "DMA2 7 Interrupt"
- default 9
-config IRQ_DMA2_8
- int "DMA2 8 Interrupt"
- default 9
-config IRQ_DMA2_9
- int "DMA2 9 Interrupt"
- default 9
-config IRQ_DMA2_10
- int "DMA2 10 Interrupt"
- default 9
-config IRQ_DMA2_11
- int "DMA2 11 Interrupt"
- default 9
-config IRQ_TIMER0
- int "TIMER 0 Interrupt"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "TIMER 1 Interrupt"
- default 10
-config IRQ_TIMER2
- int "TIMER 2 Interrupt"
- default 10
-config IRQ_TIMER3
- int "TIMER 3 Interrupt"
- default 10
-config IRQ_TIMER4
- int "TIMER 4 Interrupt"
- default 10
-config IRQ_TIMER5
- int "TIMER 5 Interrupt"
- default 10
-config IRQ_TIMER6
- int "TIMER 6 Interrupt"
- default 10
-config IRQ_TIMER7
- int "TIMER 7 Interrupt"
- default 10
-config IRQ_TIMER8
- int "TIMER 8 Interrupt"
- default 10
-config IRQ_TIMER9
- int "TIMER 9 Interrupt"
- default 10
-config IRQ_TIMER10
- int "TIMER 10 Interrupt"
- default 10
-config IRQ_TIMER11
- int "TIMER 11 Interrupt"
- default 10
-config IRQ_PROG0_INTA
- int "Programmable Flags0 A (8)"
- default 11
-config IRQ_PROG0_INTB
- int "Programmable Flags0 B (8)"
- default 11
-config IRQ_PROG1_INTA
- int "Programmable Flags1 A (8)"
- default 11
-config IRQ_PROG1_INTB
- int "Programmable Flags1 B (8)"
- default 11
-config IRQ_PROG2_INTA
- int "Programmable Flags2 A (8)"
- default 11
-config IRQ_PROG2_INTB
- int "Programmable Flags2 B (8)"
- default 11
-config IRQ_DMA1_WRRD0
- int "MDMA1 0 write/read INT"
- default 8
-config IRQ_DMA1_WRRD1
- int "MDMA1 1 write/read INT"
- default 8
-config IRQ_DMA2_WRRD0
- int "MDMA2 0 write/read INT"
- default 9
-config IRQ_DMA2_WRRD1
- int "MDMA2 1 write/read INT"
- default 9
-config IRQ_IMDMA_WRRD0
- int "IMDMA 0 write/read INT"
- default 12
-config IRQ_IMDMA_WRRD1
- int "IMDMA 1 write/read INT"
- default 12
-config IRQ_WDTIMER
- int "Watch Dog Timer"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile
deleted file mode 100644
index b340297..0000000
--- a/arch/blackfin/mach-bf561/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# arch/blackfin/mach-bf561/Makefile
-#
-
-obj-y := ints-priority.o dma.o
-
-obj-$(CONFIG_BF561_COREB) += coreb.o
-obj-$(CONFIG_SMP) += smp.o secondary.o atomic.o
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S
deleted file mode 100644
index 1e2989c..0000000
--- a/arch/blackfin/mach-bf561/atomic.S
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/cache.h>
-#include <asm/asm-offsets.h>
-#include <asm/rwlock.h>
-#include <asm/cplb.h>
-
-.text
-
-.macro coreslot_loadaddr reg:req
- \reg\().l = _corelock;
- \reg\().h = _corelock;
-.endm
-
-.macro safe_testset addr:req, scratch:req
-#if ANOMALY_05000477
- cli \scratch;
- testset (\addr);
- sti \scratch;
-#else
- testset (\addr);
-#endif
-.endm
-
-/*
- * r0 = address of atomic data to flush and invalidate (32bit).
- *
- * Clear interrupts and return the old mask.
- * We assume that no atomic data can span cachelines.
- *
- * Clobbers: r2:0, p0
- */
-ENTRY(_get_core_lock)
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- cli r0;
- coreslot_loadaddr p0;
-.Lretry_corelock:
- safe_testset p0, r2;
- if cc jump .Ldone_corelock;
- SSYNC(r2);
- jump .Lretry_corelock
-.Ldone_corelock:
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- rts;
-ENDPROC(_get_core_lock)
-
-/*
- * r0 = address of atomic data in uncacheable memory region (32bit).
- *
- * Clear interrupts and return the old mask.
- *
- * Clobbers: r0, p0
- */
-ENTRY(_get_core_lock_noflush)
- cli r0;
- coreslot_loadaddr p0;
-.Lretry_corelock_noflush:
- safe_testset p0, r2;
- if cc jump .Ldone_corelock_noflush;
- SSYNC(r2);
- jump .Lretry_corelock_noflush
-.Ldone_corelock_noflush:
- /*
- * SMP kgdb runs into dead loop without NOP here, when one core
- * single steps over get_core_lock_noflush and the other executes
- * get_core_lock as a slave node.
- */
- nop;
- CSYNC(r2);
- rts;
-ENDPROC(_get_core_lock_noflush)
-
-/*
- * r0 = interrupt mask to restore.
- * r1 = address of atomic data to flush and invalidate (32bit).
- *
- * Interrupts are masked on entry (see _get_core_lock).
- * Clobbers: r2:0, p0
- */
-ENTRY(_put_core_lock)
- /* Write-through cache assumed, so no flush needed here. */
- coreslot_loadaddr p0;
- r1 = 0;
- [p0] = r1;
- SSYNC(r2);
- sti r0;
- rts;
-ENDPROC(_put_core_lock)
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-
-ENTRY(___raw_smp_mark_barrier_asm)
- [--sp] = rets;
- [--sp] = ( r7:5 );
- [--sp] = r0;
- [--sp] = p1;
- [--sp] = p0;
- call _get_core_lock_noflush;
-
- /*
- * Calculate current core mask
- */
- GET_CPUID(p1, r7);
- r6 = 1;
- r6 <<= r7;
-
- /*
- * Set bit of other cores in barrier mask. Don't change current core bit.
- */
- p1.l = _barrier_mask;
- p1.h = _barrier_mask;
- r7 = [p1];
- r5 = r7 & r6;
- r7 = ~r6;
- cc = r5 == 0;
- if cc jump 1f;
- r7 = r7 | r6;
-1:
- [p1] = r7;
- SSYNC(r2);
-
- call _put_core_lock;
- p0 = [sp++];
- p1 = [sp++];
- r0 = [sp++];
- ( r7:5 ) = [sp++];
- rets = [sp++];
- rts;
-ENDPROC(___raw_smp_mark_barrier_asm)
-
-ENTRY(___raw_smp_check_barrier_asm)
- [--sp] = rets;
- [--sp] = ( r7:5 );
- [--sp] = r0;
- [--sp] = p1;
- [--sp] = p0;
- call _get_core_lock_noflush;
-
- /*
- * Calculate current core mask
- */
- GET_CPUID(p1, r7);
- r6 = 1;
- r6 <<= r7;
-
- /*
- * Clear current core bit in barrier mask if it is set.
- */
- p1.l = _barrier_mask;
- p1.h = _barrier_mask;
- r7 = [p1];
- r5 = r7 & r6;
- cc = r5 == 0;
- if cc jump 1f;
- r6 = ~r6;
- r7 = r7 & r6;
- [p1] = r7;
- SSYNC(r2);
-
- call _put_core_lock;
-
- /*
- * Invalidate the entire D-cache of current core.
- */
- sp += -12;
- call _resync_core_dcache
- sp += 12;
- jump 2f;
-1:
- call _put_core_lock;
-2:
- p0 = [sp++];
- p1 = [sp++];
- r0 = [sp++];
- ( r7:5 ) = [sp++];
- rets = [sp++];
- rts;
-ENDPROC(___raw_smp_check_barrier_asm)
-
-/*
- * r0 = irqflags
- * r1 = address of atomic data
- *
- * Clobbers: r2:0, p1:0
- */
-_start_lock_coherent:
-
- [--sp] = rets;
- [--sp] = ( r7:6 );
- r7 = r0;
- p1 = r1;
-
- /*
- * Determine whether the atomic data was previously
- * owned by another CPU (=r6).
- */
- GET_CPUID(p0, r2);
- r1 = 1;
- r1 <<= r2;
- r2 = ~r1;
-
- r1 = [p1];
- r1 >>= 28; /* CPU fingerprints are stored in the high nibble. */
- r6 = r1 & r2;
- r1 = [p1];
- r1 <<= 4;
- r1 >>= 4;
- [p1] = r1;
-
- /*
- * Release the core lock now, but keep IRQs disabled while we are
- * performing the remaining housekeeping chores for the current CPU.
- */
- coreslot_loadaddr p0;
- r1 = 0;
- [p0] = r1;
-
- /*
- * If another CPU has owned the same atomic section before us,
- * then our D-cached copy of the shared data protected by the
- * current spin/write_lock may be obsolete.
- */
- cc = r6 == 0;
- if cc jump .Lcache_synced
-
- /*
- * Invalidate the entire D-cache of the current core.
- */
- sp += -12;
- call _resync_core_dcache
- sp += 12;
-
-.Lcache_synced:
- SSYNC(r2);
- sti r7;
- ( r7:6 ) = [sp++];
- rets = [sp++];
- rts
-
-/*
- * r0 = irqflags
- * r1 = address of atomic data
- *
- * Clobbers: r2:0, p1:0
- */
-_end_lock_coherent:
-
- p1 = r1;
- GET_CPUID(p0, r2);
- r2 += 28;
- r1 = 1;
- r1 <<= r2;
- r2 = [p1];
- r2 = r1 | r2;
- [p1] = r2;
- r1 = p1;
- jump _put_core_lock;
-
-#endif /* __ARCH_SYNC_CORE_DCACHE */
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_is_locked_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- cc = bittst( r3, 0 );
- r3 = cc;
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = r3;
- rts;
-ENDPROC(___raw_spin_is_locked_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_lock_asm)
- p1 = r0;
- [--sp] = rets;
-.Lretry_spinlock:
- call _get_core_lock;
- r1 = p1;
- r2 = [p1];
- cc = bittst( r2, 0 );
- if cc jump .Lbusy_spinlock
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r3 = p1;
- bitset ( r2, 0 ); /* Raise the lock bit. */
- [p1] = r2;
- call _start_lock_coherent
-#else
- r2 = 1;
- [p1] = r2;
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lbusy_spinlock:
- /* We don't touch the atomic area if busy, so that flush
- will behave like nop in _put_core_lock. */
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- jump .Lretry_spinlock
-ENDPROC(___raw_spin_lock_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = p1;
- r3 = [p1];
- cc = bittst( r3, 0 );
- if cc jump .Lfailed_trylock
-#ifdef __ARCH_SYNC_CORE_DCACHE
- bitset ( r3, 0 ); /* Raise the lock bit. */
- [p1] = r3;
- call _start_lock_coherent
-#else
- r2 = 1;
- [p1] = r2;
- call _put_core_lock;
-#endif
- r0 = 1;
- rets = [sp++];
- rts;
-.Lfailed_trylock:
- call _put_core_lock;
- r0 = 0;
- rets = [sp++];
- rts;
-ENDPROC(___raw_spin_trylock_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_spin_unlock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r2 = [p1];
- bitclr ( r2, 0 );
- [p1] = r2;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _end_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-ENDPROC(___raw_spin_unlock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_read_lock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
-.Lrdlock_try:
- r1 = [p1];
- r1 += -1;
- [p1] = r1;
- cc = r1 < 0;
- if cc jump .Lrdlock_failed
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lrdlock_failed:
- r1 += 1;
- [p1] = r1;
-.Lrdlock_wait:
- r1 = p1;
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- call _get_core_lock;
- r1 = [p1];
- cc = r1 < 2;
- if cc jump .Lrdlock_wait;
- jump .Lrdlock_try
-ENDPROC(___raw_read_lock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_read_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- cc = r1 <= 0;
- if cc jump .Lfailed_tryrdlock;
- r1 += -1;
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- r0 = 1;
- rts;
-.Lfailed_tryrdlock:
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = 0;
- rts;
-ENDPROC(___raw_read_trylock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Note: Processing controlled by a reader lock should not have
- * any side-effect on cache issues with the other core, so we
- * just release the core lock and exit (no _end_lock_coherent).
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_read_unlock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r1 += 1;
- [p1] = r1;
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- rts;
-ENDPROC(___raw_read_unlock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_lock_asm)
- p1 = r0;
- r3.l = lo(RW_LOCK_BIAS);
- r3.h = hi(RW_LOCK_BIAS);
- [--sp] = rets;
- call _get_core_lock;
-.Lwrlock_try:
- r1 = [p1];
- r1 = r1 - r3;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r2 = r1;
- r2 <<= 4;
- r2 >>= 4;
- cc = r2 == 0;
-#else
- cc = r1 == 0;
-#endif
- if !cc jump .Lwrlock_wait
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lwrlock_wait:
- r1 = p1;
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- call _get_core_lock;
- r1 = [p1];
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r1 <<= 4;
- r1 >>= 4;
-#endif
- cc = r1 == r3;
- if !cc jump .Lwrlock_wait;
- jump .Lwrlock_try
-ENDPROC(___raw_write_lock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r2.l = lo(RW_LOCK_BIAS);
- r2.h = hi(RW_LOCK_BIAS);
- cc = r1 == r2;
- if !cc jump .Lfailed_trywrlock;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r1 >>= 28;
- r1 <<= 28;
-#else
- r1 = 0;
-#endif
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- r0 = 1;
- rts;
-
-.Lfailed_trywrlock:
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = 0;
- rts;
-ENDPROC(___raw_write_trylock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_unlock_asm)
- p1 = r0;
- r3.l = lo(RW_LOCK_BIAS);
- r3.h = hi(RW_LOCK_BIAS);
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r1 = r1 + r3;
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _end_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-ENDPROC(___raw_write_unlock_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * ADD a signed value to a 32bit word and return the new value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_add_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r2 = [p1];
- r3 = r3 + r2;
- [p1] = r3;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_add_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * ADD a signed value to a 32bit word and return the old value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_xadd_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r3 + r2;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_add_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * AND the mask bits from a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_and_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 & r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_and_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * OR the mask bits into a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_or_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 | r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_or_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * XOR the mask bits with a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_xor_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 ^ r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_xor_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * Perform a logical AND between the mask bits and a 32bit word, and
- * return the masked value. We need this on this architecture in
- * order to invalidate the local cache before testing.
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_test_asm)
- p1 = r0;
- r3 = r1;
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- r0 = [p1];
- r0 = r0 & r3;
- rts;
-ENDPROC(___raw_atomic_test_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * Swap *ptr with value and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-#define __do_xchg(src, dst) \
- p1 = r0; \
- r3 = r1; \
- [--sp] = rets; \
- call _get_core_lock; \
- r2 = src; \
- dst = r3; \
- r3 = r2; \
- r1 = p1; \
- call _put_core_lock; \
- r0 = r3; \
- rets = [sp++]; \
- rts;
-
-ENTRY(___raw_xchg_1_asm)
- __do_xchg(b[p1] (z), b[p1])
-ENDPROC(___raw_xchg_1_asm)
-
-ENTRY(___raw_xchg_2_asm)
- __do_xchg(w[p1] (z), w[p1])
-ENDPROC(___raw_xchg_2_asm)
-
-ENTRY(___raw_xchg_4_asm)
- __do_xchg([p1], [p1])
-ENDPROC(___raw_xchg_4_asm)
-
-/*
- * r0 = ptr
- * r1 = new
- * r2 = old
- *
- * Swap *ptr with new if *ptr == old and return the previous *ptr
- * value atomically.
- *
- * Clobbers: r3:0, p1:0
- */
-#define __do_cmpxchg(src, dst) \
- [--sp] = rets; \
- [--sp] = r4; \
- p1 = r0; \
- r3 = r1; \
- r4 = r2; \
- call _get_core_lock; \
- r2 = src; \
- cc = r2 == r4; \
- if !cc jump 1f; \
- dst = r3; \
- 1: r3 = r2; \
- r1 = p1; \
- call _put_core_lock; \
- r0 = r3; \
- r4 = [sp++]; \
- rets = [sp++]; \
- rts;
-
-ENTRY(___raw_cmpxchg_1_asm)
- __do_cmpxchg(b[p1] (z), b[p1])
-ENDPROC(___raw_cmpxchg_1_asm)
-
-ENTRY(___raw_cmpxchg_2_asm)
- __do_cmpxchg(w[p1] (z), w[p1])
-ENDPROC(___raw_cmpxchg_2_asm)
-
-ENTRY(___raw_cmpxchg_4_asm)
- __do_cmpxchg([p1], [p1])
-ENDPROC(___raw_cmpxchg_4_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Set a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_set_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_or_asm
-ENDPROC(___raw_bit_set_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Clear a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_clear_asm)
- r2 = 1;
- r2 <<= r1;
- r1 = ~r2;
- jump ___raw_atomic_and_asm
-ENDPROC(___raw_bit_clear_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Toggle a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_toggle_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_xor_asm
-ENDPROC(___raw_bit_toggle_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-set a bit in a 32bit word and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_set_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_set_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_set_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-clear a bit in a 32bit word and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_clear_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_clear_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_clear_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-toggle a bit in a 32bit word,
- * and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_toggle_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_toggle_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_toggle_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test a bit in a 32bit word and return its value.
- * We need this on this architecture in order to invalidate
- * the local cache before testing.
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_test_asm
-ENDPROC(___raw_bit_test_asm)
-
-/*
- * r0 = ptr
- *
- * Fetch and return an uncached 32bit value.
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_uncached_fetch_asm)
- p1 = r0;
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- r0 = [p1];
- rts;
-ENDPROC(___raw_uncached_fetch_asm)
diff --git a/arch/blackfin/mach-bf561/boards/Kconfig b/arch/blackfin/mach-bf561/boards/Kconfig
deleted file mode 100644
index 10e977b..0000000
--- a/arch/blackfin/mach-bf561/boards/Kconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN561_EZKIT
- help
- Select your board!
-
-config BFIN561_EZKIT
- bool "BF561-EZKIT"
- help
- BF561-EZKIT-LITE board support.
-
-config BFIN561_TEPLA
- bool "BF561-TEPLA"
- help
- BF561-TEPLA board support.
-
-config BFIN561_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF561"
- help
- CM-BF561 support for EVAL- and DEV-Board.
-
-config BFIN561_ACVILON
- bool "BF561-ACVILON"
- help
- BF561-ACVILON System On Module support (SO-DIMM 144).
- For more information about Acvilon BF561 SoM
- please go to http://www.niistt.ru/
-
-endchoice
diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile
deleted file mode 100644
index a5879f7..0000000
--- a/arch/blackfin/mach-bf561/boards/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# arch/blackfin/mach-bf561/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN561_ACVILON) += acvilon.o
-obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
-obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN561_TEPLA) += tepla.o
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
deleted file mode 100644
index 696cc9d..0000000
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * File: arch/blackfin/mach-bf561/acvilon.c
- * Based on: arch/blackfin/mach-bf561/ezkit.c
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- * Copyright 2004-2006 Analog Devices Inc.
- * Copyright 2009 CJSC "NII STT"
- *
- * Bugs:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- *
- * For more information about Acvilon BF561 SoM please
- * go to http://www.niistt.ru/
- *
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/jiffies.h>
-#include <linux/i2c-pca-platform.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/cacheflush.h>
-#include <linux/i2c.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Acvilon board";
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x20000000,
- .end = 0x20000000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF15,
- .end = IRQ_PF15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .port1_disable = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-static struct resource bfin_i2c_pca_resources[] = {
- {
- .name = "pca9564-regs",
- .start = 0x2C000000,
- .end = 0x2C000000 + 16,
- .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
- }, {
-
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
- .gpio = -1,
- .i2c_clock_speed = 330000,
- .timeout = HZ,
-};
-
-/* PCA9564 I2C Bus driver */
-static struct platform_device bfin_i2c_pca_device = {
- .name = "i2c-pca-platform",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
- .resource = bfin_i2c_pca_resources,
- .dev = {
- .platform_data = &pca9564_platform_data,
- }
-};
-
-/* I2C devices fitted. */
-static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
- {
- I2C_BOARD_INFO("ds1339", 0x68),
- },
- {
- I2C_BOARD_INFO("tcn75", 0x49),
- },
-};
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
-static struct platdata_mtd_ram mtd_ram_data = {
- .mapname = "rootfs(RAM)",
- .bankwidth = 4,
-};
-
-static struct resource mtd_ram_resource = {
- .start = 0x4000000,
- .end = 0x5ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mtd_ram_device = {
- .name = "mtd-ram",
- .id = 0,
- .dev = {
- .platform_data = &mtd_ram_data,
- },
- .num_resources = 1,
- .resource = &mtd_ram_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x28000000,
- .end = 0x28000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- /* Passed to driver */
- .platform_data = &bfin_uart0_peripherals,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
-
-static struct mtd_partition bfin_plat_nand_partitions[] = {
- {
- .name = "params(nand)",
- .size = 32 * 1024 * 1024,
- .offset = 0,
- }, {
- .name = "userfs(nand)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-#define BFIN_NAND_PLAT_CLE 2
-#define BFIN_NAND_PLAT_ALE 3
-
-static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
- else
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
-}
-
-#define BFIN_NAND_PLAT_READY GPIO_PF10
-static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(BFIN_NAND_PLAT_READY);
-}
-
-static struct platform_nand_data bfin_plat_nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_delay = 30,
- .partitions = bfin_plat_nand_partitions,
- .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
- },
- .ctrl = {
- .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
- .dev_ready = bfin_plat_nand_dev_ready,
- },
-};
-
-#define MAX(x, y) (x > y ? x : y)
-static struct resource bfin_plat_nand_resources = {
- .start = 0x24000000,
- .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device bfin_async_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_plat_nand_resources,
- .dev = {
- .platform_data = &bfin_plat_nand_data,
- },
-};
-
-static void bfin_plat_nand_init(void)
-{
- gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
-}
-#else
-static void bfin_plat_nand_init(void)
-{
-}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "bootloader",
- .size = 0x4200,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM},
- {
- .name = "u-boot",
- .size = 0x42000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "u-boot(params)",
- .size = 0x4200,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "kernel",
- .size = 0x294000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "params",
- .size = 0x42000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "rootfs",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "SPI Dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
-};
-
-/* DataFlash chip */
-static struct bfin5xx_spi_chip data_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- { /* DataFlash chip */
- .modalias = "mtd_dataflash",
- .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select */
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &data_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-static struct resource bfin_gpios_resources = {
- .start = 31,
-/* .end = MAX_BLACKFIN_GPIOS - 1, */
- .end = 32,
- .flags = IORESOURCE_IRQ,
-};
-
-static struct platform_device bfin_gpios_device = {
- .name = "simple-gpio",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_gpios_resources,
-};
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */ ,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *acvilon_devices[] __initdata = {
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
- &bfin_gpios_device,
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
- &bfin_i2c_pca_device,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
- &bfin_async_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
- &mtd_ram_device,
-#endif
-
-};
-
-static int __init acvilon_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- bfin_plat_nand_init();
- ret =
- platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
- if (ret < 0)
- return ret;
-
- i2c_register_board_info(0, acvilon_i2c_devs,
- ARRAY_SIZE(acvilon_i2c_devs));
-
- bfin_write_FIO0_FLAG_C(1 << 14);
- msleep(5);
- bfin_write_FIO0_FLAG_S(1 << 14);
-
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(acvilon_init);
-
-static struct platform_device *acvilon_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(acvilon_early_devices,
- ARRAY_SIZE(acvilon_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
deleted file mode 100644
index 10c5777..0000000
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ /dev/null
@@ -1,556 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/mtd/physmap.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF561";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x28000300,
- .end = 0x28000300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24008000,
- .end = 0x24008000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF43,
- .end = IRQ_PF43,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x24000000,
- .end = 0x24000000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF45,
- .end = IRQ_PF45,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x24008000,
- .end = 0x24008000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x24008004,
- .end = 0x24008004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF47,
- .end = IRQ_PF47,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF46
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2400C000,
- .end = 0x2400C001F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2400D018,
- .end = 0x2400D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = ¶_flash_data,
- },
- .num_resources = 1,
- .resource = ¶_flash_resource,
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf561_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- ¶_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF46, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PF46 */
- gpio_direction_output(GPIO_PF46, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF46, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf561_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf561_init);
-
-static struct platform_device *cm_bf561_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf561_early_devices,
- ARRAY_SIZE(cm_bf561_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
deleted file mode 100644
index acc5363..0000000
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ /dev/null
@@ -1,688 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF561-EZKIT";
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0F0000,
- .end = 0x203C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x2c060000,
- .end = 0x2c060000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x2c060004,
- .end = 0x2c060004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x2C000000,
- .end = 0x2C000000 + 0x7F,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x2C010300,
- .end = 0x2C010300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "config(nor)",
- .size = 0x2000 * 7,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "u-boot env(nor)",
- .size = 0x2000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF7, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF8, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 10,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_PPI,
- .dma_ch = CH_PPI0,
- .irq_err = IRQ_PPI1_ERROR,
- .base = (void __iomem *)PPI0_CONTROL,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7183)
-#include <media/i2c/adv7183.h>
-static struct v4l2_input adv7183_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
-};
-
-static struct bcap_route adv7183_routes[] = {
- {
- .input = ADV7183_COMPOSITE4,
- .output = ADV7183_8BIT_OUT,
- },
- {
- .input = ADV7183_SVIDEO0,
- .output = ADV7183_8BIT_OUT,
- },
- {
- .input = ADV7183_COMPONENT0,
- .output = ADV7183_8BIT_OUT,
- },
-};
-
-
-static const unsigned adv7183_gpio[] = {
- GPIO_PF13, /* reset pin */
- GPIO_PF2, /* output enable pin */
-};
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF561",
- .inputs = adv7183_inputs,
- .num_inputs = ARRAY_SIZE(adv7183_inputs),
- .routes = adv7183_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7183",
- .addr = 0x20,
- .platform_data = (void *)adv7183_gpio,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | DMA32 | FLD_SEL),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF11, "net2272");
- if (ret)
- return ret;
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF11, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF11, 1);
-#endif
-
- return 0;
-}
-
-static int __init ezkit_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- ret = platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 12));
- SSYNC();
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15));
- bfin_write_FIO0_FLAG_S(1 << 15);
- SSYNC();
- /*
- * This initialization lasts for approximately 4500 MCLKs.
- * MCLK = 12.288MHz
- */
- udelay(400);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
deleted file mode 100644
index f87b8cc..0000000
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright 2004-2007 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Thanks to Jamey Hicks.
- *
- * Only SMSC91C1111 was registered, may do more later.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-
-const char bfin_board_name[] = "Tepla-BF561";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-static struct resource smc91x_resources[] = {
- {
- .start = 0x2C000300,
- .end = 0x2C000320,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PROG_INTB,
- .end = IRQ_PROG_INTB,
- .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-static struct platform_device *tepla_devices[] __initdata = {
- &smc91x_device,
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-};
-
-static int __init tepla_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- return platform_add_devices(tepla_devices, ARRAY_SIZE(tepla_devices));
-}
-
-arch_initcall(tepla_init);
-
-static struct platform_device *tepla_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tepla_early_devices,
- ARRAY_SIZE(tepla_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
deleted file mode 100644
index cf27554..0000000
--- a/arch/blackfin/mach-bf561/coreb.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Load firmware into Core B on a BF561
- *
- * Author: Bas Vermeulen <bvermeul@blackstar.xs4all.nl>
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* The Core B reset func requires code in the application that is loaded into
- * Core B. In order to reset, the application needs to install an interrupt
- * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and
- * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core
- * B to stall when Supplemental Interrupt 0 is set, and will reset PC to
- * 0xff600000 when COREB_SRAM_INIT is cleared.
- */
-
-#include <linux/device.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/miscdevice.h>
-
-#define CMD_COREB_START _IO('b', 0)
-#define CMD_COREB_STOP _IO('b', 1)
-#define CMD_COREB_RESET _IO('b', 2)
-
-static long
-coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- int ret = 0;
-
- switch (cmd) {
- case CMD_COREB_START:
- bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
- break;
- case CMD_COREB_STOP:
- bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
- break;
- case CMD_COREB_RESET:
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- CSYNC();
-
- return ret;
-}
-
-static const struct file_operations coreb_fops = {
- .owner = THIS_MODULE,
- .unlocked_ioctl = coreb_ioctl,
- .llseek = noop_llseek,
-};
-
-static struct miscdevice coreb_dev = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "coreb",
- .fops = &coreb_fops,
-};
-builtin_misc_device(coreb_dev);
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
deleted file mode 100644
index 8ffdd6b..0000000
--- a/arch/blackfin/mach-bf561/dma.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI0:
- ret_irq = IRQ_PPI0;
- break;
- case CH_PPI1:
- ret_irq = IRQ_PPI1;
- break;
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
- case CH_UART_RX:
- ret_irq = IRQ_UART_RX;
- break;
- case CH_UART_TX:
- ret_irq = IRQ_UART_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MEM_DMA2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MEM_DMA3;
- break;
-
- case CH_IMEM_STREAM0_SRC:
- case CH_IMEM_STREAM0_DEST:
- ret_irq = IRQ_IMEM_DMA0;
- break;
- case CH_IMEM_STREAM1_SRC:
- case CH_IMEM_STREAM1_DEST:
- ret_irq = IRQ_IMEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c
deleted file mode 100644
index 0123117..0000000
--- a/arch/blackfin/mach-bf561/hotplug.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Graff Yang <graf.yang@analog.com>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/smp.h>
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <mach/pll.h>
-
-int hotplug_coreb;
-
-void platform_cpu_die(void)
-{
- unsigned long iwr;
-
- hotplug_coreb = 1;
-
- /*
- * When CoreB wakes up, the code in _coreb_trampoline_start cannot
- * turn off the data cache. This causes the CoreB failed to boot.
- * As a workaround, we invalidate all the data cache before sleep.
- */
- blackfin_invalidate_entire_dcache();
-
- /* disable core timer */
- bfin_write_TCNTL(0);
-
- /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1)));
- SSYNC();
-
- /* set CoreB wakeup by ipi0, iwr will be discarded */
- bfin_iwr_set_sup0(&iwr, &iwr, &iwr);
- SSYNC();
-
- coreb_die();
-}
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
deleted file mode 100644
index 038249c..0000000
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
-#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
-#define ANOMALY_05000120 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* SIGNBITS Instruction Not Functional under Certain Conditions */
-#define ANOMALY_05000127 (1)
-/* IMDMA S1/D1 Channel May Stall */
-#define ANOMALY_05000149 (1)
-/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
-#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
-/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
-#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
-/* Internal Memory DMA Does Not Operate@Full Speed */
-#define ANOMALY_05000182 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
-/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
-#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
-/* IMDMA Corrupted Data after a Halt */
-#define ANOMALY_05000187 (1)
-/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
-#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
-/* PPI Not Functional at Core Voltage < 1Volt */
-#define ANOMALY_05000190 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
-/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event@Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
-#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
-/* TESTSET Operation Forces Stall on the Other Core */
-#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
-/* Exception Not Generated for MMR Accesses in Reserved Region */
-#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
- * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
- * after the behavior and the root cause are confirmed with hardware team.
- */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
-#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
-/* IMDMA May Corrupt Data under Certain Conditions */
-#define ANOMALY_05000267 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Data Cache Write Back to External Synchronous Memory May Be Lost */
-#define ANOMALY_05000274 (1)
-/* PPI Timing and Sampling Information Updates */
-#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error when ISR Context Is Not Restored */
-/* Temporarily walk around for bug 5423 till this issue is confirmed by
- * official anomaly document. It looks 05000281 still exists on bf561
- * v0.5.
- */
-#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
-/* Reads Will Receive Incorrect Data under Certain Conditions */
-#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (1)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
-/* False Hardware Errors Caused by Fetches@the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (1)
-/* PF2 Output Remains Asserted after SPI Master Boot */
-#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
-/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
-#define ANOMALY_05000323 (1)
-/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
-#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
-/* 24-Bit SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
-/* Slave SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
-/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
-#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
-/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
-#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* Conflicting Column Address Widths Causes SDRAM Errors */
-#define ANOMALY_05000362 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
-#define ANOMALY_05000412 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
-#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* SCKELOW Feature Is Not Functional */
-#define ANOMALY_05000458 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up@CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000119 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h
deleted file mode 100644
index 9f9a367..0000000
--- a/arch/blackfin/mach-bf561/include/mach/bf561.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF561_H__
-#define __MACH_BF561_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************
- * Blackfin Cache setup
- */
-
-
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS */
-#define PLL_WAKEUP_BIT 0xFFFFFFFF
-#define DMA1_ERROR_BIT 0xFFFFFF0F
-#define DMA2_ERROR_BIT 0xFFFFF0FF
-#define IMDMA_ERROR_BIT 0xFFFF0FFF
-#define PPI1_ERROR_BIT 0xFFF0FFFF
-#define PPI2_ERROR_BIT 0xFF0FFFFF
-#define SPORT0_ERROR_BIT 0xF0FFFFFF
-#define SPORT1_ERROR_BIT 0x0FFFFFFF
-/* IAR1 BIT FIELDS */
-#define SPI_ERROR_BIT 0xFFFFFFFF
-#define UART_ERROR_BIT 0xFFFFFF0F
-#define RESERVED_ERROR_BIT 0xFFFFF0FF
-#define DMA1_0_BIT 0xFFFF0FFF
-#define DMA1_1_BIT 0xFFF0FFFF
-#define DMA1_2_BIT 0xFF0FFFFF
-#define DMA1_3_BIT 0xF0FFFFFF
-#define DMA1_4_BIT 0x0FFFFFFF
-/* IAR2 BIT FIELDS */
-#define DMA1_5_BIT 0xFFFFFFFF
-#define DMA1_6_BIT 0xFFFFFF0F
-#define DMA1_7_BIT 0xFFFFF0FF
-#define DMA1_8_BIT 0xFFFF0FFF
-#define DMA1_9_BIT 0xFFF0FFFF
-#define DMA1_10_BIT 0xFF0FFFFF
-#define DMA1_11_BIT 0xF0FFFFFF
-#define DMA2_0_BIT 0x0FFFFFFF
-/* IAR3 BIT FIELDS */
-#define DMA2_1_BIT 0xFFFFFFFF
-#define DMA2_2_BIT 0xFFFFFF0F
-#define DMA2_3_BIT 0xFFFFF0FF
-#define DMA2_4_BIT 0xFFFF0FFF
-#define DMA2_5_BIT 0xFFF0FFFF
-#define DMA2_6_BIT 0xFF0FFFFF
-#define DMA2_7_BIT 0xF0FFFFFF
-#define DMA2_8_BIT 0x0FFFFFFF
-/* IAR4 BIT FIELDS */
-#define DMA2_9_BIT 0xFFFFFFFF
-#define DMA2_10_BIT 0xFFFFFF0F
-#define DMA2_11_BIT 0xFFFFF0FF
-#define TIMER0_BIT 0xFFFF0FFF
-#define TIMER1_BIT 0xFFF0FFFF
-#define TIMER2_BIT 0xFF0FFFFF
-#define TIMER3_BIT 0xF0FFFFFF
-#define TIMER4_BIT 0x0FFFFFFF
-/* IAR5 BIT FIELDS */
-#define TIMER5_BIT 0xFFFFFFFF
-#define TIMER6_BIT 0xFFFFFF0F
-#define TIMER7_BIT 0xFFFFF0FF
-#define TIMER8_BIT 0xFFFF0FFF
-#define TIMER9_BIT 0xFFF0FFFF
-#define TIMER10_BIT 0xFF0FFFFF
-#define TIMER11_BIT 0xF0FFFFFF
-#define PROG0_INTA_BIT 0x0FFFFFFF
-/* IAR6 BIT FIELDS */
-#define PROG0_INTB_BIT 0xFFFFFFFF
-#define PROG1_INTA_BIT 0xFFFFFF0F
-#define PROG1_INTB_BIT 0xFFFFF0FF
-#define PROG2_INTA_BIT 0xFFFF0FFF
-#define PROG2_INTB_BIT 0xFFF0FFFF
-#define DMA1_WRRD0_BIT 0xFF0FFFFF
-#define DMA1_WRRD1_BIT 0xF0FFFFFF
-#define DMA2_WRRD0_BIT 0x0FFFFFFF
-/* IAR7 BIT FIELDS */
-#define DMA2_WRRD1_BIT 0xFFFFFFFF
-#define IMDMA_WRRD0_BIT 0xFFFFFF0F
-#define IMDMA_WRRD1_BIT 0xFFFFF0FF
-#define WATCH_BIT 0xFFFF0FFF
-#define RESERVED_1_BIT 0xFFF0FFFF
-#define RESERVED_2_BIT 0xFF0FFFFF
-#define SUPPLE_0_BIT 0xF0FFFFFF
-#define SUPPLE_1_BIT 0x0FFFFFFF
-
-/* Miscellaneous Values */
-
-/****************************** EBIU Settings ********************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#if defined(CONFIG_C_AMBEN_ALL)
-#define V_AMBEN AMBEN_ALL
-#elif defined(CONFIG_C_AMBEN)
-#define V_AMBEN 0x0
-#elif defined(CONFIG_C_AMBEN_B0)
-#define V_AMBEN AMBEN_B0
-#elif defined(CONFIG_C_AMBEN_B0_B1)
-#define V_AMBEN AMBEN_B0_B1
-#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#ifdef CONFIG_C_B0PEN
-#define V_B0PEN 0x10
-#else
-#define V_B0PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B1PEN
-#define V_B1PEN 0x20
-#else
-#define V_B1PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B2PEN
-#define V_B2PEN 0x40
-#else
-#define V_B2PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B3PEN
-#define V_B3PEN 0x80
-#else
-#define V_B3PEN 0x00
-#endif
-
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
-
-#ifdef CONFIG_BF561
-#define CPU "BF561"
-#define CPUID 0x27bb
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF561_H__ */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
deleted file mode 100644
index 08072c8..0000000
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 1
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
deleted file mode 100644
index dc47053..0000000
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF561_FAMILY
-
-#include "bf561.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#include "defBF561.h"
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# include "cdefBF561.h"
-#endif
-
-#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
-#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
-#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
-
-/* Weird muxer funcs which pick SIC regs from IMASK base */
-#define __SIC_MUX(base, x) ((base) + ((x) << 2))
-#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
-#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
-#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
-#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
-#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
-#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
-#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
-
-#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
deleted file mode 100644
index 7533315..0000000
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ /dev/null
@@ -1,1460 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF561_H
-#define _CDEF_BF561_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
-#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
-#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
-#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
-#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
-#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
-#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
-#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
-#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
-#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
-#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
-#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)
-#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
-#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)
-#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
-#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)
-#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
-#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)
-#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
-#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)
-#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
-#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)
-#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
-#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)
-#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
-#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)
-#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
-#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)
-#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
-#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
-#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
-#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
-#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
-#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
-#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)
-#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
-#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
-#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)
-#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
-#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)
-#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
-#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
-#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
-#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val)
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE)
-#define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val)
-#define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE)
-#define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val)
-#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
-#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val)
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val)
-#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
-#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val)
-#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
-#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val)
-#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
-#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val)
-#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
-#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val)
-#define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE)
-#define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val)
-#define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE)
-#define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val)
-#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
-#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val)
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
-#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val)
-#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
-#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val)
-#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
-#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val)
-#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
-#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val)
-#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
-#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val)
-#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
-#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val)
-#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
-#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val)
-#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
-#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val)
-#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
-#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val)
-#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
-#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val)
-#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
-#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val)
-#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
-#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val)
-#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
-#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val)
-#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
-#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val)
-#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
-#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val)
-#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
-#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val)
-#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
-#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val)
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
-#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val)
-#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
-#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val)
-#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
-#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val)
-#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
-#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val)
-#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
-#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val)
-#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
-#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val)
-#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
-#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val)
-#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
-#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val)
-#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
-#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val)
-#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
-#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val)
-#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
-#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val)
-#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
-#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val)
-#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
-#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val)
-#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
-#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val)
-#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
-#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val)
-#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
-#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val)
-#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
-#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val)
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
-#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val)
-#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
-#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val)
-#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
-#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val)
-#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
-#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val)
-#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
-#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val)
-#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
-#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val)
-#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
-#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val)
-#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
-#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val)
-#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
-#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val)
-#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
-#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val)
-#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
-#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val)
-#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
-#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val)
-#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
-#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val)
-#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
-#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val)
-#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
-#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val)
-#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
-#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val)
-#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
-#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val)
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
-#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
-#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
-#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
-#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS()
-#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
-#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
-#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
-#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val)
-#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
-#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val)
-/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
-#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
-#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
-#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
-#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS()
-#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
-#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
-#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
-#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val)
-#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
-#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
-/*DMA traffic control registers */
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val)
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val)
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
-#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
-#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR)
-#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR)
-#define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val)
-#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
-#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val)
-#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
-#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val)
-#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
-#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val)
-#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
-#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val)
-#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR)
-#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR)
-#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val)
-#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
-#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val)
-#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
-#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
-#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val)
-#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
-#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
-#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val)
-#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR)
-#define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val)
-#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
-#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val)
-#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
-#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val)
-#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
-#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val)
-#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
-#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val)
-#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR)
-#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR)
-#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val)
-#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
-#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
-#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
-#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val)
-#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
-#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val)
-#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR)
-#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR)
-#define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val)
-#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
-#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val)
-#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
-#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val)
-#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
-#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val)
-#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
-#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val)
-#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR)
-#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR)
-#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val)
-#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
-#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val)
-#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
-#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
-#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val)
-#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
-#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
-#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val)
-#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR)
-#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR)
-#define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val)
-#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
-#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val)
-#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
-#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val)
-#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
-#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val)
-#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
-#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val)
-#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR)
-#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR)
-#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val)
-#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
-#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val)
-#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
-#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
-#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val)
-#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
-#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
-#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val)
-#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR)
-#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR)
-#define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val)
-#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
-#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val)
-#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
-#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val)
-#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
-#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val)
-#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
-#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val)
-#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR)
-#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR)
-#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val)
-#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
-#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val)
-#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
-#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
-#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val)
-#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
-#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
-#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val)
-#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR)
-#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR)
-#define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val)
-#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
-#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val)
-#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
-#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val)
-#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
-#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val)
-#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
-#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val)
-#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR)
-#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR)
-#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val)
-#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
-#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val)
-#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
-#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
-#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val)
-#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
-#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
-#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val)
-#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR)
-#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR)
-#define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val)
-#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
-#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val)
-#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
-#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val)
-#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
-#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val)
-#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
-#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val)
-#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR)
-#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR)
-#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val)
-#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
-#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val)
-#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
-#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
-#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val)
-#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
-#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
-#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val)
-#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR)
-#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR)
-#define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val)
-#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
-#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val)
-#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
-#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val)
-#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
-#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val)
-#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
-#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val)
-#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR)
-#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR)
-#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val)
-#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
-#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val)
-#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
-#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
-#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val)
-#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
-#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
-#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val)
-#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR)
-#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR)
-#define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val)
-#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
-#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val)
-#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
-#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val)
-#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
-#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val)
-#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
-#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val)
-#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR)
-#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR)
-#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val)
-#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
-#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val)
-#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
-#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
-#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val)
-#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
-#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
-#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val)
-#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR)
-#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR)
-#define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val)
-#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
-#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val)
-#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
-#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val)
-#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
-#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val)
-#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
-#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val)
-#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR)
-#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR)
-#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val)
-#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
-#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val)
-#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
-#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
-#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val)
-#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
-#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
-#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val)
-#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR)
-#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR)
-#define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val)
-#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
-#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val)
-#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
-#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val)
-#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
-#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val)
-#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
-#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val)
-#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR)
-#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR)
-#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val)
-#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
-#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
-#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
-#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
-#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val)
-#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
-#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
-#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val)
-#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR)
-#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR)
-#define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val)
-#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
-#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val)
-#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
-#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val)
-#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
-#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val)
-#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
-#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val)
-#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR)
-#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR)
-#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val)
-#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
-#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
-#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
-#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
-#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val)
-#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
-#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG,val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR,val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT,val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT,val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY,val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY,val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR,val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG,val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR,val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT,val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT,val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY,val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY,val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR,val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS,val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG,val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR,val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT,val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT,val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY,val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY,val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR,val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS,val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG,val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR,val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT,val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT,val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY,val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY,val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR,val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS,val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val)
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
-#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
-#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR)
-#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR)
-#define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val)
-#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
-#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val)
-#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
-#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val)
-#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
-#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val)
-#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
-#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val)
-#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR)
-#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR)
-#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val)
-#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
-#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val)
-#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
-#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
-#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val)
-#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
-#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
-#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val)
-#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR)
-#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR)
-#define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val)
-#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
-#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val)
-#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
-#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val)
-#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
-#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val)
-#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
-#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val)
-#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR)
-#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR)
-#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val)
-#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
-#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val)
-#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
-#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
-#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val)
-#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
-#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
-#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val)
-#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR)
-#define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val)
-#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
-#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val)
-#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
-#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val)
-#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
-#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val)
-#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
-#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val)
-#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR)
-#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR)
-#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val)
-#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
-#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
-#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
-#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val)
-#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
-#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val)
-#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR)
-#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR)
-#define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val)
-#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
-#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val)
-#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
-#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val)
-#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
-#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val)
-#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
-#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val)
-#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR)
-#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR)
-#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val)
-#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
-#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val)
-#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
-#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
-#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val)
-#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
-#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
-#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val)
-#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR)
-#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR)
-#define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val)
-#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
-#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val)
-#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
-#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val)
-#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
-#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val)
-#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
-#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val)
-#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR)
-#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR)
-#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val)
-#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
-#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val)
-#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
-#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
-#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val)
-#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
-#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
-#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val)
-#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR)
-#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR)
-#define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val)
-#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
-#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val)
-#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
-#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val)
-#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
-#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val)
-#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
-#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val)
-#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR)
-#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR)
-#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val)
-#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
-#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val)
-#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
-#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
-#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val)
-#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
-#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
-#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val)
-#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR)
-#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR)
-#define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val)
-#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
-#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val)
-#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
-#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val)
-#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
-#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val)
-#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
-#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val)
-#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR)
-#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR)
-#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val)
-#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
-#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val)
-#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
-#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
-#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val)
-#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
-#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
-#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val)
-#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR)
-#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR)
-#define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val)
-#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
-#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val)
-#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
-#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val)
-#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
-#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val)
-#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
-#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val)
-#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR)
-#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR)
-#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val)
-#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
-#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val)
-#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
-#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
-#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val)
-#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
-#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
-#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val)
-#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR)
-#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR)
-#define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val)
-#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
-#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val)
-#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
-#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val)
-#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
-#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val)
-#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
-#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val)
-#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR)
-#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR)
-#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val)
-#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
-#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val)
-#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
-#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
-#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val)
-#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
-#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
-#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val)
-#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR)
-#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR)
-#define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val)
-#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
-#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val)
-#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
-#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val)
-#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
-#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val)
-#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
-#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val)
-#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR)
-#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR)
-#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val)
-#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
-#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val)
-#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
-#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
-#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val)
-#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
-#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
-#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val)
-#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR)
-#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR)
-#define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val)
-#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
-#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val)
-#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
-#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val)
-#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
-#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val)
-#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
-#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val)
-#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR)
-#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR)
-#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val)
-#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
-#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
-#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
-#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
-#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val)
-#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
-#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
-#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val)
-#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR)
-#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR)
-#define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val)
-#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
-#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val)
-#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
-#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val)
-#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
-#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val)
-#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
-#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val)
-#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR)
-#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR)
-#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val)
-#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
-#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
-#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
-#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
-#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val)
-#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
-#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
-#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
-#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR)
-#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val)
-#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
-#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val)
-#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
-#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
-#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val)
-#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
-#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val)
-#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR)
-#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val)
-#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
-#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
-#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
-#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val)
-#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR)
-#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val)
-#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
-#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val)
-#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
-#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
-#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val)
-#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
-#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val)
-#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR)
-#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val)
-#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
-#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
-#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
-#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val)
-#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR)
-#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val)
-#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
-#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val)
-#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
-#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
-#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val)
-#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
-#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val)
-#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR)
-#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val)
-#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
-#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
-#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
-#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val)
-#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR)
-#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val)
-#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
-#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val)
-#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
-#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
-#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val)
-#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
-#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val)
-#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR)
-#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val)
-#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
-#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
-#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
-
-#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
deleted file mode 100644
index 9f21f76..0000000
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ /dev/null
@@ -1,1402 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF561_H
-#define _DEF_BF561_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
-#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
-#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
-#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
-#define RESET_SOFTWARE (SWRST_OCCURRED)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define SWRST 0xFFC00100 /* Software Reset register */
-#define SYSCR 0xFFC00104 /* System Reset Configuration register */
-#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
-#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
-#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
-#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
-#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
-#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
-#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
-#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define SICB_SWRST 0xFFC01100 /* reserved */
-#define SICB_SYSCR 0xFFC01104 /* reserved */
-#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */
-#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
-#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
-#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
-#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
-#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
-#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
-#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
-#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
-#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
-#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
-#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
-#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
-#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
-#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */
-#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */
-#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */
-#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */
-#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART0_*.
- */
-#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
-#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
-#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
-#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
-#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
-#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */
-
-#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */
-#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */
-#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */
-#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */
-#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */
-
-#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */
-#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */
-#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */
-#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */
-
-#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */
-#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */
-#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */
-#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */
-
-#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */
-#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */
-#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */
-#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */
-
-#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */
-#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */
-#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */
-#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */
-#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */
-#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */
-#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */
-#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */
-#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */
-#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */
-#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */
-#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */
-#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */
-#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */
-#define FIO0_DIR 0xFFC00730 /* Flag Direction register */
-#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */
-#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */
-#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */
-#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */
-
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */
-#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */
-#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */
-#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */
-#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */
-#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */
-#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */
-#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */
-#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */
-#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */
-#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */
-#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */
-#define FIO1_DIR 0xFFC01530 /* Flag Direction register */
-#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */
-#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */
-#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */
-#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */
-
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */
-#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */
-#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */
-#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */
-#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */
-#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */
-#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */
-#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */
-#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */
-#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */
-#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */
-#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */
-#define FIO2_DIR 0xFFC01730 /* Flag Direction register */
-#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */
-#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */
-#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */
-#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */
-#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */
-#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */
-#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */
-#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */
-
-/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */
-#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */
-#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */
-#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */
-#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
-
-/*DMA traffic control registers */
-#define DMAC0_TC_PER 0xFFC00B0C /* Traffic control periods */
-#define DMAC0_TC_CNT 0xFFC00B10 /* Traffic control current counts */
-#define DMAC1_TC_PER 0xFFC01B0C /* Traffic control periods */
-#define DMAC1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
-
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
-#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
-#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
-#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */
-#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */
-#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */
-#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */
-#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
-#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */
-#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */
-#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */
-#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
-#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
-
-#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */
-#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
-#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
-#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */
-#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */
-#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */
-#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */
-#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
-#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */
-#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */
-#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */
-#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
-#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
-
-#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */
-#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
-#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
-#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */
-#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */
-#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */
-#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */
-#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
-#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */
-#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */
-#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */
-#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
-#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
-
-#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */
-#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
-#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
-#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */
-#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */
-#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */
-#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */
-#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
-#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */
-#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */
-#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */
-#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
-#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
-
-#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */
-#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
-#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
-#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */
-#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */
-#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */
-#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */
-#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
-#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */
-#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */
-#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */
-#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
-#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
-
-#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */
-#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
-#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
-#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */
-#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */
-#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */
-#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */
-#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
-#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */
-#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */
-#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */
-#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
-#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
-
-#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */
-#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
-#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
-#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */
-#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */
-#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */
-#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */
-#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
-#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */
-#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */
-#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */
-#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
-#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
-
-#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */
-#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
-#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
-#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */
-#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */
-#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */
-#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */
-#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
-#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */
-#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */
-#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */
-#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
-#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
-
-#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */
-#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
-#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
-#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */
-#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */
-#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */
-#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */
-#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
-#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */
-#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */
-#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */
-#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
-#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
-
-#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */
-#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
-#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
-#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */
-#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */
-#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */
-#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */
-#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
-#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */
-#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */
-#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */
-#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
-#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
-
-#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */
-#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */
-#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
-#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */
-#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */
-#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */
-#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */
-#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */
-#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */
-#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
-#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
-#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
-#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
-
-#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */
-#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */
-#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
-#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */
-#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */
-#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */
-#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */
-#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */
-#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */
-#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
-#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
-#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
-#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
-
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define MDMA_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
-#define MDMA_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
-#define MDMA_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
-#define MDMA_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
-#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
-#define MDMA_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
-
-#define MDMA_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
-#define MDMA_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
-#define MDMA_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
-#define MDMA_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
-#define MDMA_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
-#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
-#define MDMA_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
-
-#define MDMA_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
-#define MDMA_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
-#define MDMA_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
-#define MDMA_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
-#define MDMA_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
-#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
-#define MDMA_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
-
-#define MDMA_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
-#define MDMA_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
-#define MDMA_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
-#define MDMA_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
-#define MDMA_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
-#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
-#define MDMA_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
-
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
-#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
-#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
-#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */
-#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */
-#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */
-#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */
-#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
-#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */
-#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */
-#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */
-#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
-#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
-
-#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */
-#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
-#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
-#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */
-#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */
-#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */
-#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */
-#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
-#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */
-#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */
-#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */
-#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
-#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
-
-#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */
-#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
-#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
-#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */
-#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */
-#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */
-#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */
-#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
-#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */
-#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */
-#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */
-#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
-#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
-
-#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */
-#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
-#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
-#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */
-#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */
-#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */
-#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */
-#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
-#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */
-#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */
-#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */
-#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
-#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
-
-#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */
-#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
-#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
-#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */
-#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */
-#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */
-#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */
-#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
-#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */
-#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */
-#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */
-#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
-#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
-
-#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */
-#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
-#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
-#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */
-#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */
-#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */
-#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */
-#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
-#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */
-#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */
-#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */
-#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
-#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
-
-#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */
-#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
-#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
-#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */
-#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */
-#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */
-#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */
-#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
-#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */
-#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */
-#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */
-#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
-#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
-
-#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */
-#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
-#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
-#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */
-#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */
-#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */
-#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */
-#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
-#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */
-#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */
-#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */
-#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
-#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
-
-#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */
-#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
-#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
-#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */
-#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */
-#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */
-#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */
-#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
-#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */
-#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */
-#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */
-#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
-#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
-
-#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */
-#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
-#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
-#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */
-#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */
-#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */
-#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */
-#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
-#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */
-#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */
-#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */
-#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
-#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
-
-#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */
-#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */
-#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
-#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */
-#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */
-#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */
-#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */
-#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */
-#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */
-#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
-#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
-#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
-#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
-
-#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */
-#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */
-#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
-#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */
-#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */
-#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */
-#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */
-#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */
-#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */
-#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
-#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
-#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
-#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
-
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define MDMA_D2_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA_D2_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
-#define MDMA_D2_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
-#define MDMA_D2_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
-#define MDMA_D2_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA_D2_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA_D2_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
-#define MDMA_D2_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
-#define MDMA_D2_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
-
-#define MDMA_S2_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA_S2_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
-#define MDMA_S2_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
-#define MDMA_S2_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
-#define MDMA_S2_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
-#define MDMA_S2_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA_S2_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
-#define MDMA_S2_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
-#define MDMA_S2_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
-
-#define MDMA_D3_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA_D3_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
-#define MDMA_D3_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
-#define MDMA_D3_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
-#define MDMA_D3_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA_D3_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
-#define MDMA_D3_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
-#define MDMA_D3_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
-#define MDMA_D3_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
-
-#define MDMA_S3_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA_S3_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
-#define MDMA_S3_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
-#define MDMA_S3_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
-#define MDMA_S3_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
-#define MDMA_S3_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA_S3_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
-#define MDMA_S3_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
-#define MDMA_S3_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
-
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
-#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
-#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
-#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
-#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
-#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
-#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */
-#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */
-#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
-#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
-#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
-
-#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */
-#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
-#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
-#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
-#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
-#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
-#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
-#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
-#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */
-#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
-#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
-#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
-
-#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
-#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
-#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
-#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
-#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
-#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
-#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
-#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
-#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
-#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
-#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
-
-#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
-#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
-#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
-#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
-#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
-#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
-#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
-#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
-#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
-#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
-#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
-#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SICA_SYSCR Masks */
-#define COREB_SRAM_INIT 0x0020
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
-#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
-#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */
-#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
-#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
-#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
-#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
-#define SWRST_OCCURRED 0x8000 /* SWRST Status */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* SICu_IARv Masks */
-/* u = A or B */
-/* v = 0 to 7 */
-/* w = 0 or 1 */
-
-/* Per_number = 0 to 63 */
-/* IVG_number = 7 to 15 */
-#define Peripheral_IVG(Per_number, IVG_number) \
- ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */
- /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
- /* r0.h = hi(Peripheral_IVG(62, 10)); */
-
-/* SICx_IMASKw Masks */
-/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x00000001 /* PPI Port Enable */
-#define PORT_DIR 0x00000002 /* PPI Port Direction */
-#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
-#define PORT_CFG 0x00000030 /* PPI Port Configuration */
-#define FLD_SEL 0x00000040 /* PPI Active Field Select */
-#define PACK_EN 0x00000080 /* PPI Packing Mode */
-#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x00003800 /* PPI Data Length */
-#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
-#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#define DLEN_10 0x00000800 /* Data Length = 10 Bits */
-#define DLEN_11 0x00001000 /* Data Length = 11 Bits */
-#define DLEN_12 0x00001800 /* Data Length = 12 Bits */
-#define DLEN_13 0x00002000 /* Data Length = 13 Bits */
-#define DLEN_14 0x00002800 /* Data Length = 14 Bits */
-#define DLEN_15 0x00003000 /* Data Length = 15 Bits */
-#define DLEN_16 0x00003800 /* Data Length = 16 Bits */
-#define POL 0x0000C000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x00000400 /* Field Indicator */
-#define FT_ERR 0x00000800 /* Frame Track Error */
-#define OVR 0x00001000 /* FIFO Overflow Error */
-#define UNDR 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET 0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
-
-/* ********** DMA CONTROLLER MASKS *********************8 */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
-#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
-#define PMAP 0x00007000 /* DMA Peripheral Map Field */
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001
-#define TIMEN1 0x0002
-#define TIMEN2 0x0004
-#define TIMEN3 0x0008
-#define TIMEN4 0x0010
-#define TIMEN5 0x0020
-#define TIMEN6 0x0040
-#define TIMEN7 0x0080
-#define TIMEN8 0x0001
-#define TIMEN9 0x0002
-#define TIMEN10 0x0004
-#define TIMEN11 0x0008
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-#define TIMEN3_P 0x03
-#define TIMEN4_P 0x04
-#define TIMEN5_P 0x05
-#define TIMEN6_P 0x06
-#define TIMEN7_P 0x07
-#define TIMEN8_P 0x00
-#define TIMEN9_P 0x01
-#define TIMEN10_P 0x02
-#define TIMEN11_P 0x03
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001
-#define TIMDIS1 0x0002
-#define TIMDIS2 0x0004
-#define TIMDIS3 0x0008
-#define TIMDIS4 0x0010
-#define TIMDIS5 0x0020
-#define TIMDIS6 0x0040
-#define TIMDIS7 0x0080
-#define TIMDIS8 0x0001
-#define TIMDIS9 0x0002
-#define TIMDIS10 0x0004
-#define TIMDIS11 0x0008
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-#define TIMDIS3_P 0x03
-#define TIMDIS4_P 0x04
-#define TIMDIS5_P 0x05
-#define TIMDIS6_P 0x06
-#define TIMDIS7_P 0x07
-#define TIMDIS8_P 0x00
-#define TIMDIS9_P 0x01
-#define TIMDIS10_P 0x02
-#define TIMDIS11_P 0x03
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x00000001
-#define TIMIL1 0x00000002
-#define TIMIL2 0x00000004
-#define TIMIL3 0x00000008
-#define TIMIL4 0x00010000
-#define TIMIL5 0x00020000
-#define TIMIL6 0x00040000
-#define TIMIL7 0x00080000
-#define TIMIL8 0x0001
-#define TIMIL9 0x0002
-#define TIMIL10 0x0004
-#define TIMIL11 0x0008
-#define TOVF_ERR0 0x00000010
-#define TOVF_ERR1 0x00000020
-#define TOVF_ERR2 0x00000040
-#define TOVF_ERR3 0x00000080
-#define TOVF_ERR4 0x00100000
-#define TOVF_ERR5 0x00200000
-#define TOVF_ERR6 0x00400000
-#define TOVF_ERR7 0x00800000
-#define TOVF_ERR8 0x0010
-#define TOVF_ERR9 0x0020
-#define TOVF_ERR10 0x0040
-#define TOVF_ERR11 0x0080
-#define TRUN0 0x00001000
-#define TRUN1 0x00002000
-#define TRUN2 0x00004000
-#define TRUN3 0x00008000
-#define TRUN4 0x10000000
-#define TRUN5 0x20000000
-#define TRUN6 0x40000000
-#define TRUN7 0x80000000
-#define TRUN8 0x1000
-#define TRUN9 0x2000
-#define TRUN10 0x4000
-#define TRUN11 0x8000
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TIMIL3_P 0x03
-#define TIMIL4_P 0x10
-#define TIMIL5_P 0x11
-#define TIMIL6_P 0x12
-#define TIMIL7_P 0x13
-#define TIMIL8_P 0x00
-#define TIMIL9_P 0x01
-#define TIMIL10_P 0x02
-#define TIMIL11_P 0x03
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TOVF_ERR3_P 0x07
-#define TOVF_ERR4_P 0x14
-#define TOVF_ERR5_P 0x15
-#define TOVF_ERR6_P 0x16
-#define TOVF_ERR7_P 0x17
-#define TOVF_ERR8_P 0x04
-#define TOVF_ERR9_P 0x05
-#define TOVF_ERR10_P 0x06
-#define TOVF_ERR11_P 0x07
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-#define TRUN3_P 0x0F
-#define TRUN4_P 0x1C
-#define TRUN5_P 0x1D
-#define TRUN6_P 0x1E
-#define TRUN7_P 0x1F
-#define TRUN8_P 0x0C
-#define TRUN9_P 0x0D
-#define TRUN10_P 0x0E
-#define TRUN11_P 0x0F
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-#define TOVL_ERR8 TOVF_ERR8
-#define TOVL_ERR9 TOVF_ERR9
-#define TOVL_ERR10 TOVF_ERR10
-#define TOVL_ERR11 TOVF_ERR11
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-#define TOVL_ERR3_P TOVF_ERR3_P
-#define TOVL_ERR4_P TOVF_ERR4_P
-#define TOVL_ERR5_P TOVF_ERR5_P
-#define TOVL_ERR6_P TOVF_ERR6_P
-#define TOVL_ERR7_P TOVF_ERR7_P
-#define TOVL_ERR8_P TOVF_ERR8_P
-#define TOVL_ERR9_P TOVF_ERR9_P
-#define TOVL_ERR10_P TOVF_ERR10_P
-#define TOVL_ERR11_P TOVF_ERR11_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#define ERR_TYP(x) ((x & 0x03) << 14)
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
-#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
-#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
-#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
-#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */
-#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */
-#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */
-#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
-#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */
-#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */
-#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */
-#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */
-#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */
-
-#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */
-#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */
-#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */
-#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */
-#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */
-
-#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */
-#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */
-#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */
-#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */
-#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-#endif /* _DEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/dma.h b/arch/blackfin/mach-bf561/include/mach/dma.h
deleted file mode 100644
index 13647c7..0000000
--- a/arch/blackfin/mach-bf561/include/mach/dma.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 36
-
-/* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */
-#define MAX_DMA_SUSPEND_CHANNELS 32
-
-#define CH_PPI0 0
-#define CH_PPI (CH_PPI0)
-#define CH_PPI1 1
-#define CH_SPORT0_RX 12
-#define CH_SPORT0_TX 13
-#define CH_SPORT1_RX 14
-#define CH_SPORT1_TX 15
-#define CH_SPI 16
-#define CH_UART_RX 17
-#define CH_UART_TX 18
-#define CH_MEM_STREAM0_DEST 24 /* TX */
-#define CH_MEM_STREAM0_SRC 25 /* RX */
-#define CH_MEM_STREAM1_DEST 26 /* TX */
-#define CH_MEM_STREAM1_SRC 27 /* RX */
-#define CH_MEM_STREAM2_DEST 28
-#define CH_MEM_STREAM2_SRC 29
-#define CH_MEM_STREAM3_DEST 30
-#define CH_MEM_STREAM3_SRC 31
-#define CH_IMEM_STREAM0_DEST 32
-#define CH_IMEM_STREAM0_SRC 33
-#define CH_IMEM_STREAM1_DEST 34
-#define CH_IMEM_STREAM1_SRC 35
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
deleted file mode 100644
index f9f8b2a..0000000
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PF16 16
-#define GPIO_PF17 17
-#define GPIO_PF18 18
-#define GPIO_PF19 19
-#define GPIO_PF20 20
-#define GPIO_PF21 21
-#define GPIO_PF22 22
-#define GPIO_PF23 23
-#define GPIO_PF24 24
-#define GPIO_PF25 25
-#define GPIO_PF26 26
-#define GPIO_PF27 27
-#define GPIO_PF28 28
-#define GPIO_PF29 29
-#define GPIO_PF30 30
-#define GPIO_PF31 31
-#define GPIO_PF32 32
-#define GPIO_PF33 33
-#define GPIO_PF34 34
-#define GPIO_PF35 35
-#define GPIO_PF36 36
-#define GPIO_PF37 37
-#define GPIO_PF38 38
-#define GPIO_PF39 39
-#define GPIO_PF40 40
-#define GPIO_PF41 41
-#define GPIO_PF42 42
-#define GPIO_PF43 43
-#define GPIO_PF44 44
-#define GPIO_PF45 45
-#define GPIO_PF46 46
-#define GPIO_PF47 47
-
-#define PORT_FIO0 GPIO_PF0
-#define PORT_FIO1 GPIO_PF16
-#define PORT_FIO2 GPIO_PF32
-
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
deleted file mode 100644
index d699852..0000000
--- a/arch/blackfin/mach-bf561/include/mach/irq.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF561_IRQ_H_
-#define _BF561_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
-#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
-#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
-#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
-#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
-#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
-#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
-#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
-#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
-#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
-#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
-#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
-#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
-#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
-#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
-#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
-#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
-#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
-#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
-#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
-#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
-#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
-#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
-#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
-#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
-#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
-#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
-#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
-#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
-#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
-#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
-#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
-#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
-#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
-#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
-#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
-#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
-#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
-#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
-#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
-#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
-#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
-#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
-#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
-#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
-#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
-#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
-#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
-#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
-#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
-#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
-#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
-#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
-#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
-#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
-#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
-#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
-#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
-#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
-#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
-#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
-#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
-#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
-#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
-#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
-#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
-#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
-#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
-#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
-#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */
-
-#define SYS_IRQS 71
-
-#define IRQ_PF0 73
-#define IRQ_PF1 74
-#define IRQ_PF2 75
-#define IRQ_PF3 76
-#define IRQ_PF4 77
-#define IRQ_PF5 78
-#define IRQ_PF6 79
-#define IRQ_PF7 80
-#define IRQ_PF8 81
-#define IRQ_PF9 82
-#define IRQ_PF10 83
-#define IRQ_PF11 84
-#define IRQ_PF12 85
-#define IRQ_PF13 86
-#define IRQ_PF14 87
-#define IRQ_PF15 88
-#define IRQ_PF16 89
-#define IRQ_PF17 90
-#define IRQ_PF18 91
-#define IRQ_PF19 92
-#define IRQ_PF20 93
-#define IRQ_PF21 94
-#define IRQ_PF22 95
-#define IRQ_PF23 96
-#define IRQ_PF24 97
-#define IRQ_PF25 98
-#define IRQ_PF26 99
-#define IRQ_PF27 100
-#define IRQ_PF28 101
-#define IRQ_PF29 102
-#define IRQ_PF30 103
-#define IRQ_PF31 104
-#define IRQ_PF32 105
-#define IRQ_PF33 106
-#define IRQ_PF34 107
-#define IRQ_PF35 108
-#define IRQ_PF36 109
-#define IRQ_PF37 110
-#define IRQ_PF38 111
-#define IRQ_PF39 112
-#define IRQ_PF40 113
-#define IRQ_PF41 114
-#define IRQ_PF42 115
-#define IRQ_PF43 116
-#define IRQ_PF44 117
-#define IRQ_PF45 118
-#define IRQ_PF46 119
-#define IRQ_PF47 120
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF47 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA1_ERROR_POS 4
-#define IRQ_DMA2_ERROR_POS 8
-#define IRQ_IMDMA_ERROR_POS 12
-#define IRQ_PPI0_ERROR_POS 16
-#define IRQ_PPI1_ERROR_POS 20
-#define IRQ_SPORT0_ERROR_POS 24
-#define IRQ_SPORT1_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPI_ERROR_POS 0
-#define IRQ_UART_ERROR_POS 4
-#define IRQ_RESERVED_ERROR_POS 8
-#define IRQ_DMA1_0_POS 12
-#define IRQ_DMA1_1_POS 16
-#define IRQ_DMA1_2_POS 20
-#define IRQ_DMA1_3_POS 24
-#define IRQ_DMA1_4_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_DMA1_5_POS 0
-#define IRQ_DMA1_6_POS 4
-#define IRQ_DMA1_7_POS 8
-#define IRQ_DMA1_8_POS 12
-#define IRQ_DMA1_9_POS 16
-#define IRQ_DMA1_10_POS 20
-#define IRQ_DMA1_11_POS 24
-#define IRQ_DMA2_0_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA2_1_POS 0
-#define IRQ_DMA2_2_POS 4
-#define IRQ_DMA2_3_POS 8
-#define IRQ_DMA2_4_POS 12
-#define IRQ_DMA2_5_POS 16
-#define IRQ_DMA2_6_POS 20
-#define IRQ_DMA2_7_POS 24
-#define IRQ_DMA2_8_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_DMA2_9_POS 0
-#define IRQ_DMA2_10_POS 4
-#define IRQ_DMA2_11_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_TIMER8_POS 12
-#define IRQ_TIMER9_POS 16
-#define IRQ_TIMER10_POS 20
-#define IRQ_TIMER11_POS 24
-#define IRQ_PROG0_INTA_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_PROG0_INTB_POS 0
-#define IRQ_PROG1_INTA_POS 4
-#define IRQ_PROG1_INTB_POS 8
-#define IRQ_PROG2_INTA_POS 12
-#define IRQ_PROG2_INTB_POS 16
-#define IRQ_DMA1_WRRD0_POS 20
-#define IRQ_DMA1_WRRD1_POS 24
-#define IRQ_DMA2_WRRD0_POS 28
-
-/* IAR7 BIT FIELDS */
-#define IRQ_DMA2_WRRD1_POS 0
-#define IRQ_IMDMA_WRRD0_POS 4
-#define IRQ_IMDMA_WRRD1_POS 8
-#define IRQ_WDTIMER_POS 12
-#define IRQ_RESERVED_1_POS 16
-#define IRQ_RESERVED_2_POS 20
-#define IRQ_SUPPLE_0_POS 24
-#define IRQ_SUPPLE_1_POS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
deleted file mode 100644
index 4cc9199..0000000
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * BF561 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x800
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF561 processors */
-
-#define COREA_L1_CODE_START 0xFFA00000
-#define COREA_L1_DATA_A_START 0xFF800000
-#define COREA_L1_DATA_B_START 0xFF900000
-#define COREB_L1_CODE_START 0xFF600000
-#define COREB_L1_DATA_A_START 0xFF400000
-#define COREB_L1_DATA_B_START 0xFF500000
-
-#define L1_CODE_START COREA_L1_CODE_START
-#define L1_DATA_A_START COREA_L1_DATA_A_START
-#define L1_DATA_B_START COREA_L1_DATA_B_START
-
-#define L1_CODE_LENGTH 0x4000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/*
- * If we are in SMP mode, then the cache settings of Core B will match
- * the settings of Core A. If we aren't, then we assume Core B is not
- * using any cache. This allows the rest of the kernel to work with
- * the core in either mode as we are only loading user code into it and
- * it is the user's problem to make sure they aren't doing something
- * stupid there.
- *
- * Note that we treat the L1 code region as a contiguous blob to make
- * the rest of the kernel simpler. Easier to check one region than a
- * bunch of small ones. Again, possible misbehavior here is the fault
- * of the user -- don't try to use memory that doesn't exist.
- */
-#ifdef CONFIG_SMP
-# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH
-# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
-# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
-#else
-# define COREB_L1_CODE_LENGTH 0x14000
-# define COREB_L1_DATA_A_LENGTH 0x8000
-# define COREB_L1_DATA_B_LENGTH 0x8000
-#endif
-
-/* Level 2 Memory */
-#define L2_START 0xFEB00000
-#define L2_LENGTH 0x20000
-
-/* Scratch Pad Memory */
-
-#define COREA_L1_SCRATCH_START 0xFFB00000
-#define COREB_L1_SCRATCH_START 0xFF700000
-
-#ifdef CONFIG_SMP
-
-/*
- * The following macros both return the address of the PDA for the
- * current core.
- *
- * In its first safe (and hairy) form, the macro neither clobbers any
- * register aside of the output Preg, nor uses the stack, since it
- * could be called with an invalid stack pointer, or the current stack
- * space being uncovered by any CPLB (e.g. early exception handling).
- *
- * The constraints on the second form are a bit relaxed, and the code
- * is allowed to use the specified Dreg for determining the PDA
- * address to be returned into Preg.
- */
-# define GET_PDA_SAFE(preg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- preg = [preg]; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- if cc jump 2f; \
- cc = preg == 0x0; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- if !cc jump 3f; \
-1: \
- /* preg = 0x0; */ \
- cc = !cc; /* restore cc to 0 */ \
- jump 4f; \
-2: \
- cc = preg == 0x0; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- if cc jump 4f; \
- /* preg = 0x1000000; */ \
- cc = !cc; /* restore cc to 1 */ \
-3: \
- preg = [preg]; \
-4:
-
-# define GET_PDA(preg, dreg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- dreg = [preg]; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- cc = bittst(dreg, 0); \
- if !cc jump 1f; \
- preg = [preg]; \
-1: \
-
-# define GET_CPUID(preg, dreg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- dreg = [preg]; \
- dreg = ROT dreg BY -1; \
- dreg = CC;
-
-# ifndef __ASSEMBLY__
-
-# include <asm/processor.h>
-
-static inline unsigned long get_l1_scratch_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
-}
-static inline unsigned long get_l1_code_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
-}
-static inline unsigned long get_l1_data_a_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
-}
-static inline unsigned long get_l1_data_b_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
-}
-
-static inline unsigned long get_l1_scratch_start(void)
-{
- return get_l1_scratch_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_code_start(void)
-{
- return get_l1_code_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_data_a_start(void)
-{
- return get_l1_data_a_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_data_b_start(void)
-{
- return get_l1_data_b_start_cpu(blackfin_core_id());
-}
-
-# endif /* __ASSEMBLY__ */
-#endif /* CONFIG_SMP */
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
deleted file mode 100644
index 00bdace..0000000
--- a/arch/blackfin/mach-bf561/include/mach/pll.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_SMP
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-#include <mach/irq.h>
-
-#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
-#define SUPPLE_1_WAKEUP ((IRQ_SUPPLE_1 - (IRQ_CORETMR + 1)) % 32)
-
-static inline void
-bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
-{
- unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
-
- bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
- bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
-}
-#define bfin_iwr_restore bfin_iwr_restore
-
-static inline void
-bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
- unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
- unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
-
- *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
- *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
- bfin_iwr_restore(niwr0, niwr1, niwr2);
-}
-#define bfin_iwr_save bfin_iwr_save
-
-static inline void
-bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
- bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP) |
- IWR_ENABLE(SUPPLE_1_WAKEUP), 0, iwr0, iwr1, iwr2);
-}
-
-#endif
-
-#endif
-
-#include <mach-common/pll.h>
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/portmux.h b/arch/blackfin/mach-bf561/include/mach/portmux.h
deleted file mode 100644
index 2339ffd..0000000
--- a/arch/blackfin/mach-bf561/include/mach/portmux.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-#define P_PPI0_FS3 (P_DONTCARE)
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-#define P_PPI0_D4 (P_DONTCARE)
-#define P_PPI0_D5 (P_DONTCARE)
-#define P_PPI0_D6 (P_DONTCARE)
-#define P_PPI0_D7 (P_DONTCARE)
-#define P_PPI1_CLK (P_DONTCARE)
-#define P_PPI1_FS1 (P_DONTCARE)
-#define P_PPI1_FS2 (P_DONTCARE)
-#define P_PPI1_FS3 (P_DONTCARE)
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
-#define P_PPI1_D0 (P_DONTCARE)
-#define P_PPI1_D1 (P_DONTCARE)
-#define P_PPI1_D2 (P_DONTCARE)
-#define P_PPI1_D3 (P_DONTCARE)
-#define P_PPI1_D4 (P_DONTCARE)
-#define P_PPI1_D5 (P_DONTCARE)
-#define P_PPI1_D6 (P_DONTCARE)
-#define P_PPI1_D7 (P_DONTCARE)
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
-#define P_SPORT0_DRPRI (P_DONTCARE)
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_TMR11 (P_DONTCARE)
-#define P_TMR10 (P_DONTCARE)
-#define P_TMR9 (P_DONTCARE)
-#define P_TMR8 (P_DONTCARE)
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h
deleted file mode 100644
index 346c605..0000000
--- a/arch/blackfin/mach-bf561/include/mach/smp.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BF561_SMP
-#define _MACH_BF561_SMP
-
-/* This header has to stand alone to avoid circular deps */
-
-struct task_struct;
-
-void platform_init_cpus(void);
-
-void platform_prepare_cpus(unsigned int max_cpus);
-
-int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
-
-void platform_secondary_init(unsigned int cpu);
-
-void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler);
-
-void platform_send_ipi(cpumask_t callmap, int irq);
-
-void platform_send_ipi_cpu(unsigned int cpu, int irq);
-
-void platform_clear_ipi(unsigned int cpu, int irq);
-
-void bfin_local_timer_setup(void);
-
-#endif /* !_MACH_BF561_SMP */
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c
deleted file mode 100644
index 7ee9262..0000000
--- a/arch/blackfin/mach-bf561/ints-priority.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
- ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
- ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
- ((CONFIG_IRQ_PPI0_ERROR - 7) << IRQ_PPI0_ERROR_POS) |
- ((CONFIG_IRQ_PPI1_ERROR - 7) << IRQ_PPI1_ERROR_POS) |
- ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
- ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
- ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
- ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
- ((CONFIG_IRQ_DMA1_1 - 7) << IRQ_DMA1_1_POS) |
- ((CONFIG_IRQ_DMA1_2 - 7) << IRQ_DMA1_2_POS) |
- ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
- ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
- ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
- ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
- ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
- ((CONFIG_IRQ_DMA1_9 - 7) << IRQ_DMA1_9_POS) |
- ((CONFIG_IRQ_DMA1_10 - 7) << IRQ_DMA1_10_POS) |
- ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
- ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
- ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
- ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
- ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
- ((CONFIG_IRQ_DMA2_5 - 7) << IRQ_DMA2_5_POS) |
- ((CONFIG_IRQ_DMA2_6 - 7) << IRQ_DMA2_6_POS) |
- ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
- ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
- ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
- ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
- ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
- ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
- ((CONFIG_IRQ_TIMER10 - 7) << IRQ_TIMER10_POS) |
- ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
- ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
- ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
- ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
- ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
- ((CONFIG_IRQ_PROG2_INTB - 7) << IRQ_PROG2_INTB_POS) |
- ((CONFIG_IRQ_DMA1_WRRD0 - 7) << IRQ_DMA1_WRRD0_POS) |
- ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
- ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
-
- bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
- ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
- ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
- ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
- (0 << IRQ_RESERVED_1_POS) | (0 << IRQ_RESERVED_2_POS) |
- (0 << IRQ_SUPPLE_0_POS) | (0 << IRQ_SUPPLE_1_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
deleted file mode 100644
index 01e5408..0000000
--- a/arch/blackfin/mach-bf561/secondary.S
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * BF561 coreB bootstrap file
- *
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-
-/*
- * This code must come first as CoreB is hardcoded (in hardware)
- * to start at the beginning of its L1 instruction memory.
- */
-.section .l1.text.head
-
-/* Lay the initial stack into the L1 scratch area of Core B */
-#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-ENTRY(_coreb_trampoline_start)
- /* Enable Cycle Counter and Nesting Of Interrupts */
-#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
- R0 = SYSCFG_SNEN;
-#else
- R0 = SYSCFG_SNEN | SYSCFG_CCEN;
-#endif
- SYSCFG = R0;
-
- /* Optimization register tricks: keep a base value in the
- * reserved P registers so we use the load/store with an
- * offset syntax. R0 = [P5 + <constant>];
- * P5 - core MMR base
- * R6 - 0
- */
- r6 = 0;
- p5.l = 0;
- p5.h = hi(COREMMR_BASE);
-
- /* Zero out registers required by Blackfin ABI */
-
- /* Disable circular buffers */
- L0 = r6;
- L1 = r6;
- L2 = r6;
- L3 = r6;
-
- /* Disable hardware loops in case we were started by 'go' */
- LC0 = r6;
- LC1 = r6;
-
- /*
- * Clear ITEST_COMMAND and DTEST_COMMAND registers,
- * Leaving these as non-zero can confuse the emulator
- */
- [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
- [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
- CSYNC;
-
- trace_buffer_init(p0,r0);
-
- /* Turn off the icache */
- r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENICPLB_P);
- [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* Turn off the dcache */
- r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENDCPLB_P);
- [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* in case of double faults, save a few things */
- p1.l = _initial_pda_coreb;
- p1.h = _initial_pda_coreb;
- r4 = RETX;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Only save these if we are storing them,
- * This happens here, since L1 gets clobbered
- * below
- */
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_DF_RETX];
- r1 = [p0 + PDA_DF_DCPLB];
- r2 = [p0 + PDA_DF_ICPLB];
- r3 = [p0 + PDA_DF_SEQSTAT];
- [p1 + PDA_INIT_DF_RETX] = r0;
- [p1 + PDA_INIT_DF_DCPLB] = r1;
- [p1 + PDA_INIT_DF_ICPLB] = r2;
- [p1 + PDA_INIT_DF_SEQSTAT] = r3;
-#endif
- [p1 + PDA_INIT_RETX] = r4;
-
- /* Initialize stack pointer */
- sp.l = lo(INITIAL_STACK);
- sp.h = hi(INITIAL_STACK);
- fp = sp;
- usp = sp;
-
- /* This section keeps the processor in supervisor mode
- * during core B startup. Branches to the idle task.
- */
-
- /* EVT15 = _real_start */
-
- p1.l = _coreb_start;
- p1.h = _coreb_start;
- [p5 + (EVT15 - COREMMR_BASE)] = p1;
- csync;
-
- r0 = EVT_IVG15 (z);
- sti r0;
-
- raise 15;
- p0.l = .LWAIT_HERE;
- p0.h = .LWAIT_HERE;
- reti = p0;
-#if defined(ANOMALY_05000281)
- nop; nop; nop;
-#endif
- rti;
-
-.LWAIT_HERE:
- jump .LWAIT_HERE;
-ENDPROC(_coreb_trampoline_start)
-
-#ifdef CONFIG_HOTPLUG_CPU
-.section ".text"
-ENTRY(_coreb_die)
- sp.l = lo(INITIAL_STACK);
- sp.h = hi(INITIAL_STACK);
- fp = sp;
- usp = sp;
-
- CLI R2;
- SSYNC;
- IDLE;
- STI R2;
-
- R0 = IWR_DISABLE_ALL;
- P0.H = hi(SYSMMR_BASE);
- P0.L = lo(SYSMMR_BASE);
- [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
- [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
- SSYNC;
-
- p0.h = hi(COREB_L1_CODE_START);
- p0.l = lo(COREB_L1_CODE_START);
- jump (p0);
-ENDPROC(_coreb_die)
-#endif
-
-__INIT
-ENTRY(_coreb_start)
- [--sp] = reti;
-
- p0.l = lo(WDOGB_CTL);
- p0.h = hi(WDOGB_CTL);
- r0 = 0xAD6(z);
- w[p0] = r0; /* Clear the watchdog. */
- ssync;
-
- /*
- * switch to IDLE stack.
- */
- p0.l = _secondary_stack;
- p0.h = _secondary_stack;
- sp = [p0];
- usp = sp;
- fp = sp;
-#ifdef CONFIG_HOTPLUG_CPU
- p0.l = _hotplug_coreb;
- p0.h = _hotplug_coreb;
- r0 = [p0];
- cc = BITTST(r0, 0);
- if cc jump 3f;
-#endif
- sp += -12;
- call _init_pda
- sp += 12;
-#ifdef CONFIG_HOTPLUG_CPU
-3:
-#endif
- call _secondary_start_kernel;
-.L_exit:
- jump.s .L_exit;
-ENDPROC(_coreb_start)
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
deleted file mode 100644
index 8c0c80f..0000000
--- a/arch/blackfin/mach-bf561/smp.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <asm/smp.h>
-#include <asm/dma.h>
-#include <asm/time.h>
-
-static DEFINE_SPINLOCK(boot_lock);
-
-/*
- * platform_init_cpus() - Tell the world about how many cores we
- * have. This is called while setting up the architecture support
- * (setup_arch()), so don't be too demanding here with respect to
- * available kernel services.
- */
-
-void __init platform_init_cpus(void)
-{
- struct cpumask mask;
-
- cpumask_set_cpu(0, &mask); /* CoreA */
- cpumask_set_cpu(1, &mask); /* CoreB */
- init_cpu_possible(&mask);
-}
-
-void __init platform_prepare_cpus(unsigned int max_cpus)
-{
- struct cpumask mask;
-
- bfin_relocate_coreb_l1_mem();
-
- /* Both cores ought to be present on a bf561! */
- cpumask_set_cpu(0, &mask); /* CoreA */
- cpumask_set_cpu(1, &mask); /* CoreB */
- init_cpu_present(&mask);
-}
-
-int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
-{
- return -EINVAL;
-}
-
-void platform_secondary_init(unsigned int cpu)
-{
- /* Clone setup for peripheral interrupt sources from CoreA. */
- bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
- bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
- SSYNC();
-
- /* Clone setup for IARs from CoreA. */
- bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
- bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
- bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
- bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
- bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
- bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
- bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
- bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
- bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
- bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
- SSYNC();
-
- /* We are done with local CPU inits, unblock the boot CPU. */
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
-}
-
-int platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
- unsigned long timeout;
-
- printk(KERN_INFO "Booting Core B.\n");
-
- spin_lock(&boot_lock);
-
- if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
- /* CoreB already running, sending ipi to wakeup it */
- smp_send_reschedule(cpu);
- } else {
- /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
- bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
- SSYNC();
- }
-
- timeout = jiffies + HZ;
- /* release the lock and let coreb run */
- spin_unlock(&boot_lock);
- while (time_before(jiffies, timeout)) {
- if (cpu_online(cpu))
- break;
- udelay(100);
- barrier();
- }
-
- if (cpu_online(cpu)) {
- return 0;
- } else
- panic("CPU%u: processor failed to boot\n", cpu);
-}
-
-static const char supple0[] = "IRQ_SUPPLE_0";
-static const char supple1[] = "IRQ_SUPPLE_1";
-void __init platform_request_ipi(int irq, void *handler)
-{
- int ret;
- const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
-
- ret = request_irq(irq, handler, IRQF_PERCPU | IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, name, handler);
- if (ret)
- panic("Cannot request %s for IPI service", name);
-}
-
-void platform_send_ipi(cpumask_t callmap, int irq)
-{
- unsigned int cpu;
- int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
-
- for_each_cpu(cpu, &callmap) {
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
- }
-}
-
-void platform_send_ipi_cpu(unsigned int cpu, int irq)
-{
- int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
-}
-
-void platform_clear_ipi(unsigned int cpu, int irq)
-{
- int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
-}
-
-/*
- * Setup core B's local core timer.
- * In SMP, core timer is used for clock event device.
- */
-void bfin_local_timer_setup(void)
-{
-#if defined(CONFIG_TICKSOURCE_CORETMR)
- struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
- struct irq_chip *chip = irq_data_get_irq_chip(data);
-
- bfin_coretmr_init();
- bfin_coretmr_clockevent_init();
-
- chip->irq_unmask(data);
-#else
- /* Power down the core timer, just to play safe. */
- bfin_write_TCNTL(0);
-#endif
-
-}
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
deleted file mode 100644
index 7d6a8b8..0000000
--- a/arch/blackfin/mach-bf609/Kconfig
+++ /dev/null
@@ -1,1684 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF60x
- def_bool y
- depends on (BF609)
- select IRQ_PREFLOW_FASTEOI
-
-if (BF60x)
-
-source "arch/blackfin/mach-bf609/boards/Kconfig"
-
-menu "BF609 Specific Configuration"
-
-config SEC_IRQ_PRIORITY_LEVELS
- int "SEC interrupt priority levels"
- default 7
- range 0 7
- help
- Divide the total number of interrupt priority levels into sub-levels.
- There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
-
-config L1_PARITY_CHECK
- bool "Enable L1 parity check"
- default n
- help
- Enable the L1 parity check in L1 sram. A fault event is raised
- when L1 parity error is found.
-
-comment "System Cross Bar Priority Assignment"
-
-config SCB_PRIORITY
- bool "Init System Cross Bar Priority"
- default n
-
-menuconfig SCB0_MI0
- bool "SCB0 Master Interface 0 (DDR)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI0
-
-config SCB0_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI0_SLOT20
- int "Slot 20 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI0_SLOT21
- int "Slot 21 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI0_SLOT22
- int "Slot 22 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI0_SLOT23
- int "Slot 23 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI0_SLOT24
- int "Slot 24 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT25
- int "Slot 25 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT26
- int "Slot 26 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT27
- int "Slot 27 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT28
- int "Slot 28 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT29
- int "Slot 29 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT30
- int "Slot 30 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT31
- int "Slot 31 slave interface id"
- default 13
- range 0 13
-
-endif # SCB0_MI0
-
-menuconfig SCB0_MI1
- bool "SCB0 Master Interface 1 (SMC)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI1
-
-config SCB0_MI1_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT1
- int "Slot 1 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT2
- int "Slot 2 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT3
- int "Slot 3 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT4
- int "Slot 4 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT5
- int "Slot 5 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT6
- int "Slot 6 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT7
- int "Slot 7 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI1_SLOT8
- int "Slot 8 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI1_SLOT9
- int "Slot 9 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI1_SLOT10
- int "Slot 10 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI1_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI1_SLOT12
- int "Slot 12 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT13
- int "Slot 13 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI1_SLOT20
- int "Slot 20 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI1_SLOT21
- int "Slot 21 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI1_SLOT22
- int "Slot 22 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI1_SLOT23
- int "Slot 23 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI1_SLOT24
- int "Slot 24 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT25
- int "Slot 25 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT26
- int "Slot 26 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT27
- int "Slot 27 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT28
- int "Slot 28 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT29
- int "Slot 29 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT30
- int "Slot 30 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT31
- int "Slot 31 slave interface id"
- default 13
- range 0 13
-
-endif # SCB0_MI1
-
-menuconfig SCB0_MI2
- bool "SCB0 Master Interface 2 (Data L2)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI2
-
-config SCB0_MI2_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI2
-
-menuconfig SCB0_MI3
- bool "SCB0 Master Interface 3 (L1A)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI3
-
-config SCB0_MI3_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI3
-
-menuconfig SCB0_MI4
- bool "SCB0 Master Interface 4 (L1B)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI4
-
-config SCB0_MI4_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI4
-
-menuconfig SCB0_MI5
- bool "SCB0 Master Interface 5 (SMMR)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- MMR0 -- 1
- MMR1 -- 3
- SCB2 -- 10
- SCB4 -- 12
-
-if SCB0_MI5
-
-config SCB0_MI5_SLOT0
- int "Slot 0 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT1
- int "Slot 1 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT2
- int "Slot 2 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT3
- int "Slot 3 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT4
- int "Slot 4 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT5
- int "Slot 5 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT7
- int "Slot 7 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT8
- int "Slot 8 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT9
- int "Slot 9 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT10
- int "Slot 10 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT12
- int "Slot 12 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT13
- int "Slot 13 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT14
- int "Slot 14 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT15
- int "Slot 15 slave interface id"
- default 12
- range 0 13
-
-endif # SCB0_MI5
-
-menuconfig SCB1_MI0
- bool "SCB1 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- SPORT0A -- 0
- SPORT0B -- 1
- SPORT1A -- 2
- SPORT1B -- 3
- SPORT2A -- 4
- SPORT2B -- 5
- SPI0TX -- 6
- SPI0RX -- 7
- SPI1TX -- 8
- SPI1RX -- 9
-
-if SCB1_MI0
-
-config SCB1_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 9
-
-config SCB1_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 9
-
-config SCB1_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 9
-
-config SCB1_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 9
-
-config SCB1_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 9
-
-config SCB1_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 9
-
-config SCB1_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 9
-
-config SCB1_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 9
-
-config SCB1_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 8
- range 0 9
-
-config SCB1_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 9
- range 0 9
-
-config SCB1_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 0
- range 0 9
-
-config SCB1_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 1
- range 0 9
-
-config SCB1_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 2
- range 0 9
-
-config SCB1_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 3
- range 0 9
-
-config SCB1_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 9
-
-config SCB1_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 9
-
-config SCB1_MI0_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB1_MI0_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB1_MI0_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB1_MI0_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-endif # SCB1_MI0
-
-menuconfig SCB2_MI0
- bool "SCB2 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- RSI -- 0
- SDU DMA -- 1
- SDU -- 2
- EMAC0 -- 3
- EMAC1 -- 4
-
-if SCB2_MI0
-
-config SCB2_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 4
-
-config SCB2_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 4
-
-config SCB2_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 4
-
-config SCB2_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 4
-
-config SCB2_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 4
-
-config SCB2_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 0
- range 0 4
-
-config SCB2_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 1
- range 0 4
-
-config SCB2_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 2
- range 0 4
-
-config SCB2_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 3
- range 0 4
-
-config SCB2_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 4
- range 0 4
-
-endif # SCB2_MI0
-
-menuconfig SCB3_MI0
- bool "SCB3 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- LP0 -- 0
- LP1 -- 1
- LP2 -- 2
- LP3 -- 3
- UART0TX -- 4
- UART0RX -- 5
- UART1TX -- 4
- UART1RX -- 5
-
-if SCB3_MI0
-
-config SCB3_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 7
-
-config SCB3_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 7
-
-config SCB3_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 7
-
-config SCB3_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 7
-
-config SCB3_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 7
-
-config SCB3_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 7
-
-config SCB3_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 7
-
-config SCB3_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 7
-
-config SCB3_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 0
- range 0 7
-
-config SCB3_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 1
- range 0 7
-
-config SCB3_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 2
- range 0 7
-
-config SCB3_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 3
- range 0 7
-
-config SCB3_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 4
- range 0 7
-
-config SCB3_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 5
- range 0 7
-
-config SCB3_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 6
- range 0 7
-
-config SCB3_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 7
- range 0 7
-
-endif # SCB3_MI0
-
-menuconfig SCB4_MI0
- bool "SCB4 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- MDA21 -- 0
- MDA22 -- 1
- MDA23 -- 2
- MDA24 -- 3
- MDA25 -- 4
- MDA26 -- 5
- MDA27 -- 6
- MDA28 -- 7
-
-if SCB4_MI0
-
-config SCB4_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 7
-
-config SCB4_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 7
-
-config SCB4_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 7
-
-config SCB4_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 7
-
-config SCB4_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 7
-
-config SCB4_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 7
-
-config SCB4_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 7
-
-config SCB4_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 7
-
-config SCB4_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 0
- range 0 7
-
-config SCB4_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 1
- range 0 7
-
-config SCB4_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 2
- range 0 7
-
-config SCB4_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 3
- range 0 7
-
-config SCB4_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 4
- range 0 7
-
-config SCB4_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 5
- range 0 7
-
-config SCB4_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 6
- range 0 7
-
-config SCB4_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 7
- range 0 7
-
-endif # SCB4_MI0
-
-menuconfig SCB5_MI0
- bool "SCB5 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PPI0 MDA29 -- 0
- PPI0 MDA30 -- 1
- PPI2 MDA31 -- 2
- PPI2 MDA32 -- 3
-
-if SCB5_MI0
-
-config SCB5_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 3
-
-config SCB5_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 3
-
-config SCB5_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 3
-
-config SCB5_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 3
-
-config SCB5_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 0
- range 0 3
-
-config SCB5_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 1
- range 0 3
-
-config SCB5_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 2
- range 0 3
-
-config SCB5_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 3
- range 0 3
-
-endif # SCB5_MI0
-
-menuconfig SCB6_MI0
- bool "SCB6 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PPI1 MDA33 -- 0
- PPI1 MDA34 -- 1
-
-if SCB6_MI0
-
-config SCB6_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 1
-
-config SCB6_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 1
-
-config SCB6_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 0
- range 0 1
-
-config SCB6_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 1
- range 0 1
-
-endif # SCB6_MI0
-
-menuconfig SCB7_MI0
- bool "SCB7 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PIXC0 -- 0
- PIXC1 -- 1
- PIXC2 -- 2
-
-if SCB7_MI0
-
-config SCB7_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 2
-
-config SCB7_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 2
-
-config SCB7_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 2
-
-config SCB7_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 0
- range 0 2
-
-config SCB7_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 1
- range 0 2
-
-config SCB7_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 2
- range 0 2
-
-endif # SCB7_MI0
-
-menuconfig SCB8_MI0
- bool "SCB8 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PVP CPDOB -- 0
- PVP CPDOC -- 1
- PVP CPCO -- 2
- PVP CPCI -- 3
-
-if SCB8_MI0
-
-config SCB8_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 3
-
-config SCB8_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 3
-
-config SCB8_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 3
-
-config SCB8_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 3
-
-config SCB8_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 0
- range 0 3
-
-config SCB8_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 1
- range 0 3
-
-config SCB8_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 2
- range 0 3
-
-config SCB8_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 3
- range 0 3
-
-endif # SCB8_MI0
-
-menuconfig SCB9_MI0
- bool "SCB9 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PVP MPDO -- 0
- PVP MPDI -- 1
- PVP MPCO -- 2
- PVP MPCI -- 3
- PVP CPDOA -- 4
-
-if SCB9_MI0
-
-config SCB9_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 4
-
-config SCB9_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 4
-
-config SCB9_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 4
-
-config SCB9_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 4
-
-config SCB9_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 4
-
-config SCB9_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 0
- range 0 4
-
-config SCB9_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 1
- range 0 4
-
-config SCB9_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 2
- range 0 4
-
-config SCB9_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 3
- range 0 4
-
-config SCB9_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 4
- range 0 4
-
-endif # SCB9_MI0
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile
deleted file mode 100644
index 60ffaf8..0000000
--- a/arch/blackfin/mach-bf609/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# arch/blackfin/mach-bf609/Makefile
-#
-
-obj-y := dma.o clock.o ints-priority.o
-obj-$(CONFIG_PM) += pm.o dpm.o
-obj-$(CONFIG_SCB_PRIORITY) += scb.o
diff --git a/arch/blackfin/mach-bf609/boards/Kconfig b/arch/blackfin/mach-bf609/boards/Kconfig
deleted file mode 100644
index 350154b..0000000
--- a/arch/blackfin/mach-bf609/boards/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN609_EZKIT
- help
- Select your board!
-
-config BFIN609_EZKIT
- bool "BF609-EZKIT"
- help
- BFIN609-EZKIT board support.
-
-endchoice
diff --git a/arch/blackfin/mach-bf609/boards/Makefile b/arch/blackfin/mach-bf609/boards/Makefile
deleted file mode 100644
index 11f98b0..0000000
--- a/arch/blackfin/mach-bf609/boards/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf609/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN609_EZKIT) += ezkit.o
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
deleted file mode 100644
index 51157a2..0000000
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ /dev/null
@@ -1,2191 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-adi2.h>
-#include <linux/spi/adi_spi3.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/dpmc.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF609-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0C0000,
- .end = 0x2C0C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PG7,
- .end = IRQ_PG7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_STMMAC_ETH)
-#include <linux/stmmac.h>
-#include <linux/phy.h>
-
-static struct stmmac_mdio_bus_data phy_private_data = {
- .phy_mask = 1,
-};
-
-static struct stmmac_dma_cfg eth_dma_cfg = {
- .pbl = 2,
-};
-
-int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
-{
- bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
- return 0;
-}
-
-static struct plat_stmmacenet_data eth_private_data = {
- .has_gmac = 1,
- .bus_id = 0,
- .enh_desc = 1,
- .phy_addr = 1,
- .mdio_bus_data = &phy_private_data,
- .dma_cfg = ð_dma_cfg,
- .force_thresh_dma_mode = 1,
- .interface = PHY_INTERFACE_MODE_RMII,
- .init = stmmac_ptp_clk_init,
-};
-
-static struct platform_device bfin_eth_device = {
- .name = "stmmaceth",
- .id = 0,
- .num_resources = 2,
- .resource = (struct resource[]) {
- {
- .start = EMAC0_MACCFG,
- .end = EMAC0_MACCFG + 0x1274,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "macirq",
- .start = IRQ_EMAC0_STAT,
- .end = IRQ_EMAC0_STAT,
- .flags = IORESOURCE_IRQ,
- },
- },
- .dev = {
- .power.can_wakeup = 1,
- .platform_data = ð_private_data,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_REVID,
- .end = UART0_RXDIV+4,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTD_FER,
- .end = PORTD_FER+2,
- .flags = IORESOURCE_REG,
- },
- {
- .start = PORTD_MUX,
- .end = PORTD_MUX+3,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_STAT,
- .end = IRQ_UART0_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PD10,
- .end = GPIO_PD10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PD9,
- .end = GPIO_PD9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX,
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- P_UART0_RTS, P_UART0_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_REVID,
- .end = UART1_RXDIV+4,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTG_FER_SET,
- .end = PORTG_FER_SET+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_STAT,
- .end = IRQ_UART1_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PG13,
- .end = GPIO_PG13,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PG10,
- .end = GPIO_PG10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFCC1000,
- .end = 0xFFCC1398,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_STAT,
- .end = IRQ_USB_STAT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 0,
- .dma = 1,
- .num_eps = 16,
- .dma_channels = 8,
- .clkin = 48, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-
-static unsigned short bfin_can0_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can0_resources[] = {
- {
- .start = 0xFFC00A00,
- .end = 0xFFC00FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_STAT,
- .end = IRQ_CAN0_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can0_device = {
- .name = "bfin_can",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_can0_resources),
- .resource = bfin_can0_resources,
- .dev = {
- .platform_data = &bfin_can0_peripherals, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x80000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bfin_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bfin_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_nand_device = {
- .name = "bfin-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_nand_resources),
- .resource = bfin_nand_resources,
- .dev = {
- .platform_data = &bfin_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bfin_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x80000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x400000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x1000000 - 0x80000 - 0x400000,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-int bf609_nor_flash_init(struct platform_device *pdev)
-{
-#define CONFIG_SMC_GCTL_VAL 0x00000010
-
- bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
- bfin_write32(SMC_B0CTL, 0x01002011);
- bfin_write32(SMC_B0TIM, 0x08170977);
- bfin_write32(SMC_B0ETIM, 0x00092231);
- return 0;
-}
-
-void bf609_nor_flash_exit(struct platform_device *pdev)
-{
- bfin_write32(SMC_GCTL, 0);
-}
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .init = bf609_nor_flash_init,
- .exit = bf609_nor_flash_exit,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-#ifdef CONFIG_ROMKERNEL
- .probe_type = "map_rom",
-#endif
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0xb0000000,
- .end = 0xb0ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (w25q32) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00080000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x00180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "w25q32",
-};
-
-static struct adi_spi3_chip spi_flash_chip_info = {
- .enable_dma = true, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
-static struct adi_spi3_chip spidev_chip_info = {
- .enable_dma = true,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
-static struct platform_device bfin_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
-#include <asm/bfin_sport3.h>
-static struct resource bfin_snd_resources[] = {
- {
- .start = SPORT0_CTL_A,
- .end = SPORT0_CTL_A,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = SPORT0_CTL_B,
- .end = SPORT0_CTL_B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = IRQ_SPORT0_TX_STAT,
- .end = IRQ_SPORT0_TX_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_RX_STAT,
- .end = IRQ_SPORT0_RX_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const unsigned short bfin_snd_pin[] = {
- P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
- P_SPORT0_BFS, P_SPORT0_BD0, 0,
-};
-
-static struct bfin_snd_platform_data bfin_snd_data = {
- .pin_req = bfin_snd_pin,
-};
-
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .num_resources = ARRAY_SIZE(bfin_snd_resources),
- .resource = bfin_snd_resources,
- .dev = {
- .platform_data = &bfin_snd_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.76",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
-static struct platform_device adau1761_device = {
- .name = "bfin-eval-adau1x61",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
-#include <sound/adau17x1.h>
-static struct adau1761_platform_data adau1761_info = {
- .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
- .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
-#if !IS_ENABLED(CONFIG_VIDEO_VS6624)
- P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
- P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
-#endif
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI3,
- .dma_ch = CH_EPPI0_CH0,
- .irq_err = IRQ_EPPI0_STAT,
- .base = (void __iomem *)EPPI0_STAT,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PE4;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF609",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
- | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
- .blank_pixels = 4,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-#include <media/i2c/adv7842.h>
-
-static struct v4l2_input adv7842_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
- {
- .index = 3,
- .name = "VGA",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
- {
- .index = 4,
- .name = "HDMI",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
-};
-
-static struct bcap_route adv7842_routes[] = {
- {
- .input = 3,
- .output = 0,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
- | EPPI_CTL_ACTIVE656),
- },
- {
- .input = 4,
- .output = 0,
- },
- {
- .input = 2,
- .output = 0,
- },
- {
- .input = 1,
- .output = 0,
- },
- {
- .input = 0,
- .output = 1,
- .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
- | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
- | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
- },
-};
-
-static struct adv7842_output_format adv7842_opf[] = {
- {
- .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
- .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
- .blank_data = 1,
- .insert_av_codes = 1,
- },
- {
- .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
- .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
- .blank_data = 1,
- },
-};
-
-static struct adv7842_platform_data adv7842_data = {
- .opf = adv7842_opf,
- .num_opf = ARRAY_SIZE(adv7842_opf),
- .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
- .prim_mode = ADV7842_PRIM_MODE_SDP,
- .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
- .hdmi_free_run_enable = 1,
- .sdp_free_run_auto = 1,
- .llc_dll_phase = 0x10,
- .i2c_sdp_io = 0x40,
- .i2c_sdp = 0x41,
- .i2c_cp = 0x42,
- .i2c_vdp = 0x43,
- .i2c_afe = 0x44,
- .i2c_hdmi = 0x45,
- .i2c_repeater = 0x46,
- .i2c_edid = 0x47,
- .i2c_infoframe = 0x48,
- .i2c_cec = 0x49,
- .i2c_avlink = 0x4a,
-};
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF609",
- .inputs = adv7842_inputs,
- .num_inputs = ARRAY_SIZE(adv7842_inputs),
- .routes = adv7842_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7842",
- .addr = 0x20,
- .platform_data = (void *)&adv7842_data,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
- | EPPI_CTL_ACTIVE656),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_display.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req_disp[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI3,
- .dma_ch = CH_EPPI0_CH0,
- .irq_err = IRQ_EPPI0_STAT,
- .base = (void __iomem *)EPPI0_STAT,
- .pin_req = ppi_req_disp,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7511)
-#include <media/i2c/adv7511.h>
-
-static struct v4l2_output adv7511_outputs[] = {
- {
- .index = 0,
- .name = "HDMI",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
- },
-};
-
-static struct disp_route adv7511_routes[] = {
- {
- .output = 0,
- },
-};
-
-static struct adv7511_platform_data adv7511_data = {
- .edid_addr = 0x7e,
-};
-
-static struct bfin_display_config bfin_display_data = {
- .card_name = "BF609",
- .outputs = adv7511_outputs,
- .num_outputs = ARRAY_SIZE(adv7511_outputs),
- .routes = adv7511_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7511",
- .addr = 0x39,
- .platform_data = (void *)&adv7511_data,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
- | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
- | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
- | EPPI_CTL_NON656 | EPPI_CTL_DIR),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
-#include <media/i2c/adv7343.h>
-
-static struct v4l2_output adv7343_outputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
-
-};
-
-static struct disp_route adv7343_routes[] = {
- {
- .output = ADV7343_COMPOSITE_ID,
- },
- {
- .output = ADV7343_SVIDEO_ID,
- },
- {
- .output = ADV7343_COMPONENT_ID,
- },
-};
-
-static struct adv7343_platform_data adv7343_data = {
- .mode_config = {
- .sleep_mode = false,
- .pll_control = false,
- .dac_1 = true,
- .dac_2 = true,
- .dac_3 = true,
- .dac_4 = true,
- .dac_5 = true,
- .dac_6 = true,
- },
- .sd_config = {
- .sd_dac_out1 = false,
- .sd_dac_out2 = false,
- },
-};
-
-static struct bfin_display_config bfin_display_data = {
- .card_name = "BF609",
- .outputs = adv7343_outputs,
- .num_outputs = ARRAY_SIZE(adv7343_outputs),
- .routes = adv7343_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7343",
- .addr = 0x2b,
- .platform_data = (void *)&adv7343_data,
- },
- .ppi_info = &ppi_info_disp,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
- | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
- | EPPI_CTL_NON656 | EPPI_CTL_DIR),
-};
-#endif
-
-static struct platform_device bfin_display_device = {
- .name = "bfin_display",
- .dev = {
- .platform_data = &bfin_display_data,
- },
-};
-#endif
-
-#if defined(CONFIG_FB_BF609_NL8048) \
- || defined(CONFIG_FB_BF609_NL8048_MODULE)
-static struct resource nl8048_resources[] = {
- {
- .start = EPPI2_STAT,
- .end = EPPI2_STAT,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_EPPI2_CH0,
- .end = CH_EPPI2_CH0,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = IRQ_EPPI2_STAT,
- .end = IRQ_EPPI2_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-static struct platform_device bfin_fb_device = {
- .name = "bf609_nl8048",
- .num_resources = ARRAY_SIZE(nl8048_resources),
- .resource = nl8048_resources,
- .dev = {
- .platform_data = (void *)GPIO_PC15,
- },
-};
-#endif
-
-#if defined(CONFIG_BFIN_CRC)
-#define BFIN_CRC_NAME "bfin-crc"
-
-static struct resource bfin_crc0_resources[] = {
- {
- .start = REG_CRC0_CTL,
- .end = REG_CRC0_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC0_DCNTEXP,
- .end = IRQ_CRC0_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM0_SRC_CRC0,
- .end = CH_MEM_STREAM0_SRC_CRC0,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_MEM_STREAM0_DEST_CRC0,
- .end = CH_MEM_STREAM0_DEST_CRC0,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crc0_device = {
- .name = BFIN_CRC_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_crc0_resources),
- .resource = bfin_crc0_resources,
-};
-
-static struct resource bfin_crc1_resources[] = {
- {
- .start = REG_CRC1_CTL,
- .end = REG_CRC1_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC1_DCNTEXP,
- .end = IRQ_CRC1_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM1_SRC_CRC1,
- .end = CH_MEM_STREAM1_SRC_CRC1,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_MEM_STREAM1_DEST_CRC1,
- .end = CH_MEM_STREAM1_DEST_CRC1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crc1_device = {
- .name = BFIN_CRC_NAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_crc1_resources),
- .resource = bfin_crc1_resources,
-};
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
-#define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
-#define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
-
-static struct resource bfin_crypto_crc_resources[] = {
- {
- .start = REG_CRC0_CTL,
- .end = REG_CRC0_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC0_DCNTEXP,
- .end = IRQ_CRC0_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM0_SRC_CRC0,
- .end = CH_MEM_STREAM0_SRC_CRC0,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crypto_crc_device = {
- .name = BFIN_CRYPTO_CRC_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
- .resource = bfin_crypto_crc_resources,
- .dev = {
- .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_ADI2
-
-# define ADI_PINT_DEVNAME "adi-gpio-pint"
-# define ADI_GPIO_DEVNAME "adi-gpio"
-# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
-
-static struct platform_device bfin_pinctrl_device = {
- .name = ADI_PINCTRL_DEVNAME,
- .id = 0,
-};
-
-static struct resource bfin_pint0_resources[] = {
- {
- .start = PINT0_MASK_SET,
- .end = PINT0_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT0,
- .end = IRQ_PINT0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint0_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_pint0_resources),
- .resource = bfin_pint0_resources,
-};
-
-static struct resource bfin_pint1_resources[] = {
- {
- .start = PINT1_MASK_SET,
- .end = PINT1_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT1,
- .end = IRQ_PINT1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint1_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_pint1_resources),
- .resource = bfin_pint1_resources,
-};
-
-static struct resource bfin_pint2_resources[] = {
- {
- .start = PINT2_MASK_SET,
- .end = PINT2_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT2,
- .end = IRQ_PINT2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint2_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_pint2_resources),
- .resource = bfin_pint2_resources,
-};
-
-static struct resource bfin_pint3_resources[] = {
- {
- .start = PINT3_MASK_SET,
- .end = PINT3_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT3,
- .end = IRQ_PINT3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint3_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_pint3_resources),
- .resource = bfin_pint3_resources,
-};
-
-static struct resource bfin_pint4_resources[] = {
- {
- .start = PINT4_MASK_SET,
- .end = PINT4_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT4,
- .end = IRQ_PINT4,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint4_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_pint4_resources),
- .resource = bfin_pint4_resources,
-};
-
-static struct resource bfin_pint5_resources[] = {
- {
- .start = PINT5_MASK_SET,
- .end = PINT5_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT5,
- .end = IRQ_PINT5,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint5_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_pint5_resources),
- .resource = bfin_pint5_resources,
-};
-
-static struct resource bfin_gpa_resources[] = {
- {
- .start = PORTA_FER,
- .end = PORTA_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- { /* optional */
- .start = IRQ_PA0,
- .end = IRQ_PA0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
- .port_pin_base = GPIO_PA0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0, /* PINT0 */
- .pint_assign = true, /* PINT upper 16 bit */
- .pint_map = 0, /* mapping mask in PINT */
-};
-
-static struct platform_device bfin_gpa_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_gpa_resources),
- .resource = bfin_gpa_resources,
- .dev = {
- .platform_data = &bfin_gpa_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpb_resources[] = {
- {
- .start = PORTB_FER,
- .end = PORTB_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PB0,
- .end = IRQ_PB0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
- .port_pin_base = GPIO_PB0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpb_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_gpb_resources),
- .resource = bfin_gpb_resources,
- .dev = {
- .platform_data = &bfin_gpb_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpc_resources[] = {
- {
- .start = PORTC_FER,
- .end = PORTC_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PC0,
- .end = IRQ_PC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
- .port_pin_base = GPIO_PC0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 1,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpc_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_gpc_resources),
- .resource = bfin_gpc_resources,
- .dev = {
- .platform_data = &bfin_gpc_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpd_resources[] = {
- {
- .start = PORTD_FER,
- .end = PORTD_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PD0,
- .end = IRQ_PD0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
- .port_pin_base = GPIO_PD0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 2,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpd_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_gpd_resources),
- .resource = bfin_gpd_resources,
- .dev = {
- .platform_data = &bfin_gpd_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpe_resources[] = {
- {
- .start = PORTE_FER,
- .end = PORTE_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE0,
- .end = IRQ_PE0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
- .port_pin_base = GPIO_PE0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpe_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_gpe_resources),
- .resource = bfin_gpe_resources,
- .dev = {
- .platform_data = &bfin_gpe_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpf_resources[] = {
- {
- .start = PORTF_FER,
- .end = PORTF_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
- .port_pin_base = GPIO_PF0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 4,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpf_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_gpf_resources),
- .resource = bfin_gpf_resources,
- .dev = {
- .platform_data = &bfin_gpf_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpg_resources[] = {
- {
- .start = PORTG_FER,
- .end = PORTG_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PG0,
- .end = IRQ_PG0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
- .port_pin_base = GPIO_PG0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 5,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpg_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 6,
- .num_resources = ARRAY_SIZE(bfin_gpg_resources),
- .resource = bfin_gpg_resources,
- .dev = {
- .platform_data = &bfin_gpg_pdata, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PD9,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
- .controller_data = &spidev_chip_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PC5,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = 2,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SPI_ADI_V3)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPI0_TX,
- .end = CH_SPI0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPI0_RX,
- .end = CH_SPI0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPI1_TX,
- .end = CH_SPI1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPI1_RX,
- .end = CH_SPI1_RX,
- .flags = IORESOURCE_DMA,
- },
-
-};
-
-/* SPI controller data */
-static struct adi_spi3_master bf60x_spi_master_info0 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf60x_spi_master0 = {
- .name = "adi-spi3",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct adi_spi3_master bf60x_spi_master_info1 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf60x_spi_master1 = {
- .name = "adi-spi3",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_CLKDIV,
- .end = TWI0_CLKDIV + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_CLKDIV,
- .end = TWI1_CLKDIV + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-#include <linux/spi/mcp23s08.h>
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch0 = {
- .base = 120,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch1 = {
- .base = 130,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch2 = {
- .base = 140,
-};
-# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-static const struct mcp23s08_platform_data bfin_adv7842_soft_switch = {
- .base = 150,
-};
-# endif
-# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
-static const struct mcp23s08_platform_data bfin_adv7511_soft_switch = {
- .base = 160,
-};
-# endif
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PC5,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
- {
- I2C_BOARD_INFO("adau1761", 0x38),
- .platform_data = (void *)&adau1761_info
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
- {
- I2C_BOARD_INFO("mcp23017", 0x21),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch0
- },
- {
- I2C_BOARD_INFO("mcp23017", 0x22),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch1
- },
- {
- I2C_BOARD_INFO("mcp23017", 0x23),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch2
- },
-# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
- {
- I2C_BOARD_INFO("mcp23017", 0x26),
- .platform_data = (void *)&bfin_adv7842_soft_switch
- },
-# endif
-# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
- {
- I2C_BOARD_INFO("mcp23017", 0x25),
- .platform_data = (void *)&bfin_adv7511_soft_switch
- },
-# endif
-#endif
-};
-
-static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-#if defined(CONFIG_PINCTRL_ADI2)
- &bfin_pinctrl_device,
- &bfin_pint0_device,
- &bfin_pint1_device,
- &bfin_pint2_device,
- &bfin_pint3_device,
- &bfin_pint4_device,
- &bfin_pint5_device,
- &bfin_gpa_device,
- &bfin_gpb_device,
- &bfin_gpc_device,
- &bfin_gpd_device,
- &bfin_gpe_device,
- &bfin_gpf_device,
- &bfin_gpg_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_STMMAC_ETH)
- &bfin_eth_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bfin_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bfin_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_ADI_V3)
- &bf60x_spi_master0,
- &bf60x_spi_master1,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if defined(CONFIG_BFIN_CRC)
- &bfin_crc0_device,
- &bfin_crc1_device,
-#endif
-#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
- &bfin_crypto_crc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
- &bfin_pcm,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
- &bfin_i2s,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
- &adau1761_device,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
- &bfin_display_device,
-#endif
-
-};
-
-/* Pin control settings */
-static struct pinctrl_map __initdata bfin_pinmux_map[] = {
- /* per-device maps */
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
- PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
- PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_display.0", "8bit", "pinctrl-adi2.0", "ppi2_8bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_display.0", "16bit", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "8bit", "pinctrl-adi2.0", "ppi0_8bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "16bit", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "24bit", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- /* Initialize pinmuxing */
- pinctrl_register_mappings(bfin_pinmux_map,
- ARRAY_SIZE(bfin_pinmux_map));
-
- i2c_register_board_info(0, bfin_i2c_board_info0,
- ARRAY_SIZE(bfin_i2c_board_info0));
- i2c_register_board_info(1, bfin_i2c_board_info1,
- ARRAY_SIZE(bfin_i2c_board_info1));
-
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
deleted file mode 100644
index 16e0b09..0000000
--- a/arch/blackfin/mach-bf609/clock.c
+++ /dev/null
@@ -1,409 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/spinlock.h>
-#include <linux/debugfs.h>
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-#include <linux/seq_file.h>
-#include <linux/clkdev.h>
-
-#include <asm/clocks.h>
-
-#define CGU0_CTL_DF (1 << 0)
-
-#define CGU0_CTL_MSEL_SHIFT 8
-#define CGU0_CTL_MSEL_MASK (0x7f << 8)
-
-#define CGU0_STAT_PLLEN (1 << 0)
-#define CGU0_STAT_PLLBP (1 << 1)
-#define CGU0_STAT_PLLLK (1 << 2)
-#define CGU0_STAT_CLKSALGN (1 << 3)
-#define CGU0_STAT_CCBF0 (1 << 4)
-#define CGU0_STAT_CCBF1 (1 << 5)
-#define CGU0_STAT_SCBF0 (1 << 6)
-#define CGU0_STAT_SCBF1 (1 << 7)
-#define CGU0_STAT_DCBF (1 << 8)
-#define CGU0_STAT_OCBF (1 << 9)
-#define CGU0_STAT_ADDRERR (1 << 16)
-#define CGU0_STAT_LWERR (1 << 17)
-#define CGU0_STAT_DIVERR (1 << 18)
-#define CGU0_STAT_WDFMSERR (1 << 19)
-#define CGU0_STAT_WDIVERR (1 << 20)
-#define CGU0_STAT_PLOCKERR (1 << 21)
-
-#define CGU0_DIV_CSEL_SHIFT 0
-#define CGU0_DIV_CSEL_MASK 0x0000001F
-#define CGU0_DIV_S0SEL_SHIFT 5
-#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT)
-#define CGU0_DIV_SYSSEL_SHIFT 8
-#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT)
-#define CGU0_DIV_S1SEL_SHIFT 13
-#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT)
-#define CGU0_DIV_DSEL_SHIFT 16
-#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT)
-#define CGU0_DIV_OSEL_SHIFT 22
-#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT)
-
-#define CLK(_clk, _devname, _conname) \
- { \
- .clk = &_clk, \
- .dev_id = _devname, \
- .con_id = _conname, \
- }
-
-#define NEEDS_INITIALIZATION 0x11
-
-static LIST_HEAD(clk_list);
-
-static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
-{
- u32 val2;
-
- val2 = bfin_read32(reg);
- val2 &= ~mask;
- val2 |= val;
- bfin_write32(reg, val2);
-}
-
-int wait_for_pll_align(void)
-{
- int i = 10000;
- while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
-
- if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
- printk(KERN_CRIT "fail to align clk\n");
- return -1;
- }
-
- return 0;
-}
-
-int clk_enable(struct clk *clk)
-{
- int ret = -EIO;
- if (clk->ops && clk->ops->enable)
- ret = clk->ops->enable(clk);
- return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- if (!clk)
- return;
-
- if (clk->ops && clk->ops->disable)
- clk->ops->disable(clk);
-}
-EXPORT_SYMBOL(clk_disable);
-
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long ret = 0;
- if (clk->ops && clk->ops->get_rate)
- ret = clk->ops->get_rate(clk);
- return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- long ret = 0;
- if (clk->ops && clk->ops->round_rate)
- ret = clk->ops->round_rate(clk, rate);
- return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EIO;
- if (clk->ops && clk->ops->set_rate)
- ret = clk->ops->set_rate(clk, rate);
- return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-unsigned long vco_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-
-unsigned long pll_get_rate(struct clk *clk)
-{
- u32 df;
- u32 msel;
- u32 ctl = bfin_read32(CGU0_CTL);
- u32 stat = bfin_read32(CGU0_STAT);
- if (stat & CGU0_STAT_PLLBP)
- return 0;
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate / (df + 1) * msel * 2;
-}
-
-unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 div;
- div = rate / clk->parent->rate;
- return clk->parent->rate * div;
-}
-
-int pll_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 msel;
- u32 stat = bfin_read32(CGU0_STAT);
- if (!(stat & CGU0_STAT_PLLEN))
- return -EBUSY;
- if (!(stat & CGU0_STAT_PLLLK))
- return -EBUSY;
- if (wait_for_pll_align())
- return -EBUSY;
- msel = rate / clk->parent->rate / 2;
- clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT,
- CGU0_CTL_MSEL_MASK);
- clk->rate = rate;
- return 0;
-}
-
-unsigned long cclk_get_rate(struct clk *clk)
-{
- if (clk->parent)
- return clk->parent->rate;
- else
- return 0;
-}
-
-unsigned long sys_clk_get_rate(struct clk *clk)
-{
- unsigned long drate;
- u32 msel;
- u32 df;
- u32 ctl = bfin_read32(CGU0_CTL);
- u32 div = bfin_read32(CGU0_DIV);
- div = (div & clk->mask) >> clk->shift;
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
-
- if (!strcmp(clk->parent->name, "SYS_CLKIN")) {
- drate = clk->parent->rate / (df + 1);
- drate *= msel;
- drate /= div;
- return drate;
- } else {
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate / div;
- }
-}
-
-unsigned long dummy_get_rate(struct clk *clk)
-{
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate;
-}
-
-unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long max_rate;
- unsigned long drate;
- int i;
- u32 msel;
- u32 df;
- u32 ctl = bfin_read32(CGU0_CTL);
-
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
- max_rate = clk->parent->rate / (df + 1) * msel;
-
- if (rate > max_rate)
- return 0;
-
- for (i = 1; i < clk->mask; i++) {
- drate = max_rate / i;
- if (rate >= drate)
- return drate;
- }
- return 0;
-}
-
-int sys_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 div = bfin_read32(CGU0_DIV);
- div = (div & clk->mask) >> clk->shift;
-
- rate = clk_round_rate(clk, rate);
-
- if (!rate)
- return -EINVAL;
-
- div = (clk_get_rate(clk) * div) / rate;
-
- if (wait_for_pll_align())
- return -EBUSY;
- clk_reg_write_mask(CGU0_DIV, div << clk->shift,
- clk->mask);
- clk->rate = rate;
- return 0;
-}
-
-static struct clk_ops vco_ops = {
- .get_rate = vco_get_rate,
-};
-
-static struct clk_ops pll_ops = {
- .get_rate = pll_get_rate,
- .set_rate = pll_set_rate,
-};
-
-static struct clk_ops cclk_ops = {
- .get_rate = cclk_get_rate,
-};
-
-static struct clk_ops sys_clk_ops = {
- .get_rate = sys_clk_get_rate,
- .set_rate = sys_clk_set_rate,
- .round_rate = sys_clk_round_rate,
-};
-
-static struct clk_ops dummy_clk_ops = {
- .get_rate = dummy_get_rate,
-};
-
-static struct clk sys_clkin = {
- .name = "SYS_CLKIN",
- .rate = CONFIG_CLKIN_HZ,
- .ops = &vco_ops,
-};
-
-static struct clk pll_clk = {
- .name = "PLLCLK",
- .rate = 500000000,
- .parent = &sys_clkin,
- .ops = &pll_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk cclk = {
- .name = "CCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_CSEL_MASK,
- .shift = CGU0_DIV_CSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk cclk0 = {
- .name = "CCLK0",
- .parent = &cclk,
- .ops = &cclk_ops,
-};
-
-static struct clk cclk1 = {
- .name = "CCLK1",
- .parent = &cclk,
- .ops = &cclk_ops,
-};
-
-static struct clk sysclk = {
- .name = "SYSCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_SYSSEL_MASK,
- .shift = CGU0_DIV_SYSSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk sclk0 = {
- .name = "SCLK0",
- .rate = 500000000,
- .mask = CGU0_DIV_S0SEL_MASK,
- .shift = CGU0_DIV_S0SEL_SHIFT,
- .parent = &sysclk,
- .ops = &sys_clk_ops,
-};
-
-static struct clk sclk1 = {
- .name = "SCLK1",
- .rate = 500000000,
- .mask = CGU0_DIV_S1SEL_MASK,
- .shift = CGU0_DIV_S1SEL_SHIFT,
- .parent = &sysclk,
- .ops = &sys_clk_ops,
-};
-
-static struct clk dclk = {
- .name = "DCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_DSEL_MASK,
- .shift = CGU0_DIV_DSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
-};
-
-static struct clk oclk = {
- .name = "OCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_OSEL_MASK,
- .shift = CGU0_DIV_OSEL_SHIFT,
- .parent = &pll_clk,
-};
-
-static struct clk ethclk = {
- .name = "stmmaceth",
- .parent = &sclk0,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk ethpclk = {
- .name = "pclk",
- .parent = &sclk0,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk spiclk = {
- .name = "spi",
- .parent = &sclk1,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk_lookup bf609_clks[] = {
- CLK(sys_clkin, NULL, "SYS_CLKIN"),
- CLK(pll_clk, NULL, "PLLCLK"),
- CLK(cclk, NULL, "CCLK"),
- CLK(cclk0, NULL, "CCLK0"),
- CLK(cclk1, NULL, "CCLK1"),
- CLK(sysclk, NULL, "SYSCLK"),
- CLK(sclk0, NULL, "SCLK0"),
- CLK(sclk1, NULL, "SCLK1"),
- CLK(dclk, NULL, "DCLK"),
- CLK(oclk, NULL, "OCLK"),
- CLK(ethclk, NULL, "stmmaceth"),
- CLK(ethpclk, NULL, "pclk"),
- CLK(spiclk, NULL, "spi"),
-};
-
-int __init clk_init(void)
-{
- int i;
- struct clk *clkp;
- for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) {
- clkp = bf609_clks[i].clk;
- if (clkp->flags & NEEDS_INITIALIZATION)
- clk_get_rate(clkp);
- }
- clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks));
- return 0;
-}
diff --git a/arch/blackfin/mach-bf609/dma.c b/arch/blackfin/mach-bf609/dma.c
deleted file mode 100644
index 1da4b38..0000000
--- a/arch/blackfin/mach-bf609/dma.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) DMA20_NEXT_DESC_PTR,
- (struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR,
- (struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR,
- (struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR,
- (struct dma_register *) DMA29_NEXT_DESC_PTR,
- (struct dma_register *) DMA30_NEXT_DESC_PTR,
- (struct dma_register *) DMA31_NEXT_DESC_PTR,
- (struct dma_register *) DMA32_NEXT_DESC_PTR,
- (struct dma_register *) DMA33_NEXT_DESC_PTR,
- (struct dma_register *) DMA34_NEXT_DESC_PTR,
- (struct dma_register *) DMA35_NEXT_DESC_PTR,
- (struct dma_register *) DMA36_NEXT_DESC_PTR,
- (struct dma_register *) DMA37_NEXT_DESC_PTR,
- (struct dma_register *) DMA38_NEXT_DESC_PTR,
- (struct dma_register *) DMA39_NEXT_DESC_PTR,
- (struct dma_register *) DMA40_NEXT_DESC_PTR,
- (struct dma_register *) DMA41_NEXT_DESC_PTR,
- (struct dma_register *) DMA42_NEXT_DESC_PTR,
- (struct dma_register *) DMA43_NEXT_DESC_PTR,
- (struct dma_register *) DMA44_NEXT_DESC_PTR,
- (struct dma_register *) DMA45_NEXT_DESC_PTR,
- (struct dma_register *) DMA46_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
- case CH_SPI0_TX:
- ret_irq = IRQ_SPI0_TX;
- break;
- case CH_SPI0_RX:
- ret_irq = IRQ_SPI0_RX;
- break;
- case CH_SPI1_TX:
- ret_irq = IRQ_SPI1_TX;
- break;
- case CH_SPI1_RX:
- ret_irq = IRQ_SPI1_RX;
- break;
- case CH_RSI:
- ret_irq = IRQ_RSI;
- break;
- case CH_SDU:
- ret_irq = IRQ_SDU;
- break;
- case CH_LP0:
- ret_irq = IRQ_LP0;
- break;
- case CH_LP1:
- ret_irq = IRQ_LP1;
- break;
- case CH_LP2:
- ret_irq = IRQ_LP2;
- break;
- case CH_LP3:
- ret_irq = IRQ_LP3;
- break;
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
- case CH_EPPI0_CH0:
- ret_irq = IRQ_EPPI0_CH0;
- break;
- case CH_EPPI0_CH1:
- ret_irq = IRQ_EPPI0_CH1;
- break;
- case CH_EPPI1_CH0:
- ret_irq = IRQ_EPPI1_CH0;
- break;
- case CH_EPPI1_CH1:
- ret_irq = IRQ_EPPI1_CH1;
- break;
- case CH_EPPI2_CH0:
- ret_irq = IRQ_EPPI2_CH0;
- break;
- case CH_EPPI2_CH1:
- ret_irq = IRQ_EPPI2_CH1;
- break;
- case CH_PIXC_CH0:
- ret_irq = IRQ_PIXC_CH0;
- break;
- case CH_PIXC_CH1:
- ret_irq = IRQ_PIXC_CH1;
- break;
- case CH_PIXC_CH2:
- ret_irq = IRQ_PIXC_CH2;
- break;
- case CH_PVP_CPDOB:
- ret_irq = IRQ_PVP_CPDOB;
- break;
- case CH_PVP_CPDOC:
- ret_irq = IRQ_PVP_CPDOC;
- break;
- case CH_PVP_CPSTAT:
- ret_irq = IRQ_PVP_CPSTAT;
- break;
- case CH_PVP_CPCI:
- ret_irq = IRQ_PVP_CPCI;
- break;
- case CH_PVP_MPDO:
- ret_irq = IRQ_PVP_MPDO;
- break;
- case CH_PVP_MPDI:
- ret_irq = IRQ_PVP_MPDI;
- break;
- case CH_PVP_MPSTAT:
- ret_irq = IRQ_PVP_MPSTAT;
- break;
- case CH_PVP_MPCI:
- ret_irq = IRQ_PVP_MPCI;
- break;
- case CH_PVP_CPDOA:
- ret_irq = IRQ_PVP_CPDOA;
- break;
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MDMAS0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MDMAS1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MDMAS2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MDMAS3;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf609/dpm.S b/arch/blackfin/mach-bf609/dpm.S
deleted file mode 100644
index fcb8f68..0000000
--- a/arch/blackfin/mach-bf609/dpm.S
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/dpmc.h>
-
-#include <asm/context.S>
-
-#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-.section .l1.text
-ENTRY(_enter_hibernate)
- /* switch stack to L1 scratch, prepare for ddr srfr */
- P0.H = HI(PM_STACK);
- P0.L = LO(PM_STACK);
- SP = P0;
-
- call _bf609_ddr_sr;
- call _bfin_hibernate_syscontrol;
-
- P0.H = HI(DPM0_RESTORE4);
- P0.L = LO(DPM0_RESTORE4);
- P1.H = _bf609_pm_data;
- P1.L = _bf609_pm_data;
- [P0] = P1;
-
- P0.H = HI(DPM0_CTL);
- P0.L = LO(DPM0_CTL);
- R3.H = HI(0x00000010);
- R3.L = LO(0x00000010);
-
- bfin_init_pm_bench_cycles;
-
- [P0] = R3;
-
- SSYNC;
-ENDPROC(_enter_hibernate)
-
-/* DPM wake up interrupt won't wake up core on bf60x if its core IMASK
- * is disabled. This behavior differ from bf5xx serial processor.
- */
-ENTRY(_dummy_deepsleep)
- [--sp] = SYSCFG;
- [--sp] = (R7:0,P5:0);
- cli r0;
-
- /* get wake up interrupt ID */
- P0.l = LO(SEC_SCI_BASE + SEC_CSID);
- P0.h = HI(SEC_SCI_BASE + SEC_CSID);
- R0 = [P0];
-
- /* ACK wake up interrupt in SEC */
- P1.l = LO(SEC_END);
- P1.h = HI(SEC_END);
-
- [P1] = R0;
- SSYNC;
-
- /* restore EVT 11 entry */
- p0.h = hi(EVT11);
- p0.l = lo(EVT11);
- p1.h = _evt_evt11;
- p1.l = _evt_evt11;
-
- [p0] = p1;
- SSYNC;
-
- (R7:0,P5:0) = [sp++];
- SYSCFG = [sp++];
- RTI;
-ENDPROC(_dummy_deepsleep)
-
-ENTRY(_enter_deepsleep)
- LINK 0xC;
- [--sp] = (R7:0,P5:0);
-
- /* Change EVT 11 entry to dummy handler for wake up event */
- p0.h = hi(EVT11);
- p0.l = lo(EVT11);
- p1.h = _dummy_deepsleep;
- p1.l = _dummy_deepsleep;
-
- [p0] = p1;
-
- P0.H = HI(PM_STACK);
- P0.L = LO(PM_STACK);
-
- EX_SCRATCH_REG = SP;
- SP = P0;
-
- SSYNC;
-
- /* should put ddr to self refresh mode before sleep */
- call _bf609_ddr_sr;
-
- /* Set DPM controller to deep sleep mode */
- P0.H = HI(DPM0_CTL);
- P0.L = LO(DPM0_CTL);
- R3.H = HI(0x00000008);
- R3.L = LO(0x00000008);
- [P0] = R3;
- CSYNC;
-
- /* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */
- r0.l = 0x800;
- r0.h = 0;
- sti r0;
- SSYNC;
-
- bfin_init_pm_bench_cycles;
-
- /* Fall into deep sleep in idle*/
- idle;
- SSYNC;
-
- /* Restore PLL after wake up from deep sleep */
- call _bf609_resume_ccbuf;
-
- /* turn ddr out of self refresh mode */
- call _bf609_ddr_sr_exit;
-
- SP = EX_SCRATCH_REG;
-
- (R7:0,P5:0) = [SP++];
- UNLINK;
- RTS;
-ENDPROC(_enter_deepsleep)
-
-.section .text
-ENTRY(_bf609_hibernate)
- bfin_cpu_reg_save;
- bfin_core_mmr_save;
-
- P0.H = _bf609_pm_data;
- P0.L = _bf609_pm_data;
- R1.H = 0xDEAD;
- R1.L = 0xBEEF;
- R2.H = .Lpm_resume_here;
- R2.L = .Lpm_resume_here;
- [P0++] = R1;
- [P0++] = R2;
- [P0++] = SP;
-
- P1.H = _enter_hibernate;
- P1.L = _enter_hibernate;
-
- call (P1);
-.Lpm_resume_here:
-
- bfin_core_mmr_restore;
- bfin_cpu_reg_restore;
-
- [--sp] = RETI; /* Clear Global Interrupt Disable */
- SP += 4;
-
- RTS;
-
-ENDPROC(_bf609_hibernate)
-
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
deleted file mode 100644
index 696786e..0000000
--- a/arch/blackfin/mach-bf609/include/mach/anomaly.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2012 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF609 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
-#define ANOMALY_16000003 (1)
-/* The EPPI Data Enable (DEN) Signal is Not Functional */
-#define ANOMALY_16000004 (__SILICON_REVISION__ < 1)
-/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
-#define ANOMALY_16000005 (__SILICON_REVISION__ < 1)
-/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
-#define ANOMALY_16000006 (__SILICON_REVISION__ < 1)
-/* DDR2 Memory Reads May Fail Intermittently */
-#define ANOMALY_16000007 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_16000008 (1)
-/* TestSET Instruction Cannot Be Interrupted */
-#define ANOMALY_16000009 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_16000010 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_16000011 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_16000012 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_16000013 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_16000014 (1)
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_16000015 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_16000017 (1)
-/* RSI Boot Cleanup Routine Does Not Clear Registers */
-#define ANOMALY_16000018 (__SILICON_REVISION__ < 1)
-/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
-#define ANOMALY_16000019 (__SILICON_REVISION__ < 1)
-/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
-#define ANOMALY_16000020 (__SILICON_REVISION__ < 1)
-/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
-#define ANOMALY_16000021 (__SILICON_REVISION__ < 1)
-/* Boot Code Fails to Enable Parity Fault Detection */
-#define ANOMALY_16000022 (__SILICON_REVISION__ < 1)
-/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */
-#define ANOMALY_16000023 (__SILICON_REVISION__ < 1)
-/* Spurious Fault Signaled After Clearing an Externally Generated Fault */
-#define ANOMALY_16000024 (1)
-/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
-#define ANOMALY_16000025 (1)
-/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
-#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
-/* Default SPI Master Boot Mode Setting is Incorrect */
-#define ANOMALY_16000028 (__SILICON_REVISION__ < 1)
-/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */
-#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
-/* Interrupted Core Reads of MMRs May Cause Data Loss */
-#define ANOMALY_16000030 (__SILICON_REVISION__ < 1)
-/* Incorrect Default USB_PLL_OSC.PLLM Value */
-#define ANOMALY_16000031 (__SILICON_REVISION__ < 1)
-/* Core Reads of System MMRs May Cause the Core to Hang */
-#define ANOMALY_16000032 (__SILICON_REVISION__ < 1)
-/* PPI Data Underflow on First Word Not Reported in Certain Modes */
-#define ANOMALY_16000033 (1)
-/* CNV1 Red Pixel Substitution feature not functional in the PVP */
-#define ANOMALY_16000034 (__SILICON_REVISION__ < 1)
-/* IPF0 Output Port Color Separation feature not functional */
-#define ANOMALY_16000035 (__SILICON_REVISION__ < 1)
-/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */
-#define ANOMALY_16000036 (__SILICON_REVISION__ < 1)
-/* Core RAISE 2 Instruction Not Latched When Executed@Priority Level 0, 1, or 2 */
-#define ANOMALY_16000037 (__SILICON_REVISION__ < 1)
-/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
-#define ANOMALY_16000038 (__SILICON_REVISION__ < 1)
-/* CGU_STAT.PLOCKERR Bit May be Unreliable */
-#define ANOMALY_16000039 (1)
-/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */
-#define ANOMALY_16000040 (1)
-/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */
-#define ANOMALY_16000041 (1)
-/* Instruction Cache Failure When Parity Is Enabled */
-#define ANOMALY_16000042 (__SILICON_REVISION__ == 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000481 (1)
-
-/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
-#define ANOMALY_05000491 ANOMALY_16000008
-#define ANOMALY_05000477 ANOMALY_16000009
-#define ANOMALY_05000443 ANOMALY_16000010
-#define ANOMALY_05000461 ANOMALY_16000011
-#define ANOMALY_05000426 ANOMALY_16000012
-#define ANOMALY_05000310 ANOMALY_16000013
-#define ANOMALY_05000245 ANOMALY_16000014
-#define ANOMALY_05000074 ANOMALY_16000015
-#define ANOMALY_05000416 ANOMALY_16000017
-
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/bf609.h b/arch/blackfin/mach-bf609/include/mach/bf609.h
deleted file mode 100644
index c897c2a..0000000
--- a/arch/blackfin/mach-bf609/include/mach/bf609.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF609_H__
-#define __MACH_BF609_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF609)
-# define CPU "BF609"
-# define CPUID 0x27fe /* temperary fake value */
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF609_H__ */
diff --git a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
deleted file mode 100644
index 1fd3981..0000000
--- a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-#define BFIN_UART_TX_FIFO_SIZE 8
-
-#define BFIN_UART_BF60X_STYLE
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/blackfin.h b/arch/blackfin/mach-bf609/include/mach/blackfin.h
deleted file mode 100644
index b1a48c4..0000000
--- a/arch/blackfin/mach-bf609/include/mach/blackfin.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf609.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF609
-# include "defBF609.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF609
-# include "cdefBF609.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
deleted file mode 100644
index c4f3fe1..0000000
--- a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF609_H
-#define _CDEF_BF609_H
-
-/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */
-#include "cdefBF60x_base.h"
-
-/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
-
-#endif /* _CDEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
deleted file mode 100644
index 102ee40..0000000
--- a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
+++ /dev/null
@@ -1,3254 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF60X_H
-#define _CDEF_BF60X_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
-/* ************************************************************** */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-/* SEC0 Registers */
-#define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL)
-#define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val)
-#define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID)
-#define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val)
-#define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL)
-#define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val)
-
-#define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL)
-#define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val)
-
-#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8))
-#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val)
-
-#define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8))
-#define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
-
-/* RCU0 Registers */
-#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
-#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
-
-/* Watchdog Timer Registers */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_REVID() bfin_read32(UART0_REVID)
-#define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val)
-#define bfin_read_UART0_GCTL() bfin_read32(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val)
-#define bfin_read_UART0_STAT() bfin_read32(UART0_STAT)
-#define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val)
-#define bfin_read_UART0_SCR() bfin_read32(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val)
-#define bfin_read_UART0_CLK() bfin_read32(UART0_CLK)
-#define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val)
-#define bfin_read_UART0_IER() bfin_read32(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val)
-#define bfin_read_UART0_IER_SET() bfin_read32(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read32(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_RBR() bfin_read32(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val)
-#define bfin_read_UART0_THR() bfin_read32(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val)
-#define bfin_read_UART0_TAIP() bfin_read32(UART0_TAIP)
-#define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val)
-#define bfin_read_UART0_TSR() bfin_read32(UART0_TSR)
-#define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val)
-#define bfin_read_UART0_RSR() bfin_read32(UART0_RSR)
-#define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val)
-#define bfin_read_UART0_TXCNT() bfin_read32(UART0_TXCNT)
-#define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val)
-#define bfin_read_UART0_RXCNT() bfin_read32(UART0_RXCNT)
-#define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_REVID() bfin_read32(UART1_REVID)
-#define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val)
-#define bfin_read_UART1_GCTL() bfin_read32(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val)
-#define bfin_read_UART1_STAT() bfin_read32(UART1_STAT)
-#define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val)
-#define bfin_read_UART1_SCR() bfin_read32(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val)
-#define bfin_read_UART1_CLK() bfin_read32(UART1_CLK)
-#define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val)
-#define bfin_read_UART1_IER() bfin_read32(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val)
-#define bfin_read_UART1_IER_SET() bfin_read32(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read32(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_RBR() bfin_read32(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val)
-#define bfin_read_UART1_THR() bfin_read32(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val)
-#define bfin_read_UART1_TAIP() bfin_read32(UART1_TAIP)
-#define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val)
-#define bfin_read_UART1_TSR() bfin_read32(UART1_TSR)
-#define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val)
-#define bfin_read_UART1_RSR() bfin_read32(UART1_RSR)
-#define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val)
-#define bfin_read_UART1_TXCNT() bfin_read32(UART1_TXCNT)
-#define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val)
-#define bfin_read_UART1_RXCNT() bfin_read32(UART1_RXCNT)
-#define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val)
-
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL() bfin_read32(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val)
-#define bfin_read_SPI0_RXCTL() bfin_read32(SPI0_RXCTL)
-#define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val)
-#define bfin_read_SPI0_TXCTL() bfin_read32(SPI0_TXCTL)
-#define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val)
-#define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK)
-#define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val)
-#define bfin_read_SPI0_DLY() bfin_read32(SPI0_DLY)
-#define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val)
-#define bfin_read_SPI0_SLVSEL() bfin_read32(SPI0_SLVSEL)
-#define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val)
-#define bfin_read_SPI0_RWC() bfin_read32(SPI0_RWC)
-#define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val)
-#define bfin_read_SPI0_RWCR() bfin_read32(SPI0_RWCR)
-#define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val)
-#define bfin_read_SPI0_TWC() bfin_read32(SPI0_TWC)
-#define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val)
-#define bfin_read_SPI0_TWCR() bfin_read32(SPI0_TWCR)
-#define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val)
-#define bfin_read_SPI0_IMSK() bfin_read32(SPI0_IMSK)
-#define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val)
-#define bfin_read_SPI0_IMSK_CLR() bfin_read32(SPI0_IMSK_CLR)
-#define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val)
-#define bfin_read_SPI0_IMSK_SET() bfin_read32(SPI0_IMSK_SET)
-#define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val)
-#define bfin_read_SPI0_STAT() bfin_read32(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val)
-#define bfin_read_SPI0_ILAT() bfin_read32(SPI0_ILAT)
-#define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val)
-#define bfin_read_SPI0_ILAT_CLR() bfin_read32(SPI0_ILAT_CLR)
-#define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val)
-#define bfin_read_SPI0_RFIFO() bfin_read32(SPI0_RFIFO)
-#define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val)
-#define bfin_read_SPI0_TFIFO() bfin_read32(SPI0_TFIFO)
-#define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val)
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val)
-#define bfin_read_SPI1_RXCTL() bfin_read32(SPI1_RXCTL)
-#define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val)
-#define bfin_read_SPI1_TXCTL() bfin_read32(SPI1_TXCTL)
-#define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val)
-#define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK)
-#define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val)
-#define bfin_read_SPI1_DLY() bfin_read32(SPI1_DLY)
-#define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val)
-#define bfin_read_SPI1_SLVSEL() bfin_read32(SPI1_SLVSEL)
-#define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val)
-#define bfin_read_SPI1_RWC() bfin_read32(SPI1_RWC)
-#define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val)
-#define bfin_read_SPI1_RWCR() bfin_read32(SPI1_RWCR)
-#define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val)
-#define bfin_read_SPI1_TWC() bfin_read32(SPI1_TWC)
-#define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val)
-#define bfin_read_SPI1_TWCR() bfin_read32(SPI1_TWCR)
-#define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val)
-#define bfin_read_SPI1_IMSK() bfin_read32(SPI1_IMSK)
-#define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val)
-#define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR)
-#define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val)
-#define bfin_read_SPI1_IMSK_SET() bfin_read32(SPI1_IMSK_SET)
-#define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val)
-#define bfin_read_SPI1_STAT() bfin_read32(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val)
-#define bfin_read_SPI1_ILAT() bfin_read32(SPI1_ILAT)
-#define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val)
-#define bfin_read_SPI1_ILAT_CLR() bfin_read32(SPI1_ILAT_CLR)
-#define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val)
-#define bfin_read_SPI1_RFIFO() bfin_read32(SPI1_RFIFO)
-#define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val)
-#define bfin_read_SPI1_TFIFO() bfin_read32(SPI1_TFIFO)
-#define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val)
-
-/* Timer 0-7 registers */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-
-
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT1 Registers */
-
-
-/* SMC Registers */
-#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
-#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
-#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
-#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
-#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
-#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
-#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
-#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
-#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
-#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
-#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
-#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
-#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
-#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
-#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
-#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
-#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
-#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
-#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
-#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
-#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
-#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
-#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
-#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
-#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
-#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
-#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
-
-/* DDR2 Memory Control Registers */
-#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
-#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
-#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
-#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
-#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
-#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
-#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
-#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
-#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
-#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
-#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
-#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
-#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
-#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
-#define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL)
-#define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val)
-#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
-#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
-#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
-#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_PREV_DESC_PTR() bfin_read32(DMA0_PREV_DESC_PTR)
-#define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_BWL_COUNT() bfin_read32(DMA0_BWL_COUNT)
-#define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val)
-#define bfin_read_DMA0_CURR_BWL_COUNT() bfin_read32(DMA0_CURR_BWL_COUNT)
-#define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val)
-#define bfin_read_DMA0_BWM_COUNT() bfin_read32(DMA0_BWM_COUNT)
-#define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val)
-#define bfin_read_DMA0_CURR_BWM_COUNT() bfin_read32(DMA0_CURR_BWM_COUNT)
-#define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_PREV_DESC_PTR() bfin_read32(DMA1_PREV_DESC_PTR)
-#define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_BWL_COUNT() bfin_read32(DMA1_BWL_COUNT)
-#define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val)
-#define bfin_read_DMA1_CURR_BWL_COUNT() bfin_read32(DMA1_CURR_BWL_COUNT)
-#define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val)
-#define bfin_read_DMA1_BWM_COUNT() bfin_read32(DMA1_BWM_COUNT)
-#define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val)
-#define bfin_read_DMA1_CURR_BWM_COUNT() bfin_read32(DMA1_CURR_BWM_COUNT)
-#define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_PREV_DESC_PTR() bfin_read32(DMA2_PREV_DESC_PTR)
-#define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_BWL_COUNT() bfin_read32(DMA2_BWL_COUNT)
-#define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val)
-#define bfin_read_DMA2_CURR_BWL_COUNT() bfin_read32(DMA2_CURR_BWL_COUNT)
-#define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val)
-#define bfin_read_DMA2_BWM_COUNT() bfin_read32(DMA2_BWM_COUNT)
-#define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val)
-#define bfin_read_DMA2_CURR_BWM_COUNT() bfin_read32(DMA2_CURR_BWM_COUNT)
-#define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_PREV_DESC_PTR() bfin_read32(DMA3_PREV_DESC_PTR)
-#define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_BWL_COUNT() bfin_read32(DMA3_BWL_COUNT)
-#define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val)
-#define bfin_read_DMA3_CURR_BWL_COUNT() bfin_read32(DMA3_CURR_BWL_COUNT)
-#define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val)
-#define bfin_read_DMA3_BWM_COUNT() bfin_read32(DMA3_BWM_COUNT)
-#define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val)
-#define bfin_read_DMA3_CURR_BWM_COUNT() bfin_read32(DMA3_CURR_BWM_COUNT)
-#define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_PREV_DESC_PTR() bfin_read32(DMA4_PREV_DESC_PTR)
-#define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_BWL_COUNT() bfin_read32(DMA4_BWL_COUNT)
-#define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val)
-#define bfin_read_DMA4_CURR_BWL_COUNT() bfin_read32(DMA4_CURR_BWL_COUNT)
-#define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val)
-#define bfin_read_DMA4_BWM_COUNT() bfin_read32(DMA4_BWM_COUNT)
-#define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val)
-#define bfin_read_DMA4_CURR_BWM_COUNT() bfin_read32(DMA4_CURR_BWM_COUNT)
-#define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_PREV_DESC_PTR() bfin_read32(DMA5_PREV_DESC_PTR)
-#define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_BWL_COUNT() bfin_read32(DMA5_BWL_COUNT)
-#define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val)
-#define bfin_read_DMA5_CURR_BWL_COUNT() bfin_read32(DMA5_CURR_BWL_COUNT)
-#define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val)
-#define bfin_read_DMA5_BWM_COUNT() bfin_read32(DMA5_BWM_COUNT)
-#define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val)
-#define bfin_read_DMA5_CURR_BWM_COUNT() bfin_read32(DMA5_CURR_BWM_COUNT)
-#define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_PREV_DESC_PTR() bfin_read32(DMA6_PREV_DESC_PTR)
-#define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_BWL_COUNT() bfin_read32(DMA6_BWL_COUNT)
-#define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val)
-#define bfin_read_DMA6_CURR_BWL_COUNT() bfin_read32(DMA6_CURR_BWL_COUNT)
-#define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val)
-#define bfin_read_DMA6_BWM_COUNT() bfin_read32(DMA6_BWM_COUNT)
-#define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val)
-#define bfin_read_DMA6_CURR_BWM_COUNT() bfin_read32(DMA6_CURR_BWM_COUNT)
-#define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_PREV_DESC_PTR() bfin_read32(DMA7_PREV_DESC_PTR)
-#define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_BWL_COUNT() bfin_read32(DMA7_BWL_COUNT)
-#define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val)
-#define bfin_read_DMA7_CURR_BWL_COUNT() bfin_read32(DMA7_CURR_BWL_COUNT)
-#define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val)
-#define bfin_read_DMA7_BWM_COUNT() bfin_read32(DMA7_BWM_COUNT)
-#define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val)
-#define bfin_read_DMA7_CURR_BWM_COUNT() bfin_read32(DMA7_CURR_BWM_COUNT)
-#define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_PREV_DESC_PTR() bfin_read32(DMA8_PREV_DESC_PTR)
-#define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_BWL_COUNT() bfin_read32(DMA8_BWL_COUNT)
-#define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val)
-#define bfin_read_DMA8_CURR_BWL_COUNT() bfin_read32(DMA8_CURR_BWL_COUNT)
-#define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val)
-#define bfin_read_DMA8_BWM_COUNT() bfin_read32(DMA8_BWM_COUNT)
-#define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val)
-#define bfin_read_DMA8_CURR_BWM_COUNT() bfin_read32(DMA8_CURR_BWM_COUNT)
-#define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_PREV_DESC_PTR() bfin_read32(DMA9_PREV_DESC_PTR)
-#define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read32(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read32(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_BWL_COUNT() bfin_read32(DMA9_BWL_COUNT)
-#define bfin_write_DMA9_BWL_COUNT(val) bfin_write32(DMA9_BWL_COUNT, val)
-#define bfin_read_DMA9_CURR_BWL_COUNT() bfin_read32(DMA9_CURR_BWL_COUNT)
-#define bfin_write_DMA9_CURR_BWL_COUNT(val) bfin_write32(DMA9_CURR_BWL_COUNT, val)
-#define bfin_read_DMA9_BWM_COUNT() bfin_read32(DMA9_BWM_COUNT)
-#define bfin_write_DMA9_BWM_COUNT(val) bfin_write32(DMA9_BWM_COUNT, val)
-#define bfin_read_DMA9_CURR_BWM_COUNT() bfin_read32(DMA9_CURR_BWM_COUNT)
-#define bfin_write_DMA9_CURR_BWM_COUNT(val) bfin_write32(DMA9_CURR_BWM_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_PREV_DESC_PTR() bfin_read32(DMA10_PREV_DESC_PTR)
-#define bfin_write_DMA10_PREV_DESC_PTR(val) bfin_write32(DMA10_PREV_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_BWL_COUNT() bfin_read32(DMA10_BWL_COUNT)
-#define bfin_write_DMA10_BWL_COUNT(val) bfin_write32(DMA10_BWL_COUNT, val)
-#define bfin_read_DMA10_CURR_BWL_COUNT() bfin_read32(DMA10_CURR_BWL_COUNT)
-#define bfin_write_DMA10_CURR_BWL_COUNT(val) bfin_write32(DMA10_CURR_BWL_COUNT, val)
-#define bfin_read_DMA10_BWM_COUNT() bfin_read32(DMA10_BWM_COUNT)
-#define bfin_write_DMA10_BWM_COUNT(val) bfin_write32(DMA10_BWM_COUNT, val)
-#define bfin_read_DMA10_CURR_BWM_COUNT() bfin_read32(DMA10_CURR_BWM_COUNT)
-#define bfin_write_DMA10_CURR_BWM_COUNT(val) bfin_write32(DMA10_CURR_BWM_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read32(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read32(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read32(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read32(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read32(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_PREV_DESC_PTR() bfin_read32(DMA11_PREV_DESC_PTR)
-#define bfin_write_DMA11_PREV_DESC_PTR(val) bfin_write32(DMA11_PREV_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read32(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read32(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read32(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_BWL_COUNT() bfin_read32(DMA11_BWL_COUNT)
-#define bfin_write_DMA11_BWL_COUNT(val) bfin_write32(DMA11_BWL_COUNT, val)
-#define bfin_read_DMA11_CURR_BWL_COUNT() bfin_read32(DMA11_CURR_BWL_COUNT)
-#define bfin_write_DMA11_CURR_BWL_COUNT(val) bfin_write32(DMA11_CURR_BWL_COUNT, val)
-#define bfin_read_DMA11_BWM_COUNT() bfin_read32(DMA11_BWM_COUNT)
-#define bfin_write_DMA11_BWM_COUNT(val) bfin_write32(DMA11_BWM_COUNT, val)
-#define bfin_read_DMA11_CURR_BWM_COUNT() bfin_read32(DMA11_CURR_BWM_COUNT)
-#define bfin_write_DMA11_CURR_BWM_COUNT(val) bfin_write32(DMA11_CURR_BWM_COUNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read32(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write32(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read32(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write32(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read32(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write32(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read32(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write32(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read32(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write32(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_PREV_DESC_PTR() bfin_read32(DMA12_PREV_DESC_PTR)
-#define bfin_write_DMA12_PREV_DESC_PTR(val) bfin_write32(DMA12_PREV_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read32(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read32(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write32(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read32(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write32(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_BWL_COUNT() bfin_read32(DMA12_BWL_COUNT)
-#define bfin_write_DMA12_BWL_COUNT(val) bfin_write32(DMA12_BWL_COUNT, val)
-#define bfin_read_DMA12_CURR_BWL_COUNT() bfin_read32(DMA12_CURR_BWL_COUNT)
-#define bfin_write_DMA12_CURR_BWL_COUNT(val) bfin_write32(DMA12_CURR_BWL_COUNT, val)
-#define bfin_read_DMA12_BWM_COUNT() bfin_read32(DMA12_BWM_COUNT)
-#define bfin_write_DMA12_BWM_COUNT(val) bfin_write32(DMA12_BWM_COUNT, val)
-#define bfin_read_DMA12_CURR_BWM_COUNT() bfin_read32(DMA12_CURR_BWM_COUNT)
-#define bfin_write_DMA12_CURR_BWM_COUNT(val) bfin_write32(DMA12_CURR_BWM_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read32(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write32(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read32(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write32(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read32(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write32(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read32(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write32(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read32(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write32(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_PREV_DESC_PTR() bfin_read32(DMA13_PREV_DESC_PTR)
-#define bfin_write_DMA13_PREV_DESC_PTR(val) bfin_write32(DMA13_PREV_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read32(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write32(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read32(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write32(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read32(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write32(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_BWL_COUNT() bfin_read32(DMA13_BWL_COUNT)
-#define bfin_write_DMA13_BWL_COUNT(val) bfin_write32(DMA13_BWL_COUNT, val)
-#define bfin_read_DMA13_CURR_BWL_COUNT() bfin_read32(DMA13_CURR_BWL_COUNT)
-#define bfin_write_DMA13_CURR_BWL_COUNT(val) bfin_write32(DMA13_CURR_BWL_COUNT, val)
-#define bfin_read_DMA13_BWM_COUNT() bfin_read32(DMA13_BWM_COUNT)
-#define bfin_write_DMA13_BWM_COUNT(val) bfin_write32(DMA13_BWM_COUNT, val)
-#define bfin_read_DMA13_CURR_BWM_COUNT() bfin_read32(DMA13_CURR_BWM_COUNT)
-#define bfin_write_DMA13_CURR_BWM_COUNT(val) bfin_write32(DMA13_CURR_BWM_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read32(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write32(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read32(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write32(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read32(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write32(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read32(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write32(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read32(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write32(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_PREV_DESC_PTR() bfin_read32(DMA14_PREV_DESC_PTR)
-#define bfin_write_DMA14_PREV_DESC_PTR(val) bfin_write32(DMA14_PREV_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read32(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read32(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write32(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read32(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write32(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_BWL_COUNT() bfin_read32(DMA14_BWL_COUNT)
-#define bfin_write_DMA14_BWL_COUNT(val) bfin_write32(DMA14_BWL_COUNT, val)
-#define bfin_read_DMA14_CURR_BWL_COUNT() bfin_read32(DMA14_CURR_BWL_COUNT)
-#define bfin_write_DMA14_CURR_BWL_COUNT(val) bfin_write32(DMA14_CURR_BWL_COUNT, val)
-#define bfin_read_DMA14_BWM_COUNT() bfin_read32(DMA14_BWM_COUNT)
-#define bfin_write_DMA14_BWM_COUNT(val) bfin_write32(DMA14_BWM_COUNT, val)
-#define bfin_read_DMA14_CURR_BWM_COUNT() bfin_read32(DMA14_CURR_BWM_COUNT)
-#define bfin_write_DMA14_CURR_BWM_COUNT(val) bfin_write32(DMA14_CURR_BWM_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read32(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write32(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read32(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write32(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read32(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write32(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read32(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write32(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read32(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write32(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_PREV_DESC_PTR() bfin_read32(DMA15_PREV_DESC_PTR)
-#define bfin_write_DMA15_PREV_DESC_PTR(val) bfin_write32(DMA15_PREV_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read32(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read32(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write32(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read32(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write32(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_BWL_COUNT() bfin_read32(DMA15_BWL_COUNT)
-#define bfin_write_DMA15_BWL_COUNT(val) bfin_write32(DMA15_BWL_COUNT, val)
-#define bfin_read_DMA15_CURR_BWL_COUNT() bfin_read32(DMA15_CURR_BWL_COUNT)
-#define bfin_write_DMA15_CURR_BWL_COUNT(val) bfin_write32(DMA15_CURR_BWL_COUNT, val)
-#define bfin_read_DMA15_BWM_COUNT() bfin_read32(DMA15_BWM_COUNT)
-#define bfin_write_DMA15_BWM_COUNT(val) bfin_write32(DMA15_BWM_COUNT, val)
-#define bfin_read_DMA15_CURR_BWM_COUNT() bfin_read32(DMA15_CURR_BWM_COUNT)
-#define bfin_write_DMA15_CURR_BWM_COUNT(val) bfin_write32(DMA15_CURR_BWM_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read32(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write32(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read32(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write32(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read32(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write32(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read32(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write32(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read32(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write32(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_PREV_DESC_PTR() bfin_read32(DMA16_PREV_DESC_PTR)
-#define bfin_write_DMA16_PREV_DESC_PTR(val) bfin_write32(DMA16_PREV_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read32(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write32(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read32(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write32(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read32(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write32(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_BWL_COUNT() bfin_read32(DMA16_BWL_COUNT)
-#define bfin_write_DMA16_BWL_COUNT(val) bfin_write32(DMA16_BWL_COUNT, val)
-#define bfin_read_DMA16_CURR_BWL_COUNT() bfin_read32(DMA16_CURR_BWL_COUNT)
-#define bfin_write_DMA16_CURR_BWL_COUNT(val) bfin_write32(DMA16_CURR_BWL_COUNT, val)
-#define bfin_read_DMA16_BWM_COUNT() bfin_read32(DMA16_BWM_COUNT)
-#define bfin_write_DMA16_BWM_COUNT(val) bfin_write32(DMA16_BWM_COUNT, val)
-#define bfin_read_DMA16_CURR_BWM_COUNT() bfin_read32(DMA16_CURR_BWM_COUNT)
-#define bfin_write_DMA16_CURR_BWM_COUNT(val) bfin_write32(DMA16_CURR_BWM_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read32(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read32(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read32(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read32(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read32(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_PREV_DESC_PTR() bfin_read32(DMA17_PREV_DESC_PTR)
-#define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read32(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read32(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read32(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_BWL_COUNT() bfin_read32(DMA17_BWL_COUNT)
-#define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val)
-#define bfin_read_DMA17_CURR_BWL_COUNT() bfin_read32(DMA17_CURR_BWL_COUNT)
-#define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val)
-#define bfin_read_DMA17_BWM_COUNT() bfin_read32(DMA17_BWM_COUNT)
-#define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val)
-#define bfin_read_DMA17_CURR_BWM_COUNT() bfin_read32(DMA17_CURR_BWM_COUNT)
-#define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read32(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read32(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read32(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read32(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read32(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_PREV_DESC_PTR() bfin_read32(DMA18_PREV_DESC_PTR)
-#define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read32(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read32(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read32(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_BWL_COUNT() bfin_read32(DMA18_BWL_COUNT)
-#define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val)
-#define bfin_read_DMA18_CURR_BWL_COUNT() bfin_read32(DMA18_CURR_BWL_COUNT)
-#define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val)
-#define bfin_read_DMA18_BWM_COUNT() bfin_read32(DMA18_BWM_COUNT)
-#define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val)
-#define bfin_read_DMA18_CURR_BWM_COUNT() bfin_read32(DMA18_CURR_BWM_COUNT)
-#define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read32(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read32(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read32(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read32(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read32(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_PREV_DESC_PTR() bfin_read32(DMA19_PREV_DESC_PTR)
-#define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read32(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read32(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read32(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_BWL_COUNT() bfin_read32(DMA19_BWL_COUNT)
-#define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val)
-#define bfin_read_DMA19_CURR_BWL_COUNT() bfin_read32(DMA19_CURR_BWL_COUNT)
-#define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val)
-#define bfin_read_DMA19_BWM_COUNT() bfin_read32(DMA19_BWM_COUNT)
-#define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val)
-#define bfin_read_DMA19_CURR_BWM_COUNT() bfin_read32(DMA19_CURR_BWM_COUNT)
-#define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read32(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read32(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read32(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read32(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read32(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_PREV_DESC_PTR() bfin_read32(DMA20_PREV_DESC_PTR)
-#define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read32(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read32(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read32(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_BWL_COUNT() bfin_read32(DMA20_BWL_COUNT)
-#define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val)
-#define bfin_read_DMA20_CURR_BWL_COUNT() bfin_read32(DMA20_CURR_BWL_COUNT)
-#define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val)
-#define bfin_read_DMA20_BWM_COUNT() bfin_read32(DMA20_BWM_COUNT)
-#define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val)
-#define bfin_read_DMA20_CURR_BWM_COUNT() bfin_read32(DMA20_CURR_BWM_COUNT)
-#define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val)
-
-
-/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */
-
-#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_START_ADDR() bfin_read32(MDMA0_DEST_CRC0_START_ADDR)
-#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
-#define bfin_read_MDMA0_DEST_CRC0_CONFIG() bfin_read32(MDMA0_DEST_CRC0_CONFIG)
-#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
-#define bfin_read_MDMA0_DEST_CRC0_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_X_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY() bfin_read32(MDMA0_DEST_CRC0_X_MODIFY)
-#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
-#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_Y_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY() bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY)
-#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
-#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS() bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS)
-#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_START_ADDR() bfin_read32(MDMA0_SRC_CRC0_START_ADDR)
-#define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val)
-#define bfin_read_MDMA0_SRC_CRC0_CONFIG() bfin_read32(MDMA0_SRC_CRC0_CONFIG)
-#define bfin_write_MDMA0_SRC_CRC0_CONFIG(val) bfin_write32(MDMA0_SRC_CRC0_CONFIG, val)
-#define bfin_read_MDMA0_SRC_CRC0_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_X_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_X_MODIFY() bfin_read32(MDMA0_SRC_CRC0_X_MODIFY)
-#define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val)
-#define bfin_read_MDMA0_SRC_CRC0_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_Y_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY() bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY)
-#define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val)
-#define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS() bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS)
-#define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers (DMA Channel 23 and 24) */
-
-#define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_START_ADDR() bfin_read32(MDMA1_DEST_CRC1_START_ADDR)
-#define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val)
-#define bfin_read_MDMA1_DEST_CRC1_CONFIG() bfin_read32(MDMA1_DEST_CRC1_CONFIG)
-#define bfin_write_MDMA1_DEST_CRC1_CONFIG(val) bfin_write32(MDMA1_DEST_CRC1_CONFIG, val)
-#define bfin_read_MDMA1_DEST_CRC1_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_X_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_X_MODIFY() bfin_read32(MDMA1_DEST_CRC1_X_MODIFY)
-#define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val)
-#define bfin_read_MDMA1_DEST_CRC1_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_Y_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY() bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY)
-#define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val)
-#define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS() bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS)
-#define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_START_ADDR() bfin_read32(MDMA1_SRC_CRC1_START_ADDR)
-#define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val)
-#define bfin_read_MDMA1_SRC_CRC1_CONFIG() bfin_read32(MDMA1_SRC_CRC1_CONFIG)
-#define bfin_write_MDMA1_SRC_CRC1_CONFIG(val) bfin_write32(MDMA1_SRC_CRC1_CONFIG, val)
-#define bfin_read_MDMA1_SRC_CRC1_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_X_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_X_MODIFY() bfin_read32(MDMA1_SRC_CRC1_X_MODIFY)
-#define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val)
-#define bfin_read_MDMA1_SRC_CRC1_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_Y_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY() bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY)
-#define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val)
-#define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS() bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS)
-#define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val)
-
-
-/* MDMA Stream 2 Registers (DMA Channel 25 and 26) */
-
-#define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() bfin_read32(MDMA2_DEST_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_START_ADDR() bfin_read32(MDMA2_DEST_START_ADDR)
-#define bfin_write_MDMA2_DEST_START_ADDR(val) bfin_write32(MDMA2_DEST_START_ADDR, val)
-#define bfin_read_MDMA2_DEST_CONFIG() bfin_read32(MDMA2_DEST_CONFIG)
-#define bfin_write_MDMA2_DEST_CONFIG(val) bfin_write32(MDMA2_DEST_CONFIG, val)
-#define bfin_read_MDMA2_DEST_X_COUNT() bfin_read32(MDMA2_DEST_X_COUNT)
-#define bfin_write_MDMA2_DEST_X_COUNT(val) bfin_write32(MDMA2_DEST_X_COUNT, val)
-#define bfin_read_MDMA2_DEST_X_MODIFY() bfin_read32(MDMA2_DEST_X_MODIFY)
-#define bfin_write_MDMA2_DEST_X_MODIFY(val) bfin_write32(MDMA2_DEST_X_MODIFY, val)
-#define bfin_read_MDMA2_DEST_Y_COUNT() bfin_read32(MDMA2_DEST_Y_COUNT)
-#define bfin_write_MDMA2_DEST_Y_COUNT(val) bfin_write32(MDMA2_DEST_Y_COUNT, val)
-#define bfin_read_MDMA2_DEST_Y_MODIFY() bfin_read32(MDMA2_DEST_Y_MODIFY)
-#define bfin_write_MDMA2_DEST_Y_MODIFY(val) bfin_write32(MDMA2_DEST_Y_MODIFY, val)
-#define bfin_read_MDMA2_DEST_CURR_DESC_PTR() bfin_read32(MDMA2_DEST_CURR_DESC_PTR)
-#define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_PREV_DESC_PTR() bfin_read32(MDMA2_DEST_PREV_DESC_PTR)
-#define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_CURR_ADDR() bfin_read32(MDMA2_DEST_CURR_ADDR)
-#define bfin_write_MDMA2_DEST_CURR_ADDR(val) bfin_write32(MDMA2_DEST_CURR_ADDR, val)
-#define bfin_read_MDMA2_DEST_IRQ_STATUS() bfin_read32(MDMA2_DEST_IRQ_STATUS)
-#define bfin_write_MDMA2_DEST_IRQ_STATUS(val) bfin_write32(MDMA2_DEST_IRQ_STATUS, val)
-#define bfin_read_MDMA2_DEST_CURR_X_COUNT() bfin_read32(MDMA2_DEST_CURR_X_COUNT)
-#define bfin_write_MDMA2_DEST_CURR_X_COUNT(val) bfin_write32(MDMA2_DEST_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_DEST_CURR_Y_COUNT() bfin_read32(MDMA2_DEST_CURR_Y_COUNT)
-#define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() bfin_read32(MDMA2_SRC_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_START_ADDR() bfin_read32(MDMA2_SRC_START_ADDR)
-#define bfin_write_MDMA2_SRC_START_ADDR(val) bfin_write32(MDMA2_SRC_START_ADDR, val)
-#define bfin_read_MDMA2_SRC_CONFIG() bfin_read32(MDMA2_SRC_CONFIG)
-#define bfin_write_MDMA2_SRC_CONFIG(val) bfin_write32(MDMA2_SRC_CONFIG, val)
-#define bfin_read_MDMA2_SRC_X_COUNT() bfin_read32(MDMA2_SRC_X_COUNT)
-#define bfin_write_MDMA2_SRC_X_COUNT(val) bfin_write32(MDMA2_SRC_X_COUNT, val)
-#define bfin_read_MDMA2_SRC_X_MODIFY() bfin_read32(MDMA2_SRC_X_MODIFY)
-#define bfin_write_MDMA2_SRC_X_MODIFY(val) bfin_write32(MDMA2_SRC_X_MODIFY, val)
-#define bfin_read_MDMA2_SRC_Y_COUNT() bfin_read32(MDMA2_SRC_Y_COUNT)
-#define bfin_write_MDMA2_SRC_Y_COUNT(val) bfin_write32(MDMA2_SRC_Y_COUNT, val)
-#define bfin_read_MDMA2_SRC_Y_MODIFY() bfin_read32(MDMA2_SRC_Y_MODIFY)
-#define bfin_write_MDMA2_SRC_Y_MODIFY(val) bfin_write32(MDMA2_SRC_Y_MODIFY, val)
-#define bfin_read_MDMA2_SRC_CURR_DESC_PTR() bfin_read32(MDMA2_SRC_CURR_DESC_PTR)
-#define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_PREV_DESC_PTR() bfin_read32(MDMA2_SRC_PREV_DESC_PTR)
-#define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_CURR_ADDR() bfin_read32(MDMA2_SRC_CURR_ADDR)
-#define bfin_write_MDMA2_SRC_CURR_ADDR(val) bfin_write32(MDMA2_SRC_CURR_ADDR, val)
-#define bfin_read_MDMA2_SRC_IRQ_STATUS() bfin_read32(MDMA2_SRC_IRQ_STATUS)
-#define bfin_write_MDMA2_SRC_IRQ_STATUS(val) bfin_write32(MDMA2_SRC_IRQ_STATUS, val)
-#define bfin_read_MDMA2_SRC_CURR_X_COUNT() bfin_read32(MDMA2_SRC_CURR_X_COUNT)
-#define bfin_write_MDMA2_SRC_CURR_X_COUNT(val) bfin_write32(MDMA2_SRC_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_SRC_CURR_Y_COUNT() bfin_read32(MDMA2_SRC_CURR_Y_COUNT)
-#define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers (DMA Channel 27 and 28) */
-
-#define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() bfin_read32(MDMA3_DEST_NEXT_DESC_PTR)
-#define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_START_ADDR() bfin_read32(MDMA3_DEST_START_ADDR)
-#define bfin_write_MDMA3_DEST_START_ADDR(val) bfin_write32(MDMA3_DEST_START_ADDR, val)
-#define bfin_read_MDMA3_DEST_CONFIG() bfin_read32(MDMA3_DEST_CONFIG)
-#define bfin_write_MDMA3_DEST_CONFIG(val) bfin_write32(MDMA3_DEST_CONFIG, val)
-#define bfin_read_MDMA3_DEST_X_COUNT() bfin_read32(MDMA3_DEST_X_COUNT)
-#define bfin_write_MDMA3_DEST_X_COUNT(val) bfin_write32(MDMA3_DEST_X_COUNT, val)
-#define bfin_read_MDMA3_DEST_X_MODIFY() bfin_read32(MDMA3_DEST_X_MODIFY)
-#define bfin_write_MDMA3_DEST_X_MODIFY(val) bfin_write32(MDMA3_DEST_X_MODIFY, val)
-#define bfin_read_MDMA3_DEST_Y_COUNT() bfin_read32(MDMA3_DEST_Y_COUNT)
-#define bfin_write_MDMA3_DEST_Y_COUNT(val) bfin_write32(MDMA3_DEST_Y_COUNT, val)
-#define bfin_read_MDMA3_DEST_Y_MODIFY() bfin_read32(MDMA3_DEST_Y_MODIFY)
-#define bfin_write_MDMA3_DEST_Y_MODIFY(val) bfin_write32(MDMA3_DEST_Y_MODIFY, val)
-#define bfin_read_MDMA3_DEST_CURR_DESC_PTR() bfin_read32(MDMA3_DEST_CURR_DESC_PTR)
-#define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_PREV_DESC_PTR() bfin_read32(MDMA3_DEST_PREV_DESC_PTR)
-#define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_CURR_ADDR() bfin_read32(MDMA3_DEST_CURR_ADDR)
-#define bfin_write_MDMA3_DEST_CURR_ADDR(val) bfin_write32(MDMA3_DEST_CURR_ADDR, val)
-#define bfin_read_MDMA3_DEST_IRQ_STATUS() bfin_read32(MDMA3_DEST_IRQ_STATUS)
-#define bfin_write_MDMA3_DEST_IRQ_STATUS(val) bfin_write32(MDMA3_DEST_IRQ_STATUS, val)
-#define bfin_read_MDMA3_DEST_CURR_X_COUNT() bfin_read32(MDMA3_DEST_CURR_X_COUNT)
-#define bfin_write_MDMA3_DEST_CURR_X_COUNT(val) bfin_write32(MDMA3_DEST_CURR_X_COUNT, val)
-#define bfin_read_MDMA3_DEST_CURR_Y_COUNT() bfin_read32(MDMA3_DEST_CURR_Y_COUNT)
-#define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val)
-#define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() bfin_read32(MDMA3_SRC_NEXT_DESC_PTR)
-#define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_START_ADDR() bfin_read32(MDMA3_SRC_START_ADDR)
-#define bfin_write_MDMA3_SRC_START_ADDR(val) bfin_write32(MDMA3_SRC_START_ADDR, val)
-#define bfin_read_MDMA3_SRC_CONFIG() bfin_read32(MDMA3_SRC_CONFIG)
-#define bfin_write_MDMA3_SRC_CONFIG(val) bfin_write32(MDMA3_SRC_CONFIG, val)
-#define bfin_read_MDMA3_SRC_X_COUNT() bfin_read32(MDMA3_SRC_X_COUNT)
-#define bfin_write_MDMA3_SRC_X_COUNT(val) bfin_write32(MDMA3_SRC_X_COUNT, val)
-#define bfin_read_MDMA3_SRC_X_MODIFY() bfin_read32(MDMA3_SRC_X_MODIFY)
-#define bfin_write_MDMA3_SRC_X_MODIFY(val) bfin_write32(MDMA3_SRC_X_MODIFY, val)
-#define bfin_read_MDMA3_SRC_Y_COUNT() bfin_read32(MDMA3_SRC_Y_COUNT)
-#define bfin_write_MDMA3_SRC_Y_COUNT(val) bfin_write32(MDMA3_SRC_Y_COUNT, val)
-#define bfin_read_MDMA3_SRC_Y_MODIFY() bfin_read32(MDMA3_SRC_Y_MODIFY)
-#define bfin_write_MDMA3_SRC_Y_MODIFY(val) bfin_write32(MDMA3_SRC_Y_MODIFY, val)
-#define bfin_read_MDMA3_SRC_CURR_DESC_PTR() bfin_read32(MDMA3_SRC_CURR_DESC_PTR)
-#define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_PREV_DESC_PTR() bfin_read32(MDMA3_SRC_PREV_DESC_PTR)
-#define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_CURR_ADDR() bfin_read32(MDMA3_SRC_CURR_ADDR)
-#define bfin_write_MDMA3_SRC_CURR_ADDR(val) bfin_write32(MDMA3_SRC_CURR_ADDR, val)
-#define bfin_read_MDMA3_SRC_IRQ_STATUS() bfin_read32(MDMA3_SRC_IRQ_STATUS)
-#define bfin_write_MDMA3_SRC_IRQ_STATUS(val) bfin_write32(MDMA3_SRC_IRQ_STATUS, val)
-#define bfin_read_MDMA3_SRC_CURR_X_COUNT() bfin_read32(MDMA3_SRC_CURR_X_COUNT)
-#define bfin_write_MDMA3_SRC_CURR_X_COUNT(val) bfin_write32(MDMA3_SRC_CURR_X_COUNT, val)
-#define bfin_read_MDMA3_SRC_CURR_Y_COUNT() bfin_read32(MDMA3_SRC_CURR_Y_COUNT)
-#define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val)
-
-
-/* DMA Channel 29 Registers */
-
-#define bfin_read_DMA29_NEXT_DESC_PTR() bfin_read32(DMA29_NEXT_DESC_PTR)
-#define bfin_write_DMA29_NEXT_DESC_PTR(val) bfin_write32(DMA29_NEXT_DESC_PTR, val)
-#define bfin_read_DMA29_START_ADDR() bfin_read32(DMA29_START_ADDR)
-#define bfin_write_DMA29_START_ADDR(val) bfin_write32(DMA29_START_ADDR, val)
-#define bfin_read_DMA29_CONFIG() bfin_read32(DMA29_CONFIG)
-#define bfin_write_DMA29_CONFIG(val) bfin_write32(DMA29_CONFIG, val)
-#define bfin_read_DMA29_X_COUNT() bfin_read32(DMA29_X_COUNT)
-#define bfin_write_DMA29_X_COUNT(val) bfin_write32(DMA29_X_COUNT, val)
-#define bfin_read_DMA29_X_MODIFY() bfin_read32(DMA29_X_MODIFY)
-#define bfin_write_DMA29_X_MODIFY(val) bfin_write32(DMA29_X_MODIFY, val)
-#define bfin_read_DMA29_Y_COUNT() bfin_read32(DMA29_Y_COUNT)
-#define bfin_write_DMA29_Y_COUNT(val) bfin_write32(DMA29_Y_COUNT, val)
-#define bfin_read_DMA29_Y_MODIFY() bfin_read32(DMA29_Y_MODIFY)
-#define bfin_write_DMA29_Y_MODIFY(val) bfin_write32(DMA29_Y_MODIFY, val)
-#define bfin_read_DMA29_CURR_DESC_PTR() bfin_read32(DMA29_CURR_DESC_PTR)
-#define bfin_write_DMA29_CURR_DESC_PTR(val) bfin_write32(DMA29_CURR_DESC_PTR, val)
-#define bfin_read_DMA29_PREV_DESC_PTR() bfin_read32(DMA29_PREV_DESC_PTR)
-#define bfin_write_DMA29_PREV_DESC_PTR(val) bfin_write32(DMA29_PREV_DESC_PTR, val)
-#define bfin_read_DMA29_CURR_ADDR() bfin_read32(DMA29_CURR_ADDR)
-#define bfin_write_DMA29_CURR_ADDR(val) bfin_write32(DMA29_CURR_ADDR, val)
-#define bfin_read_DMA29_IRQ_STATUS() bfin_read32(DMA29_IRQ_STATUS)
-#define bfin_write_DMA29_IRQ_STATUS(val) bfin_write32(DMA29_IRQ_STATUS, val)
-#define bfin_read_DMA29_CURR_X_COUNT() bfin_read32(DMA29_CURR_X_COUNT)
-#define bfin_write_DMA29_CURR_X_COUNT(val) bfin_write32(DMA29_CURR_X_COUNT, val)
-#define bfin_read_DMA29_CURR_Y_COUNT() bfin_read32(DMA29_CURR_Y_COUNT)
-#define bfin_write_DMA29_CURR_Y_COUNT(val) bfin_write32(DMA29_CURR_Y_COUNT, val)
-#define bfin_read_DMA29_BWL_COUNT() bfin_read32(DMA29_BWL_COUNT)
-#define bfin_write_DMA29_BWL_COUNT(val) bfin_write32(DMA29_BWL_COUNT, val)
-#define bfin_read_DMA29_CURR_BWL_COUNT() bfin_read32(DMA29_CURR_BWL_COUNT)
-#define bfin_write_DMA29_CURR_BWL_COUNT(val) bfin_write32(DMA29_CURR_BWL_COUNT, val)
-#define bfin_read_DMA29_BWM_COUNT() bfin_read32(DMA29_BWM_COUNT)
-#define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val)
-#define bfin_read_DMA29_CURR_BWM_COUNT() bfin_read32(DMA29_CURR_BWM_COUNT)
-#define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val)
-
-/* DMA Channel 30 Registers */
-
-#define bfin_read_DMA30_NEXT_DESC_PTR() bfin_read32(DMA30_NEXT_DESC_PTR)
-#define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val)
-#define bfin_read_DMA30_START_ADDR() bfin_read32(DMA30_START_ADDR)
-#define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val)
-#define bfin_read_DMA30_CONFIG() bfin_read32(DMA30_CONFIG)
-#define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val)
-#define bfin_read_DMA30_X_COUNT() bfin_read32(DMA30_X_COUNT)
-#define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val)
-#define bfin_read_DMA30_X_MODIFY() bfin_read32(DMA30_X_MODIFY)
-#define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val)
-#define bfin_read_DMA30_Y_COUNT() bfin_read32(DMA30_Y_COUNT)
-#define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val)
-#define bfin_read_DMA30_Y_MODIFY() bfin_read32(DMA30_Y_MODIFY)
-#define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val)
-#define bfin_read_DMA30_CURR_DESC_PTR() bfin_read32(DMA30_CURR_DESC_PTR)
-#define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val)
-#define bfin_read_DMA30_PREV_DESC_PTR() bfin_read32(DMA30_PREV_DESC_PTR)
-#define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val)
-#define bfin_read_DMA30_CURR_ADDR() bfin_read32(DMA30_CURR_ADDR)
-#define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val)
-#define bfin_read_DMA30_IRQ_STATUS() bfin_read32(DMA30_IRQ_STATUS)
-#define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val)
-#define bfin_read_DMA30_CURR_X_COUNT() bfin_read32(DMA30_CURR_X_COUNT)
-#define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val)
-#define bfin_read_DMA30_CURR_Y_COUNT() bfin_read32(DMA30_CURR_Y_COUNT)
-#define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val)
-#define bfin_read_DMA30_BWL_COUNT() bfin_read32(DMA30_BWL_COUNT)
-#define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val)
-#define bfin_read_DMA30_CURR_BWL_COUNT() bfin_read32(DMA30_CURR_BWL_COUNT)
-#define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val)
-#define bfin_read_DMA30_BWM_COUNT() bfin_read32(DMA30_BWM_COUNT)
-#define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val)
-#define bfin_read_DMA30_CURR_BWM_COUNT() bfin_read32(DMA30_CURR_BWM_COUNT)
-#define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val)
-
-/* DMA Channel 31 Registers */
-
-#define bfin_read_DMA31_NEXT_DESC_PTR() bfin_read32(DMA31_NEXT_DESC_PTR)
-#define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val)
-#define bfin_read_DMA31_START_ADDR() bfin_read32(DMA31_START_ADDR)
-#define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val)
-#define bfin_read_DMA31_CONFIG() bfin_read32(DMA31_CONFIG)
-#define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val)
-#define bfin_read_DMA31_X_COUNT() bfin_read32(DMA31_X_COUNT)
-#define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val)
-#define bfin_read_DMA31_X_MODIFY() bfin_read32(DMA31_X_MODIFY)
-#define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val)
-#define bfin_read_DMA31_Y_COUNT() bfin_read32(DMA31_Y_COUNT)
-#define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val)
-#define bfin_read_DMA31_Y_MODIFY() bfin_read32(DMA31_Y_MODIFY)
-#define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val)
-#define bfin_read_DMA31_CURR_DESC_PTR() bfin_read32(DMA31_CURR_DESC_PTR)
-#define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val)
-#define bfin_read_DMA31_PREV_DESC_PTR() bfin_read32(DMA31_PREV_DESC_PTR)
-#define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val)
-#define bfin_read_DMA31_CURR_ADDR() bfin_read32(DMA31_CURR_ADDR)
-#define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val)
-#define bfin_read_DMA31_IRQ_STATUS() bfin_read32(DMA31_IRQ_STATUS)
-#define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val)
-#define bfin_read_DMA31_CURR_X_COUNT() bfin_read32(DMA31_CURR_X_COUNT)
-#define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val)
-#define bfin_read_DMA31_CURR_Y_COUNT() bfin_read32(DMA31_CURR_Y_COUNT)
-#define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val)
-#define bfin_read_DMA31_BWL_COUNT() bfin_read32(DMA31_BWL_COUNT)
-#define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val)
-#define bfin_read_DMA31_CURR_BWL_COUNT() bfin_read32(DMA31_CURR_BWL_COUNT)
-#define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val)
-#define bfin_read_DMA31_BWM_COUNT() bfin_read32(DMA31_BWM_COUNT)
-#define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val)
-#define bfin_read_DMA31_CURR_BWM_COUNT() bfin_read32(DMA31_CURR_BWM_COUNT)
-#define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val)
-
-/* DMA Channel 32 Registers */
-
-#define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR)
-#define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val)
-#define bfin_read_DMA32_START_ADDR() bfin_read32(DMA32_START_ADDR)
-#define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val)
-#define bfin_read_DMA32_CONFIG() bfin_read32(DMA32_CONFIG)
-#define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val)
-#define bfin_read_DMA32_X_COUNT() bfin_read32(DMA32_X_COUNT)
-#define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val)
-#define bfin_read_DMA32_X_MODIFY() bfin_read32(DMA32_X_MODIFY)
-#define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val)
-#define bfin_read_DMA32_Y_COUNT() bfin_read32(DMA32_Y_COUNT)
-#define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val)
-#define bfin_read_DMA32_Y_MODIFY() bfin_read32(DMA32_Y_MODIFY)
-#define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val)
-#define bfin_read_DMA32_CURR_DESC_PTR() bfin_read32(DMA32_CURR_DESC_PTR)
-#define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val)
-#define bfin_read_DMA32_PREV_DESC_PTR() bfin_read32(DMA32_PREV_DESC_PTR)
-#define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val)
-#define bfin_read_DMA32_CURR_ADDR() bfin_read32(DMA32_CURR_ADDR)
-#define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val)
-#define bfin_read_DMA32_IRQ_STATUS() bfin_read32(DMA32_IRQ_STATUS)
-#define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val)
-#define bfin_read_DMA32_CURR_X_COUNT() bfin_read32(DMA32_CURR_X_COUNT)
-#define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val)
-#define bfin_read_DMA32_CURR_Y_COUNT() bfin_read32(DMA32_CURR_Y_COUNT)
-#define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val)
-#define bfin_read_DMA32_BWL_COUNT() bfin_read32(DMA32_BWL_COUNT)
-#define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val)
-#define bfin_read_DMA32_CURR_BWL_COUNT() bfin_read32(DMA32_CURR_BWL_COUNT)
-#define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val)
-#define bfin_read_DMA32_BWM_COUNT() bfin_read32(DMA32_BWM_COUNT)
-#define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val)
-#define bfin_read_DMA32_CURR_BWM_COUNT() bfin_read32(DMA32_CURR_BWM_COUNT)
-#define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val)
-
-/* DMA Channel 33 Registers */
-
-#define bfin_read_DMA33_NEXT_DESC_PTR() bfin_read32(DMA33_NEXT_DESC_PTR)
-#define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val)
-#define bfin_read_DMA33_START_ADDR() bfin_read32(DMA33_START_ADDR)
-#define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val)
-#define bfin_read_DMA33_CONFIG() bfin_read32(DMA33_CONFIG)
-#define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val)
-#define bfin_read_DMA33_X_COUNT() bfin_read32(DMA33_X_COUNT)
-#define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val)
-#define bfin_read_DMA33_X_MODIFY() bfin_read32(DMA33_X_MODIFY)
-#define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val)
-#define bfin_read_DMA33_Y_COUNT() bfin_read32(DMA33_Y_COUNT)
-#define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val)
-#define bfin_read_DMA33_Y_MODIFY() bfin_read32(DMA33_Y_MODIFY)
-#define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val)
-#define bfin_read_DMA33_CURR_DESC_PTR() bfin_read32(DMA33_CURR_DESC_PTR)
-#define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val)
-#define bfin_read_DMA33_PREV_DESC_PTR() bfin_read32(DMA33_PREV_DESC_PTR)
-#define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val)
-#define bfin_read_DMA33_CURR_ADDR() bfin_read32(DMA33_CURR_ADDR)
-#define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val)
-#define bfin_read_DMA33_IRQ_STATUS() bfin_read32(DMA33_IRQ_STATUS)
-#define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val)
-#define bfin_read_DMA33_CURR_X_COUNT() bfin_read32(DMA33_CURR_X_COUNT)
-#define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val)
-#define bfin_read_DMA33_CURR_Y_COUNT() bfin_read32(DMA33_CURR_Y_COUNT)
-#define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val)
-#define bfin_read_DMA33_BWL_COUNT() bfin_read32(DMA33_BWL_COUNT)
-#define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val)
-#define bfin_read_DMA33_CURR_BWL_COUNT() bfin_read32(DMA33_CURR_BWL_COUNT)
-#define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val)
-#define bfin_read_DMA33_BWM_COUNT() bfin_read32(DMA33_BWM_COUNT)
-#define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val)
-#define bfin_read_DMA33_CURR_BWM_COUNT() bfin_read32(DMA33_CURR_BWM_COUNT)
-#define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val)
-
-/* DMA Channel 34 Registers */
-
-#define bfin_read_DMA34_NEXT_DESC_PTR() bfin_read32(DMA34_NEXT_DESC_PTR)
-#define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val)
-#define bfin_read_DMA34_START_ADDR() bfin_read32(DMA34_START_ADDR)
-#define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val)
-#define bfin_read_DMA34_CONFIG() bfin_read32(DMA34_CONFIG)
-#define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val)
-#define bfin_read_DMA34_X_COUNT() bfin_read32(DMA34_X_COUNT)
-#define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val)
-#define bfin_read_DMA34_X_MODIFY() bfin_read32(DMA34_X_MODIFY)
-#define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val)
-#define bfin_read_DMA34_Y_COUNT() bfin_read32(DMA34_Y_COUNT)
-#define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val)
-#define bfin_read_DMA34_Y_MODIFY() bfin_read32(DMA34_Y_MODIFY)
-#define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val)
-#define bfin_read_DMA34_CURR_DESC_PTR() bfin_read32(DMA34_CURR_DESC_PTR)
-#define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val)
-#define bfin_read_DMA34_PREV_DESC_PTR() bfin_read32(DMA34_PREV_DESC_PTR)
-#define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val)
-#define bfin_read_DMA34_CURR_ADDR() bfin_read32(DMA34_CURR_ADDR)
-#define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val)
-#define bfin_read_DMA34_IRQ_STATUS() bfin_read32(DMA34_IRQ_STATUS)
-#define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val)
-#define bfin_read_DMA34_CURR_X_COUNT() bfin_read32(DMA34_CURR_X_COUNT)
-#define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val)
-#define bfin_read_DMA34_CURR_Y_COUNT() bfin_read32(DMA34_CURR_Y_COUNT)
-#define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val)
-#define bfin_read_DMA34_BWL_COUNT() bfin_read32(DMA34_BWL_COUNT)
-#define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val)
-#define bfin_read_DMA34_CURR_BWL_COUNT() bfin_read32(DMA34_CURR_BWL_COUNT)
-#define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val)
-#define bfin_read_DMA34_BWM_COUNT() bfin_read32(DMA34_BWM_COUNT)
-#define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val)
-#define bfin_read_DMA34_CURR_BWM_COUNT() bfin_read32(DMA34_CURR_BWM_COUNT)
-#define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val)
-
-/* DMA Channel 35 Registers */
-
-#define bfin_read_DMA35_NEXT_DESC_PTR() bfin_read32(DMA35_NEXT_DESC_PTR)
-#define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val)
-#define bfin_read_DMA35_START_ADDR() bfin_read32(DMA35_START_ADDR)
-#define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val)
-#define bfin_read_DMA35_CONFIG() bfin_read32(DMA35_CONFIG)
-#define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val)
-#define bfin_read_DMA35_X_COUNT() bfin_read32(DMA35_X_COUNT)
-#define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val)
-#define bfin_read_DMA35_X_MODIFY() bfin_read32(DMA35_X_MODIFY)
-#define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val)
-#define bfin_read_DMA35_Y_COUNT() bfin_read32(DMA35_Y_COUNT)
-#define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val)
-#define bfin_read_DMA35_Y_MODIFY() bfin_read32(DMA35_Y_MODIFY)
-#define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val)
-#define bfin_read_DMA35_CURR_DESC_PTR() bfin_read32(DMA35_CURR_DESC_PTR)
-#define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val)
-#define bfin_read_DMA35_PREV_DESC_PTR() bfin_read32(DMA35_PREV_DESC_PTR)
-#define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val)
-#define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR)
-#define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val)
-#define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS)
-#define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val)
-#define bfin_read_DMA35_CURR_X_COUNT() bfin_read32(DMA35_CURR_X_COUNT)
-#define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val)
-#define bfin_read_DMA35_CURR_Y_COUNT() bfin_read32(DMA35_CURR_Y_COUNT)
-#define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val)
-#define bfin_read_DMA35_BWL_COUNT() bfin_read32(DMA35_BWL_COUNT)
-#define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val)
-#define bfin_read_DMA35_CURR_BWL_COUNT() bfin_read32(DMA35_CURR_BWL_COUNT)
-#define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val)
-#define bfin_read_DMA35_BWM_COUNT() bfin_read32(DMA35_BWM_COUNT)
-#define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val)
-#define bfin_read_DMA35_CURR_BWM_COUNT() bfin_read32(DMA35_CURR_BWM_COUNT)
-#define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val)
-
-/* DMA Channel 36 Registers */
-
-#define bfin_read_DMA36_NEXT_DESC_PTR() bfin_read32(DMA36_NEXT_DESC_PTR)
-#define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val)
-#define bfin_read_DMA36_START_ADDR() bfin_read32(DMA36_START_ADDR)
-#define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val)
-#define bfin_read_DMA36_CONFIG() bfin_read32(DMA36_CONFIG)
-#define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val)
-#define bfin_read_DMA36_X_COUNT() bfin_read32(DMA36_X_COUNT)
-#define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val)
-#define bfin_read_DMA36_X_MODIFY() bfin_read32(DMA36_X_MODIFY)
-#define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val)
-#define bfin_read_DMA36_Y_COUNT() bfin_read32(DMA36_Y_COUNT)
-#define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val)
-#define bfin_read_DMA36_Y_MODIFY() bfin_read32(DMA36_Y_MODIFY)
-#define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val)
-#define bfin_read_DMA36_CURR_DESC_PTR() bfin_read32(DMA36_CURR_DESC_PTR)
-#define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val)
-#define bfin_read_DMA36_PREV_DESC_PTR() bfin_read32(DMA36_PREV_DESC_PTR)
-#define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val)
-#define bfin_read_DMA36_CURR_ADDR() bfin_read32(DMA36_CURR_ADDR)
-#define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val)
-#define bfin_read_DMA36_IRQ_STATUS() bfin_read32(DMA36_IRQ_STATUS)
-#define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val)
-#define bfin_read_DMA36_CURR_X_COUNT() bfin_read32(DMA36_CURR_X_COUNT)
-#define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val)
-#define bfin_read_DMA36_CURR_Y_COUNT() bfin_read32(DMA36_CURR_Y_COUNT)
-#define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val)
-#define bfin_read_DMA36_BWL_COUNT() bfin_read32(DMA36_BWL_COUNT)
-#define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val)
-#define bfin_read_DMA36_CURR_BWL_COUNT() bfin_read32(DMA36_CURR_BWL_COUNT)
-#define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val)
-#define bfin_read_DMA36_BWM_COUNT() bfin_read32(DMA36_BWM_COUNT)
-#define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val)
-#define bfin_read_DMA36_CURR_BWM_COUNT() bfin_read32(DMA36_CURR_BWM_COUNT)
-#define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val)
-
-/* DMA Channel 37 Registers */
-
-#define bfin_read_DMA37_NEXT_DESC_PTR() bfin_read32(DMA37_NEXT_DESC_PTR)
-#define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val)
-#define bfin_read_DMA37_START_ADDR() bfin_read32(DMA37_START_ADDR)
-#define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val)
-#define bfin_read_DMA37_CONFIG() bfin_read32(DMA37_CONFIG)
-#define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val)
-#define bfin_read_DMA37_X_COUNT() bfin_read32(DMA37_X_COUNT)
-#define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val)
-#define bfin_read_DMA37_X_MODIFY() bfin_read32(DMA37_X_MODIFY)
-#define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val)
-#define bfin_read_DMA37_Y_COUNT() bfin_read32(DMA37_Y_COUNT)
-#define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val)
-#define bfin_read_DMA37_Y_MODIFY() bfin_read32(DMA37_Y_MODIFY)
-#define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val)
-#define bfin_read_DMA37_CURR_DESC_PTR() bfin_read32(DMA37_CURR_DESC_PTR)
-#define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val)
-#define bfin_read_DMA37_PREV_DESC_PTR() bfin_read32(DMA37_PREV_DESC_PTR)
-#define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val)
-#define bfin_read_DMA37_CURR_ADDR() bfin_read32(DMA37_CURR_ADDR)
-#define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val)
-#define bfin_read_DMA37_IRQ_STATUS() bfin_read32(DMA37_IRQ_STATUS)
-#define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val)
-#define bfin_read_DMA37_CURR_X_COUNT() bfin_read32(DMA37_CURR_X_COUNT)
-#define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val)
-#define bfin_read_DMA37_CURR_Y_COUNT() bfin_read32(DMA37_CURR_Y_COUNT)
-#define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val)
-#define bfin_read_DMA37_BWL_COUNT() bfin_read32(DMA37_BWL_COUNT)
-#define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val)
-#define bfin_read_DMA37_CURR_BWL_COUNT() bfin_read32(DMA37_CURR_BWL_COUNT)
-#define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val)
-#define bfin_read_DMA37_BWM_COUNT() bfin_read32(DMA37_BWM_COUNT)
-#define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val)
-#define bfin_read_DMA37_CURR_BWM_COUNT() bfin_read32(DMA37_CURR_BWM_COUNT)
-#define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val)
-
-/* DMA Channel 38 Registers */
-
-#define bfin_read_DMA38_NEXT_DESC_PTR() bfin_read32(DMA38_NEXT_DESC_PTR)
-#define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val)
-#define bfin_read_DMA38_START_ADDR() bfin_read32(DMA38_START_ADDR)
-#define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val)
-#define bfin_read_DMA38_CONFIG() bfin_read32(DMA38_CONFIG)
-#define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val)
-#define bfin_read_DMA38_X_COUNT() bfin_read32(DMA38_X_COUNT)
-#define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val)
-#define bfin_read_DMA38_X_MODIFY() bfin_read32(DMA38_X_MODIFY)
-#define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val)
-#define bfin_read_DMA38_Y_COUNT() bfin_read32(DMA38_Y_COUNT)
-#define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val)
-#define bfin_read_DMA38_Y_MODIFY() bfin_read32(DMA38_Y_MODIFY)
-#define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val)
-#define bfin_read_DMA38_CURR_DESC_PTR() bfin_read32(DMA38_CURR_DESC_PTR)
-#define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val)
-#define bfin_read_DMA38_PREV_DESC_PTR() bfin_read32(DMA38_PREV_DESC_PTR)
-#define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val)
-#define bfin_read_DMA38_CURR_ADDR() bfin_read32(DMA38_CURR_ADDR)
-#define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val)
-#define bfin_read_DMA38_IRQ_STATUS() bfin_read32(DMA38_IRQ_STATUS)
-#define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val)
-#define bfin_read_DMA38_CURR_X_COUNT() bfin_read32(DMA38_CURR_X_COUNT)
-#define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val)
-#define bfin_read_DMA38_CURR_Y_COUNT() bfin_read32(DMA38_CURR_Y_COUNT)
-#define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val)
-#define bfin_read_DMA38_BWL_COUNT() bfin_read32(DMA38_BWL_COUNT)
-#define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val)
-#define bfin_read_DMA38_CURR_BWL_COUNT() bfin_read32(DMA38_CURR_BWL_COUNT)
-#define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val)
-#define bfin_read_DMA38_BWM_COUNT() bfin_read32(DMA38_BWM_COUNT)
-#define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val)
-#define bfin_read_DMA38_CURR_BWM_COUNT() bfin_read32(DMA38_CURR_BWM_COUNT)
-#define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val)
-
-/* DMA Channel 39 Registers */
-
-#define bfin_read_DMA39_NEXT_DESC_PTR() bfin_read32(DMA39_NEXT_DESC_PTR)
-#define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val)
-#define bfin_read_DMA39_START_ADDR() bfin_read32(DMA39_START_ADDR)
-#define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val)
-#define bfin_read_DMA39_CONFIG() bfin_read32(DMA39_CONFIG)
-#define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val)
-#define bfin_read_DMA39_X_COUNT() bfin_read32(DMA39_X_COUNT)
-#define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val)
-#define bfin_read_DMA39_X_MODIFY() bfin_read32(DMA39_X_MODIFY)
-#define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val)
-#define bfin_read_DMA39_Y_COUNT() bfin_read32(DMA39_Y_COUNT)
-#define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val)
-#define bfin_read_DMA39_Y_MODIFY() bfin_read32(DMA39_Y_MODIFY)
-#define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val)
-#define bfin_read_DMA39_CURR_DESC_PTR() bfin_read32(DMA39_CURR_DESC_PTR)
-#define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val)
-#define bfin_read_DMA39_PREV_DESC_PTR() bfin_read32(DMA39_PREV_DESC_PTR)
-#define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val)
-#define bfin_read_DMA39_CURR_ADDR() bfin_read32(DMA39_CURR_ADDR)
-#define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val)
-#define bfin_read_DMA39_IRQ_STATUS() bfin_read32(DMA39_IRQ_STATUS)
-#define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val)
-#define bfin_read_DMA39_CURR_X_COUNT() bfin_read32(DMA39_CURR_X_COUNT)
-#define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val)
-#define bfin_read_DMA39_CURR_Y_COUNT() bfin_read32(DMA39_CURR_Y_COUNT)
-#define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val)
-#define bfin_read_DMA39_BWL_COUNT() bfin_read32(DMA39_BWL_COUNT)
-#define bfin_write_DMA39_BWL_COUNT(val) bfin_write32(DMA39_BWL_COUNT, val)
-#define bfin_read_DMA39_CURR_BWL_COUNT() bfin_read32(DMA39_CURR_BWL_COUNT)
-#define bfin_write_DMA39_CURR_BWL_COUNT(val) bfin_write32(DMA39_CURR_BWL_COUNT, val)
-#define bfin_read_DMA39_BWM_COUNT() bfin_read32(DMA39_BWM_COUNT)
-#define bfin_write_DMA39_BWM_COUNT(val) bfin_write32(DMA39_BWM_COUNT, val)
-#define bfin_read_DMA39_CURR_BWM_COUNT() bfin_read32(DMA39_CURR_BWM_COUNT)
-#define bfin_write_DMA39_CURR_BWM_COUNT(val) bfin_write32(DMA39_CURR_BWM_COUNT, val)
-
-/* DMA Channel 40 Registers */
-
-#define bfin_read_DMA40_NEXT_DESC_PTR() bfin_read32(DMA40_NEXT_DESC_PTR)
-#define bfin_write_DMA40_NEXT_DESC_PTR(val) bfin_write32(DMA40_NEXT_DESC_PTR, val)
-#define bfin_read_DMA40_START_ADDR() bfin_read32(DMA40_START_ADDR)
-#define bfin_write_DMA40_START_ADDR(val) bfin_write32(DMA40_START_ADDR, val)
-#define bfin_read_DMA40_CONFIG() bfin_read32(DMA40_CONFIG)
-#define bfin_write_DMA40_CONFIG(val) bfin_write32(DMA40_CONFIG, val)
-#define bfin_read_DMA40_X_COUNT() bfin_read32(DMA40_X_COUNT)
-#define bfin_write_DMA40_X_COUNT(val) bfin_write32(DMA40_X_COUNT, val)
-#define bfin_read_DMA40_X_MODIFY() bfin_read32(DMA40_X_MODIFY)
-#define bfin_write_DMA40_X_MODIFY(val) bfin_write32(DMA40_X_MODIFY, val)
-#define bfin_read_DMA40_Y_COUNT() bfin_read32(DMA40_Y_COUNT)
-#define bfin_write_DMA40_Y_COUNT(val) bfin_write32(DMA40_Y_COUNT, val)
-#define bfin_read_DMA40_Y_MODIFY() bfin_read32(DMA40_Y_MODIFY)
-#define bfin_write_DMA40_Y_MODIFY(val) bfin_write32(DMA40_Y_MODIFY, val)
-#define bfin_read_DMA40_CURR_DESC_PTR() bfin_read32(DMA40_CURR_DESC_PTR)
-#define bfin_write_DMA40_CURR_DESC_PTR(val) bfin_write32(DMA40_CURR_DESC_PTR, val)
-#define bfin_read_DMA40_PREV_DESC_PTR() bfin_read32(DMA40_PREV_DESC_PTR)
-#define bfin_write_DMA40_PREV_DESC_PTR(val) bfin_write32(DMA40_PREV_DESC_PTR, val)
-#define bfin_read_DMA40_CURR_ADDR() bfin_read32(DMA40_CURR_ADDR)
-#define bfin_write_DMA40_CURR_ADDR(val) bfin_write32(DMA40_CURR_ADDR, val)
-#define bfin_read_DMA40_IRQ_STATUS() bfin_read32(DMA40_IRQ_STATUS)
-#define bfin_write_DMA40_IRQ_STATUS(val) bfin_write32(DMA40_IRQ_STATUS, val)
-#define bfin_read_DMA40_CURR_X_COUNT() bfin_read32(DMA40_CURR_X_COUNT)
-#define bfin_write_DMA40_CURR_X_COUNT(val) bfin_write32(DMA40_CURR_X_COUNT, val)
-#define bfin_read_DMA40_CURR_Y_COUNT() bfin_read32(DMA40_CURR_Y_COUNT)
-#define bfin_write_DMA40_CURR_Y_COUNT(val) bfin_write32(DMA40_CURR_Y_COUNT, val)
-#define bfin_read_DMA40_BWL_COUNT() bfin_read32(DMA40_BWL_COUNT)
-#define bfin_write_DMA40_BWL_COUNT(val) bfin_write32(DMA40_BWL_COUNT, val)
-#define bfin_read_DMA40_CURR_BWL_COUNT() bfin_read32(DMA40_CURR_BWL_COUNT)
-#define bfin_write_DMA40_CURR_BWL_COUNT(val) bfin_write32(DMA40_CURR_BWL_COUNT, val)
-#define bfin_read_DMA40_BWM_COUNT() bfin_read32(DMA40_BWM_COUNT)
-#define bfin_write_DMA40_BWM_COUNT(val) bfin_write32(DMA40_BWM_COUNT, val)
-#define bfin_read_DMA40_CURR_BWM_COUNT() bfin_read32(DMA40_CURR_BWM_COUNT)
-#define bfin_write_DMA40_CURR_BWM_COUNT(val) bfin_write32(DMA40_CURR_BWM_COUNT, val)
-
-/* DMA Channel 41 Registers */
-
-#define bfin_read_DMA41_NEXT_DESC_PTR() bfin_read32(DMA41_NEXT_DESC_PTR)
-#define bfin_write_DMA41_NEXT_DESC_PTR(val) bfin_write32(DMA41_NEXT_DESC_PTR, val)
-#define bfin_read_DMA41_START_ADDR() bfin_read32(DMA41_START_ADDR)
-#define bfin_write_DMA41_START_ADDR(val) bfin_write32(DMA41_START_ADDR, val)
-#define bfin_read_DMA41_CONFIG() bfin_read32(DMA41_CONFIG)
-#define bfin_write_DMA41_CONFIG(val) bfin_write32(DMA41_CONFIG, val)
-#define bfin_read_DMA41_X_COUNT() bfin_read32(DMA41_X_COUNT)
-#define bfin_write_DMA41_X_COUNT(val) bfin_write32(DMA41_X_COUNT, val)
-#define bfin_read_DMA41_X_MODIFY() bfin_read32(DMA41_X_MODIFY)
-#define bfin_write_DMA41_X_MODIFY(val) bfin_write32(DMA41_X_MODIFY, val)
-#define bfin_read_DMA41_Y_COUNT() bfin_read32(DMA41_Y_COUNT)
-#define bfin_write_DMA41_Y_COUNT(val) bfin_write32(DMA41_Y_COUNT, val)
-#define bfin_read_DMA41_Y_MODIFY() bfin_read32(DMA41_Y_MODIFY)
-#define bfin_write_DMA41_Y_MODIFY(val) bfin_write32(DMA41_Y_MODIFY, val)
-#define bfin_read_DMA41_CURR_DESC_PTR() bfin_read32(DMA41_CURR_DESC_PTR)
-#define bfin_write_DMA41_CURR_DESC_PTR(val) bfin_write32(DMA41_CURR_DESC_PTR, val)
-#define bfin_read_DMA41_PREV_DESC_PTR() bfin_read32(DMA41_PREV_DESC_PTR)
-#define bfin_write_DMA41_PREV_DESC_PTR(val) bfin_write32(DMA41_PREV_DESC_PTR, val)
-#define bfin_read_DMA41_CURR_ADDR() bfin_read32(DMA41_CURR_ADDR)
-#define bfin_write_DMA41_CURR_ADDR(val) bfin_write32(DMA41_CURR_ADDR, val)
-#define bfin_read_DMA41_IRQ_STATUS() bfin_read32(DMA41_IRQ_STATUS)
-#define bfin_write_DMA41_IRQ_STATUS(val) bfin_write32(DMA41_IRQ_STATUS, val)
-#define bfin_read_DMA41_CURR_X_COUNT() bfin_read32(DMA41_CURR_X_COUNT)
-#define bfin_write_DMA41_CURR_X_COUNT(val) bfin_write32(DMA41_CURR_X_COUNT, val)
-#define bfin_read_DMA41_CURR_Y_COUNT() bfin_read32(DMA41_CURR_Y_COUNT)
-#define bfin_write_DMA41_CURR_Y_COUNT(val) bfin_write32(DMA41_CURR_Y_COUNT, val)
-#define bfin_read_DMA41_BWL_COUNT() bfin_read32(DMA41_BWL_COUNT)
-#define bfin_write_DMA41_BWL_COUNT(val) bfin_write32(DMA41_BWL_COUNT, val)
-#define bfin_read_DMA41_CURR_BWL_COUNT() bfin_read32(DMA41_CURR_BWL_COUNT)
-#define bfin_write_DMA41_CURR_BWL_COUNT(val) bfin_write32(DMA41_CURR_BWL_COUNT, val)
-#define bfin_read_DMA41_BWM_COUNT() bfin_read32(DMA41_BWM_COUNT)
-#define bfin_write_DMA41_BWM_COUNT(val) bfin_write32(DMA41_BWM_COUNT, val)
-#define bfin_read_DMA41_CURR_BWM_COUNT() bfin_read32(DMA41_CURR_BWM_COUNT)
-#define bfin_write_DMA41_CURR_BWM_COUNT(val) bfin_write32(DMA41_CURR_BWM_COUNT, val)
-
-/* DMA Channel 42 Registers */
-
-#define bfin_read_DMA42_NEXT_DESC_PTR() bfin_read32(DMA42_NEXT_DESC_PTR)
-#define bfin_write_DMA42_NEXT_DESC_PTR(val) bfin_write32(DMA42_NEXT_DESC_PTR, val)
-#define bfin_read_DMA42_START_ADDR() bfin_read32(DMA42_START_ADDR)
-#define bfin_write_DMA42_START_ADDR(val) bfin_write32(DMA42_START_ADDR, val)
-#define bfin_read_DMA42_CONFIG() bfin_read32(DMA42_CONFIG)
-#define bfin_write_DMA42_CONFIG(val) bfin_write32(DMA42_CONFIG, val)
-#define bfin_read_DMA42_X_COUNT() bfin_read32(DMA42_X_COUNT)
-#define bfin_write_DMA42_X_COUNT(val) bfin_write32(DMA42_X_COUNT, val)
-#define bfin_read_DMA42_X_MODIFY() bfin_read32(DMA42_X_MODIFY)
-#define bfin_write_DMA42_X_MODIFY(val) bfin_write32(DMA42_X_MODIFY, val)
-#define bfin_read_DMA42_Y_COUNT() bfin_read32(DMA42_Y_COUNT)
-#define bfin_write_DMA42_Y_COUNT(val) bfin_write32(DMA42_Y_COUNT, val)
-#define bfin_read_DMA42_Y_MODIFY() bfin_read32(DMA42_Y_MODIFY)
-#define bfin_write_DMA42_Y_MODIFY(val) bfin_write32(DMA42_Y_MODIFY, val)
-#define bfin_read_DMA42_CURR_DESC_PTR() bfin_read32(DMA42_CURR_DESC_PTR)
-#define bfin_write_DMA42_CURR_DESC_PTR(val) bfin_write32(DMA42_CURR_DESC_PTR, val)
-#define bfin_read_DMA42_PREV_DESC_PTR() bfin_read32(DMA42_PREV_DESC_PTR)
-#define bfin_write_DMA42_PREV_DESC_PTR(val) bfin_write32(DMA42_PREV_DESC_PTR, val)
-#define bfin_read_DMA42_CURR_ADDR() bfin_read32(DMA42_CURR_ADDR)
-#define bfin_write_DMA42_CURR_ADDR(val) bfin_write32(DMA42_CURR_ADDR, val)
-#define bfin_read_DMA42_IRQ_STATUS() bfin_read32(DMA42_IRQ_STATUS)
-#define bfin_write_DMA42_IRQ_STATUS(val) bfin_write32(DMA42_IRQ_STATUS, val)
-#define bfin_read_DMA42_CURR_X_COUNT() bfin_read32(DMA42_CURR_X_COUNT)
-#define bfin_write_DMA42_CURR_X_COUNT(val) bfin_write32(DMA42_CURR_X_COUNT, val)
-#define bfin_read_DMA42_CURR_Y_COUNT() bfin_read32(DMA42_CURR_Y_COUNT)
-#define bfin_write_DMA42_CURR_Y_COUNT(val) bfin_write32(DMA42_CURR_Y_COUNT, val)
-#define bfin_read_DMA42_BWL_COUNT() bfin_read32(DMA42_BWL_COUNT)
-#define bfin_write_DMA42_BWL_COUNT(val) bfin_write32(DMA42_BWL_COUNT, val)
-#define bfin_read_DMA42_CURR_BWL_COUNT() bfin_read32(DMA42_CURR_BWL_COUNT)
-#define bfin_write_DMA42_CURR_BWL_COUNT(val) bfin_write32(DMA42_CURR_BWL_COUNT, val)
-#define bfin_read_DMA42_BWM_COUNT() bfin_read32(DMA42_BWM_COUNT)
-#define bfin_write_DMA42_BWM_COUNT(val) bfin_write32(DMA42_BWM_COUNT, val)
-#define bfin_read_DMA42_CURR_BWM_COUNT() bfin_read32(DMA42_CURR_BWM_COUNT)
-#define bfin_write_DMA42_CURR_BWM_COUNT(val) bfin_write32(DMA42_CURR_BWM_COUNT, val)
-
-/* DMA Channel 43 Registers */
-
-#define bfin_read_DMA43_NEXT_DESC_PTR() bfin_read32(DMA43_NEXT_DESC_PTR)
-#define bfin_write_DMA43_NEXT_DESC_PTR(val) bfin_write32(DMA43_NEXT_DESC_PTR, val)
-#define bfin_read_DMA43_START_ADDR() bfin_read32(DMA43_START_ADDR)
-#define bfin_write_DMA43_START_ADDR(val) bfin_write32(DMA43_START_ADDR, val)
-#define bfin_read_DMA43_CONFIG() bfin_read32(DMA43_CONFIG)
-#define bfin_write_DMA43_CONFIG(val) bfin_write32(DMA43_CONFIG, val)
-#define bfin_read_DMA43_X_COUNT() bfin_read32(DMA43_X_COUNT)
-#define bfin_write_DMA43_X_COUNT(val) bfin_write32(DMA43_X_COUNT, val)
-#define bfin_read_DMA43_X_MODIFY() bfin_read32(DMA43_X_MODIFY)
-#define bfin_write_DMA43_X_MODIFY(val) bfin_write32(DMA43_X_MODIFY, val)
-#define bfin_read_DMA43_Y_COUNT() bfin_read32(DMA43_Y_COUNT)
-#define bfin_write_DMA43_Y_COUNT(val) bfin_write32(DMA43_Y_COUNT, val)
-#define bfin_read_DMA43_Y_MODIFY() bfin_read32(DMA43_Y_MODIFY)
-#define bfin_write_DMA43_Y_MODIFY(val) bfin_write32(DMA43_Y_MODIFY, val)
-#define bfin_read_DMA43_CURR_DESC_PTR() bfin_read32(DMA43_CURR_DESC_PTR)
-#define bfin_write_DMA43_CURR_DESC_PTR(val) bfin_write32(DMA43_CURR_DESC_PTR, val)
-#define bfin_read_DMA43_PREV_DESC_PTR() bfin_read32(DMA43_PREV_DESC_PTR)
-#define bfin_write_DMA43_PREV_DESC_PTR(val) bfin_write32(DMA43_PREV_DESC_PTR, val)
-#define bfin_read_DMA43_CURR_ADDR() bfin_read32(DMA43_CURR_ADDR)
-#define bfin_write_DMA43_CURR_ADDR(val) bfin_write32(DMA43_CURR_ADDR, val)
-#define bfin_read_DMA43_IRQ_STATUS() bfin_read32(DMA43_IRQ_STATUS)
-#define bfin_write_DMA43_IRQ_STATUS(val) bfin_write32(DMA43_IRQ_STATUS, val)
-#define bfin_read_DMA43_CURR_X_COUNT() bfin_read32(DMA43_CURR_X_COUNT)
-#define bfin_write_DMA43_CURR_X_COUNT(val) bfin_write32(DMA43_CURR_X_COUNT, val)
-#define bfin_read_DMA43_CURR_Y_COUNT() bfin_read32(DMA43_CURR_Y_COUNT)
-#define bfin_write_DMA43_CURR_Y_COUNT(val) bfin_write32(DMA43_CURR_Y_COUNT, val)
-#define bfin_read_DMA43_BWL_COUNT() bfin_read32(DMA43_BWL_COUNT)
-#define bfin_write_DMA43_BWL_COUNT(val) bfin_write32(DMA43_BWL_COUNT, val)
-#define bfin_read_DMA43_CURR_BWL_COUNT() bfin_read32(DMA43_CURR_BWL_COUNT)
-#define bfin_write_DMA43_CURR_BWL_COUNT(val) bfin_write32(DMA43_CURR_BWL_COUNT, val)
-#define bfin_read_DMA43_BWM_COUNT() bfin_read32(DMA43_BWM_COUNT)
-#define bfin_write_DMA43_BWM_COUNT(val) bfin_write32(DMA43_BWM_COUNT, val)
-#define bfin_read_DMA43_CURR_BWM_COUNT() bfin_read32(DMA43_CURR_BWM_COUNT)
-#define bfin_write_DMA43_CURR_BWM_COUNT(val) bfin_write32(DMA43_CURR_BWM_COUNT, val)
-
-/* DMA Channel 44 Registers */
-
-#define bfin_read_DMA44_NEXT_DESC_PTR() bfin_read32(DMA44_NEXT_DESC_PTR)
-#define bfin_write_DMA44_NEXT_DESC_PTR(val) bfin_write32(DMA44_NEXT_DESC_PTR, val)
-#define bfin_read_DMA44_START_ADDR() bfin_read32(DMA44_START_ADDR)
-#define bfin_write_DMA44_START_ADDR(val) bfin_write32(DMA44_START_ADDR, val)
-#define bfin_read_DMA44_CONFIG() bfin_read32(DMA44_CONFIG)
-#define bfin_write_DMA44_CONFIG(val) bfin_write32(DMA44_CONFIG, val)
-#define bfin_read_DMA44_X_COUNT() bfin_read32(DMA44_X_COUNT)
-#define bfin_write_DMA44_X_COUNT(val) bfin_write32(DMA44_X_COUNT, val)
-#define bfin_read_DMA44_X_MODIFY() bfin_read32(DMA44_X_MODIFY)
-#define bfin_write_DMA44_X_MODIFY(val) bfin_write32(DMA44_X_MODIFY, val)
-#define bfin_read_DMA44_Y_COUNT() bfin_read32(DMA44_Y_COUNT)
-#define bfin_write_DMA44_Y_COUNT(val) bfin_write32(DMA44_Y_COUNT, val)
-#define bfin_read_DMA44_Y_MODIFY() bfin_read32(DMA44_Y_MODIFY)
-#define bfin_write_DMA44_Y_MODIFY(val) bfin_write32(DMA44_Y_MODIFY, val)
-#define bfin_read_DMA44_CURR_DESC_PTR() bfin_read32(DMA44_CURR_DESC_PTR)
-#define bfin_write_DMA44_CURR_DESC_PTR(val) bfin_write32(DMA44_CURR_DESC_PTR, val)
-#define bfin_read_DMA44_PREV_DESC_PTR() bfin_read32(DMA44_PREV_DESC_PTR)
-#define bfin_write_DMA44_PREV_DESC_PTR(val) bfin_write32(DMA44_PREV_DESC_PTR, val)
-#define bfin_read_DMA44_CURR_ADDR() bfin_read32(DMA44_CURR_ADDR)
-#define bfin_write_DMA44_CURR_ADDR(val) bfin_write32(DMA44_CURR_ADDR, val)
-#define bfin_read_DMA44_IRQ_STATUS() bfin_read32(DMA44_IRQ_STATUS)
-#define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val)
-#define bfin_read_DMA44_CURR_X_COUNT() bfin_read32(DMA44_CURR_X_COUNT)
-#define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val)
-#define bfin_read_DMA44_CURR_Y_COUNT() bfin_read32(DMA44_CURR_Y_COUNT)
-#define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val)
-#define bfin_read_DMA44_BWL_COUNT() bfin_read32(DMA44_BWL_COUNT)
-#define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val)
-#define bfin_read_DMA44_CURR_BWL_COUNT() bfin_read32(DMA44_CURR_BWL_COUNT)
-#define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val)
-#define bfin_read_DMA44_BWM_COUNT() bfin_read32(DMA44_BWM_COUNT)
-#define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val)
-#define bfin_read_DMA44_CURR_BWM_COUNT() bfin_read32(DMA44_CURR_BWM_COUNT)
-#define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val)
-
-/* DMA Channel 45 Registers */
-
-#define bfin_read_DMA45_NEXT_DESC_PTR() bfin_read32(DMA45_NEXT_DESC_PTR)
-#define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val)
-#define bfin_read_DMA45_START_ADDR() bfin_read32(DMA45_START_ADDR)
-#define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val)
-#define bfin_read_DMA45_CONFIG() bfin_read32(DMA45_CONFIG)
-#define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val)
-#define bfin_read_DMA45_X_COUNT() bfin_read32(DMA45_X_COUNT)
-#define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val)
-#define bfin_read_DMA45_X_MODIFY() bfin_read32(DMA45_X_MODIFY)
-#define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val)
-#define bfin_read_DMA45_Y_COUNT() bfin_read32(DMA45_Y_COUNT)
-#define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val)
-#define bfin_read_DMA45_Y_MODIFY() bfin_read32(DMA45_Y_MODIFY)
-#define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val)
-#define bfin_read_DMA45_CURR_DESC_PTR() bfin_read32(DMA45_CURR_DESC_PTR)
-#define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val)
-#define bfin_read_DMA45_PREV_DESC_PTR() bfin_read32(DMA45_PREV_DESC_PTR)
-#define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val)
-#define bfin_read_DMA45_CURR_ADDR() bfin_read32(DMA45_CURR_ADDR)
-#define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val)
-#define bfin_read_DMA45_IRQ_STATUS() bfin_read32(DMA45_IRQ_STATUS)
-#define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val)
-#define bfin_read_DMA45_CURR_X_COUNT() bfin_read32(DMA45_CURR_X_COUNT)
-#define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val)
-#define bfin_read_DMA45_CURR_Y_COUNT() bfin_read32(DMA45_CURR_Y_COUNT)
-#define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val)
-#define bfin_read_DMA45_BWL_COUNT() bfin_read32(DMA45_BWL_COUNT)
-#define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val)
-#define bfin_read_DMA45_CURR_BWL_COUNT() bfin_read32(DMA45_CURR_BWL_COUNT)
-#define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val)
-#define bfin_read_DMA45_BWM_COUNT() bfin_read32(DMA45_BWM_COUNT)
-#define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val)
-#define bfin_read_DMA45_CURR_BWM_COUNT() bfin_read32(DMA45_CURR_BWM_COUNT)
-#define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val)
-
-/* DMA Channel 46 Registers */
-
-#define bfin_read_DMA46_NEXT_DESC_PTR() bfin_read32(DMA46_NEXT_DESC_PTR)
-#define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val)
-#define bfin_read_DMA46_START_ADDR() bfin_read32(DMA46_START_ADDR)
-#define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val)
-#define bfin_read_DMA46_CONFIG() bfin_read32(DMA46_CONFIG)
-#define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val)
-#define bfin_read_DMA46_X_COUNT() bfin_read32(DMA46_X_COUNT)
-#define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val)
-#define bfin_read_DMA46_X_MODIFY() bfin_read32(DMA46_X_MODIFY)
-#define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val)
-#define bfin_read_DMA46_Y_COUNT() bfin_read32(DMA46_Y_COUNT)
-#define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val)
-#define bfin_read_DMA46_Y_MODIFY() bfin_read32(DMA46_Y_MODIFY)
-#define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val)
-#define bfin_read_DMA46_CURR_DESC_PTR() bfin_read32(DMA46_CURR_DESC_PTR)
-#define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val)
-#define bfin_read_DMA46_PREV_DESC_PTR() bfin_read32(DMA46_PREV_DESC_PTR)
-#define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val)
-#define bfin_read_DMA46_CURR_ADDR() bfin_read32(DMA46_CURR_ADDR)
-#define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val)
-#define bfin_read_DMA46_IRQ_STATUS() bfin_read32(DMA46_IRQ_STATUS)
-#define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val)
-#define bfin_read_DMA46_CURR_X_COUNT() bfin_read32(DMA46_CURR_X_COUNT)
-#define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val)
-#define bfin_read_DMA46_CURR_Y_COUNT() bfin_read32(DMA46_CURR_Y_COUNT)
-#define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val)
-#define bfin_read_DMA46_BWL_COUNT() bfin_read32(DMA46_BWL_COUNT)
-#define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val)
-#define bfin_read_DMA46_CURR_BWL_COUNT() bfin_read32(DMA46_CURR_BWL_COUNT)
-#define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val)
-#define bfin_read_DMA46_BWM_COUNT() bfin_read32(DMA46_BWM_COUNT)
-#define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val)
-#define bfin_read_DMA46_CURR_BWM_COUNT() bfin_read32(DMA46_CURR_BWM_COUNT)
-#define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val)
-
-
-/* EPPI1 Registers */
-
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-
-/* Port Interrubfin_read_()t 4 Registers (32-bit) */
-
-#define bfin_read_PINT4_MASK_SET() bfin_read32(PINT4_MASK_SET)
-#define bfin_write_PINT4_MASK_SET(val) bfin_write32(PINT4_MASK_SET, val)
-#define bfin_read_PINT4_MASK_CLEAR() bfin_read32(PINT4_MASK_CLEAR)
-#define bfin_write_PINT4_MASK_CLEAR(val) bfin_write32(PINT4_MASK_CLEAR, val)
-#define bfin_read_PINT4_REQUEST() bfin_read32(PINT4_REQUEST)
-#define bfin_write_PINT4_REQUEST(val) bfin_write32(PINT4_REQUEST, val)
-#define bfin_read_PINT4_ASSIGN() bfin_read32(PINT4_ASSIGN)
-#define bfin_write_PINT4_ASSIGN(val) bfin_write32(PINT4_ASSIGN, val)
-#define bfin_read_PINT4_EDGE_SET() bfin_read32(PINT4_EDGE_SET)
-#define bfin_write_PINT4_EDGE_SET(val) bfin_write32(PINT4_EDGE_SET, val)
-#define bfin_read_PINT4_EDGE_CLEAR() bfin_read32(PINT4_EDGE_CLEAR)
-#define bfin_write_PINT4_EDGE_CLEAR(val) bfin_write32(PINT4_EDGE_CLEAR, val)
-#define bfin_read_PINT4_INVERT_SET() bfin_read32(PINT4_INVERT_SET)
-#define bfin_write_PINT4_INVERT_SET(val) bfin_write32(PINT4_INVERT_SET, val)
-#define bfin_read_PINT4_INVERT_CLEAR() bfin_read32(PINT4_INVERT_CLEAR)
-#define bfin_write_PINT4_INVERT_CLEAR(val) bfin_write32(PINT4_INVERT_CLEAR, val)
-#define bfin_read_PINT4_PINSTATE() bfin_read32(PINT4_PINSTATE)
-#define bfin_write_PINT4_PINSTATE(val) bfin_write32(PINT4_PINSTATE, val)
-#define bfin_read_PINT4_LATCH() bfin_read32(PINT4_LATCH)
-#define bfin_write_PINT4_LATCH(val) bfin_write32(PINT4_LATCH, val)
-
-/* Port Interrubfin_read_()t 5 Registers (32-bit) */
-
-#define bfin_read_PINT5_MASK_SET() bfin_read32(PINT5_MASK_SET)
-#define bfin_write_PINT5_MASK_SET(val) bfin_write32(PINT5_MASK_SET, val)
-#define bfin_read_PINT5_MASK_CLEAR() bfin_read32(PINT5_MASK_CLEAR)
-#define bfin_write_PINT5_MASK_CLEAR(val) bfin_write32(PINT5_MASK_CLEAR, val)
-#define bfin_read_PINT5_REQUEST() bfin_read32(PINT5_REQUEST)
-#define bfin_write_PINT5_REQUEST(val) bfin_write32(PINT5_REQUEST, val)
-#define bfin_read_PINT5_ASSIGN() bfin_read32(PINT5_ASSIGN)
-#define bfin_write_PINT5_ASSIGN(val) bfin_write32(PINT5_ASSIGN, val)
-#define bfin_read_PINT5_EDGE_SET() bfin_read32(PINT5_EDGE_SET)
-#define bfin_write_PINT5_EDGE_SET(val) bfin_write32(PINT5_EDGE_SET, val)
-#define bfin_read_PINT5_EDGE_CLEAR() bfin_read32(PINT5_EDGE_CLEAR)
-#define bfin_write_PINT5_EDGE_CLEAR(val) bfin_write32(PINT5_EDGE_CLEAR, val)
-#define bfin_read_PINT5_INVERT_SET() bfin_read32(PINT5_INVERT_SET)
-#define bfin_write_PINT5_INVERT_SET(val) bfin_write32(PINT5_INVERT_SET, val)
-#define bfin_read_PINT5_INVERT_CLEAR() bfin_read32(PINT5_INVERT_CLEAR)
-#define bfin_write_PINT5_INVERT_CLEAR(val) bfin_write32(PINT5_INVERT_CLEAR, val)
-#define bfin_read_PINT5_PINSTATE() bfin_read32(PINT5_PINSTATE)
-#define bfin_write_PINT5_PINSTATE(val) bfin_write32(PINT5_PINSTATE, val)
-#define bfin_read_PINT5_LATCH() bfin_read32(PINT5_LATCH)
-#define bfin_write_PINT5_LATCH(val) bfin_write32(PINT5_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER() bfin_read32(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write32(PORTA_FER, val)
-#define bfin_read_PORTA_FER_SET() bfin_read32(PORTA_FER_SET)
-#define bfin_write_PORTA_FER_SET(val) bfin_write32(PORTA_FER_SET, val)
-#define bfin_read_PORTA_FER_CLEAR() bfin_read32(PORTA_FER_CLEAR)
-#define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val)
-#define bfin_read_PORTA() bfin_read32(PORTA)
-#define bfin_write_PORTA(val) bfin_write32(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read32(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write32(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read32(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write32(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR() bfin_read32(PORTA_DIR)
-#define bfin_write_PORTA_DIR(val) bfin_write32(PORTA_DIR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read32(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write32(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read32(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read32(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write32(PORTA_INEN, val)
-#define bfin_read_PORTA_INEN_SET() bfin_read32(PORTA_INEN_SET)
-#define bfin_write_PORTA_INEN_SET(val) bfin_write32(PORTA_INEN_SET, val)
-#define bfin_read_PORTA_INEN_CLEAR() bfin_read32(PORTA_INEN_CLEAR)
-#define bfin_write_PORTA_INEN_CLEAR(val) bfin_write32(PORTA_INEN_CLEAR, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTA_DATA_TGL() bfin_read32(PORTA_DATA_TGL)
-#define bfin_write_PORTA_DATA_TGL(val) bfin_write32(PORTA_DATA_TGL, val)
-#define bfin_read_PORTA_POL() bfin_read32(PORTA_POL)
-#define bfin_write_PORTA_POL(val) bfin_write32(PORTA_POL, val)
-#define bfin_read_PORTA_POL_SET() bfin_read32(PORTA_POL_SET)
-#define bfin_write_PORTA_POL_SET(val) bfin_write32(PORTA_POL_SET, val)
-#define bfin_read_PORTA_POL_CLEAR() bfin_read32(PORTA_POL_CLEAR)
-#define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val)
-#define bfin_read_PORTA_LOCK() bfin_read32(PORTA_LOCK)
-#define bfin_write_PORTA_LOCK(val) bfin_write32(PORTA_LOCK, val)
-#define bfin_read_PORTA_REVID() bfin_read32(PORTA_REVID)
-#define bfin_write_PORTA_REVID(val) bfin_write32(PORTA_REVID, val)
-
-
-
-/* Port B Registers */
-#define bfin_read_PORTB_FER() bfin_read32(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write32(PORTB_FER, val)
-#define bfin_read_PORTB_FER_SET() bfin_read32(PORTB_FER_SET)
-#define bfin_write_PORTB_FER_SET(val) bfin_write32(PORTB_FER_SET, val)
-#define bfin_read_PORTB_FER_CLEAR() bfin_read32(PORTB_FER_CLEAR)
-#define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val)
-#define bfin_read_PORTB() bfin_read32(PORTB)
-#define bfin_write_PORTB(val) bfin_write32(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read32(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write32(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read32(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write32(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR() bfin_read32(PORTB_DIR)
-#define bfin_write_PORTB_DIR(val) bfin_write32(PORTB_DIR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read32(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write32(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read32(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read32(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write32(PORTB_INEN, val)
-#define bfin_read_PORTB_INEN_SET() bfin_read32(PORTB_INEN_SET)
-#define bfin_write_PORTB_INEN_SET(val) bfin_write32(PORTB_INEN_SET, val)
-#define bfin_read_PORTB_INEN_CLEAR() bfin_read32(PORTB_INEN_CLEAR)
-#define bfin_write_PORTB_INEN_CLEAR(val) bfin_write32(PORTB_INEN_CLEAR, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTB_DATA_TGL() bfin_read32(PORTB_DATA_TGL)
-#define bfin_write_PORTB_DATA_TGL(val) bfin_write32(PORTB_DATA_TGL, val)
-#define bfin_read_PORTB_POL() bfin_read32(PORTB_POL)
-#define bfin_write_PORTB_POL(val) bfin_write32(PORTB_POL, val)
-#define bfin_read_PORTB_POL_SET() bfin_read32(PORTB_POL_SET)
-#define bfin_write_PORTB_POL_SET(val) bfin_write32(PORTB_POL_SET, val)
-#define bfin_read_PORTB_POL_CLEAR() bfin_read32(PORTB_POL_CLEAR)
-#define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val)
-#define bfin_read_PORTB_LOCK() bfin_read32(PORTB_LOCK)
-#define bfin_write_PORTB_LOCK(val) bfin_write32(PORTB_LOCK, val)
-#define bfin_read_PORTB_REVID() bfin_read32(PORTB_REVID)
-#define bfin_write_PORTB_REVID(val) bfin_write32(PORTB_REVID, val)
-
-
-/* Port C Registers */
-#define bfin_read_PORTC_FER() bfin_read32(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write32(PORTC_FER, val)
-#define bfin_read_PORTC_FER_SET() bfin_read32(PORTC_FER_SET)
-#define bfin_write_PORTC_FER_SET(val) bfin_write32(PORTC_FER_SET, val)
-#define bfin_read_PORTC_FER_CLEAR() bfin_read32(PORTC_FER_CLEAR)
-#define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val)
-#define bfin_read_PORTC() bfin_read32(PORTC)
-#define bfin_write_PORTC(val) bfin_write32(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read32(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write32(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read32(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write32(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR() bfin_read32(PORTC_DIR)
-#define bfin_write_PORTC_DIR(val) bfin_write32(PORTC_DIR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read32(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write32(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read32(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read32(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write32(PORTC_INEN, val)
-#define bfin_read_PORTC_INEN_SET() bfin_read32(PORTC_INEN_SET)
-#define bfin_write_PORTC_INEN_SET(val) bfin_write32(PORTC_INEN_SET, val)
-#define bfin_read_PORTC_INEN_CLEAR() bfin_read32(PORTC_INEN_CLEAR)
-#define bfin_write_PORTC_INEN_CLEAR(val) bfin_write32(PORTC_INEN_CLEAR, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTC_DATA_TGL() bfin_read32(PORTC_DATA_TGL)
-#define bfin_write_PORTC_DATA_TGL(val) bfin_write32(PORTC_DATA_TGL, val)
-#define bfin_read_PORTC_POL() bfin_read32(PORTC_POL)
-#define bfin_write_PORTC_POL(val) bfin_write32(PORTC_POL, val)
-#define bfin_read_PORTC_POL_SET() bfin_read32(PORTC_POL_SET)
-#define bfin_write_PORTC_POL_SET(val) bfin_write32(PORTC_POL_SET, val)
-#define bfin_read_PORTC_POL_CLEAR() bfin_read32(PORTC_POL_CLEAR)
-#define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val)
-#define bfin_read_PORTC_LOCK() bfin_read32(PORTC_LOCK)
-#define bfin_write_PORTC_LOCK(val) bfin_write32(PORTC_LOCK, val)
-#define bfin_read_PORTC_REVID() bfin_read32(PORTC_REVID)
-#define bfin_write_PORTC_REVID(val) bfin_write32(PORTC_REVID, val)
-
-
-/* Port D Registers */
-#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write32(PORTD_FER, val)
-#define bfin_read_PORTD_FER_SET() bfin_read32(PORTD_FER_SET)
-#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
-#define bfin_read_PORTD_FER_CLEAR() bfin_read32(PORTD_FER_CLEAR)
-#define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val)
-#define bfin_read_PORTD() bfin_read32(PORTD)
-#define bfin_write_PORTD(val) bfin_write32(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read32(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write32(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read32(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write32(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR() bfin_read32(PORTD_DIR)
-#define bfin_write_PORTD_DIR(val) bfin_write32(PORTD_DIR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read32(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write32(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read32(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read32(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write32(PORTD_INEN, val)
-#define bfin_read_PORTD_INEN_SET() bfin_read32(PORTD_INEN_SET)
-#define bfin_write_PORTD_INEN_SET(val) bfin_write32(PORTD_INEN_SET, val)
-#define bfin_read_PORTD_INEN_CLEAR() bfin_read32(PORTD_INEN_CLEAR)
-#define bfin_write_PORTD_INEN_CLEAR(val) bfin_write32(PORTD_INEN_CLEAR, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTD_DATA_TGL() bfin_read32(PORTD_DATA_TGL)
-#define bfin_write_PORTD_DATA_TGL(val) bfin_write32(PORTD_DATA_TGL, val)
-#define bfin_read_PORTD_POL() bfin_read32(PORTD_POL)
-#define bfin_write_PORTD_POL(val) bfin_write32(PORTD_POL, val)
-#define bfin_read_PORTD_POL_SET() bfin_read32(PORTD_POL_SET)
-#define bfin_write_PORTD_POL_SET(val) bfin_write32(PORTD_POL_SET, val)
-#define bfin_read_PORTD_POL_CLEAR() bfin_read32(PORTD_POL_CLEAR)
-#define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val)
-#define bfin_read_PORTD_LOCK() bfin_read32(PORTD_LOCK)
-#define bfin_write_PORTD_LOCK(val) bfin_write32(PORTD_LOCK, val)
-#define bfin_read_PORTD_REVID() bfin_read32(PORTD_REVID)
-#define bfin_write_PORTD_REVID(val) bfin_write32(PORTD_REVID, val)
-
-
-/* Port E Registers */
-#define bfin_read_PORTE_FER() bfin_read32(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write32(PORTE_FER, val)
-#define bfin_read_PORTE_FER_SET() bfin_read32(PORTE_FER_SET)
-#define bfin_write_PORTE_FER_SET(val) bfin_write32(PORTE_FER_SET, val)
-#define bfin_read_PORTE_FER_CLEAR() bfin_read32(PORTE_FER_CLEAR)
-#define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val)
-#define bfin_read_PORTE() bfin_read32(PORTE)
-#define bfin_write_PORTE(val) bfin_write32(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read32(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write32(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read32(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write32(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR() bfin_read32(PORTE_DIR)
-#define bfin_write_PORTE_DIR(val) bfin_write32(PORTE_DIR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read32(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write32(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read32(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read32(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write32(PORTE_INEN, val)
-#define bfin_read_PORTE_INEN_SET() bfin_read32(PORTE_INEN_SET)
-#define bfin_write_PORTE_INEN_SET(val) bfin_write32(PORTE_INEN_SET, val)
-#define bfin_read_PORTE_INEN_CLEAR() bfin_read32(PORTE_INEN_CLEAR)
-#define bfin_write_PORTE_INEN_CLEAR(val) bfin_write32(PORTE_INEN_CLEAR, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTE_DATA_TGL() bfin_read32(PORTE_DATA_TGL)
-#define bfin_write_PORTE_DATA_TGL(val) bfin_write32(PORTE_DATA_TGL, val)
-#define bfin_read_PORTE_POL() bfin_read32(PORTE_POL)
-#define bfin_write_PORTE_POL(val) bfin_write32(PORTE_POL, val)
-#define bfin_read_PORTE_POL_SET() bfin_read32(PORTE_POL_SET)
-#define bfin_write_PORTE_POL_SET(val) bfin_write32(PORTE_POL_SET, val)
-#define bfin_read_PORTE_POL_CLEAR() bfin_read32(PORTE_POL_CLEAR)
-#define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val)
-#define bfin_read_PORTE_LOCK() bfin_read32(PORTE_LOCK)
-#define bfin_write_PORTE_LOCK(val) bfin_write32(PORTE_LOCK, val)
-#define bfin_read_PORTE_REVID() bfin_read32(PORTE_REVID)
-#define bfin_write_PORTE_REVID(val) bfin_write32(PORTE_REVID, val)
-
-
-/* Port F Registers */
-#define bfin_read_PORTF_FER() bfin_read32(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write32(PORTF_FER, val)
-#define bfin_read_PORTF_FER_SET() bfin_read32(PORTF_FER_SET)
-#define bfin_write_PORTF_FER_SET(val) bfin_write32(PORTF_FER_SET, val)
-#define bfin_read_PORTF_FER_CLEAR() bfin_read32(PORTF_FER_CLEAR)
-#define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val)
-#define bfin_read_PORTF() bfin_read32(PORTF)
-#define bfin_write_PORTF(val) bfin_write32(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read32(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write32(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read32(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write32(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR() bfin_read32(PORTF_DIR)
-#define bfin_write_PORTF_DIR(val) bfin_write32(PORTF_DIR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read32(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write32(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read32(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read32(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write32(PORTF_INEN, val)
-#define bfin_read_PORTF_INEN_SET() bfin_read32(PORTF_INEN_SET)
-#define bfin_write_PORTF_INEN_SET(val) bfin_write32(PORTF_INEN_SET, val)
-#define bfin_read_PORTF_INEN_CLEAR() bfin_read32(PORTF_INEN_CLEAR)
-#define bfin_write_PORTF_INEN_CLEAR(val) bfin_write32(PORTF_INEN_CLEAR, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTF_DATA_TGL() bfin_read32(PORTF_DATA_TGL)
-#define bfin_write_PORTF_DATA_TGL(val) bfin_write32(PORTF_DATA_TGL, val)
-#define bfin_read_PORTF_POL() bfin_read32(PORTF_POL)
-#define bfin_write_PORTF_POL(val) bfin_write32(PORTF_POL, val)
-#define bfin_read_PORTF_POL_SET() bfin_read32(PORTF_POL_SET)
-#define bfin_write_PORTF_POL_SET(val) bfin_write32(PORTF_POL_SET, val)
-#define bfin_read_PORTF_POL_CLEAR() bfin_read32(PORTF_POL_CLEAR)
-#define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val)
-#define bfin_read_PORTF_LOCK() bfin_read32(PORTF_LOCK)
-#define bfin_write_PORTF_LOCK(val) bfin_write32(PORTF_LOCK, val)
-#define bfin_read_PORTF_REVID() bfin_read32(PORTF_REVID)
-#define bfin_write_PORTF_REVID(val) bfin_write32(PORTF_REVID, val)
-
-
-/* Port G Registers */
-#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write32(PORTG_FER, val)
-#define bfin_read_PORTG_FER_SET() bfin_read32(PORTG_FER_SET)
-#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
-#define bfin_read_PORTG_FER_CLEAR() bfin_read32(PORTG_FER_CLEAR)
-#define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val)
-#define bfin_read_PORTG() bfin_read32(PORTG)
-#define bfin_write_PORTG(val) bfin_write32(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read32(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write32(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read32(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write32(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR() bfin_read32(PORTG_DIR)
-#define bfin_write_PORTG_DIR(val) bfin_write32(PORTG_DIR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read32(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write32(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read32(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read32(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write32(PORTG_INEN, val)
-#define bfin_read_PORTG_INEN_SET() bfin_read32(PORTG_INEN_SET)
-#define bfin_write_PORTG_INEN_SET(val) bfin_write32(PORTG_INEN_SET, val)
-#define bfin_read_PORTG_INEN_CLEAR() bfin_read32(PORTG_INEN_CLEAR)
-#define bfin_write_PORTG_INEN_CLEAR(val) bfin_write32(PORTG_INEN_CLEAR, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTG_DATA_TGL() bfin_read32(PORTG_DATA_TGL)
-#define bfin_write_PORTG_DATA_TGL(val) bfin_write32(PORTG_DATA_TGL, val)
-#define bfin_read_PORTG_POL() bfin_read32(PORTG_POL)
-#define bfin_write_PORTG_POL(val) bfin_write32(PORTG_POL, val)
-#define bfin_read_PORTG_POL_SET() bfin_read32(PORTG_POL_SET)
-#define bfin_write_PORTG_POL_SET(val) bfin_write32(PORTG_POL_SET, val)
-#define bfin_read_PORTG_POL_CLEAR() bfin_read32(PORTG_POL_CLEAR)
-#define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val)
-#define bfin_read_PORTG_LOCK() bfin_read32(PORTG_LOCK)
-#define bfin_write_PORTG_LOCK(val) bfin_write32(PORTG_LOCK, val)
-#define bfin_read_PORTG_REVID() bfin_read32(PORTG_REVID)
-#define bfin_write_PORTG_REVID(val) bfin_write32(PORTG_REVID, val)
-
-
-
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* RSI Register */
-#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ)
-#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS() bfin_read32(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val) bfin_write32(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK() bfin_read32(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val) bfin_write32(RSI_EMASK, val)
-#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-
-/* usb register */
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
-#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
-
-#endif /* _CDEF_BF60X_H */
-
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h
deleted file mode 100644
index 8045ade..0000000
--- a/arch/blackfin/mach-bf609/include/mach/defBF609.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF609_H
-#define _DEF_BF609_H
-
-/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */
-#include "defBF60x_base.h"
-
-/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
-/* =========================
- PIXC Registers
- ========================= */
-
-/* =========================
- PIXC0
- ========================= */
-#define PIXC0_CTL 0xFFC19000 /* PIXC0 Control Register */
-#define PIXC0_PPL 0xFFC19004 /* PIXC0 Pixels Per Line Register */
-#define PIXC0_LPF 0xFFC19008 /* PIXC0 Line Per Frame Register */
-#define PIXC0_HSTART_A 0xFFC1900C /* PIXC0 Overlay A Horizontal Start Register */
-#define PIXC0_HEND_A 0xFFC19010 /* PIXC0 Overlay A Horizontal End Register */
-#define PIXC0_VSTART_A 0xFFC19014 /* PIXC0 Overlay A Vertical Start Register */
-#define PIXC0_VEND_A 0xFFC19018 /* PIXC0 Overlay A Vertical End Register */
-#define PIXC0_TRANSP_A 0xFFC1901C /* PIXC0 Overlay A Transparency Ratio Register */
-#define PIXC0_HSTART_B 0xFFC19020 /* PIXC0 Overlay B Horizontal Start Register */
-#define PIXC0_HEND_B 0xFFC19024 /* PIXC0 Overlay B Horizontal End Register */
-#define PIXC0_VSTART_B 0xFFC19028 /* PIXC0 Overlay B Vertical Start Register */
-#define PIXC0_VEND_B 0xFFC1902C /* PIXC0 Overlay B Vertical End Register */
-#define PIXC0_TRANSP_B 0xFFC19030 /* PIXC0 Overlay B Transparency Ratio Register */
-#define PIXC0_IRQSTAT 0xFFC1903C /* PIXC0 Interrupt Status Register */
-#define PIXC0_CONRY 0xFFC19040 /* PIXC0 RY Conversion Component Register */
-#define PIXC0_CONGU 0xFFC19044 /* PIXC0 GU Conversion Component Register */
-#define PIXC0_CONBV 0xFFC19048 /* PIXC0 BV Conversion Component Register */
-#define PIXC0_CCBIAS 0xFFC1904C /* PIXC0 Conversion Bias Register */
-#define PIXC0_TC 0xFFC19050 /* PIXC0 Transparency Register */
-#define PIXC0_REVID 0xFFC19054 /* PIXC0 PIXC Revision Id */
-
-/* =========================
- PVP Registers
- ========================= */
-
-/* =========================
- PVP0
- ========================= */
-#define PVP0_REVID 0xFFC1A000 /* PVP0 Revision ID */
-#define PVP0_CTL 0xFFC1A004 /* PVP0 Control */
-#define PVP0_IMSK0 0xFFC1A008 /* PVP0 INTn interrupt line masks */
-#define PVP0_IMSK1 0xFFC1A00C /* PVP0 INTn interrupt line masks */
-#define PVP0_STAT 0xFFC1A010 /* PVP0 Status */
-#define PVP0_ILAT 0xFFC1A014 /* PVP0 Latched status */
-#define PVP0_IREQ0 0xFFC1A018 /* PVP0 INT0 masked latched status */
-#define PVP0_IREQ1 0xFFC1A01C /* PVP0 INT0 masked latched status */
-#define PVP0_OPF0_CFG 0xFFC1A020 /* PVP0 Config */
-#define PVP0_OPF1_CFG 0xFFC1A040 /* PVP0 Config */
-#define PVP0_OPF2_CFG 0xFFC1A060 /* PVP0 Config */
-#define PVP0_OPF0_CTL 0xFFC1A024 /* PVP0 Control */
-#define PVP0_OPF1_CTL 0xFFC1A044 /* PVP0 Control */
-#define PVP0_OPF2_CTL 0xFFC1A064 /* PVP0 Control */
-#define PVP0_OPF3_CFG 0xFFC1A080 /* PVP0 Config */
-#define PVP0_OPF3_CTL 0xFFC1A084 /* PVP0 Control */
-#define PVP0_PEC_CFG 0xFFC1A0A0 /* PVP0 Config */
-#define PVP0_PEC_CTL 0xFFC1A0A4 /* PVP0 Control */
-#define PVP0_PEC_D1TH0 0xFFC1A0A8 /* PVP0 Lower Hysteresis Threshold */
-#define PVP0_PEC_D1TH1 0xFFC1A0AC /* PVP0 Upper Hysteresis Threshold */
-#define PVP0_PEC_D2TH0 0xFFC1A0B0 /* PVP0 Weak Zero Crossing Threshold */
-#define PVP0_PEC_D2TH1 0xFFC1A0B4 /* PVP0 Strong Zero Crossing Threshold */
-#define PVP0_IIM0_CFG 0xFFC1A0C0 /* PVP0 Config */
-#define PVP0_IIM1_CFG 0xFFC1A0E0 /* PVP0 Config */
-#define PVP0_IIM0_CTL 0xFFC1A0C4 /* PVP0 Control */
-#define PVP0_IIM1_CTL 0xFFC1A0E4 /* PVP0 Control */
-#define PVP0_IIM0_SCALE 0xFFC1A0C8 /* PVP0 Scaler Values */
-#define PVP0_IIM1_SCALE 0xFFC1A0E8 /* PVP0 Scaler Values */
-#define PVP0_IIM0_SOVF_STAT 0xFFC1A0CC /* PVP0 Signed Overflow Status */
-#define PVP0_IIM1_SOVF_STAT 0xFFC1A0EC /* PVP0 Signed Overflow Status */
-#define PVP0_IIM0_UOVF_STAT 0xFFC1A0D0 /* PVP0 Unsigned Overflow Status */
-#define PVP0_IIM1_UOVF_STAT 0xFFC1A0F0 /* PVP0 Unsigned Overflow Status */
-#define PVP0_ACU_CFG 0xFFC1A100 /* PVP0 ACU Configuration Register */
-#define PVP0_ACU_CTL 0xFFC1A104 /* PVP0 ACU Control Register */
-#define PVP0_ACU_OFFSET 0xFFC1A108 /* PVP0 SUM constant register */
-#define PVP0_ACU_FACTOR 0xFFC1A10C /* PVP0 PROD constant register */
-#define PVP0_ACU_SHIFT 0xFFC1A110 /* PVP0 Shift constant register */
-#define PVP0_ACU_MIN 0xFFC1A114 /* PVP0 Lower saturation threshold set to MIN */
-#define PVP0_ACU_MAX 0xFFC1A118 /* PVP0 Upper saturation threshold set to MAX */
-#define PVP0_UDS_CFG 0xFFC1A140 /* PVP0 UDS Configuration Register */
-#define PVP0_UDS_CTL 0xFFC1A144 /* PVP0 UDS Control Register */
-#define PVP0_UDS_OHCNT 0xFFC1A148 /* PVP0 UDS Output H Dimension */
-#define PVP0_UDS_OVCNT 0xFFC1A14C /* PVP0 UDS Output V Dimension */
-#define PVP0_UDS_HAVG 0xFFC1A150 /* PVP0 UDS H Taps */
-#define PVP0_UDS_VAVG 0xFFC1A154 /* PVP0 UDS V Taps */
-#define PVP0_IPF0_CFG 0xFFC1A180 /* PVP0 Configuration */
-#define PVP0_IPF0_PIPECTL 0xFFC1A184 /* PVP0 Pipe Control */
-#define PVP0_IPF1_PIPECTL 0xFFC1A1C4 /* PVP0 Pipe Control */
-#define PVP0_IPF0_CTL 0xFFC1A188 /* PVP0 Control */
-#define PVP0_IPF1_CTL 0xFFC1A1C8 /* PVP0 Control */
-#define PVP0_IPF0_TAG 0xFFC1A18C /* PVP0 TAG Value */
-#define PVP0_IPF1_TAG 0xFFC1A1CC /* PVP0 TAG Value */
-#define PVP0_IPF0_FCNT 0xFFC1A190 /* PVP0 Frame Count */
-#define PVP0_IPF1_FCNT 0xFFC1A1D0 /* PVP0 Frame Count */
-#define PVP0_IPF0_HCNT 0xFFC1A194 /* PVP0 Horizontal Count */
-#define PVP0_IPF1_HCNT 0xFFC1A1D4 /* PVP0 Horizontal Count */
-#define PVP0_IPF0_VCNT 0xFFC1A198 /* PVP0 Vertical Count */
-#define PVP0_IPF1_VCNT 0xFFC1A1D8 /* PVP0 Vertical Count */
-#define PVP0_IPF0_HPOS 0xFFC1A19C /* PVP0 Horizontal Position */
-#define PVP0_IPF0_VPOS 0xFFC1A1A0 /* PVP0 Vertical Position */
-#define PVP0_IPF0_TAG_STAT 0xFFC1A1A4 /* PVP0 TAG Status */
-#define PVP0_IPF1_TAG_STAT 0xFFC1A1E4 /* PVP0 TAG Status */
-#define PVP0_IPF1_CFG 0xFFC1A1C0 /* PVP0 Configuration */
-#define PVP0_CNV0_CFG 0xFFC1A200 /* PVP0 Configuration */
-#define PVP0_CNV1_CFG 0xFFC1A280 /* PVP0 Configuration */
-#define PVP0_CNV2_CFG 0xFFC1A300 /* PVP0 Configuration */
-#define PVP0_CNV3_CFG 0xFFC1A380 /* PVP0 Configuration */
-#define PVP0_CNV0_CTL 0xFFC1A204 /* PVP0 Control */
-#define PVP0_CNV1_CTL 0xFFC1A284 /* PVP0 Control */
-#define PVP0_CNV2_CTL 0xFFC1A304 /* PVP0 Control */
-#define PVP0_CNV3_CTL 0xFFC1A384 /* PVP0 Control */
-#define PVP0_CNV0_C00C01 0xFFC1A208 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV1_C00C01 0xFFC1A288 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV2_C00C01 0xFFC1A308 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV3_C00C01 0xFFC1A388 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV0_C02C03 0xFFC1A20C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV1_C02C03 0xFFC1A28C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV2_C02C03 0xFFC1A30C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV3_C02C03 0xFFC1A38C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV0_C04 0xFFC1A210 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV1_C04 0xFFC1A290 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV2_C04 0xFFC1A310 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV3_C04 0xFFC1A390 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV0_C10C11 0xFFC1A214 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV1_C10C11 0xFFC1A294 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV2_C10C11 0xFFC1A314 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV3_C10C11 0xFFC1A394 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV0_C12C13 0xFFC1A218 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV1_C12C13 0xFFC1A298 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV2_C12C13 0xFFC1A318 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV3_C12C13 0xFFC1A398 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV0_C14 0xFFC1A21C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV1_C14 0xFFC1A29C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV2_C14 0xFFC1A31C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV3_C14 0xFFC1A39C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV0_C20C21 0xFFC1A220 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV1_C20C21 0xFFC1A2A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV2_C20C21 0xFFC1A320 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV3_C20C21 0xFFC1A3A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV0_C22C23 0xFFC1A224 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV1_C22C23 0xFFC1A2A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV2_C22C23 0xFFC1A324 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV3_C22C23 0xFFC1A3A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV0_C24 0xFFC1A228 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV1_C24 0xFFC1A2A8 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV2_C24 0xFFC1A328 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV3_C24 0xFFC1A3A8 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV0_C30C31 0xFFC1A22C /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV1_C30C31 0xFFC1A2AC /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV2_C30C31 0xFFC1A32C /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV3_C30C31 0xFFC1A3AC /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV0_C32C33 0xFFC1A230 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV1_C32C33 0xFFC1A2B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV2_C32C33 0xFFC1A330 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV3_C32C33 0xFFC1A3B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV0_C34 0xFFC1A234 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV1_C34 0xFFC1A2B4 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV2_C34 0xFFC1A334 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV3_C34 0xFFC1A3B4 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV0_C40C41 0xFFC1A238 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV1_C40C41 0xFFC1A2B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV2_C40C41 0xFFC1A338 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV3_C40C41 0xFFC1A3B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV0_C42C43 0xFFC1A23C /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV1_C42C43 0xFFC1A2BC /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV2_C42C43 0xFFC1A33C /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV3_C42C43 0xFFC1A3BC /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV0_C44 0xFFC1A240 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV1_C44 0xFFC1A2C0 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV2_C44 0xFFC1A340 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV3_C44 0xFFC1A3C0 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV0_SCALE 0xFFC1A244 /* PVP0 Scaling factor */
-#define PVP0_CNV1_SCALE 0xFFC1A2C4 /* PVP0 Scaling factor */
-#define PVP0_CNV2_SCALE 0xFFC1A344 /* PVP0 Scaling factor */
-#define PVP0_CNV3_SCALE 0xFFC1A3C4 /* PVP0 Scaling factor */
-#define PVP0_THC0_CFG 0xFFC1A400 /* PVP0 Configuration */
-#define PVP0_THC1_CFG 0xFFC1A500 /* PVP0 Configuration */
-#define PVP0_THC0_CTL 0xFFC1A404 /* PVP0 Control */
-#define PVP0_THC1_CTL 0xFFC1A504 /* PVP0 Control */
-#define PVP0_THC0_HFCNT 0xFFC1A408 /* PVP0 Number of frames */
-#define PVP0_THC1_HFCNT 0xFFC1A508 /* PVP0 Number of frames */
-#define PVP0_THC0_RMAXREP 0xFFC1A40C /* PVP0 Maximum number of RLE reports */
-#define PVP0_THC1_RMAXREP 0xFFC1A50C /* PVP0 Maximum number of RLE reports */
-#define PVP0_THC0_CMINVAL 0xFFC1A410 /* PVP0 Min clip value */
-#define PVP0_THC1_CMINVAL 0xFFC1A510 /* PVP0 Min clip value */
-#define PVP0_THC0_CMINTH 0xFFC1A414 /* PVP0 Clip Min Threshold */
-#define PVP0_THC1_CMINTH 0xFFC1A514 /* PVP0 Clip Min Threshold */
-#define PVP0_THC0_CMAXTH 0xFFC1A418 /* PVP0 Clip Max Threshold */
-#define PVP0_THC1_CMAXTH 0xFFC1A518 /* PVP0 Clip Max Threshold */
-#define PVP0_THC0_CMAXVAL 0xFFC1A41C /* PVP0 Max clip value */
-#define PVP0_THC1_CMAXVAL 0xFFC1A51C /* PVP0 Max clip value */
-#define PVP0_THC0_TH0 0xFFC1A420 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH0 0xFFC1A520 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH1 0xFFC1A424 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH1 0xFFC1A524 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH2 0xFFC1A428 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH2 0xFFC1A528 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH3 0xFFC1A42C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH3 0xFFC1A52C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH4 0xFFC1A430 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH4 0xFFC1A530 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH5 0xFFC1A434 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH5 0xFFC1A534 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH6 0xFFC1A438 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH6 0xFFC1A538 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH7 0xFFC1A43C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH7 0xFFC1A53C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH8 0xFFC1A440 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH8 0xFFC1A540 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH9 0xFFC1A444 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH9 0xFFC1A544 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH10 0xFFC1A448 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH10 0xFFC1A548 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH11 0xFFC1A44C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH11 0xFFC1A54C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH12 0xFFC1A450 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH12 0xFFC1A550 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH13 0xFFC1A454 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH13 0xFFC1A554 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH14 0xFFC1A458 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH14 0xFFC1A558 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH15 0xFFC1A45C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH15 0xFFC1A55C /* PVP0 Threshold Value */
-#define PVP0_THC0_HHPOS 0xFFC1A460 /* PVP0 Window start X-coordinate */
-#define PVP0_THC1_HHPOS 0xFFC1A560 /* PVP0 Window start X-coordinate */
-#define PVP0_THC0_HVPOS 0xFFC1A464 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC1_HVPOS 0xFFC1A564 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC0_HHCNT 0xFFC1A468 /* PVP0 Window width in X dimension */
-#define PVP0_THC1_HHCNT 0xFFC1A568 /* PVP0 Window width in X dimension */
-#define PVP0_THC0_HVCNT 0xFFC1A46C /* PVP0 Window width in Y dimension */
-#define PVP0_THC1_HVCNT 0xFFC1A56C /* PVP0 Window width in Y dimension */
-#define PVP0_THC0_RHPOS 0xFFC1A470 /* PVP0 Window start X-coordinate */
-#define PVP0_THC1_RHPOS 0xFFC1A570 /* PVP0 Window start X-coordinate */
-#define PVP0_THC0_RVPOS 0xFFC1A474 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC1_RVPOS 0xFFC1A574 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC0_RHCNT 0xFFC1A478 /* PVP0 Window width in X dimension */
-#define PVP0_THC1_RHCNT 0xFFC1A578 /* PVP0 Window width in X dimension */
-#define PVP0_THC0_RVCNT 0xFFC1A47C /* PVP0 Window width in Y dimension */
-#define PVP0_THC1_RVCNT 0xFFC1A57C /* PVP0 Window width in Y dimension */
-#define PVP0_THC0_HFCNT_STAT 0xFFC1A480 /* PVP0 Current Frame counter */
-#define PVP0_THC1_HFCNT_STAT 0xFFC1A580 /* PVP0 Current Frame counter */
-#define PVP0_THC0_HCNT0_STAT 0xFFC1A484 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT0_STAT 0xFFC1A584 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT1_STAT 0xFFC1A488 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT1_STAT 0xFFC1A588 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT2_STAT 0xFFC1A48C /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT2_STAT 0xFFC1A58C /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT3_STAT 0xFFC1A490 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT3_STAT 0xFFC1A590 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT4_STAT 0xFFC1A494 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT4_STAT 0xFFC1A594 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT5_STAT 0xFFC1A498 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT5_STAT 0xFFC1A598 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT6_STAT 0xFFC1A49C /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT6_STAT 0xFFC1A59C /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT7_STAT 0xFFC1A4A0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT7_STAT 0xFFC1A5A0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT8_STAT 0xFFC1A4A4 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT8_STAT 0xFFC1A5A4 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT9_STAT 0xFFC1A4A8 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT9_STAT 0xFFC1A5A8 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT10_STAT 0xFFC1A4AC /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT10_STAT 0xFFC1A5AC /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT11_STAT 0xFFC1A4B0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT11_STAT 0xFFC1A5B0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT12_STAT 0xFFC1A4B4 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT12_STAT 0xFFC1A5B4 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT13_STAT 0xFFC1A4B8 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT13_STAT 0xFFC1A5B8 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT14_STAT 0xFFC1A4BC /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT14_STAT 0xFFC1A5BC /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT15_STAT 0xFFC1A4C0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT15_STAT 0xFFC1A5C0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_RREP_STAT 0xFFC1A4C4 /* PVP0 Number of RLE Reports */
-#define PVP0_THC1_RREP_STAT 0xFFC1A5C4 /* PVP0 Number of RLE Reports */
-#define PVP0_PMA_CFG 0xFFC1A600 /* PVP0 PMA Configuration Register */
-
-#endif /* _DEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
deleted file mode 100644
index 3933e91..0000000
--- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
+++ /dev/null
@@ -1,3596 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF60X_H
-#define _DEF_BF60X_H
-
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
-/* ************************************************************** */
-
-
-/* =========================
- CNT Registers
- ========================= */
-
-/* =========================
- CNT0
- ========================= */
-#define CNT_CONFIG 0xFFC00400 /* CNT0 Configuration Register */
-#define CNT_IMASK 0xFFC00404 /* CNT0 Interrupt Mask Register */
-#define CNT_STATUS 0xFFC00408 /* CNT0 Status Register */
-#define CNT_COMMAND 0xFFC0040C /* CNT0 Command Register */
-#define CNT_DEBOUNCE 0xFFC00410 /* CNT0 Debounce Register */
-#define CNT_COUNTER 0xFFC00414 /* CNT0 Counter Register */
-#define CNT_MAX 0xFFC00418 /* CNT0 Maximum Count Register */
-#define CNT_MIN 0xFFC0041C /* CNT0 Minimum Count Register */
-
-
-/* =========================
- RSI Registers
- ========================= */
-
-#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */
-#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */
-#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */
-#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */
-#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */
-#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */
-#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */
-#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */
-#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */
-#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */
-#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */
-#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */
-#define RSI_MASK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
-#define RSI_MASK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 This register contains bit to dis CCS gen */
-#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */
-#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Acknowledge Timeout Register */
-#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
-#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */
-#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */
-#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */
-#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */
-#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */
-#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Identification Register */
-#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Identification Register */
-#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Identification Register */
-#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Identification Register */
-
-/* =========================
- CAN Registers
- ========================= */
-
-/* =========================
- CAN0
- ========================= */
-#define CAN0_MC1 0xFFC00A00 /* CAN0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xFFC00A04 /* CAN0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xFFC00A08 /* CAN0 Transmission Request Set Register 1 */
-#define CAN0_TRR1 0xFFC00A0C /* CAN0 Transmission Request Reset Register 1 */
-#define CAN0_TA1 0xFFC00A10 /* CAN0 Transmission Acknowledge Register 1 */
-#define CAN0_AA1 0xFFC00A14 /* CAN0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xFFC00A18 /* CAN0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xFFC00A1C /* CAN0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xFFC00A20 /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xFFC00A24 /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xFFC00A28 /* CAN0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xFFC00A2C /* CAN0 Remote Frame Handling Register 1 */
-#define CAN0_OPSS1 0xFFC00A30 /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
-#define CAN0_MC2 0xFFC00A40 /* CAN0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xFFC00A44 /* CAN0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xFFC00A48 /* CAN0 Transmission Request Set Register 2 */
-#define CAN0_TRR2 0xFFC00A4C /* CAN0 Transmission Request Reset Register 2 */
-#define CAN0_TA2 0xFFC00A50 /* CAN0 Transmission Acknowledge Register 2 */
-#define CAN0_AA2 0xFFC00A54 /* CAN0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xFFC00A58 /* CAN0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xFFC00A5C /* CAN0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xFFC00A60 /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xFFC00A64 /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xFFC00A68 /* CAN0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xFFC00A6C /* CAN0 Remote Frame Handling Register 2 */
-#define CAN0_OPSS2 0xFFC00A70 /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
-#define CAN0_CLOCK 0xFFC00A80 /* CAN0 Clock Register */
-#define CAN0_TIMING 0xFFC00A84 /* CAN0 Timing Register */
-#define CAN0_DEBUG 0xFFC00A88 /* CAN0 Debug Register */
-#define CAN0_STATUS 0xFFC00A8C /* CAN0 Status Register */
-#define CAN0_CEC 0xFFC00A90 /* CAN0 Error Counter Register */
-#define CAN0_GIS 0xFFC00A94 /* CAN0 Global CAN Interrupt Status */
-#define CAN0_GIM 0xFFC00A98 /* CAN0 Global CAN Interrupt Mask */
-#define CAN0_GIF 0xFFC00A9C /* CAN0 Global CAN Interrupt Flag */
-#define CAN0_CONTROL 0xFFC00AA0 /* CAN0 CAN Master Control Register */
-#define CAN0_INTR 0xFFC00AA4 /* CAN0 Interrupt Pending Register */
-#define CAN0_MBTD 0xFFC00AAC /* CAN0 Temporary Mailbox Disable Register */
-#define CAN0_EWR 0xFFC00AB0 /* CAN0 Error Counter Warning Level Register */
-#define CAN0_ESR 0xFFC00AB4 /* CAN0 Error Status Register */
-#define CAN0_UCCNT 0xFFC00AC4 /* CAN0 Universal Counter Register */
-#define CAN0_UCRC 0xFFC00AC8 /* CAN0 Universal Counter Reload/Capture Register */
-#define CAN0_UCCNF 0xFFC00ACC /* CAN0 Universal Counter Configuration Mode Register */
-#define CAN0_AM00L 0xFFC00B00 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM01L 0xFFC00B08 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM02L 0xFFC00B10 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM03L 0xFFC00B18 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM04L 0xFFC00B20 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM05L 0xFFC00B28 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM06L 0xFFC00B30 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM07L 0xFFC00B38 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM08L 0xFFC00B40 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM09L 0xFFC00B48 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM10L 0xFFC00B50 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM11L 0xFFC00B58 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM12L 0xFFC00B60 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM13L 0xFFC00B68 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM14L 0xFFC00B70 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM15L 0xFFC00B78 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM16L 0xFFC00B80 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM17L 0xFFC00B88 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM18L 0xFFC00B90 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM19L 0xFFC00B98 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM20L 0xFFC00BA0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM21L 0xFFC00BA8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM22L 0xFFC00BB0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM23L 0xFFC00BB8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM24L 0xFFC00BC0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM25L 0xFFC00BC8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM26L 0xFFC00BD0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM27L 0xFFC00BD8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM28L 0xFFC00BE0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM29L 0xFFC00BE8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM30L 0xFFC00BF0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM31L 0xFFC00BF8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM00H 0xFFC00B04 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM01H 0xFFC00B0C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM02H 0xFFC00B14 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM03H 0xFFC00B1C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM04H 0xFFC00B24 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM05H 0xFFC00B2C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM06H 0xFFC00B34 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM07H 0xFFC00B3C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM08H 0xFFC00B44 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM09H 0xFFC00B4C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM10H 0xFFC00B54 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM11H 0xFFC00B5C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM12H 0xFFC00B64 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM13H 0xFFC00B6C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM14H 0xFFC00B74 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM15H 0xFFC00B7C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM16H 0xFFC00B84 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM17H 0xFFC00B8C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM18H 0xFFC00B94 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM19H 0xFFC00B9C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM20H 0xFFC00BA4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM21H 0xFFC00BAC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM22H 0xFFC00BB4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM23H 0xFFC00BBC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM24H 0xFFC00BC4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM25H 0xFFC00BCC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM26H 0xFFC00BD4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM27H 0xFFC00BDC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM28H 0xFFC00BE4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM29H 0xFFC00BEC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM30H 0xFFC00BF4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM31H 0xFFC00BFC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_MB00_DATA0 0xFFC00C00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB01_DATA0 0xFFC00C20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB02_DATA0 0xFFC00C40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB03_DATA0 0xFFC00C60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB04_DATA0 0xFFC00C80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB05_DATA0 0xFFC00CA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB06_DATA0 0xFFC00CC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB07_DATA0 0xFFC00CE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB08_DATA0 0xFFC00D00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB09_DATA0 0xFFC00D20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB10_DATA0 0xFFC00D40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB11_DATA0 0xFFC00D60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB12_DATA0 0xFFC00D80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB13_DATA0 0xFFC00DA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB14_DATA0 0xFFC00DC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB15_DATA0 0xFFC00DE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB16_DATA0 0xFFC00E00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB17_DATA0 0xFFC00E20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB18_DATA0 0xFFC00E40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB19_DATA0 0xFFC00E60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB20_DATA0 0xFFC00E80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB21_DATA0 0xFFC00EA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB22_DATA0 0xFFC00EC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB23_DATA0 0xFFC00EE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB24_DATA0 0xFFC00F00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB25_DATA0 0xFFC00F20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB26_DATA0 0xFFC00F40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB27_DATA0 0xFFC00F60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB28_DATA0 0xFFC00F80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB29_DATA0 0xFFC00FA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB30_DATA0 0xFFC00FC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB31_DATA0 0xFFC00FE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB00_DATA1 0xFFC00C04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB01_DATA1 0xFFC00C24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB02_DATA1 0xFFC00C44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB03_DATA1 0xFFC00C64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB04_DATA1 0xFFC00C84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB05_DATA1 0xFFC00CA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB06_DATA1 0xFFC00CC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB07_DATA1 0xFFC00CE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB08_DATA1 0xFFC00D04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB09_DATA1 0xFFC00D24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB10_DATA1 0xFFC00D44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB11_DATA1 0xFFC00D64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB12_DATA1 0xFFC00D84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB13_DATA1 0xFFC00DA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB14_DATA1 0xFFC00DC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB15_DATA1 0xFFC00DE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB16_DATA1 0xFFC00E04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB17_DATA1 0xFFC00E24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB18_DATA1 0xFFC00E44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB19_DATA1 0xFFC00E64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB20_DATA1 0xFFC00E84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB21_DATA1 0xFFC00EA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB22_DATA1 0xFFC00EC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB23_DATA1 0xFFC00EE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB24_DATA1 0xFFC00F04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB25_DATA1 0xFFC00F24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB26_DATA1 0xFFC00F44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB27_DATA1 0xFFC00F64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB28_DATA1 0xFFC00F84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB29_DATA1 0xFFC00FA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB30_DATA1 0xFFC00FC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB31_DATA1 0xFFC00FE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB00_DATA2 0xFFC00C08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB01_DATA2 0xFFC00C28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB02_DATA2 0xFFC00C48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB03_DATA2 0xFFC00C68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB04_DATA2 0xFFC00C88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB05_DATA2 0xFFC00CA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB06_DATA2 0xFFC00CC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB07_DATA2 0xFFC00CE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB08_DATA2 0xFFC00D08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB09_DATA2 0xFFC00D28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB10_DATA2 0xFFC00D48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB11_DATA2 0xFFC00D68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB12_DATA2 0xFFC00D88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB13_DATA2 0xFFC00DA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB14_DATA2 0xFFC00DC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB15_DATA2 0xFFC00DE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB16_DATA2 0xFFC00E08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB17_DATA2 0xFFC00E28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB18_DATA2 0xFFC00E48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB19_DATA2 0xFFC00E68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB20_DATA2 0xFFC00E88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB21_DATA2 0xFFC00EA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB22_DATA2 0xFFC00EC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB23_DATA2 0xFFC00EE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB24_DATA2 0xFFC00F08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB25_DATA2 0xFFC00F28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB26_DATA2 0xFFC00F48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB27_DATA2 0xFFC00F68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB28_DATA2 0xFFC00F88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB29_DATA2 0xFFC00FA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB30_DATA2 0xFFC00FC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB31_DATA2 0xFFC00FE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB00_DATA3 0xFFC00C0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB01_DATA3 0xFFC00C2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB02_DATA3 0xFFC00C4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB03_DATA3 0xFFC00C6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB04_DATA3 0xFFC00C8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB05_DATA3 0xFFC00CAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB06_DATA3 0xFFC00CCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB07_DATA3 0xFFC00CEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB08_DATA3 0xFFC00D0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB09_DATA3 0xFFC00D2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB10_DATA3 0xFFC00D4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB11_DATA3 0xFFC00D6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB12_DATA3 0xFFC00D8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB13_DATA3 0xFFC00DAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB14_DATA3 0xFFC00DCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB15_DATA3 0xFFC00DEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB16_DATA3 0xFFC00E0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB17_DATA3 0xFFC00E2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB18_DATA3 0xFFC00E4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB19_DATA3 0xFFC00E6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB20_DATA3 0xFFC00E8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB21_DATA3 0xFFC00EAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB22_DATA3 0xFFC00ECC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB23_DATA3 0xFFC00EEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB24_DATA3 0xFFC00F0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB25_DATA3 0xFFC00F2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB26_DATA3 0xFFC00F4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB27_DATA3 0xFFC00F6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB28_DATA3 0xFFC00F8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB29_DATA3 0xFFC00FAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB30_DATA3 0xFFC00FCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB31_DATA3 0xFFC00FEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB00_LENGTH 0xFFC00C10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB01_LENGTH 0xFFC00C30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB02_LENGTH 0xFFC00C50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB03_LENGTH 0xFFC00C70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB04_LENGTH 0xFFC00C90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB05_LENGTH 0xFFC00CB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB06_LENGTH 0xFFC00CD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB07_LENGTH 0xFFC00CF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB08_LENGTH 0xFFC00D10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB09_LENGTH 0xFFC00D30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB10_LENGTH 0xFFC00D50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB11_LENGTH 0xFFC00D70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB12_LENGTH 0xFFC00D90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB13_LENGTH 0xFFC00DB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB14_LENGTH 0xFFC00DD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB15_LENGTH 0xFFC00DF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB16_LENGTH 0xFFC00E10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB17_LENGTH 0xFFC00E30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB18_LENGTH 0xFFC00E50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB19_LENGTH 0xFFC00E70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB20_LENGTH 0xFFC00E90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB21_LENGTH 0xFFC00EB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB22_LENGTH 0xFFC00ED0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB23_LENGTH 0xFFC00EF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB24_LENGTH 0xFFC00F10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB25_LENGTH 0xFFC00F30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB26_LENGTH 0xFFC00F50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB27_LENGTH 0xFFC00F70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB28_LENGTH 0xFFC00F90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB29_LENGTH 0xFFC00FB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB30_LENGTH 0xFFC00FD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB31_LENGTH 0xFFC00FF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB00_TIMESTAMP 0xFFC00C14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB01_TIMESTAMP 0xFFC00C34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB02_TIMESTAMP 0xFFC00C54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB03_TIMESTAMP 0xFFC00C74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB04_TIMESTAMP 0xFFC00C94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB05_TIMESTAMP 0xFFC00CB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB06_TIMESTAMP 0xFFC00CD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB07_TIMESTAMP 0xFFC00CF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB08_TIMESTAMP 0xFFC00D14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB09_TIMESTAMP 0xFFC00D34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB10_TIMESTAMP 0xFFC00D54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB11_TIMESTAMP 0xFFC00D74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB12_TIMESTAMP 0xFFC00D94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB13_TIMESTAMP 0xFFC00DB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB14_TIMESTAMP 0xFFC00DD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB15_TIMESTAMP 0xFFC00DF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB16_TIMESTAMP 0xFFC00E14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB17_TIMESTAMP 0xFFC00E34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB18_TIMESTAMP 0xFFC00E54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB19_TIMESTAMP 0xFFC00E74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB20_TIMESTAMP 0xFFC00E94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB21_TIMESTAMP 0xFFC00EB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB22_TIMESTAMP 0xFFC00ED4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB23_TIMESTAMP 0xFFC00EF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB24_TIMESTAMP 0xFFC00F14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB25_TIMESTAMP 0xFFC00F34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB26_TIMESTAMP 0xFFC00F54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB27_TIMESTAMP 0xFFC00F74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB28_TIMESTAMP 0xFFC00F94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB29_TIMESTAMP 0xFFC00FB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB30_TIMESTAMP 0xFFC00FD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB31_TIMESTAMP 0xFFC00FF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB00_ID0 0xFFC00C18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB01_ID0 0xFFC00C38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB02_ID0 0xFFC00C58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB03_ID0 0xFFC00C78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB04_ID0 0xFFC00C98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB05_ID0 0xFFC00CB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB06_ID0 0xFFC00CD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB07_ID0 0xFFC00CF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB08_ID0 0xFFC00D18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB09_ID0 0xFFC00D38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB10_ID0 0xFFC00D58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB11_ID0 0xFFC00D78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB12_ID0 0xFFC00D98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB13_ID0 0xFFC00DB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB14_ID0 0xFFC00DD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB15_ID0 0xFFC00DF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB16_ID0 0xFFC00E18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB17_ID0 0xFFC00E38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB18_ID0 0xFFC00E58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB19_ID0 0xFFC00E78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB20_ID0 0xFFC00E98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB21_ID0 0xFFC00EB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB22_ID0 0xFFC00ED8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB23_ID0 0xFFC00EF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB24_ID0 0xFFC00F18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB25_ID0 0xFFC00F38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB26_ID0 0xFFC00F58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB27_ID0 0xFFC00F78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB28_ID0 0xFFC00F98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB29_ID0 0xFFC00FB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB30_ID0 0xFFC00FD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB31_ID0 0xFFC00FF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB00_ID1 0xFFC00C1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB01_ID1 0xFFC00C3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB02_ID1 0xFFC00C5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB03_ID1 0xFFC00C7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB04_ID1 0xFFC00C9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB05_ID1 0xFFC00CBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB06_ID1 0xFFC00CDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB07_ID1 0xFFC00CFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB08_ID1 0xFFC00D1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB09_ID1 0xFFC00D3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB10_ID1 0xFFC00D5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB11_ID1 0xFFC00D7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB12_ID1 0xFFC00D9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB13_ID1 0xFFC00DBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB14_ID1 0xFFC00DDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB15_ID1 0xFFC00DFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB16_ID1 0xFFC00E1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB17_ID1 0xFFC00E3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB18_ID1 0xFFC00E5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB19_ID1 0xFFC00E7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB20_ID1 0xFFC00E9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB21_ID1 0xFFC00EBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB22_ID1 0xFFC00EDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB23_ID1 0xFFC00EFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB24_ID1 0xFFC00F1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB25_ID1 0xFFC00F3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB26_ID1 0xFFC00F5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB27_ID1 0xFFC00F7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB28_ID1 0xFFC00F9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB29_ID1 0xFFC00FBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB30_ID1 0xFFC00FDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB31_ID1 0xFFC00FFC /* CAN0 Mailbox Word 7 Register */
-
-/* =========================
- LINK PORT Registers
- ========================= */
-#define LP0_CTL 0xFFC01000 /* LP0 Control Register */
-#define LP0_STAT 0xFFC01004 /* LP0 Status Register */
-#define LP0_DIV 0xFFC01008 /* LP0 Clock Divider Value */
-#define LP0_CNT 0xFFC0100C /* LP0 Current Count Value of Clock Divider */
-#define LP0_TX 0xFFC01010 /* LP0 Transmit Buffer */
-#define LP0_RX 0xFFC01014 /* LP0 Receive Buffer */
-#define LP0_TXIN_SHDW 0xFFC01018 /* LP0 Shadow Input Transmit Buffer */
-#define LP0_TXOUT_SHDW 0xFFC0101C /* LP0 Shadow Output Transmit Buffer */
-#define LP1_CTL 0xFFC01100 /* LP1 Control Register */
-#define LP1_STAT 0xFFC01104 /* LP1 Status Register */
-#define LP1_DIV 0xFFC01108 /* LP1 Clock Divider Value */
-#define LP1_CNT 0xFFC0110C /* LP1 Current Count Value of Clock Divider */
-#define LP1_TX 0xFFC01110 /* LP1 Transmit Buffer */
-#define LP1_RX 0xFFC01114 /* LP1 Receive Buffer */
-#define LP1_TXIN_SHDW 0xFFC01118 /* LP1 Shadow Input Transmit Buffer */
-#define LP1_TXOUT_SHDW 0xFFC0111C /* LP1 Shadow Output Transmit Buffer */
-#define LP2_CTL 0xFFC01200 /* LP2 Control Register */
-#define LP2_STAT 0xFFC01204 /* LP2 Status Register */
-#define LP2_DIV 0xFFC01208 /* LP2 Clock Divider Value */
-#define LP2_CNT 0xFFC0120C /* LP2 Current Count Value of Clock Divider */
-#define LP2_TX 0xFFC01210 /* LP2 Transmit Buffer */
-#define LP2_RX 0xFFC01214 /* LP2 Receive Buffer */
-#define LP2_TXIN_SHDW 0xFFC01218 /* LP2 Shadow Input Transmit Buffer */
-#define LP2_TXOUT_SHDW 0xFFC0121C /* LP2 Shadow Output Transmit Buffer */
-#define LP3_CTL 0xFFC01300 /* LP3 Control Register */
-#define LP3_STAT 0xFFC01304 /* LP3 Status Register */
-#define LP3_DIV 0xFFC01308 /* LP3 Clock Divider Value */
-#define LP3_CNT 0xFFC0130C /* LP3 Current Count Value of Clock Divider */
-#define LP3_TX 0xFFC01310 /* LP3 Transmit Buffer */
-#define LP3_RX 0xFFC01314 /* LP3 Receive Buffer */
-#define LP3_TXIN_SHDW 0xFFC01318 /* LP3 Shadow Input Transmit Buffer */
-#define LP3_TXOUT_SHDW 0xFFC0131C /* LP3 Shadow Output Transmit Buffer */
-
-/* =========================
- TIMER Registers
- ========================= */
-#define TIMER_REVID 0xFFC01400 /* GPTIMER Timer IP Version ID */
-#define TIMER_RUN 0xFFC01404 /* GPTIMER Timer Run Register */
-#define TIMER_RUN_SET 0xFFC01408 /* GPTIMER Run Register Alias to Set */
-#define TIMER_RUN_CLR 0xFFC0140C /* GPTIMER Run Register Alias to Clear */
-#define TIMER_STOP_CFG 0xFFC01410 /* GPTIMER Stop Config Register */
-#define TIMER_STOP_CFG_SET 0xFFC01414 /* GPTIMER Stop Config Alias to Set */
-#define TIMER_STOP_CFG_CLR 0xFFC01418 /* GPTIMER Stop Config Alias to Clear */
-#define TIMER_DATA_IMSK 0xFFC0141C /* GPTIMER Data Interrupt Mask register */
-#define TIMER_STAT_IMSK 0xFFC01420 /* GPTIMER Status Interrupt Mask register */
-#define TIMER_TRG_MSK 0xFFC01424 /* GPTIMER Output Trigger Mask register */
-#define TIMER_TRG_IE 0xFFC01428 /* GPTIMER Slave Trigger Enable register */
-#define TIMER_DATA_ILAT 0xFFC0142C /* GPTIMER Data Interrupt Register */
-#define TIMER_STAT_ILAT 0xFFC01430 /* GPTIMER Status (Error) Interrupt Register */
-#define TIMER_ERR_TYPE 0xFFC01434 /* GPTIMER Register Indicating Type of Error */
-#define TIMER_BCAST_PER 0xFFC01438 /* GPTIMER Broadcast Period */
-#define TIMER_BCAST_WID 0xFFC0143C /* GPTIMER Broadcast Width */
-#define TIMER_BCAST_DLY 0xFFC01440 /* GPTIMER Broadcast Delay */
-
-/* =========================
- TIMER0~7
- ========================= */
-#define TIMER0_CONFIG 0xFFC01460 /* TIMER0 Per Timer Config Register */
-#define TIMER0_COUNTER 0xFFC01464 /* TIMER0 Per Timer Counter Register */
-#define TIMER0_PERIOD 0xFFC01468 /* TIMER0 Per Timer Period Register */
-#define TIMER0_WIDTH 0xFFC0146C /* TIMER0 Per Timer Width Register */
-#define TIMER0_DELAY 0xFFC01470 /* TIMER0 Per Timer Delay Register */
-
-#define TIMER1_CONFIG 0xFFC01480 /* TIMER1 Per Timer Config Register */
-#define TIMER1_COUNTER 0xFFC01484 /* TIMER1 Per Timer Counter Register */
-#define TIMER1_PERIOD 0xFFC01488 /* TIMER1 Per Timer Period Register */
-#define TIMER1_WIDTH 0xFFC0148C /* TIMER1 Per Timer Width Register */
-#define TIMER1_DELAY 0xFFC01490 /* TIMER1 Per Timer Delay Register */
-
-#define TIMER2_CONFIG 0xFFC014A0 /* TIMER2 Per Timer Config Register */
-#define TIMER2_COUNTER 0xFFC014A4 /* TIMER2 Per Timer Counter Register */
-#define TIMER2_PERIOD 0xFFC014A8 /* TIMER2 Per Timer Period Register */
-#define TIMER2_WIDTH 0xFFC014AC /* TIMER2 Per Timer Width Register */
-#define TIMER2_DELAY 0xFFC014B0 /* TIMER2 Per Timer Delay Register */
-
-#define TIMER3_CONFIG 0xFFC014C0 /* TIMER3 Per Timer Config Register */
-#define TIMER3_COUNTER 0xFFC014C4 /* TIMER3 Per Timer Counter Register */
-#define TIMER3_PERIOD 0xFFC014C8 /* TIMER3 Per Timer Period Register */
-#define TIMER3_WIDTH 0xFFC014CC /* TIMER3 Per Timer Width Register */
-#define TIMER3_DELAY 0xFFC014D0 /* TIMER3 Per Timer Delay Register */
-
-#define TIMER4_CONFIG 0xFFC014E0 /* TIMER4 Per Timer Config Register */
-#define TIMER4_COUNTER 0xFFC014E4 /* TIMER4 Per Timer Counter Register */
-#define TIMER4_PERIOD 0xFFC014E8 /* TIMER4 Per Timer Period Register */
-#define TIMER4_WIDTH 0xFFC014EC /* TIMER4 Per Timer Width Register */
-#define TIMER4_DELAY 0xFFC014F0 /* TIMER4 Per Timer Delay Register */
-
-#define TIMER5_CONFIG 0xFFC01500 /* TIMER5 Per Timer Config Register */
-#define TIMER5_COUNTER 0xFFC01504 /* TIMER5 Per Timer Counter Register */
-#define TIMER5_PERIOD 0xFFC01508 /* TIMER5 Per Timer Period Register */
-#define TIMER5_WIDTH 0xFFC0150C /* TIMER5 Per Timer Width Register */
-#define TIMER5_DELAY 0xFFC01510 /* TIMER5 Per Timer Delay Register */
-
-#define TIMER6_CONFIG 0xFFC01520 /* TIMER6 Per Timer Config Register */
-#define TIMER6_COUNTER 0xFFC01524 /* TIMER6 Per Timer Counter Register */
-#define TIMER6_PERIOD 0xFFC01528 /* TIMER6 Per Timer Period Register */
-#define TIMER6_WIDTH 0xFFC0152C /* TIMER6 Per Timer Width Register */
-#define TIMER6_DELAY 0xFFC01530 /* TIMER6 Per Timer Delay Register */
-
-#define TIMER7_CONFIG 0xFFC01540 /* TIMER7 Per Timer Config Register */
-#define TIMER7_COUNTER 0xFFC01544 /* TIMER7 Per Timer Counter Register */
-#define TIMER7_PERIOD 0xFFC01548 /* TIMER7 Per Timer Period Register */
-#define TIMER7_WIDTH 0xFFC0154C /* TIMER7 Per Timer Width Register */
-#define TIMER7_DELAY 0xFFC01550 /* TIMER7 Per Timer Delay Register */
-
-/* =========================
- CRC Registers
- ========================= */
-
-/* =========================
- CRC0
- ========================= */
-#define REG_CRC0_CTL 0xFFC01C00 /* CRC0 Control Register */
-#define REG_CRC0_DCNT 0xFFC01C04 /* CRC0 Data Word Count Register */
-#define REG_CRC0_DCNTRLD 0xFFC01C08 /* CRC0 Data Word Count Reload Register */
-#define REG_CRC0_COMP 0xFFC01C14 /* CRC0 DATA Compare Register */
-#define REG_CRC0_FILLVAL 0xFFC01C18 /* CRC0 Fill Value Register */
-#define REG_CRC0_DFIFO 0xFFC01C1C /* CRC0 DATA FIFO Register */
-#define REG_CRC0_INEN 0xFFC01C20 /* CRC0 Interrupt Enable Register */
-#define REG_CRC0_INEN_SET 0xFFC01C24 /* CRC0 Interrupt Enable Set Register */
-#define REG_CRC0_INEN_CLR 0xFFC01C28 /* CRC0 Interrupt Enable Clear Register */
-#define REG_CRC0_POLY 0xFFC01C2C /* CRC0 Polynomial Register */
-#define REG_CRC0_STAT 0xFFC01C40 /* CRC0 Status Register */
-#define REG_CRC0_DCNTCAP 0xFFC01C44 /* CRC0 DATA Count Capture Register */
-#define REG_CRC0_RESULT_FIN 0xFFC01C4C /* CRC0 Final CRC Result Register */
-#define REG_CRC0_RESULT_CUR 0xFFC01C50 /* CRC0 Current CRC Result Register */
-#define REG_CRC0_REVID 0xFFC01C60 /* CRC0 Revision ID Register */
-
-/* =========================
- CRC1
- ========================= */
-#define REG_CRC1_CTL 0xFFC01D00 /* CRC1 Control Register */
-#define REG_CRC1_DCNT 0xFFC01D04 /* CRC1 Data Word Count Register */
-#define REG_CRC1_DCNTRLD 0xFFC01D08 /* CRC1 Data Word Count Reload Register */
-#define REG_CRC1_COMP 0xFFC01D14 /* CRC1 DATA Compare Register */
-#define REG_CRC1_FILLVAL 0xFFC01D18 /* CRC1 Fill Value Register */
-#define REG_CRC1_DFIFO 0xFFC01D1C /* CRC1 DATA FIFO Register */
-#define REG_CRC1_INEN 0xFFC01D20 /* CRC1 Interrupt Enable Register */
-#define REG_CRC1_INEN_SET 0xFFC01D24 /* CRC1 Interrupt Enable Set Register */
-#define REG_CRC1_INEN_CLR 0xFFC01D28 /* CRC1 Interrupt Enable Clear Register */
-#define REG_CRC1_POLY 0xFFC01D2C /* CRC1 Polynomial Register */
-#define REG_CRC1_STAT 0xFFC01D40 /* CRC1 Status Register */
-#define REG_CRC1_DCNTCAP 0xFFC01D44 /* CRC1 DATA Count Capture Register */
-#define REG_CRC1_RESULT_FIN 0xFFC01D4C /* CRC1 Final CRC Result Register */
-#define REG_CRC1_RESULT_CUR 0xFFC01D50 /* CRC1 Current CRC Result Register */
-#define REG_CRC1_REVID 0xFFC01D60 /* CRC1 Revision ID Register */
-
-/* =========================
- TWI Registers
- ========================= */
-
-/* =========================
- TWI0
- ========================= */
-#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */
-#define TWI0_CONTROL 0xFFC01E04 /* TWI0 Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01E08 /* TWI0 Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC01E0C /* TWI0 Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01E10 /* TWI0 Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01E14 /* TWI0 Master Mode Control Registers */
-#define TWI0_MASTER_STAT 0xFFC01E18 /* TWI0 Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC01E1C /* TWI0 Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01E20 /* TWI0 Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01E24 /* TWI0 Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01E28 /* TWI0 FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC01E2C /* TWI0 FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01E80 /* TWI0 FIFO Transmit Data Single-Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01E84 /* TWI0 FIFO Transmit Data Double-Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01E88 /* TWI0 FIFO Transmit Data Single-Byte Register */
-#define TWI0_RCV_DATA16 0xFFC01E8C /* TWI0 FIFO Transmit Data Double-Byte Register */
-
-/* =========================
- TWI1
- ========================= */
-#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */
-#define TWI1_CONTROL 0xFFC01F04 /* TWI1 Control Register */
-#define TWI1_SLAVE_CTL 0xFFC01F08 /* TWI1 Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC01F0C /* TWI1 Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC01F10 /* TWI1 Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC01F14 /* TWI1 Master Mode Control Registers */
-#define TWI1_MASTER_STAT 0xFFC01F18 /* TWI1 Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC01F1C /* TWI1 Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC01F20 /* TWI1 Interrupt Status Register */
-#define TWI1_INT_MASK 0xFFC01F24 /* TWI1 Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC01F28 /* TWI1 FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC01F2C /* TWI1 FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC01F80 /* TWI1 FIFO Transmit Data Single-Byte Register */
-#define TWI1_XMT_DATA16 0xFFC01F84 /* TWI1 FIFO Transmit Data Double-Byte Register */
-#define TWI1_RCV_DATA8 0xFFC01F88 /* TWI1 FIFO Transmit Data Single-Byte Register */
-#define TWI1_RCV_DATA16 0xFFC01F8C /* TWI1 FIFO Transmit Data Double-Byte Register */
-
-
-/* =========================
- UART Registers
- ========================= */
-
-/* =========================
- UART0
- ========================= */
-#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */
-#define UART0_CTL 0xFFC02004 /* UART0 Control Register */
-#define UART0_STAT 0xFFC02008 /* UART0 Status Register */
-#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */
-#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */
-#define UART0_IER 0xFFC02014 /* UART0 Interrupt Mask Register */
-#define UART0_IER_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */
-#define UART0_IER_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */
-#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */
-#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */
-#define UART0_TAIP 0xFFC02028 /* UART0 Transmit Address/Insert Pulse Register */
-#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */
-#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */
-#define UART0_TXDIV 0xFFC02034 /* UART0 Transmit Clock Devider Register */
-#define UART0_RXDIV 0xFFC02038 /* UART0 Receive Clock Devider Register */
-
-/* =========================
- UART1
- ========================= */
-#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */
-#define UART1_CTL 0xFFC02404 /* UART1 Control Register */
-#define UART1_STAT 0xFFC02408 /* UART1 Status Register */
-#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */
-#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */
-#define UART1_IER 0xFFC02414 /* UART1 Interrupt Mask Register */
-#define UART1_IER_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */
-#define UART1_IER_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */
-#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */
-#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */
-#define UART1_TAIP 0xFFC02428 /* UART1 Transmit Address/Insert Pulse Register */
-#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */
-#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */
-#define UART1_TXDIV 0xFFC02434 /* UART1 Transmit Clock Devider Register */
-#define UART1_RXDIV 0xFFC02438 /* UART1 Receive Clock Devider Register */
-
-
-/* =========================
- PORT Registers
- ========================= */
-
-/* =========================
- PORTA
- ========================= */
-#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable Register */
-#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set Register */
-#define PORTA_FER_CLEAR 0xFFC03008 /* PORTA Port x Function Enable Clear Register */
-#define PORTA_DATA 0xFFC0300C /* PORTA Port x GPIO Data Register */
-#define PORTA_DATA_SET 0xFFC03010 /* PORTA Port x GPIO Data Set Register */
-#define PORTA_DATA_CLEAR 0xFFC03014 /* PORTA Port x GPIO Data Clear Register */
-#define PORTA_DIR 0xFFC03018 /* PORTA Port x GPIO Direction Register */
-#define PORTA_DIR_SET 0xFFC0301C /* PORTA Port x GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xFFC03020 /* PORTA Port x GPIO Direction Clear Register */
-#define PORTA_INEN 0xFFC03024 /* PORTA Port x GPIO Input Enable Register */
-#define PORTA_INEN_SET 0xFFC03028 /* PORTA Port x GPIO Input Enable Set Register */
-#define PORTA_INEN_CLEAR 0xFFC0302C /* PORTA Port x GPIO Input Enable Clear Register */
-#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control Register */
-#define PORTA_DATA_TGL 0xFFC03034 /* PORTA Port x GPIO Input Enable Toggle Register */
-#define PORTA_POL 0xFFC03038 /* PORTA Port x GPIO Programming Inversion Register */
-#define PORTA_POL_SET 0xFFC0303C /* PORTA Port x GPIO Programming Inversion Set Register */
-#define PORTA_POL_CLEAR 0xFFC03040 /* PORTA Port x GPIO Programming Inversion Clear Register */
-#define PORTA_LOCK 0xFFC03044 /* PORTA Port x GPIO Lock Register */
-#define PORTA_REVID 0xFFC0307C /* PORTA Port x GPIO Revision ID */
-
-/* =========================
- PORTB
- ========================= */
-#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable Register */
-#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set Register */
-#define PORTB_FER_CLEAR 0xFFC03088 /* PORTB Port x Function Enable Clear Register */
-#define PORTB_DATA 0xFFC0308C /* PORTB Port x GPIO Data Register */
-#define PORTB_DATA_SET 0xFFC03090 /* PORTB Port x GPIO Data Set Register */
-#define PORTB_DATA_CLEAR 0xFFC03094 /* PORTB Port x GPIO Data Clear Register */
-#define PORTB_DIR 0xFFC03098 /* PORTB Port x GPIO Direction Register */
-#define PORTB_DIR_SET 0xFFC0309C /* PORTB Port x GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xFFC030A0 /* PORTB Port x GPIO Direction Clear Register */
-#define PORTB_INEN 0xFFC030A4 /* PORTB Port x GPIO Input Enable Register */
-#define PORTB_INEN_SET 0xFFC030A8 /* PORTB Port x GPIO Input Enable Set Register */
-#define PORTB_INEN_CLEAR 0xFFC030AC /* PORTB Port x GPIO Input Enable Clear Register */
-#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control Register */
-#define PORTB_DATA_TGL 0xFFC030B4 /* PORTB Port x GPIO Input Enable Toggle Register */
-#define PORTB_POL 0xFFC030B8 /* PORTB Port x GPIO Programming Inversion Register */
-#define PORTB_POL_SET 0xFFC030BC /* PORTB Port x GPIO Programming Inversion Set Register */
-#define PORTB_POL_CLEAR 0xFFC030C0 /* PORTB Port x GPIO Programming Inversion Clear Register */
-#define PORTB_LOCK 0xFFC030C4 /* PORTB Port x GPIO Lock Register */
-#define PORTB_REVID 0xFFC030FC /* PORTB Port x GPIO Revision ID */
-
-/* =========================
- PORTC
- ========================= */
-#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable Register */
-#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set Register */
-#define PORTC_FER_CLEAR 0xFFC03108 /* PORTC Port x Function Enable Clear Register */
-#define PORTC_DATA 0xFFC0310C /* PORTC Port x GPIO Data Register */
-#define PORTC_DATA_SET 0xFFC03110 /* PORTC Port x GPIO Data Set Register */
-#define PORTC_DATA_CLEAR 0xFFC03114 /* PORTC Port x GPIO Data Clear Register */
-#define PORTC_DIR 0xFFC03118 /* PORTC Port x GPIO Direction Register */
-#define PORTC_DIR_SET 0xFFC0311C /* PORTC Port x GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xFFC03120 /* PORTC Port x GPIO Direction Clear Register */
-#define PORTC_INEN 0xFFC03124 /* PORTC Port x GPIO Input Enable Register */
-#define PORTC_INEN_SET 0xFFC03128 /* PORTC Port x GPIO Input Enable Set Register */
-#define PORTC_INEN_CLEAR 0xFFC0312C /* PORTC Port x GPIO Input Enable Clear Register */
-#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control Register */
-#define PORTC_DATA_TGL 0xFFC03134 /* PORTC Port x GPIO Input Enable Toggle Register */
-#define PORTC_POL 0xFFC03138 /* PORTC Port x GPIO Programming Inversion Register */
-#define PORTC_POL_SET 0xFFC0313C /* PORTC Port x GPIO Programming Inversion Set Register */
-#define PORTC_POL_CLEAR 0xFFC03140 /* PORTC Port x GPIO Programming Inversion Clear Register */
-#define PORTC_LOCK 0xFFC03144 /* PORTC Port x GPIO Lock Register */
-#define PORTC_REVID 0xFFC0317C /* PORTC Port x GPIO Revision ID */
-
-/* =========================
- PORTD
- ========================= */
-#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable Register */
-#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set Register */
-#define PORTD_FER_CLEAR 0xFFC03188 /* PORTD Port x Function Enable Clear Register */
-#define PORTD_DATA 0xFFC0318C /* PORTD Port x GPIO Data Register */
-#define PORTD_DATA_SET 0xFFC03190 /* PORTD Port x GPIO Data Set Register */
-#define PORTD_DATA_CLEAR 0xFFC03194 /* PORTD Port x GPIO Data Clear Register */
-#define PORTD_DIR 0xFFC03198 /* PORTD Port x GPIO Direction Register */
-#define PORTD_DIR_SET 0xFFC0319C /* PORTD Port x GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xFFC031A0 /* PORTD Port x GPIO Direction Clear Register */
-#define PORTD_INEN 0xFFC031A4 /* PORTD Port x GPIO Input Enable Register */
-#define PORTD_INEN_SET 0xFFC031A8 /* PORTD Port x GPIO Input Enable Set Register */
-#define PORTD_INEN_CLEAR 0xFFC031AC /* PORTD Port x GPIO Input Enable Clear Register */
-#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control Register */
-#define PORTD_DATA_TGL 0xFFC031B4 /* PORTD Port x GPIO Input Enable Toggle Register */
-#define PORTD_POL 0xFFC031B8 /* PORTD Port x GPIO Programming Inversion Register */
-#define PORTD_POL_SET 0xFFC031BC /* PORTD Port x GPIO Programming Inversion Set Register */
-#define PORTD_POL_CLEAR 0xFFC031C0 /* PORTD Port x GPIO Programming Inversion Clear Register */
-#define PORTD_LOCK 0xFFC031C4 /* PORTD Port x GPIO Lock Register */
-#define PORTD_REVID 0xFFC031FC /* PORTD Port x GPIO Revision ID */
-
-/* =========================
- PORTE
- ========================= */
-#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable Register */
-#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set Register */
-#define PORTE_FER_CLEAR 0xFFC03208 /* PORTE Port x Function Enable Clear Register */
-#define PORTE_DATA 0xFFC0320C /* PORTE Port x GPIO Data Register */
-#define PORTE_DATA_SET 0xFFC03210 /* PORTE Port x GPIO Data Set Register */
-#define PORTE_DATA_CLEAR 0xFFC03214 /* PORTE Port x GPIO Data Clear Register */
-#define PORTE_DIR 0xFFC03218 /* PORTE Port x GPIO Direction Register */
-#define PORTE_DIR_SET 0xFFC0321C /* PORTE Port x GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xFFC03220 /* PORTE Port x GPIO Direction Clear Register */
-#define PORTE_INEN 0xFFC03224 /* PORTE Port x GPIO Input Enable Register */
-#define PORTE_INEN_SET 0xFFC03228 /* PORTE Port x GPIO Input Enable Set Register */
-#define PORTE_INEN_CLEAR 0xFFC0322C /* PORTE Port x GPIO Input Enable Clear Register */
-#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control Register */
-#define PORTE_DATA_TGL 0xFFC03234 /* PORTE Port x GPIO Input Enable Toggle Register */
-#define PORTE_POL 0xFFC03238 /* PORTE Port x GPIO Programming Inversion Register */
-#define PORTE_POL_SET 0xFFC0323C /* PORTE Port x GPIO Programming Inversion Set Register */
-#define PORTE_POL_CLEAR 0xFFC03240 /* PORTE Port x GPIO Programming Inversion Clear Register */
-#define PORTE_LOCK 0xFFC03244 /* PORTE Port x GPIO Lock Register */
-#define PORTE_REVID 0xFFC0327C /* PORTE Port x GPIO Revision ID */
-
-/* =========================
- PORTF
- ========================= */
-#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable Register */
-#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set Register */
-#define PORTF_FER_CLEAR 0xFFC03288 /* PORTF Port x Function Enable Clear Register */
-#define PORTF_DATA 0xFFC0328C /* PORTF Port x GPIO Data Register */
-#define PORTF_DATA_SET 0xFFC03290 /* PORTF Port x GPIO Data Set Register */
-#define PORTF_DATA_CLEAR 0xFFC03294 /* PORTF Port x GPIO Data Clear Register */
-#define PORTF_DIR 0xFFC03298 /* PORTF Port x GPIO Direction Register */
-#define PORTF_DIR_SET 0xFFC0329C /* PORTF Port x GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xFFC032A0 /* PORTF Port x GPIO Direction Clear Register */
-#define PORTF_INEN 0xFFC032A4 /* PORTF Port x GPIO Input Enable Register */
-#define PORTF_INEN_SET 0xFFC032A8 /* PORTF Port x GPIO Input Enable Set Register */
-#define PORTF_INEN_CLEAR 0xFFC032AC /* PORTF Port x GPIO Input Enable Clear Register */
-#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control Register */
-#define PORTF_DATA_TGL 0xFFC032B4 /* PORTF Port x GPIO Input Enable Toggle Register */
-#define PORTF_POL 0xFFC032B8 /* PORTF Port x GPIO Programming Inversion Register */
-#define PORTF_POL_SET 0xFFC032BC /* PORTF Port x GPIO Programming Inversion Set Register */
-#define PORTF_POL_CLEAR 0xFFC032C0 /* PORTF Port x GPIO Programming Inversion Clear Register */
-#define PORTF_LOCK 0xFFC032C4 /* PORTF Port x GPIO Lock Register */
-#define PORTF_REVID 0xFFC032FC /* PORTF Port x GPIO Revision ID */
-
-/* =========================
- PORTG
- ========================= */
-#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable Register */
-#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set Register */
-#define PORTG_FER_CLEAR 0xFFC03308 /* PORTG Port x Function Enable Clear Register */
-#define PORTG_DATA 0xFFC0330C /* PORTG Port x GPIO Data Register */
-#define PORTG_DATA_SET 0xFFC03310 /* PORTG Port x GPIO Data Set Register */
-#define PORTG_DATA_CLEAR 0xFFC03314 /* PORTG Port x GPIO Data Clear Register */
-#define PORTG_DIR 0xFFC03318 /* PORTG Port x GPIO Direction Register */
-#define PORTG_DIR_SET 0xFFC0331C /* PORTG Port x GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xFFC03320 /* PORTG Port x GPIO Direction Clear Register */
-#define PORTG_INEN 0xFFC03324 /* PORTG Port x GPIO Input Enable Register */
-#define PORTG_INEN_SET 0xFFC03328 /* PORTG Port x GPIO Input Enable Set Register */
-#define PORTG_INEN_CLEAR 0xFFC0332C /* PORTG Port x GPIO Input Enable Clear Register */
-#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control Register */
-#define PORTG_DATA_TGL 0xFFC03334 /* PORTG Port x GPIO Input Enable Toggle Register */
-#define PORTG_POL 0xFFC03338 /* PORTG Port x GPIO Programming Inversion Register */
-#define PORTG_POL_SET 0xFFC0333C /* PORTG Port x GPIO Programming Inversion Set Register */
-#define PORTG_POL_CLEAR 0xFFC03340 /* PORTG Port x GPIO Programming Inversion Clear Register */
-#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
-#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
-
-/* ==================================================
- Pads Controller Registers
- ================================================== */
-
-/* =========================
- PADS0
- ========================= */
-#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */
-#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */
-#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */
-
-/* =========================
- PINT Registers
- ========================= */
-
-/* =========================
- PINT0
- ========================= */
-#define PINT0_MASK_SET 0xFFC04000 /* PINT0 Pint Mask Set Register */
-#define PINT0_MASK_CLEAR 0xFFC04004 /* PINT0 Pint Mask Clear Register */
-#define PINT0_REQUEST 0xFFC04008 /* PINT0 Pint Request Register */
-#define PINT0_ASSIGN 0xFFC0400C /* PINT0 Pint Assign Register */
-#define PINT0_EDGE_SET 0xFFC04010 /* PINT0 Pint Edge Set Register */
-#define PINT0_EDGE_CLEAR 0xFFC04014 /* PINT0 Pint Edge Clear Register */
-#define PINT0_INVERT_SET 0xFFC04018 /* PINT0 Pint Invert Set Register */
-#define PINT0_INVERT_CLEAR 0xFFC0401C /* PINT0 Pint Invert Clear Register */
-#define PINT0_PINSTATE 0xFFC04020 /* PINT0 Pint Pinstate Register */
-#define PINT0_LATCH 0xFFC04024 /* PINT0 Pint Latch Register */
-
-/* =========================
- PINT1
- ========================= */
-#define PINT1_MASK_SET 0xFFC04100 /* PINT1 Pint Mask Set Register */
-#define PINT1_MASK_CLEAR 0xFFC04104 /* PINT1 Pint Mask Clear Register */
-#define PINT1_REQUEST 0xFFC04108 /* PINT1 Pint Request Register */
-#define PINT1_ASSIGN 0xFFC0410C /* PINT1 Pint Assign Register */
-#define PINT1_EDGE_SET 0xFFC04110 /* PINT1 Pint Edge Set Register */
-#define PINT1_EDGE_CLEAR 0xFFC04114 /* PINT1 Pint Edge Clear Register */
-#define PINT1_INVERT_SET 0xFFC04118 /* PINT1 Pint Invert Set Register */
-#define PINT1_INVERT_CLEAR 0xFFC0411C /* PINT1 Pint Invert Clear Register */
-#define PINT1_PINSTATE 0xFFC04120 /* PINT1 Pint Pinstate Register */
-#define PINT1_LATCH 0xFFC04124 /* PINT1 Pint Latch Register */
-
-/* =========================
- PINT2
- ========================= */
-#define PINT2_MASK_SET 0xFFC04200 /* PINT2 Pint Mask Set Register */
-#define PINT2_MASK_CLEAR 0xFFC04204 /* PINT2 Pint Mask Clear Register */
-#define PINT2_REQUEST 0xFFC04208 /* PINT2 Pint Request Register */
-#define PINT2_ASSIGN 0xFFC0420C /* PINT2 Pint Assign Register */
-#define PINT2_EDGE_SET 0xFFC04210 /* PINT2 Pint Edge Set Register */
-#define PINT2_EDGE_CLEAR 0xFFC04214 /* PINT2 Pint Edge Clear Register */
-#define PINT2_INVERT_SET 0xFFC04218 /* PINT2 Pint Invert Set Register */
-#define PINT2_INVERT_CLEAR 0xFFC0421C /* PINT2 Pint Invert Clear Register */
-#define PINT2_PINSTATE 0xFFC04220 /* PINT2 Pint Pinstate Register */
-#define PINT2_LATCH 0xFFC04224 /* PINT2 Pint Latch Register */
-
-/* =========================
- PINT3
- ========================= */
-#define PINT3_MASK_SET 0xFFC04300 /* PINT3 Pint Mask Set Register */
-#define PINT3_MASK_CLEAR 0xFFC04304 /* PINT3 Pint Mask Clear Register */
-#define PINT3_REQUEST 0xFFC04308 /* PINT3 Pint Request Register */
-#define PINT3_ASSIGN 0xFFC0430C /* PINT3 Pint Assign Register */
-#define PINT3_EDGE_SET 0xFFC04310 /* PINT3 Pint Edge Set Register */
-#define PINT3_EDGE_CLEAR 0xFFC04314 /* PINT3 Pint Edge Clear Register */
-#define PINT3_INVERT_SET 0xFFC04318 /* PINT3 Pint Invert Set Register */
-#define PINT3_INVERT_CLEAR 0xFFC0431C /* PINT3 Pint Invert Clear Register */
-#define PINT3_PINSTATE 0xFFC04320 /* PINT3 Pint Pinstate Register */
-#define PINT3_LATCH 0xFFC04324 /* PINT3 Pint Latch Register */
-
-/* =========================
- PINT4
- ========================= */
-#define PINT4_MASK_SET 0xFFC04400 /* PINT4 Pint Mask Set Register */
-#define PINT4_MASK_CLEAR 0xFFC04404 /* PINT4 Pint Mask Clear Register */
-#define PINT4_REQUEST 0xFFC04408 /* PINT4 Pint Request Register */
-#define PINT4_ASSIGN 0xFFC0440C /* PINT4 Pint Assign Register */
-#define PINT4_EDGE_SET 0xFFC04410 /* PINT4 Pint Edge Set Register */
-#define PINT4_EDGE_CLEAR 0xFFC04414 /* PINT4 Pint Edge Clear Register */
-#define PINT4_INVERT_SET 0xFFC04418 /* PINT4 Pint Invert Set Register */
-#define PINT4_INVERT_CLEAR 0xFFC0441C /* PINT4 Pint Invert Clear Register */
-#define PINT4_PINSTATE 0xFFC04420 /* PINT4 Pint Pinstate Register */
-#define PINT4_LATCH 0xFFC04424 /* PINT4 Pint Latch Register */
-
-/* =========================
- PINT5
- ========================= */
-#define PINT5_MASK_SET 0xFFC04500 /* PINT5 Pint Mask Set Register */
-#define PINT5_MASK_CLEAR 0xFFC04504 /* PINT5 Pint Mask Clear Register */
-#define PINT5_REQUEST 0xFFC04508 /* PINT5 Pint Request Register */
-#define PINT5_ASSIGN 0xFFC0450C /* PINT5 Pint Assign Register */
-#define PINT5_EDGE_SET 0xFFC04510 /* PINT5 Pint Edge Set Register */
-#define PINT5_EDGE_CLEAR 0xFFC04514 /* PINT5 Pint Edge Clear Register */
-#define PINT5_INVERT_SET 0xFFC04518 /* PINT5 Pint Invert Set Register */
-#define PINT5_INVERT_CLEAR 0xFFC0451C /* PINT5 Pint Invert Clear Register */
-#define PINT5_PINSTATE 0xFFC04520 /* PINT5 Pint Pinstate Register */
-#define PINT5_LATCH 0xFFC04524 /* PINT5 Pint Latch Register */
-
-
-/* =========================
- SMC Registers
- ========================= */
-
-/* =========================
- SMC0
- ========================= */
-#define SMC_GCTL 0xFFC16004 /* SMC0 SMC Control Register */
-#define SMC_GSTAT 0xFFC16008 /* SMC0 SMC Status Register */
-#define SMC_B0CTL 0xFFC1600C /* SMC0 SMC Bank0 Control Register */
-#define SMC_B0TIM 0xFFC16010 /* SMC0 SMC Bank0 Timing Register */
-#define SMC_B0ETIM 0xFFC16014 /* SMC0 SMC Bank0 Extended Timing Register */
-#define SMC_B1CTL 0xFFC1601C /* SMC0 SMC BANK1 Control Register */
-#define SMC_B1TIM 0xFFC16020 /* SMC0 SMC BANK1 Timing Register */
-#define SMC_B1ETIM 0xFFC16024 /* SMC0 SMC BANK1 Extended Timing Register */
-#define SMC_B2CTL 0xFFC1602C /* SMC0 SMC BANK2 Control Register */
-#define SMC_B2TIM 0xFFC16030 /* SMC0 SMC BANK2 Timing Register */
-#define SMC_B2ETIM 0xFFC16034 /* SMC0 SMC BANK2 Extended Timing Register */
-#define SMC_B3CTL 0xFFC1603C /* SMC0 SMC BANK3 Control Register */
-#define SMC_B3TIM 0xFFC16040 /* SMC0 SMC BANK3 Timing Register */
-#define SMC_B3ETIM 0xFFC16044 /* SMC0 SMC BANK3 Extended Timing Register */
-
-
-/* =========================
- WDOG Registers
- ========================= */
-
-/* =========================
- WDOG0
- ========================= */
-#define WDOG0_CTL 0xFFC17000 /* WDOG0 Control Register */
-#define WDOG0_CNT 0xFFC17004 /* WDOG0 Count Register */
-#define WDOG0_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
-#define WDOG_CTL WDOG0_CTL
-#define WDOG_CNT WDOG0_CNT
-#define WDOG_STAT WDOG0_STAT
-
-/* =========================
- WDOG1
- ========================= */
-#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */
-#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */
-#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
-
-
-/* =========================
- SDU Registers
- ========================= */
-
-/* =========================
- SDU0
- ========================= */
-#define SDU0_IDCODE 0xFFC1F020 /* SDU0 ID Code Register */
-#define SDU0_CTL 0xFFC1F050 /* SDU0 Control Register */
-#define SDU0_STAT 0xFFC1F054 /* SDU0 Status Register */
-#define SDU0_MACCTL 0xFFC1F058 /* SDU0 Memory Access Control Register */
-#define SDU0_MACADDR 0xFFC1F05C /* SDU0 Memory Access Address Register */
-#define SDU0_MACDATA 0xFFC1F060 /* SDU0 Memory Access Data Register */
-#define SDU0_DMARD 0xFFC1F064 /* SDU0 DMA Read Data Register */
-#define SDU0_DMAWD 0xFFC1F068 /* SDU0 DMA Write Data Register */
-#define SDU0_MSG 0xFFC1F080 /* SDU0 Message Register */
-#define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */
-#define SDU0_MSG_CLR 0xFFC1F088 /* SDU0 Message Clear Register */
-#define SDU0_GHLT 0xFFC1F08C /* SDU0 Group Halt Register */
-
-
-/* =========================
- EMAC Registers
- ========================= */
-/* =========================
- EMAC0
- ========================= */
-#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */
-#define EMAC0_MACFRMFILT 0xFFC20004 /* EMAC0 Filter Register for filtering Received Frames */
-#define EMAC0_HASHTBL_HI 0xFFC20008 /* EMAC0 Contains the Upper 32 bits of the hash table */
-#define EMAC0_HASHTBL_LO 0xFFC2000C /* EMAC0 Contains the lower 32 bits of the hash table */
-#define EMAC0_GMII_ADDR 0xFFC20010 /* EMAC0 Management Address Register */
-#define EMAC0_GMII_DATA 0xFFC20014 /* EMAC0 Management Data Register */
-#define EMAC0_FLOWCTL 0xFFC20018 /* EMAC0 MAC FLow Control Register */
-#define EMAC0_VLANTAG 0xFFC2001C /* EMAC0 VLAN Tag Register */
-#define EMAC0_VER 0xFFC20020 /* EMAC0 EMAC Version Register */
-#define EMAC0_DBG 0xFFC20024 /* EMAC0 EMAC Debug Register */
-#define EMAC0_RMTWKUP 0xFFC20028 /* EMAC0 Remote wake up frame register */
-#define EMAC0_PMT_CTLSTAT 0xFFC2002C /* EMAC0 PMT Control and Status Register */
-#define EMAC0_ISTAT 0xFFC20038 /* EMAC0 EMAC Interrupt Status Register */
-#define EMAC0_IMSK 0xFFC2003C /* EMAC0 EMAC Interrupt Mask Register */
-#define EMAC0_ADDR0_HI 0xFFC20040 /* EMAC0 EMAC Address0 High Register */
-#define EMAC0_ADDR0_LO 0xFFC20044 /* EMAC0 EMAC Address0 Low Register */
-#define EMAC0_MMC_CTL 0xFFC20100 /* EMAC0 MMC Control Register */
-#define EMAC0_MMC_RXINT 0xFFC20104 /* EMAC0 MMC RX Interrupt Register */
-#define EMAC0_MMC_TXINT 0xFFC20108 /* EMAC0 MMC TX Interrupt Register */
-#define EMAC0_MMC_RXIMSK 0xFFC2010C /* EMAC0 MMC RX Interrupt Mask Register */
-#define EMAC0_MMC_TXIMSK 0xFFC20110 /* EMAC0 MMC TX Interrupt Mask Register */
-#define EMAC0_TXOCTCNT_GB 0xFFC20114 /* EMAC0 Num bytes transmitted exclusive of preamble */
-#define EMAC0_TXFRMCNT_GB 0xFFC20118 /* EMAC0 Num frames transmitted exclusive of retired */
-#define EMAC0_TXBCASTFRM_G 0xFFC2011C /* EMAC0 Number of good broadcast frames transmitted. */
-#define EMAC0_TXMCASTFRM_G 0xFFC20120 /* EMAC0 Number of good multicast frames transmitted. */
-#define EMAC0_TX64_GB 0xFFC20124 /* EMAC0 Number of 64 byte length frames */
-#define EMAC0_TX65TO127_GB 0xFFC20128 /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
-#define EMAC0_TX128TO255_GB 0xFFC2012C /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
-#define EMAC0_TX256TO511_GB 0xFFC20130 /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
-#define EMAC0_TX512TO1023_GB 0xFFC20134 /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
-#define EMAC0_TX1024TOMAX_GB 0xFFC20138 /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
-#define EMAC0_TXUCASTFRM_GB 0xFFC2013C /* EMAC0 Number of good and bad unicast frames transmitted */
-#define EMAC0_TXMCASTFRM_GB 0xFFC20140 /* EMAC0 Number of good and bad multicast frames transmitted */
-#define EMAC0_TXBCASTFRM_GB 0xFFC20144 /* EMAC0 Number of good and bad broadcast frames transmitted */
-#define EMAC0_TXUNDR_ERR 0xFFC20148 /* EMAC0 Number of frames aborted due to frame underflow error */
-#define EMAC0_TXSNGCOL_G 0xFFC2014C /* EMAC0 Number of transmitted frames after single collision */
-#define EMAC0_TXMULTCOL_G 0xFFC20150 /* EMAC0 Number of transmitted frames with more than one collision */
-#define EMAC0_TXDEFERRED 0xFFC20154 /* EMAC0 Number of transmitted frames after deferral */
-#define EMAC0_TXLATECOL 0xFFC20158 /* EMAC0 Number of frames aborted due to late collision error */
-#define EMAC0_TXEXCESSCOL 0xFFC2015C /* EMAC0 Number of aborted frames due to excessive collisions */
-#define EMAC0_TXCARR_ERR 0xFFC20160 /* EMAC0 Number of aborted frames due to carrier sense error */
-#define EMAC0_TXOCTCNT_G 0xFFC20164 /* EMAC0 Number of bytes transmitted in good frames only */
-#define EMAC0_TXFRMCNT_G 0xFFC20168 /* EMAC0 Number of good frames transmitted. */
-#define EMAC0_TXEXCESSDEF 0xFFC2016C /* EMAC0 Number of frames aborted due to excessive deferral */
-#define EMAC0_TXPAUSEFRM 0xFFC20170 /* EMAC0 Number of good PAUSE frames transmitted. */
-#define EMAC0_TXVLANFRM_G 0xFFC20174 /* EMAC0 Number of VLAN frames transmitted */
-#define EMAC0_RXFRMCNT_GB 0xFFC20180 /* EMAC0 Number of good and bad frames received. */
-#define EMAC0_RXOCTCNT_GB 0xFFC20184 /* EMAC0 Number of bytes received in good and bad frames */
-#define EMAC0_RXOCTCNT_G 0xFFC20188 /* EMAC0 Number of bytes received only in good frames */
-#define EMAC0_RXBCASTFRM_G 0xFFC2018C /* EMAC0 Number of good broadcast frames received. */
-#define EMAC0_RXMCASTFRM_G 0xFFC20190 /* EMAC0 Number of good multicast frames received */
-#define EMAC0_RXCRC_ERR 0xFFC20194 /* EMAC0 Number of frames received with CRC error */
-#define EMAC0_RXALIGN_ERR 0xFFC20198 /* EMAC0 Number of frames with alignment error */
-#define EMAC0_RXRUNT_ERR 0xFFC2019C /* EMAC0 Number of frames received with runt error. */
-#define EMAC0_RXJAB_ERR 0xFFC201A0 /* EMAC0 Number of frames received with length greater than 1518 */
-#define EMAC0_RXUSIZE_G 0xFFC201A4 /* EMAC0 Number of frames received with length 64 */
-#define EMAC0_RXOSIZE_G 0xFFC201A8 /* EMAC0 Number of frames received with length greater than maxium */
-#define EMAC0_RX64_GB 0xFFC201AC /* EMAC0 Number of good and bad frames of lengh 64 bytes */
-#define EMAC0_RX65TO127_GB 0xFFC201B0 /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
-#define EMAC0_RX128TO255_GB 0xFFC201B4 /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
-#define EMAC0_RX256TO511_GB 0xFFC201B8 /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
-#define EMAC0_RX512TO1023_GB 0xFFC201BC /* EMAC0 Number of good and bad frames received between 512-1023 */
-#define EMAC0_RX1024TOMAX_GB 0xFFC201C0 /* EMAC0 Number of frames received between 1024 and maxsize */
-#define EMAC0_RXUCASTFRM_G 0xFFC201C4 /* EMAC0 Number of good unicast frames received. */
-#define EMAC0_RXLEN_ERR 0xFFC201C8 /* EMAC0 Number of frames received with length error */
-#define EMAC0_RXOORTYPE 0xFFC201CC /* EMAC0 Number of frames with length not equal to valid frame size */
-#define EMAC0_RXPAUSEFRM 0xFFC201D0 /* EMAC0 Number of good and valid PAUSE frames received. */
-#define EMAC0_RXFIFO_OVF 0xFFC201D4 /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
-#define EMAC0_RXVLANFRM_GB 0xFFC201D8 /* EMAC0 Number of good and bad VLAN frames received. */
-#define EMAC0_RXWDOG_ERR 0xFFC201DC /* EMAC0 Frames received with error due to watchdog timeout */
-#define EMAC0_IPC_RXIMSK 0xFFC20200 /* EMAC0 MMC IPC RX Interrupt Mask Register */
-#define EMAC0_IPC_RXINT 0xFFC20208 /* EMAC0 MMC IPC RX Interrupt Register */
-#define EMAC0_RXIPV4_GD_FRM 0xFFC20210 /* EMAC0 Number of good IPv4 datagrams */
-#define EMAC0_RXIPV4_HDR_ERR_FRM 0xFFC20214 /* EMAC0 Number of IPv4 datagrams with header errors */
-#define EMAC0_RXIPV4_NOPAY_FRM 0xFFC20218 /* EMAC0 Number of IPv4 datagrams without checksum */
-#define EMAC0_RXIPV4_FRAG_FRM 0xFFC2021C /* EMAC0 Number of good IPv4 datagrams with fragmentation */
-#define EMAC0_RXIPV4_UDSBL_FRM 0xFFC20220 /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
-#define EMAC0_RXIPV6_GD_FRM 0xFFC20224 /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
-#define EMAC0_RXIPV6_HDR_ERR_FRM 0xFFC20228 /* EMAC0 Number of IPv6 datagrams with header errors */
-#define EMAC0_RXIPV6_NOPAY_FRM 0xFFC2022C /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
-#define EMAC0_RXUDP_GD_FRM 0xFFC20230 /* EMAC0 Number of good IP datagrames with good UDP payload */
-#define EMAC0_RXUDP_ERR_FRM 0xFFC20234 /* EMAC0 Number of good IP datagrams with UDP checksum errors */
-#define EMAC0_RXTCP_GD_FRM 0xFFC20238 /* EMAC0 Number of good IP datagrams with a good TCP payload */
-#define EMAC0_RXTCP_ERR_FRM 0xFFC2023C /* EMAC0 Number of good IP datagrams with TCP checksum errors */
-#define EMAC0_RXICMP_GD_FRM 0xFFC20240 /* EMAC0 Number of good IP datagrams with a good ICMP payload */
-#define EMAC0_RXICMP_ERR_FRM 0xFFC20244 /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
-#define EMAC0_RXIPV4_GD_OCT 0xFFC20250 /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
-#define EMAC0_RXIPV4_HDR_ERR_OCT 0xFFC20254 /* EMAC0 Bytes received in IPv4 datagrams with header errors */
-#define EMAC0_RXIPV4_NOPAY_OCT 0xFFC20258 /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
-#define EMAC0_RXIPV4_FRAG_OCT 0xFFC2025C /* EMAC0 Bytes received in fragmented IPv4 datagrams */
-#define EMAC0_RXIPV4_UDSBL_OCT 0xFFC20260 /* EMAC0 Bytes received in UDP segment with checksum disabled */
-#define EMAC0_RXIPV6_GD_OCT 0xFFC20264 /* EMAC0 Bytes received in good IPv6 including tcp,udp or icmp load */
-#define EMAC0_RXIPV6_HDR_ERR_OCT 0xFFC20268 /* EMAC0 Number of bytes received in IPv6 with header errors */
-#define EMAC0_RXIPV6_NOPAY_OCT 0xFFC2026C /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
-#define EMAC0_RXUDP_GD_OCT 0xFFC20270 /* EMAC0 Number of bytes received in good UDP segments */
-#define EMAC0_RXUDP_ERR_OCT 0xFFC20274 /* EMAC0 Number of bytes received in UDP segment with checksum err */
-#define EMAC0_RXTCP_GD_OCT 0xFFC20278 /* EMAC0 Number of bytes received in a good TCP segment */
-#define EMAC0_RXTCP_ERR_OCT 0xFFC2027C /* EMAC0 Number of bytes received in TCP segment with checksum err */
-#define EMAC0_RXICMP_GD_OCT 0xFFC20280 /* EMAC0 Number of bytes received in a good ICMP segment */
-#define EMAC0_RXICMP_ERR_OCT 0xFFC20284 /* EMAC0 Bytes received in an ICMP segment with checksum errors */
-#define EMAC0_TM_CTL 0xFFC20700 /* EMAC0 EMAC Time Stamp Control Register */
-#define EMAC0_TM_SUBSEC 0xFFC20704 /* EMAC0 EMAC Time Stamp Sub Second Increment */
-#define EMAC0_TM_SEC 0xFFC20708 /* EMAC0 EMAC Time Stamp Second Register */
-#define EMAC0_TM_NSEC 0xFFC2070C /* EMAC0 EMAC Time Stamp Nano Second Register */
-#define EMAC0_TM_SECUPDT 0xFFC20710 /* EMAC0 EMAC Time Stamp Seconds Update */
-#define EMAC0_TM_NSECUPDT 0xFFC20714 /* EMAC0 EMAC Time Stamp Nano Seconds Update */
-#define EMAC0_TM_ADDEND 0xFFC20718 /* EMAC0 EMAC Time Stamp Addend Register */
-#define EMAC0_TM_TGTM 0xFFC2071C /* EMAC0 EMAC Time Stamp Target Time Sec. */
-#define EMAC0_TM_NTGTM 0xFFC20720 /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
-#define EMAC0_TM_HISEC 0xFFC20724 /* EMAC0 EMAC Time Stamp High Second Register */
-#define EMAC0_TM_STMPSTAT 0xFFC20728 /* EMAC0 EMAC Time Stamp Status Register */
-#define EMAC0_TM_PPSCTL 0xFFC2072C /* EMAC0 EMAC PPS Control Register */
-#define EMAC0_TM_AUXSTMP_NSEC 0xFFC20730 /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
-#define EMAC0_TM_AUXSTMP_SEC 0xFFC20734 /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
-#define EMAC0_DMA_BUSMODE 0xFFC21000 /* EMAC0 Bus Operating Modes for EMAC DMA */
-#define EMAC0_DMA_TXPOLL 0xFFC21004 /* EMAC0 TX DMA Poll demand register */
-#define EMAC0_DMA_RXPOLL 0xFFC21008 /* EMAC0 RX DMA Poll demand register */
-#define EMAC0_DMA_RXDSC_ADDR 0xFFC2100C /* EMAC0 RX Descriptor List Address */
-#define EMAC0_DMA_TXDSC_ADDR 0xFFC21010 /* EMAC0 TX Descriptor List Address */
-#define EMAC0_DMA_STAT 0xFFC21014 /* EMAC0 DMA Status Register */
-#define EMAC0_DMA_OPMODE 0xFFC21018 /* EMAC0 DMA Operation Mode Register */
-#define EMAC0_DMA_IEN 0xFFC2101C /* EMAC0 DMA Interrupt Enable Register */
-#define EMAC0_DMA_MISS_FRM 0xFFC21020 /* EMAC0 DMA missed frame and buffer overflow counter */
-#define EMAC0_DMA_RXIWDOG 0xFFC21024 /* EMAC0 DMA RX Interrupt Watch Dog timer */
-#define EMAC0_DMA_BMMODE 0xFFC21028 /* EMAC0 AXI Bus Mode Register */
-#define EMAC0_DMA_BMSTAT 0xFFC2102C /* EMAC0 AXI Status Register */
-#define EMAC0_DMA_TXDSC_CUR 0xFFC21048 /* EMAC0 TX current descriptor register */
-#define EMAC0_DMA_RXDSC_CUR 0xFFC2104C /* EMAC0 RX current descriptor register */
-#define EMAC0_DMA_TXBUF_CUR 0xFFC21050 /* EMAC0 TX current buffer pointer register */
-#define EMAC0_DMA_RXBUF_CUR 0xFFC21054 /* EMAC0 RX current buffer pointer register */
-#define EMAC0_HWFEAT 0xFFC21058 /* EMAC0 Hardware Feature Register */
-
-/* =========================
- EMAC1
- ========================= */
-#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */
-#define EMAC1_MACFRMFILT 0xFFC22004 /* EMAC1 Filter Register for filtering Received Frames */
-#define EMAC1_HASHTBL_HI 0xFFC22008 /* EMAC1 Contains the Upper 32 bits of the hash table */
-#define EMAC1_HASHTBL_LO 0xFFC2200C /* EMAC1 Contains the lower 32 bits of the hash table */
-#define EMAC1_GMII_ADDR 0xFFC22010 /* EMAC1 Management Address Register */
-#define EMAC1_GMII_DATA 0xFFC22014 /* EMAC1 Management Data Register */
-#define EMAC1_FLOWCTL 0xFFC22018 /* EMAC1 MAC FLow Control Register */
-#define EMAC1_VLANTAG 0xFFC2201C /* EMAC1 VLAN Tag Register */
-#define EMAC1_VER 0xFFC22020 /* EMAC1 EMAC Version Register */
-#define EMAC1_DBG 0xFFC22024 /* EMAC1 EMAC Debug Register */
-#define EMAC1_RMTWKUP 0xFFC22028 /* EMAC1 Remote wake up frame register */
-#define EMAC1_PMT_CTLSTAT 0xFFC2202C /* EMAC1 PMT Control and Status Register */
-#define EMAC1_ISTAT 0xFFC22038 /* EMAC1 EMAC Interrupt Status Register */
-#define EMAC1_IMSK 0xFFC2203C /* EMAC1 EMAC Interrupt Mask Register */
-#define EMAC1_ADDR0_HI 0xFFC22040 /* EMAC1 EMAC Address0 High Register */
-#define EMAC1_ADDR0_LO 0xFFC22044 /* EMAC1 EMAC Address0 Low Register */
-#define EMAC1_MMC_CTL 0xFFC22100 /* EMAC1 MMC Control Register */
-#define EMAC1_MMC_RXINT 0xFFC22104 /* EMAC1 MMC RX Interrupt Register */
-#define EMAC1_MMC_TXINT 0xFFC22108 /* EMAC1 MMC TX Interrupt Register */
-#define EMAC1_MMC_RXIMSK 0xFFC2210C /* EMAC1 MMC RX Interrupt Mask Register */
-#define EMAC1_MMC_TXIMSK 0xFFC22110 /* EMAC1 MMC TX Interrupt Mask Register */
-#define EMAC1_TXOCTCNT_GB 0xFFC22114 /* EMAC1 Num bytes transmitted exclusive of preamble */
-#define EMAC1_TXFRMCNT_GB 0xFFC22118 /* EMAC1 Num frames transmitted exclusive of retired */
-#define EMAC1_TXBCASTFRM_G 0xFFC2211C /* EMAC1 Number of good broadcast frames transmitted. */
-#define EMAC1_TXMCASTFRM_G 0xFFC22120 /* EMAC1 Number of good multicast frames transmitted. */
-#define EMAC1_TX64_GB 0xFFC22124 /* EMAC1 Number of 64 byte length frames */
-#define EMAC1_TX65TO127_GB 0xFFC22128 /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
-#define EMAC1_TX128TO255_GB 0xFFC2212C /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
-#define EMAC1_TX256TO511_GB 0xFFC22130 /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
-#define EMAC1_TX512TO1023_GB 0xFFC22134 /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
-#define EMAC1_TX1024TOMAX_GB 0xFFC22138 /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
-#define EMAC1_TXUCASTFRM_GB 0xFFC2213C /* EMAC1 Number of good and bad unicast frames transmitted */
-#define EMAC1_TXMCASTFRM_GB 0xFFC22140 /* EMAC1 Number of good and bad multicast frames transmitted */
-#define EMAC1_TXBCASTFRM_GB 0xFFC22144 /* EMAC1 Number of good and bad broadcast frames transmitted */
-#define EMAC1_TXUNDR_ERR 0xFFC22148 /* EMAC1 Number of frames aborted due to frame underflow error */
-#define EMAC1_TXSNGCOL_G 0xFFC2214C /* EMAC1 Number of transmitted frames after single collision */
-#define EMAC1_TXMULTCOL_G 0xFFC22150 /* EMAC1 Number of transmitted frames with more than one collision */
-#define EMAC1_TXDEFERRED 0xFFC22154 /* EMAC1 Number of transmitted frames after deferral */
-#define EMAC1_TXLATECOL 0xFFC22158 /* EMAC1 Number of frames aborted due to late collision error */
-#define EMAC1_TXEXCESSCOL 0xFFC2215C /* EMAC1 Number of aborted frames due to excessive collisions */
-#define EMAC1_TXCARR_ERR 0xFFC22160 /* EMAC1 Number of aborted frames due to carrier sense error */
-#define EMAC1_TXOCTCNT_G 0xFFC22164 /* EMAC1 Number of bytes transmitted in good frames only */
-#define EMAC1_TXFRMCNT_G 0xFFC22168 /* EMAC1 Number of good frames transmitted. */
-#define EMAC1_TXEXCESSDEF 0xFFC2216C /* EMAC1 Number of frames aborted due to excessive deferral */
-#define EMAC1_TXPAUSEFRM 0xFFC22170 /* EMAC1 Number of good PAUSE frames transmitted. */
-#define EMAC1_TXVLANFRM_G 0xFFC22174 /* EMAC1 Number of VLAN frames transmitted */
-#define EMAC1_RXFRMCNT_GB 0xFFC22180 /* EMAC1 Number of good and bad frames received. */
-#define EMAC1_RXOCTCNT_GB 0xFFC22184 /* EMAC1 Number of bytes received in good and bad frames */
-#define EMAC1_RXOCTCNT_G 0xFFC22188 /* EMAC1 Number of bytes received only in good frames */
-#define EMAC1_RXBCASTFRM_G 0xFFC2218C /* EMAC1 Number of good broadcast frames received. */
-#define EMAC1_RXMCASTFRM_G 0xFFC22190 /* EMAC1 Number of good multicast frames received */
-#define EMAC1_RXCRC_ERR 0xFFC22194 /* EMAC1 Number of frames received with CRC error */
-#define EMAC1_RXALIGN_ERR 0xFFC22198 /* EMAC1 Number of frames with alignment error */
-#define EMAC1_RXRUNT_ERR 0xFFC2219C /* EMAC1 Number of frames received with runt error. */
-#define EMAC1_RXJAB_ERR 0xFFC221A0 /* EMAC1 Number of frames received with length greater than 1518 */
-#define EMAC1_RXUSIZE_G 0xFFC221A4 /* EMAC1 Number of frames received with length 64 */
-#define EMAC1_RXOSIZE_G 0xFFC221A8 /* EMAC1 Number of frames received with length greater than maxium */
-#define EMAC1_RX64_GB 0xFFC221AC /* EMAC1 Number of good and bad frames of lengh 64 bytes */
-#define EMAC1_RX65TO127_GB 0xFFC221B0 /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
-#define EMAC1_RX128TO255_GB 0xFFC221B4 /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
-#define EMAC1_RX256TO511_GB 0xFFC221B8 /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
-#define EMAC1_RX512TO1023_GB 0xFFC221BC /* EMAC1 Number of good and bad frames received between 512-1023 */
-#define EMAC1_RX1024TOMAX_GB 0xFFC221C0 /* EMAC1 Number of frames received between 1024 and maxsize */
-#define EMAC1_RXUCASTFRM_G 0xFFC221C4 /* EMAC1 Number of good unicast frames received. */
-#define EMAC1_RXLEN_ERR 0xFFC221C8 /* EMAC1 Number of frames received with length error */
-#define EMAC1_RXOORTYPE 0xFFC221CC /* EMAC1 Number of frames with length not equal to valid frame size */
-#define EMAC1_RXPAUSEFRM 0xFFC221D0 /* EMAC1 Number of good and valid PAUSE frames received. */
-#define EMAC1_RXFIFO_OVF 0xFFC221D4 /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
-#define EMAC1_RXVLANFRM_GB 0xFFC221D8 /* EMAC1 Number of good and bad VLAN frames received. */
-#define EMAC1_RXWDOG_ERR 0xFFC221DC /* EMAC1 Frames received with error due to watchdog timeout */
-#define EMAC1_IPC_RXIMSK 0xFFC22200 /* EMAC1 MMC IPC RX Interrupt Mask Register */
-#define EMAC1_IPC_RXINT 0xFFC22208 /* EMAC1 MMC IPC RX Interrupt Register */
-#define EMAC1_RXIPV4_GD_FRM 0xFFC22210 /* EMAC1 Number of good IPv4 datagrams */
-#define EMAC1_RXIPV4_HDR_ERR_FRM 0xFFC22214 /* EMAC1 Number of IPv4 datagrams with header errors */
-#define EMAC1_RXIPV4_NOPAY_FRM 0xFFC22218 /* EMAC1 Number of IPv4 datagrams without checksum */
-#define EMAC1_RXIPV4_FRAG_FRM 0xFFC2221C /* EMAC1 Number of good IPv4 datagrams with fragmentation */
-#define EMAC1_RXIPV4_UDSBL_FRM 0xFFC22220 /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
-#define EMAC1_RXIPV6_GD_FRM 0xFFC22224 /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
-#define EMAC1_RXIPV6_HDR_ERR_FRM 0xFFC22228 /* EMAC1 Number of IPv6 datagrams with header errors */
-#define EMAC1_RXIPV6_NOPAY_FRM 0xFFC2222C /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
-#define EMAC1_RXUDP_GD_FRM 0xFFC22230 /* EMAC1 Number of good IP datagrames with good UDP payload */
-#define EMAC1_RXUDP_ERR_FRM 0xFFC22234 /* EMAC1 Number of good IP datagrams with UDP checksum errors */
-#define EMAC1_RXTCP_GD_FRM 0xFFC22238 /* EMAC1 Number of good IP datagrams with a good TCP payload */
-#define EMAC1_RXTCP_ERR_FRM 0xFFC2223C /* EMAC1 Number of good IP datagrams with TCP checksum errors */
-#define EMAC1_RXICMP_GD_FRM 0xFFC22240 /* EMAC1 Number of good IP datagrams with a good ICMP payload */
-#define EMAC1_RXICMP_ERR_FRM 0xFFC22244 /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
-#define EMAC1_RXIPV4_GD_OCT 0xFFC22250 /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
-#define EMAC1_RXIPV4_HDR_ERR_OCT 0xFFC22254 /* EMAC1 Bytes received in IPv4 datagrams with header errors */
-#define EMAC1_RXIPV4_NOPAY_OCT 0xFFC22258 /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
-#define EMAC1_RXIPV4_FRAG_OCT 0xFFC2225C /* EMAC1 Bytes received in fragmented IPv4 datagrams */
-#define EMAC1_RXIPV4_UDSBL_OCT 0xFFC22260 /* EMAC1 Bytes received in UDP segment with checksum disabled */
-#define EMAC1_RXIPV6_GD_OCT 0xFFC22264 /* EMAC1 Bytes received in good IPv6 including tcp,udp or icmp load */
-#define EMAC1_RXIPV6_HDR_ERR_OCT 0xFFC22268 /* EMAC1 Number of bytes received in IPv6 with header errors */
-#define EMAC1_RXIPV6_NOPAY_OCT 0xFFC2226C /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
-#define EMAC1_RXUDP_GD_OCT 0xFFC22270 /* EMAC1 Number of bytes received in good UDP segments */
-#define EMAC1_RXUDP_ERR_OCT 0xFFC22274 /* EMAC1 Number of bytes received in UDP segment with checksum err */
-#define EMAC1_RXTCP_GD_OCT 0xFFC22278 /* EMAC1 Number of bytes received in a good TCP segment */
-#define EMAC1_RXTCP_ERR_OCT 0xFFC2227C /* EMAC1 Number of bytes received in TCP segment with checksum err */
-#define EMAC1_RXICMP_GD_OCT 0xFFC22280 /* EMAC1 Number of bytes received in a good ICMP segment */
-#define EMAC1_RXICMP_ERR_OCT 0xFFC22284 /* EMAC1 Bytes received in an ICMP segment with checksum errors */
-#define EMAC1_TM_CTL 0xFFC22700 /* EMAC1 EMAC Time Stamp Control Register */
-#define EMAC1_TM_SUBSEC 0xFFC22704 /* EMAC1 EMAC Time Stamp Sub Second Increment */
-#define EMAC1_TM_SEC 0xFFC22708 /* EMAC1 EMAC Time Stamp Second Register */
-#define EMAC1_TM_NSEC 0xFFC2270C /* EMAC1 EMAC Time Stamp Nano Second Register */
-#define EMAC1_TM_SECUPDT 0xFFC22710 /* EMAC1 EMAC Time Stamp Seconds Update */
-#define EMAC1_TM_NSECUPDT 0xFFC22714 /* EMAC1 EMAC Time Stamp Nano Seconds Update */
-#define EMAC1_TM_ADDEND 0xFFC22718 /* EMAC1 EMAC Time Stamp Addend Register */
-#define EMAC1_TM_TGTM 0xFFC2271C /* EMAC1 EMAC Time Stamp Target Time Sec. */
-#define EMAC1_TM_NTGTM 0xFFC22720 /* EMAC1 EMAC Time Stamp Target Time Nanosec. */
-#define EMAC1_TM_HISEC 0xFFC22724 /* EMAC1 EMAC Time Stamp High Second Register */
-#define EMAC1_TM_STMPSTAT 0xFFC22728 /* EMAC1 EMAC Time Stamp Status Register */
-#define EMAC1_TM_PPSCTL 0xFFC2272C /* EMAC1 EMAC PPS Control Register */
-#define EMAC1_TM_AUXSTMP_NSEC 0xFFC22730 /* EMAC1 EMAC Auxillary Time Stamp Nano Register */
-#define EMAC1_TM_AUXSTMP_SEC 0xFFC22734 /* EMAC1 EMAC Auxillary Time Stamp Sec Register */
-#define EMAC1_DMA_BUSMODE 0xFFC23000 /* EMAC1 Bus Operating Modes for EMAC DMA */
-#define EMAC1_DMA_TXPOLL 0xFFC23004 /* EMAC1 TX DMA Poll demand register */
-#define EMAC1_DMA_RXPOLL 0xFFC23008 /* EMAC1 RX DMA Poll demand register */
-#define EMAC1_DMA_RXDSC_ADDR 0xFFC2300C /* EMAC1 RX Descriptor List Address */
-#define EMAC1_DMA_TXDSC_ADDR 0xFFC23010 /* EMAC1 TX Descriptor List Address */
-#define EMAC1_DMA_STAT 0xFFC23014 /* EMAC1 DMA Status Register */
-#define EMAC1_DMA_OPMODE 0xFFC23018 /* EMAC1 DMA Operation Mode Register */
-#define EMAC1_DMA_IEN 0xFFC2301C /* EMAC1 DMA Interrupt Enable Register */
-#define EMAC1_DMA_MISS_FRM 0xFFC23020 /* EMAC1 DMA missed frame and buffer overflow counter */
-#define EMAC1_DMA_RXIWDOG 0xFFC23024 /* EMAC1 DMA RX Interrupt Watch Dog timer */
-#define EMAC1_DMA_BMMODE 0xFFC23028 /* EMAC1 AXI Bus Mode Register */
-#define EMAC1_DMA_BMSTAT 0xFFC2302C /* EMAC1 AXI Status Register */
-#define EMAC1_DMA_TXDSC_CUR 0xFFC23048 /* EMAC1 TX current descriptor register */
-#define EMAC1_DMA_RXDSC_CUR 0xFFC2304C /* EMAC1 RX current descriptor register */
-#define EMAC1_DMA_TXBUF_CUR 0xFFC23050 /* EMAC1 TX current buffer pointer register */
-#define EMAC1_DMA_RXBUF_CUR 0xFFC23054 /* EMAC1 RX current buffer pointer register */
-#define EMAC1_HWFEAT 0xFFC23058 /* EMAC1 Hardware Feature Register */
-
-
-/* =========================
- SPI Registers
- ========================= */
-
-/* =========================
- SPI0
- ========================= */
-#define SPI0_REGBASE 0xFFC40400
-#define SPI0_CTL 0xFFC40404 /* SPI0 Control Register */
-#define SPI0_RXCTL 0xFFC40408 /* SPI0 RX Control Register */
-#define SPI0_TXCTL 0xFFC4040C /* SPI0 TX Control Register */
-#define SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */
-#define SPI0_DLY 0xFFC40414 /* SPI0 Delay Register */
-#define SPI0_SLVSEL 0xFFC40418 /* SPI0 Slave Select Register */
-#define SPI0_RWC 0xFFC4041C /* SPI0 Received Word-Count Register */
-#define SPI0_RWCR 0xFFC40420 /* SPI0 Received Word-Count Reload Register */
-#define SPI0_TWC 0xFFC40424 /* SPI0 Transmitted Word-Count Register */
-#define SPI0_TWCR 0xFFC40428 /* SPI0 Transmitted Word-Count Reload Register */
-#define SPI0_IMSK 0xFFC40430 /* SPI0 Interrupt Mask Register */
-#define SPI0_IMSK_CLR 0xFFC40434 /* SPI0 Interrupt Mask Clear Register */
-#define SPI0_IMSK_SET 0xFFC40438 /* SPI0 Interrupt Mask Set Register */
-#define SPI0_STAT 0xFFC40440 /* SPI0 Status Register */
-#define SPI0_ILAT 0xFFC40444 /* SPI0 Masked Interrupt Condition Register */
-#define SPI0_ILAT_CLR 0xFFC40448 /* SPI0 Masked Interrupt Clear Register */
-#define SPI0_RFIFO 0xFFC40450 /* SPI0 Receive FIFO Data Register */
-#define SPI0_TFIFO 0xFFC40458 /* SPI0 Transmit FIFO Data Register */
-
-/* =========================
- SPI1
- ========================= */
-#define SPI1_REGBASE 0xFFC40500
-#define SPI1_CTL 0xFFC40504 /* SPI1 Control Register */
-#define SPI1_RXCTL 0xFFC40508 /* SPI1 RX Control Register */
-#define SPI1_TXCTL 0xFFC4050C /* SPI1 TX Control Register */
-#define SPI1_CLK 0xFFC40510 /* SPI1 Clock Rate Register */
-#define SPI1_DLY 0xFFC40514 /* SPI1 Delay Register */
-#define SPI1_SLVSEL 0xFFC40518 /* SPI1 Slave Select Register */
-#define SPI1_RWC 0xFFC4051C /* SPI1 Received Word-Count Register */
-#define SPI1_RWCR 0xFFC40520 /* SPI1 Received Word-Count Reload Register */
-#define SPI1_TWC 0xFFC40524 /* SPI1 Transmitted Word-Count Register */
-#define SPI1_TWCR 0xFFC40528 /* SPI1 Transmitted Word-Count Reload Register */
-#define SPI1_IMSK 0xFFC40530 /* SPI1 Interrupt Mask Register */
-#define SPI1_IMSK_CLR 0xFFC40534 /* SPI1 Interrupt Mask Clear Register */
-#define SPI1_IMSK_SET 0xFFC40538 /* SPI1 Interrupt Mask Set Register */
-#define SPI1_STAT 0xFFC40540 /* SPI1 Status Register */
-#define SPI1_ILAT 0xFFC40544 /* SPI1 Masked Interrupt Condition Register */
-#define SPI1_ILAT_CLR 0xFFC40548 /* SPI1 Masked Interrupt Clear Register */
-#define SPI1_RFIFO 0xFFC40550 /* SPI1 Receive FIFO Data Register */
-#define SPI1_TFIFO 0xFFC40558 /* SPI1 Transmit FIFO Data Register */
-
-/* =========================
- SPORT Registers
- ========================= */
-
-/* =========================
- SPORT0
- ========================= */
-#define SPORT0_CTL_A 0xFFC40000 /* SPORT0 'A' Control Register */
-#define SPORT0_DIV_A 0xFFC40004 /* SPORT0 'A' Clock and FS Divide Register */
-#define SPORT0_MCTL_A 0xFFC40008 /* SPORT0 'A' Multichannel Control Register */
-#define SPORT0_CS0_A 0xFFC4000C /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT0_CS1_A 0xFFC40010 /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT0_CS2_A 0xFFC40014 /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT0_CS3_A 0xFFC40018 /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT0_CNT_A 0xFFC4001C /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT0_ERR_A 0xFFC40020 /* SPORT0 'A' Error Register */
-#define SPORT0_MSTAT_A 0xFFC40024 /* SPORT0 'A' Multichannel Mode Status Register */
-#define SPORT0_CTL2_A 0xFFC40028 /* SPORT0 'A' Control Register 2 */
-#define SPORT0_TXPRI_A 0xFFC40040 /* SPORT0 'A' Primary Channel Transmit Buffer Register */
-#define SPORT0_RXPRI_A 0xFFC40044 /* SPORT0 'A' Primary Channel Receive Buffer Register */
-#define SPORT0_TXSEC_A 0xFFC40048 /* SPORT0 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT0_RXSEC_A 0xFFC4004C /* SPORT0 'A' Secondary Channel Receive Buffer Register */
-#define SPORT0_CTL_B 0xFFC40080 /* SPORT0 'B' Control Register */
-#define SPORT0_DIV_B 0xFFC40084 /* SPORT0 'B' Clock and FS Divide Register */
-#define SPORT0_MCTL_B 0xFFC40088 /* SPORT0 'B' Multichannel Control Register */
-#define SPORT0_CS0_B 0xFFC4008C /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT0_CS1_B 0xFFC40090 /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT0_CS2_B 0xFFC40094 /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT0_CS3_B 0xFFC40098 /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT0_CNT_B 0xFFC4009C /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT0_ERR_B 0xFFC400A0 /* SPORT0 'B' Error Register */
-#define SPORT0_MSTAT_B 0xFFC400A4 /* SPORT0 'B' Multichannel Mode Status Register */
-#define SPORT0_CTL2_B 0xFFC400A8 /* SPORT0 'B' Control Register 2 */
-#define SPORT0_TXPRI_B 0xFFC400C0 /* SPORT0 'B' Primary Channel Transmit Buffer Register */
-#define SPORT0_RXPRI_B 0xFFC400C4 /* SPORT0 'B' Primary Channel Receive Buffer Register */
-#define SPORT0_TXSEC_B 0xFFC400C8 /* SPORT0 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT0_RXSEC_B 0xFFC400CC /* SPORT0 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- SPORT1
- ========================= */
-#define SPORT1_CTL_A 0xFFC40100 /* SPORT1 'A' Control Register */
-#define SPORT1_DIV_A 0xFFC40104 /* SPORT1 'A' Clock and FS Divide Register */
-#define SPORT1_MCTL_A 0xFFC40108 /* SPORT1 'A' Multichannel Control Register */
-#define SPORT1_CS0_A 0xFFC4010C /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT1_CS1_A 0xFFC40110 /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT1_CS2_A 0xFFC40114 /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT1_CS3_A 0xFFC40118 /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT1_CNT_A 0xFFC4011C /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT1_ERR_A 0xFFC40120 /* SPORT1 'A' Error Register */
-#define SPORT1_MSTAT_A 0xFFC40124 /* SPORT1 'A' Multichannel Mode Status Register */
-#define SPORT1_CTL2_A 0xFFC40128 /* SPORT1 'A' Control Register 2 */
-#define SPORT1_TXPRI_A 0xFFC40140 /* SPORT1 'A' Primary Channel Transmit Buffer Register */
-#define SPORT1_RXPRI_A 0xFFC40144 /* SPORT1 'A' Primary Channel Receive Buffer Register */
-#define SPORT1_TXSEC_A 0xFFC40148 /* SPORT1 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT1_RXSEC_A 0xFFC4014C /* SPORT1 'A' Secondary Channel Receive Buffer Register */
-#define SPORT1_CTL_B 0xFFC40180 /* SPORT1 'B' Control Register */
-#define SPORT1_DIV_B 0xFFC40184 /* SPORT1 'B' Clock and FS Divide Register */
-#define SPORT1_MCTL_B 0xFFC40188 /* SPORT1 'B' Multichannel Control Register */
-#define SPORT1_CS0_B 0xFFC4018C /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT1_CS1_B 0xFFC40190 /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT1_CS2_B 0xFFC40194 /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT1_CS3_B 0xFFC40198 /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT1_CNT_B 0xFFC4019C /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT1_ERR_B 0xFFC401A0 /* SPORT1 'B' Error Register */
-#define SPORT1_MSTAT_B 0xFFC401A4 /* SPORT1 'B' Multichannel Mode Status Register */
-#define SPORT1_CTL2_B 0xFFC401A8 /* SPORT1 'B' Control Register 2 */
-#define SPORT1_TXPRI_B 0xFFC401C0 /* SPORT1 'B' Primary Channel Transmit Buffer Register */
-#define SPORT1_RXPRI_B 0xFFC401C4 /* SPORT1 'B' Primary Channel Receive Buffer Register */
-#define SPORT1_TXSEC_B 0xFFC401C8 /* SPORT1 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT1_RXSEC_B 0xFFC401CC /* SPORT1 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- SPORT2
- ========================= */
-#define SPORT2_CTL_A 0xFFC40200 /* SPORT2 'A' Control Register */
-#define SPORT2_DIV_A 0xFFC40204 /* SPORT2 'A' Clock and FS Divide Register */
-#define SPORT2_MCTL_A 0xFFC40208 /* SPORT2 'A' Multichannel Control Register */
-#define SPORT2_CS0_A 0xFFC4020C /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT2_CS1_A 0xFFC40210 /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT2_CS2_A 0xFFC40214 /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT2_CS3_A 0xFFC40218 /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT2_CNT_A 0xFFC4021C /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT2_ERR_A 0xFFC40220 /* SPORT2 'A' Error Register */
-#define SPORT2_MSTAT_A 0xFFC40224 /* SPORT2 'A' Multichannel Mode Status Register */
-#define SPORT2_CTL2_A 0xFFC40228 /* SPORT2 'A' Control Register 2 */
-#define SPORT2_TXPRI_A 0xFFC40240 /* SPORT2 'A' Primary Channel Transmit Buffer Register */
-#define SPORT2_RXPRI_A 0xFFC40244 /* SPORT2 'A' Primary Channel Receive Buffer Register */
-#define SPORT2_TXSEC_A 0xFFC40248 /* SPORT2 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT2_RXSEC_A 0xFFC4024C /* SPORT2 'A' Secondary Channel Receive Buffer Register */
-#define SPORT2_CTL_B 0xFFC40280 /* SPORT2 'B' Control Register */
-#define SPORT2_DIV_B 0xFFC40284 /* SPORT2 'B' Clock and FS Divide Register */
-#define SPORT2_MCTL_B 0xFFC40288 /* SPORT2 'B' Multichannel Control Register */
-#define SPORT2_CS0_B 0xFFC4028C /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT2_CS1_B 0xFFC40290 /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT2_CS2_B 0xFFC40294 /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT2_CS3_B 0xFFC40298 /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT2_CNT_B 0xFFC4029C /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT2_ERR_B 0xFFC402A0 /* SPORT2 'B' Error Register */
-#define SPORT2_MSTAT_B 0xFFC402A4 /* SPORT2 'B' Multichannel Mode Status Register */
-#define SPORT2_CTL2_B 0xFFC402A8 /* SPORT2 'B' Control Register 2 */
-#define SPORT2_TXPRI_B 0xFFC402C0 /* SPORT2 'B' Primary Channel Transmit Buffer Register */
-#define SPORT2_RXPRI_B 0xFFC402C4 /* SPORT2 'B' Primary Channel Receive Buffer Register */
-#define SPORT2_TXSEC_B 0xFFC402C8 /* SPORT2 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT2_RXSEC_B 0xFFC402CC /* SPORT2 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- EPPI Registers
- ========================= */
-
-/* =========================
- EPPI0
- ========================= */
-#define EPPI0_STAT 0xFFC18000 /* EPPI0 Status Register */
-#define EPPI0_HCNT 0xFFC18004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDLY 0xFFC18008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCNT 0xFFC1800C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDLY 0xFFC18010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xFFC18014 /* EPPI0 Lines Per Frame Register */
-#define EPPI0_LINE 0xFFC18018 /* EPPI0 Samples Per Line Register */
-#define EPPI0_CLKDIV 0xFFC1801C /* EPPI0 Clock Divide Register */
-#define EPPI0_CTL 0xFFC18020 /* EPPI0 Control Register */
-#define EPPI0_FS1_WLHB 0xFFC18024 /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1_PASPL 0xFFC18028 /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI0_FS2_WLVB 0xFFC1802C /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI0_FS2_PALPF 0xFFC18030 /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI0_IMSK 0xFFC18034 /* EPPI0 Interrupt Mask Register */
-#define EPPI0_ODDCLIP 0xFFC1803C /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define EPPI0_EVENCLIP 0xFFC18040 /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define EPPI0_FS1_DLY 0xFFC18044 /* EPPI0 Frame Sync 1 Delay Value */
-#define EPPI0_FS2_DLY 0xFFC18048 /* EPPI0 Frame Sync 2 Delay Value */
-#define EPPI0_CTL2 0xFFC1804C /* EPPI0 Control Register 2 */
-
-/* =========================
- EPPI1
- ========================= */
-#define EPPI1_STAT 0xFFC18400 /* EPPI1 Status Register */
-#define EPPI1_HCNT 0xFFC18404 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDLY 0xFFC18408 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCNT 0xFFC1840C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDLY 0xFFC18410 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xFFC18414 /* EPPI1 Lines Per Frame Register */
-#define EPPI1_LINE 0xFFC18418 /* EPPI1 Samples Per Line Register */
-#define EPPI1_CLKDIV 0xFFC1841C /* EPPI1 Clock Divide Register */
-#define EPPI1_CTL 0xFFC18420 /* EPPI1 Control Register */
-#define EPPI1_FS1_WLHB 0xFFC18424 /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1_PASPL 0xFFC18428 /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI1_FS2_WLVB 0xFFC1842C /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI1_FS2_PALPF 0xFFC18430 /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI1_IMSK 0xFFC18434 /* EPPI1 Interrupt Mask Register */
-#define EPPI1_ODDCLIP 0xFFC1843C /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define EPPI1_EVENCLIP 0xFFC18440 /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define EPPI1_FS1_DLY 0xFFC18444 /* EPPI1 Frame Sync 1 Delay Value */
-#define EPPI1_FS2_DLY 0xFFC18448 /* EPPI1 Frame Sync 2 Delay Value */
-#define EPPI1_CTL2 0xFFC1844C /* EPPI1 Control Register 2 */
-
-/* =========================
- EPPI2
- ========================= */
-#define EPPI2_STAT 0xFFC18800 /* EPPI2 Status Register */
-#define EPPI2_HCNT 0xFFC18804 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDLY 0xFFC18808 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCNT 0xFFC1880C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDLY 0xFFC18810 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xFFC18814 /* EPPI2 Lines Per Frame Register */
-#define EPPI2_LINE 0xFFC18818 /* EPPI2 Samples Per Line Register */
-#define EPPI2_CLKDIV 0xFFC1881C /* EPPI2 Clock Divide Register */
-#define EPPI2_CTL 0xFFC18820 /* EPPI2 Control Register */
-#define EPPI2_FS1_WLHB 0xFFC18824 /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1_PASPL 0xFFC18828 /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI2_FS2_WLVB 0xFFC1882C /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI2_FS2_PALPF 0xFFC18830 /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI2_IMSK 0xFFC18834 /* EPPI2 Interrupt Mask Register */
-#define EPPI2_ODDCLIP 0xFFC1883C /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define EPPI2_EVENCLIP 0xFFC18840 /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define EPPI2_FS1_DLY 0xFFC18844 /* EPPI2 Frame Sync 1 Delay Value */
-#define EPPI2_FS2_DLY 0xFFC18848 /* EPPI2 Frame Sync 2 Delay Value */
-#define EPPI2_CTL2 0xFFC1884C /* EPPI2 Control Register 2 */
-
-
-
-/* =========================
- DDE Registers
- ========================= */
-
-/* =========================
- DMA0
- ========================= */
-#define DMA0_NEXT_DESC_PTR 0xFFC41000 /* DMA0 Pointer to Next Initial Descriptor */
-#define DMA0_START_ADDR 0xFFC41004 /* DMA0 Start Address of Current Buffer */
-#define DMA0_CONFIG 0xFFC41008 /* DMA0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC4100C /* DMA0 Inner Loop Count Start Value */
-#define DMA0_X_MODIFY 0xFFC41010 /* DMA0 Inner Loop Address Increment */
-#define DMA0_Y_COUNT 0xFFC41014 /* DMA0 Outer Loop Count Start Value (2D only) */
-#define DMA0_Y_MODIFY 0xFFC41018 /* DMA0 Outer Loop Address Increment (2D only) */
-#define DMA0_CURR_DESC_PTR 0xFFC41024 /* DMA0 Current Descriptor Pointer */
-#define DMA0_PREV_DESC_PTR 0xFFC41028 /* DMA0 Previous Initial Descriptor Pointer */
-#define DMA0_CURR_ADDR 0xFFC4102C /* DMA0 Current Address */
-#define DMA0_IRQ_STATUS 0xFFC41030 /* DMA0 Status Register */
-#define DMA0_CURR_X_COUNT 0xFFC41034 /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA0_CURR_Y_COUNT 0xFFC41038 /* DMA0 Current Row Count (2D only) */
-#define DMA0_BWL_COUNT 0xFFC41040 /* DMA0 Bandwidth Limit Count */
-#define DMA0_CURR_BWL_COUNT 0xFFC41044 /* DMA0 Bandwidth Limit Count Current */
-#define DMA0_BWM_COUNT 0xFFC41048 /* DMA0 Bandwidth Monitor Count */
-#define DMA0_CURR_BWM_COUNT 0xFFC4104C /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA1
- ========================= */
-#define DMA1_NEXT_DESC_PTR 0xFFC41080 /* DMA1 Pointer to Next Initial Descriptor */
-#define DMA1_START_ADDR 0xFFC41084 /* DMA1 Start Address of Current Buffer */
-#define DMA1_CONFIG 0xFFC41088 /* DMA1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC4108C /* DMA1 Inner Loop Count Start Value */
-#define DMA1_X_MODIFY 0xFFC41090 /* DMA1 Inner Loop Address Increment */
-#define DMA1_Y_COUNT 0xFFC41094 /* DMA1 Outer Loop Count Start Value (2D only) */
-#define DMA1_Y_MODIFY 0xFFC41098 /* DMA1 Outer Loop Address Increment (2D only) */
-#define DMA1_CURR_DESC_PTR 0xFFC410A4 /* DMA1 Current Descriptor Pointer */
-#define DMA1_PREV_DESC_PTR 0xFFC410A8 /* DMA1 Previous Initial Descriptor Pointer */
-#define DMA1_CURR_ADDR 0xFFC410AC /* DMA1 Current Address */
-#define DMA1_IRQ_STATUS 0xFFC410B0 /* DMA1 Status Register */
-#define DMA1_CURR_X_COUNT 0xFFC410B4 /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA1_CURR_Y_COUNT 0xFFC410B8 /* DMA1 Current Row Count (2D only) */
-#define DMA1_BWL_COUNT 0xFFC410C0 /* DMA1 Bandwidth Limit Count */
-#define DMA1_CURR_BWL_COUNT 0xFFC410C4 /* DMA1 Bandwidth Limit Count Current */
-#define DMA1_BWM_COUNT 0xFFC410C8 /* DMA1 Bandwidth Monitor Count */
-#define DMA1_CURR_BWM_COUNT 0xFFC410CC /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA2
- ========================= */
-#define DMA2_NEXT_DESC_PTR 0xFFC41100 /* DMA2 Pointer to Next Initial Descriptor */
-#define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */
-#define DMA2_CONFIG 0xFFC41108 /* DMA2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */
-#define DMA2_X_MODIFY 0xFFC41110 /* DMA2 Inner Loop Address Increment */
-#define DMA2_Y_COUNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */
-#define DMA2_Y_MODIFY 0xFFC41118 /* DMA2 Outer Loop Address Increment (2D only) */
-#define DMA2_CURR_DESC_PTR 0xFFC41124 /* DMA2 Current Descriptor Pointer */
-#define DMA2_PREV_DESC_PTR 0xFFC41128 /* DMA2 Previous Initial Descriptor Pointer */
-#define DMA2_CURR_ADDR 0xFFC4112C /* DMA2 Current Address */
-#define DMA2_IRQ_STATUS 0xFFC41130 /* DMA2 Status Register */
-#define DMA2_CURR_X_COUNT 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA2_CURR_Y_COUNT 0xFFC41138 /* DMA2 Current Row Count (2D only) */
-#define DMA2_BWL_COUNT 0xFFC41140 /* DMA2 Bandwidth Limit Count */
-#define DMA2_CURR_BWL_COUNT 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */
-#define DMA2_BWM_COUNT 0xFFC41148 /* DMA2 Bandwidth Monitor Count */
-#define DMA2_CURR_BWM_COUNT 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA3
- ========================= */
-#define DMA3_NEXT_DESC_PTR 0xFFC41180 /* DMA3 Pointer to Next Initial Descriptor */
-#define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */
-#define DMA3_CONFIG 0xFFC41188 /* DMA3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */
-#define DMA3_X_MODIFY 0xFFC41190 /* DMA3 Inner Loop Address Increment */
-#define DMA3_Y_COUNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */
-#define DMA3_Y_MODIFY 0xFFC41198 /* DMA3 Outer Loop Address Increment (2D only) */
-#define DMA3_CURR_DESC_PTR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */
-#define DMA3_PREV_DESC_PTR 0xFFC411A8 /* DMA3 Previous Initial Descriptor Pointer */
-#define DMA3_CURR_ADDR 0xFFC411AC /* DMA3 Current Address */
-#define DMA3_IRQ_STATUS 0xFFC411B0 /* DMA3 Status Register */
-#define DMA3_CURR_X_COUNT 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA3_CURR_Y_COUNT 0xFFC411B8 /* DMA3 Current Row Count (2D only) */
-#define DMA3_BWL_COUNT 0xFFC411C0 /* DMA3 Bandwidth Limit Count */
-#define DMA3_CURR_BWL_COUNT 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */
-#define DMA3_BWM_COUNT 0xFFC411C8 /* DMA3 Bandwidth Monitor Count */
-#define DMA3_CURR_BWM_COUNT 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA4
- ========================= */
-#define DMA4_NEXT_DESC_PTR 0xFFC41200 /* DMA4 Pointer to Next Initial Descriptor */
-#define DMA4_START_ADDR 0xFFC41204 /* DMA4 Start Address of Current Buffer */
-#define DMA4_CONFIG 0xFFC41208 /* DMA4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC4120C /* DMA4 Inner Loop Count Start Value */
-#define DMA4_X_MODIFY 0xFFC41210 /* DMA4 Inner Loop Address Increment */
-#define DMA4_Y_COUNT 0xFFC41214 /* DMA4 Outer Loop Count Start Value (2D only) */
-#define DMA4_Y_MODIFY 0xFFC41218 /* DMA4 Outer Loop Address Increment (2D only) */
-#define DMA4_CURR_DESC_PTR 0xFFC41224 /* DMA4 Current Descriptor Pointer */
-#define DMA4_PREV_DESC_PTR 0xFFC41228 /* DMA4 Previous Initial Descriptor Pointer */
-#define DMA4_CURR_ADDR 0xFFC4122C /* DMA4 Current Address */
-#define DMA4_IRQ_STATUS 0xFFC41230 /* DMA4 Status Register */
-#define DMA4_CURR_X_COUNT 0xFFC41234 /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA4_CURR_Y_COUNT 0xFFC41238 /* DMA4 Current Row Count (2D only) */
-#define DMA4_BWL_COUNT 0xFFC41240 /* DMA4 Bandwidth Limit Count */
-#define DMA4_CURR_BWL_COUNT 0xFFC41244 /* DMA4 Bandwidth Limit Count Current */
-#define DMA4_BWM_COUNT 0xFFC41248 /* DMA4 Bandwidth Monitor Count */
-#define DMA4_CURR_BWM_COUNT 0xFFC4124C /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA5
- ========================= */
-#define DMA5_NEXT_DESC_PTR 0xFFC41280 /* DMA5 Pointer to Next Initial Descriptor */
-#define DMA5_START_ADDR 0xFFC41284 /* DMA5 Start Address of Current Buffer */
-#define DMA5_CONFIG 0xFFC41288 /* DMA5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC4128C /* DMA5 Inner Loop Count Start Value */
-#define DMA5_X_MODIFY 0xFFC41290 /* DMA5 Inner Loop Address Increment */
-#define DMA5_Y_COUNT 0xFFC41294 /* DMA5 Outer Loop Count Start Value (2D only) */
-#define DMA5_Y_MODIFY 0xFFC41298 /* DMA5 Outer Loop Address Increment (2D only) */
-#define DMA5_CURR_DESC_PTR 0xFFC412A4 /* DMA5 Current Descriptor Pointer */
-#define DMA5_PREV_DESC_PTR 0xFFC412A8 /* DMA5 Previous Initial Descriptor Pointer */
-#define DMA5_CURR_ADDR 0xFFC412AC /* DMA5 Current Address */
-#define DMA5_IRQ_STATUS 0xFFC412B0 /* DMA5 Status Register */
-#define DMA5_CURR_X_COUNT 0xFFC412B4 /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA5_CURR_Y_COUNT 0xFFC412B8 /* DMA5 Current Row Count (2D only) */
-#define DMA5_BWL_COUNT 0xFFC412C0 /* DMA5 Bandwidth Limit Count */
-#define DMA5_CURR_BWL_COUNT 0xFFC412C4 /* DMA5 Bandwidth Limit Count Current */
-#define DMA5_BWM_COUNT 0xFFC412C8 /* DMA5 Bandwidth Monitor Count */
-#define DMA5_CURR_BWM_COUNT 0xFFC412CC /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA6
- ========================= */
-#define DMA6_NEXT_DESC_PTR 0xFFC41300 /* DMA6 Pointer to Next Initial Descriptor */
-#define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */
-#define DMA6_CONFIG 0xFFC41308 /* DMA6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */
-#define DMA6_X_MODIFY 0xFFC41310 /* DMA6 Inner Loop Address Increment */
-#define DMA6_Y_COUNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */
-#define DMA6_Y_MODIFY 0xFFC41318 /* DMA6 Outer Loop Address Increment (2D only) */
-#define DMA6_CURR_DESC_PTR 0xFFC41324 /* DMA6 Current Descriptor Pointer */
-#define DMA6_PREV_DESC_PTR 0xFFC41328 /* DMA6 Previous Initial Descriptor Pointer */
-#define DMA6_CURR_ADDR 0xFFC4132C /* DMA6 Current Address */
-#define DMA6_IRQ_STATUS 0xFFC41330 /* DMA6 Status Register */
-#define DMA6_CURR_X_COUNT 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA6_CURR_Y_COUNT 0xFFC41338 /* DMA6 Current Row Count (2D only) */
-#define DMA6_BWL_COUNT 0xFFC41340 /* DMA6 Bandwidth Limit Count */
-#define DMA6_CURR_BWL_COUNT 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */
-#define DMA6_BWM_COUNT 0xFFC41348 /* DMA6 Bandwidth Monitor Count */
-#define DMA6_CURR_BWM_COUNT 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA7
- ========================= */
-#define DMA7_NEXT_DESC_PTR 0xFFC41380 /* DMA7 Pointer to Next Initial Descriptor */
-#define DMA7_START_ADDR 0xFFC41384 /* DMA7 Start Address of Current Buffer */
-#define DMA7_CONFIG 0xFFC41388 /* DMA7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC4138C /* DMA7 Inner Loop Count Start Value */
-#define DMA7_X_MODIFY 0xFFC41390 /* DMA7 Inner Loop Address Increment */
-#define DMA7_Y_COUNT 0xFFC41394 /* DMA7 Outer Loop Count Start Value (2D only) */
-#define DMA7_Y_MODIFY 0xFFC41398 /* DMA7 Outer Loop Address Increment (2D only) */
-#define DMA7_CURR_DESC_PTR 0xFFC413A4 /* DMA7 Current Descriptor Pointer */
-#define DMA7_PREV_DESC_PTR 0xFFC413A8 /* DMA7 Previous Initial Descriptor Pointer */
-#define DMA7_CURR_ADDR 0xFFC413AC /* DMA7 Current Address */
-#define DMA7_IRQ_STATUS 0xFFC413B0 /* DMA7 Status Register */
-#define DMA7_CURR_X_COUNT 0xFFC413B4 /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA7_CURR_Y_COUNT 0xFFC413B8 /* DMA7 Current Row Count (2D only) */
-#define DMA7_BWL_COUNT 0xFFC413C0 /* DMA7 Bandwidth Limit Count */
-#define DMA7_CURR_BWL_COUNT 0xFFC413C4 /* DMA7 Bandwidth Limit Count Current */
-#define DMA7_BWM_COUNT 0xFFC413C8 /* DMA7 Bandwidth Monitor Count */
-#define DMA7_CURR_BWM_COUNT 0xFFC413CC /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA8
- ========================= */
-#define DMA8_NEXT_DESC_PTR 0xFFC41400 /* DMA8 Pointer to Next Initial Descriptor */
-#define DMA8_START_ADDR 0xFFC41404 /* DMA8 Start Address of Current Buffer */
-#define DMA8_CONFIG 0xFFC41408 /* DMA8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC4140C /* DMA8 Inner Loop Count Start Value */
-#define DMA8_X_MODIFY 0xFFC41410 /* DMA8 Inner Loop Address Increment */
-#define DMA8_Y_COUNT 0xFFC41414 /* DMA8 Outer Loop Count Start Value (2D only) */
-#define DMA8_Y_MODIFY 0xFFC41418 /* DMA8 Outer Loop Address Increment (2D only) */
-#define DMA8_CURR_DESC_PTR 0xFFC41424 /* DMA8 Current Descriptor Pointer */
-#define DMA8_PREV_DESC_PTR 0xFFC41428 /* DMA8 Previous Initial Descriptor Pointer */
-#define DMA8_CURR_ADDR 0xFFC4142C /* DMA8 Current Address */
-#define DMA8_IRQ_STATUS 0xFFC41430 /* DMA8 Status Register */
-#define DMA8_CURR_X_COUNT 0xFFC41434 /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA8_CURR_Y_COUNT 0xFFC41438 /* DMA8 Current Row Count (2D only) */
-#define DMA8_BWL_COUNT 0xFFC41440 /* DMA8 Bandwidth Limit Count */
-#define DMA8_CURR_BWL_COUNT 0xFFC41444 /* DMA8 Bandwidth Limit Count Current */
-#define DMA8_BWM_COUNT 0xFFC41448 /* DMA8 Bandwidth Monitor Count */
-#define DMA8_CURR_BWM_COUNT 0xFFC4144C /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA9
- ========================= */
-#define DMA9_NEXT_DESC_PTR 0xFFC41480 /* DMA9 Pointer to Next Initial Descriptor */
-#define DMA9_START_ADDR 0xFFC41484 /* DMA9 Start Address of Current Buffer */
-#define DMA9_CONFIG 0xFFC41488 /* DMA9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC4148C /* DMA9 Inner Loop Count Start Value */
-#define DMA9_X_MODIFY 0xFFC41490 /* DMA9 Inner Loop Address Increment */
-#define DMA9_Y_COUNT 0xFFC41494 /* DMA9 Outer Loop Count Start Value (2D only) */
-#define DMA9_Y_MODIFY 0xFFC41498 /* DMA9 Outer Loop Address Increment (2D only) */
-#define DMA9_CURR_DESC_PTR 0xFFC414A4 /* DMA9 Current Descriptor Pointer */
-#define DMA9_PREV_DESC_PTR 0xFFC414A8 /* DMA9 Previous Initial Descriptor Pointer */
-#define DMA9_CURR_ADDR 0xFFC414AC /* DMA9 Current Address */
-#define DMA9_IRQ_STATUS 0xFFC414B0 /* DMA9 Status Register */
-#define DMA9_CURR_X_COUNT 0xFFC414B4 /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA9_CURR_Y_COUNT 0xFFC414B8 /* DMA9 Current Row Count (2D only) */
-#define DMA9_BWL_COUNT 0xFFC414C0 /* DMA9 Bandwidth Limit Count */
-#define DMA9_CURR_BWL_COUNT 0xFFC414C4 /* DMA9 Bandwidth Limit Count Current */
-#define DMA9_BWM_COUNT 0xFFC414C8 /* DMA9 Bandwidth Monitor Count */
-#define DMA9_CURR_BWM_COUNT 0xFFC414CC /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA10
- ========================= */
-#define DMA10_NEXT_DESC_PTR 0xFFC05000 /* DMA10 Pointer to Next Initial Descriptor */
-#define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */
-#define DMA10_CONFIG 0xFFC05008 /* DMA10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
-#define DMA10_X_MODIFY 0xFFC05010 /* DMA10 Inner Loop Address Increment */
-#define DMA10_Y_COUNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */
-#define DMA10_Y_MODIFY 0xFFC05018 /* DMA10 Outer Loop Address Increment (2D only) */
-#define DMA10_CURR_DESC_PTR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
-#define DMA10_PREV_DESC_PTR 0xFFC05028 /* DMA10 Previous Initial Descriptor Pointer */
-#define DMA10_CURR_ADDR 0xFFC0502C /* DMA10 Current Address */
-#define DMA10_IRQ_STATUS 0xFFC05030 /* DMA10 Status Register */
-#define DMA10_CURR_X_COUNT 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA10_CURR_Y_COUNT 0xFFC05038 /* DMA10 Current Row Count (2D only) */
-#define DMA10_BWL_COUNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
-#define DMA10_CURR_BWL_COUNT 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
-#define DMA10_BWM_COUNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
-#define DMA10_CURR_BWM_COUNT 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA11
- ========================= */
-#define DMA11_NEXT_DESC_PTR 0xFFC05080 /* DMA11 Pointer to Next Initial Descriptor */
-#define DMA11_START_ADDR 0xFFC05084 /* DMA11 Start Address of Current Buffer */
-#define DMA11_CONFIG 0xFFC05088 /* DMA11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC0508C /* DMA11 Inner Loop Count Start Value */
-#define DMA11_X_MODIFY 0xFFC05090 /* DMA11 Inner Loop Address Increment */
-#define DMA11_Y_COUNT 0xFFC05094 /* DMA11 Outer Loop Count Start Value (2D only) */
-#define DMA11_Y_MODIFY 0xFFC05098 /* DMA11 Outer Loop Address Increment (2D only) */
-#define DMA11_CURR_DESC_PTR 0xFFC050A4 /* DMA11 Current Descriptor Pointer */
-#define DMA11_PREV_DESC_PTR 0xFFC050A8 /* DMA11 Previous Initial Descriptor Pointer */
-#define DMA11_CURR_ADDR 0xFFC050AC /* DMA11 Current Address */
-#define DMA11_IRQ_STATUS 0xFFC050B0 /* DMA11 Status Register */
-#define DMA11_CURR_X_COUNT 0xFFC050B4 /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA11_CURR_Y_COUNT 0xFFC050B8 /* DMA11 Current Row Count (2D only) */
-#define DMA11_BWL_COUNT 0xFFC050C0 /* DMA11 Bandwidth Limit Count */
-#define DMA11_CURR_BWL_COUNT 0xFFC050C4 /* DMA11 Bandwidth Limit Count Current */
-#define DMA11_BWM_COUNT 0xFFC050C8 /* DMA11 Bandwidth Monitor Count */
-#define DMA11_CURR_BWM_COUNT 0xFFC050CC /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA12
- ========================= */
-#define DMA12_NEXT_DESC_PTR 0xFFC05100 /* DMA12 Pointer to Next Initial Descriptor */
-#define DMA12_START_ADDR 0xFFC05104 /* DMA12 Start Address of Current Buffer */
-#define DMA12_CONFIG 0xFFC05108 /* DMA12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC0510C /* DMA12 Inner Loop Count Start Value */
-#define DMA12_X_MODIFY 0xFFC05110 /* DMA12 Inner Loop Address Increment */
-#define DMA12_Y_COUNT 0xFFC05114 /* DMA12 Outer Loop Count Start Value (2D only) */
-#define DMA12_Y_MODIFY 0xFFC05118 /* DMA12 Outer Loop Address Increment (2D only) */
-#define DMA12_CURR_DESC_PTR 0xFFC05124 /* DMA12 Current Descriptor Pointer */
-#define DMA12_PREV_DESC_PTR 0xFFC05128 /* DMA12 Previous Initial Descriptor Pointer */
-#define DMA12_CURR_ADDR 0xFFC0512C /* DMA12 Current Address */
-#define DMA12_IRQ_STATUS 0xFFC05130 /* DMA12 Status Register */
-#define DMA12_CURR_X_COUNT 0xFFC05134 /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA12_CURR_Y_COUNT 0xFFC05138 /* DMA12 Current Row Count (2D only) */
-#define DMA12_BWL_COUNT 0xFFC05140 /* DMA12 Bandwidth Limit Count */
-#define DMA12_CURR_BWL_COUNT 0xFFC05144 /* DMA12 Bandwidth Limit Count Current */
-#define DMA12_BWM_COUNT 0xFFC05148 /* DMA12 Bandwidth Monitor Count */
-#define DMA12_CURR_BWM_COUNT 0xFFC0514C /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA13
- ========================= */
-#define DMA13_NEXT_DESC_PTR 0xFFC07000 /* DMA13 Pointer to Next Initial Descriptor */
-#define DMA13_START_ADDR 0xFFC07004 /* DMA13 Start Address of Current Buffer */
-#define DMA13_CONFIG 0xFFC07008 /* DMA13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC0700C /* DMA13 Inner Loop Count Start Value */
-#define DMA13_X_MODIFY 0xFFC07010 /* DMA13 Inner Loop Address Increment */
-#define DMA13_Y_COUNT 0xFFC07014 /* DMA13 Outer Loop Count Start Value (2D only) */
-#define DMA13_Y_MODIFY 0xFFC07018 /* DMA13 Outer Loop Address Increment (2D only) */
-#define DMA13_CURR_DESC_PTR 0xFFC07024 /* DMA13 Current Descriptor Pointer */
-#define DMA13_PREV_DESC_PTR 0xFFC07028 /* DMA13 Previous Initial Descriptor Pointer */
-#define DMA13_CURR_ADDR 0xFFC0702C /* DMA13 Current Address */
-#define DMA13_IRQ_STATUS 0xFFC07030 /* DMA13 Status Register */
-#define DMA13_CURR_X_COUNT 0xFFC07034 /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA13_CURR_Y_COUNT 0xFFC07038 /* DMA13 Current Row Count (2D only) */
-#define DMA13_BWL_COUNT 0xFFC07040 /* DMA13 Bandwidth Limit Count */
-#define DMA13_CURR_BWL_COUNT 0xFFC07044 /* DMA13 Bandwidth Limit Count Current */
-#define DMA13_BWM_COUNT 0xFFC07048 /* DMA13 Bandwidth Monitor Count */
-#define DMA13_CURR_BWM_COUNT 0xFFC0704C /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA14
- ========================= */
-#define DMA14_NEXT_DESC_PTR 0xFFC07080 /* DMA14 Pointer to Next Initial Descriptor */
-#define DMA14_START_ADDR 0xFFC07084 /* DMA14 Start Address of Current Buffer */
-#define DMA14_CONFIG 0xFFC07088 /* DMA14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC0708C /* DMA14 Inner Loop Count Start Value */
-#define DMA14_X_MODIFY 0xFFC07090 /* DMA14 Inner Loop Address Increment */
-#define DMA14_Y_COUNT 0xFFC07094 /* DMA14 Outer Loop Count Start Value (2D only) */
-#define DMA14_Y_MODIFY 0xFFC07098 /* DMA14 Outer Loop Address Increment (2D only) */
-#define DMA14_CURR_DESC_PTR 0xFFC070A4 /* DMA14 Current Descriptor Pointer */
-#define DMA14_PREV_DESC_PTR 0xFFC070A8 /* DMA14 Previous Initial Descriptor Pointer */
-#define DMA14_CURR_ADDR 0xFFC070AC /* DMA14 Current Address */
-#define DMA14_IRQ_STATUS 0xFFC070B0 /* DMA14 Status Register */
-#define DMA14_CURR_X_COUNT 0xFFC070B4 /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA14_CURR_Y_COUNT 0xFFC070B8 /* DMA14 Current Row Count (2D only) */
-#define DMA14_BWL_COUNT 0xFFC070C0 /* DMA14 Bandwidth Limit Count */
-#define DMA14_CURR_BWL_COUNT 0xFFC070C4 /* DMA14 Bandwidth Limit Count Current */
-#define DMA14_BWM_COUNT 0xFFC070C8 /* DMA14 Bandwidth Monitor Count */
-#define DMA14_CURR_BWM_COUNT 0xFFC070CC /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA15
- ========================= */
-#define DMA15_NEXT_DESC_PTR 0xFFC07100 /* DMA15 Pointer to Next Initial Descriptor */
-#define DMA15_START_ADDR 0xFFC07104 /* DMA15 Start Address of Current Buffer */
-#define DMA15_CONFIG 0xFFC07108 /* DMA15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC0710C /* DMA15 Inner Loop Count Start Value */
-#define DMA15_X_MODIFY 0xFFC07110 /* DMA15 Inner Loop Address Increment */
-#define DMA15_Y_COUNT 0xFFC07114 /* DMA15 Outer Loop Count Start Value (2D only) */
-#define DMA15_Y_MODIFY 0xFFC07118 /* DMA15 Outer Loop Address Increment (2D only) */
-#define DMA15_CURR_DESC_PTR 0xFFC07124 /* DMA15 Current Descriptor Pointer */
-#define DMA15_PREV_DESC_PTR 0xFFC07128 /* DMA15 Previous Initial Descriptor Pointer */
-#define DMA15_CURR_ADDR 0xFFC0712C /* DMA15 Current Address */
-#define DMA15_IRQ_STATUS 0xFFC07130 /* DMA15 Status Register */
-#define DMA15_CURR_X_COUNT 0xFFC07134 /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA15_CURR_Y_COUNT 0xFFC07138 /* DMA15 Current Row Count (2D only) */
-#define DMA15_BWL_COUNT 0xFFC07140 /* DMA15 Bandwidth Limit Count */
-#define DMA15_CURR_BWL_COUNT 0xFFC07144 /* DMA15 Bandwidth Limit Count Current */
-#define DMA15_BWM_COUNT 0xFFC07148 /* DMA15 Bandwidth Monitor Count */
-#define DMA15_CURR_BWM_COUNT 0xFFC0714C /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA16
- ========================= */
-#define DMA16_NEXT_DESC_PTR 0xFFC07180 /* DMA16 Pointer to Next Initial Descriptor */
-#define DMA16_START_ADDR 0xFFC07184 /* DMA16 Start Address of Current Buffer */
-#define DMA16_CONFIG 0xFFC07188 /* DMA16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC0718C /* DMA16 Inner Loop Count Start Value */
-#define DMA16_X_MODIFY 0xFFC07190 /* DMA16 Inner Loop Address Increment */
-#define DMA16_Y_COUNT 0xFFC07194 /* DMA16 Outer Loop Count Start Value (2D only) */
-#define DMA16_Y_MODIFY 0xFFC07198 /* DMA16 Outer Loop Address Increment (2D only) */
-#define DMA16_CURR_DESC_PTR 0xFFC071A4 /* DMA16 Current Descriptor Pointer */
-#define DMA16_PREV_DESC_PTR 0xFFC071A8 /* DMA16 Previous Initial Descriptor Pointer */
-#define DMA16_CURR_ADDR 0xFFC071AC /* DMA16 Current Address */
-#define DMA16_IRQ_STATUS 0xFFC071B0 /* DMA16 Status Register */
-#define DMA16_CURR_X_COUNT 0xFFC071B4 /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA16_CURR_Y_COUNT 0xFFC071B8 /* DMA16 Current Row Count (2D only) */
-#define DMA16_BWL_COUNT 0xFFC071C0 /* DMA16 Bandwidth Limit Count */
-#define DMA16_CURR_BWL_COUNT 0xFFC071C4 /* DMA16 Bandwidth Limit Count Current */
-#define DMA16_BWM_COUNT 0xFFC071C8 /* DMA16 Bandwidth Monitor Count */
-#define DMA16_CURR_BWM_COUNT 0xFFC071CC /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA17
- ========================= */
-#define DMA17_NEXT_DESC_PTR 0xFFC07200 /* DMA17 Pointer to Next Initial Descriptor */
-#define DMA17_START_ADDR 0xFFC07204 /* DMA17 Start Address of Current Buffer */
-#define DMA17_CONFIG 0xFFC07208 /* DMA17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC0720C /* DMA17 Inner Loop Count Start Value */
-#define DMA17_X_MODIFY 0xFFC07210 /* DMA17 Inner Loop Address Increment */
-#define DMA17_Y_COUNT 0xFFC07214 /* DMA17 Outer Loop Count Start Value (2D only) */
-#define DMA17_Y_MODIFY 0xFFC07218 /* DMA17 Outer Loop Address Increment (2D only) */
-#define DMA17_CURR_DESC_PTR 0xFFC07224 /* DMA17 Current Descriptor Pointer */
-#define DMA17_PREV_DESC_PTR 0xFFC07228 /* DMA17 Previous Initial Descriptor Pointer */
-#define DMA17_CURR_ADDR 0xFFC0722C /* DMA17 Current Address */
-#define DMA17_IRQ_STATUS 0xFFC07230 /* DMA17 Status Register */
-#define DMA17_CURR_X_COUNT 0xFFC07234 /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA17_CURR_Y_COUNT 0xFFC07238 /* DMA17 Current Row Count (2D only) */
-#define DMA17_BWL_COUNT 0xFFC07240 /* DMA17 Bandwidth Limit Count */
-#define DMA17_CURR_BWL_COUNT 0xFFC07244 /* DMA17 Bandwidth Limit Count Current */
-#define DMA17_BWM_COUNT 0xFFC07248 /* DMA17 Bandwidth Monitor Count */
-#define DMA17_CURR_BWM_COUNT 0xFFC0724C /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA18
- ========================= */
-#define DMA18_NEXT_DESC_PTR 0xFFC07280 /* DMA18 Pointer to Next Initial Descriptor */
-#define DMA18_START_ADDR 0xFFC07284 /* DMA18 Start Address of Current Buffer */
-#define DMA18_CONFIG 0xFFC07288 /* DMA18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC0728C /* DMA18 Inner Loop Count Start Value */
-#define DMA18_X_MODIFY 0xFFC07290 /* DMA18 Inner Loop Address Increment */
-#define DMA18_Y_COUNT 0xFFC07294 /* DMA18 Outer Loop Count Start Value (2D only) */
-#define DMA18_Y_MODIFY 0xFFC07298 /* DMA18 Outer Loop Address Increment (2D only) */
-#define DMA18_CURR_DESC_PTR 0xFFC072A4 /* DMA18 Current Descriptor Pointer */
-#define DMA18_PREV_DESC_PTR 0xFFC072A8 /* DMA18 Previous Initial Descriptor Pointer */
-#define DMA18_CURR_ADDR 0xFFC072AC /* DMA18 Current Address */
-#define DMA18_IRQ_STATUS 0xFFC072B0 /* DMA18 Status Register */
-#define DMA18_CURR_X_COUNT 0xFFC072B4 /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA18_CURR_Y_COUNT 0xFFC072B8 /* DMA18 Current Row Count (2D only) */
-#define DMA18_BWL_COUNT 0xFFC072C0 /* DMA18 Bandwidth Limit Count */
-#define DMA18_CURR_BWL_COUNT 0xFFC072C4 /* DMA18 Bandwidth Limit Count Current */
-#define DMA18_BWM_COUNT 0xFFC072C8 /* DMA18 Bandwidth Monitor Count */
-#define DMA18_CURR_BWM_COUNT 0xFFC072CC /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA19
- ========================= */
-#define DMA19_NEXT_DESC_PTR 0xFFC07300 /* DMA19 Pointer to Next Initial Descriptor */
-#define DMA19_START_ADDR 0xFFC07304 /* DMA19 Start Address of Current Buffer */
-#define DMA19_CONFIG 0xFFC07308 /* DMA19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC0730C /* DMA19 Inner Loop Count Start Value */
-#define DMA19_X_MODIFY 0xFFC07310 /* DMA19 Inner Loop Address Increment */
-#define DMA19_Y_COUNT 0xFFC07314 /* DMA19 Outer Loop Count Start Value (2D only) */
-#define DMA19_Y_MODIFY 0xFFC07318 /* DMA19 Outer Loop Address Increment (2D only) */
-#define DMA19_CURR_DESC_PTR 0xFFC07324 /* DMA19 Current Descriptor Pointer */
-#define DMA19_PREV_DESC_PTR 0xFFC07328 /* DMA19 Previous Initial Descriptor Pointer */
-#define DMA19_CURR_ADDR 0xFFC0732C /* DMA19 Current Address */
-#define DMA19_IRQ_STATUS 0xFFC07330 /* DMA19 Status Register */
-#define DMA19_CURR_X_COUNT 0xFFC07334 /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA19_CURR_Y_COUNT 0xFFC07338 /* DMA19 Current Row Count (2D only) */
-#define DMA19_BWL_COUNT 0xFFC07340 /* DMA19 Bandwidth Limit Count */
-#define DMA19_CURR_BWL_COUNT 0xFFC07344 /* DMA19 Bandwidth Limit Count Current */
-#define DMA19_BWM_COUNT 0xFFC07348 /* DMA19 Bandwidth Monitor Count */
-#define DMA19_CURR_BWM_COUNT 0xFFC0734C /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA20
- ========================= */
-#define DMA20_NEXT_DESC_PTR 0xFFC07380 /* DMA20 Pointer to Next Initial Descriptor */
-#define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */
-#define DMA20_CONFIG 0xFFC07388 /* DMA20 Configuration Register */
-#define DMA20_X_COUNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */
-#define DMA20_X_MODIFY 0xFFC07390 /* DMA20 Inner Loop Address Increment */
-#define DMA20_Y_COUNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */
-#define DMA20_Y_MODIFY 0xFFC07398 /* DMA20 Outer Loop Address Increment (2D only) */
-#define DMA20_CURR_DESC_PTR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */
-#define DMA20_PREV_DESC_PTR 0xFFC073A8 /* DMA20 Previous Initial Descriptor Pointer */
-#define DMA20_CURR_ADDR 0xFFC073AC /* DMA20 Current Address */
-#define DMA20_IRQ_STATUS 0xFFC073B0 /* DMA20 Status Register */
-#define DMA20_CURR_X_COUNT 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA20_CURR_Y_COUNT 0xFFC073B8 /* DMA20 Current Row Count (2D only) */
-#define DMA20_BWL_COUNT 0xFFC073C0 /* DMA20 Bandwidth Limit Count */
-#define DMA20_CURR_BWL_COUNT 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */
-#define DMA20_BWM_COUNT 0xFFC073C8 /* DMA20 Bandwidth Monitor Count */
-#define DMA20_CURR_BWM_COUNT 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA21
- ========================= */
-#define DMA21_NEXT_DESC_PTR 0xFFC09000 /* DMA21 Pointer to Next Initial Descriptor */
-#define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */
-#define DMA21_CONFIG 0xFFC09008 /* DMA21 Configuration Register */
-#define DMA21_X_COUNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */
-#define DMA21_X_MODIFY 0xFFC09010 /* DMA21 Inner Loop Address Increment */
-#define DMA21_Y_COUNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */
-#define DMA21_Y_MODIFY 0xFFC09018 /* DMA21 Outer Loop Address Increment (2D only) */
-#define DMA21_CURR_DESC_PTR 0xFFC09024 /* DMA21 Current Descriptor Pointer */
-#define DMA21_PREV_DESC_PTR 0xFFC09028 /* DMA21 Previous Initial Descriptor Pointer */
-#define DMA21_CURR_ADDR 0xFFC0902C /* DMA21 Current Address */
-#define DMA21_IRQ_STATUS 0xFFC09030 /* DMA21 Status Register */
-#define DMA21_CURR_X_COUNT 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA21_CURR_Y_COUNT 0xFFC09038 /* DMA21 Current Row Count (2D only) */
-#define DMA21_BWL_COUNT 0xFFC09040 /* DMA21 Bandwidth Limit Count */
-#define DMA21_CURR_BWL_COUNT 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */
-#define DMA21_BWM_COUNT 0xFFC09048 /* DMA21 Bandwidth Monitor Count */
-#define DMA21_CURR_BWM_COUNT 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA22
- ========================= */
-#define DMA22_NEXT_DESC_PTR 0xFFC09080 /* DMA22 Pointer to Next Initial Descriptor */
-#define DMA22_START_ADDR 0xFFC09084 /* DMA22 Start Address of Current Buffer */
-#define DMA22_CONFIG 0xFFC09088 /* DMA22 Configuration Register */
-#define DMA22_X_COUNT 0xFFC0908C /* DMA22 Inner Loop Count Start Value */
-#define DMA22_X_MODIFY 0xFFC09090 /* DMA22 Inner Loop Address Increment */
-#define DMA22_Y_COUNT 0xFFC09094 /* DMA22 Outer Loop Count Start Value (2D only) */
-#define DMA22_Y_MODIFY 0xFFC09098 /* DMA22 Outer Loop Address Increment (2D only) */
-#define DMA22_CURR_DESC_PTR 0xFFC090A4 /* DMA22 Current Descriptor Pointer */
-#define DMA22_PREV_DESC_PTR 0xFFC090A8 /* DMA22 Previous Initial Descriptor Pointer */
-#define DMA22_CURR_ADDR 0xFFC090AC /* DMA22 Current Address */
-#define DMA22_IRQ_STATUS 0xFFC090B0 /* DMA22 Status Register */
-#define DMA22_CURR_X_COUNT 0xFFC090B4 /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA22_CURR_Y_COUNT 0xFFC090B8 /* DMA22 Current Row Count (2D only) */
-#define DMA22_BWL_COUNT 0xFFC090C0 /* DMA22 Bandwidth Limit Count */
-#define DMA22_CURR_BWL_COUNT 0xFFC090C4 /* DMA22 Bandwidth Limit Count Current */
-#define DMA22_BWM_COUNT 0xFFC090C8 /* DMA22 Bandwidth Monitor Count */
-#define DMA22_CURR_BWM_COUNT 0xFFC090CC /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA23
- ========================= */
-#define DMA23_NEXT_DESC_PTR 0xFFC09100 /* DMA23 Pointer to Next Initial Descriptor */
-#define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */
-#define DMA23_CONFIG 0xFFC09108 /* DMA23 Configuration Register */
-#define DMA23_X_COUNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */
-#define DMA23_X_MODIFY 0xFFC09110 /* DMA23 Inner Loop Address Increment */
-#define DMA23_Y_COUNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */
-#define DMA23_Y_MODIFY 0xFFC09118 /* DMA23 Outer Loop Address Increment (2D only) */
-#define DMA23_CURR_DESC_PTR 0xFFC09124 /* DMA23 Current Descriptor Pointer */
-#define DMA23_PREV_DESC_PTR 0xFFC09128 /* DMA23 Previous Initial Descriptor Pointer */
-#define DMA23_CURR_ADDR 0xFFC0912C /* DMA23 Current Address */
-#define DMA23_IRQ_STATUS 0xFFC09130 /* DMA23 Status Register */
-#define DMA23_CURR_X_COUNT 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA23_CURR_Y_COUNT 0xFFC09138 /* DMA23 Current Row Count (2D only) */
-#define DMA23_BWL_COUNT 0xFFC09140 /* DMA23 Bandwidth Limit Count */
-#define DMA23_CURR_BWL_COUNT 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */
-#define DMA23_BWM_COUNT 0xFFC09148 /* DMA23 Bandwidth Monitor Count */
-#define DMA23_CURR_BWM_COUNT 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA24
- ========================= */
-#define DMA24_NEXT_DESC_PTR 0xFFC09180 /* DMA24 Pointer to Next Initial Descriptor */
-#define DMA24_START_ADDR 0xFFC09184 /* DMA24 Start Address of Current Buffer */
-#define DMA24_CONFIG 0xFFC09188 /* DMA24 Configuration Register */
-#define DMA24_X_COUNT 0xFFC0918C /* DMA24 Inner Loop Count Start Value */
-#define DMA24_X_MODIFY 0xFFC09190 /* DMA24 Inner Loop Address Increment */
-#define DMA24_Y_COUNT 0xFFC09194 /* DMA24 Outer Loop Count Start Value (2D only) */
-#define DMA24_Y_MODIFY 0xFFC09198 /* DMA24 Outer Loop Address Increment (2D only) */
-#define DMA24_CURR_DESC_PTR 0xFFC091A4 /* DMA24 Current Descriptor Pointer */
-#define DMA24_PREV_DESC_PTR 0xFFC091A8 /* DMA24 Previous Initial Descriptor Pointer */
-#define DMA24_CURR_ADDR 0xFFC091AC /* DMA24 Current Address */
-#define DMA24_IRQ_STATUS 0xFFC091B0 /* DMA24 Status Register */
-#define DMA24_CURR_X_COUNT 0xFFC091B4 /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA24_CURR_Y_COUNT 0xFFC091B8 /* DMA24 Current Row Count (2D only) */
-#define DMA24_BWL_COUNT 0xFFC091C0 /* DMA24 Bandwidth Limit Count */
-#define DMA24_CURR_BWL_COUNT 0xFFC091C4 /* DMA24 Bandwidth Limit Count Current */
-#define DMA24_BWM_COUNT 0xFFC091C8 /* DMA24 Bandwidth Monitor Count */
-#define DMA24_CURR_BWM_COUNT 0xFFC091CC /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA25
- ========================= */
-#define DMA25_NEXT_DESC_PTR 0xFFC09200 /* DMA25 Pointer to Next Initial Descriptor */
-#define DMA25_START_ADDR 0xFFC09204 /* DMA25 Start Address of Current Buffer */
-#define DMA25_CONFIG 0xFFC09208 /* DMA25 Configuration Register */
-#define DMA25_X_COUNT 0xFFC0920C /* DMA25 Inner Loop Count Start Value */
-#define DMA25_X_MODIFY 0xFFC09210 /* DMA25 Inner Loop Address Increment */
-#define DMA25_Y_COUNT 0xFFC09214 /* DMA25 Outer Loop Count Start Value (2D only) */
-#define DMA25_Y_MODIFY 0xFFC09218 /* DMA25 Outer Loop Address Increment (2D only) */
-#define DMA25_CURR_DESC_PTR 0xFFC09224 /* DMA25 Current Descriptor Pointer */
-#define DMA25_PREV_DESC_PTR 0xFFC09228 /* DMA25 Previous Initial Descriptor Pointer */
-#define DMA25_CURR_ADDR 0xFFC0922C /* DMA25 Current Address */
-#define DMA25_IRQ_STATUS 0xFFC09230 /* DMA25 Status Register */
-#define DMA25_CURR_X_COUNT 0xFFC09234 /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA25_CURR_Y_COUNT 0xFFC09238 /* DMA25 Current Row Count (2D only) */
-#define DMA25_BWL_COUNT 0xFFC09240 /* DMA25 Bandwidth Limit Count */
-#define DMA25_CURR_BWL_COUNT 0xFFC09244 /* DMA25 Bandwidth Limit Count Current */
-#define DMA25_BWM_COUNT 0xFFC09248 /* DMA25 Bandwidth Monitor Count */
-#define DMA25_CURR_BWM_COUNT 0xFFC0924C /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA26
- ========================= */
-#define DMA26_NEXT_DESC_PTR 0xFFC09280 /* DMA26 Pointer to Next Initial Descriptor */
-#define DMA26_START_ADDR 0xFFC09284 /* DMA26 Start Address of Current Buffer */
-#define DMA26_CONFIG 0xFFC09288 /* DMA26 Configuration Register */
-#define DMA26_X_COUNT 0xFFC0928C /* DMA26 Inner Loop Count Start Value */
-#define DMA26_X_MODIFY 0xFFC09290 /* DMA26 Inner Loop Address Increment */
-#define DMA26_Y_COUNT 0xFFC09294 /* DMA26 Outer Loop Count Start Value (2D only) */
-#define DMA26_Y_MODIFY 0xFFC09298 /* DMA26 Outer Loop Address Increment (2D only) */
-#define DMA26_CURR_DESC_PTR 0xFFC092A4 /* DMA26 Current Descriptor Pointer */
-#define DMA26_PREV_DESC_PTR 0xFFC092A8 /* DMA26 Previous Initial Descriptor Pointer */
-#define DMA26_CURR_ADDR 0xFFC092AC /* DMA26 Current Address */
-#define DMA26_IRQ_STATUS 0xFFC092B0 /* DMA26 Status Register */
-#define DMA26_CURR_X_COUNT 0xFFC092B4 /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA26_CURR_Y_COUNT 0xFFC092B8 /* DMA26 Current Row Count (2D only) */
-#define DMA26_BWL_COUNT 0xFFC092C0 /* DMA26 Bandwidth Limit Count */
-#define DMA26_CURR_BWL_COUNT 0xFFC092C4 /* DMA26 Bandwidth Limit Count Current */
-#define DMA26_BWM_COUNT 0xFFC092C8 /* DMA26 Bandwidth Monitor Count */
-#define DMA26_CURR_BWM_COUNT 0xFFC092CC /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA27
- ========================= */
-#define DMA27_NEXT_DESC_PTR 0xFFC09300 /* DMA27 Pointer to Next Initial Descriptor */
-#define DMA27_START_ADDR 0xFFC09304 /* DMA27 Start Address of Current Buffer */
-#define DMA27_CONFIG 0xFFC09308 /* DMA27 Configuration Register */
-#define DMA27_X_COUNT 0xFFC0930C /* DMA27 Inner Loop Count Start Value */
-#define DMA27_X_MODIFY 0xFFC09310 /* DMA27 Inner Loop Address Increment */
-#define DMA27_Y_COUNT 0xFFC09314 /* DMA27 Outer Loop Count Start Value (2D only) */
-#define DMA27_Y_MODIFY 0xFFC09318 /* DMA27 Outer Loop Address Increment (2D only) */
-#define DMA27_CURR_DESC_PTR 0xFFC09324 /* DMA27 Current Descriptor Pointer */
-#define DMA27_PREV_DESC_PTR 0xFFC09328 /* DMA27 Previous Initial Descriptor Pointer */
-#define DMA27_CURR_ADDR 0xFFC0932C /* DMA27 Current Address */
-#define DMA27_IRQ_STATUS 0xFFC09330 /* DMA27 Status Register */
-#define DMA27_CURR_X_COUNT 0xFFC09334 /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA27_CURR_Y_COUNT 0xFFC09338 /* DMA27 Current Row Count (2D only) */
-#define DMA27_BWL_COUNT 0xFFC09340 /* DMA27 Bandwidth Limit Count */
-#define DMA27_CURR_BWL_COUNT 0xFFC09344 /* DMA27 Bandwidth Limit Count Current */
-#define DMA27_BWM_COUNT 0xFFC09348 /* DMA27 Bandwidth Monitor Count */
-#define DMA27_CURR_BWM_COUNT 0xFFC0934C /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA28
- ========================= */
-#define DMA28_NEXT_DESC_PTR 0xFFC09380 /* DMA28 Pointer to Next Initial Descriptor */
-#define DMA28_START_ADDR 0xFFC09384 /* DMA28 Start Address of Current Buffer */
-#define DMA28_CONFIG 0xFFC09388 /* DMA28 Configuration Register */
-#define DMA28_X_COUNT 0xFFC0938C /* DMA28 Inner Loop Count Start Value */
-#define DMA28_X_MODIFY 0xFFC09390 /* DMA28 Inner Loop Address Increment */
-#define DMA28_Y_COUNT 0xFFC09394 /* DMA28 Outer Loop Count Start Value (2D only) */
-#define DMA28_Y_MODIFY 0xFFC09398 /* DMA28 Outer Loop Address Increment (2D only) */
-#define DMA28_CURR_DESC_PTR 0xFFC093A4 /* DMA28 Current Descriptor Pointer */
-#define DMA28_PREV_DESC_PTR 0xFFC093A8 /* DMA28 Previous Initial Descriptor Pointer */
-#define DMA28_CURR_ADDR 0xFFC093AC /* DMA28 Current Address */
-#define DMA28_IRQ_STATUS 0xFFC093B0 /* DMA28 Status Register */
-#define DMA28_CURR_X_COUNT 0xFFC093B4 /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA28_CURR_Y_COUNT 0xFFC093B8 /* DMA28 Current Row Count (2D only) */
-#define DMA28_BWL_COUNT 0xFFC093C0 /* DMA28 Bandwidth Limit Count */
-#define DMA28_CURR_BWL_COUNT 0xFFC093C4 /* DMA28 Bandwidth Limit Count Current */
-#define DMA28_BWM_COUNT 0xFFC093C8 /* DMA28 Bandwidth Monitor Count */
-#define DMA28_CURR_BWM_COUNT 0xFFC093CC /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA29
- ========================= */
-#define DMA29_NEXT_DESC_PTR 0xFFC0B000 /* DMA29 Pointer to Next Initial Descriptor */
-#define DMA29_START_ADDR 0xFFC0B004 /* DMA29 Start Address of Current Buffer */
-#define DMA29_CONFIG 0xFFC0B008 /* DMA29 Configuration Register */
-#define DMA29_X_COUNT 0xFFC0B00C /* DMA29 Inner Loop Count Start Value */
-#define DMA29_X_MODIFY 0xFFC0B010 /* DMA29 Inner Loop Address Increment */
-#define DMA29_Y_COUNT 0xFFC0B014 /* DMA29 Outer Loop Count Start Value (2D only) */
-#define DMA29_Y_MODIFY 0xFFC0B018 /* DMA29 Outer Loop Address Increment (2D only) */
-#define DMA29_CURR_DESC_PTR 0xFFC0B024 /* DMA29 Current Descriptor Pointer */
-#define DMA29_PREV_DESC_PTR 0xFFC0B028 /* DMA29 Previous Initial Descriptor Pointer */
-#define DMA29_CURR_ADDR 0xFFC0B02C /* DMA29 Current Address */
-#define DMA29_IRQ_STATUS 0xFFC0B030 /* DMA29 Status Register */
-#define DMA29_CURR_X_COUNT 0xFFC0B034 /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA29_CURR_Y_COUNT 0xFFC0B038 /* DMA29 Current Row Count (2D only) */
-#define DMA29_BWL_COUNT 0xFFC0B040 /* DMA29 Bandwidth Limit Count */
-#define DMA29_CURR_BWL_COUNT 0xFFC0B044 /* DMA29 Bandwidth Limit Count Current */
-#define DMA29_BWM_COUNT 0xFFC0B048 /* DMA29 Bandwidth Monitor Count */
-#define DMA29_CURR_BWM_COUNT 0xFFC0B04C /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA30
- ========================= */
-#define DMA30_NEXT_DESC_PTR 0xFFC0B080 /* DMA30 Pointer to Next Initial Descriptor */
-#define DMA30_START_ADDR 0xFFC0B084 /* DMA30 Start Address of Current Buffer */
-#define DMA30_CONFIG 0xFFC0B088 /* DMA30 Configuration Register */
-#define DMA30_X_COUNT 0xFFC0B08C /* DMA30 Inner Loop Count Start Value */
-#define DMA30_X_MODIFY 0xFFC0B090 /* DMA30 Inner Loop Address Increment */
-#define DMA30_Y_COUNT 0xFFC0B094 /* DMA30 Outer Loop Count Start Value (2D only) */
-#define DMA30_Y_MODIFY 0xFFC0B098 /* DMA30 Outer Loop Address Increment (2D only) */
-#define DMA30_CURR_DESC_PTR 0xFFC0B0A4 /* DMA30 Current Descriptor Pointer */
-#define DMA30_PREV_DESC_PTR 0xFFC0B0A8 /* DMA30 Previous Initial Descriptor Pointer */
-#define DMA30_CURR_ADDR 0xFFC0B0AC /* DMA30 Current Address */
-#define DMA30_IRQ_STATUS 0xFFC0B0B0 /* DMA30 Status Register */
-#define DMA30_CURR_X_COUNT 0xFFC0B0B4 /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA30_CURR_Y_COUNT 0xFFC0B0B8 /* DMA30 Current Row Count (2D only) */
-#define DMA30_BWL_COUNT 0xFFC0B0C0 /* DMA30 Bandwidth Limit Count */
-#define DMA30_CURR_BWL_COUNT 0xFFC0B0C4 /* DMA30 Bandwidth Limit Count Current */
-#define DMA30_BWM_COUNT 0xFFC0B0C8 /* DMA30 Bandwidth Monitor Count */
-#define DMA30_CURR_BWM_COUNT 0xFFC0B0CC /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA31
- ========================= */
-#define DMA31_NEXT_DESC_PTR 0xFFC0B100 /* DMA31 Pointer to Next Initial Descriptor */
-#define DMA31_START_ADDR 0xFFC0B104 /* DMA31 Start Address of Current Buffer */
-#define DMA31_CONFIG 0xFFC0B108 /* DMA31 Configuration Register */
-#define DMA31_X_COUNT 0xFFC0B10C /* DMA31 Inner Loop Count Start Value */
-#define DMA31_X_MODIFY 0xFFC0B110 /* DMA31 Inner Loop Address Increment */
-#define DMA31_Y_COUNT 0xFFC0B114 /* DMA31 Outer Loop Count Start Value (2D only) */
-#define DMA31_Y_MODIFY 0xFFC0B118 /* DMA31 Outer Loop Address Increment (2D only) */
-#define DMA31_CURR_DESC_PTR 0xFFC0B124 /* DMA31 Current Descriptor Pointer */
-#define DMA31_PREV_DESC_PTR 0xFFC0B128 /* DMA31 Previous Initial Descriptor Pointer */
-#define DMA31_CURR_ADDR 0xFFC0B12C /* DMA31 Current Address */
-#define DMA31_IRQ_STATUS 0xFFC0B130 /* DMA31 Status Register */
-#define DMA31_CURR_X_COUNT 0xFFC0B134 /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA31_CURR_Y_COUNT 0xFFC0B138 /* DMA31 Current Row Count (2D only) */
-#define DMA31_BWL_COUNT 0xFFC0B140 /* DMA31 Bandwidth Limit Count */
-#define DMA31_CURR_BWL_COUNT 0xFFC0B144 /* DMA31 Bandwidth Limit Count Current */
-#define DMA31_BWM_COUNT 0xFFC0B148 /* DMA31 Bandwidth Monitor Count */
-#define DMA31_CURR_BWM_COUNT 0xFFC0B14C /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA32
- ========================= */
-#define DMA32_NEXT_DESC_PTR 0xFFC0B180 /* DMA32 Pointer to Next Initial Descriptor */
-#define DMA32_START_ADDR 0xFFC0B184 /* DMA32 Start Address of Current Buffer */
-#define DMA32_CONFIG 0xFFC0B188 /* DMA32 Configuration Register */
-#define DMA32_X_COUNT 0xFFC0B18C /* DMA32 Inner Loop Count Start Value */
-#define DMA32_X_MODIFY 0xFFC0B190 /* DMA32 Inner Loop Address Increment */
-#define DMA32_Y_COUNT 0xFFC0B194 /* DMA32 Outer Loop Count Start Value (2D only) */
-#define DMA32_Y_MODIFY 0xFFC0B198 /* DMA32 Outer Loop Address Increment (2D only) */
-#define DMA32_CURR_DESC_PTR 0xFFC0B1A4 /* DMA32 Current Descriptor Pointer */
-#define DMA32_PREV_DESC_PTR 0xFFC0B1A8 /* DMA32 Previous Initial Descriptor Pointer */
-#define DMA32_CURR_ADDR 0xFFC0B1AC /* DMA32 Current Address */
-#define DMA32_IRQ_STATUS 0xFFC0B1B0 /* DMA32 Status Register */
-#define DMA32_CURR_X_COUNT 0xFFC0B1B4 /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA32_CURR_Y_COUNT 0xFFC0B1B8 /* DMA32 Current Row Count (2D only) */
-#define DMA32_BWL_COUNT 0xFFC0B1C0 /* DMA32 Bandwidth Limit Count */
-#define DMA32_CURR_BWL_COUNT 0xFFC0B1C4 /* DMA32 Bandwidth Limit Count Current */
-#define DMA32_BWM_COUNT 0xFFC0B1C8 /* DMA32 Bandwidth Monitor Count */
-#define DMA32_CURR_BWM_COUNT 0xFFC0B1CC /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA33
- ========================= */
-#define DMA33_NEXT_DESC_PTR 0xFFC0D000 /* DMA33 Pointer to Next Initial Descriptor */
-#define DMA33_START_ADDR 0xFFC0D004 /* DMA33 Start Address of Current Buffer */
-#define DMA33_CONFIG 0xFFC0D008 /* DMA33 Configuration Register */
-#define DMA33_X_COUNT 0xFFC0D00C /* DMA33 Inner Loop Count Start Value */
-#define DMA33_X_MODIFY 0xFFC0D010 /* DMA33 Inner Loop Address Increment */
-#define DMA33_Y_COUNT 0xFFC0D014 /* DMA33 Outer Loop Count Start Value (2D only) */
-#define DMA33_Y_MODIFY 0xFFC0D018 /* DMA33 Outer Loop Address Increment (2D only) */
-#define DMA33_CURR_DESC_PTR 0xFFC0D024 /* DMA33 Current Descriptor Pointer */
-#define DMA33_PREV_DESC_PTR 0xFFC0D028 /* DMA33 Previous Initial Descriptor Pointer */
-#define DMA33_CURR_ADDR 0xFFC0D02C /* DMA33 Current Address */
-#define DMA33_IRQ_STATUS 0xFFC0D030 /* DMA33 Status Register */
-#define DMA33_CURR_X_COUNT 0xFFC0D034 /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA33_CURR_Y_COUNT 0xFFC0D038 /* DMA33 Current Row Count (2D only) */
-#define DMA33_BWL_COUNT 0xFFC0D040 /* DMA33 Bandwidth Limit Count */
-#define DMA33_CURR_BWL_COUNT 0xFFC0D044 /* DMA33 Bandwidth Limit Count Current */
-#define DMA33_BWM_COUNT 0xFFC0D048 /* DMA33 Bandwidth Monitor Count */
-#define DMA33_CURR_BWM_COUNT 0xFFC0D04C /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA34
- ========================= */
-#define DMA34_NEXT_DESC_PTR 0xFFC0D080 /* DMA34 Pointer to Next Initial Descriptor */
-#define DMA34_START_ADDR 0xFFC0D084 /* DMA34 Start Address of Current Buffer */
-#define DMA34_CONFIG 0xFFC0D088 /* DMA34 Configuration Register */
-#define DMA34_X_COUNT 0xFFC0D08C /* DMA34 Inner Loop Count Start Value */
-#define DMA34_X_MODIFY 0xFFC0D090 /* DMA34 Inner Loop Address Increment */
-#define DMA34_Y_COUNT 0xFFC0D094 /* DMA34 Outer Loop Count Start Value (2D only) */
-#define DMA34_Y_MODIFY 0xFFC0D098 /* DMA34 Outer Loop Address Increment (2D only) */
-#define DMA34_CURR_DESC_PTR 0xFFC0D0A4 /* DMA34 Current Descriptor Pointer */
-#define DMA34_PREV_DESC_PTR 0xFFC0D0A8 /* DMA34 Previous Initial Descriptor Pointer */
-#define DMA34_CURR_ADDR 0xFFC0D0AC /* DMA34 Current Address */
-#define DMA34_IRQ_STATUS 0xFFC0D0B0 /* DMA34 Status Register */
-#define DMA34_CURR_X_COUNT 0xFFC0D0B4 /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA34_CURR_Y_COUNT 0xFFC0D0B8 /* DMA34 Current Row Count (2D only) */
-#define DMA34_BWL_COUNT 0xFFC0D0C0 /* DMA34 Bandwidth Limit Count */
-#define DMA34_CURR_BWL_COUNT 0xFFC0D0C4 /* DMA34 Bandwidth Limit Count Current */
-#define DMA34_BWM_COUNT 0xFFC0D0C8 /* DMA34 Bandwidth Monitor Count */
-#define DMA34_CURR_BWM_COUNT 0xFFC0D0CC /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA35
- ========================= */
-#define DMA35_NEXT_DESC_PTR 0xFFC10000 /* DMA35 Pointer to Next Initial Descriptor */
-#define DMA35_START_ADDR 0xFFC10004 /* DMA35 Start Address of Current Buffer */
-#define DMA35_CONFIG 0xFFC10008 /* DMA35 Configuration Register */
-#define DMA35_X_COUNT 0xFFC1000C /* DMA35 Inner Loop Count Start Value */
-#define DMA35_X_MODIFY 0xFFC10010 /* DMA35 Inner Loop Address Increment */
-#define DMA35_Y_COUNT 0xFFC10014 /* DMA35 Outer Loop Count Start Value (2D only) */
-#define DMA35_Y_MODIFY 0xFFC10018 /* DMA35 Outer Loop Address Increment (2D only) */
-#define DMA35_CURR_DESC_PTR 0xFFC10024 /* DMA35 Current Descriptor Pointer */
-#define DMA35_PREV_DESC_PTR 0xFFC10028 /* DMA35 Previous Initial Descriptor Pointer */
-#define DMA35_CURR_ADDR 0xFFC1002C /* DMA35 Current Address */
-#define DMA35_IRQ_STATUS 0xFFC10030 /* DMA35 Status Register */
-#define DMA35_CURR_X_COUNT 0xFFC10034 /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA35_CURR_Y_COUNT 0xFFC10038 /* DMA35 Current Row Count (2D only) */
-#define DMA35_BWL_COUNT 0xFFC10040 /* DMA35 Bandwidth Limit Count */
-#define DMA35_CURR_BWL_COUNT 0xFFC10044 /* DMA35 Bandwidth Limit Count Current */
-#define DMA35_BWM_COUNT 0xFFC10048 /* DMA35 Bandwidth Monitor Count */
-#define DMA35_CURR_BWM_COUNT 0xFFC1004C /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA36
- ========================= */
-#define DMA36_NEXT_DESC_PTR 0xFFC10080 /* DMA36 Pointer to Next Initial Descriptor */
-#define DMA36_START_ADDR 0xFFC10084 /* DMA36 Start Address of Current Buffer */
-#define DMA36_CONFIG 0xFFC10088 /* DMA36 Configuration Register */
-#define DMA36_X_COUNT 0xFFC1008C /* DMA36 Inner Loop Count Start Value */
-#define DMA36_X_MODIFY 0xFFC10090 /* DMA36 Inner Loop Address Increment */
-#define DMA36_Y_COUNT 0xFFC10094 /* DMA36 Outer Loop Count Start Value (2D only) */
-#define DMA36_Y_MODIFY 0xFFC10098 /* DMA36 Outer Loop Address Increment (2D only) */
-#define DMA36_CURR_DESC_PTR 0xFFC100A4 /* DMA36 Current Descriptor Pointer */
-#define DMA36_PREV_DESC_PTR 0xFFC100A8 /* DMA36 Previous Initial Descriptor Pointer */
-#define DMA36_CURR_ADDR 0xFFC100AC /* DMA36 Current Address */
-#define DMA36_IRQ_STATUS 0xFFC100B0 /* DMA36 Status Register */
-#define DMA36_CURR_X_COUNT 0xFFC100B4 /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA36_CURR_Y_COUNT 0xFFC100B8 /* DMA36 Current Row Count (2D only) */
-#define DMA36_BWL_COUNT 0xFFC100C0 /* DMA36 Bandwidth Limit Count */
-#define DMA36_CURR_BWL_COUNT 0xFFC100C4 /* DMA36 Bandwidth Limit Count Current */
-#define DMA36_BWM_COUNT 0xFFC100C8 /* DMA36 Bandwidth Monitor Count */
-#define DMA36_CURR_BWM_COUNT 0xFFC100CC /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA37
- ========================= */
-#define DMA37_NEXT_DESC_PTR 0xFFC10100 /* DMA37 Pointer to Next Initial Descriptor */
-#define DMA37_START_ADDR 0xFFC10104 /* DMA37 Start Address of Current Buffer */
-#define DMA37_CONFIG 0xFFC10108 /* DMA37 Configuration Register */
-#define DMA37_X_COUNT 0xFFC1010C /* DMA37 Inner Loop Count Start Value */
-#define DMA37_X_MODIFY 0xFFC10110 /* DMA37 Inner Loop Address Increment */
-#define DMA37_Y_COUNT 0xFFC10114 /* DMA37 Outer Loop Count Start Value (2D only) */
-#define DMA37_Y_MODIFY 0xFFC10118 /* DMA37 Outer Loop Address Increment (2D only) */
-#define DMA37_CURR_DESC_PTR 0xFFC10124 /* DMA37 Current Descriptor Pointer */
-#define DMA37_PREV_DESC_PTR 0xFFC10128 /* DMA37 Previous Initial Descriptor Pointer */
-#define DMA37_CURR_ADDR 0xFFC1012C /* DMA37 Current Address */
-#define DMA37_IRQ_STATUS 0xFFC10130 /* DMA37 Status Register */
-#define DMA37_CURR_X_COUNT 0xFFC10134 /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA37_CURR_Y_COUNT 0xFFC10138 /* DMA37 Current Row Count (2D only) */
-#define DMA37_BWL_COUNT 0xFFC10140 /* DMA37 Bandwidth Limit Count */
-#define DMA37_CURR_BWL_COUNT 0xFFC10144 /* DMA37 Bandwidth Limit Count Current */
-#define DMA37_BWM_COUNT 0xFFC10148 /* DMA37 Bandwidth Monitor Count */
-#define DMA37_CURR_BWM_COUNT 0xFFC1014C /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA38
- ========================= */
-#define DMA38_NEXT_DESC_PTR 0xFFC12000 /* DMA38 Pointer to Next Initial Descriptor */
-#define DMA38_START_ADDR 0xFFC12004 /* DMA38 Start Address of Current Buffer */
-#define DMA38_CONFIG 0xFFC12008 /* DMA38 Configuration Register */
-#define DMA38_X_COUNT 0xFFC1200C /* DMA38 Inner Loop Count Start Value */
-#define DMA38_X_MODIFY 0xFFC12010 /* DMA38 Inner Loop Address Increment */
-#define DMA38_Y_COUNT 0xFFC12014 /* DMA38 Outer Loop Count Start Value (2D only) */
-#define DMA38_Y_MODIFY 0xFFC12018 /* DMA38 Outer Loop Address Increment (2D only) */
-#define DMA38_CURR_DESC_PTR 0xFFC12024 /* DMA38 Current Descriptor Pointer */
-#define DMA38_PREV_DESC_PTR 0xFFC12028 /* DMA38 Previous Initial Descriptor Pointer */
-#define DMA38_CURR_ADDR 0xFFC1202C /* DMA38 Current Address */
-#define DMA38_IRQ_STATUS 0xFFC12030 /* DMA38 Status Register */
-#define DMA38_CURR_X_COUNT 0xFFC12034 /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA38_CURR_Y_COUNT 0xFFC12038 /* DMA38 Current Row Count (2D only) */
-#define DMA38_BWL_COUNT 0xFFC12040 /* DMA38 Bandwidth Limit Count */
-#define DMA38_CURR_BWL_COUNT 0xFFC12044 /* DMA38 Bandwidth Limit Count Current */
-#define DMA38_BWM_COUNT 0xFFC12048 /* DMA38 Bandwidth Monitor Count */
-#define DMA38_CURR_BWM_COUNT 0xFFC1204C /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA39
- ========================= */
-#define DMA39_NEXT_DESC_PTR 0xFFC12080 /* DMA39 Pointer to Next Initial Descriptor */
-#define DMA39_START_ADDR 0xFFC12084 /* DMA39 Start Address of Current Buffer */
-#define DMA39_CONFIG 0xFFC12088 /* DMA39 Configuration Register */
-#define DMA39_X_COUNT 0xFFC1208C /* DMA39 Inner Loop Count Start Value */
-#define DMA39_X_MODIFY 0xFFC12090 /* DMA39 Inner Loop Address Increment */
-#define DMA39_Y_COUNT 0xFFC12094 /* DMA39 Outer Loop Count Start Value (2D only) */
-#define DMA39_Y_MODIFY 0xFFC12098 /* DMA39 Outer Loop Address Increment (2D only) */
-#define DMA39_CURR_DESC_PTR 0xFFC120A4 /* DMA39 Current Descriptor Pointer */
-#define DMA39_PREV_DESC_PTR 0xFFC120A8 /* DMA39 Previous Initial Descriptor Pointer */
-#define DMA39_CURR_ADDR 0xFFC120AC /* DMA39 Current Address */
-#define DMA39_IRQ_STATUS 0xFFC120B0 /* DMA39 Status Register */
-#define DMA39_CURR_X_COUNT 0xFFC120B4 /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA39_CURR_Y_COUNT 0xFFC120B8 /* DMA39 Current Row Count (2D only) */
-#define DMA39_BWL_COUNT 0xFFC120C0 /* DMA39 Bandwidth Limit Count */
-#define DMA39_CURR_BWL_COUNT 0xFFC120C4 /* DMA39 Bandwidth Limit Count Current */
-#define DMA39_BWM_COUNT 0xFFC120C8 /* DMA39 Bandwidth Monitor Count */
-#define DMA39_CURR_BWM_COUNT 0xFFC120CC /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA40
- ========================= */
-#define DMA40_NEXT_DESC_PTR 0xFFC12100 /* DMA40 Pointer to Next Initial Descriptor */
-#define DMA40_START_ADDR 0xFFC12104 /* DMA40 Start Address of Current Buffer */
-#define DMA40_CONFIG 0xFFC12108 /* DMA40 Configuration Register */
-#define DMA40_X_COUNT 0xFFC1210C /* DMA40 Inner Loop Count Start Value */
-#define DMA40_X_MODIFY 0xFFC12110 /* DMA40 Inner Loop Address Increment */
-#define DMA40_Y_COUNT 0xFFC12114 /* DMA40 Outer Loop Count Start Value (2D only) */
-#define DMA40_Y_MODIFY 0xFFC12118 /* DMA40 Outer Loop Address Increment (2D only) */
-#define DMA40_CURR_DESC_PTR 0xFFC12124 /* DMA40 Current Descriptor Pointer */
-#define DMA40_PREV_DESC_PTR 0xFFC12128 /* DMA40 Previous Initial Descriptor Pointer */
-#define DMA40_CURR_ADDR 0xFFC1212C /* DMA40 Current Address */
-#define DMA40_IRQ_STATUS 0xFFC12130 /* DMA40 Status Register */
-#define DMA40_CURR_X_COUNT 0xFFC12134 /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA40_CURR_Y_COUNT 0xFFC12138 /* DMA40 Current Row Count (2D only) */
-#define DMA40_BWL_COUNT 0xFFC12140 /* DMA40 Bandwidth Limit Count */
-#define DMA40_CURR_BWL_COUNT 0xFFC12144 /* DMA40 Bandwidth Limit Count Current */
-#define DMA40_BWM_COUNT 0xFFC12148 /* DMA40 Bandwidth Monitor Count */
-#define DMA40_CURR_BWM_COUNT 0xFFC1214C /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA41
- ========================= */
-#define DMA41_NEXT_DESC_PTR 0xFFC12180 /* DMA41 Pointer to Next Initial Descriptor */
-#define DMA41_START_ADDR 0xFFC12184 /* DMA41 Start Address of Current Buffer */
-#define DMA41_CONFIG 0xFFC12188 /* DMA41 Configuration Register */
-#define DMA41_X_COUNT 0xFFC1218C /* DMA41 Inner Loop Count Start Value */
-#define DMA41_X_MODIFY 0xFFC12190 /* DMA41 Inner Loop Address Increment */
-#define DMA41_Y_COUNT 0xFFC12194 /* DMA41 Outer Loop Count Start Value (2D only) */
-#define DMA41_Y_MODIFY 0xFFC12198 /* DMA41 Outer Loop Address Increment (2D only) */
-#define DMA41_CURR_DESC_PTR 0xFFC121A4 /* DMA41 Current Descriptor Pointer */
-#define DMA41_PREV_DESC_PTR 0xFFC121A8 /* DMA41 Previous Initial Descriptor Pointer */
-#define DMA41_CURR_ADDR 0xFFC121AC /* DMA41 Current Address */
-#define DMA41_IRQ_STATUS 0xFFC121B0 /* DMA41 Status Register */
-#define DMA41_CURR_X_COUNT 0xFFC121B4 /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA41_CURR_Y_COUNT 0xFFC121B8 /* DMA41 Current Row Count (2D only) */
-#define DMA41_BWL_COUNT 0xFFC121C0 /* DMA41 Bandwidth Limit Count */
-#define DMA41_CURR_BWL_COUNT 0xFFC121C4 /* DMA41 Bandwidth Limit Count Current */
-#define DMA41_BWM_COUNT 0xFFC121C8 /* DMA41 Bandwidth Monitor Count */
-#define DMA41_CURR_BWM_COUNT 0xFFC121CC /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA42
- ========================= */
-#define DMA42_NEXT_DESC_PTR 0xFFC14000 /* DMA42 Pointer to Next Initial Descriptor */
-#define DMA42_START_ADDR 0xFFC14004 /* DMA42 Start Address of Current Buffer */
-#define DMA42_CONFIG 0xFFC14008 /* DMA42 Configuration Register */
-#define DMA42_X_COUNT 0xFFC1400C /* DMA42 Inner Loop Count Start Value */
-#define DMA42_X_MODIFY 0xFFC14010 /* DMA42 Inner Loop Address Increment */
-#define DMA42_Y_COUNT 0xFFC14014 /* DMA42 Outer Loop Count Start Value (2D only) */
-#define DMA42_Y_MODIFY 0xFFC14018 /* DMA42 Outer Loop Address Increment (2D only) */
-#define DMA42_CURR_DESC_PTR 0xFFC14024 /* DMA42 Current Descriptor Pointer */
-#define DMA42_PREV_DESC_PTR 0xFFC14028 /* DMA42 Previous Initial Descriptor Pointer */
-#define DMA42_CURR_ADDR 0xFFC1402C /* DMA42 Current Address */
-#define DMA42_IRQ_STATUS 0xFFC14030 /* DMA42 Status Register */
-#define DMA42_CURR_X_COUNT 0xFFC14034 /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA42_CURR_Y_COUNT 0xFFC14038 /* DMA42 Current Row Count (2D only) */
-#define DMA42_BWL_COUNT 0xFFC14040 /* DMA42 Bandwidth Limit Count */
-#define DMA42_CURR_BWL_COUNT 0xFFC14044 /* DMA42 Bandwidth Limit Count Current */
-#define DMA42_BWM_COUNT 0xFFC14048 /* DMA42 Bandwidth Monitor Count */
-#define DMA42_CURR_BWM_COUNT 0xFFC1404C /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA43
- ========================= */
-#define DMA43_NEXT_DESC_PTR 0xFFC14080 /* DMA43 Pointer to Next Initial Descriptor */
-#define DMA43_START_ADDR 0xFFC14084 /* DMA43 Start Address of Current Buffer */
-#define DMA43_CONFIG 0xFFC14088 /* DMA43 Configuration Register */
-#define DMA43_X_COUNT 0xFFC1408C /* DMA43 Inner Loop Count Start Value */
-#define DMA43_X_MODIFY 0xFFC14090 /* DMA43 Inner Loop Address Increment */
-#define DMA43_Y_COUNT 0xFFC14094 /* DMA43 Outer Loop Count Start Value (2D only) */
-#define DMA43_Y_MODIFY 0xFFC14098 /* DMA43 Outer Loop Address Increment (2D only) */
-#define DMA43_CURR_DESC_PTR 0xFFC140A4 /* DMA43 Current Descriptor Pointer */
-#define DMA43_PREV_DESC_PTR 0xFFC140A8 /* DMA43 Previous Initial Descriptor Pointer */
-#define DMA43_CURR_ADDR 0xFFC140AC /* DMA43 Current Address */
-#define DMA43_IRQ_STATUS 0xFFC140B0 /* DMA43 Status Register */
-#define DMA43_CURR_X_COUNT 0xFFC140B4 /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA43_CURR_Y_COUNT 0xFFC140B8 /* DMA43 Current Row Count (2D only) */
-#define DMA43_BWL_COUNT 0xFFC140C0 /* DMA43 Bandwidth Limit Count */
-#define DMA43_CURR_BWL_COUNT 0xFFC140C4 /* DMA43 Bandwidth Limit Count Current */
-#define DMA43_BWM_COUNT 0xFFC140C8 /* DMA43 Bandwidth Monitor Count */
-#define DMA43_CURR_BWM_COUNT 0xFFC140CC /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA44
- ========================= */
-#define DMA44_NEXT_DESC_PTR 0xFFC14100 /* DMA44 Pointer to Next Initial Descriptor */
-#define DMA44_START_ADDR 0xFFC14104 /* DMA44 Start Address of Current Buffer */
-#define DMA44_CONFIG 0xFFC14108 /* DMA44 Configuration Register */
-#define DMA44_X_COUNT 0xFFC1410C /* DMA44 Inner Loop Count Start Value */
-#define DMA44_X_MODIFY 0xFFC14110 /* DMA44 Inner Loop Address Increment */
-#define DMA44_Y_COUNT 0xFFC14114 /* DMA44 Outer Loop Count Start Value (2D only) */
-#define DMA44_Y_MODIFY 0xFFC14118 /* DMA44 Outer Loop Address Increment (2D only) */
-#define DMA44_CURR_DESC_PTR 0xFFC14124 /* DMA44 Current Descriptor Pointer */
-#define DMA44_PREV_DESC_PTR 0xFFC14128 /* DMA44 Previous Initial Descriptor Pointer */
-#define DMA44_CURR_ADDR 0xFFC1412C /* DMA44 Current Address */
-#define DMA44_IRQ_STATUS 0xFFC14130 /* DMA44 Status Register */
-#define DMA44_CURR_X_COUNT 0xFFC14134 /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA44_CURR_Y_COUNT 0xFFC14138 /* DMA44 Current Row Count (2D only) */
-#define DMA44_BWL_COUNT 0xFFC14140 /* DMA44 Bandwidth Limit Count */
-#define DMA44_CURR_BWL_COUNT 0xFFC14144 /* DMA44 Bandwidth Limit Count Current */
-#define DMA44_BWM_COUNT 0xFFC14148 /* DMA44 Bandwidth Monitor Count */
-#define DMA44_CURR_BWM_COUNT 0xFFC1414C /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA45
- ========================= */
-#define DMA45_NEXT_DESC_PTR 0xFFC14180 /* DMA45 Pointer to Next Initial Descriptor */
-#define DMA45_START_ADDR 0xFFC14184 /* DMA45 Start Address of Current Buffer */
-#define DMA45_CONFIG 0xFFC14188 /* DMA45 Configuration Register */
-#define DMA45_X_COUNT 0xFFC1418C /* DMA45 Inner Loop Count Start Value */
-#define DMA45_X_MODIFY 0xFFC14190 /* DMA45 Inner Loop Address Increment */
-#define DMA45_Y_COUNT 0xFFC14194 /* DMA45 Outer Loop Count Start Value (2D only) */
-#define DMA45_Y_MODIFY 0xFFC14198 /* DMA45 Outer Loop Address Increment (2D only) */
-#define DMA45_CURR_DESC_PTR 0xFFC141A4 /* DMA45 Current Descriptor Pointer */
-#define DMA45_PREV_DESC_PTR 0xFFC141A8 /* DMA45 Previous Initial Descriptor Pointer */
-#define DMA45_CURR_ADDR 0xFFC141AC /* DMA45 Current Address */
-#define DMA45_IRQ_STATUS 0xFFC141B0 /* DMA45 Status Register */
-#define DMA45_CURR_X_COUNT 0xFFC141B4 /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA45_CURR_Y_COUNT 0xFFC141B8 /* DMA45 Current Row Count (2D only) */
-#define DMA45_BWL_COUNT 0xFFC141C0 /* DMA45 Bandwidth Limit Count */
-#define DMA45_CURR_BWL_COUNT 0xFFC141C4 /* DMA45 Bandwidth Limit Count Current */
-#define DMA45_BWM_COUNT 0xFFC141C8 /* DMA45 Bandwidth Monitor Count */
-#define DMA45_CURR_BWM_COUNT 0xFFC141CC /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA46
- ========================= */
-#define DMA46_NEXT_DESC_PTR 0xFFC14200 /* DMA46 Pointer to Next Initial Descriptor */
-#define DMA46_START_ADDR 0xFFC14204 /* DMA46 Start Address of Current Buffer */
-#define DMA46_CONFIG 0xFFC14208 /* DMA46 Configuration Register */
-#define DMA46_X_COUNT 0xFFC1420C /* DMA46 Inner Loop Count Start Value */
-#define DMA46_X_MODIFY 0xFFC14210 /* DMA46 Inner Loop Address Increment */
-#define DMA46_Y_COUNT 0xFFC14214 /* DMA46 Outer Loop Count Start Value (2D only) */
-#define DMA46_Y_MODIFY 0xFFC14218 /* DMA46 Outer Loop Address Increment (2D only) */
-#define DMA46_CURR_DESC_PTR 0xFFC14224 /* DMA46 Current Descriptor Pointer */
-#define DMA46_PREV_DESC_PTR 0xFFC14228 /* DMA46 Previous Initial Descriptor Pointer */
-#define DMA46_CURR_ADDR 0xFFC1422C /* DMA46 Current Address */
-#define DMA46_IRQ_STATUS 0xFFC14230 /* DMA46 Status Register */
-#define DMA46_CURR_X_COUNT 0xFFC14234 /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA46_CURR_Y_COUNT 0xFFC14238 /* DMA46 Current Row Count (2D only) */
-#define DMA46_BWL_COUNT 0xFFC14240 /* DMA46 Bandwidth Limit Count */
-#define DMA46_CURR_BWL_COUNT 0xFFC14244 /* DMA46 Bandwidth Limit Count Current */
-#define DMA46_BWM_COUNT 0xFFC14248 /* DMA46 Bandwidth Monitor Count */
-#define DMA46_CURR_BWM_COUNT 0xFFC1424C /* DMA46 Bandwidth Monitor Count Current */
-
-
-/********************************************************************************
- DMA Alias Definitions
- ********************************************************************************/
-#define MDMA0_DEST_CRC0_NEXT_DESC_PTR (DMA22_NEXT_DESC_PTR)
-#define MDMA0_DEST_CRC0_START_ADDR (DMA22_START_ADDR)
-#define MDMA0_DEST_CRC0_CONFIG (DMA22_CONFIG)
-#define MDMA0_DEST_CRC0_X_COUNT (DMA22_X_COUNT)
-#define MDMA0_DEST_CRC0_X_MODIFY (DMA22_X_MODIFY)
-#define MDMA0_DEST_CRC0_Y_COUNT (DMA22_Y_COUNT)
-#define MDMA0_DEST_CRC0_Y_MODIFY (DMA22_Y_MODIFY)
-#define MDMA0_DEST_CRC0_CURR_DESC_PTR (DMA22_CURR_DESC_PTR)
-#define MDMA0_DEST_CRC0_PREV_DESC_PTR (DMA22_PREV_DESC_PTR)
-#define MDMA0_DEST_CRC0_CURR_ADDR (DMA22_CURR_ADDR)
-#define MDMA0_DEST_CRC0_IRQ_STATUS (DMA22_IRQ_STATUS)
-#define MDMA0_DEST_CRC0_CURR_X_COUNT (DMA22_CURR_X_COUNT)
-#define MDMA0_DEST_CRC0_CURR_Y_COUNT (DMA22_CURR_Y_COUNT)
-#define MDMA0_DEST_CRC0_BWL_COUNT (DMA22_BWL_COUNT)
-#define MDMA0_DEST_CRC0_CURR_BWL_COUNT (DMA22_CURR_BWL_COUNT)
-#define MDMA0_DEST_CRC0_BWM_COUNT (DMA22_BWM_COUNT)
-#define MDMA0_DEST_CRC0_CURR_BWM_COUNT (DMA22_CURR_BWM_COUNT)
-#define MDMA0_SRC_CRC0_NEXT_DESC_PTR (DMA21_NEXT_DESC_PTR)
-#define MDMA0_SRC_CRC0_START_ADDR (DMA21_START_ADDR)
-#define MDMA0_SRC_CRC0_CONFIG (DMA21_CONFIG)
-#define MDMA0_SRC_CRC0_X_COUNT (DMA21_X_COUNT)
-#define MDMA0_SRC_CRC0_X_MODIFY (DMA21_X_MODIFY)
-#define MDMA0_SRC_CRC0_Y_COUNT (DMA21_Y_COUNT)
-#define MDMA0_SRC_CRC0_Y_MODIFY (DMA21_Y_MODIFY)
-#define MDMA0_SRC_CRC0_CURR_DESC_PTR (DMA21_CURR_DESC_PTR)
-#define MDMA0_SRC_CRC0_PREV_DESC_PTR (DMA21_PREV_DESC_PTR)
-#define MDMA0_SRC_CRC0_CURR_ADDR (DMA21_CURR_ADDR)
-#define MDMA0_SRC_CRC0_IRQ_STATUS (DMA21_IRQ_STATUS)
-#define MDMA0_SRC_CRC0_CURR_X_COUNT (DMA21_CURR_X_COUNT)
-#define MDMA0_SRC_CRC0_CURR_Y_COUNT (DMA21_CURR_Y_COUNT)
-#define MDMA0_SRC_CRC0_BWL_COUNT (DMA21_BWL_COUNT)
-#define MDMA0_SRC_CRC0_CURR_BWL_COUNT (DMA21_CURR_BWL_COUNT)
-#define MDMA0_SRC_CRC0_BWM_COUNT (DMA21_BWM_COUNT)
-#define MDMA0_SRC_CRC0_CURR_BWM_COUNT (DMA21_CURR_BWM_COUNT)
-#define MDMA1_DEST_CRC1_NEXT_DESC_PTR (DMA24_NEXT_DESC_PTR)
-#define MDMA1_DEST_CRC1_START_ADDR (DMA24_START_ADDR)
-#define MDMA1_DEST_CRC1_CONFIG (DMA24_CONFIG)
-#define MDMA1_DEST_CRC1_X_COUNT (DMA24_X_COUNT)
-#define MDMA1_DEST_CRC1_X_MODIFY (DMA24_X_MODIFY)
-#define MDMA1_DEST_CRC1_Y_COUNT (DMA24_Y_COUNT)
-#define MDMA1_DEST_CRC1_Y_MODIFY (DMA24_Y_MODIFY)
-#define MDMA1_DEST_CRC1_CURR_DESC_PTR (DMA24_CURR_DESC_PTR)
-#define MDMA1_DEST_CRC1_PREV_DESC_PTR (DMA24_PREV_DESC_PTR)
-#define MDMA1_DEST_CRC1_CURR_ADDR (DMA24_CURR_ADDR)
-#define MDMA1_DEST_CRC1_IRQ_STATUS (DMA24_IRQ_STATUS)
-#define MDMA1_DEST_CRC1_CURR_X_COUNT (DMA24_CURR_X_COUNT)
-#define MDMA1_DEST_CRC1_CURR_Y_COUNT (DMA24_CURR_Y_COUNT)
-#define MDMA1_DEST_CRC1_BWL_COUNT (DMA24_BWL_COUNT)
-#define MDMA1_DEST_CRC1_CURR_BWL_COUNT (DMA24_CURR_BWL_COUNT)
-#define MDMA1_DEST_CRC1_BWM_COUNT (DMA24_BWM_COUNT)
-#define MDMA1_DEST_CRC1_CURR_BWM_COUNT (DMA24_CURR_BWM_COUNT)
-#define MDMA1_SRC_CRC1_NEXT_DESC_PTR (DMA23_NEXT_DESC_PTR)
-#define MDMA1_SRC_CRC1_START_ADDR (DMA23_START_ADDR)
-#define MDMA1_SRC_CRC1_CONFIG (DMA23_CONFIG)
-#define MDMA1_SRC_CRC1_X_COUNT (DMA23_X_COUNT)
-#define MDMA1_SRC_CRC1_X_MODIFY (DMA23_X_MODIFY)
-#define MDMA1_SRC_CRC1_Y_COUNT (DMA23_Y_COUNT)
-#define MDMA1_SRC_CRC1_Y_MODIFY (DMA23_Y_MODIFY)
-#define MDMA1_SRC_CRC1_CURR_DESC_PTR (DMA23_CURR_DESC_PTR)
-#define MDMA1_SRC_CRC1_PREV_DESC_PTR (DMA23_PREV_DESC_PTR)
-#define MDMA1_SRC_CRC1_CURR_ADDR (DMA23_CURR_ADDR)
-#define MDMA1_SRC_CRC1_IRQ_STATUS (DMA23_IRQ_STATUS)
-#define MDMA1_SRC_CRC1_CURR_X_COUNT (DMA23_CURR_X_COUNT)
-#define MDMA1_SRC_CRC1_CURR_Y_COUNT (DMA23_CURR_Y_COUNT)
-#define MDMA1_SRC_CRC1_BWL_COUNT (DMA23_BWL_COUNT)
-#define MDMA1_SRC_CRC1_CURR_BWL_COUNT (DMA23_CURR_BWL_COUNT)
-#define MDMA1_SRC_CRC1_BWM_COUNT (DMA23_BWM_COUNT)
-#define MDMA1_SRC_CRC1_CURR_BWM_COUNT (DMA23_CURR_BWM_COUNT)
-#define MDMA2_DEST_NEXT_DESC_PTR (DMA26_NEXT_DESC_PTR)
-#define MDMA2_DEST_START_ADDR (DMA26_START_ADDR)
-#define MDMA2_DEST_CONFIG (DMA26_CONFIG)
-#define MDMA2_DEST_X_COUNT (DMA26_X_COUNT)
-#define MDMA2_DEST_X_MODIFY (DMA26_X_MODIFY)
-#define MDMA2_DEST_Y_COUNT (DMA26_Y_COUNT)
-#define MDMA2_DEST_Y_MODIFY (DMA26_Y_MODIFY)
-#define MDMA2_DEST_CURR_DESC_PTR (DMA26_CURR_DESC_PTR)
-#define MDMA2_DEST_PREV_DESC_PTR (DMA26_PREV_DESC_PTR)
-#define MDMA2_DEST_CURR_ADDR (DMA26_CURR_ADDR)
-#define MDMA2_DEST_IRQ_STATUS (DMA26_IRQ_STATUS)
-#define MDMA2_DEST_CURR_X_COUNT (DMA26_CURR_X_COUNT)
-#define MDMA2_DEST_CURR_Y_COUNT (DMA26_CURR_Y_COUNT)
-#define MDMA2_DEST_BWL_COUNT (DMA26_BWL_COUNT)
-#define MDMA2_DEST_CURR_BWL_COUNT (DMA26_CURR_BWL_COUNT)
-#define MDMA2_DEST_BWM_COUNT (DMA26_BWM_COUNT)
-#define MDMA2_DEST_CURR_BWM_COUNT (DMA26_CURR_BWM_COUNT)
-#define MDMA2_SRC_NEXT_DESC_PTR (DMA25_NEXT_DESC_PTR)
-#define MDMA2_SRC_START_ADDR (DMA25_START_ADDR)
-#define MDMA2_SRC_CONFIG (DMA25_CONFIG)
-#define MDMA2_SRC_X_COUNT (DMA25_X_COUNT)
-#define MDMA2_SRC_X_MODIFY (DMA25_X_MODIFY)
-#define MDMA2_SRC_Y_COUNT (DMA25_Y_COUNT)
-#define MDMA2_SRC_Y_MODIFY (DMA25_Y_MODIFY)
-#define MDMA2_SRC_CURR_DESC_PTR (DMA25_CURR_DESC_PTR)
-#define MDMA2_SRC_PREV_DESC_PTR (DMA25_PREV_DESC_PTR)
-#define MDMA2_SRC_CURR_ADDR (DMA25_CURR_ADDR)
-#define MDMA2_SRC_IRQ_STATUS (DMA25_IRQ_STATUS)
-#define MDMA2_SRC_CURR_X_COUNT (DMA25_CURR_X_COUNT)
-#define MDMA2_SRC_CURR_Y_COUNT (DMA25_CURR_Y_COUNT)
-#define MDMA2_SRC_BWL_COUNT (DMA25_BWL_COUNT)
-#define MDMA2_SRC_CURR_BWL_COUNT (DMA25_CURR_BWL_COUNT)
-#define MDMA2_SRC_BWM_COUNT (DMA25_BWM_COUNT)
-#define MDMA2_SRC_CURR_BWM_COUNT (DMA25_CURR_BWM_COUNT)
-#define MDMA3_DEST_NEXT_DESC_PTR (DMA28_NEXT_DESC_PTR)
-#define MDMA3_DEST_START_ADDR (DMA28_START_ADDR)
-#define MDMA3_DEST_CONFIG (DMA28_CONFIG)
-#define MDMA3_DEST_X_COUNT (DMA28_X_COUNT)
-#define MDMA3_DEST_X_MODIFY (DMA28_X_MODIFY)
-#define MDMA3_DEST_Y_COUNT (DMA28_Y_COUNT)
-#define MDMA3_DEST_Y_MODIFY (DMA28_Y_MODIFY)
-#define MDMA3_DEST_CURR_DESC_PTR (DMA28_CURR_DESC_PTR)
-#define MDMA3_DEST_PREV_DESC_PTR (DMA28_PREV_DESC_PTR)
-#define MDMA3_DEST_CURR_ADDR (DMA28_CURR_ADDR)
-#define MDMA3_DEST_IRQ_STATUS (DMA28_IRQ_STATUS)
-#define MDMA3_DEST_CURR_X_COUNT (DMA28_CURR_X_COUNT)
-#define MDMA3_DEST_CURR_Y_COUNT (DMA28_CURR_Y_COUNT)
-#define MDMA3_DEST_BWL_COUNT (DMA28_BWL_COUNT)
-#define MDMA3_DEST_CURR_BWL_COUNT (DMA28_CURR_BWL_COUNT)
-#define MDMA3_DEST_BWM_COUNT (DMA28_BWM_COUNT)
-#define MDMA3_DEST_CURR_BWM_COUNT (DMA28_CURR_BWM_COUNT)
-#define MDMA3_SRC_NEXT_DESC_PTR (DMA27_NEXT_DESC_PTR)
-#define MDMA3_SRC_START_ADDR (DMA27_START_ADDR)
-#define MDMA3_SRC_CONFIG (DMA27_CONFIG)
-#define MDMA3_SRC_X_COUNT (DMA27_X_COUNT)
-#define MDMA3_SRC_X_MODIFY (DMA27_X_MODIFY)
-#define MDMA3_SRC_Y_COUNT (DMA27_Y_COUNT)
-#define MDMA3_SRC_Y_MODIFY (DMA27_Y_MODIFY)
-#define MDMA3_SRC_CURR_DESC_PTR (DMA27_CURR_DESC_PTR)
-#define MDMA3_SRC_PREV_DESC_PTR (DMA27_PREV_DESC_PTR)
-#define MDMA3_SRC_CURR_ADDR (DMA27_CURR_ADDR)
-#define MDMA3_SRC_IRQ_STATUS (DMA27_IRQ_STATUS)
-#define MDMA3_SRC_CURR_X_COUNT (DMA27_CURR_X_COUNT)
-#define MDMA3_SRC_CURR_Y_COUNT (DMA27_CURR_Y_COUNT)
-#define MDMA3_SRC_BWL_COUNT (DMA27_BWL_COUNT)
-#define MDMA3_SRC_CURR_BWL_COUNT (DMA27_CURR_BWL_COUNT)
-#define MDMA3_SRC_BWM_COUNT (DMA27_BWM_COUNT)
-#define MDMA3_SRC_CURR_BWM_COUNT (DMA27_CURR_BWM_COUNT)
-
-
-/* =========================
- DMC Registers
- ========================= */
-
-/* =========================
- DMC0
- ========================= */
-#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */
-#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */
-#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */
-#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */
-#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */
-#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */
-#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */
-#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */
-#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */
-#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */
-#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */
-#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */
-#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */
-#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */
-#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */
-#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */
-#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */
-
-#define DEVSZ_64 0x000 /* DMC External Bank Size = 64Mbit */
-#define DEVSZ_128 0x100 /* DMC External Bank Size = 128Mbit */
-#define DEVSZ_256 0x200 /* DMC External Bank Size = 256Mbit */
-#define DEVSZ_512 0x300 /* DMC External Bank Size = 512Mbit */
-#define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */
-#define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */
-
-/* =========================
- L2CTL Registers
- ========================= */
-
-/* =========================
- L2CTL0
- ========================= */
-#define L2CTL0_CTL 0xFFCA3000 /* L2CTL0 L2 Control Register */
-#define L2CTL0_ACTL_C0 0xFFCA3004 /* L2CTL0 L2 Core 0 Access Control Register */
-#define L2CTL0_ACTL_C1 0xFFCA3008 /* L2CTL0 L2 Core 1 Access Control Register */
-#define L2CTL0_ACTL_SYS 0xFFCA300C /* L2CTL0 L2 System Access Control Register */
-#define L2CTL0_STAT 0xFFCA3010 /* L2CTL0 L2 Status Register */
-#define L2CTL0_RPCR 0xFFCA3014 /* L2CTL0 L2 Read Priority Count Register */
-#define L2CTL0_WPCR 0xFFCA3018 /* L2CTL0 L2 Write Priority Count Register */
-#define L2CTL0_RFA 0xFFCA3024 /* L2CTL0 L2 Refresh Address Register */
-#define L2CTL0_ERRADDR0 0xFFCA3040 /* L2CTL0 L2 Bank 0 ECC Error Address Register */
-#define L2CTL0_ERRADDR1 0xFFCA3044 /* L2CTL0 L2 Bank 1 ECC Error Address Register */
-#define L2CTL0_ERRADDR2 0xFFCA3048 /* L2CTL0 L2 Bank 2 ECC Error Address Register */
-#define L2CTL0_ERRADDR3 0xFFCA304C /* L2CTL0 L2 Bank 3 ECC Error Address Register */
-#define L2CTL0_ERRADDR4 0xFFCA3050 /* L2CTL0 L2 Bank 4 ECC Error Address Register */
-#define L2CTL0_ERRADDR5 0xFFCA3054 /* L2CTL0 L2 Bank 5 ECC Error Address Register */
-#define L2CTL0_ERRADDR6 0xFFCA3058 /* L2CTL0 L2 Bank 6 ECC Error Address Register */
-#define L2CTL0_ERRADDR7 0xFFCA305C /* L2CTL0 L2 Bank 7 ECC Error Address Register */
-#define L2CTL0_ET0 0xFFCA3080 /* L2CTL0 L2 AXI Error 0 Type Register */
-#define L2CTL0_EADDR0 0xFFCA3084 /* L2CTL0 L2 AXI Error 0 Address Register */
-#define L2CTL0_ET1 0xFFCA3088 /* L2CTL0 L2 AXI Error 1 Type Register */
-#define L2CTL0_EADDR1 0xFFCA308C /* L2CTL0 L2 AXI Error 1 Address Register */
-
-
-/* =========================
- SEC Registers
- ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Core Interface (SCI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-
-#define SEC_SCI_BASE 0xFFCA4400
-#define SEC_SCI_OFF 0x40
-#define SEC_CCTL 0x0 /* SEC Core Control Register n */
-#define SEC_CSTAT 0x4 /* SEC Core Status Register n */
-#define SEC_CPND 0x8 /* SEC Core Pending IRQ Register n */
-#define SEC_CACT 0xC /* SEC Core Active IRQ Register n */
-#define SEC_CPMSK 0x10 /* SEC Core IRQ Priority Mask Register n */
-#define SEC_CGMSK 0x14 /* SEC Core IRQ Group Mask Register n */
-#define SEC_CPLVL 0x18 /* SEC Core IRQ Priority Level Register n */
-#define SEC_CSID 0x1C /* SEC Core IRQ Source ID Register n */
-
-#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg)
-#define bfin_write_SEC_SCI(n, reg, val) \
- bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val)
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Fault Management Interface (SFI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FCTL 0xFFCA4010 /* SEC Fault Control Register */
-#define SEC_FSTAT 0xFFCA4014 /* SEC Fault Status Register */
-#define SEC_FSID 0xFFCA4018 /* SEC Fault Source ID Register */
-#define SEC_FEND 0xFFCA401C /* SEC Fault End Register */
-#define SEC_FDLY 0xFFCA4020 /* SEC Fault Delay Register */
-#define SEC_FDLY_CUR 0xFFCA4024 /* SEC Fault Delay Current Register */
-#define SEC_FSRDLY 0xFFCA4028 /* SEC Fault System Reset Delay Register */
-#define SEC_FSRDLY_CUR 0xFFCA402C /* SEC Fault System Reset Delay Current Register */
-#define SEC_FCOPP 0xFFCA4030 /* SEC Fault COP Period Register */
-#define SEC_FCOPP_CUR 0xFFCA4034 /* SEC Fault COP Period Current Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Global Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GCTL 0xFFCA4000 /* SEC Global Control Register */
-#define SEC_GSTAT 0xFFCA4004 /* SEC Global Status Register */
-#define SEC_RAISE 0xFFCA4008 /* SEC Global Raise Register */
-#define SEC_END 0xFFCA400C /* SEC Global End Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Source Interface (SSI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SCTL0 0xFFCA4800 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL1 0xFFCA4808 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL2 0xFFCA4810 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL3 0xFFCA4818 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL4 0xFFCA4820 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL5 0xFFCA4828 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL6 0xFFCA4830 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL7 0xFFCA4838 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL8 0xFFCA4840 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL9 0xFFCA4848 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL10 0xFFCA4850 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL11 0xFFCA4858 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL12 0xFFCA4860 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL13 0xFFCA4868 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL14 0xFFCA4870 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL15 0xFFCA4878 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL16 0xFFCA4880 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL17 0xFFCA4888 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL18 0xFFCA4890 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL19 0xFFCA4898 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL20 0xFFCA48A0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL21 0xFFCA48A8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL22 0xFFCA48B0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL23 0xFFCA48B8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL24 0xFFCA48C0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL25 0xFFCA48C8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL26 0xFFCA48D0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL27 0xFFCA48D8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL28 0xFFCA48E0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL29 0xFFCA48E8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL30 0xFFCA48F0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL31 0xFFCA48F8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL32 0xFFCA4900 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL33 0xFFCA4908 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL34 0xFFCA4910 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL35 0xFFCA4918 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL36 0xFFCA4920 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL37 0xFFCA4928 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL38 0xFFCA4930 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL39 0xFFCA4938 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL40 0xFFCA4940 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL41 0xFFCA4948 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL42 0xFFCA4950 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL43 0xFFCA4958 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL44 0xFFCA4960 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL45 0xFFCA4968 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL46 0xFFCA4970 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL47 0xFFCA4978 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL48 0xFFCA4980 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL49 0xFFCA4988 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL50 0xFFCA4990 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL51 0xFFCA4998 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL52 0xFFCA49A0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL53 0xFFCA49A8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL54 0xFFCA49B0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL55 0xFFCA49B8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL56 0xFFCA49C0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL57 0xFFCA49C8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL58 0xFFCA49D0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL59 0xFFCA49D8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL60 0xFFCA49E0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL61 0xFFCA49E8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL62 0xFFCA49F0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL63 0xFFCA49F8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL64 0xFFCA4A00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL65 0xFFCA4A08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL66 0xFFCA4A10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL67 0xFFCA4A18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL68 0xFFCA4A20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL69 0xFFCA4A28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL70 0xFFCA4A30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL71 0xFFCA4A38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL72 0xFFCA4A40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL73 0xFFCA4A48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL74 0xFFCA4A50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL75 0xFFCA4A58 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL76 0xFFCA4A60 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL77 0xFFCA4A68 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL78 0xFFCA4A70 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL79 0xFFCA4A78 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL80 0xFFCA4A80 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL81 0xFFCA4A88 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL82 0xFFCA4A90 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL83 0xFFCA4A98 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL84 0xFFCA4AA0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL85 0xFFCA4AA8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL86 0xFFCA4AB0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL87 0xFFCA4AB8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL88 0xFFCA4AC0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL89 0xFFCA4AC8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL90 0xFFCA4AD0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL91 0xFFCA4AD8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL92 0xFFCA4AE0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL93 0xFFCA4AE8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL94 0xFFCA4AF0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL95 0xFFCA4AF8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL96 0xFFCA4B00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL97 0xFFCA4B08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL98 0xFFCA4B10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL99 0xFFCA4B18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL100 0xFFCA4B20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL101 0xFFCA4B28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL102 0xFFCA4B30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL103 0xFFCA4B38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL104 0xFFCA4B40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL105 0xFFCA4B48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL106 0xFFCA4B50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL107 0xFFCA4B58 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL108 0xFFCA4B60 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL109 0xFFCA4B68 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL110 0xFFCA4B70 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL111 0xFFCA4B78 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL112 0xFFCA4B80 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL113 0xFFCA4B88 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL114 0xFFCA4B90 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL115 0xFFCA4B98 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL116 0xFFCA4BA0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL117 0xFFCA4BA8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL118 0xFFCA4BB0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL119 0xFFCA4BB8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL120 0xFFCA4BC0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL121 0xFFCA4BC8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL122 0xFFCA4BD0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL123 0xFFCA4BD8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL124 0xFFCA4BE0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL125 0xFFCA4BE8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL126 0xFFCA4BF0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL127 0xFFCA4BF8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL128 0xFFCA4C00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL129 0xFFCA4C08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL130 0xFFCA4C10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL131 0xFFCA4C18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL132 0xFFCA4C20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL133 0xFFCA4C28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL134 0xFFCA4C30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL135 0xFFCA4C38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL136 0xFFCA4C40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL137 0xFFCA4C48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL138 0xFFCA4C50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL139 0xFFCA4C58 /* SEC IRQ Source Control Register n */
-#define SEC_SSTAT0 0xFFCA4804 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT1 0xFFCA480C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT2 0xFFCA4814 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT3 0xFFCA481C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT4 0xFFCA4824 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT5 0xFFCA482C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT6 0xFFCA4834 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT7 0xFFCA483C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT8 0xFFCA4844 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT9 0xFFCA484C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT10 0xFFCA4854 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT11 0xFFCA485C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT12 0xFFCA4864 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT13 0xFFCA486C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT14 0xFFCA4874 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT15 0xFFCA487C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT16 0xFFCA4884 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT17 0xFFCA488C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT18 0xFFCA4894 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT19 0xFFCA489C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT20 0xFFCA48A4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT21 0xFFCA48AC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT22 0xFFCA48B4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT23 0xFFCA48BC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT24 0xFFCA48C4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT25 0xFFCA48CC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT26 0xFFCA48D4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT27 0xFFCA48DC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT28 0xFFCA48E4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT29 0xFFCA48EC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT30 0xFFCA48F4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT31 0xFFCA48FC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT32 0xFFCA4904 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT33 0xFFCA490C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT34 0xFFCA4914 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT35 0xFFCA491C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT36 0xFFCA4924 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT37 0xFFCA492C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT38 0xFFCA4934 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT39 0xFFCA493C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT40 0xFFCA4944 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT41 0xFFCA494C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT42 0xFFCA4954 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT43 0xFFCA495C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT44 0xFFCA4964 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT45 0xFFCA496C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT46 0xFFCA4974 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT47 0xFFCA497C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT48 0xFFCA4984 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT49 0xFFCA498C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT50 0xFFCA4994 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT51 0xFFCA499C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT52 0xFFCA49A4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT53 0xFFCA49AC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT54 0xFFCA49B4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT55 0xFFCA49BC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT56 0xFFCA49C4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT57 0xFFCA49CC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT58 0xFFCA49D4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT59 0xFFCA49DC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT60 0xFFCA49E4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT61 0xFFCA49EC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT62 0xFFCA49F4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT63 0xFFCA49FC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT64 0xFFCA4A04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT65 0xFFCA4A0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT66 0xFFCA4A14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT67 0xFFCA4A1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT68 0xFFCA4A24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT69 0xFFCA4A2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT70 0xFFCA4A34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT71 0xFFCA4A3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT72 0xFFCA4A44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT73 0xFFCA4A4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT74 0xFFCA4A54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT75 0xFFCA4A5C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT76 0xFFCA4A64 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT77 0xFFCA4A6C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT78 0xFFCA4A74 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT79 0xFFCA4A7C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT80 0xFFCA4A84 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT81 0xFFCA4A8C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT82 0xFFCA4A94 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT83 0xFFCA4A9C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT84 0xFFCA4AA4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT85 0xFFCA4AAC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT86 0xFFCA4AB4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT87 0xFFCA4ABC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT88 0xFFCA4AC4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT89 0xFFCA4ACC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT90 0xFFCA4AD4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT91 0xFFCA4ADC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT92 0xFFCA4AE4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT93 0xFFCA4AEC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT94 0xFFCA4AF4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT95 0xFFCA4AFC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT96 0xFFCA4B04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT97 0xFFCA4B0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT98 0xFFCA4B14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT99 0xFFCA4B1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT100 0xFFCA4B24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT101 0xFFCA4B2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT102 0xFFCA4B34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT103 0xFFCA4B3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT104 0xFFCA4B44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT105 0xFFCA4B4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT106 0xFFCA4B54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT107 0xFFCA4B5C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT108 0xFFCA4B64 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT109 0xFFCA4B6C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT110 0xFFCA4B74 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT111 0xFFCA4B7C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT112 0xFFCA4B84 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT113 0xFFCA4B8C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT114 0xFFCA4B94 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT115 0xFFCA4B9C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT116 0xFFCA4BA4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT117 0xFFCA4BAC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT118 0xFFCA4BB4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT119 0xFFCA4BBC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT120 0xFFCA4BC4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT121 0xFFCA4BCC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT122 0xFFCA4BD4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT123 0xFFCA4BDC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT124 0xFFCA4BE4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT125 0xFFCA4BEC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT126 0xFFCA4BF4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT127 0xFFCA4BFC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT128 0xFFCA4C04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT129 0xFFCA4C0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT130 0xFFCA4C14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT131 0xFFCA4C1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT132 0xFFCA4C24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT133 0xFFCA4C2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT134 0xFFCA4C34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT135 0xFFCA4C3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT136 0xFFCA4C44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT137 0xFFCA4C4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT138 0xFFCA4C54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT139 0xFFCA4C5C /* SEC IRQ Source Status Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CCTL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CCTL_NMI_EN 0x00010000 /* NMIEN: Enable */
-#define SEC_CCTL_WAITIDLE 0x00001000 /* WFI: Wait for Idle */
-#define SEC_CCTL_RESET 0x00000002 /* RESET: Reset */
-#define SEC_CCTL_EN 0x00000001 /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CSTAT_NMI 0x00010000 /* NMI Status */
-#define SEC_CSTAT_WAITING 0x00001000 /* WFI: Waiting */
-#define SEC_CSTAT_VALID_SID 0x00000400 /* SIDV: Valid */
-#define SEC_CSTAT_VALID_ACT 0x00000200 /* ACTV: Valid */
-#define SEC_CSTAT_VALID_PND 0x00000100 /* PNDV: Valid */
-#define SEC_CSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_CSTAT_ACKERR 0x00000010 /* ERRC: Acknowledge Error */
-#define SEC_CSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPND Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPND_PRIO 0x0000FF00 /* Highest Pending IRQ Priority */
-#define SEC_CPND_SID 0x000000FF /* Highest Pending IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CACT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CACT_PRIO 0x0000FF00 /* Highest Active IRQ Priority */
-#define SEC_CACT_SID 0x000000FF /* Highest Active IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPMSK Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPMSK_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CPMSK_PRIO 0x000000FF /* IRQ Priority Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CGMSK Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CGMSK_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CGMSK_MASK 0x00000100 /* UGRP: Mask Ungrouped Sources */
-#define SEC_CGMSK_GRP 0x0000000F /* Grouped Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPLVL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPLVL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CPLVL_PLVL 0x00000007 /* Priority Levels */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CSID Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CSID_SID 0x000000FF /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FCTL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_FCTL_FLTPND_MODE 0x00002000 /* TES: Fault Pending Mode */
-#define SEC_FCTL_COP_MODE 0x00001000 /* CMS: COP Mode */
-#define SEC_FCTL_FLTIN_EN 0x00000080 /* FIEN: Enable */
-#define SEC_FCTL_SYSRST_EN 0x00000040 /* SREN: Enable */
-#define SEC_FCTL_TRGOUT_EN 0x00000020 /* TOEN: Enable */
-#define SEC_FCTL_FLTOUT_EN 0x00000010 /* FOEN: Enable */
-#define SEC_FCTL_RESET 0x00000002 /* RESET: Reset */
-#define SEC_FCTL_EN 0x00000001 /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FSTAT_NXTFLT 0x00000400 /* NPND: Pending */
-#define SEC_FSTAT_FLTACT 0x00000200 /* ACT: Active Fault */
-#define SEC_FSTAT_FLTPND 0x00000100 /* PND: Pending */
-#define SEC_FSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_FSTAT_ENDERR 0x00000020 /* ERRC: End Error */
-#define SEC_FSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FSID Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FSID_SRC_EXTFLT 0x00010000 /* FEXT: Fault External */
-#define SEC_FSID_SID 0x000000FF /* Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FEND Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FEND_END_EXTFLT 0x00010000 /* FEXT: Fault External */
-#define SEC_FEND_SID 0x000000FF /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_GCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GCTL_LOCK 0x80000000 /* Lock */
-#define SEC_GCTL_RESET 0x00000002 /* Reset */
-#define SEC_GCTL_EN 0x00000001 /* Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_GSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GSTAT_LWERR 0x80000000 /* LWERR: Error Occurred */
-#define SEC_GSTAT_ADRERR 0x40000000 /* ADRERR: Error Occurred */
-#define SEC_GSTAT_SID 0x00FF0000 /* Source ID for SSI Error */
-#define SEC_GSTAT_SCI 0x00000F00 /* SCI ID for SCI Error */
-#define SEC_GSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_GSTAT_SCIERR 0x00000010 /* ERRC: SCI Error */
-#define SEC_GSTAT_SSIERR 0x00000020 /* ERRC: SSI Error */
-#define SEC_GSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_RAISE Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_RAISE_SID 0x000000FF /* Source ID IRQ Set to Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_END Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_END_SID 0x000000FF /* Source ID IRQ to End */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_SCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SCTL_LOCK 0x80000000 /* Lock */
-#define SEC_SCTL_CTG 0x0F000000 /* Core Target Select */
-#define SEC_SCTL_GRP 0x000F0000 /* Group Select */
-#define SEC_SCTL_PRIO 0x0000FF00 /* Priority Level Select */
-#define SEC_SCTL_ERR_EN 0x00000010 /* ERREN: Enable */
-#define SEC_SCTL_EDGE 0x00000008 /* ES: Edge Sensitive */
-#define SEC_SCTL_SRC_EN 0x00000004 /* SEN: Enable */
-#define SEC_SCTL_FAULT_EN 0x00000002 /* FEN: Enable */
-#define SEC_SCTL_INT_EN 0x00000001 /* IEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_SSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SSTAT_CHID 0x00FF0000 /* Channel ID */
-#define SEC_SSTAT_ACTIVE_SRC 0x00000200 /* ACT: Active Source */
-#define SEC_SSTAT_PENDING 0x00000100 /* PND: Pending */
-#define SEC_SSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_SSTAT_ENDERR 0x00000020 /* ERRC: End Error */
-#define SEC_SSTAT_ERR 0x00000002 /* Error */
-
-
-/* =========================
- RCU Registers
- ========================= */
-
-/* =========================
- RCU0
- ========================= */
-#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */
-#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */
-#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */
-#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */
-#define RCU0_SIDIS 0xFFCA6010 /* RCU0 System Interface Disable Register */
-#define RCU0_SISTAT 0xFFCA6014 /* RCU0 System Interface Status Register */
-#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */
-#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */
-#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */
-#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */
-
-
-/* =========================
- CGU0
- ========================= */
-#define CGU0_CTL 0xFFCA8000 /* CGU0 Control Register */
-#define CGU0_STAT 0xFFCA8004 /* CGU0 Status Register */
-#define CGU0_DIV 0xFFCA8008 /* CGU0 Divisor Register */
-#define CGU0_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */
-
-
-/* =========================
- DPM Registers
- ========================= */
-
-/* =========================
- DPM0
- ========================= */
-#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
-#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
-#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable Register */
-#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable Register */
-#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status Register */
-#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Status Sticky Register */
-#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable Register */
-#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
-#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
-#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
-#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
-#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */
-#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */
-#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */
-#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */
-#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */
-#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */
-#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */
-#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */
-#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */
-#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */
-#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */
-#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */
-#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */
-#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */
-#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */
-#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */
-#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */
-
-
-/* =========================
- DBG Registers
- ========================= */
-
-/* USB register */
-#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode */
-#define USB_POWER 0xFFCC1001 /* USB Power and Device Control */
-#define USB_INTRTX 0xFFCC1002 /* USB Transmit Interrupt */
-#define USB_INTRRX 0xFFCC1004 /* USB Receive Interrupts */
-#define USB_INTRTXE 0xFFCC1006 /* USB Transmit Interrupt Enable */
-#define USB_INTRRXE 0xFFCC1008 /* USB Receive Interrupt Enable */
-#define USB_INTRUSB 0xFFCC100A /* USB USB Interrupts */
-#define USB_INTRUSBE 0xFFCC100B /* USB USB Interrupt Enable */
-#define USB_FRAME 0xFFCC100C /* USB Frame Number */
-#define USB_INDEX 0xFFCC100E /* USB Index */
-#define USB_TESTMODE 0xFFCC100F /* USB Testmodes */
-#define USB_EPI_TXMAXP0 0xFFCC1010 /* USB Transmit Maximum Packet Length */
-#define USB_EP_NI0_TXMAXP 0xFFCC1010
-#define USB_EP0I_CSR0_H 0xFFCC1012 /* USB Config and Status EP0 */
-#define USB_EPI_TXCSR0_H 0xFFCC1012 /* USB Transmit Configuration and Status */
-#define USB_EP0I_CSR0_P 0xFFCC1012 /* USB Config and Status EP0 */
-#define USB_EPI_TXCSR0_P 0xFFCC1012 /* USB Transmit Configuration and Status */
-#define USB_EPI_RXMAXP0 0xFFCC1014 /* USB Receive Maximum Packet Length */
-#define USB_EPI_RXCSR0_H 0xFFCC1016 /* USB Receive Configuration and Status Register */
-#define USB_EPI_RXCSR0_P 0xFFCC1016 /* USB Receive Configuration and Status Register */
-#define USB_EP0I_CNT0 0xFFCC1018 /* USB Number of Received Bytes for Endpoint 0 */
-#define USB_EPI_RXCNT0 0xFFCC1018 /* USB Number of Byte Received */
-#define USB_EP0I_TYPE0 0xFFCC101A /* USB Speed for Endpoint 0 */
-#define USB_EPI_TXTYPE0 0xFFCC101A /* USB Transmit Type */
-#define USB_EP0I_NAKLIMIT0 0xFFCC101B /* USB NAK Response Timeout for Endpoint 0 */
-#define USB_EPI_TXINTERVAL0 0xFFCC101B /* USB Transmit Polling Interval */
-#define USB_EPI_RXTYPE0 0xFFCC101C /* USB Receive Type */
-#define USB_EPI_RXINTERVAL0 0xFFCC101D /* USB Receive Polling Interval */
-#define USB_EP0I_CFGDATA0 0xFFCC101F /* USB Configuration Information */
-#define USB_FIFOB0 0xFFCC1020 /* USB FIFO Data */
-#define USB_FIFOB1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFOB2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFOB3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFOB4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFOB5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFOB6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFOB7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFOB8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFOB9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFOB10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFOB11 0xFFCC104C /* USB FIFO Data */
-#define USB_FIFOH0 0xFFCC1020 /* USB FIFO Data */
-#define USB_FIFOH1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFOH2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFOH3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFOH4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFOH5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFOH6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFOH7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFOH8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFOH9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFOH10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFOH11 0xFFCC104C /* USB FIFO Data */
-#define USB_FIFO0 0xFFCC1020 /* USB FIFO Data */
-#define USB_EP0_FIFO 0xFFCC1020
-#define USB_FIFO1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFO2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFO3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFO4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFO5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFO6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFO7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFO8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFO9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFO10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFO11 0xFFCC104C /* USB FIFO Data */
-#define USB_OTG_DEV_CTL 0xFFCC1060 /* USB Device Control */
-#define USB_TXFIFOSZ 0xFFCC1062 /* USB Transmit FIFO Size */
-#define USB_RXFIFOSZ 0xFFCC1063 /* USB Receive FIFO Size */
-#define USB_TXFIFOADDR 0xFFCC1064 /* USB Transmit FIFO Address */
-#define USB_RXFIFOADDR 0xFFCC1066 /* USB Receive FIFO Address */
-#define USB_VENDSTAT 0xFFCC1068 /* USB Vendor Status */
-#define USB_HWVERS 0xFFCC106C /* USB Hardware Version */
-#define USB_EPINFO 0xFFCC1078 /* USB Endpoint Info */
-#define USB_RAMINFO 0xFFCC1079 /* USB Ram Information */
-#define USB_LINKINFO 0xFFCC107A /* USB Programmable Delay Values */
-#define USB_VPLEN 0xFFCC107B /* USB VBus Pulse Duration */
-#define USB_HS_EOF1 0xFFCC107C /* USB High Speed End of Frame Remaining */
-#define USB_FS_EOF1 0xFFCC107D /* USB Full Speed End of Frame Remaining */
-#define USB_LS_EOF1 0xFFCC107E /* USB Low Speed End of Frame Remaining */
-#define USB_SOFT_RST 0xFFCC107F /* USB Software Reset */
-#define USB_TXFUNCADDR0 0xFFCC1080 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR1 0xFFCC1088 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR2 0xFFCC1090 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR3 0xFFCC1098 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR4 0xFFCC10A0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR5 0xFFCC10A8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR6 0xFFCC10B0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR7 0xFFCC10B8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR8 0xFFCC10C0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR9 0xFFCC10C8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR10 0xFFCC10D0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR11 0xFFCC10D8 /* USB Transmit Function Address */
-#define USB_TXHUBADDR0 0xFFCC1082 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR1 0xFFCC108A /* USB Transmit Hub Address */
-#define USB_TXHUBADDR2 0xFFCC1092 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR3 0xFFCC109A /* USB Transmit Hub Address */
-#define USB_TXHUBADDR4 0xFFCC10A2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR5 0xFFCC10AA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR6 0xFFCC10B2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR7 0xFFCC10BA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR8 0xFFCC10C2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR9 0xFFCC10CA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR10 0xFFCC10D2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR11 0xFFCC10DA /* USB Transmit Hub Address */
-#define USB_TXHUBPORT0 0xFFCC1083 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT1 0xFFCC108B /* USB Transmit Hub Port */
-#define USB_TXHUBPORT2 0xFFCC1093 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT3 0xFFCC109B /* USB Transmit Hub Port */
-#define USB_TXHUBPORT4 0xFFCC10A3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT5 0xFFCC10AB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT6 0xFFCC10B3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT7 0xFFCC10BB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT8 0xFFCC10C3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT9 0xFFCC10CB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT10 0xFFCC10D3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT11 0xFFCC10DB /* USB Transmit Hub Port */
-#define USB_RXFUNCADDR0 0xFFCC1084 /* USB Receive Function Address */
-#define USB_RXFUNCADDR1 0xFFCC108C /* USB Receive Function Address */
-#define USB_RXFUNCADDR2 0xFFCC1094 /* USB Receive Function Address */
-#define USB_RXFUNCADDR3 0xFFCC109C /* USB Receive Function Address */
-#define USB_RXFUNCADDR4 0xFFCC10A4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR5 0xFFCC10AC /* USB Receive Function Address */
-#define USB_RXFUNCADDR6 0xFFCC10B4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR7 0xFFCC10BC /* USB Receive Function Address */
-#define USB_RXFUNCADDR8 0xFFCC10C4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR9 0xFFCC10CC /* USB Receive Function Address */
-#define USB_RXFUNCADDR10 0xFFCC10D4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR11 0xFFCC10DC /* USB Receive Function Address */
-#define USB_RXHUBADDR0 0xFFCC1086 /* USB Receive Hub Address */
-#define USB_RXHUBADDR1 0xFFCC108E /* USB Receive Hub Address */
-#define USB_RXHUBADDR2 0xFFCC1096 /* USB Receive Hub Address */
-#define USB_RXHUBADDR3 0xFFCC109E /* USB Receive Hub Address */
-#define USB_RXHUBADDR4 0xFFCC10A6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR5 0xFFCC10AE /* USB Receive Hub Address */
-#define USB_RXHUBADDR6 0xFFCC10B6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR7 0xFFCC10BE /* USB Receive Hub Address */
-#define USB_RXHUBADDR8 0xFFCC10C6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR9 0xFFCC10CE /* USB Receive Hub Address */
-#define USB_RXHUBADDR10 0xFFCC10D6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR11 0xFFCC10DE /* USB Receive Hub Address */
-#define USB_RXHUBPORT0 0xFFCC1087 /* USB Receive Hub Port */
-#define USB_RXHUBPORT1 0xFFCC108F /* USB Receive Hub Port */
-#define USB_RXHUBPORT2 0xFFCC1097 /* USB Receive Hub Port */
-#define USB_RXHUBPORT3 0xFFCC109F /* USB Receive Hub Port */
-#define USB_RXHUBPORT4 0xFFCC10A7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT5 0xFFCC10AF /* USB Receive Hub Port */
-#define USB_RXHUBPORT6 0xFFCC10B7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT7 0xFFCC10BF /* USB Receive Hub Port */
-#define USB_RXHUBPORT8 0xFFCC10C7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT9 0xFFCC10CF /* USB Receive Hub Port */
-#define USB_RXHUBPORT10 0xFFCC10D7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT11 0xFFCC10DF /* USB Receive Hub Port */
-#define USB_EP0_CSR0_H 0xFFCC1102 /* USB Config and Status EP0 */
-#define USB_EP0_CSR0_P 0xFFCC1102 /* USB Config and Status EP0 */
-#define USB_EP0_CNT0 0xFFCC1108 /* USB Number of Received Bytes for Endpoint 0 */
-#define USB_EP0_TYPE0 0xFFCC110A /* USB Speed for Endpoint 0 */
-#define USB_EP0_NAKLIMIT0 0xFFCC110B /* USB NAK Response Timeout for Endpoint 0 */
-#define USB_EP0_CFGDATA0 0xFFCC110F /* USB Configuration Information */
-#define USB_EP_TXMAXP0 0xFFCC1110 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP1 0xFFCC1120 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP2 0xFFCC1130 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP3 0xFFCC1140 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP4 0xFFCC1150 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP5 0xFFCC1160 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP6 0xFFCC1170 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP7 0xFFCC1180 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP8 0xFFCC1190 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP9 0xFFCC11A0 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP10 0xFFCC11B0 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXCSR0_H 0xFFCC1112 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR1_H 0xFFCC1122 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR2_H 0xFFCC1132 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR3_H 0xFFCC1142 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR4_H 0xFFCC1152 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR5_H 0xFFCC1162 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR6_H 0xFFCC1172 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR7_H 0xFFCC1182 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR8_H 0xFFCC1192 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR9_H 0xFFCC11A2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR10_H 0xFFCC11B2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR0_P 0xFFCC1112 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR1_P 0xFFCC1122 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR2_P 0xFFCC1132 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR3_P 0xFFCC1142 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR4_P 0xFFCC1152 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR5_P 0xFFCC1162 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR6_P 0xFFCC1172 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR7_P 0xFFCC1182 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR8_P 0xFFCC1192 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR9_P 0xFFCC11A2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR10_P 0xFFCC11B2 /* USB Transmit Configuration and Status */
-#define USB_EP_RXMAXP0 0xFFCC1114 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP1 0xFFCC1124 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP2 0xFFCC1134 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP3 0xFFCC1144 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP4 0xFFCC1154 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP5 0xFFCC1164 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP6 0xFFCC1174 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP7 0xFFCC1184 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP8 0xFFCC1194 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP9 0xFFCC11A4 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP10 0xFFCC11B4 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXCSR0_H 0xFFCC1116 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR1_H 0xFFCC1126 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR2_H 0xFFCC1136 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR3_H 0xFFCC1146 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR4_H 0xFFCC1156 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR5_H 0xFFCC1166 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR6_H 0xFFCC1176 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR7_H 0xFFCC1186 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR8_H 0xFFCC1196 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR9_H 0xFFCC11A6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR10_H 0xFFCC11B6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR0_P 0xFFCC1116 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR1_P 0xFFCC1126 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR2_P 0xFFCC1136 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR3_P 0xFFCC1146 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR4_P 0xFFCC1156 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR5_P 0xFFCC1166 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR6_P 0xFFCC1176 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR7_P 0xFFCC1186 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR8_P 0xFFCC1196 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR9_P 0xFFCC11A6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR10_P 0xFFCC11B6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCNT0 0xFFCC1118 /* USB Number of Byte Received */
-#define USB_EP_RXCNT1 0xFFCC1128 /* USB Number of Byte Received */
-#define USB_EP_RXCNT2 0xFFCC1138 /* USB Number of Byte Received */
-#define USB_EP_RXCNT3 0xFFCC1148 /* USB Number of Byte Received */
-#define USB_EP_RXCNT4 0xFFCC1158 /* USB Number of Byte Received */
-#define USB_EP_RXCNT5 0xFFCC1168 /* USB Number of Byte Received */
-#define USB_EP_RXCNT6 0xFFCC1178 /* USB Number of Byte Received */
-#define USB_EP_RXCNT7 0xFFCC1188 /* USB Number of Byte Received */
-#define USB_EP_RXCNT8 0xFFCC1198 /* USB Number of Byte Received */
-#define USB_EP_RXCNT9 0xFFCC11A8 /* USB Number of Byte Received */
-#define USB_EP_RXCNT10 0xFFCC11B8 /* USB Number of Byte Received */
-#define USB_EP_TXTYPE0 0xFFCC111A /* USB Transmit Type */
-#define USB_EP_TXTYPE1 0xFFCC112A /* USB Transmit Type */
-#define USB_EP_TXTYPE2 0xFFCC113A /* USB Transmit Type */
-#define USB_EP_TXTYPE3 0xFFCC114A /* USB Transmit Type */
-#define USB_EP_TXTYPE4 0xFFCC115A /* USB Transmit Type */
-#define USB_EP_TXTYPE5 0xFFCC116A /* USB Transmit Type */
-#define USB_EP_TXTYPE6 0xFFCC117A /* USB Transmit Type */
-#define USB_EP_TXTYPE7 0xFFCC118A /* USB Transmit Type */
-#define USB_EP_TXTYPE8 0xFFCC119A /* USB Transmit Type */
-#define USB_EP_TXTYPE9 0xFFCC11AA /* USB Transmit Type */
-#define USB_EP_TXTYPE10 0xFFCC11BA /* USB Transmit Type */
-#define USB_EP_TXINTERVAL0 0xFFCC111B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL1 0xFFCC112B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL2 0xFFCC113B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL3 0xFFCC114B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL4 0xFFCC115B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL5 0xFFCC116B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL6 0xFFCC117B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL7 0xFFCC118B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL8 0xFFCC119B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL9 0xFFCC11AB /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL10 0xFFCC11BB /* USB Transmit Polling Interval */
-#define USB_EP_RXTYPE0 0xFFCC111C /* USB Receive Type */
-#define USB_EP_RXTYPE1 0xFFCC112C /* USB Receive Type */
-#define USB_EP_RXTYPE2 0xFFCC113C /* USB Receive Type */
-#define USB_EP_RXTYPE3 0xFFCC114C /* USB Receive Type */
-#define USB_EP_RXTYPE4 0xFFCC115C /* USB Receive Type */
-#define USB_EP_RXTYPE5 0xFFCC116C /* USB Receive Type */
-#define USB_EP_RXTYPE6 0xFFCC117C /* USB Receive Type */
-#define USB_EP_RXTYPE7 0xFFCC118C /* USB Receive Type */
-#define USB_EP_RXTYPE8 0xFFCC119C /* USB Receive Type */
-#define USB_EP_RXTYPE9 0xFFCC11AC /* USB Receive Type */
-#define USB_EP_RXTYPE10 0xFFCC11BC /* USB Receive Type */
-#define USB_EP_RXINTERVAL0 0xFFCC111D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL1 0xFFCC112D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL2 0xFFCC113D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL3 0xFFCC114D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL4 0xFFCC115D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL5 0xFFCC116D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL6 0xFFCC117D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL7 0xFFCC118D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL8 0xFFCC119D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL9 0xFFCC11AD /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL10 0xFFCC11BD /* USB Receive Polling Interval */
-#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */
-#define USB_DMA_CTL0 0xFFCC1204 /* USB DMA Control */
-#define USB_DMA_CTL1 0xFFCC1214 /* USB DMA Control */
-#define USB_DMA_CTL2 0xFFCC1224 /* USB DMA Control */
-#define USB_DMA_CTL3 0xFFCC1234 /* USB DMA Control */
-#define USB_DMA_CTL4 0xFFCC1244 /* USB DMA Control */
-#define USB_DMA_CTL5 0xFFCC1254 /* USB DMA Control */
-#define USB_DMA_CTL6 0xFFCC1264 /* USB DMA Control */
-#define USB_DMA_CTL7 0xFFCC1274 /* USB DMA Control */
-#define USB_DMA_ADDR0 0xFFCC1208 /* USB DMA Address */
-#define USB_DMA_ADDR1 0xFFCC1218 /* USB DMA Address */
-#define USB_DMA_ADDR2 0xFFCC1228 /* USB DMA Address */
-#define USB_DMA_ADDR3 0xFFCC1238 /* USB DMA Address */
-#define USB_DMA_ADDR4 0xFFCC1248 /* USB DMA Address */
-#define USB_DMA_ADDR5 0xFFCC1258 /* USB DMA Address */
-#define USB_DMA_ADDR6 0xFFCC1268 /* USB DMA Address */
-#define USB_DMA_ADDR7 0xFFCC1278 /* USB DMA Address */
-#define USB_DMA_CNT0 0xFFCC120C /* USB DMA Count */
-#define USB_DMA_CNT1 0xFFCC121C /* USB DMA Count */
-#define USB_DMA_CNT2 0xFFCC122C /* USB DMA Count */
-#define USB_DMA_CNT3 0xFFCC123C /* USB DMA Count */
-#define USB_DMA_CNT4 0xFFCC124C /* USB DMA Count */
-#define USB_DMA_CNT5 0xFFCC125C /* USB DMA Count */
-#define USB_DMA_CNT6 0xFFCC126C /* USB DMA Count */
-#define USB_DMA_CNT7 0xFFCC127C /* USB DMA Count */
-#define USB_RQPKTCNT0 0xFFCC1300 /* USB Request Packet Count */
-#define USB_RQPKTCNT1 0xFFCC1304 /* USB Request Packet Count */
-#define USB_RQPKTCNT2 0xFFCC1308 /* USB Request Packet Count */
-#define USB_RQPKTCNT3 0xFFCC130C /* USB Request Packet Count */
-#define USB_RQPKTCNT4 0xFFCC1310 /* USB Request Packet Count */
-#define USB_RQPKTCNT5 0xFFCC1314 /* USB Request Packet Count */
-#define USB_RQPKTCNT6 0xFFCC1318 /* USB Request Packet Count */
-#define USB_RQPKTCNT7 0xFFCC131C /* USB Request Packet Count */
-#define USB_RQPKTCNT8 0xFFCC1320 /* USB Request Packet Count */
-#define USB_RQPKTCNT9 0xFFCC1324 /* USB Request Packet Count */
-#define USB_RQPKTCNT10 0xFFCC1328 /* USB Request Packet Count */
-#define USB_CT_UCH 0xFFCC1344 /* USB Chirp Timeout */
-#define USB_CT_HHSRTN 0xFFCC1346 /* USB High Speed Resume Return to Normal */
-#define USB_CT_HSBT 0xFFCC1348 /* USB High Speed Timeout */
-#define USB_LPM_ATTR 0xFFCC1360 /* USB LPM Attribute */
-#define USB_LPM_CTL 0xFFCC1362 /* USB LPM Control */
-#define USB_LPM_IEN 0xFFCC1363 /* USB LPM Interrupt Enable */
-#define USB_LPM_IRQ 0xFFCC1364 /* USB LPM Interrupt */
-#define USB_LPM_FADDR 0xFFCC1365 /* USB LPM Function Address */
-#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */
-#define USB_BAT_CHG 0xFFCC1381 /* USB Battery Charging */
-#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */
-#define USB_TESTCTL 0xFFCC1397 /* USB Test Control */
-#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */
-
-
-
-/* =========================
- CHIPID
- ========================= */
-
-#define CHIPID 0xffc00014
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-
-#endif /* _DEF_BF60X_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/dma.h b/arch/blackfin/mach-bf609/include/mach/dma.h
deleted file mode 100644
index 872d141..0000000
--- a/arch/blackfin/mach-bf609/include/mach/dma.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_TX 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT1_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT2_TX 4
-#define CH_SPORT2_RX 5
-#define CH_SPI0_TX 6
-#define CH_SPI0_RX 7
-#define CH_SPI1_TX 8
-#define CH_SPI1_RX 9
-#define CH_RSI 10
-#define CH_SDU 11
-#define CH_LP0 13
-#define CH_LP1 14
-#define CH_LP2 15
-#define CH_LP3 16
-#define CH_UART0_TX 17
-#define CH_UART0_RX 18
-#define CH_UART1_TX 19
-#define CH_UART1_RX 20
-#define CH_MEM_STREAM0_SRC_CRC0 21
-#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0
-#define CH_MEM_STREAM0_DEST_CRC0 22
-#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0
-#define CH_MEM_STREAM1_SRC_CRC1 23
-#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1
-#define CH_MEM_STREAM1_DEST_CRC1 24
-#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1
-#define CH_MEM_STREAM2_SRC 25
-#define CH_MEM_STREAM2_DEST 26
-#define CH_MEM_STREAM3_SRC 27
-#define CH_MEM_STREAM3_DEST 28
-#define CH_EPPI0_CH0 29
-#define CH_EPPI0_CH1 30
-#define CH_EPPI1_CH0 31
-#define CH_EPPI1_CH1 32
-#define CH_EPPI2_CH0 33
-#define CH_EPPI2_CH1 34
-#define CH_PIXC_CH0 35
-#define CH_PIXC_CH1 36
-#define CH_PIXC_CH2 37
-#define CH_PVP_CPDOB 38
-#define CH_PVP_CPDOC 39
-#define CH_PVP_CPSTAT 40
-#define CH_PVP_CPCI 41
-#define CH_PVP_MPDO 42
-#define CH_PVP_MPDI 43
-#define CH_PVP_MPSTAT 44
-#define CH_PVP_MPCI 45
-#define CH_PVP_CPDOA 46
-
-#define MAX_DMA_CHANNELS 47
-#define MAX_DMA_SUSPEND_CHANNELS 0
-#define DMA_MMR_SIZE_32
-
-#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
-#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
-#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
-#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
-#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
-#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
-#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
-#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
-#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
-#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
-#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
-#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
-#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
-#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
-
-#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
-#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
-#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
-#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
-#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
-#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
-
-#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
-#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
-#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
-#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
-#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
-#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
-#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
-#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
-#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
-#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
-#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
-#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
-#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
-#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
-#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
-#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
-#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
-#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
-
-#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
-#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
-#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
-#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
deleted file mode 100644
index 0718251..0000000
--- a/arch/blackfin/mach-bf609/include/mach/gpio.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 112
-
-#define GPIO_PA0 0
-#define GPIO_PA1 1
-#define GPIO_PA2 2
-#define GPIO_PA3 3
-#define GPIO_PA4 4
-#define GPIO_PA5 5
-#define GPIO_PA6 6
-#define GPIO_PA7 7
-#define GPIO_PA8 8
-#define GPIO_PA9 9
-#define GPIO_PA10 10
-#define GPIO_PA11 11
-#define GPIO_PA12 12
-#define GPIO_PA13 13
-#define GPIO_PA14 14
-#define GPIO_PA15 15
-#define GPIO_PB0 16
-#define GPIO_PB1 17
-#define GPIO_PB2 18
-#define GPIO_PB3 19
-#define GPIO_PB4 20
-#define GPIO_PB5 21
-#define GPIO_PB6 22
-#define GPIO_PB7 23
-#define GPIO_PB8 24
-#define GPIO_PB9 25
-#define GPIO_PB10 26
-#define GPIO_PB11 27
-#define GPIO_PB12 28
-#define GPIO_PB13 29
-#define GPIO_PB14 30
-#define GPIO_PB15 31
-#define GPIO_PC0 32
-#define GPIO_PC1 33
-#define GPIO_PC2 34
-#define GPIO_PC3 35
-#define GPIO_PC4 36
-#define GPIO_PC5 37
-#define GPIO_PC6 38
-#define GPIO_PC7 39
-#define GPIO_PC8 40
-#define GPIO_PC9 41
-#define GPIO_PC10 42
-#define GPIO_PC11 43
-#define GPIO_PC12 44
-#define GPIO_PC13 45
-#define GPIO_PC14 46
-#define GPIO_PC15 47
-#define GPIO_PD0 48
-#define GPIO_PD1 49
-#define GPIO_PD2 50
-#define GPIO_PD3 51
-#define GPIO_PD4 52
-#define GPIO_PD5 53
-#define GPIO_PD6 54
-#define GPIO_PD7 55
-#define GPIO_PD8 56
-#define GPIO_PD9 57
-#define GPIO_PD10 58
-#define GPIO_PD11 59
-#define GPIO_PD12 60
-#define GPIO_PD13 61
-#define GPIO_PD14 62
-#define GPIO_PD15 63
-#define GPIO_PE0 64
-#define GPIO_PE1 65
-#define GPIO_PE2 66
-#define GPIO_PE3 67
-#define GPIO_PE4 68
-#define GPIO_PE5 69
-#define GPIO_PE6 70
-#define GPIO_PE7 71
-#define GPIO_PE8 72
-#define GPIO_PE9 73
-#define GPIO_PE10 74
-#define GPIO_PE11 75
-#define GPIO_PE12 76
-#define GPIO_PE13 77
-#define GPIO_PE14 78
-#define GPIO_PE15 79
-#define GPIO_PF0 80
-#define GPIO_PF1 81
-#define GPIO_PF2 82
-#define GPIO_PF3 83
-#define GPIO_PF4 84
-#define GPIO_PF5 85
-#define GPIO_PF6 86
-#define GPIO_PF7 87
-#define GPIO_PF8 88
-#define GPIO_PF9 89
-#define GPIO_PF10 90
-#define GPIO_PF11 91
-#define GPIO_PF12 92
-#define GPIO_PF13 93
-#define GPIO_PF14 94
-#define GPIO_PF15 95
-#define GPIO_PG0 96
-#define GPIO_PG1 97
-#define GPIO_PG2 98
-#define GPIO_PG3 99
-#define GPIO_PG4 100
-#define GPIO_PG5 101
-#define GPIO_PG6 102
-#define GPIO_PG7 103
-#define GPIO_PG8 104
-#define GPIO_PG9 105
-#define GPIO_PG10 106
-#define GPIO_PG11 107
-#define GPIO_PG12 108
-#define GPIO_PG13 109
-#define GPIO_PG14 110
-#define GPIO_PG15 111
-
-
-#define BFIN_GPIO_PINT 1
-#define NR_PINT_SYS_IRQS 6
-#define NR_PINTS 112
-
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
- unsigned long port_fer;
- unsigned long port_fer_set;
- unsigned long port_fer_clear;
- unsigned long data;
- unsigned long data_set;
- unsigned long data_clear;
- unsigned long dir;
- unsigned long dir_set;
- unsigned long dir_clear;
- unsigned long inen;
- unsigned long inen_set;
- unsigned long inen_clear;
- unsigned long port_mux;
- unsigned long toggle;
- unsigned long polar;
- unsigned long polar_set;
- unsigned long polar_clear;
- unsigned long lock;
- unsigned long spare;
- unsigned long revid;
-};
-
-#endif
-
-#include <mach-common/ports-a.h>
-#include <mach-common/ports-b.h>
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
deleted file mode 100644
index d1cb6a8..0000000
--- a/arch/blackfin/mach-bf609/include/mach/irq.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF60x_IRQ_H_
-#define _BF60x_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (5 * 32)
-
-#define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */
-#define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */
-#define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */
-#define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */
-#define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */
-#define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */
-#define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */
-#define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */
-#define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */
-#define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */
-#define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */
-#define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */
-#define CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1)
-
-#define IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */
-#define IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */
-#define IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */
-#define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */
-#define IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */
-#define IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */
-#define IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */
-#define IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */
-#define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */
-#define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */
-#define IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */
-#define IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */
-#define IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */
-#define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */
-#define IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */
-#define IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */
-#define IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */
-#define IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */
-#define IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */
-#define IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */
-#define IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */
-#define IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */
-#define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */
-#define IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */
-#define IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */
-#define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */
-#define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */
-#define IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */
-#define IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */
-#define IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */
-#define IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */
-#define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */
-#define IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */
-#define IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */
-#define IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */
-#define IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */
-#define IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */
-#define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */
-#define IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */
-#define IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */
-#define IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */
-/* -- RESERVED -- 65 DMA12 Data (Reserved) */
-/* -- RESERVED -- 66 Reserved */
-/* -- RESERVED -- 67 Reserved */
-#define IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */
-/* -- RESERVED -- 69 EMAC0 Power (Reserved) */
-#define IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */
-/* -- RESERVED -- 71 EMAC1 Power (Reserved) */
-#define IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */
-#define IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */
-#define IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */
-#define IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */
-#define IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */
-#define IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */
-#define IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */
-#define IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */
-#define IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */
-#define IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */
-#define IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */
-#define IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */
-#define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */
-#define IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */
-#define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
-#define IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */
-#define IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0
-#define IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */
-#define IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */
-#define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
-#define IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */
-#define IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1
-#define IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */
-#define IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */
-#define IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */
-#define IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */
-#define IRQ_MDMAS2 IRQ_MDMA2_DEST
-#define IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */
-#define IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */
-#define IRQ_MDMAS3 IRQ_MDMA3_DEST
-#define IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */
-#define IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */
-#define IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */
-#define IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */
-#define IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */
-#define IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */
-#define IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */
-#define IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */
-#define IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */
-#define IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */
-#define IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */
-#define IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */
-#define IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */
-#define IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */
-#define IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */
-#define IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */
-#define IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */
-#define IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */
-#define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */
-#define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */
-#define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */
-#define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */
-#define IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */
-#define IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */
-#define IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */
-#define IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */
-#define IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */
-#define IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */
-#define IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */
-#define IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */
-#define IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */
-/* -- RESERVED -- 130 Reserved */
-#define IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */
-/* -- RESERVED -- 132 Reserved */
-#define IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */
-#define IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */
-#define IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */
-#define IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */
-#define IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */
-#define IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */
-#define IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */
-
-#define SYS_IRQS IRQ_SWU6
-
-#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
-#define IRQ_PA0 BFIN_PA_IRQ(0)
-#define IRQ_PA1 BFIN_PA_IRQ(1)
-#define IRQ_PA2 BFIN_PA_IRQ(2)
-#define IRQ_PA3 BFIN_PA_IRQ(3)
-#define IRQ_PA4 BFIN_PA_IRQ(4)
-#define IRQ_PA5 BFIN_PA_IRQ(5)
-#define IRQ_PA6 BFIN_PA_IRQ(6)
-#define IRQ_PA7 BFIN_PA_IRQ(7)
-#define IRQ_PA8 BFIN_PA_IRQ(8)
-#define IRQ_PA9 BFIN_PA_IRQ(9)
-#define IRQ_PA10 BFIN_PA_IRQ(10)
-#define IRQ_PA11 BFIN_PA_IRQ(11)
-#define IRQ_PA12 BFIN_PA_IRQ(12)
-#define IRQ_PA13 BFIN_PA_IRQ(13)
-#define IRQ_PA14 BFIN_PA_IRQ(14)
-#define IRQ_PA15 BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
-#define IRQ_PB0 BFIN_PB_IRQ(0)
-#define IRQ_PB1 BFIN_PB_IRQ(1)
-#define IRQ_PB2 BFIN_PB_IRQ(2)
-#define IRQ_PB3 BFIN_PB_IRQ(3)
-#define IRQ_PB4 BFIN_PB_IRQ(4)
-#define IRQ_PB5 BFIN_PB_IRQ(5)
-#define IRQ_PB6 BFIN_PB_IRQ(6)
-#define IRQ_PB7 BFIN_PB_IRQ(7)
-#define IRQ_PB8 BFIN_PB_IRQ(8)
-#define IRQ_PB9 BFIN_PB_IRQ(9)
-#define IRQ_PB10 BFIN_PB_IRQ(10)
-#define IRQ_PB11 BFIN_PB_IRQ(11)
-#define IRQ_PB12 BFIN_PB_IRQ(12)
-#define IRQ_PB13 BFIN_PB_IRQ(13)
-#define IRQ_PB14 BFIN_PB_IRQ(14)
-#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
-
-#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
-#define IRQ_PC0 BFIN_PC_IRQ(0)
-#define IRQ_PC1 BFIN_PC_IRQ(1)
-#define IRQ_PC2 BFIN_PC_IRQ(2)
-#define IRQ_PC3 BFIN_PC_IRQ(3)
-#define IRQ_PC4 BFIN_PC_IRQ(4)
-#define IRQ_PC5 BFIN_PC_IRQ(5)
-#define IRQ_PC6 BFIN_PC_IRQ(6)
-#define IRQ_PC7 BFIN_PC_IRQ(7)
-#define IRQ_PC8 BFIN_PC_IRQ(8)
-#define IRQ_PC9 BFIN_PC_IRQ(9)
-#define IRQ_PC10 BFIN_PC_IRQ(10)
-#define IRQ_PC11 BFIN_PC_IRQ(11)
-#define IRQ_PC12 BFIN_PC_IRQ(12)
-#define IRQ_PC13 BFIN_PC_IRQ(13)
-#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
-#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
-
-#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
-#define IRQ_PD0 BFIN_PD_IRQ(0)
-#define IRQ_PD1 BFIN_PD_IRQ(1)
-#define IRQ_PD2 BFIN_PD_IRQ(2)
-#define IRQ_PD3 BFIN_PD_IRQ(3)
-#define IRQ_PD4 BFIN_PD_IRQ(4)
-#define IRQ_PD5 BFIN_PD_IRQ(5)
-#define IRQ_PD6 BFIN_PD_IRQ(6)
-#define IRQ_PD7 BFIN_PD_IRQ(7)
-#define IRQ_PD8 BFIN_PD_IRQ(8)
-#define IRQ_PD9 BFIN_PD_IRQ(9)
-#define IRQ_PD10 BFIN_PD_IRQ(10)
-#define IRQ_PD11 BFIN_PD_IRQ(11)
-#define IRQ_PD12 BFIN_PD_IRQ(12)
-#define IRQ_PD13 BFIN_PD_IRQ(13)
-#define IRQ_PD14 BFIN_PD_IRQ(14)
-#define IRQ_PD15 BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
-#define IRQ_PE0 BFIN_PE_IRQ(0)
-#define IRQ_PE1 BFIN_PE_IRQ(1)
-#define IRQ_PE2 BFIN_PE_IRQ(2)
-#define IRQ_PE3 BFIN_PE_IRQ(3)
-#define IRQ_PE4 BFIN_PE_IRQ(4)
-#define IRQ_PE5 BFIN_PE_IRQ(5)
-#define IRQ_PE6 BFIN_PE_IRQ(6)
-#define IRQ_PE7 BFIN_PE_IRQ(7)
-#define IRQ_PE8 BFIN_PE_IRQ(8)
-#define IRQ_PE9 BFIN_PE_IRQ(9)
-#define IRQ_PE10 BFIN_PE_IRQ(10)
-#define IRQ_PE11 BFIN_PE_IRQ(11)
-#define IRQ_PE12 BFIN_PE_IRQ(12)
-#define IRQ_PE13 BFIN_PE_IRQ(13)
-#define IRQ_PE14 BFIN_PE_IRQ(14)
-#define IRQ_PE15 BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
-#define IRQ_PF0 BFIN_PF_IRQ(0)
-#define IRQ_PF1 BFIN_PF_IRQ(1)
-#define IRQ_PF2 BFIN_PF_IRQ(2)
-#define IRQ_PF3 BFIN_PF_IRQ(3)
-#define IRQ_PF4 BFIN_PF_IRQ(4)
-#define IRQ_PF5 BFIN_PF_IRQ(5)
-#define IRQ_PF6 BFIN_PF_IRQ(6)
-#define IRQ_PF7 BFIN_PF_IRQ(7)
-#define IRQ_PF8 BFIN_PF_IRQ(8)
-#define IRQ_PF9 BFIN_PF_IRQ(9)
-#define IRQ_PF10 BFIN_PF_IRQ(10)
-#define IRQ_PF11 BFIN_PF_IRQ(11)
-#define IRQ_PF12 BFIN_PF_IRQ(12)
-#define IRQ_PF13 BFIN_PF_IRQ(13)
-#define IRQ_PF14 BFIN_PF_IRQ(14)
-#define IRQ_PF15 BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
-#define IRQ_PG0 BFIN_PG_IRQ(0)
-#define IRQ_PG1 BFIN_PG_IRQ(1)
-#define IRQ_PG2 BFIN_PG_IRQ(2)
-#define IRQ_PG3 BFIN_PG_IRQ(3)
-#define IRQ_PG4 BFIN_PG_IRQ(4)
-#define IRQ_PG5 BFIN_PG_IRQ(5)
-#define IRQ_PG6 BFIN_PG_IRQ(6)
-#define IRQ_PG7 BFIN_PG_IRQ(7)
-#define IRQ_PG8 BFIN_PG_IRQ(8)
-#define IRQ_PG9 BFIN_PG_IRQ(9)
-#define IRQ_PG10 BFIN_PG_IRQ(10)
-#define IRQ_PG11 BFIN_PG_IRQ(11)
-#define IRQ_PG12 BFIN_PG_IRQ(12)
-#define IRQ_PG13 BFIN_PG_IRQ(13)
-#define IRQ_PG14 BFIN_PG_IRQ(14)
-#define IRQ_PG15 BFIN_PG_IRQ(15)
-
-#define GPIO_IRQ_BASE IRQ_PA0
-
-#define NR_MACH_IRQS (IRQ_PG15 + 1)
-
-#define SEC_SCTL_PRIO_OFFSET 8
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-extern u8 sec_int_priority[];
-
-/*
- * gpio pint registers layout
- */
-struct bfin_pint_regs {
- u32 mask_set;
- u32 mask_clear;
- u32 request;
- u32 assign;
- u32 edge_set;
- u32 edge_clear;
- u32 invert_set;
- u32 invert_clear;
- u32 pinstate;
- u32 latch;
- u32 __pad0[2];
-};
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/mem_map.h b/arch/blackfin/mach-bf609/include/mach/mem_map.h
deleted file mode 100644
index 20b65bf..0000000
--- a/arch/blackfin/mach-bf609/include/mach/mem_map.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * BF60x memory map
- *
- * Copyright 2011 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xC8000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF60x processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#define L1_CODE_LENGTH 0x10000
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-
-#define COREA_L1_SCRATCH_START 0xFFB00000
-#define COREB_L1_SCRATCH_START 0xFF700000
-
-#define COREB_L1_CODE_START 0xFF600000
-#define COREB_L1_DATA_A_START 0xFF400000
-#define COREB_L1_DATA_B_START 0xFF500000
-
-#define COREB_L1_CODE_LENGTH 0x14000
-#define COREB_L1_DATA_A_LENGTH 0x8000
-#define COREB_L1_DATA_B_LENGTH 0x8000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#define L2_START 0xC8080000
-#define L2_LENGTH 0x40000
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/pll.h b/arch/blackfin/mach-bf609/include/mach/pll.h
deleted file mode 100644
index 1857a4a..0000000
--- a/arch/blackfin/mach-bf609/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-/* #include <mach-common/pll.h> */
diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h
deleted file mode 100644
index a1efd93..0000000
--- a/arch/blackfin/mach-bf609/include/mach/pm.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __MACH_BF609_PM_H__
-#define __MACH_BF609_PM_H__
-
-#include <linux/suspend.h>
-#include <linux/platform_device.h>
-
-extern int bfin609_pm_enter(suspend_state_t state);
-extern int bf609_pm_prepare(void);
-extern void bf609_pm_finish(void);
-
-void bf609_hibernate(void);
-void bfin_sec_raise_irq(unsigned int sid);
-void coreb_enable(void);
-
-int bf609_nor_flash_init(struct platform_device *pdev);
-void bf609_nor_flash_exit(struct platform_device *pdev);
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
deleted file mode 100644
index c48bb71..0000000
--- a/arch/blackfin/mach-bf609/include/mach/portmux.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-/* EMAC RMII Port Mux */
-#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_CRS, \
- P_MII0_PTPPPS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-
-#define P_RMII1 {\
- P_MII1_ETxD0, \
- P_MII1_ETxD1, \
- P_MII1_ETxEN, \
- P_MII1_ERxD0, \
- P_MII1_ERxD1, \
- P_MII1_ERxER, \
- P_MII1_TxCLK, \
- P_MII1_PHYINT, \
- P_MII1_CRS, \
- P_MII1_PTPPPS, \
- P_MII1_MDC, \
- P_MII1_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-
-#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
-#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
-#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
-#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
-#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
-#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
-#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
-#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
-#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
-
-#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
-#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
-#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
-#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
-#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
-#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
-#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
-#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
-#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
-#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
-#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
-#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
-#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
-#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
-#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
-#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
-#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS
-#define P_DEFAULT_BOOT_SPI_CS
-
-/* CORE IDLE */
-#define P_IDLEA (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_IDLEB (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_SLEEP (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-/* UART Port Mux */
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-
-/* Timer */
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-/* SMC Port Mux */
-#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-
-#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-
-/* CAN */
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-
-/* SPORT */
-#define P_SPORT0_ACLK (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2))
-#define P_SPORT0_AFS (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2))
-#define P_SPORT0_AD0 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2))
-#define P_SPORT0_AD1 (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2))
-#define P_SPORT0_ATDV (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1))
-#define P_SPORT0_BCLK (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2))
-#define P_SPORT0_BFS (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2))
-#define P_SPORT0_BD0 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2))
-#define P_SPORT0_BD1 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2))
-#define P_SPORT0_BTDV (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1))
-
-#define P_SPORT1_ACLK (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2))
-#define P_SPORT1_AFS (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2))
-#define P_SPORT1_AD0 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPORT1_AD1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_SPORT1_ATDV (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_SPORT1_BCLK (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2))
-#define P_SPORT1_BFS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2))
-#define P_SPORT1_BD0 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2))
-#define P_SPORT1_BD1 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2))
-#define P_SPORT1_BTDV (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-
-#define P_SPORT2_ACLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT2_AFS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPORT2_AD0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT2_AD1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT2_ATDV (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1))
-#define P_SPORT2_BCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT2_BFS (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT2_BD0 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPORT2_BD1 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPORT2_BTDV (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-
-/* LINK PORT */
-#define P_LP0_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2))
-#define P_LP0_ACK (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2))
-#define P_LP0_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2))
-#define P_LP0_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2))
-#define P_LP0_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2))
-#define P_LP0_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2))
-#define P_LP0_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2))
-#define P_LP0_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2))
-#define P_LP0_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2))
-#define P_LP0_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2))
-
-#define P_LP1_CLK (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2))
-#define P_LP1_ACK (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2))
-#define P_LP1_D0 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2))
-#define P_LP1_D1 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2))
-#define P_LP1_D2 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2))
-#define P_LP1_D3 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2))
-#define P_LP1_D4 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2))
-#define P_LP1_D5 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2))
-#define P_LP1_D6 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2))
-#define P_LP1_D7 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2))
-
-#define P_LP2_CLK (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2))
-#define P_LP2_ACK (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2))
-#define P_LP2_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_LP2_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_LP2_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_LP2_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_LP2_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_LP2_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_LP2_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_LP2_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-
-#define P_LP3_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2))
-#define P_LP3_ACK (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2))
-#define P_LP3_D0 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_LP3_D1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_LP3_D2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_LP3_D3 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_LP3_D4 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_LP3_D5 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_LP3_D6 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_LP3_D7 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-
-/* TWI */
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_TWI1_SCL (P_DONTCARE)
-#define P_TWI1_SDA (P_DONTCARE)
-
-/* Rotary Encoder */
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf609/ints-priority.c b/arch/blackfin/mach-bf609/ints-priority.c
deleted file mode 100644
index f68abb9..0000000
--- a/arch/blackfin/mach-bf609/ints-priority.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-u8 sec_int_priority[] = {
- 255, /* IRQ_SEC_ERR */
- 255, /* IRQ_CGU_EVT */
- 254, /* IRQ_WATCH0 */
- 254, /* IRQ_WATCH1 */
- 253, /* IRQ_L2CTL0_ECC_ERR */
- 253, /* IRQ_L2CTL0_ECC_WARN */
- 253, /* IRQ_C0_DBL_FAULT */
- 253, /* IRQ_C1_DBL_FAULT */
- 252, /* IRQ_C0_HW_ERR */
- 252, /* IRQ_C1_HW_ERR */
- 255, /* IRQ_C0_NMI_L1_PARITY_ERR */
- 255, /* IRQ_C1_NMI_L1_PARITY_ERR */
-
- 50, /* IRQ_TIMER0 */
- 50, /* IRQ_TIMER1 */
- 50, /* IRQ_TIMER2 */
- 50, /* IRQ_TIMER3 */
- 50, /* IRQ_TIMER4 */
- 50, /* IRQ_TIMER5 */
- 50, /* IRQ_TIMER6 */
- 50, /* IRQ_TIMER7 */
- 50, /* IRQ_TIMER_STAT */
- 0, /* IRQ_PINT0 */
- 0, /* IRQ_PINT1 */
- 0, /* IRQ_PINT2 */
- 0, /* IRQ_PINT3 */
- 0, /* IRQ_PINT4 */
- 0, /* IRQ_PINT5 */
- 0, /* IRQ_CNT */
- 50, /* RQ_PWM0_TRIP */
- 50, /* IRQ_PWM0_SYNC */
- 50, /* IRQ_PWM1_TRIP */
- 50, /* IRQ_PWM1_SYNC */
- 0, /* IRQ_TWI0 */
- 0, /* IRQ_TWI1 */
- 10, /* IRQ_SOFT0 */
- 10, /* IRQ_SOFT1 */
- 10, /* IRQ_SOFT2 */
- 10, /* IRQ_SOFT3 */
- 0, /* IRQ_ACM_EVT_MISS */
- 0, /* IRQ_ACM_EVT_COMPLETE */
- 0, /* IRQ_CAN0_RX */
- 0, /* IRQ_CAN0_TX */
- 0, /* IRQ_CAN0_STAT */
- 100, /* IRQ_SPORT0_TX */
- 100, /* IRQ_SPORT0_TX_STAT */
- 100, /* IRQ_SPORT0_RX */
- 100, /* IRQ_SPORT0_RX_STAT */
- 100, /* IRQ_SPORT1_TX */
- 100, /* IRQ_SPORT1_TX_STAT */
- 100, /* IRQ_SPORT1_RX */
- 100, /* IRQ_SPORT1_RX_STAT */
- 100, /* IRQ_SPORT2_TX */
- 100, /* IRQ_SPORT2_TX_STAT */
- 100, /* IRQ_SPORT2_RX */
- 100, /* IRQ_SPORT2_RX_STAT */
- 0, /* IRQ_SPI0_TX */
- 0, /* IRQ_SPI0_RX */
- 0, /* IRQ_SPI0_STAT */
- 0, /* IRQ_SPI1_TX */
- 0, /* IRQ_SPI1_RX */
- 0, /* IRQ_SPI1_STAT */
- 0, /* IRQ_RSI */
- 0, /* IRQ_RSI_INT0 */
- 0, /* IRQ_RSI_INT1 */
- 0, /* DMA11 Data (SDU) */
- 0, /* DMA12 Data (Reserved) */
- 0, /* Reserved */
- 0, /* Reserved */
- 30, /* IRQ_EMAC0_STAT */
- 0, /* EMAC0 Power (Reserved) */
- 30, /* IRQ_EMAC1_STAT */
- 0, /* EMAC1 Power (Reserved) */
- 0, /* IRQ_LP0 */
- 0, /* IRQ_LP0_STAT */
- 0, /* IRQ_LP1 */
- 0, /* IRQ_LP1_STAT */
- 0, /* IRQ_LP2 */
- 0, /* IRQ_LP2_STAT */
- 0, /* IRQ_LP3 */
- 0, /* IRQ_LP3_STAT */
- 0, /* IRQ_UART0_TX */
- 0, /* IRQ_UART0_RX */
- 0, /* IRQ_UART0_STAT */
- 0, /* IRQ_UART1_TX */
- 0, /* IRQ_UART1_RX */
- 0, /* IRQ_UART1_STAT */
- 0, /* IRQ_MDMA0_SRC_CRC0 */
- 0, /* IRQ_MDMA0_DEST_CRC0 */
- 0, /* IRQ_CRC0_DCNTEXP */
- 0, /* IRQ_CRC0_ERR */
- 0, /* IRQ_MDMA1_SRC_CRC1 */
- 0, /* IRQ_MDMA1_DEST_CRC1 */
- 0, /* IRQ_CRC1_DCNTEXP */
- 0, /* IRQ_CRC1_ERR */
- 0, /* IRQ_MDMA2_SRC */
- 0, /* IRQ_MDMA2_DEST */
- 0, /* IRQ_MDMA3_SRC */
- 0, /* IRQ_MDMA3_DEST */
- 120, /* IRQ_EPPI0_CH0 */
- 120, /* IRQ_EPPI0_CH1 */
- 120, /* IRQ_EPPI0_STAT */
- 120, /* IRQ_EPPI2_CH0 */
- 120, /* IRQ_EPPI2_CH1 */
- 120, /* IRQ_EPPI2_STAT */
- 120, /* IRQ_EPPI1_CH0 */
- 120, /* IRQ_EPPI1_CH1 */
- 120, /* IRQ_EPPI1_STAT */
- 120, /* IRQ_PIXC_CH0 */
- 120, /* IRQ_PIXC_CH1 */
- 120, /* IRQ_PIXC_CH2 */
- 120, /* IRQ_PIXC_STAT */
- 120, /* IRQ_PVP_CPDOB */
- 120, /* IRQ_PVP_CPDOC */
- 120, /* IRQ_PVP_CPSTAT */
- 120, /* IRQ_PVP_CPCI */
- 120, /* IRQ_PVP_STAT0 */
- 120, /* IRQ_PVP_MPDO */
- 120, /* IRQ_PVP_MPDI */
- 120, /* IRQ_PVP_MPSTAT */
- 120, /* IRQ_PVP_MPCI */
- 120, /* IRQ_PVP_CPDOA */
- 120, /* IRQ_PVP_STAT1 */
- 0, /* IRQ_USB_STAT */
- 0, /* IRQ_USB_DMA */
- 0, /* IRQ_TRU_INT0 */
- 0, /* IRQ_TRU_INT1 */
- 0, /* IRQ_TRU_INT2 */
- 0, /* IRQ_TRU_INT3 */
- 0, /* IRQ_DMAC0_ERROR */
- 0, /* IRQ_CGU0_ERROR */
- 0, /* Reserved */
- 0, /* IRQ_DPM */
- 0, /* Reserved */
- 0, /* IRQ_SWU0 */
- 0, /* IRQ_SWU1 */
- 0, /* IRQ_SWU2 */
- 0, /* IRQ_SWU3 */
- 0, /* IRQ_SWU4 */
- 0, /* IRQ_SWU4 */
- 0, /* IRQ_SWU6 */
-};
-
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c
deleted file mode 100644
index b1bfcf4..0000000
--- a/arch/blackfin/mach-bf609/pm.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/suspend.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/dpmc.h>
-#include <asm/pm.h>
-#include <mach/pm.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-
-/***********************************************************/
-/* */
-/* Wakeup Actions for DPM_RESTORE */
-/* */
-/***********************************************************/
-#define BITP_ROM_WUA_CHKHDR 24
-#define BITP_ROM_WUA_DDRLOCK 7
-#define BITP_ROM_WUA_DDRDLLEN 6
-#define BITP_ROM_WUA_DDR 5
-#define BITP_ROM_WUA_CGU 4
-#define BITP_ROM_WUA_MEMBOOT 2
-#define BITP_ROM_WUA_EN 1
-
-#define BITM_ROM_WUA_CHKHDR (0xFF000000)
-#define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000
-
-#define BITM_ROM_WUA_DDRLOCK (0x00000080)
-#define BITM_ROM_WUA_DDRDLLEN (0x00000040)
-#define BITM_ROM_WUA_DDR (0x00000020)
-#define BITM_ROM_WUA_CGU (0x00000010)
-#define BITM_ROM_WUA_MEMBOOT (0x00000002)
-#define BITM_ROM_WUA_EN (0x00000001)
-
-/***********************************************************/
-/* */
-/* Syscontrol */
-/* */
-/***********************************************************/
-#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */
-#define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24
-#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */
-#define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
-#define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
-#define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */
-#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */
-#define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */
-#define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */
-#define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */
-#define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */
-#define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */
-#define BITP_ROM_SYSCTRL_READ 0 /* read registers */
-
-#define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */
-#define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */
-#define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */
-#define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */
-#define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */
-#define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */
-#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */
-#define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */
-#define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */
-#define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
-#define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */
-#define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
-#define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
-#define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
-#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */
-#define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000)
-#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */
-
-
-/* Structures for the syscontrol() function */
-struct STRUCT_ROM_SYSCTRL {
- uint32_t ulCGU_CTL;
- uint32_t ulCGU_STAT;
- uint32_t ulCGU_DIV;
- uint32_t ulCGU_CLKOUTSEL;
- uint32_t ulWUA_Flags;
- uint32_t ulWUA_BootAddr;
- uint32_t ulWUA_User;
- uint32_t ulDDR_CTL;
- uint32_t ulDDR_CFG;
- uint32_t ulDDR_TR0;
- uint32_t ulDDR_TR1;
- uint32_t ulDDR_TR2;
- uint32_t ulDDR_MR;
- uint32_t ulDDR_EMR1;
- uint32_t ulDDR_EMR2;
- uint32_t ulDDR_PADCTL;
- uint32_t ulDDR_DLLCTL;
- uint32_t ulReserved;
-};
-
-struct bfin_pm_data {
- uint32_t magic;
- uint32_t resume_addr;
- uint32_t sp;
-};
-
-struct bfin_pm_data bf609_pm_data;
-
-struct STRUCT_ROM_SYSCTRL configvalues;
-uint32_t dactionflags;
-
-#define FUNC_ROM_SYSCONTROL 0xC8000080
-__attribute__((l1_data))
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;
-
-__attribute__((l1_text))
-void bfin_cpu_suspend(void)
-{
- __asm__ __volatile__( \
- ".align 8;" \
- "idle;" \
- : : \
- );
-}
-
-__attribute__((l1_text))
-void bf609_ddr_sr(void)
-{
- dmc_enter_self_refresh();
-}
-
-__attribute__((l1_text))
-void bf609_ddr_sr_exit(void)
-{
- dmc_exit_self_refresh();
-
- /* After wake up from deep sleep and exit DDR from self refress mode,
- * should wait till CGU PLL is locked.
- */
- while (bfin_read32(CGU0_STAT) & CLKSALGN)
- continue;
-}
-
-__attribute__((l1_text))
-void bf609_resume_ccbuf(void)
-{
- bfin_write32(DPM0_CCBF_EN, 3);
- bfin_write32(DPM0_CTL, 2);
-
- while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
-}
-
-__attribute__((l1_text))
-void bfin_hibernate_syscontrol(void)
-{
- configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
- | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);
-
- dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
- | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
- | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
-
- bfrom_SysControl(dactionflags, &configvalues, NULL);
-
- bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
-}
-
-asmlinkage void enter_deepsleep(void);
-
-__attribute__((l1_text))
-void bfin_deepsleep(unsigned long mask, unsigned long pol_mask)
-{
- bfin_write32(DPM0_WAKE_EN, mask);
- bfin_write32(DPM0_WAKE_POL, pol_mask);
- SSYNC();
- enter_deepsleep();
-}
-
-void bfin_hibernate(unsigned long mask, unsigned long pol_mask)
-{
- bfin_write32(DPM0_WAKE_EN, mask);
- bfin_write32(DPM0_WAKE_POL, pol_mask);
- bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
- bfin_write32(DPM0_HIB_DIS, 0xFFFF);
-
- bf609_hibernate();
-}
-
-void bf609_cpu_pm_enter(suspend_state_t state)
-{
- int error;
- unsigned long wakeup = 0;
- unsigned long wakeup_pol = 0;
-
-#ifdef CONFIG_PM_BFIN_WAKE_PA15
- wakeup |= PA15WE;
-# if CONFIG_PM_BFIN_WAKE_PA15_POL
- wakeup_pol |= PA15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PB15
- wakeup |= PB15WE;
-# if CONFIG_PM_BFIN_WAKE_PB15_POL
- wakeup_pol |= PB15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PC15
- wakeup |= PC15WE;
-# if CONFIG_PM_BFIN_WAKE_PC15_POL
- wakeup_pol |= PC15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PD06
- wakeup |= PD06WE;
-# if CONFIG_PM_BFIN_WAKE_PD06_POL
- wakeup_pol |= PD06WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PE12
- wakeup |= PE12WE;
-# if CONFIG_PM_BFIN_WAKE_PE12_POL
- wakeup_pol |= PE12WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PG04
- wakeup |= PG04WE;
-# if CONFIG_PM_BFIN_WAKE_PG04_POL
- wakeup_pol |= PG04WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PG13
- wakeup |= PG13WE;
-# if CONFIG_PM_BFIN_WAKE_PG13_POL
- wakeup_pol |= PG13WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_USB
- wakeup |= USBWE;
-# if CONFIG_PM_BFIN_WAKE_USB_POL
- wakeup_pol |= USBWE;
-# endif
-#endif
-
- error = irq_set_irq_wake(255, 1);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq wake\n");
- error = irq_set_irq_wake(231, 1);
- if (error < 0)
- printk(KERN_DEBUG "Unable to get irq wake\n");
-
- if (state == PM_SUSPEND_STANDBY)
- bfin_deepsleep(wakeup, wakeup_pol);
- else {
- bfin_hibernate(wakeup, wakeup_pol);
- }
-
-}
-
-int bf609_cpu_pm_prepare(void)
-{
- return 0;
-}
-
-void bf609_cpu_pm_finish(void)
-{
-
-}
-
-static struct bfin_cpu_pm_fns bf609_cpu_pm = {
- .enter = bf609_cpu_pm_enter,
- .prepare = bf609_cpu_pm_prepare,
- .finish = bf609_cpu_pm_finish,
-};
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static int smc_pm_syscore_suspend(void)
-{
- bf609_nor_flash_exit(NULL);
- return 0;
-}
-
-static void smc_pm_syscore_resume(void)
-{
- bf609_nor_flash_init(NULL);
-}
-
-static struct syscore_ops smc_pm_syscore_ops = {
- .suspend = smc_pm_syscore_suspend,
- .resume = smc_pm_syscore_resume,
-};
-#endif
-
-static irqreturn_t test_isr(int irq, void *dev_id)
-{
- printk(KERN_DEBUG "gpio irq %d\n", irq);
- if (irq == 231)
- bfin_sec_raise_irq(BFIN_SYSIRQ(IRQ_SOFT1));
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dpm0_isr(int irq, void *dev_id)
-{
- bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
- bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
- return IRQ_HANDLED;
-}
-
-static int __init bf609_init_pm(void)
-{
- int irq;
- int error;
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
- register_syscore_ops(&smc_pm_syscore_ops);
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PE12
- irq = gpio_to_irq(GPIO_PE12);
- if (irq < 0) {
- error = irq;
- printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
- GPIO_PE12, error);
- }
-
- error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND
- | IRQF_FORCE_RESUME, "gpiope12", NULL);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-#endif
-
- error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, "cgu0 event", NULL);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-
- error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, "dpm0 event", NULL);
- if (error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-
- bfin_cpu_pm = &bf609_cpu_pm;
- return 0;
-}
-
-late_initcall(bf609_init_pm);
diff --git a/arch/blackfin/mach-bf609/scb.c b/arch/blackfin/mach-bf609/scb.c
deleted file mode 100644
index ac1f07c..0000000
--- a/arch/blackfin/mach-bf609/scb.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <asm/scb.h>
-
-struct scb_mi_prio scb_data[] = {
-#ifdef CONFIG_SCB0_MI0
- { REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
- CONFIG_SCB0_MI0_SLOT0,
- CONFIG_SCB0_MI0_SLOT1,
- CONFIG_SCB0_MI0_SLOT2,
- CONFIG_SCB0_MI0_SLOT3,
- CONFIG_SCB0_MI0_SLOT4,
- CONFIG_SCB0_MI0_SLOT5,
- CONFIG_SCB0_MI0_SLOT6,
- CONFIG_SCB0_MI0_SLOT7,
- CONFIG_SCB0_MI0_SLOT8,
- CONFIG_SCB0_MI0_SLOT9,
- CONFIG_SCB0_MI0_SLOT10,
- CONFIG_SCB0_MI0_SLOT11,
- CONFIG_SCB0_MI0_SLOT12,
- CONFIG_SCB0_MI0_SLOT13,
- CONFIG_SCB0_MI0_SLOT14,
- CONFIG_SCB0_MI0_SLOT15,
- CONFIG_SCB0_MI0_SLOT16,
- CONFIG_SCB0_MI0_SLOT17,
- CONFIG_SCB0_MI0_SLOT18,
- CONFIG_SCB0_MI0_SLOT19,
- CONFIG_SCB0_MI0_SLOT20,
- CONFIG_SCB0_MI0_SLOT21,
- CONFIG_SCB0_MI0_SLOT22,
- CONFIG_SCB0_MI0_SLOT23,
- CONFIG_SCB0_MI0_SLOT24,
- CONFIG_SCB0_MI0_SLOT25,
- CONFIG_SCB0_MI0_SLOT26,
- CONFIG_SCB0_MI0_SLOT27,
- CONFIG_SCB0_MI0_SLOT28,
- CONFIG_SCB0_MI0_SLOT29,
- CONFIG_SCB0_MI0_SLOT30,
- CONFIG_SCB0_MI0_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI1
- { REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
- CONFIG_SCB0_MI1_SLOT0,
- CONFIG_SCB0_MI1_SLOT1,
- CONFIG_SCB0_MI1_SLOT2,
- CONFIG_SCB0_MI1_SLOT3,
- CONFIG_SCB0_MI1_SLOT4,
- CONFIG_SCB0_MI1_SLOT5,
- CONFIG_SCB0_MI1_SLOT6,
- CONFIG_SCB0_MI1_SLOT7,
- CONFIG_SCB0_MI1_SLOT8,
- CONFIG_SCB0_MI1_SLOT9,
- CONFIG_SCB0_MI1_SLOT10,
- CONFIG_SCB0_MI1_SLOT11,
- CONFIG_SCB0_MI1_SLOT12,
- CONFIG_SCB0_MI1_SLOT13,
- CONFIG_SCB0_MI1_SLOT14,
- CONFIG_SCB0_MI1_SLOT15,
- CONFIG_SCB0_MI1_SLOT16,
- CONFIG_SCB0_MI1_SLOT17,
- CONFIG_SCB0_MI1_SLOT18,
- CONFIG_SCB0_MI1_SLOT19,
- CONFIG_SCB0_MI1_SLOT20,
- CONFIG_SCB0_MI1_SLOT21,
- CONFIG_SCB0_MI1_SLOT22,
- CONFIG_SCB0_MI1_SLOT23,
- CONFIG_SCB0_MI1_SLOT24,
- CONFIG_SCB0_MI1_SLOT25,
- CONFIG_SCB0_MI1_SLOT26,
- CONFIG_SCB0_MI1_SLOT27,
- CONFIG_SCB0_MI1_SLOT28,
- CONFIG_SCB0_MI1_SLOT29,
- CONFIG_SCB0_MI1_SLOT30,
- CONFIG_SCB0_MI1_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI2
- { REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
- CONFIG_SCB0_MI2_SLOT0,
- CONFIG_SCB0_MI2_SLOT1,
- CONFIG_SCB0_MI2_SLOT2,
- CONFIG_SCB0_MI2_SLOT3,
- CONFIG_SCB0_MI2_SLOT4,
- CONFIG_SCB0_MI2_SLOT5,
- CONFIG_SCB0_MI2_SLOT6,
- CONFIG_SCB0_MI2_SLOT7,
- CONFIG_SCB0_MI2_SLOT8,
- CONFIG_SCB0_MI2_SLOT9,
- CONFIG_SCB0_MI2_SLOT10,
- CONFIG_SCB0_MI2_SLOT11,
- CONFIG_SCB0_MI2_SLOT12,
- CONFIG_SCB0_MI2_SLOT13,
- CONFIG_SCB0_MI2_SLOT14,
- CONFIG_SCB0_MI2_SLOT15,
- CONFIG_SCB0_MI2_SLOT16,
- CONFIG_SCB0_MI2_SLOT17,
- CONFIG_SCB0_MI2_SLOT18,
- CONFIG_SCB0_MI2_SLOT19,
- CONFIG_SCB0_MI2_SLOT20,
- CONFIG_SCB0_MI2_SLOT21,
- CONFIG_SCB0_MI2_SLOT22,
- CONFIG_SCB0_MI2_SLOT23,
- CONFIG_SCB0_MI2_SLOT24,
- CONFIG_SCB0_MI2_SLOT25,
- CONFIG_SCB0_MI2_SLOT26,
- CONFIG_SCB0_MI2_SLOT27,
- CONFIG_SCB0_MI2_SLOT28,
- CONFIG_SCB0_MI2_SLOT29,
- CONFIG_SCB0_MI2_SLOT30,
- CONFIG_SCB0_MI2_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI3
- { REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
- CONFIG_SCB0_MI3_SLOT0,
- CONFIG_SCB0_MI3_SLOT1,
- CONFIG_SCB0_MI3_SLOT2,
- CONFIG_SCB0_MI3_SLOT3,
- CONFIG_SCB0_MI3_SLOT4,
- CONFIG_SCB0_MI3_SLOT5,
- CONFIG_SCB0_MI3_SLOT6,
- CONFIG_SCB0_MI3_SLOT7,
- CONFIG_SCB0_MI3_SLOT8,
- CONFIG_SCB0_MI3_SLOT9,
- CONFIG_SCB0_MI3_SLOT10,
- CONFIG_SCB0_MI3_SLOT11,
- CONFIG_SCB0_MI3_SLOT12,
- CONFIG_SCB0_MI3_SLOT13,
- CONFIG_SCB0_MI3_SLOT14,
- CONFIG_SCB0_MI3_SLOT15,
- CONFIG_SCB0_MI3_SLOT16,
- CONFIG_SCB0_MI3_SLOT17,
- CONFIG_SCB0_MI3_SLOT18,
- CONFIG_SCB0_MI3_SLOT19,
- CONFIG_SCB0_MI3_SLOT20,
- CONFIG_SCB0_MI3_SLOT21,
- CONFIG_SCB0_MI3_SLOT22,
- CONFIG_SCB0_MI3_SLOT23,
- CONFIG_SCB0_MI3_SLOT24,
- CONFIG_SCB0_MI3_SLOT25,
- CONFIG_SCB0_MI3_SLOT26,
- CONFIG_SCB0_MI3_SLOT27,
- CONFIG_SCB0_MI3_SLOT28,
- CONFIG_SCB0_MI3_SLOT29,
- CONFIG_SCB0_MI3_SLOT30,
- CONFIG_SCB0_MI3_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI4
- { REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
- CONFIG_SCB0_MI4_SLOT0,
- CONFIG_SCB0_MI4_SLOT1,
- CONFIG_SCB0_MI4_SLOT2,
- CONFIG_SCB0_MI4_SLOT3,
- CONFIG_SCB0_MI4_SLOT4,
- CONFIG_SCB0_MI4_SLOT5,
- CONFIG_SCB0_MI4_SLOT6,
- CONFIG_SCB0_MI4_SLOT7,
- CONFIG_SCB0_MI4_SLOT8,
- CONFIG_SCB0_MI4_SLOT9,
- CONFIG_SCB0_MI4_SLOT10,
- CONFIG_SCB0_MI4_SLOT11,
- CONFIG_SCB0_MI4_SLOT12,
- CONFIG_SCB0_MI4_SLOT13,
- CONFIG_SCB0_MI4_SLOT14,
- CONFIG_SCB0_MI4_SLOT15,
- CONFIG_SCB0_MI4_SLOT16,
- CONFIG_SCB0_MI4_SLOT17,
- CONFIG_SCB0_MI4_SLOT18,
- CONFIG_SCB0_MI4_SLOT19,
- CONFIG_SCB0_MI4_SLOT20,
- CONFIG_SCB0_MI4_SLOT21,
- CONFIG_SCB0_MI4_SLOT22,
- CONFIG_SCB0_MI4_SLOT23,
- CONFIG_SCB0_MI4_SLOT24,
- CONFIG_SCB0_MI4_SLOT25,
- CONFIG_SCB0_MI4_SLOT26,
- CONFIG_SCB0_MI4_SLOT27,
- CONFIG_SCB0_MI4_SLOT28,
- CONFIG_SCB0_MI4_SLOT29,
- CONFIG_SCB0_MI4_SLOT30,
- CONFIG_SCB0_MI4_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI5
- { REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
- CONFIG_SCB0_MI5_SLOT0,
- CONFIG_SCB0_MI5_SLOT1,
- CONFIG_SCB0_MI5_SLOT2,
- CONFIG_SCB0_MI5_SLOT3,
- CONFIG_SCB0_MI5_SLOT4,
- CONFIG_SCB0_MI5_SLOT5,
- CONFIG_SCB0_MI5_SLOT6,
- CONFIG_SCB0_MI5_SLOT7,
- CONFIG_SCB0_MI5_SLOT8,
- CONFIG_SCB0_MI5_SLOT9,
- CONFIG_SCB0_MI5_SLOT10,
- CONFIG_SCB0_MI5_SLOT11,
- CONFIG_SCB0_MI5_SLOT12,
- CONFIG_SCB0_MI5_SLOT13,
- CONFIG_SCB0_MI5_SLOT14,
- CONFIG_SCB0_MI5_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB1_MI0
- { REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, {
- CONFIG_SCB1_MI0_SLOT0,
- CONFIG_SCB1_MI0_SLOT1,
- CONFIG_SCB1_MI0_SLOT2,
- CONFIG_SCB1_MI0_SLOT3,
- CONFIG_SCB1_MI0_SLOT4,
- CONFIG_SCB1_MI0_SLOT5,
- CONFIG_SCB1_MI0_SLOT6,
- CONFIG_SCB1_MI0_SLOT7,
- CONFIG_SCB1_MI0_SLOT8,
- CONFIG_SCB1_MI0_SLOT9,
- CONFIG_SCB1_MI0_SLOT10,
- CONFIG_SCB1_MI0_SLOT11,
- CONFIG_SCB1_MI0_SLOT12,
- CONFIG_SCB1_MI0_SLOT13,
- CONFIG_SCB1_MI0_SLOT14,
- CONFIG_SCB1_MI0_SLOT15,
- CONFIG_SCB1_MI0_SLOT16,
- CONFIG_SCB1_MI0_SLOT17,
- CONFIG_SCB1_MI0_SLOT18,
- CONFIG_SCB1_MI0_SLOT19
- },
- },
-#endif
-#ifdef CONFIG_SCB2_MI0
- { REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, {
- CONFIG_SCB2_MI0_SLOT0,
- CONFIG_SCB2_MI0_SLOT1,
- CONFIG_SCB2_MI0_SLOT2,
- CONFIG_SCB2_MI0_SLOT3,
- CONFIG_SCB2_MI0_SLOT4,
- CONFIG_SCB2_MI0_SLOT5,
- CONFIG_SCB2_MI0_SLOT6,
- CONFIG_SCB2_MI0_SLOT7,
- CONFIG_SCB2_MI0_SLOT8,
- CONFIG_SCB2_MI0_SLOT9
- },
- },
-#endif
-#ifdef CONFIG_SCB3_MI0
- { REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, {
- CONFIG_SCB3_MI0_SLOT0,
- CONFIG_SCB3_MI0_SLOT1,
- CONFIG_SCB3_MI0_SLOT2,
- CONFIG_SCB3_MI0_SLOT3,
- CONFIG_SCB3_MI0_SLOT4,
- CONFIG_SCB3_MI0_SLOT5,
- CONFIG_SCB3_MI0_SLOT6,
- CONFIG_SCB3_MI0_SLOT7,
- CONFIG_SCB3_MI0_SLOT8,
- CONFIG_SCB3_MI0_SLOT9,
- CONFIG_SCB3_MI0_SLOT10,
- CONFIG_SCB3_MI0_SLOT11,
- CONFIG_SCB3_MI0_SLOT12,
- CONFIG_SCB3_MI0_SLOT13,
- CONFIG_SCB3_MI0_SLOT14,
- CONFIG_SCB3_MI0_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB4_MI0
- { REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, {
- CONFIG_SCB4_MI0_SLOT0,
- CONFIG_SCB4_MI0_SLOT1,
- CONFIG_SCB4_MI0_SLOT2,
- CONFIG_SCB4_MI0_SLOT3,
- CONFIG_SCB4_MI0_SLOT4,
- CONFIG_SCB4_MI0_SLOT5,
- CONFIG_SCB4_MI0_SLOT6,
- CONFIG_SCB4_MI0_SLOT7,
- CONFIG_SCB4_MI0_SLOT8,
- CONFIG_SCB4_MI0_SLOT9,
- CONFIG_SCB4_MI0_SLOT10,
- CONFIG_SCB4_MI0_SLOT11,
- CONFIG_SCB4_MI0_SLOT12,
- CONFIG_SCB4_MI0_SLOT13,
- CONFIG_SCB4_MI0_SLOT14,
- CONFIG_SCB4_MI0_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB5_MI0
- { REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, {
- CONFIG_SCB5_MI0_SLOT0,
- CONFIG_SCB5_MI0_SLOT1,
- CONFIG_SCB5_MI0_SLOT2,
- CONFIG_SCB5_MI0_SLOT3,
- CONFIG_SCB5_MI0_SLOT4,
- CONFIG_SCB5_MI0_SLOT5,
- CONFIG_SCB5_MI0_SLOT6,
- CONFIG_SCB5_MI0_SLOT7
- },
- },
-#endif
-#ifdef CONFIG_SCB6_MI0
- { REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, {
- CONFIG_SCB6_MI0_SLOT0,
- CONFIG_SCB6_MI0_SLOT1,
- CONFIG_SCB6_MI0_SLOT2,
- CONFIG_SCB6_MI0_SLOT3
- },
- },
-#endif
-#ifdef CONFIG_SCB7_MI0
- { REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, {
- CONFIG_SCB7_MI0_SLOT0,
- CONFIG_SCB7_MI0_SLOT1,
- CONFIG_SCB7_MI0_SLOT2,
- CONFIG_SCB7_MI0_SLOT3,
- CONFIG_SCB7_MI0_SLOT4,
- CONFIG_SCB7_MI0_SLOT5
- },
- },
-#endif
-#ifdef CONFIG_SCB8_MI0
- { REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, {
- CONFIG_SCB8_MI0_SLOT0,
- CONFIG_SCB8_MI0_SLOT1,
- CONFIG_SCB8_MI0_SLOT2,
- CONFIG_SCB8_MI0_SLOT3,
- CONFIG_SCB8_MI0_SLOT4,
- CONFIG_SCB8_MI0_SLOT5,
- CONFIG_SCB8_MI0_SLOT6,
- CONFIG_SCB8_MI0_SLOT7
- },
- },
-#endif
-#ifdef CONFIG_SCB9_MI0
- { REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, {
- CONFIG_SCB9_MI0_SLOT0,
- CONFIG_SCB9_MI0_SLOT1,
- CONFIG_SCB9_MI0_SLOT2,
- CONFIG_SCB9_MI0_SLOT3,
- CONFIG_SCB9_MI0_SLOT4,
- CONFIG_SCB9_MI0_SLOT5,
- CONFIG_SCB9_MI0_SLOT6,
- CONFIG_SCB9_MI0_SLOT7,
- CONFIG_SCB9_MI0_SLOT8,
- CONFIG_SCB9_MI0_SLOT9
- },
- },
-#endif
- { 0, }
-};
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
deleted file mode 100644
index fcef1c8..0000000
--- a/arch/blackfin/mach-common/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-common/Makefile
-#
-
-obj-y := \
- cache.o cache-c.o entry.o head.o \
- interrupt.o arch_checks.o ints-priority.o
-
-obj-$(CONFIG_PM) += pm.o
-ifneq ($(CONFIG_BF60x),y)
-obj-$(CONFIG_PM) += dpmc_modes.o
-endif
-obj-$(CONFIG_SCB_PRIORITY) += scb-init.o
-obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
-obj-$(CONFIG_SMP) += smp.o
-obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
deleted file mode 100644
index d8643fd..0000000
--- a/arch/blackfin/mach-common/arch_checks.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Do some checking to make sure things are OK
- *
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/fixed_code.h>
-#include <mach/anomaly.h>
-#include <asm/clocks.h>
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-
-# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
-# error "VCO selected is more than maximum value. Please change the VCO multipler"
-# endif
-
-# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
-# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
-# endif
-
-# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
-# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
-# endif
-
-# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
-# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
-# endif
-
-# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
-# error "Please select sclk less than cclk"
-# endif
-
-#endif /* CONFIG_BFIN_KERNEL_CLOCK */
-
-#if CONFIG_BOOT_LOAD < FIXED_CODE_END
-# error "The kernel load address must be after the fixed code section"
-#endif
-
-#if (CONFIG_BOOT_LOAD & 0x3)
-# error "The kernel load address must be 4 byte aligned"
-#endif
-
-/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */
-#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000
-# error "The kernel load address is too high; keep it below 10meg for safety"
-#endif
-
-#if ANOMALY_05000263 && defined(CONFIG_MPU)
-# error the MPU will not function safely while Anomaly 05000263 applies
-#endif
-
-#if ANOMALY_05000448
-# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
-#endif
-
-/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
-#if ANOMALY_05000220 && \
- (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK))
-# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory"
-#endif
-
-#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1)
-# error You need IFLUSH in L1 inst while Anomaly 05000491 applies
-#endif
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c
deleted file mode 100644
index f4adedc..0000000
--- a/arch/blackfin/mach-common/cache-c.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Blackfin cache control code (simpler control-style functions)
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-
-/* Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-void blackfin_invalidate_entire_dcache(void)
-{
- u32 dmem = bfin_read_DMEM_CONTROL();
- bfin_write_DMEM_CONTROL(dmem & ~0xc);
- SSYNC();
- bfin_write_DMEM_CONTROL(dmem);
- SSYNC();
-}
-
-/* Invalidate the Entire Instruction cache by
- * clearing IMC bit
- */
-void blackfin_invalidate_entire_icache(void)
-{
- u32 imem = bfin_read_IMEM_CONTROL();
- bfin_write_IMEM_CONTROL(imem & ~0x4);
- SSYNC();
- bfin_write_IMEM_CONTROL(imem);
- SSYNC();
-}
-
-#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
-
-static void
-bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
- unsigned long cplb_data, unsigned long mem_control,
- unsigned long mem_mask)
-{
- int i;
-#ifdef CONFIG_L1_PARITY_CHECK
- u32 ctrl;
-
- if (cplb_addr == DCPLB_ADDR0) {
- ctrl = bfin_read32(mem_control) | (1 << RDCHK);
- CSYNC();
- bfin_write32(mem_control, ctrl);
- SSYNC();
- }
-#endif
-
- for (i = 0; i < MAX_CPLBS; i++) {
- bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
- bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
- }
-
- _enable_cplb(mem_control, mem_mask);
-}
-
-#ifdef CONFIG_BFIN_ICACHE
-void bfin_icache_init(struct cplb_entry *icplb_tbl)
-{
- bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
- (IMC | ENICPLB));
-}
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-void bfin_dcache_init(struct cplb_entry *dcplb_tbl)
-{
- /*
- * Anomaly notes:
- * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
- * register, so that the port preferences for DAG0 and DAG1 are set
- * to port B
- */
- bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
- (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
-}
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
deleted file mode 100644
index 9f4dd35..0000000
--- a/arch/blackfin/mach-common/cache.S
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Blackfin cache control code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/cache.h>
-#include <asm/page.h>
-
-/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
-#if ANOMALY_05000443
-# define BROK_FLUSH_INST "IFLUSH"
-#else
-# define BROK_FLUSH_INST "no anomaly! yeah!"
-#endif
-
-/* Since all L1 caches work the same way, we use the same method for flushing
- * them. Only the actual flush instruction differs. We write this in asm as
- * GCC can be hard to coax into writing nice hardware loops.
- *
- * Also, we assume the following register setup:
- * R0 = start address
- * R1 = end address
- */
-.macro do_flush flushins:req label
-
- R2 = -L1_CACHE_BYTES;
-
- /* start = (start & -L1_CACHE_BYTES) */
- R0 = R0 & R2;
-
- /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
- R1 += -1;
- R1 = R1 & R2;
- R1 += L1_CACHE_BYTES;
-
- /* count = (end - start) >> L1_CACHE_SHIFT */
- R2 = R1 - R0;
- R2 >>= L1_CACHE_SHIFT;
- P1 = R2;
-
-.ifnb \label
-\label :
-.endif
- P0 = R0;
-
- LSETUP (1f, 2f) LC1 = P1;
-1:
-.ifeqs "\flushins", BROK_FLUSH_INST
- \flushins [P0++];
- nop;
- nop;
-2: nop;
-.else
-2: \flushins [P0++];
-.endif
-
- RTS;
-.endm
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Invalidate all instruction cache lines assocoiated with this memory area */
-#ifdef CONFIG_SMP
-# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1
-#endif
-ENTRY(_blackfin_icache_flush_range)
- do_flush IFLUSH
-ENDPROC(_blackfin_icache_flush_range)
-
-#ifdef CONFIG_SMP
-.text
-# undef _blackfin_icache_flush_range
-ENTRY(_blackfin_icache_flush_range)
- p0.L = LO(DSPID);
- p0.H = HI(DSPID);
- r3 = [p0];
- r3 = r3.b (z);
- p2 = r3;
- p0.L = _blackfin_iflush_l1_entry;
- p0.H = _blackfin_iflush_l1_entry;
- p0 = p0 + (p2 << 2);
- p1 = [p0];
- jump (p1);
-ENDPROC(_blackfin_icache_flush_range)
-#endif
-
-#ifdef CONFIG_DCACHE_FLUSH_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Throw away all D-cached data in specified region without any obligation to
- * write them back. Since the Blackfin ISA does not have an "invalidate"
- * instruction, we use flush/invalidate. Perhaps as a speed optimization we
- * could bang on the DTEST MMRs ...
- */
-ENTRY(_blackfin_dcache_invalidate_range)
- do_flush FLUSHINV
-ENDPROC(_blackfin_dcache_invalidate_range)
-
-/* Flush all data cache lines assocoiated with this memory area */
-ENTRY(_blackfin_dcache_flush_range)
- do_flush FLUSH, .Ldfr
-ENDPROC(_blackfin_dcache_flush_range)
-
-/* Our headers convert the page structure to an address, so just need to flush
- * its contents like normal. We know the start address is page aligned (which
- * greater than our cache alignment), as is the end address. So just jump into
- * the middle of the dcache flush function.
- */
-ENTRY(_blackfin_dflush_page)
- P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
- jump .Ldfr;
-ENDPROC(_blackfin_dflush_page)
diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h
deleted file mode 100644
index fed851a..0000000
--- a/arch/blackfin/mach-common/clock.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MACH_COMMON_CLKDEV_H
-#define __MACH_COMMON_CLKDEV_H
-
-#include <linux/clk.h>
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk *clk);
- unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk *clk, unsigned long rate);
- int (*enable)(struct clk *clk);
- int (*disable)(struct clk *clk);
-};
-
-struct clk {
- const char *name;
- unsigned long rate;
- spinlock_t lock;
- u32 flags;
- const struct clk_ops *ops;
- const struct params *params;
- void __iomem *reg;
- u32 mask;
- u32 shift;
-};
-
-#endif
-
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
deleted file mode 100644
index d436bd9..0000000
--- a/arch/blackfin/mach-common/clocks-init.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-#include <asm/dma.h>
-#include <asm/clocks.h>
-#include <asm/mem_init.h>
-#include <asm/dpmc.h>
-
-#ifdef CONFIG_BF60x
-
-#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
-#define CGU_DIV_VAL \
- ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \
- (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \
- (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \
- (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \
- (CONFIG_DCLK_DIV << DSEL_OFFSET))
-
-#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
-#if ((CONFIG_BFIN_DCLK != 125) && \
- (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \
- (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \
- (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
-#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
-#endif
-
-#else
-#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
-#define PLL_CTL_VAL \
- (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
- (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
-#endif
-
-__attribute__((l1_text))
-static void do_sync(void)
-{
- __builtin_bfin_ssync();
-}
-
-__attribute__((l1_text))
-void init_clocks(void)
-{
- /* Kill any active DMAs as they may trigger external memory accesses
- * in the middle of reprogramming things, and that'll screw us up.
- * For example, any automatic DMAs left by U-Boot for splash screens.
- */
-#ifdef CONFIG_BF60x
- init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
- init_dmc(CONFIG_BFIN_DCLK);
-#else
- size_t i;
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- struct dma_register *dma = dma_io_base_addr[i];
- dma->cfg = 0;
- }
-
- do_sync();
-
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_ENABLE(0));
-# ifdef SIC_IWR1
- /* BF52x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_ENABLE(0));
-#endif
- do_sync();
-#ifdef EBIU_SDGCTL
- bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
- do_sync();
-#endif
-
-#ifdef CLKBUFOE
- bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
- do_sync();
- __asm__ __volatile__("IDLE;");
-#endif
- bfin_write_PLL_LOCKCNT(0x300);
- do_sync();
- /* We always write PLL_CTL thus avoiding Anomaly 05000242 */
- bfin_write16(PLL_CTL, PLL_CTL_VAL);
- __asm__ __volatile__("IDLE;");
- bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-#ifdef EBIU_SDGCTL
- bfin_write_EBIU_SDRRC(mem_SDRRC);
- bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);
-#else
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
- do_sync();
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
- bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
- bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
- bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
-#ifdef CONFIG_MEM_EBIU_DDRQUE
- bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
-#endif
-#endif
-#endif
- do_sync();
- bfin_read16(0);
-
-}
diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c
deleted file mode 100644
index 724a8c5..0000000
--- a/arch/blackfin/mach-common/dpmc.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/cdev.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/cpufreq.h>
-
-#include <asm/delay.h>
-#include <asm/dpmc.h>
-
-#define DRIVER_NAME "bfin dpmc"
-
-struct bfin_dpmc_platform_data *pdata;
-
-/**
- * bfin_set_vlev - Update VLEV field in VR_CTL Reg.
- * Avoid BYPASS sequence
- */
-static void bfin_set_vlev(unsigned int vlev)
-{
- unsigned pll_lcnt;
-
- pll_lcnt = bfin_read_PLL_LOCKCNT();
-
- bfin_write_PLL_LOCKCNT(1);
- bfin_write_VR_CTL((bfin_read_VR_CTL() & ~VLEV) | vlev);
- bfin_write_PLL_LOCKCNT(pll_lcnt);
-}
-
-/**
- * bfin_get_vlev - Get CPU specific VLEV from platform device data
- */
-static unsigned int bfin_get_vlev(unsigned int freq)
-{
- int i;
-
- if (!pdata)
- goto err_out;
-
- freq >>= 16;
-
- for (i = 0; i < pdata->tabsize; i++)
- if (freq <= (pdata->tuple_tab[i] & 0xFFFF))
- return pdata->tuple_tab[i] >> 16;
-
-err_out:
- printk(KERN_WARNING "DPMC: No suitable CCLK VDDINT voltage pair found\n");
- return VLEV_120;
-}
-
-#ifdef CONFIG_CPU_FREQ
-# ifdef CONFIG_SMP
-static void bfin_idle_this_cpu(void *info)
-{
- unsigned long flags = 0;
- unsigned long iwr0, iwr1, iwr2;
- unsigned int cpu = smp_processor_id();
-
- local_irq_save_hw(flags);
- bfin_iwr_set_sup0(&iwr0, &iwr1, &iwr2);
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_0);
- SSYNC();
- asm("IDLE;");
- bfin_iwr_restore(iwr0, iwr1, iwr2);
-
- local_irq_restore_hw(flags);
-}
-
-static void bfin_idle_cpu(void)
-{
- smp_call_function(bfin_idle_this_cpu, NULL, 0);
-}
-
-static void bfin_wakeup_cpu(void)
-{
- unsigned int cpu;
- unsigned int this_cpu = smp_processor_id();
- cpumask_t mask;
-
- cpumask_copy(&mask, cpu_online_mask);
- cpumask_clear_cpu(this_cpu, &mask);
- for_each_cpu(cpu, &mask)
- platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
-}
-
-# else
-static void bfin_idle_cpu(void) {}
-static void bfin_wakeup_cpu(void) {}
-# endif
-
-static int
-vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
-{
- struct cpufreq_freqs *freq = data;
-
- if (freq->cpu != CPUFREQ_CPU)
- return 0;
-
- if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) {
- bfin_idle_cpu();
- bfin_set_vlev(bfin_get_vlev(freq->new));
- udelay(pdata->vr_settling_time); /* Wait until Volatge settled */
- bfin_wakeup_cpu();
- } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) {
- bfin_idle_cpu();
- bfin_set_vlev(bfin_get_vlev(freq->new));
- bfin_wakeup_cpu();
- }
-
- return 0;
-}
-
-static struct notifier_block vreg_cpufreq_notifier_block = {
- .notifier_call = vreg_cpufreq_notifier
-};
-#endif /* CONFIG_CPU_FREQ */
-
-/**
- * bfin_dpmc_probe -
- *
- */
-static int bfin_dpmc_probe(struct platform_device *pdev)
-{
- if (pdev->dev.platform_data)
- pdata = pdev->dev.platform_data;
- else
- return -EINVAL;
-
- return cpufreq_register_notifier(&vreg_cpufreq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-/**
- * bfin_dpmc_remove -
- */
-static int bfin_dpmc_remove(struct platform_device *pdev)
-{
- pdata = NULL;
- return cpufreq_unregister_notifier(&vreg_cpufreq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-struct platform_driver bfin_dpmc_device_driver = {
- .probe = bfin_dpmc_probe,
- .remove = bfin_dpmc_remove,
- .driver = {
- .name = DRIVER_NAME,
- }
-};
-module_platform_driver(bfin_dpmc_device_driver);
-
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("cpu power management driver for Blackfin");
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
deleted file mode 100644
index de99f3a..0000000
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <mach/irq.h>
-#include <asm/dpmc.h>
-
-.section .l1.text
-ENTRY(_sleep_mode)
- [--SP] = (R7:4, P5:3);
- [--SP] = RETS;
-
- call _set_sic_iwr;
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R1 = W[P0](z);
- BITSET (R1, 3);
- W[P0] = R1.L;
-
- CLI R2;
- SSYNC;
- IDLE;
- STI R2;
-
- call _test_pll_locked;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr;
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R7 = w[p0](z);
- BITCLR (R7, 3);
- BITCLR (R7, 5);
- w[p0] = R7.L;
- IDLE;
-
- bfin_init_pm_bench_cycles;
-
- call _test_pll_locked;
-
- RETS = [SP++];
- (R7:4, P5:3) = [SP++];
- RTS;
-ENDPROC(_sleep_mode)
-
-/*
- * This func never returns as it puts the part into hibernate, and
- * is only called from do_hibernate, so we don't bother saving or
- * restoring any of the normal C runtime state. When we wake up,
- * the entry point will be in do_hibernate and not here.
- *
- * We accept just one argument -- the value to write to VR_CTL.
- */
-
-ENTRY(_hibernate_mode)
- /* Save/setup the regs we need early for minor pipeline optimization */
- R4 = R0;
-
- P3.H = hi(VR_CTL);
- P3.L = lo(VR_CTL);
- /* Disable all wakeup sources */
- R0 = IWR_DISABLE_ALL;
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
- call _set_sic_iwr;
- call _set_dram_srfs;
- SSYNC;
-
- /* Finally, we climb into our cave to hibernate */
- W[P3] = R4.L;
-
- bfin_init_pm_bench_cycles;
-
- CLI R2;
- IDLE;
-.Lforever:
- jump .Lforever;
-ENDPROC(_hibernate_mode)
-
-ENTRY(_sleep_deeper)
- [--SP] = (R7:4, P5:3);
- [--SP] = RETS;
-
- CLI R4;
-
- P3 = R0;
- P4 = R1;
- P5 = R2;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr;
- call _set_dram_srfs; /* Set SDRAM Self Refresh */
-
- P0.H = hi(PLL_DIV);
- P0.L = lo(PLL_DIV);
- R6 = W[P0](z);
- R0.L = 0xF;
- W[P0] = R0.l; /* Set Max VCO to SCLK divider */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R5 = W[P0](z);
- R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
- W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
-
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- P0.H = hi(VR_CTL);
- P0.L = lo(VR_CTL);
- R7 = W[P0](z);
- R1 = 0x6;
- R1 <<= 16;
- R2 = 0x0404(Z);
- R1 = R1|R2;
-
- R2 = DEPOSIT(R7, R1);
- W[P0] = R2; /* Set Min Core Voltage */
-
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- R0 = P3;
- R1 = P4;
- R3 = P5;
- call _set_sic_iwr; /* Set Awake from IDLE */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R0 = W[P0](z);
- BITSET (R0, 3);
- W[P0] = R0.L; /* Turn CCLK OFF */
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr; /* Set Awake from IDLE PLL */
-
- P0.H = hi(VR_CTL);
- P0.L = lo(VR_CTL);
- W[P0]= R7;
-
- SSYNC;
- IDLE;
-
- bfin_init_pm_bench_cycles;
-
- call _test_pll_locked;
-
- P0.H = hi(PLL_DIV);
- P0.L = lo(PLL_DIV);
- W[P0]= R6; /* Restore CCLK and SCLK divider */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- w[p0] = R5; /* Restore VCO multiplier */
- IDLE;
- call _test_pll_locked;
-
- call _unset_dram_srfs; /* SDRAM Self Refresh Off */
-
- STI R4;
-
- RETS = [SP++];
- (R7:4, P5:3) = [SP++];
- RTS;
-ENDPROC(_sleep_deeper)
-
-ENTRY(_set_dram_srfs)
- /* set the dram to self refresh mode */
- SSYNC;
-#if defined(EBIU_RSTCTL) /* DDR */
- P0.H = hi(EBIU_RSTCTL);
- P0.L = lo(EBIU_RSTCTL);
- R2 = [P0];
- BITSET(R2, 3); /* SRREQ enter self-refresh mode */
- [P0] = R2;
- SSYNC;
-1:
- R2 = [P0];
- CC = BITTST(R2, 4);
- if !CC JUMP 1b;
-#else /* SDRAM */
- P0.L = lo(EBIU_SDGCTL);
- P0.H = hi(EBIU_SDGCTL);
- P1.L = lo(EBIU_SDSTAT);
- P1.H = hi(EBIU_SDSTAT);
-
- R2 = [P0];
- BITSET(R2, 24); /* SRFS enter self-refresh mode */
- [P0] = R2;
- SSYNC;
-
-1:
- R2 = w[P1];
- SSYNC;
- cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
- if !cc jump 1b;
-
- R2 = [P0];
- BITCLR(R2, 0); /* SCTLE disable CLKOUT */
- [P0] = R2;
-#endif
- RTS;
-ENDPROC(_set_dram_srfs)
-
-ENTRY(_unset_dram_srfs)
- /* set the dram out of self refresh mode */
-
-#if defined(EBIU_RSTCTL) /* DDR */
- P0.H = hi(EBIU_RSTCTL);
- P0.L = lo(EBIU_RSTCTL);
- R2 = [P0];
- BITCLR(R2, 3); /* clear SRREQ bit */
- [P0] = R2;
-#elif defined(EBIU_SDGCTL) /* SDRAM */
- /* release CLKOUT from self-refresh */
- P0.L = lo(EBIU_SDGCTL);
- P0.H = hi(EBIU_SDGCTL);
-
- R2 = [P0];
- BITSET(R2, 0); /* SCTLE enable CLKOUT */
- [P0] = R2
- SSYNC;
-
- /* release SDRAM from self-refresh */
- R2 = [P0];
- BITCLR(R2, 24); /* clear SRFS bit */
- [P0] = R2
-#endif
-
- SSYNC;
- RTS;
-ENDPROC(_unset_dram_srfs)
-
-ENTRY(_set_sic_iwr)
-#ifdef SIC_IWR0
- P0.H = hi(SYSMMR_BASE);
- P0.L = lo(SYSMMR_BASE);
- [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
- [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
-# ifdef SIC_IWR2
- [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
-# endif
-#else
- P0.H = hi(SIC_IWR);
- P0.L = lo(SIC_IWR);
- [P0] = R0;
-#endif
-
- SSYNC;
- RTS;
-ENDPROC(_set_sic_iwr)
-
-ENTRY(_test_pll_locked)
- P0.H = hi(PLL_STAT);
- P0.L = lo(PLL_STAT);
-1:
- R0 = W[P0] (Z);
- CC = BITTST(R0,5);
- IF !CC JUMP 1b;
- RTS;
-ENDPROC(_test_pll_locked)
-
-.section .text
-ENTRY(_do_hibernate)
- bfin_cpu_reg_save;
- bfin_sys_mmr_save;
- bfin_core_mmr_save;
-
- /* Setup args to hibernate mode early for pipeline optimization */
- R0 = M3;
- P1.H = _hibernate_mode;
- P1.L = _hibernate_mode;
-
- /* Save Magic, return address and Stack Pointer */
- P0 = 0;
- R1.H = 0xDEAD; /* Hibernate Magic */
- R1.L = 0xBEEF;
- R2.H = .Lpm_resume_here;
- R2.L = .Lpm_resume_here;
- [P0++] = R1; /* Store Hibernate Magic */
- [P0++] = R2; /* Save Return Address */
- [P0++] = SP; /* Save Stack Pointer */
-
- /* Must use an indirect call as we need to jump to L1 */
- call (P1); /* Goodbye */
-
-.Lpm_resume_here:
-
- bfin_core_mmr_restore;
- bfin_sys_mmr_restore;
- bfin_cpu_reg_restore;
-
- [--sp] = RETI; /* Clear Global Interrupt Disable */
- SP += 4;
-
- RTS;
-ENDPROC(_do_hibernate)
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
deleted file mode 100644
index 8d9431e..0000000
--- a/arch/blackfin/mach-common/entry.S
+++ /dev/null
@@ -1,1711 +0,0 @@
-/*
- * Contains the system-call and fault low-level handling routines.
- * This also contains the timer-interrupt handler, as well as all
- * interrupts and faults that can result in a task-switch.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- */
-
-#include <linux/init.h>
-#include <linux/linkage.h>
-#include <linux/unistd.h>
-#include <asm/blackfin.h>
-#include <asm/errno.h>
-#include <asm/fixed_code.h>
-#include <asm/thread_info.h> /* TIF_NEED_RESCHED */
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-#include <asm/traps.h>
-
-#include <asm/context.S>
-
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Slightly simplified and streamlined entry point for CPLB misses.
- * This one does not lower the level to IRQ5, and thus can be used to
- * patch up CPLB misses on the kernel stack.
- */
-#if ANOMALY_05000261
-#define _ex_dviol _ex_workaround_261
-#define _ex_dmiss _ex_workaround_261
-#define _ex_dmult _ex_workaround_261
-
-ENTRY(_ex_workaround_261)
- /*
- * Work around an anomaly: if we see a new DCPLB fault, return
- * without doing anything. Then, if we get the same fault again,
- * handle it.
- */
- P4 = R7; /* Store EXCAUSE */
-
- GET_PDA(p5, r7);
- r7 = [p5 + PDA_LFRETX];
- r6 = retx;
- [p5 + PDA_LFRETX] = r6;
- cc = r6 == r7;
- if !cc jump _bfin_return_from_exception;
- /* fall through */
- R7 = P4;
- R6 = VEC_CPLB_M; /* Data CPLB Miss */
- cc = R6 == R7;
- if cc jump _ex_dcplb_miss (BP);
-#ifdef CONFIG_MPU
- R6 = VEC_CPLB_VL; /* Data CPLB Violation */
- cc = R6 == R7;
- if cc jump _ex_dcplb_viol (BP);
-#endif
- /* Handle Data CPLB Protection Violation
- * and Data CPLB Multiple Hits - Linux Trap Zero
- */
- jump _ex_trap_c;
-ENDPROC(_ex_workaround_261)
-
-#else
-#ifdef CONFIG_MPU
-#define _ex_dviol _ex_dcplb_viol
-#else
-#define _ex_dviol _ex_trap_c
-#endif
-#define _ex_dmiss _ex_dcplb_miss
-#define _ex_dmult _ex_trap_c
-#endif
-
-
-ENTRY(_ex_dcplb_viol)
-ENTRY(_ex_dcplb_miss)
-ENTRY(_ex_icplb_miss)
- (R7:6,P5:4) = [sp++];
- /* We leave the previously pushed ASTAT on the stack. */
- SAVE_CONTEXT_CPLB
-
- /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that
- * will change the stack pointer. */
- R0 = SEQSTAT;
- R1 = SP;
-
- DEBUG_HWTRACE_SAVE(p5, r7)
-
- sp += -12;
- call _cplb_hdr;
- sp += 12;
- CC = R0 == 0;
- IF !CC JUMP _handle_bad_cplb;
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* While we were processing this, did we double fault? */
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- r6 = 0x25;
- CC = R7 == R6;
- if CC JUMP _double_fault;
-#endif
-
- DEBUG_HWTRACE_RESTORE(p5, r7)
- RESTORE_CONTEXT_CPLB
- ASTAT = [SP++];
- SP = EX_SCRATCH_REG;
- rtx;
-ENDPROC(_ex_icplb_miss)
-
-ENTRY(_ex_syscall)
- raise 15; /* invoked by TRAP #0, for sys call */
- jump.s _bfin_return_from_exception;
-ENDPROC(_ex_syscall)
-
-ENTRY(_ex_single_step)
- /* If we just returned from an interrupt, the single step event is
- for the RTI instruction. */
- r7 = retx;
- r6 = reti;
- cc = r7 == r6;
- if cc jump _bfin_return_from_exception;
-
-#ifdef CONFIG_KGDB
- /* Don't do single step in hardware exception handler */
- p5.l = lo(IPEND);
- p5.h = hi(IPEND);
- r6 = [p5];
- cc = bittst(r6, 4);
- if cc jump _bfin_return_from_exception;
- cc = bittst(r6, 5);
- if cc jump _bfin_return_from_exception;
-
- /* skip single step if current interrupt priority is higher than
- * that of the first instruction, from which gdb starts single step */
- r6 >>= 6;
- r7 = 10;
-.Lfind_priority_start:
- cc = bittst(r6, 0);
- if cc jump .Lfind_priority_done;
- r6 >>= 1;
- r7 += -1;
- cc = r7 == 0;
- if cc jump .Lfind_priority_done;
- jump.s .Lfind_priority_start;
-.Lfind_priority_done:
- p4.l = _kgdb_single_step;
- p4.h = _kgdb_single_step;
- r6 = [p4];
- cc = r6 == 0;
- if cc jump .Ldo_single_step;
- r6 += -1;
- cc = r6 < r7;
- if cc jump 1f;
-.Ldo_single_step:
-#else
- /* If we were in user mode, do the single step normally. */
- p5.l = lo(IPEND);
- p5.h = hi(IPEND);
- r6 = [p5];
- r7 = 0xffe0 (z);
- r7 = r7 & r6;
- cc = r7 == 0;
- if !cc jump 1f;
-#endif
-#ifdef CONFIG_EXACT_HWERR
- /* Read the ILAT, and to check to see if the process we are
- * single stepping caused a previous hardware error
- * If so, do not single step, (which lowers to IRQ5, and makes
- * us miss the error).
- */
- p5.l = lo(ILAT);
- p5.h = hi(ILAT);
- r7 = [p5];
- cc = bittst(r7, EVT_IVHW_P);
- if cc jump 1f;
-#endif
- /* Single stepping only a single instruction, so clear the trace
- * bit here. */
- r7 = syscfg;
- bitclr (r7, SYSCFG_SSSTEP_P);
- syscfg = R7;
- jump _ex_trap_c;
-
-1:
- /*
- * We were in an interrupt handler. By convention, all of them save
- * SYSCFG with their first instruction, so by checking whether our
- * RETX points@the entry point, we can determine whether to allow
- * a single step, or whether to clear SYSCFG.
- *
- * First, find out the interrupt level and the event vector for it.
- */
- p5.l = lo(EVT0);
- p5.h = hi(EVT0);
- p5 += -4;
-2:
- r7 = rot r7 by -1;
- p5 += 4;
- if !cc jump 2b;
-
- /* What we actually do is test for the _second_ instruction in the
- * IRQ handler. That way, if there are insns following the restore
- * of SYSCFG after leaving the handler, we will not turn off SYSCFG
- * for them. */
-
- r7 = [p5];
- r7 += 2;
- r6 = RETX;
- cc = R7 == R6;
- if !cc jump _bfin_return_from_exception;
-
- r7 = syscfg;
- bitclr (r7, SYSCFG_SSSTEP_P); /* Turn off single step */
- syscfg = R7;
-
- /* Fall through to _bfin_return_from_exception. */
-ENDPROC(_ex_single_step)
-
-ENTRY(_bfin_return_from_exception)
-#if ANOMALY_05000257
- R7=LC0;
- LC0=R7;
- R7=LC1;
- LC1=R7;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* While we were processing the current exception,
- * did we cause another, and double fault?
- */
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- r6 = VEC_UNCOV;
- CC = R7 == R6;
- if CC JUMP _double_fault;
-#endif
-
- (R7:6,P5:4) = [sp++];
- ASTAT = [sp++];
- sp = EX_SCRATCH_REG;
- rtx;
-ENDPROC(_bfin_return_from_exception)
-
-ENTRY(_handle_bad_cplb)
- DEBUG_HWTRACE_RESTORE(p5, r7)
- /* To get here, we just tried and failed to change a CPLB
- * so, handle things in trap_c (C code), by lowering to
- * IRQ5, just like we normally do. Since this is not a
- * "normal" return path, we have a do a lot of stuff to
- * the stack to get ready so, we can fall through - we
- * need to make a CPLB exception look like a normal exception
- */
- RESTORE_CONTEXT_CPLB
- /* ASTAT is still on the stack, where it is needed. */
- [--sp] = (R7:6,P5:4);
-
-ENTRY(_ex_replaceable)
- nop;
-
-ENTRY(_ex_trap_c)
- /* The only thing that has been saved in this context is
- * (R7:6,P5:4), ASTAT & SP - don't use anything else
- */
-
- GET_PDA(p5, r6);
-
- /* Make sure we are not in a double fault */
- p4.l = lo(IPEND);
- p4.h = hi(IPEND);
- r7 = [p4];
- CC = BITTST (r7, 5);
- if CC jump _double_fault;
- [p5 + PDA_EXIPEND] = r7;
-
- /* Call C code (trap_c) to handle the exception, which most
- * likely involves sending a signal to the current process.
- * To avoid double faults, lower our priority to IRQ5 first.
- */
- r7.h = _exception_to_level5;
- r7.l = _exception_to_level5;
- p4.l = lo(EVT5);
- p4.h = hi(EVT5);
- [p4] = r7;
- csync;
-
- /*
- * Save these registers, as they are only valid in exception context
- * (where we are now - as soon as we defer to IRQ5, they can change)
- * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
- * but they are not very interesting, so don't save them
- */
-
- p4.l = lo(DCPLB_FAULT_ADDR);
- p4.h = hi(DCPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DCPLB] = r7;
-
- p4.l = lo(ICPLB_FAULT_ADDR);
- p4.h = hi(ICPLB_FAULT_ADDR);
- r6 = [p4];
- [p5 + PDA_ICPLB] = r6;
-
- r6 = retx;
- [p5 + PDA_RETX] = r6;
-
- r6 = SEQSTAT;
- [p5 + PDA_SEQSTAT] = r6;
-
- /* Save the state of single stepping */
- r6 = SYSCFG;
- [p5 + PDA_SYSCFG] = r6;
- /* Clear it while we handle the exception in IRQ5 mode */
- BITCLR(r6, SYSCFG_SSSTEP_P);
- SYSCFG = r6;
-
- /* Save the current IMASK, since we change in order to jump to level 5 */
- cli r6;
- [p5 + PDA_EXIMASK] = r6;
-
- p4.l = lo(SAFE_USER_INSTRUCTION);
- p4.h = hi(SAFE_USER_INSTRUCTION);
- retx = p4;
-
- /* Disable all interrupts, but make sure level 5 is enabled so
- * we can switch to that level.
- */
- r6 = 0x3f;
- sti r6;
-
- /* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
- * clear it (re-enabling interrupts again) by the special sequence of pushing
- * RETI onto the stack. This way we can lower ourselves to IVG5 even if the
- * exception was taken after the interrupt handler was called but before it
- * got a chance to enable global interrupts itself.
- */
- [--sp] = reti;
- sp += 4;
-
- raise 5;
- jump.s _bfin_return_from_exception;
-ENDPROC(_ex_trap_c)
-
-/* We just realized we got an exception, while we were processing a different
- * exception. This is a unrecoverable event, so crash.
- * Note: this cannot be ENTRY() as we jump here with "if cc jump" ...
- */
-ENTRY(_double_fault)
- /* Turn caches & protection off, to ensure we don't get any more
- * double exceptions
- */
-
- P4.L = LO(IMEM_CONTROL);
- P4.H = HI(IMEM_CONTROL);
-
- R5 = [P4]; /* Control Register*/
- BITCLR(R5,ENICPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- P4.L = LO(DMEM_CONTROL);
- P4.H = HI(DMEM_CONTROL);
- R5 = [P4];
- BITCLR(R5,ENDCPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- /* Fix up the stack */
- (R7:6,P5:4) = [sp++];
- ASTAT = [sp++];
- SP = EX_SCRATCH_REG;
-
- /* We should be out of the exception stack, and back down into
- * kernel or user space stack
- */
- SAVE_ALL_SYS
-
- /* The dumping functions expect the return address in the RETI
- * slot. */
- r6 = retx;
- [sp + PT_PC] = r6;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _double_fault_c, p5;
- SP += 12;
-.L_double_fault_panic:
- JUMP .L_double_fault_panic
-
-ENDPROC(_double_fault)
-
-ENTRY(_exception_to_level5)
- SAVE_ALL_SYS
-
- GET_PDA(p5, r7); /* Fetch current PDA */
- r6 = [p5 + PDA_RETX];
- [sp + PT_PC] = r6;
-
- r6 = [p5 + PDA_SYSCFG];
- [sp + PT_SYSCFG] = r6;
-
- r6 = [p5 + PDA_SEQSTAT]; /* Read back seqstat */
- [sp + PT_SEQSTAT] = r6;
-
- /* Restore the hardware error vector. */
- r7.h = _evt_ivhw;
- r7.l = _evt_ivhw;
- p4.l = lo(EVT5);
- p4.h = hi(EVT5);
- [p4] = r7;
- csync;
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Now that we have the hardware error vector programmed properly
- * we can re-enable interrupts (IPEND[4]), so if the _trap_c causes
- * another hardware error, we can catch it (self-nesting).
- */
- [--sp] = reti;
- sp += 4;
-#endif
-
- r7 = [p5 + PDA_EXIPEND] /* Read the IPEND from the Exception state */
- [sp + PT_IPEND] = r7; /* Store IPEND onto the stack */
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _trap_c, p4;
- SP += 12;
-
- /* If interrupts were off during the exception (IPEND[4] = 1), turn them off
- * before we return.
- */
- CC = BITTST(r7, EVT_IRPTEN_P)
- if !CC jump 1f;
- /* this will load a random value into the reti register - but that is OK,
- * since we do restore it to the correct value in the 'RESTORE_ALL_SYS' macro
- */
- sp += -4;
- reti = [sp++];
-1:
- /* restore the interrupt mask (IMASK) */
- r6 = [p5 + PDA_EXIMASK];
- sti r6;
-
- call _ret_from_exception;
- RESTORE_ALL_SYS
- rti;
-ENDPROC(_exception_to_level5)
-
-ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
- /* Since the kernel stack can be anywhere, it's not guaranteed to be
- * covered by a CPLB. Switch to an exception stack; use RETN as a
- * scratch register (for want of a better option).
- */
- EX_SCRATCH_REG = sp;
- GET_PDA_SAFE(sp);
- sp = [sp + PDA_EXSTACK];
- /* Try to deal with syscalls quickly. */
- [--sp] = ASTAT;
- [--sp] = (R7:6,P5:4);
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
-#ifdef CONFIG_EXACT_HWERR
- /* Make sure all pending read/writes complete. This will ensure any
- * accesses which could cause hardware errors completes, and signal
- * the the hardware before we do something silly, like crash the
- * kernel. We don't need to work around anomaly 05000312, since
- * we are already atomic
- */
- ssync;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /*
- * Save these registers, as they are only valid in exception context
- * (where we are now - as soon as we defer to IRQ5, they can change)
- * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
- * but they are not very interesting, so don't save them
- */
-
- GET_PDA(p5, r7);
- p4.l = lo(DCPLB_FAULT_ADDR);
- p4.h = hi(DCPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DF_DCPLB] = r7;
-
- p4.l = lo(ICPLB_FAULT_ADDR);
- p4.h = hi(ICPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DF_ICPLB] = r7;
-
- r7 = retx;
- [p5 + PDA_DF_RETX] = r7;
-
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- [p5 + PDA_DF_SEQSTAT] = r7;
-#else
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
-#endif
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- p5.h = _ex_table;
- p5.l = _ex_table;
- p4 = r7;
- p5 = p5 + (p4 << 2);
- p4 = [p5];
- jump (p4);
-
-.Lbadsys:
- r7 = -ENOSYS; /* signextending enough */
- [sp + PT_R0] = r7; /* return value from system call */
- jump .Lsyscall_really_exit;
-ENDPROC(_trap)
-
-ENTRY(_system_call)
- /* Store IPEND */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- csync;
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
- /* Store RETS for now */
- r0 = rets;
- [sp + PT_RESERVED] = r0;
- /* Set the stack for the current process */
- r7 = sp;
- r6.l = lo(ALIGN_PAGE_MASK);
- r6.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r6; /* thread_info */
- p2 = r7;
- p2 = [p2];
-
- [p2+(TASK_THREAD+THREAD_KSP)] = sp;
-#ifdef CONFIG_IPIPE
- r0 = sp;
- SP += -12;
- pseudo_long_call ___ipipe_syscall_root, p0;
- SP += 12;
- cc = r0 == 1;
- if cc jump .Lsyscall_really_exit;
- cc = r0 == -1;
- if cc jump .Lresume_userspace;
- r3 = [sp + PT_R3];
- r4 = [sp + PT_R4];
- p0 = [sp + PT_ORIG_P0];
-#endif /* CONFIG_IPIPE */
-
- /* are we tracing syscalls?*/
- r7 = sp;
- r6.l = lo(ALIGN_PAGE_MASK);
- r6.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r6;
- p2 = r7;
- r7 = [p2+TI_FLAGS];
- CC = BITTST(r7,TIF_SYSCALL_TRACE);
- if CC JUMP _sys_trace;
- CC = BITTST(r7,TIF_SINGLESTEP);
- if CC JUMP _sys_trace;
-
- /* Make sure the system call # is valid */
- p4 = __NR_syscall;
- /* System call number is passed in P0 */
- cc = p4 <= p0;
- if cc jump .Lbadsys;
-
- /* Execute the appropriate system call */
-
- p4 = p0;
- p5.l = _sys_call_table;
- p5.h = _sys_call_table;
- p5 = p5 + (p4 << 2);
- r0 = [sp + PT_R0];
- r1 = [sp + PT_R1];
- r2 = [sp + PT_R2];
- p5 = [p5];
-
- [--sp] = r5;
- [--sp] = r4;
- [--sp] = r3;
- SP += -12;
- call (p5);
- SP += 24;
- [sp + PT_R0] = r0;
-
-.Lresume_userspace:
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4; /* thread_info->flags */
- p5 = r7;
-.Lresume_userspace_1:
- /* Disable interrupts. */
- [--sp] = reti;
- reti = [sp++];
-
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
-
-.Lsyscall_resched:
-#ifdef CONFIG_IPIPE
- cc = BITTST(r7, TIF_IRQ_SYNC);
- if !cc jump .Lsyscall_no_irqsync;
- /*
- * Clear IPEND[4] manually to undo what resume_userspace_1 just did;
- * we need this so that high priority domain interrupts may still
- * preempt the current domain while the pipeline log is being played
- * back.
- */
- [--sp] = reti;
- SP += 4; /* don't merge with next insn to keep the pattern obvious */
- SP += -12;
- pseudo_long_call ___ipipe_sync_root, p4;
- SP += 12;
- jump .Lresume_userspace_1;
-.Lsyscall_no_irqsync:
-#endif
- cc = BITTST(r7, TIF_NEED_RESCHED);
- if !cc jump .Lsyscall_sigpending;
-
- /* Reenable interrupts. */
- [--sp] = reti;
- sp += 4;
-
- SP += -12;
- pseudo_long_call _schedule, p4;
- SP += 12;
-
- jump .Lresume_userspace_1;
-
-.Lsyscall_sigpending:
- cc = BITTST(r7, TIF_SIGPENDING);
- if cc jump .Lsyscall_do_signals;
- cc = BITTST(r7, TIF_NOTIFY_RESUME);
- if !cc jump .Lsyscall_really_exit;
-.Lsyscall_do_signals:
- /* Reenable interrupts. */
- [--sp] = reti;
- sp += 4;
-
- r0 = sp;
- SP += -12;
- pseudo_long_call _do_notify_resume, p5;
- SP += 12;
-
-.Lsyscall_really_exit:
- r5 = [sp + PT_RESERVED];
- rets = r5;
- rts;
-ENDPROC(_system_call)
-
-/* Do not mark as ENTRY() to avoid error in assembler ...
- * this symbol need not be global anyways, so ...
- */
-_sys_trace:
- r0 = sp;
- pseudo_long_call _syscall_trace_enter, p5;
-
- /* Make sure the system call # is valid */
- p4 = [SP + PT_P0];
- p3 = __NR_syscall;
- cc = p3 <= p4;
- r0 = -ENOSYS;
- if cc jump .Lsys_trace_badsys;
-
- /* Execute the appropriate system call */
- p5.l = _sys_call_table;
- p5.h = _sys_call_table;
- p5 = p5 + (p4 << 2);
- r0 = [sp + PT_R0];
- r1 = [sp + PT_R1];
- r2 = [sp + PT_R2];
- r3 = [sp + PT_R3];
- r4 = [sp + PT_R4];
- r5 = [sp + PT_R5];
- p5 = [p5];
-
- [--sp] = r5;
- [--sp] = r4;
- [--sp] = r3;
- SP += -12;
- call (p5);
- SP += 24;
-.Lsys_trace_badsys:
- [sp + PT_R0] = r0;
-
- r0 = sp;
- pseudo_long_call _syscall_trace_leave, p5;
- jump .Lresume_userspace;
-ENDPROC(_sys_trace)
-
-ENTRY(_resume)
- /*
- * Beware - when entering resume, prev (the current task) is
- * in r0, next (the new task) is in r1.
- */
- p0 = r0;
- p1 = r1;
- [--sp] = rets;
- [--sp] = fp;
- [--sp] = (r7:4, p5:3);
-
- /* save usp */
- p2 = usp;
- [p0+(TASK_THREAD+THREAD_USP)] = p2;
-
- /* save current kernel stack pointer */
- [p0+(TASK_THREAD+THREAD_KSP)] = sp;
-
- /* save program counter */
- r1.l = _new_old_task;
- r1.h = _new_old_task;
- [p0+(TASK_THREAD+THREAD_PC)] = r1;
-
- /* restore the kernel stack pointer */
- sp = [p1+(TASK_THREAD+THREAD_KSP)];
-
- /* restore user stack pointer */
- p0 = [p1+(TASK_THREAD+THREAD_USP)];
- usp = p0;
-
- /* restore pc */
- p0 = [p1+(TASK_THREAD+THREAD_PC)];
- jump (p0);
-
- /*
- * Following code actually lands up in a new (old) task.
- */
-
-_new_old_task:
- (r7:4, p5:3) = [sp++];
- fp = [sp++];
- rets = [sp++];
-
- /*
- * When we come out of resume, r0 carries "old" task, because we are
- * in "new" task.
- */
- rts;
-ENDPROC(_resume)
-
-ENTRY(_ret_from_exception)
-#ifdef CONFIG_IPIPE
- p2.l = _ipipe_percpu_domain;
- p2.h = _ipipe_percpu_domain;
- r0.l = _ipipe_root;
- r0.h = _ipipe_root;
- r2 = [p2];
- cc = r0 == r2;
- if !cc jump 4f; /* not on behalf of the root domain, get out */
-#endif /* CONFIG_IPIPE */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
-
- csync;
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
-1:
- r2 = LO(~0x37) (Z);
- r0 = r2 & r0;
- cc = r0 == 0;
- if !cc jump 4f; /* if not return to user mode, get out */
-
- /* Make sure any pending system call or deferred exception
- * return in ILAT for this process to get executed, otherwise
- * in case context switch happens, system call of
- * first process (i.e in ILAT) will be carried
- * forward to the switched process
- */
-
- p2.l = lo(ILAT);
- p2.h = hi(ILAT);
- r0 = [p2];
- r1 = (EVT_IVG14 | EVT_IVG15) (z);
- r0 = r0 & r1;
- cc = r0 == 0;
- if !cc jump 5f;
-
- /* Set the stack for the current process */
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4; /* thread_info->flags */
- p5 = r7;
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
- cc = r7 == 0;
- if cc jump 4f;
-
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _schedule_and_signal;
- p1.h = _schedule_and_signal;
- [p0] = p1;
- csync;
- raise 15; /* raise evt15 to do signal or reschedule */
-4:
- r0 = syscfg;
- bitclr(r0, SYSCFG_SSSTEP_P); /* Turn off single step */
- syscfg = r0;
-5:
- rts;
-ENDPROC(_ret_from_exception)
-
-#if defined(CONFIG_PREEMPT)
-
-ENTRY(_up_to_irq14)
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
-
- p0.l = lo(EVT14);
- p0.h = hi(EVT14);
- p1.l = _evt_up_evt14;
- p1.h = _evt_up_evt14;
- [p0] = p1;
- csync;
-
- raise 14;
-1:
- jump 1b;
-ENDPROC(_up_to_irq14)
-
-ENTRY(_evt_up_evt14)
-#ifdef CONFIG_DEBUG_HWERR
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = rets;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- rets = [sp++];
-#endif
- [--sp] = RETI;
- SP += 4;
-
- /* restore normal evt14 */
- p0.l = lo(EVT14);
- p0.h = hi(EVT14);
- p1.l = _evt_evt14;
- p1.h = _evt_evt14;
- [p0] = p1;
- csync;
-
- rts;
-ENDPROC(_evt_up_evt14)
-
-#endif
-
-#ifdef CONFIG_IPIPE
-
-_resume_kernel_from_int:
- r1 = LO(~0x8000) (Z);
- r1 = r0 & r1;
- r0 = 1;
- r0 = r1 - r0;
- r2 = r1 & r0;
- cc = r2 == 0;
- /* Sync the root stage only from the outer interrupt level. */
- if !cc jump .Lnosync;
- r0.l = ___ipipe_sync_root;
- r0.h = ___ipipe_sync_root;
- [--sp] = reti;
- [--sp] = rets;
- [--sp] = ( r7:4, p5:3 );
- SP += -12;
- call ___ipipe_call_irqtail
- SP += 12;
- ( r7:4, p5:3 ) = [sp++];
- rets = [sp++];
- reti = [sp++];
-.Lnosync:
- rts
-#elif defined(CONFIG_PREEMPT)
-
-_resume_kernel_from_int:
- /* check preempt_count */
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4;
- p5 = r7;
- r7 = [p5 + TI_PREEMPT];
- cc = r7 == 0x0;
- if !cc jump .Lreturn_to_kernel;
-.Lneed_schedule:
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
- cc = BITTST(r7, TIF_NEED_RESCHED);
- if !cc jump .Lreturn_to_kernel;
- /*
- * let schedule done at level 15, otherwise sheduled process will run
- * at high level and block low level interrupt
- */
- r6 = reti; /* save reti */
- r5.l = .Lkernel_schedule;
- r5.h = .Lkernel_schedule;
- reti = r5;
- rti;
-.Lkernel_schedule:
- [--sp] = rets;
- sp += -12;
- pseudo_long_call _preempt_schedule_irq, p4;
- sp += 12;
- rets = [sp++];
-
- [--sp] = rets;
- sp += -12;
- /* up to irq14 so that reti after restore_all can return to irq15(kernel) */
- pseudo_long_call _up_to_irq14, p4;
- sp += 12;
- rets = [sp++];
-
- reti = r6; /* restore reti so that origin process can return to interrupted point */
-
- jump .Lneed_schedule;
-#else
-
-#define _resume_kernel_from_int .Lreturn_to_kernel
-#endif
-
-ENTRY(_return_from_int)
- /* If someone else already raised IRQ 15, do nothing. */
- csync;
- p2.l = lo(ILAT);
- p2.h = hi(ILAT);
- r0 = [p2];
- cc = bittst (r0, EVT_IVG15_P);
- if cc jump .Lreturn_to_kernel;
-
- /* if not return to user mode, get out */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- r0 = [p2];
- r1 = 0x17(Z);
- r2 = ~r1;
- r2.h = 0;
- r0 = r2 & r0;
- r1 = 1;
- r1 = r0 - r1;
- r2 = r0 & r1;
- cc = r2 == 0;
- if !cc jump _resume_kernel_from_int;
-
- /* Lower the interrupt level to 15. */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _schedule_and_signal_from_int;
- p1.h = _schedule_and_signal_from_int;
- [p0] = p1;
- csync;
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
- r0 = 0x801f (z);
- STI r0;
- raise 15; /* raise evt15 to do signal or reschedule */
- rti;
-.Lreturn_to_kernel:
- rts;
-ENDPROC(_return_from_int)
-
-ENTRY(_lower_to_irq14)
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
- raise 14;
- rti;
-ENDPROC(_lower_to_irq14)
-
-ENTRY(_evt_evt14)
-#ifdef CONFIG_DEBUG_HWERR
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = rets;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- rets = [sp++];
-#endif
- [--sp] = RETI;
- SP += 4;
- rts;
-ENDPROC(_evt_evt14)
-
-ENTRY(_schedule_and_signal_from_int)
- /* To end up here, vector 15 was changed - so we have to change it
- * back.
- */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _evt_system_call;
- p1.h = _evt_system_call;
- [p0] = p1;
- csync;
-
- /* Set orig_p0 to -1 to indicate this isn't the end of a syscall. */
- r0 = -1 (x);
- [sp + PT_ORIG_P0] = r0;
-
- p1 = rets;
- [sp + PT_RESERVED] = p1;
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- /* trace_hardirqs_on() checks if all irqs are disabled. But here IRQ 15
- * is turned on, so disable all irqs. */
- cli r0;
- sp += -12;
- call _trace_hardirqs_on;
- sp += 12;
-#endif
-#ifdef CONFIG_SMP
- GET_PDA(p0, r0); /* Fetch current PDA (can't migrate to other CPU here) */
- r0 = [p0 + PDA_IRQFLAGS];
-#else
- p0.l = _bfin_irq_flags;
- p0.h = _bfin_irq_flags;
- r0 = [p0];
-#endif
- sti r0;
-
- /* finish the userspace "atomic" functions for it */
- r1.l = lo(FIXED_CODE_END);
- r1.h = hi(FIXED_CODE_END);
- r2 = [sp + PT_PC];
- cc = r1 <= r2;
- if cc jump .Lresume_userspace (bp);
-
- r0 = sp;
- sp += -12;
-
- pseudo_long_call _finish_atomic_sections, p5;
- sp += 12;
- jump.s .Lresume_userspace;
-ENDPROC(_schedule_and_signal_from_int)
-
-ENTRY(_schedule_and_signal)
- SAVE_CONTEXT_SYSCALL
- /* To end up here, vector 15 was changed - so we have to change it
- * back.
- */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _evt_system_call;
- p1.h = _evt_system_call;
- [p0] = p1;
- csync;
- p0.l = 1f;
- p0.h = 1f;
- [sp + PT_RESERVED] = P0;
- call .Lresume_userspace;
-1:
- RESTORE_CONTEXT
- rti;
-ENDPROC(_schedule_and_signal)
-
-/* We handle this 100% in exception space - to reduce overhead
- * Only potiential problem is if the software buffer gets swapped out of the
- * CPLB table - then double fault. - so we don't let this happen in other places
- */
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
-ENTRY(_ex_trace_buff_full)
- [--sp] = P3;
- [--sp] = P2;
- [--sp] = LC0;
- [--sp] = LT0;
- [--sp] = LB0;
- P5.L = _trace_buff_offset;
- P5.H = _trace_buff_offset;
- P3 = [P5]; /* trace_buff_offset */
- P5.L = lo(TBUFSTAT);
- P5.H = hi(TBUFSTAT);
- R7 = [P5];
- R7 <<= 1; /* double, since we need to read twice */
- LC0 = R7;
- R7 <<= 2; /* need to shift over again,
- * to get the number of bytes */
- P5.L = lo(TBUF);
- P5.H = hi(TBUF);
- R6 = ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*1024) - 1;
-
- P2 = R7;
- P3 = P3 + P2;
- R7 = P3;
- R7 = R7 & R6;
- P3 = R7;
- P2.L = _trace_buff_offset;
- P2.H = _trace_buff_offset;
- [P2] = P3;
-
- P2.L = _software_trace_buff;
- P2.H = _software_trace_buff;
-
- LSETUP (.Lstart, .Lend) LC0;
-.Lstart:
- R7 = [P5]; /* read TBUF */
- P4 = P3 + P2;
- [P4] = R7;
- P3 += -4;
- R7 = P3;
- R7 = R7 & R6;
-.Lend:
- P3 = R7;
-
- LB0 = [sp++];
- LT0 = [sp++];
- LC0 = [sp++];
- P2 = [sp++];
- P3 = [sp++];
- jump _bfin_return_from_exception;
-ENDPROC(_ex_trace_buff_full)
-
-#if CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN == 4
-.data
-#else
-.section .l1.data.B
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN */
-ENTRY(_trace_buff_offset)
- .long 0;
-ALIGN
-ENTRY(_software_trace_buff)
- .rept ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*256);
- .long 0
- .endr
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */
-
-#ifdef CONFIG_EARLY_PRINTK
-__INIT
-ENTRY(_early_trap)
- SAVE_ALL_SYS
- trace_buffer_stop(p0,r0);
-
- ANOMALY_283_315_WORKAROUND(p4, r5)
-
- /* Turn caches off, to ensure we don't get double exceptions */
-
- P4.L = LO(IMEM_CONTROL);
- P4.H = HI(IMEM_CONTROL);
-
- R5 = [P4]; /* Control Register*/
- BITCLR(R5,ENICPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- P4.L = LO(DMEM_CONTROL);
- P4.H = HI(DMEM_CONTROL);
- R5 = [P4];
- BITCLR(R5,ENDCPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- r1 = RETX;
-
- SP += -12;
- call _early_trap_c;
- SP += 12;
-ENDPROC(_early_trap)
-__FINIT
-#endif /* CONFIG_EARLY_PRINTK */
-
-/*
- * Put these in the kernel data section - that should always be covered by
- * a CPLB. This is needed to ensure we don't get double fault conditions
- */
-
-#ifdef CONFIG_SYSCALL_TAB_L1
-.section .l1.data
-#else
-.data
-#endif
-
-ENTRY(_ex_table)
- /* entry for each EXCAUSE[5:0]
- * This table must be in sync with the table in ./kernel/traps.c
- * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined
- */
- .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */
- .long _ex_trap_c /* 0x01 - User Defined - Software breakpoint */
-#ifdef CONFIG_KGDB
- .long _ex_trap_c /* 0x02 - User Defined - KGDB initial connection
- and break signal trap */
-#else
- .long _ex_replaceable /* 0x02 - User Defined */
-#endif
- .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
- .long _ex_trap_c /* 0x04 - User Defined - dump trace buffer */
- .long _ex_replaceable /* 0x05 - User Defined */
- .long _ex_replaceable /* 0x06 - User Defined */
- .long _ex_replaceable /* 0x07 - User Defined */
- .long _ex_replaceable /* 0x08 - User Defined */
- .long _ex_replaceable /* 0x09 - User Defined */
- .long _ex_replaceable /* 0x0A - User Defined */
- .long _ex_replaceable /* 0x0B - User Defined */
- .long _ex_replaceable /* 0x0C - User Defined */
- .long _ex_replaceable /* 0x0D - User Defined */
- .long _ex_replaceable /* 0x0E - User Defined */
- .long _ex_replaceable /* 0x0F - User Defined */
- .long _ex_single_step /* 0x10 - HW Single step */
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- .long _ex_trace_buff_full /* 0x11 - Trace Buffer Full */
-#else
- .long _ex_trap_c /* 0x11 - Trace Buffer Full */
-#endif
- .long _ex_trap_c /* 0x12 - Reserved */
- .long _ex_trap_c /* 0x13 - Reserved */
- .long _ex_trap_c /* 0x14 - Reserved */
- .long _ex_trap_c /* 0x15 - Reserved */
- .long _ex_trap_c /* 0x16 - Reserved */
- .long _ex_trap_c /* 0x17 - Reserved */
- .long _ex_trap_c /* 0x18 - Reserved */
- .long _ex_trap_c /* 0x19 - Reserved */
- .long _ex_trap_c /* 0x1A - Reserved */
- .long _ex_trap_c /* 0x1B - Reserved */
- .long _ex_trap_c /* 0x1C - Reserved */
- .long _ex_trap_c /* 0x1D - Reserved */
- .long _ex_trap_c /* 0x1E - Reserved */
- .long _ex_trap_c /* 0x1F - Reserved */
- .long _ex_trap_c /* 0x20 - Reserved */
- .long _ex_trap_c /* 0x21 - Undefined Instruction */
- .long _ex_trap_c /* 0x22 - Illegal Instruction Combination */
- .long _ex_dviol /* 0x23 - Data CPLB Protection Violation */
- .long _ex_trap_c /* 0x24 - Data access misaligned */
- .long _ex_trap_c /* 0x25 - Unrecoverable Event */
- .long _ex_dmiss /* 0x26 - Data CPLB Miss */
- .long _ex_dmult /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero */
- .long _ex_trap_c /* 0x28 - Emulation Watchpoint */
- .long _ex_trap_c /* 0x29 - Instruction fetch access error (535 only) */
- .long _ex_trap_c /* 0x2A - Instruction fetch misaligned */
- .long _ex_trap_c /* 0x2B - Instruction CPLB protection Violation */
- .long _ex_icplb_miss /* 0x2C - Instruction CPLB miss */
- .long _ex_trap_c /* 0x2D - Instruction CPLB Multiple Hits */
- .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */
- .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */
- .long _ex_trap_c /* 0x2F - Reserved */
- .long _ex_trap_c /* 0x30 - Reserved */
- .long _ex_trap_c /* 0x31 - Reserved */
- .long _ex_trap_c /* 0x32 - Reserved */
- .long _ex_trap_c /* 0x33 - Reserved */
- .long _ex_trap_c /* 0x34 - Reserved */
- .long _ex_trap_c /* 0x35 - Reserved */
- .long _ex_trap_c /* 0x36 - Reserved */
- .long _ex_trap_c /* 0x37 - Reserved */
- .long _ex_trap_c /* 0x38 - Reserved */
- .long _ex_trap_c /* 0x39 - Reserved */
- .long _ex_trap_c /* 0x3A - Reserved */
- .long _ex_trap_c /* 0x3B - Reserved */
- .long _ex_trap_c /* 0x3C - Reserved */
- .long _ex_trap_c /* 0x3D - Reserved */
- .long _ex_trap_c /* 0x3E - Reserved */
- .long _ex_trap_c /* 0x3F - Reserved */
-END(_ex_table)
-
-ENTRY(_sys_call_table)
- .long _sys_restart_syscall /* 0 */
- .long _sys_exit
- .long _sys_ni_syscall /* fork */
- .long _sys_read
- .long _sys_write
- .long _sys_open /* 5 */
- .long _sys_close
- .long _sys_ni_syscall /* old waitpid */
- .long _sys_creat
- .long _sys_link
- .long _sys_unlink /* 10 */
- .long _sys_execve
- .long _sys_chdir
- .long _sys_time
- .long _sys_mknod
- .long _sys_chmod /* 15 */
- .long _sys_chown /* chown16 */
- .long _sys_ni_syscall /* old break syscall holder */
- .long _sys_ni_syscall /* old stat */
- .long _sys_lseek
- .long _sys_getpid /* 20 */
- .long _sys_mount
- .long _sys_ni_syscall /* old umount */
- .long _sys_setuid
- .long _sys_getuid
- .long _sys_stime /* 25 */
- .long _sys_ptrace
- .long _sys_alarm
- .long _sys_ni_syscall /* old fstat */
- .long _sys_pause
- .long _sys_ni_syscall /* old utime */ /* 30 */
- .long _sys_ni_syscall /* old stty syscall holder */
- .long _sys_ni_syscall /* old gtty syscall holder */
- .long _sys_access
- .long _sys_nice
- .long _sys_ni_syscall /* 35 */ /* old ftime syscall holder */
- .long _sys_sync
- .long _sys_kill
- .long _sys_rename
- .long _sys_mkdir
- .long _sys_rmdir /* 40 */
- .long _sys_dup
- .long _sys_pipe
- .long _sys_times
- .long _sys_ni_syscall /* old prof syscall holder */
- .long _sys_brk /* 45 */
- .long _sys_setgid
- .long _sys_getgid
- .long _sys_ni_syscall /* old sys_signal */
- .long _sys_geteuid /* geteuid16 */
- .long _sys_getegid /* getegid16 */ /* 50 */
- .long _sys_acct
- .long _sys_umount /* recycled never used phys() */
- .long _sys_ni_syscall /* old lock syscall holder */
- .long _sys_ioctl
- .long _sys_fcntl /* 55 */
- .long _sys_ni_syscall /* old mpx syscall holder */
- .long _sys_setpgid
- .long _sys_ni_syscall /* old ulimit syscall holder */
- .long _sys_ni_syscall /* old old uname */
- .long _sys_umask /* 60 */
- .long _sys_chroot
- .long _sys_ustat
- .long _sys_dup2
- .long _sys_getppid
- .long _sys_getpgrp /* 65 */
- .long _sys_setsid
- .long _sys_ni_syscall /* old sys_sigaction */
- .long _sys_sgetmask
- .long _sys_ssetmask
- .long _sys_setreuid /* setreuid16 */ /* 70 */
- .long _sys_setregid /* setregid16 */
- .long _sys_ni_syscall /* old sys_sigsuspend */
- .long _sys_ni_syscall /* old sys_sigpending */
- .long _sys_sethostname
- .long _sys_setrlimit /* 75 */
- .long _sys_ni_syscall /* old getrlimit */
- .long _sys_getrusage
- .long _sys_gettimeofday
- .long _sys_settimeofday
- .long _sys_getgroups /* getgroups16 */ /* 80 */
- .long _sys_setgroups /* setgroups16 */
- .long _sys_ni_syscall /* old_select */
- .long _sys_symlink
- .long _sys_ni_syscall /* old lstat */
- .long _sys_readlink /* 85 */
- .long _sys_uselib
- .long _sys_ni_syscall /* sys_swapon */
- .long _sys_reboot
- .long _sys_ni_syscall /* old_readdir */
- .long _sys_ni_syscall /* sys_mmap */ /* 90 */
- .long _sys_munmap
- .long _sys_truncate
- .long _sys_ftruncate
- .long _sys_fchmod
- .long _sys_fchown /* fchown16 */ /* 95 */
- .long _sys_getpriority
- .long _sys_setpriority
- .long _sys_ni_syscall /* old profil syscall holder */
- .long _sys_statfs
- .long _sys_fstatfs /* 100 */
- .long _sys_ni_syscall
- .long _sys_ni_syscall /* old sys_socketcall */
- .long _sys_syslog
- .long _sys_setitimer
- .long _sys_getitimer /* 105 */
- .long _sys_newstat
- .long _sys_newlstat
- .long _sys_newfstat
- .long _sys_ni_syscall /* old uname */
- .long _sys_ni_syscall /* iopl for i386 */ /* 110 */
- .long _sys_vhangup
- .long _sys_ni_syscall /* obsolete idle() syscall */
- .long _sys_ni_syscall /* vm86old for i386 */
- .long _sys_wait4
- .long _sys_ni_syscall /* 115 */ /* sys_swapoff */
- .long _sys_sysinfo
- .long _sys_ni_syscall /* old sys_ipc */
- .long _sys_fsync
- .long _sys_ni_syscall /* old sys_sigreturn */
- .long _bfin_clone /* 120 */
- .long _sys_setdomainname
- .long _sys_newuname
- .long _sys_ni_syscall /* old sys_modify_ldt */
- .long _sys_adjtimex
- .long _sys_mprotect /* 125 */
- .long _sys_ni_syscall /* old sys_sigprocmask */
- .long _sys_ni_syscall /* old "creat_module" */
- .long _sys_init_module
- .long _sys_delete_module
- .long _sys_ni_syscall /* 130: old "get_kernel_syms" */
- .long _sys_quotactl
- .long _sys_getpgid
- .long _sys_fchdir
- .long _sys_bdflush
- .long _sys_ni_syscall /* 135 */ /* sys_sysfs */
- .long _sys_personality
- .long _sys_ni_syscall /* for afs_syscall */
- .long _sys_setfsuid /* setfsuid16 */
- .long _sys_setfsgid /* setfsgid16 */
- .long _sys_llseek /* 140 */
- .long _sys_getdents
- .long _sys_ni_syscall /* sys_select */
- .long _sys_flock
- .long _sys_msync
- .long _sys_readv /* 145 */
- .long _sys_writev
- .long _sys_getsid
- .long _sys_fdatasync
- .long _sys_sysctl
- .long _sys_mlock /* 150 */
- .long _sys_munlock
- .long _sys_mlockall
- .long _sys_munlockall
- .long _sys_sched_setparam
- .long _sys_sched_getparam /* 155 */
- .long _sys_sched_setscheduler
- .long _sys_sched_getscheduler
- .long _sys_sched_yield
- .long _sys_sched_get_priority_max
- .long _sys_sched_get_priority_min /* 160 */
- .long _sys_sched_rr_get_interval
- .long _sys_nanosleep
- .long _sys_mremap
- .long _sys_setresuid /* setresuid16 */
- .long _sys_getresuid /* getresuid16 */ /* 165 */
- .long _sys_ni_syscall /* for vm86 */
- .long _sys_ni_syscall /* old "query_module" */
- .long _sys_ni_syscall /* sys_poll */
- .long _sys_ni_syscall /* old nfsservctl */
- .long _sys_setresgid /* setresgid16 */ /* 170 */
- .long _sys_getresgid /* getresgid16 */
- .long _sys_prctl
- .long _sys_rt_sigreturn
- .long _sys_rt_sigaction
- .long _sys_rt_sigprocmask /* 175 */
- .long _sys_rt_sigpending
- .long _sys_rt_sigtimedwait
- .long _sys_rt_sigqueueinfo
- .long _sys_rt_sigsuspend
- .long _sys_pread64 /* 180 */
- .long _sys_pwrite64
- .long _sys_lchown /* lchown16 */
- .long _sys_getcwd
- .long _sys_capget
- .long _sys_capset /* 185 */
- .long _sys_sigaltstack
- .long _sys_sendfile
- .long _sys_ni_syscall /* streams1 */
- .long _sys_ni_syscall /* streams2 */
- .long _sys_vfork /* 190 */
- .long _sys_getrlimit
- .long _sys_mmap_pgoff
- .long _sys_truncate64
- .long _sys_ftruncate64
- .long _sys_stat64 /* 195 */
- .long _sys_lstat64
- .long _sys_fstat64
- .long _sys_chown
- .long _sys_getuid
- .long _sys_getgid /* 200 */
- .long _sys_geteuid
- .long _sys_getegid
- .long _sys_setreuid
- .long _sys_setregid
- .long _sys_getgroups /* 205 */
- .long _sys_setgroups
- .long _sys_fchown
- .long _sys_setresuid
- .long _sys_getresuid
- .long _sys_setresgid /* 210 */
- .long _sys_getresgid
- .long _sys_lchown
- .long _sys_setuid
- .long _sys_setgid
- .long _sys_setfsuid /* 215 */
- .long _sys_setfsgid
- .long _sys_pivot_root
- .long _sys_mincore
- .long _sys_madvise
- .long _sys_getdents64 /* 220 */
- .long _sys_fcntl64
- .long _sys_ni_syscall /* reserved for TUX */
- .long _sys_ni_syscall
- .long _sys_gettid
- .long _sys_readahead /* 225 */
- .long _sys_setxattr
- .long _sys_lsetxattr
- .long _sys_fsetxattr
- .long _sys_getxattr
- .long _sys_lgetxattr /* 230 */
- .long _sys_fgetxattr
- .long _sys_listxattr
- .long _sys_llistxattr
- .long _sys_flistxattr
- .long _sys_removexattr /* 235 */
- .long _sys_lremovexattr
- .long _sys_fremovexattr
- .long _sys_tkill
- .long _sys_sendfile64
- .long _sys_futex /* 240 */
- .long _sys_sched_setaffinity
- .long _sys_sched_getaffinity
- .long _sys_ni_syscall /* sys_set_thread_area */
- .long _sys_ni_syscall /* sys_get_thread_area */
- .long _sys_io_setup /* 245 */
- .long _sys_io_destroy
- .long _sys_io_getevents
- .long _sys_io_submit
- .long _sys_io_cancel
- .long _sys_ni_syscall /* 250 */ /* sys_alloc_hugepages */
- .long _sys_ni_syscall /* sys_freec_hugepages */
- .long _sys_exit_group
- .long _sys_lookup_dcookie
- .long _sys_bfin_spinlock
- .long _sys_epoll_create /* 255 */
- .long _sys_epoll_ctl
- .long _sys_epoll_wait
- .long _sys_ni_syscall /* remap_file_pages */
- .long _sys_set_tid_address
- .long _sys_timer_create /* 260 */
- .long _sys_timer_settime
- .long _sys_timer_gettime
- .long _sys_timer_getoverrun
- .long _sys_timer_delete
- .long _sys_clock_settime /* 265 */
- .long _sys_clock_gettime
- .long _sys_clock_getres
- .long _sys_clock_nanosleep
- .long _sys_statfs64
- .long _sys_fstatfs64 /* 270 */
- .long _sys_tgkill
- .long _sys_utimes
- .long _sys_fadvise64_64
- .long _sys_ni_syscall /* vserver */
- .long _sys_mbind /* 275 */
- .long _sys_ni_syscall /* get_mempolicy */
- .long _sys_ni_syscall /* set_mempolicy */
- .long _sys_mq_open
- .long _sys_mq_unlink
- .long _sys_mq_timedsend /* 280 */
- .long _sys_mq_timedreceive
- .long _sys_mq_notify
- .long _sys_mq_getsetattr
- .long _sys_ni_syscall /* kexec_load */
- .long _sys_waitid /* 285 */
- .long _sys_add_key
- .long _sys_request_key
- .long _sys_keyctl
- .long _sys_ioprio_set
- .long _sys_ioprio_get /* 290 */
- .long _sys_inotify_init
- .long _sys_inotify_add_watch
- .long _sys_inotify_rm_watch
- .long _sys_ni_syscall /* migrate_pages */
- .long _sys_openat /* 295 */
- .long _sys_mkdirat
- .long _sys_mknodat
- .long _sys_fchownat
- .long _sys_futimesat
- .long _sys_fstatat64 /* 300 */
- .long _sys_unlinkat
- .long _sys_renameat
- .long _sys_linkat
- .long _sys_symlinkat
- .long _sys_readlinkat /* 305 */
- .long _sys_fchmodat
- .long _sys_faccessat
- .long _sys_pselect6
- .long _sys_ppoll
- .long _sys_unshare /* 310 */
- .long _sys_sram_alloc
- .long _sys_sram_free
- .long _sys_dma_memcpy
- .long _sys_accept
- .long _sys_bind /* 315 */
- .long _sys_connect
- .long _sys_getpeername
- .long _sys_getsockname
- .long _sys_getsockopt
- .long _sys_listen /* 320 */
- .long _sys_recv
- .long _sys_recvfrom
- .long _sys_recvmsg
- .long _sys_send
- .long _sys_sendmsg /* 325 */
- .long _sys_sendto
- .long _sys_setsockopt
- .long _sys_shutdown
- .long _sys_socket
- .long _sys_socketpair /* 330 */
- .long _sys_semctl
- .long _sys_semget
- .long _sys_semop
- .long _sys_msgctl
- .long _sys_msgget /* 335 */
- .long _sys_msgrcv
- .long _sys_msgsnd
- .long _sys_shmat
- .long _sys_shmctl
- .long _sys_shmdt /* 340 */
- .long _sys_shmget
- .long _sys_splice
- .long _sys_sync_file_range
- .long _sys_tee
- .long _sys_vmsplice /* 345 */
- .long _sys_epoll_pwait
- .long _sys_utimensat
- .long _sys_signalfd
- .long _sys_timerfd_create
- .long _sys_eventfd /* 350 */
- .long _sys_pread64
- .long _sys_pwrite64
- .long _sys_fadvise64
- .long _sys_set_robust_list
- .long _sys_get_robust_list /* 355 */
- .long _sys_fallocate
- .long _sys_semtimedop
- .long _sys_timerfd_settime
- .long _sys_timerfd_gettime
- .long _sys_signalfd4 /* 360 */
- .long _sys_eventfd2
- .long _sys_epoll_create1
- .long _sys_dup3
- .long _sys_pipe2
- .long _sys_inotify_init1 /* 365 */
- .long _sys_preadv
- .long _sys_pwritev
- .long _sys_rt_tgsigqueueinfo
- .long _sys_perf_event_open
- .long _sys_recvmmsg /* 370 */
- .long _sys_fanotify_init
- .long _sys_fanotify_mark
- .long _sys_prlimit64
- .long _sys_cacheflush
- .long _sys_name_to_handle_at /* 375 */
- .long _sys_open_by_handle_at
- .long _sys_clock_adjtime
- .long _sys_syncfs
- .long _sys_setns
- .long _sys_sendmmsg /* 380 */
- .long _sys_process_vm_readv
- .long _sys_process_vm_writev
- .long _sys_kcmp
- .long _sys_finit_module
- .long _sys_sched_setattr /* 385 */
- .long _sys_sched_getattr
- .long _sys_renameat2
- .long _sys_seccomp
- .long _sys_getrandom
- .long _sys_memfd_create /* 390 */
- .long _sys_bpf
- .long _sys_execveat
-
- .rept NR_syscalls-(.-_sys_call_table)/4
- .long _sys_ni_syscall
- .endr
-END(_sys_call_table)
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
deleted file mode 100644
index 31515f0..0000000
--- a/arch/blackfin/mach-common/head.S
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Common Blackfin startup code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#include <asm/thread_info.h>
-#include <asm/trace.h>
-#include <asm/asm-offsets.h>
-
-__INIT
-
-ENTRY(__init_clear_bss)
- r2 = r2 - r1;
- cc = r2 == 0;
- if cc jump .L_bss_done;
- r2 >>= 2;
- p1 = r1;
- p2 = r2;
- lsetup (1f, 1f) lc0 = p2;
-1: [p1++] = r0;
-.L_bss_done:
- rts;
-ENDPROC(__init_clear_bss)
-
-ENTRY(__start)
- /* R0: argument of command line string, passed from uboot, save it */
- R7 = R0;
-
- /* Enable Cycle Counter and Nesting Of Interrupts */
-#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
- R0 = SYSCFG_SNEN;
-#else
- R0 = SYSCFG_SNEN | SYSCFG_CCEN;
-#endif
- SYSCFG = R0;
-
- /* Optimization register tricks: keep a base value in the
- * reserved P registers so we use the load/store with an
- * offset syntax. R0 = [P5 + <constant>];
- * P5 - core MMR base
- * R6 - 0
- */
- r6 = 0;
- p5.l = 0;
- p5.h = hi(COREMMR_BASE);
-
- /* Zero out registers required by Blackfin ABI */
-
- /* Disable circular buffers */
- L0 = r6;
- L1 = r6;
- L2 = r6;
- L3 = r6;
-
- /* Disable hardware loops in case we were started by 'go' */
- LC0 = r6;
- LC1 = r6;
-
- /*
- * Clear ITEST_COMMAND and DTEST_COMMAND registers,
- * Leaving these as non-zero can confuse the emulator
- */
- [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
- [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
- CSYNC;
-
- trace_buffer_init(p0,r0);
-
- /* Turn off the icache */
- r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENICPLB_P);
- [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* Turn off the dcache */
- r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENDCPLB_P);
- [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* in case of double faults, save a few things */
- p1.l = _initial_pda;
- p1.h = _initial_pda;
- r4 = RETX;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Only save these if we are storing them,
- * This happens here, since L1 gets clobbered
- * below
- */
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_DF_RETX];
- r1 = [p0 + PDA_DF_DCPLB];
- r2 = [p0 + PDA_DF_ICPLB];
- r3 = [p0 + PDA_DF_SEQSTAT];
- [p1 + PDA_INIT_DF_RETX] = r0;
- [p1 + PDA_INIT_DF_DCPLB] = r1;
- [p1 + PDA_INIT_DF_ICPLB] = r2;
- [p1 + PDA_INIT_DF_SEQSTAT] = r3;
-#endif
- [p1 + PDA_INIT_RETX] = r4;
-
- /* Initialize stack pointer */
- sp.l = _init_thread_union + THREAD_SIZE;
- sp.h = _init_thread_union + THREAD_SIZE;
- fp = sp;
- usp = sp;
-
-#ifdef CONFIG_EARLY_PRINTK
- call _init_early_exception_vectors;
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#endif
-
- r0 = r6;
- /* Zero out all of the fun bss regions */
-#if L1_DATA_A_LENGTH > 0
- r1.l = __sbss_l1;
- r1.h = __sbss_l1;
- r2.l = __ebss_l1;
- r2.h = __ebss_l1;
- call __init_clear_bss
-#endif
-#if L1_DATA_B_LENGTH > 0
- r1.l = __sbss_b_l1;
- r1.h = __sbss_b_l1;
- r2.l = __ebss_b_l1;
- r2.h = __ebss_b_l1;
- call __init_clear_bss
-#endif
-#if L2_LENGTH > 0
- r1.l = __sbss_l2;
- r1.h = __sbss_l2;
- r2.l = __ebss_l2;
- r2.h = __ebss_l2;
- call __init_clear_bss
-#endif
- r1.l = ___bss_start;
- r1.h = ___bss_start;
- r2.l = ___bss_stop;
- r2.h = ___bss_stop;
- call __init_clear_bss
-
- /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
- call _bfin_relocate_l1_mem;
-
-#ifdef CONFIG_ROMKERNEL
- call _bfin_relocate_xip_data;
-#endif
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
- /* Only use on-chip scratch space for stack when absolutely required
- * to avoid Anomaly 05000227 ... we know the init_clocks() func only
- * uses L1 text and stack space and no other memory region.
- */
-# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
- sp.l = lo(KERNEL_CLOCK_STACK);
- sp.h = hi(KERNEL_CLOCK_STACK);
- call _init_clocks;
- sp = usp; /* usp hasn't been touched, so restore from there */
-#endif
-
- /* This section keeps the processor in supervisor mode
- * during kernel boot. Switches to user mode at end of boot.
- * See page 3-9 of Hardware Reference manual for documentation.
- */
-
- /* EVT15 = _real_start */
-
- p1.l = _real_start;
- p1.h = _real_start;
- [p5 + (EVT15 - COREMMR_BASE)] = p1;
- csync;
-
-#ifdef CONFIG_EARLY_PRINTK
- r0 = (EVT_IVG15 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU) (z);
-#else
- r0 = EVT_IVG15 (z);
-#endif
- sti r0;
-
- raise 15;
-#ifdef CONFIG_EARLY_PRINTK
- p0.l = _early_trap;
- p0.h = _early_trap;
-#else
- p0.l = .LWAIT_HERE;
- p0.h = .LWAIT_HERE;
-#endif
- reti = p0;
-#if ANOMALY_05000281
- nop; nop; nop;
-#endif
- rti;
-
-.LWAIT_HERE:
- jump .LWAIT_HERE;
-ENDPROC(__start)
-
-/* A little BF561 glue ... */
-#ifndef WDOG_CTL
-# define WDOG_CTL WDOGA_CTL
-#endif
-
-ENTRY(_real_start)
- /* Enable nested interrupts */
- [--sp] = reti;
- /* watchdog off for now */
- p0.l = lo(WDOG_CTL);
- p0.h = hi(WDOG_CTL);
- r0 = 0xAD6(z);
- w[p0] = r0;
- ssync;
- /* Pass the u-boot arguments to the global value command line */
- R0 = R7;
- call _cmdline_init;
-
- sp += -12 + 4; /* +4 is for reti loading above */
- call _init_pda
- sp += 12;
- jump.l _start_kernel;
-ENDPROC(_real_start)
-
-__FINIT
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
deleted file mode 100644
index 469ce72..0000000
--- a/arch/blackfin/mach-common/interrupt.S
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * Interrupt Entries
- *
- * Copyright 2005-2009 Analog Devices Inc.
- * D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>
- * Kenneth Albanowski <kjahds@kjahds.com>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <mach/irq.h>
-#include <linux/linkage.h>
-#include <asm/entry.h>
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-#include <asm/traps.h>
-#include <asm/thread_info.h>
-
-#include <asm/context.S>
-
-.extern _ret_from_exception
-
-#ifdef CONFIG_I_ENTRY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 4 /* just in case */
-
-/* Common interrupt entry code. First we do CLI, then push
- * RETI, to keep interrupts disabled, but to allow this state to be changed
- * by local_bh_enable.
- * R0 contains the interrupt number, while R1 may contain the value of IPEND,
- * or garbage if IPEND won't be needed by the ISR. */
-__common_int_entry:
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r2 = RETI;
- [--sp] = r2;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r1; /* IPEND - R1 may or may not be set up before jumping here. */
-
- /* Switch to other method of keeping interrupts disabled. */
-#ifdef CONFIG_DEBUG_HWERR
- r1 = 0x3f;
- sti r1;
-#else
- cli r1;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = r0;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- r0 = [sp++];
-#endif
- [--sp] = RETI; /* orig_pc */
- /* Clear all L registers. */
- r1 = 0 (x);
- l0 = r1;
- l1 = r1;
- l2 = r1;
- l3 = r1;
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
- r1 = sp;
- SP += -12;
-#ifdef CONFIG_IPIPE
- call ___ipipe_grab_irq
- SP += 12;
- cc = r0 == 0;
- if cc jump .Lcommon_restore_context;
-#else /* CONFIG_IPIPE */
-
-#ifdef CONFIG_PREEMPT
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4;
- p5 = r7;
- r7 = [p5 + TI_PREEMPT]; /* get preempt count */
- r7 += 1; /* increment it */
- [p5 + TI_PREEMPT] = r7;
-#endif
- pseudo_long_call _do_irq, p2;
-
-#ifdef CONFIG_PREEMPT
- r7 += -1;
- [p5 + TI_PREEMPT] = r7; /* restore preempt count */
-#endif
-
- SP += 12;
-#endif /* CONFIG_IPIPE */
- pseudo_long_call _return_from_int, p2;
-.Lcommon_restore_context:
- RESTORE_CONTEXT
- rti;
-
-/* interrupt routine for ivhw - 5 */
-ENTRY(_evt_ivhw)
- /* In case a single action kicks off multiple memory transactions, (like
- * a cache line fetch, - this can cause multiple hardware errors, let's
- * catch them all. First - make sure all the actions are complete, and
- * the core sees the hardware errors.
- */
- SSYNC;
- SSYNC;
-
- SAVE_ALL_SYS
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
- /* Handle all stacked hardware errors
- * To make sure we don't hang forever, only do it 10 times
- */
- R0 = 0;
- R2 = 10;
-1:
- P0.L = LO(ILAT);
- P0.H = HI(ILAT);
- R1 = [P0];
- CC = BITTST(R1, EVT_IVHW_P);
- IF ! CC JUMP 2f;
- /* OK a hardware error is pending - clear it */
- R1 = EVT_IVHW_P;
- [P0] = R1;
- R0 += 1;
- CC = R1 == R2;
- if CC JUMP 2f;
- JUMP 1b;
-2:
- # We are going to dump something out, so make sure we print IPEND properly
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
- /* set the EXCAUSE to HWERR for trap_c */
- r0 = [sp + PT_SEQSTAT];
- R1.L = LO(VEC_HWERR);
- R1.H = HI(VEC_HWERR);
- R0 = R0 | R1;
- [sp + PT_SEQSTAT] = R0;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _trap_c, p5;
- SP += 12;
-
-#ifdef EBIU_ERRMST
- /* make sure EBIU_ERRMST is clear */
- p0.l = LO(EBIU_ERRMST);
- p0.h = HI(EBIU_ERRMST);
- r0.l = (CORE_ERROR | CORE_MERROR);
- w[p0] = r0.l;
-#endif
-
- pseudo_long_call _ret_from_exception, p2;
-
-.Lcommon_restore_all_sys:
- RESTORE_ALL_SYS
- rti;
-ENDPROC(_evt_ivhw)
-
-/* Interrupt routine for evt2 (NMI).
- * For inner circle type details, please see:
- * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:nmi
- */
-ENTRY(_evt_nmi)
-#ifndef CONFIG_NMI_WATCHDOG
-.weak _evt_nmi
-#else
- /* Not take account of CPLBs, this handler will not return */
- SAVE_ALL_SYS
- r0 = sp;
- r1 = retn;
- [sp + PT_PC] = r1;
- trace_buffer_save(p4,r5);
-
- ANOMALY_283_315_WORKAROUND(p4, r5)
-
- SP += -12;
- call _do_nmi;
- SP += 12;
-1:
- jump 1b;
-#endif
- rtn;
-ENDPROC(_evt_nmi)
-
-/* interrupt routine for core timer - 6 */
-ENTRY(_evt_timer)
- TIMER_INTERRUPT_ENTRY(EVT_IVTMR_P)
-
-/* interrupt routine for evt7 - 7 */
-ENTRY(_evt_evt7)
- INTERRUPT_ENTRY(EVT_IVG7_P)
-ENTRY(_evt_evt8)
- INTERRUPT_ENTRY(EVT_IVG8_P)
-ENTRY(_evt_evt9)
- INTERRUPT_ENTRY(EVT_IVG9_P)
-ENTRY(_evt_evt10)
- INTERRUPT_ENTRY(EVT_IVG10_P)
-ENTRY(_evt_evt11)
- INTERRUPT_ENTRY(EVT_IVG11_P)
-ENTRY(_evt_evt12)
- INTERRUPT_ENTRY(EVT_IVG12_P)
-ENTRY(_evt_evt13)
- INTERRUPT_ENTRY(EVT_IVG13_P)
-
-
- /* interrupt routine for system_call - 15 */
-ENTRY(_evt_system_call)
- SAVE_CONTEXT_SYSCALL
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
- pseudo_long_call _system_call, p2;
- jump .Lcommon_restore_context;
-ENDPROC(_evt_system_call)
-
-#ifdef CONFIG_IPIPE
-/*
- * __ipipe_call_irqtail: lowers the current priority level to EVT15
- * before running a user-defined routine, then raises the priority
- * level to EVT14 to prepare the caller for a normal interrupt
- * return through RTI.
- *
- * We currently use this feature in two occasions:
- *
- * - before branching to __ipipe_irq_tail_hook as requested by a high
- * priority domain after the pipeline delivered an interrupt,
- * e.g. such as Xenomai, in order to start its rescheduling
- * procedure, since we may not switch tasks when IRQ levels are
- * nested on the Blackfin, so we have to fake an interrupt return
- * so that we may reschedule immediately.
- *
- * - before branching to __ipipe_sync_root(), in order to play any interrupt
- * pending for the root domain (i.e. the Linux kernel). This lowers
- * the core priority level enough so that Linux IRQ handlers may
- * never delay interrupts handled by high priority domains; we defer
- * those handlers until this point instead. This is a substitute
- * to using a threaded interrupt model for the Linux kernel.
- *
- * r0: address of user-defined routine
- * context: caller must have preempted EVT15, hw interrupts must be off.
- */
-ENTRY(___ipipe_call_irqtail)
- p0 = r0;
- r0.l = 1f;
- r0.h = 1f;
- reti = r0;
- rti;
-1:
- [--sp] = rets;
- [--sp] = ( r7:4, p5:3 );
- sp += -12;
- call (p0);
- sp += 12;
- ( r7:4, p5:3 ) = [sp++];
- rets = [sp++];
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | \
- EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | \
- EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
- raise 14; /* Branches to _evt_evt14 */
-2:
- jump 2b; /* Likely paranoid. */
-ENDPROC(___ipipe_call_irqtail)
-
-#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
deleted file mode 100644
index e81a5b7..0000000
--- a/arch/blackfin/mach-common/ints-priority.c
+++ /dev/null
@@ -1,1366 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * 2003 Bas Vermeulen <bas@buyways.nl>
- * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * 1999 D. Jeff Dionne <jeff@uclinux.org>
- * 1996 Roman Zippel
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/module.h>
-#include <linux/kernel_stat.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/syscore_ops.h>
-#include <asm/delay.h>
-#ifdef CONFIG_IPIPE
-#include <linux/ipipe.h>
-#endif
-#include <asm/traps.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/dpmc.h>
-#include <asm/traps.h>
-#include <asm/gpio.h>
-
-/*
- * NOTES:
- * - we have separated the physical Hardware interrupt from the
- * levels that the LINUX kernel sees (see the description in irq.h)
- * -
- */
-
-#ifndef CONFIG_SMP
-/* Initialize this to an actual value to force it into the .data
- * section so that we know it is properly initialized at entry into
- * the kernel but before bss is initialized to zero (which is where
- * it would live otherwise). The 0x1f magic represents the IRQs we
- * cannot actually mask out in hardware.
- */
-unsigned long bfin_irq_flags = 0x1f;
-EXPORT_SYMBOL(bfin_irq_flags);
-#endif
-
-#ifdef CONFIG_PM
-unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
-unsigned vr_wakeup;
-#endif
-
-#ifndef SEC_GCTL
-static struct ivgx {
- /* irq number for request_irq, available in mach-bf5xx/irq.h */
- unsigned int irqno;
- /* corresponding bit in the SIC_ISR register */
- unsigned int isrflag;
-} ivg_table[NR_PERI_INTS];
-
-static struct ivg_slice {
- /* position of first irq in ivg_table for given ivg */
- struct ivgx *ifirst;
- struct ivgx *istop;
-} ivg7_13[IVG13 - IVG7 + 1];
-
-
-/*
- * Search SIC_IAR and fill tables with the irqvalues
- * and their positions in the SIC_ISR register.
- */
-static void __init search_IAR(void)
-{
- unsigned ivg, irq_pos = 0;
- for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
- int irqN;
-
- ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
-
- for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
- int irqn;
- u32 iar =
- bfin_read32((unsigned long *)SIC_IAR0 +
-#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
- defined(CONFIG_BF538) || defined(CONFIG_BF539)
- ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
-#else
- (irqN >> 3)
-#endif
- );
- for (irqn = irqN; irqn < irqN + 4; ++irqn) {
- int iar_shift = (irqn & 7) * 4;
- if (ivg == (0xf & (iar >> iar_shift))) {
- ivg_table[irq_pos].irqno = IVG7 + irqn;
- ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
- ivg7_13[ivg].istop++;
- irq_pos++;
- }
- }
- }
- }
-}
-#endif
-
-/*
- * This is for core internal IRQs
- */
-void bfin_ack_noop(struct irq_data *d)
-{
- /* Dummy function. */
-}
-
-static void bfin_core_mask_irq(struct irq_data *d)
-{
- bfin_irq_flags &= ~(1 << d->irq);
- if (!hard_irqs_disabled())
- hard_local_irq_enable();
-}
-
-static void bfin_core_unmask_irq(struct irq_data *d)
-{
- bfin_irq_flags |= 1 << d->irq;
- /*
- * If interrupts are enabled, IMASK must contain the same value
- * as bfin_irq_flags. Make sure that invariant holds. If interrupts
- * are currently disabled we need not do anything; one of the
- * callers will take care of setting IMASK to the proper value
- * when reenabling interrupts.
- * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
- * what we need.
- */
- if (!hard_irqs_disabled())
- hard_local_irq_enable();
- return;
-}
-
-#ifndef SEC_GCTL
-void bfin_internal_mask_irq(unsigned int irq)
-{
- unsigned long flags = hard_local_irq_save();
-#ifdef SIC_IMASK0
- unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
- unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
- bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
- ~(1 << mask_bit));
-# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
- ~(1 << mask_bit));
-# endif
-#else
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
- ~(1 << BFIN_SYSIRQ(irq)));
-#endif /* end of SIC_IMASK0 */
- hard_local_irq_restore(flags);
-}
-
-static void bfin_internal_mask_irq_chip(struct irq_data *d)
-{
- bfin_internal_mask_irq(d->irq);
-}
-
-#ifdef CONFIG_SMP
-void bfin_internal_unmask_irq_affinity(unsigned int irq,
- const struct cpumask *affinity)
-#else
-void bfin_internal_unmask_irq(unsigned int irq)
-#endif
-{
- unsigned long flags = hard_local_irq_save();
-
-#ifdef SIC_IMASK0
- unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
- unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
-# ifdef CONFIG_SMP
- if (cpumask_test_cpu(0, affinity))
-# endif
- bfin_write_SIC_IMASK(mask_bank,
- bfin_read_SIC_IMASK(mask_bank) |
- (1 << mask_bit));
-# ifdef CONFIG_SMP
- if (cpumask_test_cpu(1, affinity))
- bfin_write_SICB_IMASK(mask_bank,
- bfin_read_SICB_IMASK(mask_bank) |
- (1 << mask_bit));
-# endif
-#else
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
- (1 << BFIN_SYSIRQ(irq)));
-#endif
- hard_local_irq_restore(flags);
-}
-
-#ifdef CONFIG_SMP
-static void bfin_internal_unmask_irq_chip(struct irq_data *d)
-{
- bfin_internal_unmask_irq_affinity(d->irq,
- irq_data_get_affinity_mask(d));
-}
-
-static int bfin_internal_set_affinity(struct irq_data *d,
- const struct cpumask *mask, bool force)
-{
- bfin_internal_mask_irq(d->irq);
- bfin_internal_unmask_irq_affinity(d->irq, mask);
-
- return 0;
-}
-#else
-static void bfin_internal_unmask_irq_chip(struct irq_data *d)
-{
- bfin_internal_unmask_irq(d->irq);
-}
-#endif
-
-#if defined(CONFIG_PM)
-int bfin_internal_set_wake(unsigned int irq, unsigned int state)
-{
- u32 bank, bit, wakeup = 0;
- unsigned long flags;
- bank = BFIN_SYSIRQ(irq) / 32;
- bit = BFIN_SYSIRQ(irq) % 32;
-
- switch (irq) {
-#ifdef IRQ_RTC
- case IRQ_RTC:
- wakeup |= WAKE;
- break;
-#endif
-#ifdef IRQ_CAN0_RX
- case IRQ_CAN0_RX:
- wakeup |= CANWE;
- break;
-#endif
-#ifdef IRQ_CAN1_RX
- case IRQ_CAN1_RX:
- wakeup |= CANWE;
- break;
-#endif
-#ifdef IRQ_USB_INT0
- case IRQ_USB_INT0:
- wakeup |= USBWE;
- break;
-#endif
-#ifdef CONFIG_BF54x
- case IRQ_CNT:
- wakeup |= ROTWE;
- break;
-#endif
- default:
- break;
- }
-
- flags = hard_local_irq_save();
-
- if (state) {
- bfin_sic_iwr[bank] |= (1 << bit);
- vr_wakeup |= wakeup;
-
- } else {
- bfin_sic_iwr[bank] &= ~(1 << bit);
- vr_wakeup &= ~wakeup;
- }
-
- hard_local_irq_restore(flags);
-
- return 0;
-}
-
-static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
-{
- return bfin_internal_set_wake(d->irq, state);
-}
-#else
-inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
-{
- return 0;
-}
-# define bfin_internal_set_wake_chip NULL
-#endif
-
-#else /* SEC_GCTL */
-static void bfin_sec_preflow_handler(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write_SEC_SCI(0, SEC_CSID, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_mask_ack_irq(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write_SEC_SCI(0, SEC_CSID, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_unmask_irq(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write32(SEC_END, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable_ssi(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl |= SEC_SCTL_SRC_EN;
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable_ssi(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
- bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable_sci(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- if (sid == BFIN_SYSIRQ(IRQ_WATCH0))
- reg_sctl |= SEC_SCTL_FAULT_EN;
- else
- reg_sctl |= SEC_SCTL_INT_EN;
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable_sci(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_sec_enable_sci(sid);
- bfin_sec_enable_ssi(sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_sec_disable_sci(sid);
- bfin_sec_disable_ssi(sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl;
- int i;
-
- bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
-
- for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
- reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
- reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
- bfin_write_SEC_SCTL(i, reg_sctl);
- }
-
- hard_local_irq_restore(flags);
-}
-
-void bfin_sec_raise_irq(unsigned int irq)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(irq);
-
- bfin_write32(SEC_RAISE, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void init_software_driven_irq(void)
-{
- bfin_sec_set_ssi_coreid(34, 0);
- bfin_sec_set_ssi_coreid(35, 1);
-
- bfin_sec_enable_sci(35);
- bfin_sec_enable_ssi(35);
- bfin_sec_set_ssi_coreid(36, 0);
- bfin_sec_set_ssi_coreid(37, 1);
- bfin_sec_enable_sci(37);
- bfin_sec_enable_ssi(37);
-}
-
-void handle_sec_sfi_fault(uint32_t gstat)
-{
-
-}
-
-void handle_sec_sci_fault(uint32_t gstat)
-{
- uint32_t core_id;
- uint32_t cstat;
-
- core_id = gstat & SEC_GSTAT_SCI;
- cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
- if (cstat & SEC_CSTAT_ERR) {
- switch (cstat & SEC_CSTAT_ERRC) {
- case SEC_CSTAT_ACKERR:
- printk(KERN_DEBUG "sec ack err\n");
- break;
- default:
- printk(KERN_DEBUG "sec sci unknown err\n");
- }
- }
-
-}
-
-void handle_sec_ssi_fault(uint32_t gstat)
-{
- uint32_t sid;
- uint32_t sstat;
-
- sid = gstat & SEC_GSTAT_SID;
- sstat = bfin_read_SEC_SSTAT(sid);
-
-}
-
-void handle_sec_fault(uint32_t sec_gstat)
-{
- if (sec_gstat & SEC_GSTAT_ERR) {
-
- switch (sec_gstat & SEC_GSTAT_ERRC) {
- case 0:
- handle_sec_sfi_fault(sec_gstat);
- break;
- case SEC_GSTAT_SCIERR:
- handle_sec_sci_fault(sec_gstat);
- break;
- case SEC_GSTAT_SSIERR:
- handle_sec_ssi_fault(sec_gstat);
- break;
- }
-
-
- }
-}
-
-static struct irqaction bfin_fault_irq = {
- .name = "Blackfin fault",
-};
-
-static irqreturn_t bfin_fault_routine(int irq, void *data)
-{
- struct pt_regs *fp = get_irq_regs();
-
- switch (irq) {
- case IRQ_C0_DBL_FAULT:
- double_fault_c(fp);
- break;
- case IRQ_C0_HW_ERR:
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- printk(KERN_NOTICE "Kernel Stack\n");
- show_stack(current, NULL);
- print_modules();
- panic("Core 0 hardware error");
- break;
- case IRQ_C0_NMI_L1_PARITY_ERR:
- panic("Core 0 NMI L1 parity error");
- break;
- case IRQ_SEC_ERR:
- pr_err("SEC error\n");
- handle_sec_fault(bfin_read32(SEC_GSTAT));
- break;
- default:
- panic("Unknown fault %d", irq);
- }
-
- return IRQ_HANDLED;
-}
-#endif /* SEC_GCTL */
-
-static struct irq_chip bfin_core_irqchip = {
- .name = "CORE",
- .irq_mask = bfin_core_mask_irq,
- .irq_unmask = bfin_core_unmask_irq,
-};
-
-#ifndef SEC_GCTL
-static struct irq_chip bfin_internal_irqchip = {
- .name = "INTN",
- .irq_mask = bfin_internal_mask_irq_chip,
- .irq_unmask = bfin_internal_unmask_irq_chip,
- .irq_disable = bfin_internal_mask_irq_chip,
- .irq_enable = bfin_internal_unmask_irq_chip,
-#ifdef CONFIG_SMP
- .irq_set_affinity = bfin_internal_set_affinity,
-#endif
- .irq_set_wake = bfin_internal_set_wake_chip,
-};
-#else
-static struct irq_chip bfin_sec_irqchip = {
- .name = "SEC",
- .irq_mask_ack = bfin_sec_mask_ack_irq,
- .irq_mask = bfin_sec_mask_ack_irq,
- .irq_unmask = bfin_sec_unmask_irq,
- .irq_eoi = bfin_sec_unmask_irq,
- .irq_disable = bfin_sec_disable,
- .irq_enable = bfin_sec_enable,
-};
-#endif
-
-void bfin_handle_irq(unsigned irq)
-{
-#ifdef CONFIG_IPIPE
- struct pt_regs regs; /* Contents not used. */
- ipipe_trace_irq_entry(irq);
- __ipipe_handle_irq(irq, ®s);
- ipipe_trace_irq_exit(irq);
-#else /* !CONFIG_IPIPE */
- generic_handle_irq(irq);
-#endif /* !CONFIG_IPIPE */
-}
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-static int mac_stat_int_mask;
-
-static void bfin_mac_status_ack_irq(unsigned int irq)
-{
- switch (irq) {
- case IRQ_MAC_MMCINT:
- bfin_write_EMAC_MMC_TIRQS(
- bfin_read_EMAC_MMC_TIRQE() &
- bfin_read_EMAC_MMC_TIRQS());
- bfin_write_EMAC_MMC_RIRQS(
- bfin_read_EMAC_MMC_RIRQE() &
- bfin_read_EMAC_MMC_RIRQS());
- break;
- case IRQ_MAC_RXFSINT:
- bfin_write_EMAC_RX_STKY(
- bfin_read_EMAC_RX_IRQE() &
- bfin_read_EMAC_RX_STKY());
- break;
- case IRQ_MAC_TXFSINT:
- bfin_write_EMAC_TX_STKY(
- bfin_read_EMAC_TX_IRQE() &
- bfin_read_EMAC_TX_STKY());
- break;
- case IRQ_MAC_WAKEDET:
- bfin_write_EMAC_WKUP_CTL(
- bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
- break;
- default:
- /* These bits are W1C */
- bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
- break;
- }
-}
-
-static void bfin_mac_status_mask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
- mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
-#ifdef BF537_FAMILY
- switch (irq) {
- case IRQ_MAC_PHYINT:
- bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
- break;
- default:
- break;
- }
-#else
- if (!mac_stat_int_mask)
- bfin_internal_mask_irq(IRQ_MAC_ERROR);
-#endif
- bfin_mac_status_ack_irq(irq);
-}
-
-static void bfin_mac_status_unmask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
-#ifdef BF537_FAMILY
- switch (irq) {
- case IRQ_MAC_PHYINT:
- bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
- break;
- default:
- break;
- }
-#else
- if (!mac_stat_int_mask)
- bfin_internal_unmask_irq(IRQ_MAC_ERROR);
-#endif
- mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
-}
-
-#ifdef CONFIG_PM
-int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
-{
-#ifdef BF537_FAMILY
- return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
-#else
- return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
-#endif
-}
-#else
-# define bfin_mac_status_set_wake NULL
-#endif
-
-static struct irq_chip bfin_mac_status_irqchip = {
- .name = "MACST",
- .irq_mask = bfin_mac_status_mask_irq,
- .irq_unmask = bfin_mac_status_unmask_irq,
- .irq_set_wake = bfin_mac_status_set_wake,
-};
-
-void bfin_demux_mac_status_irq(struct irq_desc *inta_desc)
-{
- int i, irq = 0;
- u32 status = bfin_read_EMAC_SYSTAT();
-
- for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
- if (status & (1L << i)) {
- irq = IRQ_MAC_PHYINT + i;
- break;
- }
-
- if (irq) {
- if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
- bfin_handle_irq(irq);
- } else {
- bfin_mac_status_ack_irq(irq);
- pr_debug("IRQ %d:"
- " MASKED MAC ERROR INTERRUPT ASSERTED\n",
- irq);
- }
- } else
- printk(KERN_ERR
- "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
- " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
- "(EMAC_SYSTAT=0x%X)\n",
- __func__, __FILE__, __LINE__, status);
-}
-#endif
-
-static inline void bfin_set_irq_handler(struct irq_data *d, irq_flow_handler_t handle)
-{
-#ifdef CONFIG_IPIPE
- handle = handle_level_irq;
-#endif
- irq_set_handler_locked(d, handle);
-}
-
-#ifdef CONFIG_GPIO_ADI
-
-static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
-
-static void bfin_gpio_ack_irq(struct irq_data *d)
-{
- /* AFAIK ack_irq in case mask_ack is provided
- * get's only called for edge sense irqs
- */
- set_gpio_data(irq_to_gpio(d->irq), 0);
-}
-
-static void bfin_gpio_mask_ack_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- u32 gpionr = irq_to_gpio(irq);
-
- if (!irqd_is_level_type(d))
- set_gpio_data(gpionr, 0);
-
- set_gpio_maska(gpionr, 0);
-}
-
-static void bfin_gpio_mask_irq(struct irq_data *d)
-{
- set_gpio_maska(irq_to_gpio(d->irq), 0);
-}
-
-static void bfin_gpio_unmask_irq(struct irq_data *d)
-{
- set_gpio_maska(irq_to_gpio(d->irq), 1);
-}
-
-static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
-{
- u32 gpionr = irq_to_gpio(d->irq);
-
- if (__test_and_set_bit(gpionr, gpio_enabled))
- bfin_gpio_irq_prepare(gpionr);
-
- bfin_gpio_unmask_irq(d);
-
- return 0;
-}
-
-static void bfin_gpio_irq_shutdown(struct irq_data *d)
-{
- u32 gpionr = irq_to_gpio(d->irq);
-
- bfin_gpio_mask_irq(d);
- __clear_bit(gpionr, gpio_enabled);
- bfin_gpio_irq_free(gpionr);
-}
-
-static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
-{
- unsigned int irq = d->irq;
- int ret;
- char buf[16];
- u32 gpionr = irq_to_gpio(irq);
-
- if (type == IRQ_TYPE_PROBE) {
- /* only probe unenabled GPIO interrupt lines */
- if (test_bit(gpionr, gpio_enabled))
- return 0;
- type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
- }
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
- IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-
- snprintf(buf, 16, "gpio-irq%d", irq);
- ret = bfin_gpio_irq_request(gpionr, buf);
- if (ret)
- return ret;
-
- if (__test_and_set_bit(gpionr, gpio_enabled))
- bfin_gpio_irq_prepare(gpionr);
-
- } else {
- __clear_bit(gpionr, gpio_enabled);
- return 0;
- }
-
- set_gpio_inen(gpionr, 0);
- set_gpio_dir(gpionr, 0);
-
- if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- set_gpio_both(gpionr, 1);
- else
- set_gpio_both(gpionr, 0);
-
- if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
- set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
- else
- set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
- set_gpio_edge(gpionr, 1);
- set_gpio_inen(gpionr, 1);
- set_gpio_data(gpionr, 0);
-
- } else {
- set_gpio_edge(gpionr, 0);
- set_gpio_inen(gpionr, 1);
- }
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- bfin_set_irq_handler(d, handle_edge_irq);
- else
- bfin_set_irq_handler(d, handle_level_irq);
-
- return 0;
-}
-
-static void bfin_demux_gpio_block(unsigned int irq)
-{
- unsigned int gpio, mask;
-
- gpio = irq_to_gpio(irq);
- mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
-
- while (mask) {
- if (mask & 1)
- bfin_handle_irq(irq);
- irq++;
- mask >>= 1;
- }
-}
-
-void bfin_demux_gpio_irq(struct irq_desc *desc)
-{
- unsigned int inta_irq = irq_desc_get_irq(desc);
- unsigned int irq;
-
- switch (inta_irq) {
-#if defined(BF537_FAMILY)
- case IRQ_PF_INTA_PG_INTA:
- bfin_demux_gpio_block(IRQ_PF0);
- irq = IRQ_PG0;
- break;
- case IRQ_PH_INTA_MAC_RX:
- irq = IRQ_PH0;
- break;
-#elif defined(BF533_FAMILY)
- case IRQ_PROG_INTA:
- irq = IRQ_PF0;
- break;
-#elif defined(BF538_FAMILY)
- case IRQ_PORTF_INTA:
- irq = IRQ_PF0;
- break;
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- case IRQ_PORTF_INTA:
- irq = IRQ_PF0;
- break;
- case IRQ_PORTG_INTA:
- irq = IRQ_PG0;
- break;
- case IRQ_PORTH_INTA:
- irq = IRQ_PH0;
- break;
-#elif defined(CONFIG_BF561)
- case IRQ_PROG0_INTA:
- irq = IRQ_PF0;
- break;
- case IRQ_PROG1_INTA:
- irq = IRQ_PF16;
- break;
- case IRQ_PROG2_INTA:
- irq = IRQ_PF32;
- break;
-#endif
- default:
- BUG();
- return;
- }
-
- bfin_demux_gpio_block(irq);
-}
-
-#ifdef CONFIG_PM
-
-static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
-{
- return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
-}
-
-#else
-
-# define bfin_gpio_set_wake NULL
-
-#endif
-
-static struct irq_chip bfin_gpio_irqchip = {
- .name = "GPIO",
- .irq_ack = bfin_gpio_ack_irq,
- .irq_mask = bfin_gpio_mask_irq,
- .irq_mask_ack = bfin_gpio_mask_ack_irq,
- .irq_unmask = bfin_gpio_unmask_irq,
- .irq_disable = bfin_gpio_mask_irq,
- .irq_enable = bfin_gpio_unmask_irq,
- .irq_set_type = bfin_gpio_irq_type,
- .irq_startup = bfin_gpio_irq_startup,
- .irq_shutdown = bfin_gpio_irq_shutdown,
- .irq_set_wake = bfin_gpio_set_wake,
-};
-
-#endif
-
-#ifdef CONFIG_PM
-
-#ifdef SEC_GCTL
-static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
-
-static int sec_suspend(void)
-{
- u32 bank;
-
- for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
- save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0));
- return 0;
-}
-
-static void sec_resume(void)
-{
- u32 bank;
-
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
- udelay(100);
- bfin_write_SEC_GCTL(SEC_GCTL_EN);
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-
- for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
- bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
-}
-
-static struct syscore_ops sec_pm_syscore_ops = {
- .suspend = sec_suspend,
- .resume = sec_resume,
-};
-#endif
-
-#endif
-
-void init_exception_vectors(void)
-{
- /* cannot program in software:
- * evt0 - emulation (jtag)
- * evt1 - reset
- */
- bfin_write_EVT2(evt_nmi);
- bfin_write_EVT3(trap);
- bfin_write_EVT5(evt_ivhw);
- bfin_write_EVT6(evt_timer);
- bfin_write_EVT7(evt_evt7);
- bfin_write_EVT8(evt_evt8);
- bfin_write_EVT9(evt_evt9);
- bfin_write_EVT10(evt_evt10);
- bfin_write_EVT11(evt_evt11);
- bfin_write_EVT12(evt_evt12);
- bfin_write_EVT13(evt_evt13);
- bfin_write_EVT14(evt_evt14);
- bfin_write_EVT15(evt_system_call);
- CSYNC();
-}
-
-#ifndef SEC_GCTL
-/*
- * This function should be called during kernel startup to initialize
- * the BFin IRQ handling routines.
- */
-
-int __init init_arch_irq(void)
-{
- int irq;
- unsigned long ilat = 0;
-
- /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
-#ifdef SIC_IMASK0
- bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
- bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
-# ifdef SIC_IMASK2
- bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
-# endif
-# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
- bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
-# endif
-#else
- bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
-#endif
-
- local_irq_disable();
-
- for (irq = 0; irq <= SYS_IRQS; irq++) {
- if (irq <= IRQ_CORETMR)
- irq_set_chip(irq, &bfin_core_irqchip);
- else
- irq_set_chip(irq, &bfin_internal_irqchip);
-
- switch (irq) {
-#if !BFIN_GPIO_PINT
-#if defined(BF537_FAMILY)
- case IRQ_PH_INTA_MAC_RX:
- case IRQ_PF_INTA_PG_INTA:
-#elif defined(BF533_FAMILY)
- case IRQ_PROG_INTA:
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- case IRQ_PORTF_INTA:
- case IRQ_PORTG_INTA:
- case IRQ_PORTH_INTA:
-#elif defined(CONFIG_BF561)
- case IRQ_PROG0_INTA:
- case IRQ_PROG1_INTA:
- case IRQ_PROG2_INTA:
-#elif defined(BF538_FAMILY)
- case IRQ_PORTF_INTA:
-#endif
- irq_set_chained_handler(irq, bfin_demux_gpio_irq);
- break;
-#endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
- case IRQ_MAC_ERROR:
- irq_set_chained_handler(irq,
- bfin_demux_mac_status_irq);
- break;
-#endif
-#if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- case IRQ_SUPPLE_0:
- case IRQ_SUPPLE_1:
- irq_set_handler(irq, handle_percpu_irq);
- break;
-#endif
-
-#ifdef CONFIG_TICKSOURCE_CORETMR
- case IRQ_CORETMR:
-# ifdef CONFIG_SMP
- irq_set_handler(irq, handle_percpu_irq);
-# else
- irq_set_handler(irq, handle_simple_irq);
-# endif
- break;
-#endif
-
-#ifdef CONFIG_TICKSOURCE_GPTMR0
- case IRQ_TIMER0:
- irq_set_handler(irq, handle_simple_irq);
- break;
-#endif
-
- default:
-#ifdef CONFIG_IPIPE
- irq_set_handler(irq, handle_level_irq);
-#else
- irq_set_handler(irq, handle_simple_irq);
-#endif
- break;
- }
- }
-
- init_mach_irq();
-
-#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
- for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
- irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
- handle_level_irq);
-#endif
- /* if configured as edge, then will be changed to do_edge_IRQ */
-#ifdef CONFIG_GPIO_ADI
- for (irq = GPIO_IRQ_BASE;
- irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
- irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
- handle_level_irq);
-#endif
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
- /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
- * local_irq_enable()
- */
- program_IAR();
- /* Therefore it's better to setup IARs before interrupts enabled */
- search_IAR();
-
- /* Enable interrupts IVG7-15 */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
-
- /* This implicitly covers ANOMALY_05000171
- * Boot-ROM code modifies SICA_IWRx wakeup registers
- */
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-# ifdef SIC_IWR1
- /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_DISABLE_ALL);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-static int vec_to_irq(int vec)
-{
- struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
- struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
- unsigned long sic_status[3];
- if (likely(vec == EVT_IVTMR_P))
- return IRQ_CORETMR;
-#ifdef SIC_ISR
- sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
-#else
- if (smp_processor_id()) {
-# ifdef SICB_ISR0
- /* This will be optimized out in UP mode. */
- sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
- sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
-# endif
- } else {
- sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
- sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
- }
-#endif
-#ifdef SIC_ISR2
- sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
-#endif
-
- for (;; ivg++) {
- if (ivg >= ivg_stop)
- return -1;
-#ifdef SIC_ISR
- if (sic_status[0] & ivg->isrflag)
-#else
- if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
-#endif
- return ivg->irqno;
- }
-}
-
-#else /* SEC_GCTL */
-
-/*
- * This function should be called during kernel startup to initialize
- * the BFin IRQ handling routines.
- */
-
-int __init init_arch_irq(void)
-{
- int irq;
- unsigned long ilat = 0;
-
- bfin_write_SEC_GCTL(SEC_GCTL_RESET);
-
- local_irq_disable();
-
- for (irq = 0; irq <= SYS_IRQS; irq++) {
- if (irq <= IRQ_CORETMR) {
- irq_set_chip_and_handler(irq, &bfin_core_irqchip,
- handle_simple_irq);
-#if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP)
- if (irq == IRQ_CORETMR)
- irq_set_handler(irq, handle_percpu_irq);
-#endif
- } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
- irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
- handle_percpu_irq);
- } else {
- irq_set_chip(irq, &bfin_sec_irqchip);
- irq_set_handler(irq, handle_fasteoi_irq);
- __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
- }
- }
-
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
-
- bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
-
- /* Enable interrupts IVG7-15 */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
-
- bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
- bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0));
- bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0));
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
- udelay(100);
- bfin_write_SEC_GCTL(SEC_GCTL_EN);
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
- bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-
- init_software_driven_irq();
-
-#ifdef CONFIG_PM
- register_syscore_ops(&sec_pm_syscore_ops);
-#endif
-
- bfin_fault_irq.handler = bfin_fault_routine;
-#ifdef CONFIG_L1_PARITY_CHECK
- setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq);
-#endif
- setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq);
- setup_irq(IRQ_SEC_ERR, &bfin_fault_irq);
-
- return 0;
-}
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-static int vec_to_irq(int vec)
-{
- if (likely(vec == EVT_IVTMR_P))
- return IRQ_CORETMR;
-
- return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
-}
-#endif /* SEC_GCTL */
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-void do_irq(int vec, struct pt_regs *fp)
-{
- int irq = vec_to_irq(vec);
- if (irq == -1)
- return;
- asm_do_IRQ(irq, fp);
-}
-
-#ifdef CONFIG_IPIPE
-
-int __ipipe_get_irq_priority(unsigned irq)
-{
- int ient, prio;
-
- if (irq <= IRQ_CORETMR)
- return irq;
-
-#ifdef SEC_GCTL
- if (irq >= BFIN_IRQ(0))
- return IVG11;
-#else
- for (ient = 0; ient < NR_PERI_INTS; ient++) {
- struct ivgx *ivg = ivg_table + ient;
- if (ivg->irqno == irq) {
- for (prio = 0; prio <= IVG13-IVG7; prio++) {
- if (ivg7_13[prio].ifirst <= ivg &&
- ivg7_13[prio].istop > ivg)
- return IVG7 + prio;
- }
- }
- }
-#endif
-
- return IVG15;
-}
-
-/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
- struct ipipe_domain *this_domain = __ipipe_current_domain;
- int irq, s = 0;
-
- irq = vec_to_irq(vec);
- if (irq == -1)
- return 0;
-
- if (irq == IRQ_SYSTMR) {
-#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
- bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
-#endif
- /* This is basically what we need from the register frame. */
- __this_cpu_write(__ipipe_tick_regs.ipend, regs->ipend);
- __this_cpu_write(__ipipe_tick_regs.pc, regs->pc);
- if (this_domain != ipipe_root_domain)
- __this_cpu_and(__ipipe_tick_regs.ipend, ~0x10);
- else
- __this_cpu_or(__ipipe_tick_regs.ipend, 0x10);
- }
-
- /*
- * We don't want Linux interrupt handlers to run at the
- * current core priority level (i.e. < EVT15), since this
- * might delay other interrupts handled by a high priority
- * domain. Here is what we do instead:
- *
- * - we raise the SYNCDEFER bit to prevent
- * __ipipe_handle_irq() to sync the pipeline for the root
- * stage for the incoming interrupt. Upon return, that IRQ is
- * pending in the interrupt log.
- *
- * - we raise the TIF_IRQ_SYNC bit for the current thread, so
- * that _schedule_and_signal_from_int will eventually sync the
- * pipeline from EVT15.
- */
- if (this_domain == ipipe_root_domain) {
- s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
- barrier();
- }
-
- ipipe_trace_irq_entry(irq);
- __ipipe_handle_irq(irq, regs);
- ipipe_trace_irq_exit(irq);
-
- if (user_mode(regs) &&
- !ipipe_test_foreign_stack() &&
- (current->ipipe_flags & PF_EVTRET) != 0) {
- /*
- * Testing for user_regs() does NOT fully eliminate
- * foreign stack contexts, because of the forged
- * interrupt returns we do through
- * __ipipe_call_irqtail. In that case, we might have
- * preempted a foreign stack context in a high
- * priority domain, with a single interrupt level now
- * pending after the irqtail unwinding is done. In
- * which case user_mode() is now true, and the event
- * gets dispatched spuriously.
- */
- current->ipipe_flags &= ~PF_EVTRET;
- __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
- }
-
- if (this_domain == ipipe_root_domain) {
- set_thread_flag(TIF_IRQ_SYNC);
- if (!s) {
- __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
- return !test_bit(IPIPE_STALL_FLAG, &p->status);
- }
- }
-
- return 0;
-}
-
-#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
deleted file mode 100644
index f57b5fe..0000000
--- a/arch/blackfin/mach-common/pm.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Blackfin power management
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- * based on arm/mach-omap/pm.c
- * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
- */
-
-#include <linux/suspend.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-
-#include <asm/cplb.h>
-#include <asm/dma.h>
-#include <asm/dpmc.h>
-#include <asm/pm.h>
-#include <asm/gpio.h>
-
-#ifdef CONFIG_BF60x
-struct bfin_cpu_pm_fns *bfin_cpu_pm;
-#endif
-
-void bfin_pm_suspend_standby_enter(void)
-{
-#if !BFIN_GPIO_PINT
- bfin_pm_standby_setup();
-#endif
-
-#ifdef CONFIG_BF60x
- bfin_cpu_pm->enter(PM_SUSPEND_STANDBY);
-#else
-# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
- sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
-# else
- sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
-# endif
-#endif
-
-#if !BFIN_GPIO_PINT
- bfin_pm_standby_restore();
-#endif
-
-#ifndef CONFIG_BF60x
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-# ifdef SIC_IWR1
- /* BF52x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_DISABLE_ALL);
-#endif
-
-#endif
-}
-
-int bf53x_suspend_l1_mem(unsigned char *memptr)
-{
- dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
- L1_CODE_LENGTH);
- dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
- (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
- dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
- (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
- memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
- L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
- L1_SCRATCH_LENGTH);
-
- return 0;
-}
-
-int bf53x_resume_l1_mem(unsigned char *memptr)
-{
- dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
- dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
- L1_DATA_A_LENGTH);
- dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
- L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
- memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
- L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
-
- return 0;
-}
-
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-# ifdef CONFIG_BF60x
-__attribute__((l1_text))
-# endif
-static void flushinv_all_dcache(void)
-{
- register u32 way, bank, subbank, set;
- register u32 status, addr;
- u32 dmem_ctl = bfin_read_DMEM_CONTROL();
-
- for (bank = 0; bank < 2; ++bank) {
- if (!(dmem_ctl & (1 << (DMC1_P - bank))))
- continue;
-
- for (way = 0; way < 2; ++way)
- for (subbank = 0; subbank < 4; ++subbank)
- for (set = 0; set < 64; ++set) {
-
- bfin_write_DTEST_COMMAND(
- way << 26 |
- bank << 23 |
- subbank << 16 |
- set << 5
- );
- CSYNC();
- status = bfin_read_DTEST_DATA0();
-
- /* only worry about valid/dirty entries */
- if ((status & 0x3) != 0x3)
- continue;
-
-
- /* construct the address using the tag */
- addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
-
- /* flush it */
- __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
- }
- }
-}
-#endif
-
-int bfin_pm_suspend_mem_enter(void)
-{
- int ret;
-#ifndef CONFIG_BF60x
- int wakeup;
-#endif
-
- unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
- + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
- GFP_ATOMIC);
-
- if (memptr == NULL) {
- panic("bf53x_suspend_l1_mem malloc failed");
- return -ENOMEM;
- }
-
-#ifndef CONFIG_BF60x
- wakeup = bfin_read_VR_CTL() & ~FREQ;
- wakeup |= SCKELOW;
-
-#ifdef CONFIG_PM_BFIN_WAKE_PH6
- wakeup |= PHYWE;
-#endif
-#ifdef CONFIG_PM_BFIN_WAKE_GP
- wakeup |= GPWE;
-#endif
-#endif
-
- ret = blackfin_dma_suspend();
-
- if (ret) {
- kfree(memptr);
- return ret;
- }
-
-#ifdef CONFIG_GPIO_ADI
- bfin_gpio_pm_hibernate_suspend();
-#endif
-
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
- flushinv_all_dcache();
- udelay(1);
-#endif
- _disable_dcplb();
- _disable_icplb();
- bf53x_suspend_l1_mem(memptr);
-
-#ifndef CONFIG_BF60x
- do_hibernate(wakeup | vr_wakeup); /* See you later! */
-#else
- bfin_cpu_pm->enter(PM_SUSPEND_MEM);
-#endif
-
- bf53x_resume_l1_mem(memptr);
-
- _enable_icplb();
- _enable_dcplb();
-
-#ifdef CONFIG_GPIO_ADI
- bfin_gpio_pm_hibernate_restore();
-#endif
- blackfin_dma_resume();
-
- kfree(memptr);
-
- return 0;
-}
-
-/*
- * bfin_pm_valid - Tell the PM core that we only support the standby sleep
- * state
- * @state: suspend state we're checking.
- *
- */
-static int bfin_pm_valid(suspend_state_t state)
-{
- return (state == PM_SUSPEND_STANDBY
-#if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
- /*
- * On BF533/2/1:
- * If we enter Hibernate the SCKE Pin is driven Low,
- * so that the SDRAM enters Self Refresh Mode.
- * However when the reset sequence that follows hibernate
- * state is executed, SCKE is driven High, taking the
- * SDRAM out of Self Refresh.
- *
- * If you reconfigure and access the SDRAM "very quickly",
- * you are likely to avoid errors, otherwise the SDRAM
- * start losing its contents.
- * An external HW workaround is possible using logic gates.
- */
- || state == PM_SUSPEND_MEM
-#endif
- );
-}
-
-/*
- * bfin_pm_enter - Actually enter a sleep state.
- * @state: State we're entering.
- *
- */
-static int bfin_pm_enter(suspend_state_t state)
-{
- switch (state) {
- case PM_SUSPEND_STANDBY:
- bfin_pm_suspend_standby_enter();
- break;
- case PM_SUSPEND_MEM:
- bfin_pm_suspend_mem_enter();
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
-void bfin_pm_end(void)
-{
- u32 cycle, cycle2;
- u64 usec64;
- u32 usec;
-
- __asm__ __volatile__ (
- "1: %0 = CYCLES2\n"
- "%1 = CYCLES\n"
- "%2 = CYCLES2\n"
- "CC = %2 == %0\n"
- "if ! CC jump 1b\n"
- : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC"
- );
-
- usec64 = ((u64)cycle2 << 32) + cycle;
- do_div(usec64, get_cclk() / USEC_PER_SEC);
- usec = usec64;
- if (usec == 0)
- usec = 1;
-
- pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n",
- usec / USEC_PER_MSEC, usec % USEC_PER_MSEC);
-}
-#endif
-
-static const struct platform_suspend_ops bfin_pm_ops = {
- .enter = bfin_pm_enter,
- .valid = bfin_pm_valid,
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- .end = bfin_pm_end,
-#endif
-};
-
-static int __init bfin_pm_init(void)
-{
- suspend_set_ops(&bfin_pm_ops);
- return 0;
-}
-
-__initcall(bfin_pm_init);
diff --git a/arch/blackfin/mach-common/scb-init.c b/arch/blackfin/mach-common/scb-init.c
deleted file mode 100644
index 8923398..0000000
--- a/arch/blackfin/mach-common/scb-init.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <asm/scb.h>
-
-__attribute__((l1_text))
-inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots,
- unsigned char *scb_mi_prio)
-{
- unsigned int i;
-
- for (i = 0; i < slots; ++i)
- bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]);
-}
-
-__attribute__((l1_text))
-inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots,
- unsigned char *scb_mi_prio)
-{
- unsigned int i;
-
- for (i = 0; i < slots; ++i) {
- bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i);
- scb_mi_prio[i] = bfin_read32(scb_mi_arbw);
- }
-}
-
-__attribute__((l1_text))
-void init_scb(void)
-{
- unsigned int i, j;
- unsigned char scb_tmp_prio[32];
-
- pr_info("Init System Crossbar\n");
- for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) {
-
- scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio);
-
- pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr);
- scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio);
- for (j = 0; j < scb_data[i].scb_mi_slots; ++j)
- pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]);
- }
-
-}
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
deleted file mode 100644
index b32ddab..0000000
--- a/arch/blackfin/mach-common/smp.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
- *
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched/mm.h>
-#include <linux/sched/task_stack.h>
-#include <linux/interrupt.h>
-#include <linux/cache.h>
-#include <linux/clockchips.h>
-#include <linux/profile.h>
-#include <linux/errno.h>
-#include <linux/mm.h>
-#include <linux/cpu.h>
-#include <linux/smp.h>
-#include <linux/cpumask.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#include <linux/slab.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-#include <asm/irq_handler.h>
-#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/processor.h>
-#include <asm/ptrace.h>
-#include <asm/cpu.h>
-#include <asm/time.h>
-#include <linux/err.h>
-
-/*
- * Anomaly notes:
- * 05000120 - we always define corelock as 32-bit integer in L2
- */
-struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
-unsigned long blackfin_iflush_l1_entry[NR_CPUS];
-#endif
-
-struct blackfin_initial_pda initial_pda_coreb;
-
-enum ipi_message_type {
- BFIN_IPI_NONE,
- BFIN_IPI_TIMER,
- BFIN_IPI_RESCHEDULE,
- BFIN_IPI_CALL_FUNC,
- BFIN_IPI_CPU_STOP,
-};
-
-struct blackfin_flush_data {
- unsigned long start;
- unsigned long end;
-};
-
-void *secondary_stack;
-
-static struct blackfin_flush_data smp_flush_data;
-
-static DEFINE_SPINLOCK(stop_lock);
-
-/* A magic number - stress test shows this is safe for common cases */
-#define BFIN_IPI_MSGQ_LEN 5
-
-/* Simple FIFO buffer, overflow leads to panic */
-struct ipi_data {
- atomic_t count;
- atomic_t bits;
-};
-
-static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);
-
-static void ipi_cpu_stop(unsigned int cpu)
-{
- spin_lock(&stop_lock);
- printk(KERN_CRIT "CPU%u: stopping\n", cpu);
- dump_stack();
- spin_unlock(&stop_lock);
-
- set_cpu_online(cpu, false);
-
- local_irq_disable();
-
- while (1)
- SSYNC();
-}
-
-static void ipi_flush_icache(void *info)
-{
- struct blackfin_flush_data *fdata = info;
-
- /* Invalidate the memory holding the bounds of the flushed region. */
- blackfin_dcache_invalidate_range((unsigned long)fdata,
- (unsigned long)fdata + sizeof(*fdata));
-
- /* Make sure all write buffers in the data side of the core
- * are flushed before trying to invalidate the icache. This
- * needs to be after the data flush and before the icache
- * flush so that the SSYNC does the right thing in preventing
- * the instruction prefetcher from hitting things in cached
- * memory at the wrong time -- it runs much further ahead than
- * the pipeline.
- */
- SSYNC();
-
- /* ipi_flaush_icache is invoked by generic flush_icache_range,
- * so call blackfin arch icache flush directly here.
- */
- blackfin_icache_flush_range(fdata->start, fdata->end);
-}
-
-/* Use IRQ_SUPPLE_0 to request reschedule.
- * When returning from interrupt to user space,
- * there is chance to reschedule */
-static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
-{
- unsigned int cpu = smp_processor_id();
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_0);
- return IRQ_HANDLED;
-}
-
-DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
-void ipi_timer(void)
-{
- int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
- evt->event_handler(evt);
-}
-
-static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
-{
- struct ipi_data *bfin_ipi_data;
- unsigned int cpu = smp_processor_id();
- unsigned long pending;
- unsigned long msg;
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_1);
-
- smp_rmb();
- bfin_ipi_data = this_cpu_ptr(&bfin_ipi);
- while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
- msg = 0;
- do {
- msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
- switch (msg) {
- case BFIN_IPI_TIMER:
- ipi_timer();
- break;
- case BFIN_IPI_RESCHEDULE:
- scheduler_ipi();
- break;
- case BFIN_IPI_CALL_FUNC:
- generic_smp_call_function_interrupt();
- break;
- case BFIN_IPI_CPU_STOP:
- ipi_cpu_stop(cpu);
- break;
- default:
- goto out;
- }
- atomic_dec(&bfin_ipi_data->count);
- } while (msg < BITS_PER_LONG);
-
- }
-out:
- return IRQ_HANDLED;
-}
-
-static void bfin_ipi_init(void)
-{
- unsigned int cpu;
- struct ipi_data *bfin_ipi_data;
- for_each_possible_cpu(cpu) {
- bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
- atomic_set(&bfin_ipi_data->bits, 0);
- atomic_set(&bfin_ipi_data->count, 0);
- }
-}
-
-void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
-{
- unsigned int cpu;
- struct ipi_data *bfin_ipi_data;
- unsigned long flags;
-
- local_irq_save(flags);
- for_each_cpu(cpu, cpumask) {
- bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
- atomic_or((1 << msg), &bfin_ipi_data->bits);
- atomic_inc(&bfin_ipi_data->count);
- }
- local_irq_restore(flags);
- smp_wmb();
- for_each_cpu(cpu, cpumask)
- platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
-}
-
-void arch_send_call_function_single_ipi(int cpu)
-{
- send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
-}
-
-void arch_send_call_function_ipi_mask(const struct cpumask *mask)
-{
- send_ipi(mask, BFIN_IPI_CALL_FUNC);
-}
-
-void smp_send_reschedule(int cpu)
-{
- send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);
-
- return;
-}
-
-void smp_send_msg(const struct cpumask *mask, unsigned long type)
-{
- send_ipi(mask, type);
-}
-
-void smp_timer_broadcast(const struct cpumask *mask)
-{
- smp_send_msg(mask, BFIN_IPI_TIMER);
-}
-
-void smp_send_stop(void)
-{
- cpumask_t callmap;
-
- preempt_disable();
- cpumask_copy(&callmap, cpu_online_mask);
- cpumask_clear_cpu(smp_processor_id(), &callmap);
- if (!cpumask_empty(&callmap))
- send_ipi(&callmap, BFIN_IPI_CPU_STOP);
-
- preempt_enable();
-
- return;
-}
-
-int __cpu_up(unsigned int cpu, struct task_struct *idle)
-{
- int ret;
-
- secondary_stack = task_stack_page(idle) + THREAD_SIZE;
-
- ret = platform_boot_secondary(cpu, idle);
-
- secondary_stack = NULL;
-
- return ret;
-}
-
-static void setup_secondary(unsigned int cpu)
-{
- unsigned long ilat;
-
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- /* Enable interrupt levels IVG7-15. IARs have been already
- * programmed by the boot CPU. */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-}
-
-void secondary_start_kernel(void)
-{
- unsigned int cpu = smp_processor_id();
- struct mm_struct *mm = &init_mm;
-
- if (_bfin_swrst & SWRST_DBL_FAULT_B) {
- printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
- initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
- initial_pda_coreb.retx_doublefault);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
- initial_pda_coreb.dcplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
- initial_pda_coreb.icplb_doublefault_addr);
-#endif
- printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
- initial_pda_coreb.retx);
- }
-
- /*
- * We want the D-cache to be enabled early, in case the atomic
- * support code emulates cache coherence (see
- * __ARCH_SYNC_CORE_DCACHE).
- */
- init_exception_vectors();
-
- local_irq_disable();
-
- /* Attach the new idle task to the global mm. */
- mmget(mm);
- mmgrab(mm);
- current->active_mm = mm;
-
- preempt_disable();
-
- setup_secondary(cpu);
-
- platform_secondary_init(cpu);
- /* setup local core timer */
- bfin_local_timer_setup();
-
- local_irq_enable();
-
- bfin_setup_caches(cpu);
-
- notify_cpu_starting(cpu);
- /*
- * Calibrate loops per jiffy value.
- * IRQs need to be enabled here - D-cache can be invalidated
- * in timer irq handler, so core B can read correct jiffies.
- */
- calibrate_delay();
-
- /* We are done with local CPU inits, unblock the boot CPU. */
- set_cpu_online(cpu, true);
- cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
-}
-
-void __init smp_prepare_boot_cpu(void)
-{
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
- platform_prepare_cpus(max_cpus);
- bfin_ipi_init();
- platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
- platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
-}
-
-void __init smp_cpus_done(unsigned int max_cpus)
-{
- unsigned long bogosum = 0;
- unsigned int cpu;
-
- for_each_online_cpu(cpu)
- bogosum += loops_per_jiffy;
-
- printk(KERN_INFO "SMP: Total of %d processors activated "
- "(%lu.%02lu BogoMIPS).\n",
- num_online_cpus(),
- bogosum / (500000/HZ),
- (bogosum / (5000/HZ)) % 100);
-}
-
-void smp_icache_flush_range_others(unsigned long start, unsigned long end)
-{
- smp_flush_data.start = start;
- smp_flush_data.end = end;
-
- preempt_disable();
- if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
- printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
- preempt_enable();
-}
-EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
-
-#ifdef __ARCH_SYNC_CORE_ICACHE
-unsigned long icache_invld_count[NR_CPUS];
-void resync_core_icache(void)
-{
- unsigned int cpu = get_cpu();
- blackfin_invalidate_entire_icache();
- icache_invld_count[cpu]++;
- put_cpu();
-}
-EXPORT_SYMBOL(resync_core_icache);
-#endif
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-unsigned long dcache_invld_count[NR_CPUS];
-unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
-
-void resync_core_dcache(void)
-{
- unsigned int cpu = get_cpu();
- blackfin_invalidate_entire_dcache();
- dcache_invld_count[cpu]++;
- put_cpu();
-}
-EXPORT_SYMBOL(resync_core_dcache);
-#endif
-
-#ifdef CONFIG_HOTPLUG_CPU
-int __cpu_disable(void)
-{
- unsigned int cpu = smp_processor_id();
-
- if (cpu == 0)
- return -EPERM;
-
- set_cpu_online(cpu, false);
- return 0;
-}
-
-int __cpu_die(unsigned int cpu)
-{
- return cpu_wait_death(cpu, 5);
-}
-
-void cpu_die(void)
-{
- (void)cpu_report_death();
-
- atomic_dec(&init_mm.mm_users);
- atomic_dec(&init_mm.mm_count);
-
- local_irq_disable();
- platform_cpu_die();
-}
-#endif
diff --git a/arch/blackfin/mm/Makefile b/arch/blackfin/mm/Makefile
deleted file mode 100644
index 4c011b1f6..0000000
--- a/arch/blackfin/mm/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mm/Makefile
-#
-
-obj-y := sram-alloc.o isram-driver.o init.o maccess.o
diff --git a/arch/blackfin/mm/blackfin_sram.h b/arch/blackfin/mm/blackfin_sram.h
deleted file mode 100644
index fb0b159..0000000
--- a/arch/blackfin/mm/blackfin_sram.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Local prototypes meant for internal use only
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_SRAM_H__
-#define __BLACKFIN_SRAM_H__
-
-extern void *l1sram_alloc(size_t);
-
-#endif
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
deleted file mode 100644
index b59cd7c..0000000
--- a/arch/blackfin/mm/init.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/gfp.h>
-#include <linux/swap.h>
-#include <linux/bootmem.h>
-#include <linux/uaccess.h>
-#include <linux/export.h>
-#include <asm/bfin-global.h>
-#include <asm/pda.h>
-#include <asm/cplbinit.h>
-#include <asm/early_printk.h>
-#include "blackfin_sram.h"
-
-/*
- * ZERO_PAGE is a special page that is used for zero-initialized data and COW.
- * Let the bss do its zero-init magic so we don't have to do it ourselves.
- */
-char empty_zero_page[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
-EXPORT_SYMBOL(empty_zero_page);
-
-#ifndef CONFIG_EXCEPTION_L1_SCRATCH
-#if defined CONFIG_SYSCALL_TAB_L1
-__attribute__((l1_data))
-#endif
-static unsigned long exception_stack[NR_CPUS][1024];
-#endif
-
-struct blackfin_pda cpu_pda[NR_CPUS];
-EXPORT_SYMBOL(cpu_pda);
-
-/*
- * paging_init() continues the virtual memory environment setup which
- * was begun by the code in arch/head.S.
- * The parameters are pointers to where to stick the starting and ending
- * addresses of available kernel virtual memory.
- */
-void __init paging_init(void)
-{
- /*
- * make sure start_mem is page aligned, otherwise bootmem and
- * page_alloc get different views of the world
- */
- unsigned long end_mem = memory_end & PAGE_MASK;
-
- unsigned long zones_size[MAX_NR_ZONES] = {
- [0] = 0,
- [ZONE_DMA] = (end_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> PAGE_SHIFT,
- [ZONE_NORMAL] = 0,
-#ifdef CONFIG_HIGHMEM
- [ZONE_HIGHMEM] = 0,
-#endif
- };
-
- /* Set up SFC/DFC registers (user data space) */
- set_fs(KERNEL_DS);
-
- pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
- PAGE_ALIGN(memory_start), end_mem);
- free_area_init_node(0, zones_size,
- CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT, NULL);
-}
-
-asmlinkage void __init init_pda(void)
-{
- unsigned int cpu = raw_smp_processor_id();
-
- early_shadow_stamp();
-
- /* Initialize the PDA fields holding references to other parts
- of the memory. The content of such memory is still
- undefined at the time of the call, we are only setting up
- valid pointers to it. */
- memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu]));
-
-#ifdef CONFIG_EXCEPTION_L1_SCRATCH
- cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \
- L1_SCRATCH_LENGTH);
-#else
- cpu_pda[cpu].ex_stack = exception_stack[cpu + 1];
-#endif
-
-#ifdef CONFIG_SMP
- cpu_pda[cpu].imask = 0x1f;
-#endif
-}
-
-void __init mem_init(void)
-{
- char buf[64];
-
- high_memory = (void *)(memory_end & PAGE_MASK);
- max_mapnr = MAP_NR(high_memory);
- printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", max_mapnr);
-
- /* This will put all low memory onto the freelists. */
- free_all_bootmem();
-
- snprintf(buf, sizeof(buf) - 1, "%uK DMA", DMA_UNCACHED_REGION >> 10);
- mem_init_print_info(buf);
-}
-
-#ifdef CONFIG_BLK_DEV_INITRD
-void __init free_initrd_mem(unsigned long start, unsigned long end)
-{
-#ifndef CONFIG_MPU
- free_reserved_area((void *)start, (void *)end, -1, "initrd");
-#endif
-}
-#endif
-
-void __ref free_initmem(void)
-{
-#if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU
- free_initmem_default(-1);
- if (memory_start == (unsigned long)(&__init_end))
- memory_start = (unsigned long)(&__init_begin);
-#endif
-}
diff --git a/arch/blackfin/mm/isram-driver.c b/arch/blackfin/mm/isram-driver.c
deleted file mode 100644
index aaa1e64..0000000
--- a/arch/blackfin/mm/isram-driver.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Instruction SRAM accessor functions for the Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#define pr_fmt(fmt) "isram: " fmt
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-/*
- * IMPORTANT WARNING ABOUT THESE FUNCTIONS
- *
- * The emulator will not function correctly if a write command is left in
- * ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
- * the emulator. To avoid such problems, ensure that both ITEST_COMMAND
- * and DTEST_COMMAND are zero when exiting these functions.
- */
-
-
-/*
- * On the Blackfin, L1 instruction sram (which operates at core speeds) can not
- * be accessed by a normal core load, so we need to go through a few hoops to
- * read/write it.
- * To try to make it easier - we export a memcpy interface, where either src or
- * dest can be in this special L1 memory area.
- * The low level read/write functions should not be exposed to the rest of the
- * kernel, since they operate on 64-bit data, and need specific address alignment
- */
-
-static DEFINE_SPINLOCK(dtest_lock);
-
-/* Takes a void pointer */
-#define IADDR2DTEST(x) \
- ({ unsigned long __addr = (unsigned long)(x); \
- ((__addr & (1 << 11)) << (26 - 11)) | /* addr bit 11 (Way0/Way1) */ \
- (1 << 24) | /* instruction access = 1 */ \
- ((__addr & (1 << 15)) << (23 - 15)) | /* addr bit 15 (Data Bank) */ \
- ((__addr & (3 << 12)) << (16 - 12)) | /* addr bits 13:12 (Subbank) */ \
- (__addr & 0x47F8) | /* addr bits 14 & 10:3 */ \
- (1 << 2); /* data array = 1 */ \
- })
-
-/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
-#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
-
-/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
-#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
-
-static void isram_write(const void *addr, uint64_t data)
-{
- uint32_t cmd;
- unsigned long flags;
-
- if (unlikely(addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH)))
- return;
-
- cmd = IADDR2DTEST(addr) | 2; /* write */
-
- /*
- * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
- * While in exception context - atomicity is guaranteed or double fault
- */
- spin_lock_irqsave(&dtest_lock, flags);
-
- bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
- bfin_write_DTEST_DATA1(data >> 32);
-
- /* use the builtin, since interrupts are already turned off */
- __builtin_bfin_csync();
- bfin_write_DTEST_COMMAND(cmd);
- __builtin_bfin_csync();
-
- bfin_write_DTEST_COMMAND(0);
- __builtin_bfin_csync();
-
- spin_unlock_irqrestore(&dtest_lock, flags);
-}
-
-static uint64_t isram_read(const void *addr)
-{
- uint32_t cmd;
- unsigned long flags;
- uint64_t ret;
-
- if (unlikely(addr > (void *)(L1_CODE_START + L1_CODE_LENGTH)))
- return 0;
-
- cmd = IADDR2DTEST(addr) | 0; /* read */
-
- /*
- * Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
- * While in exception context - atomicity is guaranteed or double fault
- */
- spin_lock_irqsave(&dtest_lock, flags);
- /* use the builtin, since interrupts are already turned off */
- __builtin_bfin_csync();
- bfin_write_DTEST_COMMAND(cmd);
- __builtin_bfin_csync();
- ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);
-
- bfin_write_DTEST_COMMAND(0);
- __builtin_bfin_csync();
- spin_unlock_irqrestore(&dtest_lock, flags);
-
- return ret;
-}
-
-static bool isram_check_addr(const void *addr, size_t n)
-{
- if ((addr >= (void *)L1_CODE_START) &&
- (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
- if (unlikely((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
- show_stack(NULL, NULL);
- pr_err("copy involving %p length (%zu) too long\n", addr, n);
- }
- return true;
- }
- return false;
-}
-
-/*
- * The isram_memcpy() function copies n bytes from memory area src to memory area dest.
- * The isram_memcpy() function returns a pointer to dest.
- * Either dest or src can be in L1 instruction sram.
- */
-void *isram_memcpy(void *dest, const void *src, size_t n)
-{
- uint64_t data_in = 0, data_out = 0;
- size_t count;
- bool dest_in_l1, src_in_l1, need_data, put_data;
- unsigned char byte, *src_byte, *dest_byte;
-
- src_byte = (unsigned char *)src;
- dest_byte = (unsigned char *)dest;
-
- dest_in_l1 = isram_check_addr(dest, n);
- src_in_l1 = isram_check_addr(src, n);
-
- need_data = true;
- put_data = true;
- for (count = 0; count < n; count++) {
- if (src_in_l1) {
- if (need_data) {
- data_in = isram_read(src + count);
- need_data = false;
- }
-
- if (ADDR2LAST(src + count))
- need_data = true;
-
- byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);
-
- } else {
- /* src is in L2 or L3 - so just dereference*/
- byte = src_byte[count];
- }
-
- if (dest_in_l1) {
- if (put_data) {
- data_out = isram_read(dest + count);
- put_data = false;
- }
-
- data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
- data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count));
-
- if (ADDR2LAST(dest + count)) {
- put_data = true;
- isram_write(dest + count, data_out);
- }
- } else {
- /* dest in L2 or L3 - so just dereference */
- dest_byte[count] = byte;
- }
- }
-
- /* make sure we dump the last byte if necessary */
- if (dest_in_l1 && !put_data)
- isram_write(dest + count, data_out);
-
- return dest;
-}
-EXPORT_SYMBOL(isram_memcpy);
-
-#ifdef CONFIG_BFIN_ISRAM_SELF_TEST
-
-static int test_len = 0x20000;
-
-static __init void hex_dump(unsigned char *buf, int len)
-{
- while (len--)
- pr_cont("%02x", *buf++);
-}
-
-static __init int isram_read_test(char *sdram, void *l1inst)
-{
- int i, ret = 0;
- uint64_t data1, data2;
-
- pr_info("INFO: running isram_read tests\n");
-
- /* setup some different data to play with */
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
- dma_memcpy(l1inst, sdram, test_len);
-
- /* make sure we can read the L1 inst */
- for (i = 0; i < test_len; i += sizeof(uint64_t)) {
- data1 = isram_read(l1inst + i);
- memcpy(&data2, sdram + i, sizeof(data2));
- if (data1 != data2) {
- pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
- l1inst + i, data1, data2);
- ++ret;
- }
- }
-
- return ret;
-}
-
-static __init int isram_write_test(char *sdram, void *l1inst)
-{
- int i, ret = 0;
- uint64_t data1, data2;
-
- pr_info("INFO: running isram_write tests\n");
-
- /* setup some different data to play with */
- memset(sdram, 0, test_len * 2);
- dma_memcpy(l1inst, sdram, test_len);
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
-
- /* make sure we can write the L1 inst */
- for (i = 0; i < test_len; i += sizeof(uint64_t)) {
- memcpy(&data1, sdram + i, sizeof(data1));
- isram_write(l1inst + i, data1);
- data2 = isram_read(l1inst + i);
- if (data1 != data2) {
- pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
- l1inst + i, data1, data2);
- ++ret;
- }
- }
-
- dma_memcpy(sdram + test_len, l1inst, test_len);
- if (memcmp(sdram, sdram + test_len, test_len)) {
- pr_err("FAIL: isram_write() did not work properly\n");
- ++ret;
- }
-
- return ret;
-}
-
-static __init int
-_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy,
- void *(*fmemcpy)(void *, const void *, size_t))
-{
- memset(sdram, pattern, test_len);
- fmemcpy(l1inst, sdram, test_len);
- fmemcpy(sdram + test_len, l1inst, test_len);
- if (memcmp(sdram, sdram + test_len, test_len)) {
- pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
- smemcpy, l1inst, sdram, test_len, pattern);
- return 1;
- }
- return 0;
-}
-#define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d)
-
-static __init int isram_memcpy_test(char *sdram, void *l1inst)
-{
- int i, j, thisret, ret = 0;
-
- /* check broad isram_memcpy() */
- pr_info("INFO: running broad isram_memcpy tests\n");
- for (i = 0xf; i >= 0; --i)
- ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy);
-
- /* check read of small, unaligned, and hardware 64bit limits */
- pr_info("INFO: running isram_memcpy (read) tests\n");
-
- /* setup some different data to play with */
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
- dma_memcpy(l1inst, sdram, test_len);
-
- thisret = 0;
- for (i = 0; i < test_len - 32; ++i) {
- unsigned char cmp[32];
- for (j = 1; j <= 32; ++j) {
- memset(cmp, 0, sizeof(cmp));
- isram_memcpy(cmp, l1inst + i, j);
- if (memcmp(cmp, sdram + i, j)) {
- pr_err("FAIL: %p:", l1inst + 1);
- hex_dump(cmp, j);
- pr_cont(" SDRAM:");
- hex_dump(sdram + i, j);
- pr_cont("\n");
- if (++thisret > 20) {
- pr_err("FAIL: skipping remaining series\n");
- i = test_len;
- break;
- }
- }
- }
- }
- ret += thisret;
-
- /* check write of small, unaligned, and hardware 64bit limits */
- pr_info("INFO: running isram_memcpy (write) tests\n");
-
- memset(sdram + test_len, 0, test_len);
- dma_memcpy(l1inst, sdram + test_len, test_len);
-
- thisret = 0;
- for (i = 0; i < test_len - 32; ++i) {
- unsigned char cmp[32];
- for (j = 1; j <= 32; ++j) {
- isram_memcpy(l1inst + i, sdram + i, j);
- dma_memcpy(cmp, l1inst + i, j);
- if (memcmp(cmp, sdram + i, j)) {
- pr_err("FAIL: %p:", l1inst + i);
- hex_dump(cmp, j);
- pr_cont(" SDRAM:");
- hex_dump(sdram + i, j);
- pr_cont("\n");
- if (++thisret > 20) {
- pr_err("FAIL: skipping remaining series\n");
- i = test_len;
- break;
- }
- }
- }
- }
- ret += thisret;
-
- return ret;
-}
-
-static __init int isram_test_init(void)
-{
- int ret;
- char *sdram;
- void *l1inst;
-
- /* Try to test as much of L1SRAM as possible */
- while (test_len) {
- test_len >>= 1;
- l1inst = l1_inst_sram_alloc(test_len);
- if (l1inst)
- break;
- }
- if (!l1inst) {
- pr_warning("SKIP: could not allocate L1 inst\n");
- return 0;
- }
- pr_info("INFO: testing %#x bytes (%p - %p)\n",
- test_len, l1inst, l1inst + test_len);
-
- sdram = kmalloc(test_len * 2, GFP_KERNEL);
- if (!sdram) {
- sram_free(l1inst);
- pr_warning("SKIP: could not allocate sdram\n");
- return 0;
- }
-
- /* sanity check initial L1 inst state */
- ret = 1;
- pr_info("INFO: running initial dma_memcpy checks %p\n", sdram);
- if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
- goto abort;
- if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
- goto abort;
-
- ret = 0;
- ret += isram_read_test(sdram, l1inst);
- ret += isram_write_test(sdram, l1inst);
- ret += isram_memcpy_test(sdram, l1inst);
-
- abort:
- sram_free(l1inst);
- kfree(sdram);
-
- if (ret)
- return -EIO;
-
- pr_info("PASS: all tests worked !\n");
- return 0;
-}
-late_initcall(isram_test_init);
-
-static __exit void isram_test_exit(void)
-{
- /* stub to allow unloading */
-}
-module_exit(isram_test_exit);
-
-#endif
diff --git a/arch/blackfin/mm/maccess.c b/arch/blackfin/mm/maccess.c
deleted file mode 100644
index e253211..0000000
--- a/arch/blackfin/mm/maccess.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * safe read and write memory routines callable while atomic
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/uaccess.h>
-#include <asm/dma.h>
-
-static int validate_memory_access_address(unsigned long addr, int size)
-{
- if (size < 0 || addr == 0)
- return -EFAULT;
- return bfin_mem_access_type(addr, size);
-}
-
-long probe_kernel_read(void *dst, const void *src, size_t size)
-{
- unsigned long lsrc = (unsigned long)src;
- int mem_type;
-
- mem_type = validate_memory_access_address(lsrc, size);
- if (mem_type < 0)
- return mem_type;
-
- if (lsrc >= SYSMMR_BASE) {
- if (size == 2 && lsrc % 2 == 0) {
- u16 mmr = bfin_read16(src);
- memcpy(dst, &mmr, sizeof(mmr));
- return 0;
- } else if (size == 4 && lsrc % 4 == 0) {
- u32 mmr = bfin_read32(src);
- memcpy(dst, &mmr, sizeof(mmr));
- return 0;
- }
- } else {
- switch (mem_type) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- return __probe_kernel_read(dst, src, size);
- /* XXX: should support IDMA here with SMP */
- case BFIN_MEM_ACCESS_DMA:
- if (dma_memcpy(dst, src, size))
- return 0;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(dst, src, size))
- return 0;
- break;
- }
- }
-
- return -EFAULT;
-}
-
-long probe_kernel_write(void *dst, const void *src, size_t size)
-{
- unsigned long ldst = (unsigned long)dst;
- int mem_type;
-
- mem_type = validate_memory_access_address(ldst, size);
- if (mem_type < 0)
- return mem_type;
-
- if (ldst >= SYSMMR_BASE) {
- if (size == 2 && ldst % 2 == 0) {
- u16 mmr;
- memcpy(&mmr, src, sizeof(mmr));
- bfin_write16(dst, mmr);
- return 0;
- } else if (size == 4 && ldst % 4 == 0) {
- u32 mmr;
- memcpy(&mmr, src, sizeof(mmr));
- bfin_write32(dst, mmr);
- return 0;
- }
- } else {
- switch (mem_type) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- return __probe_kernel_write(dst, src, size);
- /* XXX: should support IDMA here with SMP */
- case BFIN_MEM_ACCESS_DMA:
- if (dma_memcpy(dst, src, size))
- return 0;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(dst, src, size))
- return 0;
- break;
- }
- }
-
- return -EFAULT;
-}
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
deleted file mode 100644
index d2a96c2..0000000
--- a/arch/blackfin/mm/sram-alloc.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * SRAM allocator for Blackfin on-chip memory
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/miscdevice.h>
-#include <linux/ioport.h>
-#include <linux/fcntl.h>
-#include <linux/init.h>
-#include <linux/poll.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/spinlock.h>
-#include <linux/rtc.h>
-#include <linux/slab.h>
-#include <linux/mm_types.h>
-
-#include <asm/blackfin.h>
-#include <asm/mem_map.h>
-#include "blackfin_sram.h"
-
-/* the data structure for L1 scratchpad and DATA SRAM */
-struct sram_piece {
- void *paddr;
- int size;
- pid_t pid;
- struct sram_piece *next;
-};
-
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1sram_lock);
-static DEFINE_PER_CPU(struct sram_piece, free_l1_ssram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_ssram_head);
-
-#if L1_DATA_A_LENGTH != 0
-static DEFINE_PER_CPU(struct sram_piece, free_l1_data_A_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_data_A_sram_head);
-#endif
-
-#if L1_DATA_B_LENGTH != 0
-static DEFINE_PER_CPU(struct sram_piece, free_l1_data_B_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_data_B_sram_head);
-#endif
-
-#if L1_DATA_A_LENGTH || L1_DATA_B_LENGTH
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_data_sram_lock);
-#endif
-
-#if L1_CODE_LENGTH != 0
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_inst_sram_lock);
-static DEFINE_PER_CPU(struct sram_piece, free_l1_inst_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_inst_sram_head);
-#endif
-
-#if L2_LENGTH != 0
-static spinlock_t l2_sram_lock ____cacheline_aligned_in_smp;
-static struct sram_piece free_l2_sram_head, used_l2_sram_head;
-#endif
-
-static struct kmem_cache *sram_piece_cache;
-
-/* L1 Scratchpad SRAM initialization function */
-static void __init l1sram_init(void)
-{
- unsigned int cpu;
- unsigned long reserve;
-
-#ifdef CONFIG_SMP
- reserve = 0;
-#else
- reserve = sizeof(struct l1_scratch_task_info);
-#endif
-
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_ssram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_ssram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize Scratchpad data SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_ssram_head, cpu).next->paddr = (void *)get_l1_scratch_start_cpu(cpu) + reserve;
- per_cpu(free_l1_ssram_head, cpu).next->size = L1_SCRATCH_LENGTH - reserve;
- per_cpu(free_l1_ssram_head, cpu).next->pid = 0;
- per_cpu(free_l1_ssram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_ssram_head, cpu).next = NULL;
-
- /* mutex initialize */
- spin_lock_init(&per_cpu(l1sram_lock, cpu));
- printk(KERN_INFO "Blackfin Scratchpad data SRAM: %d KB\n",
- L1_SCRATCH_LENGTH >> 10);
- }
-}
-
-static void __init l1_data_sram_init(void)
-{
-#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0
- unsigned int cpu;
-#endif
-#if L1_DATA_A_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_data_A_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_data_A_sram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize L1 Data A SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_data_A_sram_head, cpu).next->paddr =
- (void *)get_l1_data_a_start_cpu(cpu) + (_ebss_l1 - _sdata_l1);
- per_cpu(free_l1_data_A_sram_head, cpu).next->size =
- L1_DATA_A_LENGTH - (_ebss_l1 - _sdata_l1);
- per_cpu(free_l1_data_A_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_data_A_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_data_A_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Data A SRAM: %d KB (%d KB free)\n",
- L1_DATA_A_LENGTH >> 10,
- per_cpu(free_l1_data_A_sram_head, cpu).next->size >> 10);
- }
-#endif
-#if L1_DATA_B_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_data_B_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_data_B_sram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize L1 Data B SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_data_B_sram_head, cpu).next->paddr =
- (void *)get_l1_data_b_start_cpu(cpu) + (_ebss_b_l1 - _sdata_b_l1);
- per_cpu(free_l1_data_B_sram_head, cpu).next->size =
- L1_DATA_B_LENGTH - (_ebss_b_l1 - _sdata_b_l1);
- per_cpu(free_l1_data_B_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_data_B_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_data_B_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Data B SRAM: %d KB (%d KB free)\n",
- L1_DATA_B_LENGTH >> 10,
- per_cpu(free_l1_data_B_sram_head, cpu).next->size >> 10);
- /* mutex initialize */
- }
-#endif
-
-#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
- spin_lock_init(&per_cpu(l1_data_sram_lock, cpu));
-#endif
-}
-
-static void __init l1_inst_sram_init(void)
-{
-#if L1_CODE_LENGTH != 0
- unsigned int cpu;
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_inst_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_inst_sram_head, cpu).next) {
- printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n");
- return;
- }
-
- per_cpu(free_l1_inst_sram_head, cpu).next->paddr =
- (void *)get_l1_code_start_cpu(cpu) + (_etext_l1 - _stext_l1);
- per_cpu(free_l1_inst_sram_head, cpu).next->size =
- L1_CODE_LENGTH - (_etext_l1 - _stext_l1);
- per_cpu(free_l1_inst_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_inst_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_inst_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Instruction SRAM: %d KB (%d KB free)\n",
- L1_CODE_LENGTH >> 10,
- per_cpu(free_l1_inst_sram_head, cpu).next->size >> 10);
-
- /* mutex initialize */
- spin_lock_init(&per_cpu(l1_inst_sram_lock, cpu));
- }
-#endif
-}
-
-#ifdef __ADSPBF60x__
-static irqreturn_t l2_ecc_err(int irq, void *dev_id)
-{
- int status;
-
- printk(KERN_ERR "L2 ecc error happened\n");
- status = bfin_read32(L2CTL0_STAT);
- if (status & 0x1)
- printk(KERN_ERR "Core channel error type:0x%x, addr:0x%x\n",
- bfin_read32(L2CTL0_ET0), bfin_read32(L2CTL0_EADDR0));
- if (status & 0x2)
- printk(KERN_ERR "System channel error type:0x%x, addr:0x%x\n",
- bfin_read32(L2CTL0_ET1), bfin_read32(L2CTL0_EADDR1));
-
- status = status >> 8;
- if (status)
- printk(KERN_ERR "L2 Bank%d error, addr:0x%x\n",
- status, bfin_read32(L2CTL0_ERRADDR0 + status));
-
- panic("L2 Ecc error");
- return IRQ_HANDLED;
-}
-#endif
-
-static void __init l2_sram_init(void)
-{
-#if L2_LENGTH != 0
-
-#ifdef __ADSPBF60x__
- int ret;
-
- ret = request_irq(IRQ_L2CTL0_ECC_ERR, l2_ecc_err, 0, "l2-ecc-err",
- NULL);
- if (unlikely(ret < 0)) {
- printk(KERN_INFO "Fail to request l2 ecc error interrupt");
- return;
- }
-#endif
-
- free_l2_sram_head.next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!free_l2_sram_head.next) {
- printk(KERN_INFO "Fail to initialize L2 SRAM.\n");
- return;
- }
-
- free_l2_sram_head.next->paddr =
- (void *)L2_START + (_ebss_l2 - _stext_l2);
- free_l2_sram_head.next->size =
- L2_LENGTH - (_ebss_l2 - _stext_l2);
- free_l2_sram_head.next->pid = 0;
- free_l2_sram_head.next->next = NULL;
-
- used_l2_sram_head.next = NULL;
-
- printk(KERN_INFO "Blackfin L2 SRAM: %d KB (%d KB free)\n",
- L2_LENGTH >> 10,
- free_l2_sram_head.next->size >> 10);
-
- /* mutex initialize */
- spin_lock_init(&l2_sram_lock);
-#endif
-}
-
-static int __init bfin_sram_init(void)
-{
- sram_piece_cache = kmem_cache_create("sram_piece_cache",
- sizeof(struct sram_piece),
- 0, SLAB_PANIC, NULL);
-
- l1sram_init();
- l1_data_sram_init();
- l1_inst_sram_init();
- l2_sram_init();
-
- return 0;
-}
-pure_initcall(bfin_sram_init);
-
-/* SRAM allocate function */
-static void *_sram_alloc(size_t size, struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot, *plast, *pavail;
-
- if (size <= 0 || !pfree_head || !pused_head)
- return NULL;
-
- /* Align the size */
- size = (size + 3) & ~3;
-
- pslot = pfree_head->next;
- plast = pfree_head;
-
- /* search an available piece slot */
- while (pslot != NULL && size > pslot->size) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (!pslot)
- return NULL;
-
- if (pslot->size == size) {
- plast->next = pslot->next;
- pavail = pslot;
- } else {
- /* use atomic so our L1 allocator can be used atomically */
- pavail = kmem_cache_alloc(sram_piece_cache, GFP_ATOMIC);
-
- if (!pavail)
- return NULL;
-
- pavail->paddr = pslot->paddr;
- pavail->size = size;
- pslot->paddr += size;
- pslot->size -= size;
- }
-
- pavail->pid = current->pid;
-
- pslot = pused_head->next;
- plast = pused_head;
-
- /* insert new piece into used piece list !!! */
- while (pslot != NULL && pavail->paddr < pslot->paddr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- pavail->next = pslot;
- plast->next = pavail;
-
- return pavail->paddr;
-}
-
-/* Allocate the largest available block. */
-static void *_sram_alloc_max(struct sram_piece *pfree_head,
- struct sram_piece *pused_head,
- unsigned long *psize)
-{
- struct sram_piece *pslot, *pmax;
-
- if (!pfree_head || !pused_head)
- return NULL;
-
- pmax = pslot = pfree_head->next;
-
- /* search an available piece slot */
- while (pslot != NULL) {
- if (pslot->size > pmax->size)
- pmax = pslot;
- pslot = pslot->next;
- }
-
- if (!pmax)
- return NULL;
-
- *psize = pmax->size;
-
- return _sram_alloc(*psize, pfree_head, pused_head);
-}
-
-/* SRAM free function */
-static int _sram_free(const void *addr,
- struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot, *plast, *pavail;
-
- if (!pfree_head || !pused_head)
- return -1;
-
- /* search the relevant memory slot */
- pslot = pused_head->next;
- plast = pused_head;
-
- /* search an available piece slot */
- while (pslot != NULL && pslot->paddr != addr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (!pslot)
- return -1;
-
- plast->next = pslot->next;
- pavail = pslot;
- pavail->pid = 0;
-
- /* insert free pieces back to the free list */
- pslot = pfree_head->next;
- plast = pfree_head;
-
- while (pslot != NULL && addr > pslot->paddr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (plast != pfree_head && plast->paddr + plast->size == pavail->paddr) {
- plast->size += pavail->size;
- kmem_cache_free(sram_piece_cache, pavail);
- } else {
- pavail->next = plast->next;
- plast->next = pavail;
- plast = pavail;
- }
-
- if (pslot && plast->paddr + plast->size == pslot->paddr) {
- plast->size += pslot->size;
- plast->next = pslot->next;
- kmem_cache_free(sram_piece_cache, pslot);
- }
-
- return 0;
-}
-
-int sram_free(const void *addr)
-{
-
-#if L1_CODE_LENGTH != 0
- if (addr >= (void *)get_l1_code_start()
- && addr < (void *)(get_l1_code_start() + L1_CODE_LENGTH))
- return l1_inst_sram_free(addr);
- else
-#endif
-#if L1_DATA_A_LENGTH != 0
- if (addr >= (void *)get_l1_data_a_start()
- && addr < (void *)(get_l1_data_a_start() + L1_DATA_A_LENGTH))
- return l1_data_A_sram_free(addr);
- else
-#endif
-#if L1_DATA_B_LENGTH != 0
- if (addr >= (void *)get_l1_data_b_start()
- && addr < (void *)(get_l1_data_b_start() + L1_DATA_B_LENGTH))
- return l1_data_B_sram_free(addr);
- else
-#endif
-#if L2_LENGTH != 0
- if (addr >= (void *)L2_START
- && addr < (void *)(L2_START + L2_LENGTH))
- return l2_sram_free(addr);
- else
-#endif
- return -1;
-}
-EXPORT_SYMBOL(sram_free);
-
-void *l1_data_A_sram_alloc(size_t size)
-{
-#if L1_DATA_A_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_data_A_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_data_A_sram_alloc);
-
-int l1_data_A_sram_free(const void *addr)
-{
-#if L1_DATA_A_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_data_A_sram_free);
-
-void *l1_data_B_sram_alloc(size_t size)
-{
-#if L1_DATA_B_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_data_B_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_data_B_sram_alloc);
-
-int l1_data_B_sram_free(const void *addr)
-{
-#if L1_DATA_B_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_data_B_sram_free);
-
-void *l1_data_sram_alloc(size_t size)
-{
- void *addr = l1_data_A_sram_alloc(size);
-
- if (!addr)
- addr = l1_data_B_sram_alloc(size);
-
- return addr;
-}
-EXPORT_SYMBOL(l1_data_sram_alloc);
-
-void *l1_data_sram_zalloc(size_t size)
-{
- void *addr = l1_data_sram_alloc(size);
-
- if (addr)
- memset(addr, 0x00, size);
-
- return addr;
-}
-EXPORT_SYMBOL(l1_data_sram_zalloc);
-
-int l1_data_sram_free(const void *addr)
-{
- int ret;
- ret = l1_data_A_sram_free(addr);
- if (ret == -1)
- ret = l1_data_B_sram_free(addr);
- return ret;
-}
-EXPORT_SYMBOL(l1_data_sram_free);
-
-void *l1_inst_sram_alloc(size_t size)
-{
-#if L1_CODE_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_inst_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_inst_sram_alloc);
-
-int l1_inst_sram_free(const void *addr)
-{
-#if L1_CODE_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_inst_sram_free);
-
-/* L1 Scratchpad memory allocate function */
-void *l1sram_alloc(size_t size)
-{
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return addr;
-}
-
-/* L1 Scratchpad memory allocate function */
-void *l1sram_alloc_max(size_t *psize)
-{
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- addr = _sram_alloc_max(&per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu), psize);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return addr;
-}
-
-/* L1 Scratchpad memory free function */
-int l1sram_free(const void *addr)
-{
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return ret;
-}
-
-void *l2_sram_alloc(size_t size)
-{
-#if L2_LENGTH != 0
- unsigned long flags;
- void *addr;
-
- /* add mutex operation */
- spin_lock_irqsave(&l2_sram_lock, flags);
-
- addr = _sram_alloc(size, &free_l2_sram_head,
- &used_l2_sram_head);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&l2_sram_lock, flags);
-
- pr_debug("Allocated address in l2_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l2_sram_alloc);
-
-void *l2_sram_zalloc(size_t size)
-{
- void *addr = l2_sram_alloc(size);
-
- if (addr)
- memset(addr, 0x00, size);
-
- return addr;
-}
-EXPORT_SYMBOL(l2_sram_zalloc);
-
-int l2_sram_free(const void *addr)
-{
-#if L2_LENGTH != 0
- unsigned long flags;
- int ret;
-
- /* add mutex operation */
- spin_lock_irqsave(&l2_sram_lock, flags);
-
- ret = _sram_free(addr, &free_l2_sram_head,
- &used_l2_sram_head);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&l2_sram_lock, flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l2_sram_free);
-
-int sram_free_with_lsl(const void *addr)
-{
- struct sram_list_struct *lsl, **tmp;
- struct mm_struct *mm = current->mm;
- int ret = -1;
-
- for (tmp = &mm->context.sram_list; *tmp; tmp = &(*tmp)->next)
- if ((*tmp)->addr == addr) {
- lsl = *tmp;
- ret = sram_free(addr);
- *tmp = lsl->next;
- kfree(lsl);
- break;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(sram_free_with_lsl);
-
-/* Allocate memory and keep in L1 SRAM List (lsl) so that the resources are
- * tracked. These are designed for userspace so that when a process exits,
- * we can safely reap their resources.
- */
-void *sram_alloc_with_lsl(size_t size, unsigned long flags)
-{
- void *addr = NULL;
- struct sram_list_struct *lsl = NULL;
- struct mm_struct *mm = current->mm;
-
- lsl = kzalloc(sizeof(struct sram_list_struct), GFP_KERNEL);
- if (!lsl)
- return NULL;
-
- if (flags & L1_INST_SRAM)
- addr = l1_inst_sram_alloc(size);
-
- if (addr == NULL && (flags & L1_DATA_A_SRAM))
- addr = l1_data_A_sram_alloc(size);
-
- if (addr == NULL && (flags & L1_DATA_B_SRAM))
- addr = l1_data_B_sram_alloc(size);
-
- if (addr == NULL && (flags & L2_SRAM))
- addr = l2_sram_alloc(size);
-
- if (addr == NULL) {
- kfree(lsl);
- return NULL;
- }
- lsl->addr = addr;
- lsl->length = size;
- lsl->next = mm->context.sram_list;
- mm->context.sram_list = lsl;
- return addr;
-}
-EXPORT_SYMBOL(sram_alloc_with_lsl);
-
-#ifdef CONFIG_PROC_FS
-/* Once we get a real allocator, we'll throw all of this away.
- * Until then, we need some sort of visibility into the L1 alloc.
- */
-/* Need to keep line of output the same. Currently, that is 44 bytes
- * (including newline).
- */
-static int _sram_proc_show(struct seq_file *m, const char *desc,
- struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot;
-
- if (!pfree_head || !pused_head)
- return -1;
-
- seq_printf(m, "--- SRAM %-14s Size PID State \n", desc);
-
- /* search the relevant memory slot */
- pslot = pused_head->next;
-
- while (pslot != NULL) {
- seq_printf(m, "%p-%p %10i %5i %-10s\n",
- pslot->paddr, pslot->paddr + pslot->size,
- pslot->size, pslot->pid, "ALLOCATED");
-
- pslot = pslot->next;
- }
-
- pslot = pfree_head->next;
-
- while (pslot != NULL) {
- seq_printf(m, "%p-%p %10i %5i %-10s\n",
- pslot->paddr, pslot->paddr + pslot->size,
- pslot->size, pslot->pid, "FREE");
-
- pslot = pslot->next;
- }
-
- return 0;
-}
-static int sram_proc_show(struct seq_file *m, void *v)
-{
- unsigned int cpu;
-
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- if (_sram_proc_show(m, "Scratchpad",
- &per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu)))
- goto not_done;
-#if L1_DATA_A_LENGTH != 0
- if (_sram_proc_show(m, "L1 Data A",
- &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu)))
- goto not_done;
-#endif
-#if L1_DATA_B_LENGTH != 0
- if (_sram_proc_show(m, "L1 Data B",
- &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu)))
- goto not_done;
-#endif
-#if L1_CODE_LENGTH != 0
- if (_sram_proc_show(m, "L1 Instruction",
- &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu)))
- goto not_done;
-#endif
- }
-#if L2_LENGTH != 0
- if (_sram_proc_show(m, "L2", &free_l2_sram_head, &used_l2_sram_head))
- goto not_done;
-#endif
- not_done:
- return 0;
-}
-
-static int sram_proc_open(struct inode *inode, struct file *file)
-{
- return single_open(file, sram_proc_show, NULL);
-}
-
-static const struct file_operations sram_proc_ops = {
- .open = sram_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init sram_proc_init(void)
-{
- struct proc_dir_entry *ptr;
-
- ptr = proc_create("sram", S_IRUGO, NULL, &sram_proc_ops);
- if (!ptr) {
- printk(KERN_WARNING "unable to create /proc/sram\n");
- return -1;
- }
- return 0;
-}
-late_initcall(sram_proc_init);
-#endif
diff --git a/arch/blackfin/oprofile/Makefile b/arch/blackfin/oprofile/Makefile
deleted file mode 100644
index e89e1c9..0000000
--- a/arch/blackfin/oprofile/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/oprofile/Makefile
-#
-
-obj-$(CONFIG_OPROFILE) += oprofile.o
-
-DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \
- oprof.o cpu_buffer.o buffer_sync.o \
- event_buffer.o oprofile_files.o \
- oprofilefs.o oprofile_stats.o \
- timer_int.o )
-
-oprofile-y := $(DRIVER_OBJS) bfin_oprofile.o
diff --git a/arch/blackfin/oprofile/bfin_oprofile.c b/arch/blackfin/oprofile/bfin_oprofile.c
deleted file mode 100644
index c3b9713..0000000
--- a/arch/blackfin/oprofile/bfin_oprofile.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * bfin_oprofile.c - Blackfin oprofile code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/oprofile.h>
-#include <linux/init.h>
-
-int __init oprofile_arch_init(struct oprofile_operations *ops)
-{
- return -1;
-}
-
-void oprofile_arch_exit(void)
-{
-}
diff --git a/fs/Kconfig.binfmt b/fs/Kconfig.binfmt
index 58c2bbd..dcb770f 100644
--- a/fs/Kconfig.binfmt
+++ b/fs/Kconfig.binfmt
@@ -35,7 +35,7 @@ config ARCH_BINFMT_ELF_STATE
config BINFMT_ELF_FDPIC
bool "Kernel support for FDPIC ELF binaries"
default y if !BINFMT_ELF
- depends on (ARM || FRV || BLACKFIN || (SUPERH32 && !MMU) || C6X)
+ depends on (ARM || FRV || (SUPERH32 && !MMU) || C6X)
select ELFCORE
help
ELF FDPIC binaries are based on ELF, but allow the individual load
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 5172ad0..1cbf78b 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -29,7 +29,6 @@ enum cpuhp_state {
CPUHP_PERF_PREPARE,
CPUHP_PERF_X86_PREPARE,
CPUHP_PERF_X86_AMD_UNCORE_PREP,
- CPUHP_PERF_BFIN,
CPUHP_PERF_POWER,
CPUHP_PERF_SUPERH,
CPUHP_X86_HPET_DEAD,
diff --git a/include/uapi/asm-generic/siginfo.h b/include/uapi/asm-generic/siginfo.h
index 99c902e..43bd689 100644
--- a/include/uapi/asm-generic/siginfo.h
+++ b/include/uapi/asm-generic/siginfo.h
@@ -179,24 +179,13 @@ typedef struct siginfo {
* SIGILL si_codes
*/
#define ILL_ILLOPC 1 /* illegal opcode */
-#ifdef __bfin__
-# define ILL_ILLPARAOP 2 /* illegal opcode combine */
-#endif
#define ILL_ILLOPN 2 /* illegal operand */
#define ILL_ILLADR 3 /* illegal addressing mode */
#define ILL_ILLTRP 4 /* illegal trap */
-#ifdef __bfin__
-# define ILL_ILLEXCPT 4 /* unrecoverable exception */
-#endif
#define ILL_PRVOPC 5 /* privileged opcode */
#define ILL_PRVREG 6 /* privileged register */
#define ILL_COPROC 7 /* coprocessor error */
#define ILL_BADSTK 8 /* internal stack error */
-#ifdef __bfin__
-# define ILL_CPLB_VI 9 /* D/I CPLB protect violation */
-# define ILL_CPLB_MISS 10 /* D/I CPLB miss */
-# define ILL_CPLB_MULHIT 11 /* D/I CPLB multiple hit */
-#endif
#ifdef __tile__
# define ILL_DBLFLT 9 /* double fault */
# define ILL_HARDWALL 10 /* user networks hardwall violation */
@@ -236,11 +225,7 @@ typedef struct siginfo {
*/
#define SEGV_MAPERR 1 /* address not mapped to object */
#define SEGV_ACCERR 2 /* invalid permissions for mapped object */
-#ifdef __bfin__
-# define SEGV_STACKFLOW 3 /* stack overflow */
-#else
-# define SEGV_BNDERR 3 /* failed address bound checks */
-#endif
+#define SEGV_BNDERR 3 /* failed address bound checks */
#ifdef __ia64__
# define __SEGV_PSTKOVF 4 /* paragraph stack overflow */
#else
@@ -254,12 +239,8 @@ typedef struct siginfo {
#define BUS_ADRALN 1 /* invalid address alignment */
#define BUS_ADRERR 2 /* non-existent physical address */
#define BUS_OBJERR 3 /* object specific hardware error */
-#ifdef __bfin__
-# define BUS_OPFETCH 4 /* error from instruction fetch */
-#else
/* hardware memory error consumed on a machine check: action required */
-# define BUS_MCEERR_AR 4
-#endif
+#define BUS_MCEERR_AR 4
/* hardware memory error detected in process but not consumed: action optional*/
#define BUS_MCEERR_AO 5
#define NSIGBUS 5
@@ -271,12 +252,6 @@ typedef struct siginfo {
#define TRAP_TRACE 2 /* process trace trap */
#define TRAP_BRANCH 3 /* process taken branch trap */
#define TRAP_HWBKPT 4 /* hardware breakpoint/watchpoint */
-#ifdef __bfin__
-# define TRAP_STEP 1 /* single-step breakpoint */
-# define TRAP_TRACEFLOW 2 /* trace buffer overflow */
-# define TRAP_WATCHPT 3 /* watchpoint match */
-# define TRAP_ILLTRAP 4 /* illegal trap */
-#endif
#define NSIGTRAP 4
/*
diff --git a/include/uapi/linux/elf-em.h b/include/uapi/linux/elf-em.h
index 31aa101..37a8057 100644
--- a/include/uapi/linux/elf-em.h
+++ b/include/uapi/linux/elf-em.h
@@ -34,7 +34,6 @@
#define EM_M32R 88 /* Renesas M32R */
#define EM_MN10300 89 /* Panasonic/MEI MN10300, AM33 */
#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
-#define EM_BLACKFIN 106 /* ADI Blackfin Processor */
#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */
#define EM_TI_C6000 140 /* TI C6X DSPs */
#define EM_AARCH64 183 /* ARM 64 bit */
diff --git a/init/Kconfig b/init/Kconfig
index e37f4b2..98c5ff5 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1108,7 +1108,7 @@ config MULTIUSER
config SGETMASK_SYSCALL
bool "sgetmask/ssetmask syscalls support" if EXPERT
- def_bool PARISC || MN10300 || BLACKFIN || M68K || PPC || MIPS || X86 || SPARC || CRIS || MICROBLAZE || SUPERH
+ def_bool PARISC || MN10300 || M68K || PPC || MIPS || X86 || SPARC || CRIS || MICROBLAZE || SUPERH
---help---
sys_sgetmask and sys_ssetmask are obsolete system calls
no longer supported in libc but still enabled by default in some
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 64155e3..4174635 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -356,7 +356,7 @@ config FRAME_POINTER
bool "Compile the kernel with frame pointers"
depends on DEBUG_KERNEL && \
(CRIS || M68K || FRV || UML || \
- SUPERH || BLACKFIN || MN10300 || METAG) || \
+ SUPERH || MN10300 || METAG) || \
ARCH_WANT_FRAME_POINTERS
default y if (DEBUG_INFO && UML) || ARCH_WANT_FRAME_POINTERS
help
diff --git a/lib/test_user_copy.c b/lib/test_user_copy.c
index 4621db8..7c58ebf 100644
--- a/lib/test_user_copy.c
+++ b/lib/test_user_copy.c
@@ -31,7 +31,6 @@
* their capability at compile-time, we just have to opt-out certain archs.
*/
#if BITS_PER_LONG == 64 || (!(defined(CONFIG_ARM) && !defined(MMU)) && \
- !defined(CONFIG_BLACKFIN) && \
!defined(CONFIG_M32R) && \
!defined(CONFIG_M68K) && \
!defined(CONFIG_MICROBLAZE) && \
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 02/28] net: Remove Blackfin Ethernet support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 03/28] media: Remove Blackfin media support Aaron Wu
` (25 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin Ethernet support
---
drivers/net/ethernet/Kconfig | 1 -
drivers/net/ethernet/Makefile | 1 -
drivers/net/ethernet/adi/Kconfig | 66 --
drivers/net/ethernet/adi/Makefile | 5 -
drivers/net/ethernet/adi/bfin_mac.c | 1881 ----------------------------------
drivers/net/ethernet/adi/bfin_mac.h | 104 --
drivers/net/ethernet/davicom/Kconfig | 2 +-
drivers/net/ethernet/smsc/Kconfig | 4 +-
include/linux/bfin_mac.h | 30 -
9 files changed, 3 insertions(+), 2091 deletions(-)
delete mode 100644 drivers/net/ethernet/adi/Kconfig
delete mode 100644 drivers/net/ethernet/adi/Makefile
delete mode 100644 drivers/net/ethernet/adi/bfin_mac.c
delete mode 100644 drivers/net/ethernet/adi/bfin_mac.h
delete mode 100644 include/linux/bfin_mac.h
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index b6cf4b6..b9b673d 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -34,7 +34,6 @@ source "drivers/net/ethernet/arc/Kconfig"
source "drivers/net/ethernet/atheros/Kconfig"
source "drivers/net/ethernet/aurora/Kconfig"
source "drivers/net/ethernet/cadence/Kconfig"
-source "drivers/net/ethernet/adi/Kconfig"
source "drivers/net/ethernet/broadcom/Kconfig"
source "drivers/net/ethernet/brocade/Kconfig"
source "drivers/net/ethernet/calxeda/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 3cdf01e..c557407 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_NET_VENDOR_ARC) += arc/
obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
obj-$(CONFIG_NET_VENDOR_AURORA) += aurora/
obj-$(CONFIG_NET_CADENCE) += cadence/
-obj-$(CONFIG_NET_BFIN) += adi/
obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/
obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/
obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/
diff --git a/drivers/net/ethernet/adi/Kconfig b/drivers/net/ethernet/adi/Kconfig
deleted file mode 100644
index 98cc8f5..0000000
--- a/drivers/net/ethernet/adi/Kconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-#
-# Blackfin device configuration
-#
-
-config NET_BFIN
- bool "Blackfin devices"
- depends on BF516 || BF518 || BF526 || BF527 || BF536 || BF537
- ---help---
- If you have a network (Ethernet) card belonging to this class, say Y.
-
- If unsure, say Y.
-
- Note that the answer to this question doesn't directly affect the
- kernel: saying N will just cause the configurator to skip all
- the remaining Blackfin card questions. If you say Y, you will be
- asked for your specific card in the following questions.
-
-if NET_BFIN
-
-config BFIN_MAC
- tristate "Blackfin on-chip MAC support"
- depends on (BF516 || BF518 || BF526 || BF527 || BF536 || BF537)
- select CRC32
- select MII
- select PHYLIB
- select BFIN_MAC_USE_L1 if DMA_UNCACHED_NONE
- ---help---
- This is the driver for Blackfin on-chip mac device. Say Y if you want
- it compiled into the kernel. This driver is also available as a
- module ( = code which can be inserted in and removed from the running
- kernel whenever you want). The module will be called bfin_mac.
-
-config BFIN_MAC_USE_L1
- bool "Use L1 memory for rx/tx packets"
- depends on BFIN_MAC && (BF527 || BF537)
- default y
- ---help---
- To get maximum network performance, you should use L1 memory as rx/tx
- buffers. Say N here if you want to reserve L1 memory for other uses.
-
-config BFIN_TX_DESC_NUM
- int "Number of transmit buffer packets"
- depends on BFIN_MAC
- range 6 10 if BFIN_MAC_USE_L1
- range 10 100
- default "10"
- ---help---
- Set the number of buffer packets used in driver.
-
-config BFIN_RX_DESC_NUM
- int "Number of receive buffer packets"
- depends on BFIN_MAC
- range 20 64
- default "20"
- ---help---
- Set the number of buffer packets used in driver.
-
-config BFIN_MAC_USE_HWSTAMP
- bool "Use IEEE 1588 hwstamp"
- depends on BFIN_MAC && BF518
- imply PTP_1588_CLOCK
- default y
- ---help---
- To support the IEEE 1588 Precision Time Protocol (PTP), select y here
-
-endif # NET_BFIN
diff --git a/drivers/net/ethernet/adi/Makefile b/drivers/net/ethernet/adi/Makefile
deleted file mode 100644
index b1fbe19..0000000
--- a/drivers/net/ethernet/adi/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the Blackfin device drivers.
-#
-
-obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
diff --git a/drivers/net/ethernet/adi/bfin_mac.c b/drivers/net/ethernet/adi/bfin_mac.c
deleted file mode 100644
index 7120f2b..0000000
--- a/drivers/net/ethernet/adi/bfin_mac.c
+++ /dev/null
@@ -1,1881 +0,0 @@
-/*
- * Blackfin On-Chip MAC Driver
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define DRV_VERSION "1.1"
-#define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/timer.h>
-#include <linux/errno.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/crc32.h>
-#include <linux/device.h>
-#include <linux/spinlock.h>
-#include <linux/mii.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/ethtool.h>
-#include <linux/skbuff.h>
-#include <linux/platform_device.h>
-
-#include <asm/dma.h>
-#include <linux/dma-mapping.h>
-
-#include <asm/div64.h>
-#include <asm/dpmc.h>
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/portmux.h>
-#include <mach/pll.h>
-
-#include "bfin_mac.h"
-
-MODULE_AUTHOR("Bryan Wu, Luke Yang");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_ALIAS("platform:bfin_mac");
-
-#if defined(CONFIG_BFIN_MAC_USE_L1)
-# define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
-# define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
-#else
-# define bfin_mac_alloc(dma_handle, size, num) \
- dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
-# define bfin_mac_free(dma_handle, ptr, num) \
- dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
-#endif
-
-#define PKT_BUF_SZ 1580
-
-#define MAX_TIMEOUT_CNT 500
-
-/* pointers to maintain transmit list */
-static struct net_dma_desc_tx *tx_list_head;
-static struct net_dma_desc_tx *tx_list_tail;
-static struct net_dma_desc_rx *rx_list_head;
-static struct net_dma_desc_rx *rx_list_tail;
-static struct net_dma_desc_rx *current_rx_ptr;
-static struct net_dma_desc_tx *current_tx_ptr;
-static struct net_dma_desc_tx *tx_desc;
-static struct net_dma_desc_rx *rx_desc;
-
-static void desc_list_free(void)
-{
- struct net_dma_desc_rx *r;
- struct net_dma_desc_tx *t;
- int i;
-#if !defined(CONFIG_BFIN_MAC_USE_L1)
- dma_addr_t dma_handle = 0;
-#endif
-
- if (tx_desc) {
- t = tx_list_head;
- for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
- if (t) {
- if (t->skb) {
- dev_kfree_skb(t->skb);
- t->skb = NULL;
- }
- t = t->next;
- }
- }
- bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
- }
-
- if (rx_desc) {
- r = rx_list_head;
- for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
- if (r) {
- if (r->skb) {
- dev_kfree_skb(r->skb);
- r->skb = NULL;
- }
- r = r->next;
- }
- }
- bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
- }
-}
-
-static int desc_list_init(struct net_device *dev)
-{
- int i;
- struct sk_buff *new_skb;
-#if !defined(CONFIG_BFIN_MAC_USE_L1)
- /*
- * This dma_handle is useless in Blackfin dma_alloc_coherent().
- * The real dma handler is the return value of dma_alloc_coherent().
- */
- dma_addr_t dma_handle;
-#endif
-
- tx_desc = bfin_mac_alloc(&dma_handle,
- sizeof(struct net_dma_desc_tx),
- CONFIG_BFIN_TX_DESC_NUM);
- if (tx_desc == NULL)
- goto init_error;
-
- rx_desc = bfin_mac_alloc(&dma_handle,
- sizeof(struct net_dma_desc_rx),
- CONFIG_BFIN_RX_DESC_NUM);
- if (rx_desc == NULL)
- goto init_error;
-
- /* init tx_list */
- tx_list_head = tx_list_tail = tx_desc;
-
- for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
- struct net_dma_desc_tx *t = tx_desc + i;
- struct dma_descriptor *a = &(t->desc_a);
- struct dma_descriptor *b = &(t->desc_b);
-
- /*
- * disable DMA
- * read from memory WNR = 0
- * wordsize is 32 bits
- * 6 half words is desc size
- * large desc flow
- */
- a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
- a->start_addr = (unsigned long)t->packet;
- a->x_count = 0;
- a->next_dma_desc = b;
-
- /*
- * enabled DMA
- * write to memory WNR = 1
- * wordsize is 32 bits
- * disable interrupt
- * 6 half words is desc size
- * large desc flow
- */
- b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
- b->start_addr = (unsigned long)(&(t->status));
- b->x_count = 0;
-
- t->skb = NULL;
- tx_list_tail->desc_b.next_dma_desc = a;
- tx_list_tail->next = t;
- tx_list_tail = t;
- }
- tx_list_tail->next = tx_list_head; /* tx_list is a circle */
- tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
- current_tx_ptr = tx_list_head;
-
- /* init rx_list */
- rx_list_head = rx_list_tail = rx_desc;
-
- for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
- struct net_dma_desc_rx *r = rx_desc + i;
- struct dma_descriptor *a = &(r->desc_a);
- struct dma_descriptor *b = &(r->desc_b);
-
- /* allocate a new skb for next time receive */
- new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
- if (!new_skb)
- goto init_error;
-
- skb_reserve(new_skb, NET_IP_ALIGN);
- /* Invalidate the data cache of skb->data range when it is write back
- * cache. It will prevent overwriting the new data from DMA
- */
- blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
- (unsigned long)new_skb->end);
- r->skb = new_skb;
-
- /*
- * enabled DMA
- * write to memory WNR = 1
- * wordsize is 32 bits
- * disable interrupt
- * 6 half words is desc size
- * large desc flow
- */
- a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
- /* since RXDWA is enabled */
- a->start_addr = (unsigned long)new_skb->data - 2;
- a->x_count = 0;
- a->next_dma_desc = b;
-
- /*
- * enabled DMA
- * write to memory WNR = 1
- * wordsize is 32 bits
- * enable interrupt
- * 6 half words is desc size
- * large desc flow
- */
- b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
- NDSIZE_6 | DMAFLOW_LARGE;
- b->start_addr = (unsigned long)(&(r->status));
- b->x_count = 0;
-
- rx_list_tail->desc_b.next_dma_desc = a;
- rx_list_tail->next = r;
- rx_list_tail = r;
- }
- rx_list_tail->next = rx_list_head; /* rx_list is a circle */
- rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
- current_rx_ptr = rx_list_head;
-
- return 0;
-
-init_error:
- desc_list_free();
- pr_err("kmalloc failed\n");
- return -ENOMEM;
-}
-
-
-/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
-
-/*
- * MII operations
- */
-/* Wait until the previous MDC/MDIO transaction has completed */
-static int bfin_mdio_poll(void)
-{
- int timeout_cnt = MAX_TIMEOUT_CNT;
-
- /* poll the STABUSY bit */
- while ((bfin_read_EMAC_STAADD()) & STABUSY) {
- udelay(1);
- if (timeout_cnt-- < 0) {
- pr_err("wait MDC/MDIO transaction to complete timeout\n");
- return -ETIMEDOUT;
- }
- }
-
- return 0;
-}
-
-/* Read an off-chip register in a PHY through the MDC/MDIO port */
-static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
-{
- int ret;
-
- ret = bfin_mdio_poll();
- if (ret)
- return ret;
-
- /* read mode */
- bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
- SET_REGAD((u16) regnum) |
- STABUSY);
-
- ret = bfin_mdio_poll();
- if (ret)
- return ret;
-
- return (int) bfin_read_EMAC_STADAT();
-}
-
-/* Write an off-chip register in a PHY through the MDC/MDIO port */
-static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
- u16 value)
-{
- int ret;
-
- ret = bfin_mdio_poll();
- if (ret)
- return ret;
-
- bfin_write_EMAC_STADAT((u32) value);
-
- /* write mode */
- bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
- SET_REGAD((u16) regnum) |
- STAOP |
- STABUSY);
-
- return bfin_mdio_poll();
-}
-
-static void bfin_mac_adjust_link(struct net_device *dev)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
- struct phy_device *phydev = dev->phydev;
- unsigned long flags;
- int new_state = 0;
-
- spin_lock_irqsave(&lp->lock, flags);
- if (phydev->link) {
- /* Now we make sure that we can be in full duplex mode.
- * If not, we operate in half-duplex mode. */
- if (phydev->duplex != lp->old_duplex) {
- u32 opmode = bfin_read_EMAC_OPMODE();
- new_state = 1;
-
- if (phydev->duplex)
- opmode |= FDMODE;
- else
- opmode &= ~(FDMODE);
-
- bfin_write_EMAC_OPMODE(opmode);
- lp->old_duplex = phydev->duplex;
- }
-
- if (phydev->speed != lp->old_speed) {
- if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
- u32 opmode = bfin_read_EMAC_OPMODE();
- switch (phydev->speed) {
- case 10:
- opmode |= RMII_10;
- break;
- case 100:
- opmode &= ~RMII_10;
- break;
- default:
- netdev_warn(dev,
- "Ack! Speed (%d) is not 10/100!\n",
- phydev->speed);
- break;
- }
- bfin_write_EMAC_OPMODE(opmode);
- }
-
- new_state = 1;
- lp->old_speed = phydev->speed;
- }
-
- if (!lp->old_link) {
- new_state = 1;
- lp->old_link = 1;
- }
- } else if (lp->old_link) {
- new_state = 1;
- lp->old_link = 0;
- lp->old_speed = 0;
- lp->old_duplex = -1;
- }
-
- if (new_state) {
- u32 opmode = bfin_read_EMAC_OPMODE();
- phy_print_status(phydev);
- pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
- }
-
- spin_unlock_irqrestore(&lp->lock, flags);
-}
-
-/* MDC = 2.5 MHz */
-#define MDC_CLK 2500000
-
-static int mii_probe(struct net_device *dev, int phy_mode)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
- struct phy_device *phydev;
- unsigned short sysctl;
- u32 sclk, mdc_div;
-
- /* Enable PHY output early */
- if (!(bfin_read_VR_CTL() & CLKBUFOE))
- bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-
- sclk = get_sclk();
- mdc_div = ((sclk / MDC_CLK) / 2) - 1;
-
- sysctl = bfin_read_EMAC_SYSCTL();
- sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
- bfin_write_EMAC_SYSCTL(sysctl);
-
- phydev = phy_find_first(lp->mii_bus);
- if (!phydev) {
- netdev_err(dev, "no phy device found\n");
- return -ENODEV;
- }
-
- if (phy_mode != PHY_INTERFACE_MODE_RMII &&
- phy_mode != PHY_INTERFACE_MODE_MII) {
- netdev_err(dev, "invalid phy interface mode\n");
- return -EINVAL;
- }
-
- phydev = phy_connect(dev, phydev_name(phydev),
- &bfin_mac_adjust_link, phy_mode);
-
- if (IS_ERR(phydev)) {
- netdev_err(dev, "could not attach PHY\n");
- return PTR_ERR(phydev);
- }
-
- /* mask with MAC supported features */
- phydev->supported &= (SUPPORTED_10baseT_Half
- | SUPPORTED_10baseT_Full
- | SUPPORTED_100baseT_Half
- | SUPPORTED_100baseT_Full
- | SUPPORTED_Autoneg
- | SUPPORTED_Pause | SUPPORTED_Asym_Pause
- | SUPPORTED_MII
- | SUPPORTED_TP);
-
- phydev->advertising = phydev->supported;
-
- lp->old_link = 0;
- lp->old_speed = 0;
- lp->old_duplex = -1;
-
- phy_attached_print(phydev, "mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
- MDC_CLK, mdc_div, sclk / 1000000);
-
- return 0;
-}
-
-/*
- * Ethtool support
- */
-
-/*
- * interrupt routine for magic packet wakeup
- */
-static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
-{
- return IRQ_HANDLED;
-}
-
-static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
- struct ethtool_drvinfo *info)
-{
- strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
- strlcpy(info->version, DRV_VERSION, sizeof(info->version));
- strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
- strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
-}
-
-static void bfin_mac_ethtool_getwol(struct net_device *dev,
- struct ethtool_wolinfo *wolinfo)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
-
- wolinfo->supported = WAKE_MAGIC;
- wolinfo->wolopts = lp->wol;
-}
-
-static int bfin_mac_ethtool_setwol(struct net_device *dev,
- struct ethtool_wolinfo *wolinfo)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
- int rc;
-
- if (wolinfo->wolopts & (WAKE_MAGICSECURE |
- WAKE_UCAST |
- WAKE_MCAST |
- WAKE_BCAST |
- WAKE_ARP))
- return -EOPNOTSUPP;
-
- lp->wol = wolinfo->wolopts;
-
- if (lp->wol && !lp->irq_wake_requested) {
- /* register wake irq handler */
- rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
- 0, "EMAC_WAKE", dev);
- if (rc)
- return rc;
- lp->irq_wake_requested = true;
- }
-
- if (!lp->wol && lp->irq_wake_requested) {
- free_irq(IRQ_MAC_WAKEDET, dev);
- lp->irq_wake_requested = false;
- }
-
- /* Make sure the PHY driver doesn't suspend */
- device_init_wakeup(&dev->dev, lp->wol);
-
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
-static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
- struct ethtool_ts_info *info)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
-
- info->so_timestamping =
- SOF_TIMESTAMPING_TX_HARDWARE |
- SOF_TIMESTAMPING_RX_HARDWARE |
- SOF_TIMESTAMPING_RAW_HARDWARE;
- info->phc_index = lp->phc_index;
- info->tx_types =
- (1 << HWTSTAMP_TX_OFF) |
- (1 << HWTSTAMP_TX_ON);
- info->rx_filters =
- (1 << HWTSTAMP_FILTER_NONE) |
- (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
- (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
- (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
- return 0;
-}
-#endif
-
-static const struct ethtool_ops bfin_mac_ethtool_ops = {
- .get_link = ethtool_op_get_link,
- .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
- .get_wol = bfin_mac_ethtool_getwol,
- .set_wol = bfin_mac_ethtool_setwol,
-#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
- .get_ts_info = bfin_mac_ethtool_get_ts_info,
-#endif
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
- .set_link_ksettings = phy_ethtool_set_link_ksettings,
-};
-
-/**************************************************************************/
-static void setup_system_regs(struct net_device *dev)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
- int i;
- unsigned short sysctl;
-
- /*
- * Odd word alignment for Receive Frame DMA word
- * Configure checksum support and rcve frame word alignment
- */
- sysctl = bfin_read_EMAC_SYSCTL();
- /*
- * check if interrupt is requested for any PHY,
- * enable PHY interrupt only if needed
- */
- for (i = 0; i < PHY_MAX_ADDR; ++i)
- if (lp->mii_bus->irq[i] != PHY_POLL)
- break;
- if (i < PHY_MAX_ADDR)
- sysctl |= PHYIE;
- sysctl |= RXDWA;
-#if defined(BFIN_MAC_CSUM_OFFLOAD)
- sysctl |= RXCKS;
-#else
- sysctl &= ~RXCKS;
-#endif
- bfin_write_EMAC_SYSCTL(sysctl);
-
- bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
-
- /* Set vlan regs to let 1522 bytes long packets pass through */
- bfin_write_EMAC_VLAN1(lp->vlan1_mask);
- bfin_write_EMAC_VLAN2(lp->vlan2_mask);
-
- /* Initialize the TX DMA channel registers */
- bfin_write_DMA2_X_COUNT(0);
- bfin_write_DMA2_X_MODIFY(4);
- bfin_write_DMA2_Y_COUNT(0);
- bfin_write_DMA2_Y_MODIFY(0);
-
- /* Initialize the RX DMA channel registers */
- bfin_write_DMA1_X_COUNT(0);
- bfin_write_DMA1_X_MODIFY(4);
- bfin_write_DMA1_Y_COUNT(0);
- bfin_write_DMA1_Y_MODIFY(0);
-}
-
-static void setup_mac_addr(u8 *mac_addr)
-{
- u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
- u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
-
- /* this depends on a little-endian machine */
- bfin_write_EMAC_ADDRLO(addr_low);
- bfin_write_EMAC_ADDRHI(addr_hi);
-}
-
-static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
-{
- struct sockaddr *addr = p;
- if (netif_running(dev))
- return -EBUSY;
- memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
- setup_mac_addr(dev->dev_addr);
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
-#define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
-
-static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result)
-{
- u32 ipn = 1000000000UL / input_clk;
- u32 ppn = 1;
- unsigned int shift = 0;
-
- while (ppn <= ipn) {
- ppn <<= 1;
- shift++;
- }
- *shift_result = shift;
- return 1000000000UL / ppn;
-}
-
-static int bfin_mac_hwtstamp_set(struct net_device *netdev,
- struct ifreq *ifr)
-{
- struct hwtstamp_config config;
- struct bfin_mac_local *lp = netdev_priv(netdev);
- u16 ptpctl;
- u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
-
- if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
- return -EFAULT;
-
- pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
- __func__, config.flags, config.tx_type, config.rx_filter);
-
- /* reserved for future extensions */
- if (config.flags)
- return -EINVAL;
-
- if ((config.tx_type != HWTSTAMP_TX_OFF) &&
- (config.tx_type != HWTSTAMP_TX_ON))
- return -ERANGE;
-
- ptpctl = bfin_read_EMAC_PTP_CTL();
-
- switch (config.rx_filter) {
- case HWTSTAMP_FILTER_NONE:
- /*
- * Dont allow any timestamping
- */
- ptpfv3 = 0xFFFFFFFF;
- bfin_write_EMAC_PTP_FV3(ptpfv3);
- break;
- case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
- case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
- case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
- /*
- * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
- * to enable all the field matches.
- */
- ptpctl &= ~0x1F00;
- bfin_write_EMAC_PTP_CTL(ptpctl);
- /*
- * Keep the default values of the EMAC_PTP_FOFF register.
- */
- ptpfoff = 0x4A24170C;
- bfin_write_EMAC_PTP_FOFF(ptpfoff);
- /*
- * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
- * registers.
- */
- ptpfv1 = 0x11040800;
- bfin_write_EMAC_PTP_FV1(ptpfv1);
- ptpfv2 = 0x0140013F;
- bfin_write_EMAC_PTP_FV2(ptpfv2);
- /*
- * The default value (0xFFFC) allows the timestamping of both
- * received Sync messages and Delay_Req messages.
- */
- ptpfv3 = 0xFFFFFFFC;
- bfin_write_EMAC_PTP_FV3(ptpfv3);
-
- config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
- break;
- case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
- case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
- case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
- /* Clear all five comparison mask bits (bits[12:8]) in the
- * EMAC_PTP_CTL register to enable all the field matches.
- */
- ptpctl &= ~0x1F00;
- bfin_write_EMAC_PTP_CTL(ptpctl);
- /*
- * Keep the default values of the EMAC_PTP_FOFF register, except set
- * the PTPCOF field to 0x2A.
- */
- ptpfoff = 0x2A24170C;
- bfin_write_EMAC_PTP_FOFF(ptpfoff);
- /*
- * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
- * registers.
- */
- ptpfv1 = 0x11040800;
- bfin_write_EMAC_PTP_FV1(ptpfv1);
- ptpfv2 = 0x0140013F;
- bfin_write_EMAC_PTP_FV2(ptpfv2);
- /*
- * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
- * the value to 0xFFF0.
- */
- ptpfv3 = 0xFFFFFFF0;
- bfin_write_EMAC_PTP_FV3(ptpfv3);
-
- config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
- break;
- case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
- case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
- case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
- /*
- * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
- * EFTM and PTPCM field comparison.
- */
- ptpctl &= ~0x1100;
- bfin_write_EMAC_PTP_CTL(ptpctl);
- /*
- * Keep the default values of all the fields of the EMAC_PTP_FOFF
- * register, except set the PTPCOF field to 0x0E.
- */
- ptpfoff = 0x0E24170C;
- bfin_write_EMAC_PTP_FOFF(ptpfoff);
- /*
- * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
- * corresponds to PTP messages on the MAC layer.
- */
- ptpfv1 = 0x110488F7;
- bfin_write_EMAC_PTP_FV1(ptpfv1);
- ptpfv2 = 0x0140013F;
- bfin_write_EMAC_PTP_FV2(ptpfv2);
- /*
- * To allow the timestamping of Pdelay_Req and Pdelay_Resp
- * messages, set the value to 0xFFF0.
- */
- ptpfv3 = 0xFFFFFFF0;
- bfin_write_EMAC_PTP_FV3(ptpfv3);
-
- config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
- break;
- default:
- return -ERANGE;
- }
-
- if (config.tx_type == HWTSTAMP_TX_OFF &&
- bfin_mac_hwtstamp_is_none(config.rx_filter)) {
- ptpctl &= ~PTP_EN;
- bfin_write_EMAC_PTP_CTL(ptpctl);
-
- SSYNC();
- } else {
- ptpctl |= PTP_EN;
- bfin_write_EMAC_PTP_CTL(ptpctl);
-
- /*
- * clear any existing timestamp
- */
- bfin_read_EMAC_PTP_RXSNAPLO();
- bfin_read_EMAC_PTP_RXSNAPHI();
-
- bfin_read_EMAC_PTP_TXSNAPLO();
- bfin_read_EMAC_PTP_TXSNAPHI();
-
- SSYNC();
- }
-
- lp->stamp_cfg = config;
- return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
- -EFAULT : 0;
-}
-
-static int bfin_mac_hwtstamp_get(struct net_device *netdev,
- struct ifreq *ifr)
-{
- struct bfin_mac_local *lp = netdev_priv(netdev);
-
- return copy_to_user(ifr->ifr_data, &lp->stamp_cfg,
- sizeof(lp->stamp_cfg)) ?
- -EFAULT : 0;
-}
-
-static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
-{
- struct bfin_mac_local *lp = netdev_priv(netdev);
-
- if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
- int timeout_cnt = MAX_TIMEOUT_CNT;
-
- /* When doing time stamping, keep the connection to the socket
- * a while longer
- */
- skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
-
- /*
- * The timestamping is done at the EMAC module's MII/RMII interface
- * when the module sees the Start of Frame of an event message packet. This
- * interface is the closest possible place to the physical Ethernet transmission
- * medium, providing the best timing accuracy.
- */
- while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
- udelay(1);
- if (timeout_cnt == 0)
- netdev_err(netdev, "timestamp the TX packet failed\n");
- else {
- struct skb_shared_hwtstamps shhwtstamps;
- u64 ns;
- u64 regval;
-
- regval = bfin_read_EMAC_PTP_TXSNAPLO();
- regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
- memset(&shhwtstamps, 0, sizeof(shhwtstamps));
- ns = regval << lp->shift;
- shhwtstamps.hwtstamp = ns_to_ktime(ns);
- skb_tstamp_tx(skb, &shhwtstamps);
- }
- }
-}
-
-static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
-{
- struct bfin_mac_local *lp = netdev_priv(netdev);
- u32 valid;
- u64 regval, ns;
- struct skb_shared_hwtstamps *shhwtstamps;
-
- if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
- return;
-
- valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
- if (!valid)
- return;
-
- shhwtstamps = skb_hwtstamps(skb);
-
- regval = bfin_read_EMAC_PTP_RXSNAPLO();
- regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
- ns = regval << lp->shift;
- memset(shhwtstamps, 0, sizeof(*shhwtstamps));
- shhwtstamps->hwtstamp = ns_to_ktime(ns);
-}
-
-static void bfin_mac_hwtstamp_init(struct net_device *netdev)
-{
- struct bfin_mac_local *lp = netdev_priv(netdev);
- u64 addend, ppb;
- u32 input_clk, phc_clk;
-
- /* Initialize hardware timer */
- input_clk = get_sclk();
- phc_clk = bfin_select_phc_clock(input_clk, &lp->shift);
- addend = phc_clk * (1ULL << 32);
- do_div(addend, input_clk);
- bfin_write_EMAC_PTP_ADDEND((u32)addend);
-
- lp->addend = addend;
- ppb = 1000000000ULL * input_clk;
- do_div(ppb, phc_clk);
- lp->max_ppb = ppb - 1000000000ULL - 1ULL;
-
- /* Initialize hwstamp config */
- lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
- lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
-}
-
-static u64 bfin_ptp_time_read(struct bfin_mac_local *lp)
-{
- u64 ns;
- u32 lo, hi;
-
- lo = bfin_read_EMAC_PTP_TIMELO();
- hi = bfin_read_EMAC_PTP_TIMEHI();
-
- ns = ((u64) hi) << 32;
- ns |= lo;
- ns <<= lp->shift;
-
- return ns;
-}
-
-static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns)
-{
- u32 hi, lo;
-
- ns >>= lp->shift;
- hi = ns >> 32;
- lo = ns & 0xffffffff;
-
- bfin_write_EMAC_PTP_TIMELO(lo);
- bfin_write_EMAC_PTP_TIMEHI(hi);
-}
-
-/* PTP Hardware Clock operations */
-
-static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
-{
- u64 adj;
- u32 diff, addend;
- int neg_adj = 0;
- struct bfin_mac_local *lp =
- container_of(ptp, struct bfin_mac_local, caps);
-
- if (ppb < 0) {
- neg_adj = 1;
- ppb = -ppb;
- }
- addend = lp->addend;
- adj = addend;
- adj *= ppb;
- diff = div_u64(adj, 1000000000ULL);
-
- addend = neg_adj ? addend - diff : addend + diff;
-
- bfin_write_EMAC_PTP_ADDEND(addend);
-
- return 0;
-}
-
-static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
-{
- s64 now;
- unsigned long flags;
- struct bfin_mac_local *lp =
- container_of(ptp, struct bfin_mac_local, caps);
-
- spin_lock_irqsave(&lp->phc_lock, flags);
-
- now = bfin_ptp_time_read(lp);
- now += delta;
- bfin_ptp_time_write(lp, now);
-
- spin_unlock_irqrestore(&lp->phc_lock, flags);
-
- return 0;
-}
-
-static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
-{
- u64 ns;
- unsigned long flags;
- struct bfin_mac_local *lp =
- container_of(ptp, struct bfin_mac_local, caps);
-
- spin_lock_irqsave(&lp->phc_lock, flags);
-
- ns = bfin_ptp_time_read(lp);
-
- spin_unlock_irqrestore(&lp->phc_lock, flags);
-
- *ts = ns_to_timespec64(ns);
-
- return 0;
-}
-
-static int bfin_ptp_settime(struct ptp_clock_info *ptp,
- const struct timespec64 *ts)
-{
- u64 ns;
- unsigned long flags;
- struct bfin_mac_local *lp =
- container_of(ptp, struct bfin_mac_local, caps);
-
- ns = timespec64_to_ns(ts);
-
- spin_lock_irqsave(&lp->phc_lock, flags);
-
- bfin_ptp_time_write(lp, ns);
-
- spin_unlock_irqrestore(&lp->phc_lock, flags);
-
- return 0;
-}
-
-static int bfin_ptp_enable(struct ptp_clock_info *ptp,
- struct ptp_clock_request *rq, int on)
-{
- return -EOPNOTSUPP;
-}
-
-static const struct ptp_clock_info bfin_ptp_caps = {
- .owner = THIS_MODULE,
- .name = "BF518 clock",
- .max_adj = 0,
- .n_alarm = 0,
- .n_ext_ts = 0,
- .n_per_out = 0,
- .n_pins = 0,
- .pps = 0,
- .adjfreq = bfin_ptp_adjfreq,
- .adjtime = bfin_ptp_adjtime,
- .gettime64 = bfin_ptp_gettime,
- .settime64 = bfin_ptp_settime,
- .enable = bfin_ptp_enable,
-};
-
-static int bfin_phc_init(struct net_device *netdev, struct device *dev)
-{
- struct bfin_mac_local *lp = netdev_priv(netdev);
-
- lp->caps = bfin_ptp_caps;
- lp->caps.max_adj = lp->max_ppb;
- lp->clock = ptp_clock_register(&lp->caps, dev);
- if (IS_ERR(lp->clock))
- return PTR_ERR(lp->clock);
-
- lp->phc_index = ptp_clock_index(lp->clock);
- spin_lock_init(&lp->phc_lock);
-
- return 0;
-}
-
-static void bfin_phc_release(struct bfin_mac_local *lp)
-{
- ptp_clock_unregister(lp->clock);
-}
-
-#else
-# define bfin_mac_hwtstamp_is_none(cfg) 0
-# define bfin_mac_hwtstamp_init(dev)
-# define bfin_mac_hwtstamp_set(dev, ifr) (-EOPNOTSUPP)
-# define bfin_mac_hwtstamp_get(dev, ifr) (-EOPNOTSUPP)
-# define bfin_rx_hwtstamp(dev, skb)
-# define bfin_tx_hwtstamp(dev, skb)
-# define bfin_phc_init(netdev, dev) 0
-# define bfin_phc_release(lp)
-#endif
-
-static inline void _tx_reclaim_skb(void)
-{
- do {
- tx_list_head->desc_a.config &= ~DMAEN;
- tx_list_head->status.status_word = 0;
- if (tx_list_head->skb) {
- dev_consume_skb_any(tx_list_head->skb);
- tx_list_head->skb = NULL;
- }
- tx_list_head = tx_list_head->next;
-
- } while (tx_list_head->status.status_word != 0);
-}
-
-static void tx_reclaim_skb(struct bfin_mac_local *lp)
-{
- int timeout_cnt = MAX_TIMEOUT_CNT;
-
- if (tx_list_head->status.status_word != 0)
- _tx_reclaim_skb();
-
- if (current_tx_ptr->next == tx_list_head) {
- while (tx_list_head->status.status_word == 0) {
- /* slow down polling to avoid too many queue stop. */
- udelay(10);
- /* reclaim skb if DMA is not running. */
- if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
- break;
- if (timeout_cnt-- < 0)
- break;
- }
-
- if (timeout_cnt >= 0)
- _tx_reclaim_skb();
- else
- netif_stop_queue(lp->ndev);
- }
-
- if (current_tx_ptr->next != tx_list_head &&
- netif_queue_stopped(lp->ndev))
- netif_wake_queue(lp->ndev);
-
- if (tx_list_head != current_tx_ptr) {
- /* shorten the timer interval if tx queue is stopped */
- if (netif_queue_stopped(lp->ndev))
- lp->tx_reclaim_timer.expires =
- jiffies + (TX_RECLAIM_JIFFIES >> 4);
- else
- lp->tx_reclaim_timer.expires =
- jiffies + TX_RECLAIM_JIFFIES;
-
- mod_timer(&lp->tx_reclaim_timer,
- lp->tx_reclaim_timer.expires);
- }
-
- return;
-}
-
-static void tx_reclaim_skb_timeout(struct timer_list *t)
-{
- struct bfin_mac_local *lp = from_timer(lp, t, tx_reclaim_timer);
-
- tx_reclaim_skb(lp);
-}
-
-static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
- struct net_device *dev)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
- u16 *data;
- u32 data_align = (unsigned long)(skb->data) & 0x3;
-
- current_tx_ptr->skb = skb;
-
- if (data_align == 0x2) {
- /* move skb->data to current_tx_ptr payload */
- data = (u16 *)(skb->data) - 1;
- *data = (u16)(skb->len);
- /*
- * When transmitting an Ethernet packet, the PTP_TSYNC module requires
- * a DMA_Length_Word field associated with the packet. The lower 12 bits
- * of this field are the length of the packet payload in bytes and the higher
- * 4 bits are the timestamping enable field.
- */
- if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
- *data |= 0x1000;
-
- current_tx_ptr->desc_a.start_addr = (u32)data;
- /* this is important! */
- blackfin_dcache_flush_range((u32)data,
- (u32)((u8 *)data + skb->len + 4));
- } else {
- *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
- /* enable timestamping for the sent packet */
- if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
- *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
- memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
- skb->len);
- current_tx_ptr->desc_a.start_addr =
- (u32)current_tx_ptr->packet;
- blackfin_dcache_flush_range(
- (u32)current_tx_ptr->packet,
- (u32)(current_tx_ptr->packet + skb->len + 2));
- }
-
- /* make sure the internal data buffers in the core are drained
- * so that the DMA descriptors are completely written when the
- * DMA engine goes to fetch them below
- */
- SSYNC();
-
- /* always clear status buffer before start tx dma */
- current_tx_ptr->status.status_word = 0;
-
- /* enable this packet's dma */
- current_tx_ptr->desc_a.config |= DMAEN;
-
- /* tx dma is running, just return */
- if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
- goto out;
-
- /* tx dma is not running */
- bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
- /* dma enabled, read from memory, size is 6 */
- bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
- /* Turn on the EMAC tx */
- bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
-
-out:
- bfin_tx_hwtstamp(dev, skb);
-
- current_tx_ptr = current_tx_ptr->next;
- dev->stats.tx_packets++;
- dev->stats.tx_bytes += (skb->len);
-
- tx_reclaim_skb(lp);
-
- return NETDEV_TX_OK;
-}
-
-#define IP_HEADER_OFF 0
-#define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
- RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
-
-static void bfin_mac_rx(struct bfin_mac_local *lp)
-{
- struct net_device *dev = lp->ndev;
- struct sk_buff *skb, *new_skb;
- unsigned short len;
-#if defined(BFIN_MAC_CSUM_OFFLOAD)
- unsigned int i;
- unsigned char fcs[ETH_FCS_LEN + 1];
-#endif
-
- /* check if frame status word reports an error condition
- * we which case we simply drop the packet
- */
- if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
- netdev_notice(dev, "rx: receive error - packet dropped\n");
- dev->stats.rx_dropped++;
- goto out;
- }
-
- /* allocate a new skb for next time receive */
- skb = current_rx_ptr->skb;
-
- new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
- if (!new_skb) {
- dev->stats.rx_dropped++;
- goto out;
- }
- /* reserve 2 bytes for RXDWA padding */
- skb_reserve(new_skb, NET_IP_ALIGN);
- /* Invalidate the data cache of skb->data range when it is write back
- * cache. It will prevent overwriting the new data from DMA
- */
- blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
- (unsigned long)new_skb->end);
-
- current_rx_ptr->skb = new_skb;
- current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
-
- len = (unsigned short)(current_rx_ptr->status.status_word & RX_FRLEN);
- /* Deduce Ethernet FCS length from Ethernet payload length */
- len -= ETH_FCS_LEN;
- skb_put(skb, len);
-
- skb->protocol = eth_type_trans(skb, dev);
-
- bfin_rx_hwtstamp(dev, skb);
-
-#if defined(BFIN_MAC_CSUM_OFFLOAD)
- /* Checksum offloading only works for IPv4 packets with the standard IP header
- * length of 20 bytes, because the blackfin MAC checksum calculation is
- * based on that assumption. We must NOT use the calculated checksum if our
- * IP version or header break that assumption.
- */
- if (skb->data[IP_HEADER_OFF] == 0x45) {
- skb->csum = current_rx_ptr->status.ip_payload_csum;
- /*
- * Deduce Ethernet FCS from hardware generated IP payload checksum.
- * IP checksum is based on 16-bit one's complement algorithm.
- * To deduce a value from checksum is equal to add its inversion.
- * If the IP payload len is odd, the inversed FCS should also
- * begin from odd address and leave first byte zero.
- */
- if (skb->len % 2) {
- fcs[0] = 0;
- for (i = 0; i < ETH_FCS_LEN; i++)
- fcs[i + 1] = ~skb->data[skb->len + i];
- skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
- } else {
- for (i = 0; i < ETH_FCS_LEN; i++)
- fcs[i] = ~skb->data[skb->len + i];
- skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
- }
- skb->ip_summed = CHECKSUM_COMPLETE;
- }
-#endif
-
- napi_gro_receive(&lp->napi, skb);
-
- dev->stats.rx_packets++;
- dev->stats.rx_bytes += len;
-out:
- current_rx_ptr->status.status_word = 0x00000000;
- current_rx_ptr = current_rx_ptr->next;
-}
-
-static int bfin_mac_poll(struct napi_struct *napi, int budget)
-{
- int i = 0;
- struct bfin_mac_local *lp = container_of(napi,
- struct bfin_mac_local,
- napi);
-
- while (current_rx_ptr->status.status_word != 0 && i < budget) {
- bfin_mac_rx(lp);
- i++;
- }
-
- if (i < budget) {
- napi_complete_done(napi, i);
- if (test_and_clear_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags))
- enable_irq(IRQ_MAC_RX);
- }
-
- return i;
-}
-
-/* interrupt routine to handle rx and error signal */
-static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
-{
- struct bfin_mac_local *lp = netdev_priv(dev_id);
- u32 status;
-
- status = bfin_read_DMA1_IRQ_STATUS();
-
- bfin_write_DMA1_IRQ_STATUS(status | DMA_DONE | DMA_ERR);
- if (status & DMA_DONE) {
- disable_irq_nosync(IRQ_MAC_RX);
- set_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags);
- napi_schedule(&lp->napi);
- }
-
- return IRQ_HANDLED;
-}
-
-#ifdef CONFIG_NET_POLL_CONTROLLER
-static void bfin_mac_poll_controller(struct net_device *dev)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
-
- bfin_mac_interrupt(IRQ_MAC_RX, dev);
- tx_reclaim_skb(lp);
-}
-#endif /* CONFIG_NET_POLL_CONTROLLER */
-
-static void bfin_mac_disable(void)
-{
- unsigned int opmode;
-
- opmode = bfin_read_EMAC_OPMODE();
- opmode &= (~RE);
- opmode &= (~TE);
- /* Turn off the EMAC */
- bfin_write_EMAC_OPMODE(opmode);
-}
-
-/*
- * Enable Interrupts, Receive, and Transmit
- */
-static int bfin_mac_enable(struct phy_device *phydev)
-{
- int ret;
- u32 opmode;
-
- pr_debug("%s\n", __func__);
-
- /* Set RX DMA */
- bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
- bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
-
- /* Wait MII done */
- ret = bfin_mdio_poll();
- if (ret)
- return ret;
-
- /* We enable only RX here */
- /* ASTP : Enable Automatic Pad Stripping
- PR : Promiscuous Mode for test
- PSF : Receive frames with total length less than 64 bytes.
- FDMODE : Full Duplex Mode
- LB : Internal Loopback for test
- RE : Receiver Enable */
- opmode = bfin_read_EMAC_OPMODE();
- if (opmode & FDMODE)
- opmode |= PSF;
- else
- opmode |= DRO | DC | PSF;
- opmode |= RE;
-
- if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
- opmode |= RMII; /* For Now only 100MBit are supported */
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
- if (__SILICON_REVISION__ < 3) {
- /*
- * This isn't publicly documented (fun times!), but in
- * silicon <=0.2, the RX and TX pins are clocked together.
- * So in order to recv, we must enable the transmit side
- * as well. This will cause a spurious TX interrupt too,
- * but we can easily consume that.
- */
- opmode |= TE;
- }
-#endif
- }
-
- /* Turn on the EMAC rx */
- bfin_write_EMAC_OPMODE(opmode);
-
- return 0;
-}
-
-/* Our watchdog timed out. Called by the networking layer */
-static void bfin_mac_timeout(struct net_device *dev)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
-
- pr_debug("%s: %s\n", dev->name, __func__);
-
- bfin_mac_disable();
-
- del_timer(&lp->tx_reclaim_timer);
-
- /* reset tx queue and free skb */
- while (tx_list_head != current_tx_ptr) {
- tx_list_head->desc_a.config &= ~DMAEN;
- tx_list_head->status.status_word = 0;
- if (tx_list_head->skb) {
- dev_kfree_skb(tx_list_head->skb);
- tx_list_head->skb = NULL;
- }
- tx_list_head = tx_list_head->next;
- }
-
- if (netif_queue_stopped(dev))
- netif_wake_queue(dev);
-
- bfin_mac_enable(dev->phydev);
-
- /* We can accept TX packets again */
- netif_trans_update(dev); /* prevent tx timeout */
-}
-
-static void bfin_mac_multicast_hash(struct net_device *dev)
-{
- u32 emac_hashhi, emac_hashlo;
- struct netdev_hw_addr *ha;
- u32 crc;
-
- emac_hashhi = emac_hashlo = 0;
-
- netdev_for_each_mc_addr(ha, dev) {
- crc = ether_crc(ETH_ALEN, ha->addr);
- crc >>= 26;
-
- if (crc & 0x20)
- emac_hashhi |= 1 << (crc & 0x1f);
- else
- emac_hashlo |= 1 << (crc & 0x1f);
- }
-
- bfin_write_EMAC_HASHHI(emac_hashhi);
- bfin_write_EMAC_HASHLO(emac_hashlo);
-}
-
-/*
- * This routine will, depending on the values passed to it,
- * either make it accept multicast packets, go into
- * promiscuous mode (for TCPDUMP and cousins) or accept
- * a select set of multicast packets
- */
-static void bfin_mac_set_multicast_list(struct net_device *dev)
-{
- u32 sysctl;
-
- if (dev->flags & IFF_PROMISC) {
- netdev_info(dev, "set promisc mode\n");
- sysctl = bfin_read_EMAC_OPMODE();
- sysctl |= PR;
- bfin_write_EMAC_OPMODE(sysctl);
- } else if (dev->flags & IFF_ALLMULTI) {
- /* accept all multicast */
- sysctl = bfin_read_EMAC_OPMODE();
- sysctl |= PAM;
- bfin_write_EMAC_OPMODE(sysctl);
- } else if (!netdev_mc_empty(dev)) {
- /* set up multicast hash table */
- sysctl = bfin_read_EMAC_OPMODE();
- sysctl |= HM;
- bfin_write_EMAC_OPMODE(sysctl);
- bfin_mac_multicast_hash(dev);
- } else {
- /* clear promisc or multicast mode */
- sysctl = bfin_read_EMAC_OPMODE();
- sysctl &= ~(RAF | PAM);
- bfin_write_EMAC_OPMODE(sysctl);
- }
-}
-
-static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
-{
- if (!netif_running(netdev))
- return -EINVAL;
-
- switch (cmd) {
- case SIOCSHWTSTAMP:
- return bfin_mac_hwtstamp_set(netdev, ifr);
- case SIOCGHWTSTAMP:
- return bfin_mac_hwtstamp_get(netdev, ifr);
- default:
- if (netdev->phydev)
- return phy_mii_ioctl(netdev->phydev, ifr, cmd);
- else
- return -EOPNOTSUPP;
- }
-}
-
-/*
- * this puts the device in an inactive state
- */
-static void bfin_mac_shutdown(struct net_device *dev)
-{
- /* Turn off the EMAC */
- bfin_write_EMAC_OPMODE(0x00000000);
- /* Turn off the EMAC RX DMA */
- bfin_write_DMA1_CONFIG(0x0000);
- bfin_write_DMA2_CONFIG(0x0000);
-}
-
-/*
- * Open and Initialize the interface
- *
- * Set up everything, reset the card, etc..
- */
-static int bfin_mac_open(struct net_device *dev)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
- int ret;
- pr_debug("%s: %s\n", dev->name, __func__);
-
- /*
- * Check that the address is valid. If its not, refuse
- * to bring the device up. The user must specify an
- * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
- */
- if (!is_valid_ether_addr(dev->dev_addr)) {
- netdev_warn(dev, "no valid ethernet hw addr\n");
- return -EINVAL;
- }
-
- /* initial rx and tx list */
- ret = desc_list_init(dev);
- if (ret)
- return ret;
-
- phy_start(dev->phydev);
- setup_system_regs(dev);
- setup_mac_addr(dev->dev_addr);
-
- bfin_mac_disable();
- ret = bfin_mac_enable(dev->phydev);
- if (ret)
- return ret;
- pr_debug("hardware init finished\n");
-
- napi_enable(&lp->napi);
- netif_start_queue(dev);
- netif_carrier_on(dev);
-
- return 0;
-}
-
-/*
- * this makes the board clean up everything that it can
- * and not talk to the outside world. Caused by
- * an 'ifconfig ethX down'
- */
-static int bfin_mac_close(struct net_device *dev)
-{
- struct bfin_mac_local *lp = netdev_priv(dev);
- pr_debug("%s: %s\n", dev->name, __func__);
-
- netif_stop_queue(dev);
- napi_disable(&lp->napi);
- netif_carrier_off(dev);
-
- phy_stop(dev->phydev);
- phy_write(dev->phydev, MII_BMCR, BMCR_PDOWN);
-
- /* clear everything */
- bfin_mac_shutdown(dev);
-
- /* free the rx/tx buffers */
- desc_list_free();
-
- return 0;
-}
-
-static const struct net_device_ops bfin_mac_netdev_ops = {
- .ndo_open = bfin_mac_open,
- .ndo_stop = bfin_mac_close,
- .ndo_start_xmit = bfin_mac_hard_start_xmit,
- .ndo_set_mac_address = bfin_mac_set_mac_address,
- .ndo_tx_timeout = bfin_mac_timeout,
- .ndo_set_rx_mode = bfin_mac_set_multicast_list,
- .ndo_do_ioctl = bfin_mac_ioctl,
- .ndo_validate_addr = eth_validate_addr,
-#ifdef CONFIG_NET_POLL_CONTROLLER
- .ndo_poll_controller = bfin_mac_poll_controller,
-#endif
-};
-
-static int bfin_mac_probe(struct platform_device *pdev)
-{
- struct net_device *ndev;
- struct bfin_mac_local *lp;
- struct platform_device *pd;
- struct bfin_mii_bus_platform_data *mii_bus_data;
- int rc;
-
- ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
- if (!ndev)
- return -ENOMEM;
-
- SET_NETDEV_DEV(ndev, &pdev->dev);
- platform_set_drvdata(pdev, ndev);
- lp = netdev_priv(ndev);
- lp->ndev = ndev;
-
- /* Grab the MAC address in the MAC */
- *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
- *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
-
- /* probe mac */
- /*todo: how to probe? which is revision_register */
- bfin_write_EMAC_ADDRLO(0x12345678);
- if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
- dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
- rc = -ENODEV;
- goto out_err_probe_mac;
- }
-
-
- /*
- * Is it valid? (Did bootloader initialize it?)
- * Grab the MAC from the board somehow
- * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
- */
- if (!is_valid_ether_addr(ndev->dev_addr)) {
- if (bfin_get_ether_addr(ndev->dev_addr) ||
- !is_valid_ether_addr(ndev->dev_addr)) {
- /* Still not valid, get a random one */
- netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
- eth_hw_addr_random(ndev);
- }
- }
-
- setup_mac_addr(ndev->dev_addr);
-
- if (!dev_get_platdata(&pdev->dev)) {
- dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
- rc = -ENODEV;
- goto out_err_probe_mac;
- }
- pd = dev_get_platdata(&pdev->dev);
- lp->mii_bus = platform_get_drvdata(pd);
- if (!lp->mii_bus) {
- dev_err(&pdev->dev, "Cannot get mii_bus!\n");
- rc = -ENODEV;
- goto out_err_probe_mac;
- }
- lp->mii_bus->priv = ndev;
- mii_bus_data = dev_get_platdata(&pd->dev);
-
- rc = mii_probe(ndev, mii_bus_data->phy_mode);
- if (rc) {
- dev_err(&pdev->dev, "MII Probe failed!\n");
- goto out_err_mii_probe;
- }
-
- lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
- lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
-
- ndev->netdev_ops = &bfin_mac_netdev_ops;
- ndev->ethtool_ops = &bfin_mac_ethtool_ops;
-
- timer_setup(&lp->tx_reclaim_timer, tx_reclaim_skb_timeout, 0);
-
- lp->flags = 0;
- netif_napi_add(ndev, &lp->napi, bfin_mac_poll, CONFIG_BFIN_RX_DESC_NUM);
-
- spin_lock_init(&lp->lock);
-
- /* now, enable interrupts */
- /* register irq handler */
- rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
- 0, "EMAC_RX", ndev);
- if (rc) {
- dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
- rc = -EBUSY;
- goto out_err_request_irq;
- }
-
- rc = register_netdev(ndev);
- if (rc) {
- dev_err(&pdev->dev, "Cannot register net device!\n");
- goto out_err_reg_ndev;
- }
-
- bfin_mac_hwtstamp_init(ndev);
- rc = bfin_phc_init(ndev, &pdev->dev);
- if (rc) {
- dev_err(&pdev->dev, "Cannot register PHC device!\n");
- goto out_err_phc;
- }
-
- /* now, print out the card info, in a short format.. */
- netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
-
- return 0;
-
-out_err_phc:
-out_err_reg_ndev:
- free_irq(IRQ_MAC_RX, ndev);
-out_err_request_irq:
- netif_napi_del(&lp->napi);
-out_err_mii_probe:
- mdiobus_unregister(lp->mii_bus);
- mdiobus_free(lp->mii_bus);
-out_err_probe_mac:
- free_netdev(ndev);
-
- return rc;
-}
-
-static int bfin_mac_remove(struct platform_device *pdev)
-{
- struct net_device *ndev = platform_get_drvdata(pdev);
- struct bfin_mac_local *lp = netdev_priv(ndev);
-
- bfin_phc_release(lp);
-
- lp->mii_bus->priv = NULL;
-
- unregister_netdev(ndev);
-
- netif_napi_del(&lp->napi);
-
- free_irq(IRQ_MAC_RX, ndev);
-
- free_netdev(ndev);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
-{
- struct net_device *net_dev = platform_get_drvdata(pdev);
- struct bfin_mac_local *lp = netdev_priv(net_dev);
-
- if (lp->wol) {
- bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
- bfin_write_EMAC_WKUP_CTL(MPKE);
- enable_irq_wake(IRQ_MAC_WAKEDET);
- } else {
- if (netif_running(net_dev))
- bfin_mac_close(net_dev);
- }
-
- return 0;
-}
-
-static int bfin_mac_resume(struct platform_device *pdev)
-{
- struct net_device *net_dev = platform_get_drvdata(pdev);
- struct bfin_mac_local *lp = netdev_priv(net_dev);
-
- if (lp->wol) {
- bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
- bfin_write_EMAC_WKUP_CTL(0);
- disable_irq_wake(IRQ_MAC_WAKEDET);
- } else {
- if (netif_running(net_dev))
- bfin_mac_open(net_dev);
- }
-
- return 0;
-}
-#else
-#define bfin_mac_suspend NULL
-#define bfin_mac_resume NULL
-#endif /* CONFIG_PM */
-
-static int bfin_mii_bus_probe(struct platform_device *pdev)
-{
- struct mii_bus *miibus;
- struct bfin_mii_bus_platform_data *mii_bus_pd;
- const unsigned short *pin_req;
- int rc, i;
-
- mii_bus_pd = dev_get_platdata(&pdev->dev);
- if (!mii_bus_pd) {
- dev_err(&pdev->dev, "No peripherals in platform data!\n");
- return -EINVAL;
- }
-
- /*
- * We are setting up a network card,
- * so set the GPIO pins to Ethernet mode
- */
- pin_req = mii_bus_pd->mac_peripherals;
- rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
- if (rc) {
- dev_err(&pdev->dev, "Requesting peripherals failed!\n");
- return rc;
- }
-
- rc = -ENOMEM;
- miibus = mdiobus_alloc();
- if (miibus == NULL)
- goto out_err_alloc;
- miibus->read = bfin_mdiobus_read;
- miibus->write = bfin_mdiobus_write;
-
- miibus->parent = &pdev->dev;
- miibus->name = "bfin_mii_bus";
- miibus->phy_mask = mii_bus_pd->phy_mask;
-
- snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
- pdev->name, pdev->id);
-
- rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
- if (rc != mii_bus_pd->phydev_number)
- dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
- mii_bus_pd->phydev_number);
- for (i = 0; i < rc; ++i) {
- unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
- if (phyaddr < PHY_MAX_ADDR)
- miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
- else
- dev_err(&pdev->dev,
- "Invalid PHY address %i for phydev %i\n",
- phyaddr, i);
- }
-
- rc = mdiobus_register(miibus);
- if (rc) {
- dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
- goto out_err_irq_alloc;
- }
-
- platform_set_drvdata(pdev, miibus);
- return 0;
-
-out_err_irq_alloc:
- mdiobus_free(miibus);
-out_err_alloc:
- peripheral_free_list(pin_req);
-
- return rc;
-}
-
-static int bfin_mii_bus_remove(struct platform_device *pdev)
-{
- struct mii_bus *miibus = platform_get_drvdata(pdev);
- struct bfin_mii_bus_platform_data *mii_bus_pd =
- dev_get_platdata(&pdev->dev);
-
- mdiobus_unregister(miibus);
- mdiobus_free(miibus);
- peripheral_free_list(mii_bus_pd->mac_peripherals);
-
- return 0;
-}
-
-static struct platform_driver bfin_mii_bus_driver = {
- .probe = bfin_mii_bus_probe,
- .remove = bfin_mii_bus_remove,
- .driver = {
- .name = "bfin_mii_bus",
- },
-};
-
-static struct platform_driver bfin_mac_driver = {
- .probe = bfin_mac_probe,
- .remove = bfin_mac_remove,
- .resume = bfin_mac_resume,
- .suspend = bfin_mac_suspend,
- .driver = {
- .name = KBUILD_MODNAME,
- },
-};
-
-static struct platform_driver * const drivers[] = {
- &bfin_mii_bus_driver,
- &bfin_mac_driver,
-};
-
-static int __init bfin_mac_init(void)
-{
- return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
-}
-
-module_init(bfin_mac_init);
-
-static void __exit bfin_mac_cleanup(void)
-{
- platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
-}
-
-module_exit(bfin_mac_cleanup);
-
diff --git a/drivers/net/ethernet/adi/bfin_mac.h b/drivers/net/ethernet/adi/bfin_mac.h
deleted file mode 100644
index 4ad5b9b..0000000
--- a/drivers/net/ethernet/adi/bfin_mac.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Blackfin On-Chip MAC Driver
- *
- * Copyright 2004-2007 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef _BFIN_MAC_H_
-#define _BFIN_MAC_H_
-
-#include <linux/net_tstamp.h>
-#include <linux/ptp_clock_kernel.h>
-#include <linux/timer.h>
-#include <linux/etherdevice.h>
-#include <linux/bfin_mac.h>
-
-/*
- * Disable hardware checksum for bug #5600 if writeback cache is
- * enabled. Otherwize, corrupted RX packet will be sent up stack
- * without error mark.
- */
-#ifndef CONFIG_BFIN_EXTMEM_WRITEBACK
-#define BFIN_MAC_CSUM_OFFLOAD
-#endif
-
-#define TX_RECLAIM_JIFFIES (HZ / 5)
-#define BFIN_MAC_RX_IRQ_DISABLED 1
-
-struct dma_descriptor {
- struct dma_descriptor *next_dma_desc;
- unsigned long start_addr;
- unsigned short config;
- unsigned short x_count;
-};
-
-struct status_area_rx {
-#if defined(BFIN_MAC_CSUM_OFFLOAD)
- unsigned short ip_hdr_csum; /* ip header checksum */
- /* ip payload(udp or tcp or others) checksum */
- unsigned short ip_payload_csum;
-#endif
- unsigned long status_word; /* the frame status word */
-};
-
-struct status_area_tx {
- unsigned long status_word; /* the frame status word */
-};
-
-/* use two descriptors for a packet */
-struct net_dma_desc_rx {
- struct net_dma_desc_rx *next;
- struct sk_buff *skb;
- struct dma_descriptor desc_a;
- struct dma_descriptor desc_b;
- struct status_area_rx status;
-};
-
-/* use two descriptors for a packet */
-struct net_dma_desc_tx {
- struct net_dma_desc_tx *next;
- struct sk_buff *skb;
- struct dma_descriptor desc_a;
- struct dma_descriptor desc_b;
- unsigned char packet[1560];
- struct status_area_tx status;
-};
-
-struct bfin_mac_local {
- spinlock_t lock;
-
- int wol; /* Wake On Lan */
- int irq_wake_requested;
- struct timer_list tx_reclaim_timer;
- struct net_device *ndev;
- struct napi_struct napi;
- unsigned long flags;
-
- /* Data for EMAC_VLAN1 regs */
- u16 vlan1_mask, vlan2_mask;
-
- /* MII and PHY stuffs */
- int old_link; /* used by bf537_adjust_link */
- int old_speed;
- int old_duplex;
-
- struct mii_bus *mii_bus;
-
-#if defined(CONFIG_BFIN_MAC_USE_HWSTAMP)
- u32 addend;
- unsigned int shift;
- s32 max_ppb;
- struct hwtstamp_config stamp_cfg;
- struct ptp_clock_info caps;
- struct ptp_clock *clock;
- int phc_index;
- spinlock_t phc_lock; /* protects time lo/hi registers */
-#endif
-};
-
-int bfin_get_ether_addr(char *addr);
-
-#endif
diff --git a/drivers/net/ethernet/davicom/Kconfig b/drivers/net/ethernet/davicom/Kconfig
index 7ec2d74..680a6d9 100644
--- a/drivers/net/ethernet/davicom/Kconfig
+++ b/drivers/net/ethernet/davicom/Kconfig
@@ -4,7 +4,7 @@
config DM9000
tristate "DM9000 support"
- depends on ARM || BLACKFIN || MIPS || COLDFIRE || NIOS2
+ depends on ARM || MIPS || COLDFIRE || NIOS2
select CRC32
select MII
---help---
diff --git a/drivers/net/ethernet/smsc/Kconfig b/drivers/net/ethernet/smsc/Kconfig
index 4c2f612e..aefa001 100644
--- a/drivers/net/ethernet/smsc/Kconfig
+++ b/drivers/net/ethernet/smsc/Kconfig
@@ -5,7 +5,7 @@
config NET_VENDOR_SMSC
bool "SMC (SMSC)/Western Digital devices"
default y
- depends on ARM || ARM64 || ATARI_ETHERNAT || BLACKFIN || COLDFIRE || \
+ depends on ARM || ARM64 || ATARI_ETHERNAT || COLDFIRE || \
ISA || M32R || MAC || MIPS || MN10300 || NIOS2 || PCI || \
PCMCIA || SUPERH || XTENSA || H8300
---help---
@@ -37,7 +37,7 @@ config SMC91X
select CRC32
select MII
depends on !OF || GPIOLIB
- depends on ARM || ARM64 || ATARI_ETHERNAT || BLACKFIN || COLDFIRE || \
+ depends on ARM || ARM64 || ATARI_ETHERNAT || COLDFIRE || \
M32R || MIPS || MN10300 || NIOS2 || SUPERH || XTENSA || H8300
---help---
This is a driver for SMC's 91x series of Ethernet chipsets,
diff --git a/include/linux/bfin_mac.h b/include/linux/bfin_mac.h
deleted file mode 100644
index a69554e..0000000
--- a/include/linux/bfin_mac.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Blackfin On-Chip MAC Driver
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _LINUX_BFIN_MAC_H_
-#define _LINUX_BFIN_MAC_H_
-
-#include <linux/phy.h>
-
-struct bfin_phydev_platform_data {
- unsigned short addr;
- int irq;
-};
-
-struct bfin_mii_bus_platform_data {
- int phydev_number;
- struct bfin_phydev_platform_data *phydev_data;
- const unsigned short *mac_peripherals;
- int phy_mode;
- unsigned int phy_mask;
- unsigned short vlan1_mask, vlan2_mask;
-};
-
-#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 03/28] media: Remove Blackfin media support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 02/28] net: Remove Blackfin Ethernet support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 04/28] tty: Remove Blackfin tty and uart support Aaron Wu
` (24 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin media support
---
drivers/media/platform/Kconfig | 2 -
drivers/media/platform/Makefile | 2 -
drivers/media/platform/blackfin/Kconfig | 16 -
drivers/media/platform/blackfin/Makefile | 2 -
drivers/media/platform/blackfin/bfin_capture.c | 989 -------------------------
drivers/media/platform/blackfin/ppi.c | 361 ---------
include/media/blackfin/bfin_capture.h | 39 -
include/media/blackfin/ppi.h | 94 ---
8 files changed, 1505 deletions(-)
delete mode 100644 drivers/media/platform/blackfin/Kconfig
delete mode 100644 drivers/media/platform/blackfin/Makefile
delete mode 100644 drivers/media/platform/blackfin/bfin_capture.c
delete mode 100644 drivers/media/platform/blackfin/ppi.c
delete mode 100644 include/media/blackfin/bfin_capture.h
delete mode 100644 include/media/blackfin/ppi.h
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 614fbef..00158b3 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -31,8 +31,6 @@ source "drivers/media/platform/davinci/Kconfig"
source "drivers/media/platform/omap/Kconfig"
-source "drivers/media/platform/blackfin/Kconfig"
-
config VIDEO_SH_VOU
tristate "SuperH VOU video output driver"
depends on MEDIA_CAMERA_SUPPORT
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 7f30804..e2b5cb3 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -53,8 +53,6 @@ obj-$(CONFIG_VIDEO_TEGRA_HDMI_CEC) += tegra-cec/
obj-y += stm32/
-obj-y += blackfin/
-
obj-y += davinci/
obj-$(CONFIG_VIDEO_SH_VOU) += sh_vou.o
diff --git a/drivers/media/platform/blackfin/Kconfig b/drivers/media/platform/blackfin/Kconfig
deleted file mode 100644
index 68fa901..0000000
--- a/drivers/media/platform/blackfin/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-config VIDEO_BLACKFIN_CAPTURE
- tristate "Blackfin Video Capture Driver"
- depends on VIDEO_V4L2 && BLACKFIN && I2C
- depends on HAS_DMA
- select VIDEOBUF2_DMA_CONTIG
- help
- V4L2 bridge driver for Blackfin video capture device.
- Choose PPI or EPPI as its interface.
-
- To compile this driver as a module, choose M here: the
- module will be called bfin_capture.
-
-config VIDEO_BLACKFIN_PPI
- tristate
- depends on VIDEO_BLACKFIN_CAPTURE
- default VIDEO_BLACKFIN_CAPTURE
diff --git a/drivers/media/platform/blackfin/Makefile b/drivers/media/platform/blackfin/Makefile
deleted file mode 100644
index 30421bc..0000000
--- a/drivers/media/platform/blackfin/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-$(CONFIG_VIDEO_BLACKFIN_CAPTURE) += bfin_capture.o
-obj-$(CONFIG_VIDEO_BLACKFIN_PPI) += ppi.o
diff --git a/drivers/media/platform/blackfin/bfin_capture.c b/drivers/media/platform/blackfin/bfin_capture.c
deleted file mode 100644
index 41f1791..0000000
--- a/drivers/media/platform/blackfin/bfin_capture.c
+++ /dev/null
@@ -1,989 +0,0 @@
-/*
- * Analog Devices video capture driver
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/completion.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/time.h>
-#include <linux/types.h>
-
-#include <media/v4l2-common.h>
-#include <media/v4l2-ctrls.h>
-#include <media/v4l2-device.h>
-#include <media/v4l2-ioctl.h>
-#include <media/videobuf2-dma-contig.h>
-
-#include <asm/dma.h>
-
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-#define CAPTURE_DRV_NAME "bfin_capture"
-
-struct bcap_format {
- char *desc;
- u32 pixelformat;
- u32 mbus_code;
- int bpp; /* bits per pixel */
- int dlen; /* data length for ppi in bits */
-};
-
-struct bcap_buffer {
- struct vb2_v4l2_buffer vb;
- struct list_head list;
-};
-
-struct bcap_device {
- /* capture device instance */
- struct v4l2_device v4l2_dev;
- /* v4l2 control handler */
- struct v4l2_ctrl_handler ctrl_handler;
- /* device node data */
- struct video_device video_dev;
- /* sub device instance */
- struct v4l2_subdev *sd;
- /* capture config */
- struct bfin_capture_config *cfg;
- /* ppi interface */
- struct ppi_if *ppi;
- /* current input */
- unsigned int cur_input;
- /* current selected standard */
- v4l2_std_id std;
- /* current selected dv_timings */
- struct v4l2_dv_timings dv_timings;
- /* used to store pixel format */
- struct v4l2_pix_format fmt;
- /* bits per pixel*/
- int bpp;
- /* data length for ppi in bits */
- int dlen;
- /* used to store sensor supported format */
- struct bcap_format *sensor_formats;
- /* number of sensor formats array */
- int num_sensor_formats;
- /* pointing to current video buffer */
- struct bcap_buffer *cur_frm;
- /* buffer queue used in videobuf2 */
- struct vb2_queue buffer_queue;
- /* queue of filled frames */
- struct list_head dma_queue;
- /* used in videobuf2 callback */
- spinlock_t lock;
- /* used to access capture device */
- struct mutex mutex;
- /* used to wait ppi to complete one transfer */
- struct completion comp;
- /* prepare to stop */
- bool stop;
- /* vb2 buffer sequence counter */
- unsigned sequence;
-};
-
-static const struct bcap_format bcap_formats[] = {
- {
- .desc = "YCbCr 4:2:2 Interleaved UYVY",
- .pixelformat = V4L2_PIX_FMT_UYVY,
- .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
- .bpp = 16,
- .dlen = 8,
- },
- {
- .desc = "YCbCr 4:2:2 Interleaved YUYV",
- .pixelformat = V4L2_PIX_FMT_YUYV,
- .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
- .bpp = 16,
- .dlen = 8,
- },
- {
- .desc = "YCbCr 4:2:2 Interleaved UYVY",
- .pixelformat = V4L2_PIX_FMT_UYVY,
- .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16,
- .bpp = 16,
- .dlen = 16,
- },
- {
- .desc = "RGB 565",
- .pixelformat = V4L2_PIX_FMT_RGB565,
- .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
- .bpp = 16,
- .dlen = 8,
- },
- {
- .desc = "RGB 444",
- .pixelformat = V4L2_PIX_FMT_RGB444,
- .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
- .bpp = 16,
- .dlen = 8,
- },
-
-};
-#define BCAP_MAX_FMTS ARRAY_SIZE(bcap_formats)
-
-static irqreturn_t bcap_isr(int irq, void *dev_id);
-
-static struct bcap_buffer *to_bcap_vb(struct vb2_v4l2_buffer *vb)
-{
- return container_of(vb, struct bcap_buffer, vb);
-}
-
-static int bcap_init_sensor_formats(struct bcap_device *bcap_dev)
-{
- struct v4l2_subdev_mbus_code_enum code = {
- .which = V4L2_SUBDEV_FORMAT_ACTIVE,
- };
- struct bcap_format *sf;
- unsigned int num_formats = 0;
- int i, j;
-
- while (!v4l2_subdev_call(bcap_dev->sd, pad,
- enum_mbus_code, NULL, &code)) {
- num_formats++;
- code.index++;
- }
- if (!num_formats)
- return -ENXIO;
-
- sf = kcalloc(num_formats, sizeof(*sf), GFP_KERNEL);
- if (!sf)
- return -ENOMEM;
-
- for (i = 0; i < num_formats; i++) {
- code.index = i;
- v4l2_subdev_call(bcap_dev->sd, pad,
- enum_mbus_code, NULL, &code);
- for (j = 0; j < BCAP_MAX_FMTS; j++)
- if (code.code == bcap_formats[j].mbus_code)
- break;
- if (j == BCAP_MAX_FMTS) {
- /* we don't allow this sensor working with our bridge */
- kfree(sf);
- return -EINVAL;
- }
- sf[i] = bcap_formats[j];
- }
- bcap_dev->sensor_formats = sf;
- bcap_dev->num_sensor_formats = num_formats;
- return 0;
-}
-
-static void bcap_free_sensor_formats(struct bcap_device *bcap_dev)
-{
- bcap_dev->num_sensor_formats = 0;
- kfree(bcap_dev->sensor_formats);
- bcap_dev->sensor_formats = NULL;
-}
-
-static int bcap_queue_setup(struct vb2_queue *vq,
- unsigned int *nbuffers, unsigned int *nplanes,
- unsigned int sizes[], struct device *alloc_devs[])
-{
- struct bcap_device *bcap_dev = vb2_get_drv_priv(vq);
-
- if (vq->num_buffers + *nbuffers < 2)
- *nbuffers = 2;
-
- if (*nplanes)
- return sizes[0] < bcap_dev->fmt.sizeimage ? -EINVAL : 0;
-
- *nplanes = 1;
- sizes[0] = bcap_dev->fmt.sizeimage;
-
- return 0;
-}
-
-static int bcap_buffer_prepare(struct vb2_buffer *vb)
-{
- struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
- struct bcap_device *bcap_dev = vb2_get_drv_priv(vb->vb2_queue);
- unsigned long size = bcap_dev->fmt.sizeimage;
-
- if (vb2_plane_size(vb, 0) < size) {
- v4l2_err(&bcap_dev->v4l2_dev, "buffer too small (%lu < %lu)\n",
- vb2_plane_size(vb, 0), size);
- return -EINVAL;
- }
- vb2_set_plane_payload(vb, 0, size);
-
- vbuf->field = bcap_dev->fmt.field;
-
- return 0;
-}
-
-static void bcap_buffer_queue(struct vb2_buffer *vb)
-{
- struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
- struct bcap_device *bcap_dev = vb2_get_drv_priv(vb->vb2_queue);
- struct bcap_buffer *buf = to_bcap_vb(vbuf);
- unsigned long flags;
-
- spin_lock_irqsave(&bcap_dev->lock, flags);
- list_add_tail(&buf->list, &bcap_dev->dma_queue);
- spin_unlock_irqrestore(&bcap_dev->lock, flags);
-}
-
-static void bcap_buffer_cleanup(struct vb2_buffer *vb)
-{
- struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
- struct bcap_device *bcap_dev = vb2_get_drv_priv(vb->vb2_queue);
- struct bcap_buffer *buf = to_bcap_vb(vbuf);
- unsigned long flags;
-
- spin_lock_irqsave(&bcap_dev->lock, flags);
- list_del_init(&buf->list);
- spin_unlock_irqrestore(&bcap_dev->lock, flags);
-}
-
-static int bcap_start_streaming(struct vb2_queue *vq, unsigned int count)
-{
- struct bcap_device *bcap_dev = vb2_get_drv_priv(vq);
- struct ppi_if *ppi = bcap_dev->ppi;
- struct bcap_buffer *buf, *tmp;
- struct ppi_params params;
- dma_addr_t addr;
- int ret;
-
- /* enable streamon on the sub device */
- ret = v4l2_subdev_call(bcap_dev->sd, video, s_stream, 1);
- if (ret && (ret != -ENOIOCTLCMD)) {
- v4l2_err(&bcap_dev->v4l2_dev, "stream on failed in subdev\n");
- goto err;
- }
-
- /* set ppi params */
- params.width = bcap_dev->fmt.width;
- params.height = bcap_dev->fmt.height;
- params.bpp = bcap_dev->bpp;
- params.dlen = bcap_dev->dlen;
- params.ppi_control = bcap_dev->cfg->ppi_control;
- params.int_mask = bcap_dev->cfg->int_mask;
- if (bcap_dev->cfg->inputs[bcap_dev->cur_input].capabilities
- & V4L2_IN_CAP_DV_TIMINGS) {
- struct v4l2_bt_timings *bt = &bcap_dev->dv_timings.bt;
-
- params.hdelay = bt->hsync + bt->hbackporch;
- params.vdelay = bt->vsync + bt->vbackporch;
- params.line = V4L2_DV_BT_FRAME_WIDTH(bt);
- params.frame = V4L2_DV_BT_FRAME_HEIGHT(bt);
- } else if (bcap_dev->cfg->inputs[bcap_dev->cur_input].capabilities
- & V4L2_IN_CAP_STD) {
- params.hdelay = 0;
- params.vdelay = 0;
- if (bcap_dev->std & V4L2_STD_525_60) {
- params.line = 858;
- params.frame = 525;
- } else {
- params.line = 864;
- params.frame = 625;
- }
- } else {
- params.hdelay = 0;
- params.vdelay = 0;
- params.line = params.width + bcap_dev->cfg->blank_pixels;
- params.frame = params.height;
- }
- ret = ppi->ops->set_params(ppi, ¶ms);
- if (ret < 0) {
- v4l2_err(&bcap_dev->v4l2_dev,
- "Error in setting ppi params\n");
- goto err;
- }
-
- /* attach ppi DMA irq handler */
- ret = ppi->ops->attach_irq(ppi, bcap_isr);
- if (ret < 0) {
- v4l2_err(&bcap_dev->v4l2_dev,
- "Error in attaching interrupt handler\n");
- goto err;
- }
-
- bcap_dev->sequence = 0;
-
- reinit_completion(&bcap_dev->comp);
- bcap_dev->stop = false;
-
- /* get the next frame from the dma queue */
- bcap_dev->cur_frm = list_entry(bcap_dev->dma_queue.next,
- struct bcap_buffer, list);
- /* remove buffer from the dma queue */
- list_del_init(&bcap_dev->cur_frm->list);
- addr = vb2_dma_contig_plane_dma_addr(&bcap_dev->cur_frm->vb.vb2_buf,
- 0);
- /* update DMA address */
- ppi->ops->update_addr(ppi, (unsigned long)addr);
- /* enable ppi */
- ppi->ops->start(ppi);
-
- return 0;
-
-err:
- list_for_each_entry_safe(buf, tmp, &bcap_dev->dma_queue, list) {
- list_del(&buf->list);
- vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
- }
-
- return ret;
-}
-
-static void bcap_stop_streaming(struct vb2_queue *vq)
-{
- struct bcap_device *bcap_dev = vb2_get_drv_priv(vq);
- struct ppi_if *ppi = bcap_dev->ppi;
- int ret;
-
- bcap_dev->stop = true;
- wait_for_completion(&bcap_dev->comp);
- ppi->ops->stop(ppi);
- ppi->ops->detach_irq(ppi);
- ret = v4l2_subdev_call(bcap_dev->sd, video, s_stream, 0);
- if (ret && (ret != -ENOIOCTLCMD))
- v4l2_err(&bcap_dev->v4l2_dev,
- "stream off failed in subdev\n");
-
- /* release all active buffers */
- if (bcap_dev->cur_frm)
- vb2_buffer_done(&bcap_dev->cur_frm->vb.vb2_buf,
- VB2_BUF_STATE_ERROR);
-
- while (!list_empty(&bcap_dev->dma_queue)) {
- bcap_dev->cur_frm = list_entry(bcap_dev->dma_queue.next,
- struct bcap_buffer, list);
- list_del_init(&bcap_dev->cur_frm->list);
- vb2_buffer_done(&bcap_dev->cur_frm->vb.vb2_buf,
- VB2_BUF_STATE_ERROR);
- }
-}
-
-static const struct vb2_ops bcap_video_qops = {
- .queue_setup = bcap_queue_setup,
- .buf_prepare = bcap_buffer_prepare,
- .buf_cleanup = bcap_buffer_cleanup,
- .buf_queue = bcap_buffer_queue,
- .wait_prepare = vb2_ops_wait_prepare,
- .wait_finish = vb2_ops_wait_finish,
- .start_streaming = bcap_start_streaming,
- .stop_streaming = bcap_stop_streaming,
-};
-
-static irqreturn_t bcap_isr(int irq, void *dev_id)
-{
- struct ppi_if *ppi = dev_id;
- struct bcap_device *bcap_dev = ppi->priv;
- struct vb2_v4l2_buffer *vbuf = &bcap_dev->cur_frm->vb;
- struct vb2_buffer *vb = &vbuf->vb2_buf;
- dma_addr_t addr;
-
- spin_lock(&bcap_dev->lock);
-
- if (!list_empty(&bcap_dev->dma_queue)) {
- vb->timestamp = ktime_get_ns();
- if (ppi->err) {
- vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
- ppi->err = false;
- } else {
- vbuf->sequence = bcap_dev->sequence++;
- vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
- }
- bcap_dev->cur_frm = list_entry(bcap_dev->dma_queue.next,
- struct bcap_buffer, list);
- list_del_init(&bcap_dev->cur_frm->list);
- } else {
- /* clear error flag, we will get a new frame */
- if (ppi->err)
- ppi->err = false;
- }
-
- ppi->ops->stop(ppi);
-
- if (bcap_dev->stop) {
- complete(&bcap_dev->comp);
- } else {
- addr = vb2_dma_contig_plane_dma_addr(
- &bcap_dev->cur_frm->vb.vb2_buf, 0);
- ppi->ops->update_addr(ppi, (unsigned long)addr);
- ppi->ops->start(ppi);
- }
-
- spin_unlock(&bcap_dev->lock);
-
- return IRQ_HANDLED;
-}
-
-static int bcap_querystd(struct file *file, void *priv, v4l2_std_id *std)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct v4l2_input input;
-
- input = bcap_dev->cfg->inputs[bcap_dev->cur_input];
- if (!(input.capabilities & V4L2_IN_CAP_STD))
- return -ENODATA;
-
- return v4l2_subdev_call(bcap_dev->sd, video, querystd, std);
-}
-
-static int bcap_g_std(struct file *file, void *priv, v4l2_std_id *std)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct v4l2_input input;
-
- input = bcap_dev->cfg->inputs[bcap_dev->cur_input];
- if (!(input.capabilities & V4L2_IN_CAP_STD))
- return -ENODATA;
-
- *std = bcap_dev->std;
- return 0;
-}
-
-static int bcap_s_std(struct file *file, void *priv, v4l2_std_id std)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct v4l2_input input;
- int ret;
-
- input = bcap_dev->cfg->inputs[bcap_dev->cur_input];
- if (!(input.capabilities & V4L2_IN_CAP_STD))
- return -ENODATA;
-
- if (vb2_is_busy(&bcap_dev->buffer_queue))
- return -EBUSY;
-
- ret = v4l2_subdev_call(bcap_dev->sd, video, s_std, std);
- if (ret < 0)
- return ret;
-
- bcap_dev->std = std;
- return 0;
-}
-
-static int bcap_enum_dv_timings(struct file *file, void *priv,
- struct v4l2_enum_dv_timings *timings)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct v4l2_input input;
-
- input = bcap_dev->cfg->inputs[bcap_dev->cur_input];
- if (!(input.capabilities & V4L2_IN_CAP_DV_TIMINGS))
- return -ENODATA;
-
- timings->pad = 0;
-
- return v4l2_subdev_call(bcap_dev->sd, pad,
- enum_dv_timings, timings);
-}
-
-static int bcap_query_dv_timings(struct file *file, void *priv,
- struct v4l2_dv_timings *timings)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct v4l2_input input;
-
- input = bcap_dev->cfg->inputs[bcap_dev->cur_input];
- if (!(input.capabilities & V4L2_IN_CAP_DV_TIMINGS))
- return -ENODATA;
-
- return v4l2_subdev_call(bcap_dev->sd, video,
- query_dv_timings, timings);
-}
-
-static int bcap_g_dv_timings(struct file *file, void *priv,
- struct v4l2_dv_timings *timings)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct v4l2_input input;
-
- input = bcap_dev->cfg->inputs[bcap_dev->cur_input];
- if (!(input.capabilities & V4L2_IN_CAP_DV_TIMINGS))
- return -ENODATA;
-
- *timings = bcap_dev->dv_timings;
- return 0;
-}
-
-static int bcap_s_dv_timings(struct file *file, void *priv,
- struct v4l2_dv_timings *timings)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct v4l2_input input;
- int ret;
-
- input = bcap_dev->cfg->inputs[bcap_dev->cur_input];
- if (!(input.capabilities & V4L2_IN_CAP_DV_TIMINGS))
- return -ENODATA;
-
- if (vb2_is_busy(&bcap_dev->buffer_queue))
- return -EBUSY;
-
- ret = v4l2_subdev_call(bcap_dev->sd, video, s_dv_timings, timings);
- if (ret < 0)
- return ret;
-
- bcap_dev->dv_timings = *timings;
- return 0;
-}
-
-static int bcap_enum_input(struct file *file, void *priv,
- struct v4l2_input *input)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct bfin_capture_config *config = bcap_dev->cfg;
- int ret;
- u32 status;
-
- if (input->index >= config->num_inputs)
- return -EINVAL;
-
- *input = config->inputs[input->index];
- /* get input status */
- ret = v4l2_subdev_call(bcap_dev->sd, video, g_input_status, &status);
- if (!ret)
- input->status = status;
- return 0;
-}
-
-static int bcap_g_input(struct file *file, void *priv, unsigned int *index)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
-
- *index = bcap_dev->cur_input;
- return 0;
-}
-
-static int bcap_s_input(struct file *file, void *priv, unsigned int index)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct bfin_capture_config *config = bcap_dev->cfg;
- struct bcap_route *route;
- int ret;
-
- if (vb2_is_busy(&bcap_dev->buffer_queue))
- return -EBUSY;
-
- if (index >= config->num_inputs)
- return -EINVAL;
-
- route = &config->routes[index];
- ret = v4l2_subdev_call(bcap_dev->sd, video, s_routing,
- route->input, route->output, 0);
- if ((ret < 0) && (ret != -ENOIOCTLCMD)) {
- v4l2_err(&bcap_dev->v4l2_dev, "Failed to set input\n");
- return ret;
- }
- bcap_dev->cur_input = index;
- /* if this route has specific config, update ppi control */
- if (route->ppi_control)
- config->ppi_control = route->ppi_control;
- return 0;
-}
-
-static int bcap_try_format(struct bcap_device *bcap,
- struct v4l2_pix_format *pixfmt,
- struct bcap_format *bcap_fmt)
-{
- struct bcap_format *sf = bcap->sensor_formats;
- struct bcap_format *fmt = NULL;
- struct v4l2_subdev_pad_config pad_cfg;
- struct v4l2_subdev_format format = {
- .which = V4L2_SUBDEV_FORMAT_TRY,
- };
- int ret, i;
-
- for (i = 0; i < bcap->num_sensor_formats; i++) {
- fmt = &sf[i];
- if (pixfmt->pixelformat == fmt->pixelformat)
- break;
- }
- if (i == bcap->num_sensor_formats)
- fmt = &sf[0];
-
- v4l2_fill_mbus_format(&format.format, pixfmt, fmt->mbus_code);
- ret = v4l2_subdev_call(bcap->sd, pad, set_fmt, &pad_cfg,
- &format);
- if (ret < 0)
- return ret;
- v4l2_fill_pix_format(pixfmt, &format.format);
- if (bcap_fmt) {
- for (i = 0; i < bcap->num_sensor_formats; i++) {
- fmt = &sf[i];
- if (format.format.code == fmt->mbus_code)
- break;
- }
- *bcap_fmt = *fmt;
- }
- pixfmt->bytesperline = pixfmt->width * fmt->bpp / 8;
- pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
- return 0;
-}
-
-static int bcap_enum_fmt_vid_cap(struct file *file, void *priv,
- struct v4l2_fmtdesc *fmt)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct bcap_format *sf = bcap_dev->sensor_formats;
-
- if (fmt->index >= bcap_dev->num_sensor_formats)
- return -EINVAL;
-
- fmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- strlcpy(fmt->description,
- sf[fmt->index].desc,
- sizeof(fmt->description));
- fmt->pixelformat = sf[fmt->index].pixelformat;
- return 0;
-}
-
-static int bcap_try_fmt_vid_cap(struct file *file, void *priv,
- struct v4l2_format *fmt)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct v4l2_pix_format *pixfmt = &fmt->fmt.pix;
-
- return bcap_try_format(bcap_dev, pixfmt, NULL);
-}
-
-static int bcap_g_fmt_vid_cap(struct file *file, void *priv,
- struct v4l2_format *fmt)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
-
- fmt->fmt.pix = bcap_dev->fmt;
- return 0;
-}
-
-static int bcap_s_fmt_vid_cap(struct file *file, void *priv,
- struct v4l2_format *fmt)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- struct v4l2_subdev_format format = {
- .which = V4L2_SUBDEV_FORMAT_ACTIVE,
- };
- struct bcap_format bcap_fmt;
- struct v4l2_pix_format *pixfmt = &fmt->fmt.pix;
- int ret;
-
- if (vb2_is_busy(&bcap_dev->buffer_queue))
- return -EBUSY;
-
- /* see if format works */
- ret = bcap_try_format(bcap_dev, pixfmt, &bcap_fmt);
- if (ret < 0)
- return ret;
-
- v4l2_fill_mbus_format(&format.format, pixfmt, bcap_fmt.mbus_code);
- ret = v4l2_subdev_call(bcap_dev->sd, pad, set_fmt, NULL, &format);
- if (ret < 0)
- return ret;
- bcap_dev->fmt = *pixfmt;
- bcap_dev->bpp = bcap_fmt.bpp;
- bcap_dev->dlen = bcap_fmt.dlen;
- return 0;
-}
-
-static int bcap_querycap(struct file *file, void *priv,
- struct v4l2_capability *cap)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
-
- cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
- cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
- strlcpy(cap->driver, CAPTURE_DRV_NAME, sizeof(cap->driver));
- strlcpy(cap->bus_info, "Blackfin Platform", sizeof(cap->bus_info));
- strlcpy(cap->card, bcap_dev->cfg->card_name, sizeof(cap->card));
- return 0;
-}
-
-static int bcap_g_parm(struct file *file, void *fh,
- struct v4l2_streamparm *a)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
-
- if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
- return -EINVAL;
- return v4l2_subdev_call(bcap_dev->sd, video, g_parm, a);
-}
-
-static int bcap_s_parm(struct file *file, void *fh,
- struct v4l2_streamparm *a)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
-
- if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
- return -EINVAL;
- return v4l2_subdev_call(bcap_dev->sd, video, s_parm, a);
-}
-
-static int bcap_log_status(struct file *file, void *priv)
-{
- struct bcap_device *bcap_dev = video_drvdata(file);
- /* status for sub devices */
- v4l2_device_call_all(&bcap_dev->v4l2_dev, 0, core, log_status);
- return 0;
-}
-
-static const struct v4l2_ioctl_ops bcap_ioctl_ops = {
- .vidioc_querycap = bcap_querycap,
- .vidioc_g_fmt_vid_cap = bcap_g_fmt_vid_cap,
- .vidioc_enum_fmt_vid_cap = bcap_enum_fmt_vid_cap,
- .vidioc_s_fmt_vid_cap = bcap_s_fmt_vid_cap,
- .vidioc_try_fmt_vid_cap = bcap_try_fmt_vid_cap,
- .vidioc_enum_input = bcap_enum_input,
- .vidioc_g_input = bcap_g_input,
- .vidioc_s_input = bcap_s_input,
- .vidioc_querystd = bcap_querystd,
- .vidioc_s_std = bcap_s_std,
- .vidioc_g_std = bcap_g_std,
- .vidioc_s_dv_timings = bcap_s_dv_timings,
- .vidioc_g_dv_timings = bcap_g_dv_timings,
- .vidioc_query_dv_timings = bcap_query_dv_timings,
- .vidioc_enum_dv_timings = bcap_enum_dv_timings,
- .vidioc_reqbufs = vb2_ioctl_reqbufs,
- .vidioc_create_bufs = vb2_ioctl_create_bufs,
- .vidioc_querybuf = vb2_ioctl_querybuf,
- .vidioc_qbuf = vb2_ioctl_qbuf,
- .vidioc_dqbuf = vb2_ioctl_dqbuf,
- .vidioc_expbuf = vb2_ioctl_expbuf,
- .vidioc_streamon = vb2_ioctl_streamon,
- .vidioc_streamoff = vb2_ioctl_streamoff,
- .vidioc_g_parm = bcap_g_parm,
- .vidioc_s_parm = bcap_s_parm,
- .vidioc_log_status = bcap_log_status,
-};
-
-static const struct v4l2_file_operations bcap_fops = {
- .owner = THIS_MODULE,
- .open = v4l2_fh_open,
- .release = vb2_fop_release,
- .unlocked_ioctl = video_ioctl2,
- .mmap = vb2_fop_mmap,
-#ifndef CONFIG_MMU
- .get_unmapped_area = vb2_fop_get_unmapped_area,
-#endif
- .poll = vb2_fop_poll
-};
-
-static int bcap_probe(struct platform_device *pdev)
-{
- struct bcap_device *bcap_dev;
- struct video_device *vfd;
- struct i2c_adapter *i2c_adap;
- struct bfin_capture_config *config;
- struct vb2_queue *q;
- struct bcap_route *route;
- int ret;
-
- config = pdev->dev.platform_data;
- if (!config || !config->num_inputs) {
- v4l2_err(pdev->dev.driver, "Unable to get board config\n");
- return -ENODEV;
- }
-
- bcap_dev = kzalloc(sizeof(*bcap_dev), GFP_KERNEL);
- if (!bcap_dev)
- return -ENOMEM;
-
- bcap_dev->cfg = config;
-
- bcap_dev->ppi = ppi_create_instance(pdev, config->ppi_info);
- if (!bcap_dev->ppi) {
- v4l2_err(pdev->dev.driver, "Unable to create ppi\n");
- ret = -ENODEV;
- goto err_free_dev;
- }
- bcap_dev->ppi->priv = bcap_dev;
-
- vfd = &bcap_dev->video_dev;
- /* initialize field of video device */
- vfd->release = video_device_release_empty;
- vfd->fops = &bcap_fops;
- vfd->ioctl_ops = &bcap_ioctl_ops;
- vfd->tvnorms = 0;
- vfd->v4l2_dev = &bcap_dev->v4l2_dev;
- strncpy(vfd->name, CAPTURE_DRV_NAME, sizeof(vfd->name));
-
- ret = v4l2_device_register(&pdev->dev, &bcap_dev->v4l2_dev);
- if (ret) {
- v4l2_err(pdev->dev.driver,
- "Unable to register v4l2 device\n");
- goto err_free_ppi;
- }
- v4l2_info(&bcap_dev->v4l2_dev, "v4l2 device registered\n");
-
- bcap_dev->v4l2_dev.ctrl_handler = &bcap_dev->ctrl_handler;
- ret = v4l2_ctrl_handler_init(&bcap_dev->ctrl_handler, 0);
- if (ret) {
- v4l2_err(&bcap_dev->v4l2_dev,
- "Unable to init control handler\n");
- goto err_unreg_v4l2;
- }
-
- spin_lock_init(&bcap_dev->lock);
- /* initialize queue */
- q = &bcap_dev->buffer_queue;
- q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- q->io_modes = VB2_MMAP | VB2_DMABUF;
- q->drv_priv = bcap_dev;
- q->buf_struct_size = sizeof(struct bcap_buffer);
- q->ops = &bcap_video_qops;
- q->mem_ops = &vb2_dma_contig_memops;
- q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
- q->lock = &bcap_dev->mutex;
- q->min_buffers_needed = 1;
- q->dev = &pdev->dev;
-
- ret = vb2_queue_init(q);
- if (ret)
- goto err_free_handler;
-
- mutex_init(&bcap_dev->mutex);
- init_completion(&bcap_dev->comp);
-
- /* init video dma queues */
- INIT_LIST_HEAD(&bcap_dev->dma_queue);
-
- vfd->lock = &bcap_dev->mutex;
- vfd->queue = q;
-
- /* register video device */
- ret = video_register_device(&bcap_dev->video_dev, VFL_TYPE_GRABBER, -1);
- if (ret) {
- v4l2_err(&bcap_dev->v4l2_dev,
- "Unable to register video device\n");
- goto err_free_handler;
- }
- video_set_drvdata(&bcap_dev->video_dev, bcap_dev);
- v4l2_info(&bcap_dev->v4l2_dev, "video device registered as: %s\n",
- video_device_node_name(vfd));
-
- /* load up the subdevice */
- i2c_adap = i2c_get_adapter(config->i2c_adapter_id);
- if (!i2c_adap) {
- v4l2_err(&bcap_dev->v4l2_dev,
- "Unable to find i2c adapter\n");
- ret = -ENODEV;
- goto err_unreg_vdev;
-
- }
- bcap_dev->sd = v4l2_i2c_new_subdev_board(&bcap_dev->v4l2_dev,
- i2c_adap,
- &config->board_info,
- NULL);
- if (bcap_dev->sd) {
- int i;
-
- /* update tvnorms from the sub devices */
- for (i = 0; i < config->num_inputs; i++)
- vfd->tvnorms |= config->inputs[i].std;
- } else {
- v4l2_err(&bcap_dev->v4l2_dev,
- "Unable to register sub device\n");
- ret = -ENODEV;
- goto err_unreg_vdev;
- }
-
- v4l2_info(&bcap_dev->v4l2_dev, "v4l2 sub device registered\n");
-
- /*
- * explicitly set input, otherwise some boards
- * may not work at the state as we expected
- */
- route = &config->routes[0];
- ret = v4l2_subdev_call(bcap_dev->sd, video, s_routing,
- route->input, route->output, 0);
- if ((ret < 0) && (ret != -ENOIOCTLCMD)) {
- v4l2_err(&bcap_dev->v4l2_dev, "Failed to set input\n");
- goto err_unreg_vdev;
- }
- bcap_dev->cur_input = 0;
- /* if this route has specific config, update ppi control */
- if (route->ppi_control)
- config->ppi_control = route->ppi_control;
-
- /* now we can probe the default state */
- if (config->inputs[0].capabilities & V4L2_IN_CAP_STD) {
- v4l2_std_id std;
- ret = v4l2_subdev_call(bcap_dev->sd, video, g_std, &std);
- if (ret) {
- v4l2_err(&bcap_dev->v4l2_dev,
- "Unable to get std\n");
- goto err_unreg_vdev;
- }
- bcap_dev->std = std;
- }
- if (config->inputs[0].capabilities & V4L2_IN_CAP_DV_TIMINGS) {
- struct v4l2_dv_timings dv_timings;
- ret = v4l2_subdev_call(bcap_dev->sd, video,
- g_dv_timings, &dv_timings);
- if (ret) {
- v4l2_err(&bcap_dev->v4l2_dev,
- "Unable to get dv timings\n");
- goto err_unreg_vdev;
- }
- bcap_dev->dv_timings = dv_timings;
- }
- ret = bcap_init_sensor_formats(bcap_dev);
- if (ret) {
- v4l2_err(&bcap_dev->v4l2_dev,
- "Unable to create sensor formats table\n");
- goto err_unreg_vdev;
- }
- return 0;
-err_unreg_vdev:
- video_unregister_device(&bcap_dev->video_dev);
-err_free_handler:
- v4l2_ctrl_handler_free(&bcap_dev->ctrl_handler);
-err_unreg_v4l2:
- v4l2_device_unregister(&bcap_dev->v4l2_dev);
-err_free_ppi:
- ppi_delete_instance(bcap_dev->ppi);
-err_free_dev:
- kfree(bcap_dev);
- return ret;
-}
-
-static int bcap_remove(struct platform_device *pdev)
-{
- struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
- struct bcap_device *bcap_dev = container_of(v4l2_dev,
- struct bcap_device, v4l2_dev);
-
- bcap_free_sensor_formats(bcap_dev);
- video_unregister_device(&bcap_dev->video_dev);
- v4l2_ctrl_handler_free(&bcap_dev->ctrl_handler);
- v4l2_device_unregister(v4l2_dev);
- ppi_delete_instance(bcap_dev->ppi);
- kfree(bcap_dev);
- return 0;
-}
-
-static struct platform_driver bcap_driver = {
- .driver = {
- .name = CAPTURE_DRV_NAME,
- },
- .probe = bcap_probe,
- .remove = bcap_remove,
-};
-module_platform_driver(bcap_driver);
-
-MODULE_DESCRIPTION("Analog Devices blackfin video capture driver");
-MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/platform/blackfin/ppi.c b/drivers/media/platform/blackfin/ppi.c
deleted file mode 100644
index d3dc765..0000000
--- a/drivers/media/platform/blackfin/ppi.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * ppi.c Analog Devices Parallel Peripheral Interface driver
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-
-#include <asm/bfin_ppi.h>
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#include <media/blackfin/ppi.h>
-
-static int ppi_attach_irq(struct ppi_if *ppi, irq_handler_t handler);
-static void ppi_detach_irq(struct ppi_if *ppi);
-static int ppi_start(struct ppi_if *ppi);
-static int ppi_stop(struct ppi_if *ppi);
-static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params);
-static void ppi_update_addr(struct ppi_if *ppi, unsigned long addr);
-
-static const struct ppi_ops ppi_ops = {
- .attach_irq = ppi_attach_irq,
- .detach_irq = ppi_detach_irq,
- .start = ppi_start,
- .stop = ppi_stop,
- .set_params = ppi_set_params,
- .update_addr = ppi_update_addr,
-};
-
-static irqreturn_t ppi_irq_err(int irq, void *dev_id)
-{
- struct ppi_if *ppi = dev_id;
- const struct ppi_info *info = ppi->info;
-
- switch (info->type) {
- case PPI_TYPE_PPI:
- {
- struct bfin_ppi_regs *reg = info->base;
- unsigned short status;
-
- /* register on bf561 is cleared when read
- * others are W1C
- */
- status = bfin_read16(®->status);
- if (status & 0x3000)
- ppi->err = true;
- bfin_write16(®->status, 0xff00);
- break;
- }
- case PPI_TYPE_EPPI:
- {
- struct bfin_eppi_regs *reg = info->base;
- unsigned short status;
-
- status = bfin_read16(®->status);
- if (status & 0x2)
- ppi->err = true;
- bfin_write16(®->status, 0xffff);
- break;
- }
- case PPI_TYPE_EPPI3:
- {
- struct bfin_eppi3_regs *reg = info->base;
- unsigned long stat;
-
- stat = bfin_read32(®->stat);
- if (stat & 0x2)
- ppi->err = true;
- bfin_write32(®->stat, 0xc0ff);
- break;
- }
- default:
- break;
- }
-
- return IRQ_HANDLED;
-}
-
-static int ppi_attach_irq(struct ppi_if *ppi, irq_handler_t handler)
-{
- const struct ppi_info *info = ppi->info;
- int ret;
-
- ret = request_dma(info->dma_ch, "PPI_DMA");
-
- if (ret) {
- pr_err("Unable to allocate DMA channel for PPI\n");
- return ret;
- }
- set_dma_callback(info->dma_ch, handler, ppi);
-
- if (ppi->err_int) {
- ret = request_irq(info->irq_err, ppi_irq_err, 0, "PPI ERROR", ppi);
- if (ret) {
- pr_err("Unable to allocate IRQ for PPI\n");
- free_dma(info->dma_ch);
- }
- }
- return ret;
-}
-
-static void ppi_detach_irq(struct ppi_if *ppi)
-{
- const struct ppi_info *info = ppi->info;
-
- if (ppi->err_int)
- free_irq(info->irq_err, ppi);
- free_dma(info->dma_ch);
-}
-
-static int ppi_start(struct ppi_if *ppi)
-{
- const struct ppi_info *info = ppi->info;
-
- /* enable DMA */
- enable_dma(info->dma_ch);
-
- /* enable PPI */
- ppi->ppi_control |= PORT_EN;
- switch (info->type) {
- case PPI_TYPE_PPI:
- {
- struct bfin_ppi_regs *reg = info->base;
- bfin_write16(®->control, ppi->ppi_control);
- break;
- }
- case PPI_TYPE_EPPI:
- {
- struct bfin_eppi_regs *reg = info->base;
- bfin_write32(®->control, ppi->ppi_control);
- break;
- }
- case PPI_TYPE_EPPI3:
- {
- struct bfin_eppi3_regs *reg = info->base;
- bfin_write32(®->ctl, ppi->ppi_control);
- break;
- }
- default:
- return -EINVAL;
- }
-
- SSYNC();
- return 0;
-}
-
-static int ppi_stop(struct ppi_if *ppi)
-{
- const struct ppi_info *info = ppi->info;
-
- /* disable PPI */
- ppi->ppi_control &= ~PORT_EN;
- switch (info->type) {
- case PPI_TYPE_PPI:
- {
- struct bfin_ppi_regs *reg = info->base;
- bfin_write16(®->control, ppi->ppi_control);
- break;
- }
- case PPI_TYPE_EPPI:
- {
- struct bfin_eppi_regs *reg = info->base;
- bfin_write32(®->control, ppi->ppi_control);
- break;
- }
- case PPI_TYPE_EPPI3:
- {
- struct bfin_eppi3_regs *reg = info->base;
- bfin_write32(®->ctl, ppi->ppi_control);
- break;
- }
- default:
- return -EINVAL;
- }
-
- /* disable DMA */
- clear_dma_irqstat(info->dma_ch);
- disable_dma(info->dma_ch);
-
- SSYNC();
- return 0;
-}
-
-static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params)
-{
- const struct ppi_info *info = ppi->info;
- int dma32 = 0;
- int dma_config, bytes_per_line;
- int hcount, hdelay, samples_per_line;
-
-#ifdef CONFIG_PINCTRL
- static const char * const pin_state[] = {"8bit", "16bit", "24bit"};
- struct pinctrl *pctrl;
- struct pinctrl_state *pstate;
-
- if (params->dlen > 24 || params->dlen <= 0)
- return -EINVAL;
- pctrl = devm_pinctrl_get(ppi->dev);
- if (IS_ERR(pctrl))
- return PTR_ERR(pctrl);
- pstate = pinctrl_lookup_state(pctrl,
- pin_state[(params->dlen + 7) / 8 - 1]);
- if (pinctrl_select_state(pctrl, pstate))
- return -EINVAL;
-#endif
-
- bytes_per_line = params->width * params->bpp / 8;
- /* convert parameters unit from pixels to samples */
- hcount = params->width * params->bpp / params->dlen;
- hdelay = params->hdelay * params->bpp / params->dlen;
- samples_per_line = params->line * params->bpp / params->dlen;
- if (params->int_mask == 0xFFFFFFFF)
- ppi->err_int = false;
- else
- ppi->err_int = true;
-
- dma_config = (DMA_FLOW_STOP | RESTART | DMA2D | DI_EN_Y);
- ppi->ppi_control = params->ppi_control & ~PORT_EN;
- if (!(ppi->ppi_control & PORT_DIR))
- dma_config |= WNR;
- switch (info->type) {
- case PPI_TYPE_PPI:
- {
- struct bfin_ppi_regs *reg = info->base;
-
- if (params->ppi_control & DMA32)
- dma32 = 1;
-
- bfin_write16(®->control, ppi->ppi_control);
- bfin_write16(®->count, samples_per_line - 1);
- bfin_write16(®->frame, params->frame);
- break;
- }
- case PPI_TYPE_EPPI:
- {
- struct bfin_eppi_regs *reg = info->base;
-
- if ((params->ppi_control & PACK_EN)
- || (params->ppi_control & 0x38000) > DLEN_16)
- dma32 = 1;
-
- bfin_write32(®->control, ppi->ppi_control);
- bfin_write16(®->line, samples_per_line);
- bfin_write16(®->frame, params->frame);
- bfin_write16(®->hdelay, hdelay);
- bfin_write16(®->vdelay, params->vdelay);
- bfin_write16(®->hcount, hcount);
- bfin_write16(®->vcount, params->height);
- break;
- }
- case PPI_TYPE_EPPI3:
- {
- struct bfin_eppi3_regs *reg = info->base;
-
- if ((params->ppi_control & PACK_EN)
- || (params->ppi_control & 0x70000) > DLEN_16)
- dma32 = 1;
-
- bfin_write32(®->ctl, ppi->ppi_control);
- bfin_write32(®->line, samples_per_line);
- bfin_write32(®->frame, params->frame);
- bfin_write32(®->hdly, hdelay);
- bfin_write32(®->vdly, params->vdelay);
- bfin_write32(®->hcnt, hcount);
- bfin_write32(®->vcnt, params->height);
- if (params->int_mask)
- bfin_write32(®->imsk, params->int_mask & 0xFF);
- if (ppi->ppi_control & PORT_DIR) {
- u32 hsync_width, vsync_width, vsync_period;
-
- hsync_width = params->hsync
- * params->bpp / params->dlen;
- vsync_width = params->vsync * samples_per_line;
- vsync_period = samples_per_line * params->frame;
- bfin_write32(®->fs1_wlhb, hsync_width);
- bfin_write32(®->fs1_paspl, samples_per_line);
- bfin_write32(®->fs2_wlvb, vsync_width);
- bfin_write32(®->fs2_palpf, vsync_period);
- }
- break;
- }
- default:
- return -EINVAL;
- }
-
- if (dma32) {
- dma_config |= WDSIZE_32 | PSIZE_32;
- set_dma_x_count(info->dma_ch, bytes_per_line >> 2);
- set_dma_x_modify(info->dma_ch, 4);
- set_dma_y_modify(info->dma_ch, 4);
- } else {
- dma_config |= WDSIZE_16 | PSIZE_16;
- set_dma_x_count(info->dma_ch, bytes_per_line >> 1);
- set_dma_x_modify(info->dma_ch, 2);
- set_dma_y_modify(info->dma_ch, 2);
- }
- set_dma_y_count(info->dma_ch, params->height);
- set_dma_config(info->dma_ch, dma_config);
-
- SSYNC();
- return 0;
-}
-
-static void ppi_update_addr(struct ppi_if *ppi, unsigned long addr)
-{
- set_dma_start_addr(ppi->info->dma_ch, addr);
-}
-
-struct ppi_if *ppi_create_instance(struct platform_device *pdev,
- const struct ppi_info *info)
-{
- struct ppi_if *ppi;
-
- if (!info || !info->pin_req)
- return NULL;
-
-#ifndef CONFIG_PINCTRL
- if (peripheral_request_list(info->pin_req, KBUILD_MODNAME)) {
- dev_err(&pdev->dev, "request peripheral failed\n");
- return NULL;
- }
-#endif
-
- ppi = kzalloc(sizeof(*ppi), GFP_KERNEL);
- if (!ppi) {
- peripheral_free_list(info->pin_req);
- return NULL;
- }
- ppi->ops = &ppi_ops;
- ppi->info = info;
- ppi->dev = &pdev->dev;
-
- pr_info("ppi probe success\n");
- return ppi;
-}
-EXPORT_SYMBOL(ppi_create_instance);
-
-void ppi_delete_instance(struct ppi_if *ppi)
-{
- peripheral_free_list(ppi->info->pin_req);
- kfree(ppi);
-}
-EXPORT_SYMBOL(ppi_delete_instance);
-
-MODULE_DESCRIPTION("Analog Devices PPI driver");
-MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
-MODULE_LICENSE("GPL v2");
diff --git a/include/media/blackfin/bfin_capture.h b/include/media/blackfin/bfin_capture.h
deleted file mode 100644
index a999a397..0000000
--- a/include/media/blackfin/bfin_capture.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _BFIN_CAPTURE_H_
-#define _BFIN_CAPTURE_H_
-
-#include <linux/i2c.h>
-
-struct v4l2_input;
-struct ppi_info;
-
-struct bcap_route {
- u32 input;
- u32 output;
- u32 ppi_control;
-};
-
-struct bfin_capture_config {
- /* card name */
- char *card_name;
- /* inputs available at the sub device */
- struct v4l2_input *inputs;
- /* number of inputs supported */
- int num_inputs;
- /* routing information for each input */
- struct bcap_route *routes;
- /* i2c bus adapter no */
- int i2c_adapter_id;
- /* i2c subdevice board info */
- struct i2c_board_info board_info;
- /* ppi board info */
- const struct ppi_info *ppi_info;
- /* ppi control */
- unsigned long ppi_control;
- /* ppi interrupt mask */
- u32 int_mask;
- /* horizontal blanking pixels */
- int blank_pixels;
-};
-
-#endif
diff --git a/include/media/blackfin/ppi.h b/include/media/blackfin/ppi.h
deleted file mode 100644
index 987e49e..0000000
--- a/include/media/blackfin/ppi.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Analog Devices PPI header file
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _PPI_H_
-#define _PPI_H_
-
-#include <linux/interrupt.h>
-#include <asm/blackfin.h>
-#include <asm/bfin_ppi.h>
-
-/* EPPI */
-#ifdef EPPI_EN
-#define PORT_EN EPPI_EN
-#define PORT_DIR EPPI_DIR
-#define DMA32 0
-#define PACK_EN PACKEN
-#endif
-
-/* EPPI3 */
-#ifdef EPPI0_CTL2
-#define PORT_EN EPPI_CTL_EN
-#define PORT_DIR EPPI_CTL_DIR
-#define PACK_EN EPPI_CTL_PACKEN
-#define DMA32 0
-#define DLEN_8 EPPI_CTL_DLEN08
-#define DLEN_16 EPPI_CTL_DLEN16
-#endif
-
-struct ppi_if;
-
-struct ppi_params {
- u32 width; /* width in pixels */
- u32 height; /* height in lines */
- u32 hdelay; /* delay after the HSYNC in pixels */
- u32 vdelay; /* delay after the VSYNC in lines */
- u32 line; /* total pixels per line */
- u32 frame; /* total lines per frame */
- u32 hsync; /* HSYNC length in pixels */
- u32 vsync; /* VSYNC length in lines */
- int bpp; /* bits per pixel */
- int dlen; /* data length for ppi in bits */
- u32 ppi_control; /* ppi configuration */
- u32 int_mask; /* interrupt mask */
-};
-
-struct ppi_ops {
- int (*attach_irq)(struct ppi_if *ppi, irq_handler_t handler);
- void (*detach_irq)(struct ppi_if *ppi);
- int (*start)(struct ppi_if *ppi);
- int (*stop)(struct ppi_if *ppi);
- int (*set_params)(struct ppi_if *ppi, struct ppi_params *params);
- void (*update_addr)(struct ppi_if *ppi, unsigned long addr);
-};
-
-enum ppi_type {
- PPI_TYPE_PPI,
- PPI_TYPE_EPPI,
- PPI_TYPE_EPPI3,
-};
-
-struct ppi_info {
- enum ppi_type type;
- int dma_ch;
- int irq_err;
- void __iomem *base;
- const unsigned short *pin_req;
-};
-
-struct ppi_if {
- struct device *dev;
- unsigned long ppi_control;
- const struct ppi_ops *ops;
- const struct ppi_info *info;
- bool err_int; /* if we need request error interrupt */
- bool err; /* if ppi has fifo error */
- void *priv;
-};
-
-struct ppi_if *ppi_create_instance(struct platform_device *pdev,
- const struct ppi_info *info);
-void ppi_delete_instance(struct ppi_if *ppi);
-#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 04/28] tty: Remove Blackfin tty and uart support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 02/28] net: Remove Blackfin Ethernet support Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 03/28] media: Remove Blackfin media support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 05/28] rtc: Remove Blackfin RTC support Aaron Wu
` (23 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin tty and uart support
---
drivers/tty/Kconfig | 13 -
drivers/tty/Makefile | 1 -
drivers/tty/bfin_jtag_comm.c | 353 --------
drivers/tty/hvc/Kconfig | 9 -
drivers/tty/hvc/Makefile | 1 -
drivers/tty/hvc/hvc_bfin_jtag.c | 104 ---
drivers/tty/serial/Kconfig | 149 ----
drivers/tty/serial/Makefile | 2 -
drivers/tty/serial/bfin_sport_uart.c | 937 --------------------
drivers/tty/serial/bfin_sport_uart.h | 86 --
drivers/tty/serial/bfin_uart.c | 1551 ----------------------------------
include/uapi/linux/serial_core.h | 6 -
12 files changed, 3212 deletions(-)
delete mode 100644 drivers/tty/bfin_jtag_comm.c
delete mode 100644 drivers/tty/hvc/hvc_bfin_jtag.c
delete mode 100644 drivers/tty/serial/bfin_sport_uart.c
delete mode 100644 drivers/tty/serial/bfin_sport_uart.h
delete mode 100644 drivers/tty/serial/bfin_uart.c
diff --git a/drivers/tty/Kconfig b/drivers/tty/Kconfig
index b811442..f298179 100644
--- a/drivers/tty/Kconfig
+++ b/drivers/tty/Kconfig
@@ -151,19 +151,6 @@ config LEGACY_PTY_COUNT
When not in use, each legacy PTY occupies 12 bytes on 32-bit
architectures and 24 bytes on 64-bit architectures.
-config BFIN_JTAG_COMM
- tristate "Blackfin JTAG Communication"
- depends on BLACKFIN
- help
- Add support for emulating a TTY device over the Blackfin JTAG.
-
- To compile this driver as a module, choose M here: the
- module will be called bfin_jtag_comm.
-
-config BFIN_JTAG_COMM_CONSOLE
- bool "Console on Blackfin JTAG"
- depends on BFIN_JTAG_COMM=y
-
config SERIAL_NONSTANDARD
bool "Non-standard serial port support"
depends on HAS_IOMEM
diff --git a/drivers/tty/Makefile b/drivers/tty/Makefile
index 8ce3a86..42054c7 100644
--- a/drivers/tty/Makefile
+++ b/drivers/tty/Makefile
@@ -20,7 +20,6 @@ obj-$(CONFIG_SERIAL_DEV_BUS) += serdev/
# tty drivers
obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
-obj-$(CONFIG_BFIN_JTAG_COMM) += bfin_jtag_comm.o
obj-$(CONFIG_CYCLADES) += cyclades.o
obj-$(CONFIG_ISI) += isicom.o
obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
diff --git a/drivers/tty/bfin_jtag_comm.c b/drivers/tty/bfin_jtag_comm.c
deleted file mode 100644
index c369bf2..0000000
--- a/drivers/tty/bfin_jtag_comm.c
+++ /dev/null
@@ -1,353 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * TTY over Blackfin JTAG Communication
- *
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- */
-
-#define DRV_NAME "bfin-jtag-comm"
-#define DEV_NAME "ttyBFJC"
-#define pr_fmt(fmt) DRV_NAME ": " fmt
-
-#include <linux/circ_buf.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/kthread.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/tty.h>
-#include <linux/tty_driver.h>
-#include <linux/tty_flip.h>
-#include <linux/atomic.h>
-
-#define pr_init(fmt, args...) ({ static const __initconst char __fmt[] = fmt; printk(__fmt, ## args); })
-
-/* See the Debug/Emulation chapter in the HRM */
-#define EMUDOF 0x00000001 /* EMUDAT_OUT full & valid */
-#define EMUDIF 0x00000002 /* EMUDAT_IN full & valid */
-#define EMUDOOVF 0x00000004 /* EMUDAT_OUT overflow */
-#define EMUDIOVF 0x00000008 /* EMUDAT_IN overflow */
-
-static inline uint32_t bfin_write_emudat(uint32_t emudat)
-{
- __asm__ __volatile__("emudat = %0;" : : "d"(emudat));
- return emudat;
-}
-
-static inline uint32_t bfin_read_emudat(void)
-{
- uint32_t emudat;
- __asm__ __volatile__("%0 = emudat;" : "=d"(emudat));
- return emudat;
-}
-
-static inline uint32_t bfin_write_emudat_chars(char a, char b, char c, char d)
-{
- return bfin_write_emudat((a << 0) | (b << 8) | (c << 16) | (d << 24));
-}
-
-#define CIRC_SIZE 2048 /* see comment in tty_io.c:do_tty_write() */
-#define CIRC_MASK (CIRC_SIZE - 1)
-#define circ_empty(circ) ((circ)->head == (circ)->tail)
-#define circ_free(circ) CIRC_SPACE((circ)->head, (circ)->tail, CIRC_SIZE)
-#define circ_cnt(circ) CIRC_CNT((circ)->head, (circ)->tail, CIRC_SIZE)
-#define circ_byte(circ, idx) ((circ)->buf[(idx) & CIRC_MASK])
-
-static struct tty_driver *bfin_jc_driver;
-static struct task_struct *bfin_jc_kthread;
-static struct tty_port port;
-static volatile struct circ_buf bfin_jc_write_buf;
-
-static int
-bfin_jc_emudat_manager(void *arg)
-{
- uint32_t inbound_len = 0, outbound_len = 0;
-
- while (!kthread_should_stop()) {
- struct tty_struct *tty = tty_port_tty_get(&port);
- /* no one left to give data to, so sleep */
- if (tty == NULL && circ_empty(&bfin_jc_write_buf)) {
- pr_debug("waiting for readers\n");
- __set_current_state(TASK_UNINTERRUPTIBLE);
- schedule();
- continue;
- }
-
- /* no data available, so just chill */
- if (!(bfin_read_DBGSTAT() & EMUDIF) && circ_empty(&bfin_jc_write_buf)) {
- pr_debug("waiting for data (in_len = %i) (circ: %i %i)\n",
- inbound_len, bfin_jc_write_buf.tail, bfin_jc_write_buf.head);
- tty_kref_put(tty);
- if (inbound_len)
- schedule();
- else
- schedule_timeout_interruptible(HZ);
- continue;
- }
-
- /* if incoming data is ready, eat it */
- if (bfin_read_DBGSTAT() & EMUDIF) {
- uint32_t emudat = bfin_read_emudat();
- if (inbound_len == 0) {
- pr_debug("incoming length: 0x%08x\n", emudat);
- inbound_len = emudat;
- } else {
- size_t num_chars = (4 <= inbound_len ? 4 : inbound_len);
- pr_debug(" incoming data: 0x%08x (pushing %zu)\n", emudat, num_chars);
- inbound_len -= num_chars;
- tty_insert_flip_string(&port, (unsigned char *)&emudat, num_chars);
- tty_flip_buffer_push(&port);
- }
- }
-
- /* if outgoing data is ready, post it */
- if (!(bfin_read_DBGSTAT() & EMUDOF) && !circ_empty(&bfin_jc_write_buf)) {
- if (outbound_len == 0) {
- outbound_len = circ_cnt(&bfin_jc_write_buf);
- bfin_write_emudat(outbound_len);
- pr_debug("outgoing length: 0x%08x\n", outbound_len);
- } else {
- int tail = bfin_jc_write_buf.tail;
- size_t ate = (4 <= outbound_len ? 4 : outbound_len);
- uint32_t emudat =
- bfin_write_emudat_chars(
- circ_byte(&bfin_jc_write_buf, tail + 0),
- circ_byte(&bfin_jc_write_buf, tail + 1),
- circ_byte(&bfin_jc_write_buf, tail + 2),
- circ_byte(&bfin_jc_write_buf, tail + 3)
- );
- bfin_jc_write_buf.tail += ate;
- outbound_len -= ate;
- if (tty)
- tty_wakeup(tty);
- pr_debug(" outgoing data: 0x%08x (pushing %zu)\n", emudat, ate);
- }
- }
- tty_kref_put(tty);
- }
-
- __set_current_state(TASK_RUNNING);
- return 0;
-}
-
-static int
-bfin_jc_open(struct tty_struct *tty, struct file *filp)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&port.lock, flags);
- port.count++;
- spin_unlock_irqrestore(&port.lock, flags);
- tty_port_tty_set(&port, tty);
- wake_up_process(bfin_jc_kthread);
- return 0;
-}
-
-static void
-bfin_jc_close(struct tty_struct *tty, struct file *filp)
-{
- unsigned long flags;
- bool last;
-
- spin_lock_irqsave(&port.lock, flags);
- last = --port.count == 0;
- spin_unlock_irqrestore(&port.lock, flags);
- if (last)
- tty_port_tty_set(&port, NULL);
- wake_up_process(bfin_jc_kthread);
-}
-
-/* XXX: we dont handle the put_char() case where we must handle count = 1 */
-static int
-bfin_jc_circ_write(const unsigned char *buf, int count)
-{
- int i;
- count = min(count, circ_free(&bfin_jc_write_buf));
- pr_debug("going to write chunk of %i bytes\n", count);
- for (i = 0; i < count; ++i)
- circ_byte(&bfin_jc_write_buf, bfin_jc_write_buf.head + i) = buf[i];
- bfin_jc_write_buf.head += i;
- return i;
-}
-
-#ifndef CONFIG_BFIN_JTAG_COMM_CONSOLE
-# define console_lock()
-# define console_unlock()
-#endif
-static int
-bfin_jc_write(struct tty_struct *tty, const unsigned char *buf, int count)
-{
- int i;
- console_lock();
- i = bfin_jc_circ_write(buf, count);
- console_unlock();
- wake_up_process(bfin_jc_kthread);
- return i;
-}
-
-static void
-bfin_jc_flush_chars(struct tty_struct *tty)
-{
- wake_up_process(bfin_jc_kthread);
-}
-
-static int
-bfin_jc_write_room(struct tty_struct *tty)
-{
- return circ_free(&bfin_jc_write_buf);
-}
-
-static int
-bfin_jc_chars_in_buffer(struct tty_struct *tty)
-{
- return circ_cnt(&bfin_jc_write_buf);
-}
-
-static const struct tty_operations bfin_jc_ops = {
- .open = bfin_jc_open,
- .close = bfin_jc_close,
- .write = bfin_jc_write,
- /*.put_char = bfin_jc_put_char,*/
- .flush_chars = bfin_jc_flush_chars,
- .write_room = bfin_jc_write_room,
- .chars_in_buffer = bfin_jc_chars_in_buffer,
-};
-
-static int __init bfin_jc_init(void)
-{
- int ret;
-
- bfin_jc_kthread = kthread_create(bfin_jc_emudat_manager, NULL, DRV_NAME);
- if (IS_ERR(bfin_jc_kthread))
- return PTR_ERR(bfin_jc_kthread);
-
- ret = -ENOMEM;
-
- bfin_jc_write_buf.head = bfin_jc_write_buf.tail = 0;
- bfin_jc_write_buf.buf = kmalloc(CIRC_SIZE, GFP_KERNEL);
- if (!bfin_jc_write_buf.buf)
- goto err_buf;
-
- bfin_jc_driver = alloc_tty_driver(1);
- if (!bfin_jc_driver)
- goto err_driver;
-
- tty_port_init(&port);
-
- bfin_jc_driver->driver_name = DRV_NAME;
- bfin_jc_driver->name = DEV_NAME;
- bfin_jc_driver->type = TTY_DRIVER_TYPE_SERIAL;
- bfin_jc_driver->subtype = SERIAL_TYPE_NORMAL;
- bfin_jc_driver->init_termios = tty_std_termios;
- tty_set_operations(bfin_jc_driver, &bfin_jc_ops);
- tty_port_link_device(&port, bfin_jc_driver, 0);
-
- ret = tty_register_driver(bfin_jc_driver);
- if (ret)
- goto err;
-
- pr_init(KERN_INFO DRV_NAME ": initialized\n");
-
- return 0;
-
- err:
- tty_port_destroy(&port);
- put_tty_driver(bfin_jc_driver);
- err_driver:
- kfree(bfin_jc_write_buf.buf);
- err_buf:
- kthread_stop(bfin_jc_kthread);
- return ret;
-}
-module_init(bfin_jc_init);
-
-static void __exit bfin_jc_exit(void)
-{
- kthread_stop(bfin_jc_kthread);
- kfree(bfin_jc_write_buf.buf);
- tty_unregister_driver(bfin_jc_driver);
- put_tty_driver(bfin_jc_driver);
- tty_port_destroy(&port);
-}
-module_exit(bfin_jc_exit);
-
-#if defined(CONFIG_BFIN_JTAG_COMM_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-static void
-bfin_jc_straight_buffer_write(const char *buf, unsigned count)
-{
- unsigned ate = 0;
- while (bfin_read_DBGSTAT() & EMUDOF)
- continue;
- bfin_write_emudat(count);
- while (ate < count) {
- while (bfin_read_DBGSTAT() & EMUDOF)
- continue;
- bfin_write_emudat_chars(buf[ate], buf[ate+1], buf[ate+2], buf[ate+3]);
- ate += 4;
- }
-}
-#endif
-
-#ifdef CONFIG_BFIN_JTAG_COMM_CONSOLE
-static void
-bfin_jc_console_write(struct console *co, const char *buf, unsigned count)
-{
- if (bfin_jc_kthread == NULL)
- bfin_jc_straight_buffer_write(buf, count);
- else
- bfin_jc_circ_write(buf, count);
-}
-
-static struct tty_driver *
-bfin_jc_console_device(struct console *co, int *index)
-{
- *index = co->index;
- return bfin_jc_driver;
-}
-
-static struct console bfin_jc_console = {
- .name = DEV_NAME,
- .write = bfin_jc_console_write,
- .device = bfin_jc_console_device,
- .flags = CON_ANYTIME | CON_PRINTBUFFER,
- .index = -1,
-};
-
-static int __init bfin_jc_console_init(void)
-{
- register_console(&bfin_jc_console);
- return 0;
-}
-console_initcall(bfin_jc_console_init);
-#endif
-
-#ifdef CONFIG_EARLY_PRINTK
-static void __init
-bfin_jc_early_write(struct console *co, const char *buf, unsigned int count)
-{
- bfin_jc_straight_buffer_write(buf, count);
-}
-
-static struct console bfin_jc_early_console __initdata = {
- .name = "early_BFJC",
- .write = bfin_jc_early_write,
- .flags = CON_ANYTIME | CON_PRINTBUFFER,
- .index = -1,
-};
-
-struct console * __init
-bfin_jc_early_init(unsigned int port, unsigned int cflag)
-{
- return &bfin_jc_early_console;
-}
-#endif
-
-MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
-MODULE_DESCRIPTION("TTY over Blackfin JTAG Communication");
-MODULE_LICENSE("GPL");
diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig
index fec457e..3bade5a 100644
--- a/drivers/tty/hvc/Kconfig
+++ b/drivers/tty/hvc/Kconfig
@@ -88,15 +88,6 @@ config HVC_DCC
driver. This console is used through a JTAG only on ARM. If you don't have
a JTAG then you probably don't want this option.
-config HVC_BFIN_JTAG
- bool "Blackfin JTAG console"
- depends on BLACKFIN
- select HVC_DRIVER
- help
- This console uses the Blackfin JTAG to create a console under the
- the HVC driver. If you don't have JTAG, then you probably don't
- want this option.
-
config HVCS
tristate "IBM Hypervisor Virtual Console Server support"
depends on PPC_PSERIES && HVC_CONSOLE
diff --git a/drivers/tty/hvc/Makefile b/drivers/tty/hvc/Makefile
index 0b02ec7..b82f9f6 100644
--- a/drivers/tty/hvc/Makefile
+++ b/drivers/tty/hvc/Makefile
@@ -10,5 +10,4 @@ obj-$(CONFIG_HVC_IRQ) += hvc_irq.o
obj-$(CONFIG_HVC_XEN) += hvc_xen.o
obj-$(CONFIG_HVC_IUCV) += hvc_iucv.o
obj-$(CONFIG_HVC_UDBG) += hvc_udbg.o
-obj-$(CONFIG_HVC_BFIN_JTAG) += hvc_bfin_jtag.o
obj-$(CONFIG_HVCS) += hvcs.o
diff --git a/drivers/tty/hvc/hvc_bfin_jtag.c b/drivers/tty/hvc/hvc_bfin_jtag.c
deleted file mode 100644
index dd7cae4..0000000
--- a/drivers/tty/hvc/hvc_bfin_jtag.c
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Console via Blackfin JTAG Communication
- *
- * Copyright 2008-2011 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- */
-
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/moduleparam.h>
-#include <linux/types.h>
-
-#include "hvc_console.h"
-
-/* See the Debug/Emulation chapter in the HRM */
-#define EMUDOF 0x00000001 /* EMUDAT_OUT full & valid */
-#define EMUDIF 0x00000002 /* EMUDAT_IN full & valid */
-#define EMUDOOVF 0x00000004 /* EMUDAT_OUT overflow */
-#define EMUDIOVF 0x00000008 /* EMUDAT_IN overflow */
-
-/* Helper functions to glue the register API to simple C operations */
-static inline uint32_t bfin_write_emudat(uint32_t emudat)
-{
- __asm__ __volatile__("emudat = %0;" : : "d"(emudat));
- return emudat;
-}
-
-static inline uint32_t bfin_read_emudat(void)
-{
- uint32_t emudat;
- __asm__ __volatile__("%0 = emudat;" : "=d"(emudat));
- return emudat;
-}
-
-/* Send data to the host */
-static int hvc_bfin_put_chars(uint32_t vt, const char *buf, int count)
-{
- static uint32_t outbound_len;
- uint32_t emudat;
- int ret;
-
- if (bfin_read_DBGSTAT() & EMUDOF)
- return 0;
-
- if (!outbound_len) {
- outbound_len = count;
- bfin_write_emudat(outbound_len);
- return 0;
- }
-
- ret = min(outbound_len, (uint32_t)4);
- memcpy(&emudat, buf, ret);
- bfin_write_emudat(emudat);
- outbound_len -= ret;
-
- return ret;
-}
-
-/* Receive data from the host */
-static int hvc_bfin_get_chars(uint32_t vt, char *buf, int count)
-{
- static uint32_t inbound_len;
- uint32_t emudat;
- int ret;
-
- if (!(bfin_read_DBGSTAT() & EMUDIF))
- return 0;
- emudat = bfin_read_emudat();
-
- if (!inbound_len) {
- inbound_len = emudat;
- return 0;
- }
-
- ret = min(inbound_len, (uint32_t)4);
- memcpy(buf, &emudat, ret);
- inbound_len -= ret;
-
- return ret;
-}
-
-/* Glue the HVC layers to the Blackfin layers */
-static const struct hv_ops hvc_bfin_get_put_ops = {
- .get_chars = hvc_bfin_get_chars,
- .put_chars = hvc_bfin_put_chars,
-};
-
-static int __init hvc_bfin_console_init(void)
-{
- hvc_instantiate(0, 0, &hvc_bfin_get_put_ops);
- return 0;
-}
-console_initcall(hvc_bfin_console_init);
-
-static int __init hvc_bfin_init(void)
-{
- hvc_alloc(0, 0, &hvc_bfin_get_put_ops, 128);
- return 0;
-}
-device_initcall(hvc_bfin_init);
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 3682fd3..b9b6450 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -498,92 +498,6 @@ config SERIAL_SA1100_CONSOLE
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
-config SERIAL_BFIN
- tristate "Blackfin serial port support"
- depends on BLACKFIN
- select SERIAL_CORE
- select SERIAL_BFIN_UART0 if (BF531 || BF532 || BF533 || BF561)
- help
- Add support for the built-in UARTs on the Blackfin.
-
- To compile this driver as a module, choose M here: the
- module is named bfin_uart.ko.
-
-config SERIAL_BFIN_CONSOLE
- bool "Console on Blackfin serial port"
- depends on SERIAL_BFIN=y
- select SERIAL_CORE_CONSOLE
-
-choice
- prompt "UART Mode"
- depends on SERIAL_BFIN
- default SERIAL_BFIN_DMA
- help
- This driver supports the built-in serial ports of the Blackfin family
- of CPUs
-
-config SERIAL_BFIN_DMA
- bool "DMA mode"
- depends on !DMA_UNCACHED_NONE && KGDB_SERIAL_CONSOLE=n
- help
- This driver works under DMA mode. If this option is selected, the
- blackfin simple dma driver is also enabled.
-
-config SERIAL_BFIN_PIO
- bool "PIO mode"
- help
- This driver works under PIO mode.
-
-endchoice
-
-config SERIAL_BFIN_UART0
- bool "Enable UART0"
- depends on SERIAL_BFIN
- help
- Enable UART0
-
-config BFIN_UART0_CTSRTS
- bool "Enable UART0 hardware flow control"
- depends on SERIAL_BFIN_UART0
- help
- Enable hardware flow control in the driver.
-
-config SERIAL_BFIN_UART1
- bool "Enable UART1"
- depends on SERIAL_BFIN && (!BF531 && !BF532 && !BF533 && !BF561)
- help
- Enable UART1
-
-config BFIN_UART1_CTSRTS
- bool "Enable UART1 hardware flow control"
- depends on SERIAL_BFIN_UART1
- help
- Enable hardware flow control in the driver.
-
-config SERIAL_BFIN_UART2
- bool "Enable UART2"
- depends on SERIAL_BFIN && (BF54x || BF538 || BF539)
- help
- Enable UART2
-
-config BFIN_UART2_CTSRTS
- bool "Enable UART2 hardware flow control"
- depends on SERIAL_BFIN_UART2
- help
- Enable hardware flow control in the driver.
-
-config SERIAL_BFIN_UART3
- bool "Enable UART3"
- depends on SERIAL_BFIN && (BF54x)
- help
- Enable UART3
-
-config BFIN_UART3_CTSRTS
- bool "Enable UART3 hardware flow control"
- depends on SERIAL_BFIN_UART3
- help
- Enable hardware flow control in the driver.
-
config SERIAL_IMX
tristate "IMX serial port support"
depends on HAS_DMA
@@ -1242,69 +1156,6 @@ config SERIAL_SC16IS7XX_SPI
This is additional support to exsisting driver.
You must select at least one bus for the driver to be built.
-config SERIAL_BFIN_SPORT
- tristate "Blackfin SPORT emulate UART"
- depends on BLACKFIN
- select SERIAL_CORE
- help
- Enable SPORT emulate UART on Blackfin series.
-
- To compile this driver as a module, choose M here: the
- module will be called bfin_sport_uart.
-
-config SERIAL_BFIN_SPORT_CONSOLE
- bool "Console on Blackfin sport emulated uart"
- depends on SERIAL_BFIN_SPORT=y
- select SERIAL_CORE_CONSOLE
-
-config SERIAL_BFIN_SPORT0_UART
- bool "Enable UART over SPORT0"
- depends on SERIAL_BFIN_SPORT && !(BF542 || BF544)
- help
- Enable UART over SPORT0
-
-config SERIAL_BFIN_SPORT0_UART_CTSRTS
- bool "Enable UART over SPORT0 hardware flow control"
- depends on SERIAL_BFIN_SPORT0_UART
- help
- Enable hardware flow control in the driver.
-
-config SERIAL_BFIN_SPORT1_UART
- bool "Enable UART over SPORT1"
- depends on SERIAL_BFIN_SPORT
- help
- Enable UART over SPORT1
-
-config SERIAL_BFIN_SPORT1_UART_CTSRTS
- bool "Enable UART over SPORT1 hardware flow control"
- depends on SERIAL_BFIN_SPORT1_UART
- help
- Enable hardware flow control in the driver.
-
-config SERIAL_BFIN_SPORT2_UART
- bool "Enable UART over SPORT2"
- depends on SERIAL_BFIN_SPORT && (BF54x || BF538 || BF539)
- help
- Enable UART over SPORT2
-
-config SERIAL_BFIN_SPORT2_UART_CTSRTS
- bool "Enable UART over SPORT2 hardware flow control"
- depends on SERIAL_BFIN_SPORT2_UART
- help
- Enable hardware flow control in the driver.
-
-config SERIAL_BFIN_SPORT3_UART
- bool "Enable UART over SPORT3"
- depends on SERIAL_BFIN_SPORT && (BF54x || BF538 || BF539)
- help
- Enable UART over SPORT3
-
-config SERIAL_BFIN_SPORT3_UART_CTSRTS
- bool "Enable UART over SPORT3 hardware flow control"
- depends on SERIAL_BFIN_SPORT3_UART
- help
- Enable hardware flow control in the driver.
-
config SERIAL_TIMBERDALE
tristate "Support for timberdale UART"
select SERIAL_CORE
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 842d185..1342ffc 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -29,8 +29,6 @@ obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o
obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o
obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o
-obj-$(CONFIG_SERIAL_BFIN) += bfin_uart.o
-obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o
obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
obj-$(CONFIG_SERIAL_MAX310X) += max310x.o
diff --git a/drivers/tty/serial/bfin_sport_uart.c b/drivers/tty/serial/bfin_sport_uart.c
deleted file mode 100644
index 4ccca5d..0000000
--- a/drivers/tty/serial/bfin_sport_uart.c
+++ /dev/null
@@ -1,937 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Blackfin On-Chip Sport Emulated UART Driver
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- */
-
-/*
- * This driver and the hardware supported are in term of EE-191 of ADI.
- * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
- * This application note describe how to implement a UART on a Sharc DSP,
- * but this driver is implemented on Blackfin Processor.
- * Transmit Frame Sync is not used by this driver to transfer data out.
- */
-
-/* #define DEBUG */
-
-#define DRV_NAME "bfin-sport-uart"
-#define DEVICE_NAME "ttySS"
-#define pr_fmt(fmt) DRV_NAME ": " fmt
-
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/sysrq.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/tty.h>
-#include <linux/tty_flip.h>
-#include <linux/serial_core.h>
-#include <linux/gpio.h>
-
-#include <asm/bfin_sport.h>
-#include <asm/delay.h>
-#include <asm/portmux.h>
-
-#include "bfin_sport_uart.h"
-
-struct sport_uart_port {
- struct uart_port port;
- int err_irq;
- unsigned short csize;
- unsigned short rxmask;
- unsigned short txmask1;
- unsigned short txmask2;
- unsigned char stopb;
-/* unsigned char parib; */
-#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
- int cts_pin;
- int rts_pin;
-#endif
-};
-
-static int sport_uart_tx_chars(struct sport_uart_port *up);
-static void sport_stop_tx(struct uart_port *port);
-
-static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
-{
- pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
- up->txmask1, up->txmask2);
-
- /* Place Start and Stop bits */
- __asm__ __volatile__ (
- "%[val] <<= 1;"
- "%[val] = %[val] & %[mask1];"
- "%[val] = %[val] | %[mask2];"
- : [val]"+d"(value)
- : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
- : "ASTAT"
- );
- pr_debug("%s value:%x\n", __func__, value);
-
- SPORT_PUT_TX(up, value);
-}
-
-static inline unsigned char rx_one_byte(struct sport_uart_port *up)
-{
- unsigned int value;
- unsigned char extract;
- u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
-
- if ((up->csize + up->stopb) > 7)
- value = SPORT_GET_RX32(up);
- else
- value = SPORT_GET_RX(up);
-
- pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
- up->csize, up->rxmask);
-
- /* Extract data */
- __asm__ __volatile__ (
- "%[extr] = 0;"
- "%[mask1] = %[rxmask];"
- "%[mask2] = 0x0200(Z);"
- "%[shift] = 0;"
- "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
- ".Lloop_s:"
- "%[tmp] = extract(%[val], %[mask1].L)(Z);"
- "%[tmp] <<= %[shift];"
- "%[extr] = %[extr] | %[tmp];"
- "%[mask1] = %[mask1] - %[mask2];"
- ".Lloop_e:"
- "%[shift] += 1;"
- : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
- [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
- : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
- : "ASTAT", "LB0", "LC0", "LT0"
- );
-
- pr_debug(" extract:%x\n", extract);
- return extract;
-}
-
-static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
-{
- int tclkdiv, rclkdiv;
- unsigned int sclk = get_sclk();
-
- /* Set TCR1 and TCR2, TFSR is not enabled for uart */
- SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
- SPORT_PUT_TCR2(up, size + 1);
- pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
-
- /* Set RCR1 and RCR2 */
- SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
- SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
- pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
-
- tclkdiv = sclk / (2 * baud_rate) - 1;
- /* The actual uart baud rate of devices vary between +/-2%. The sport
- * RX sample rate should be faster than the double of the worst case,
- * otherwise, wrong data are received. So, set sport RX clock to be
- * 3% faster.
- */
- rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
- SPORT_PUT_TCLKDIV(up, tclkdiv);
- SPORT_PUT_RCLKDIV(up, rclkdiv);
- SSYNC();
- pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
- __func__, sclk, baud_rate, tclkdiv, rclkdiv);
-
- return 0;
-}
-
-static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
-{
- struct sport_uart_port *up = dev_id;
- struct tty_port *port = &up->port.state->port;
- unsigned int ch;
-
- spin_lock(&up->port.lock);
-
- while (SPORT_GET_STAT(up) & RXNE) {
- ch = rx_one_byte(up);
- up->port.icount.rx++;
-
- if (!uart_handle_sysrq_char(&up->port, ch))
- tty_insert_flip_char(port, ch, TTY_NORMAL);
- }
-
- spin_unlock(&up->port.lock);
-
- /* XXX this won't deadlock with lowlat? */
- tty_flip_buffer_push(port);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
-{
- struct sport_uart_port *up = dev_id;
-
- spin_lock(&up->port.lock);
- sport_uart_tx_chars(up);
- spin_unlock(&up->port.lock);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
-{
- struct sport_uart_port *up = dev_id;
- unsigned int stat = SPORT_GET_STAT(up);
-
- spin_lock(&up->port.lock);
-
- /* Overflow in RX FIFO */
- if (stat & ROVF) {
- up->port.icount.overrun++;
- tty_insert_flip_char(&up->port.state->port, 0, TTY_OVERRUN);
- SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
- }
- /* These should not happen */
- if (stat & (TOVF | TUVF | RUVF)) {
- pr_err("SPORT Error:%s %s %s\n",
- (stat & TOVF) ? "TX overflow" : "",
- (stat & TUVF) ? "TX underflow" : "",
- (stat & RUVF) ? "RX underflow" : "");
- SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
- SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
- }
- SSYNC();
-
- spin_unlock(&up->port.lock);
- /* XXX we don't push the overrun bit to TTY? */
-
- return IRQ_HANDLED;
-}
-
-#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
-static unsigned int sport_get_mctrl(struct uart_port *port)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
- if (up->cts_pin < 0)
- return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
-
- /* CTS PIN is negative assertive. */
- if (SPORT_UART_GET_CTS(up))
- return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
- else
- return TIOCM_DSR | TIOCM_CAR;
-}
-
-static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
- if (up->rts_pin < 0)
- return;
-
- /* RTS PIN is negative assertive. */
- if (mctrl & TIOCM_RTS)
- SPORT_UART_ENABLE_RTS(up);
- else
- SPORT_UART_DISABLE_RTS(up);
-}
-
-/*
- * Handle any change of modem status signal.
- */
-static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
- unsigned int status;
-
- status = sport_get_mctrl(&up->port);
- uart_handle_cts_change(&up->port, status & TIOCM_CTS);
-
- return IRQ_HANDLED;
-}
-#else
-static unsigned int sport_get_mctrl(struct uart_port *port)
-{
- pr_debug("%s enter\n", __func__);
- return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
-}
-
-static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
-{
- pr_debug("%s enter\n", __func__);
-}
-#endif
-
-/* Reqeust IRQ, Setup clock */
-static int sport_startup(struct uart_port *port)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
- int ret;
-
- pr_debug("%s enter\n", __func__);
- ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
- "SPORT_UART_RX", up);
- if (ret) {
- dev_err(port->dev, "unable to request SPORT RX interrupt\n");
- return ret;
- }
-
- ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
- "SPORT_UART_TX", up);
- if (ret) {
- dev_err(port->dev, "unable to request SPORT TX interrupt\n");
- goto fail1;
- }
-
- ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
- "SPORT_UART_STATUS", up);
- if (ret) {
- dev_err(port->dev, "unable to request SPORT status interrupt\n");
- goto fail2;
- }
-
-#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
- if (up->cts_pin >= 0) {
- if (request_irq(gpio_to_irq(up->cts_pin),
- sport_mctrl_cts_int,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
- 0, "BFIN_SPORT_UART_CTS", up)) {
- up->cts_pin = -1;
- dev_info(port->dev, "Unable to attach BlackFin UART over SPORT CTS interrupt. So, disable it.\n");
- }
- }
- if (up->rts_pin >= 0) {
- if (gpio_request(up->rts_pin, DRV_NAME)) {
- dev_info(port->dev, "fail to request RTS PIN at GPIO_%d\n", up->rts_pin);
- up->rts_pin = -1;
- } else
- gpio_direction_output(up->rts_pin, 0);
- }
-#endif
-
- return 0;
- fail2:
- free_irq(up->port.irq+1, up);
- fail1:
- free_irq(up->port.irq, up);
-
- return ret;
-}
-
-/*
- * sport_uart_tx_chars
- *
- * ret 1 means need to enable sport.
- * ret 0 means do nothing.
- */
-static int sport_uart_tx_chars(struct sport_uart_port *up)
-{
- struct circ_buf *xmit = &up->port.state->xmit;
-
- if (SPORT_GET_STAT(up) & TXF)
- return 0;
-
- if (up->port.x_char) {
- tx_one_byte(up, up->port.x_char);
- up->port.icount.tx++;
- up->port.x_char = 0;
- return 1;
- }
-
- if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
- /* The waiting loop to stop SPORT TX from TX interrupt is
- * too long. This may block SPORT RX interrupts and cause
- * RX FIFO overflow. So, do stop sport TX only after the last
- * char in TX FIFO is moved into the shift register.
- */
- if (SPORT_GET_STAT(up) & TXHRE)
- sport_stop_tx(&up->port);
- return 0;
- }
-
- while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
- tx_one_byte(up, xmit->buf[xmit->tail]);
- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
- up->port.icount.tx++;
- }
-
- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
- uart_write_wakeup(&up->port);
-
- return 1;
-}
-
-static unsigned int sport_tx_empty(struct uart_port *port)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
- unsigned int stat;
-
- stat = SPORT_GET_STAT(up);
- pr_debug("%s stat:%04x\n", __func__, stat);
- if (stat & TXHRE) {
- return TIOCSER_TEMT;
- } else
- return 0;
-}
-
-static void sport_stop_tx(struct uart_port *port)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
-
- pr_debug("%s enter\n", __func__);
-
- if (!(SPORT_GET_TCR1(up) & TSPEN))
- return;
-
- /* Although the hold register is empty, last byte is still in shift
- * register and not sent out yet. So, put a dummy data into TX FIFO.
- * Then, sport tx stops when last byte is shift out and the dummy
- * data is moved into the shift register.
- */
- SPORT_PUT_TX(up, 0xffff);
- while (!(SPORT_GET_STAT(up) & TXHRE))
- cpu_relax();
-
- SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
- SSYNC();
-
- return;
-}
-
-static void sport_start_tx(struct uart_port *port)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
-
- pr_debug("%s enter\n", __func__);
-
- /* Write data into SPORT FIFO before enable SPROT to transmit */
- if (sport_uart_tx_chars(up)) {
- /* Enable transmit, then an interrupt will generated */
- SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
- SSYNC();
- }
-
- pr_debug("%s exit\n", __func__);
-}
-
-static void sport_stop_rx(struct uart_port *port)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
-
- pr_debug("%s enter\n", __func__);
- /* Disable sport to stop rx */
- SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
- SSYNC();
-}
-
-static void sport_break_ctl(struct uart_port *port, int break_state)
-{
- pr_debug("%s enter\n", __func__);
-}
-
-static void sport_shutdown(struct uart_port *port)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
-
- dev_dbg(port->dev, "%s enter\n", __func__);
-
- /* Disable sport */
- SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
- SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
- SSYNC();
-
- free_irq(up->port.irq, up);
- free_irq(up->port.irq+1, up);
- free_irq(up->err_irq, up);
-#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
- if (up->cts_pin >= 0)
- free_irq(gpio_to_irq(up->cts_pin), up);
- if (up->rts_pin >= 0)
- gpio_free(up->rts_pin);
-#endif
-}
-
-static const char *sport_type(struct uart_port *port)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
-
- pr_debug("%s enter\n", __func__);
- return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
-}
-
-static void sport_release_port(struct uart_port *port)
-{
- pr_debug("%s enter\n", __func__);
-}
-
-static int sport_request_port(struct uart_port *port)
-{
- pr_debug("%s enter\n", __func__);
- return 0;
-}
-
-static void sport_config_port(struct uart_port *port, int flags)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
-
- pr_debug("%s enter\n", __func__);
- up->port.type = PORT_BFIN_SPORT;
-}
-
-static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
-{
- pr_debug("%s enter\n", __func__);
- return 0;
-}
-
-static void sport_set_termios(struct uart_port *port,
- struct ktermios *termios, struct ktermios *old)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
- unsigned long flags;
- int i;
-
- pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
-
-#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
- if (old == NULL && up->cts_pin != -1)
- termios->c_cflag |= CRTSCTS;
- else if (up->cts_pin == -1)
- termios->c_cflag &= ~CRTSCTS;
-#endif
-
- switch (termios->c_cflag & CSIZE) {
- case CS8:
- up->csize = 8;
- break;
- case CS7:
- up->csize = 7;
- break;
- case CS6:
- up->csize = 6;
- break;
- case CS5:
- up->csize = 5;
- break;
- default:
- pr_warn("requested word length not supported\n");
- break;
- }
-
- if (termios->c_cflag & CSTOPB) {
- up->stopb = 1;
- }
- if (termios->c_cflag & PARENB) {
- pr_warn("PAREN bit is not supported yet\n");
- /* up->parib = 1; */
- }
-
- spin_lock_irqsave(&up->port.lock, flags);
-
- port->read_status_mask = 0;
-
- /*
- * Characters to ignore
- */
- port->ignore_status_mask = 0;
-
- /* RX extract mask */
- up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
- /* TX masks, 8 bit data and 1 bit stop for example:
- * mask1 = b#0111111110
- * mask2 = b#1000000000
- */
- for (i = 0, up->txmask1 = 0; i < up->csize; i++)
- up->txmask1 |= (1<<i);
- up->txmask2 = (1<<i);
- if (up->stopb) {
- ++i;
- up->txmask2 |= (1<<i);
- }
- up->txmask1 <<= 1;
- up->txmask2 <<= 1;
- /* uart baud rate */
- port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
-
- /* Disable UART */
- SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
- SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
-
- sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
-
- /* driver TX line high after config, one dummy data is
- * necessary to stop sport after shift one byte
- */
- SPORT_PUT_TX(up, 0xffff);
- SPORT_PUT_TX(up, 0xffff);
- SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
- SSYNC();
- while (!(SPORT_GET_STAT(up) & TXHRE))
- cpu_relax();
- SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
- SSYNC();
-
- /* Port speed changed, update the per-port timeout. */
- uart_update_timeout(port, termios->c_cflag, port->uartclk);
-
- /* Enable sport rx */
- SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
- SSYNC();
-
- spin_unlock_irqrestore(&up->port.lock, flags);
-}
-
-static const struct uart_ops sport_uart_ops = {
- .tx_empty = sport_tx_empty,
- .set_mctrl = sport_set_mctrl,
- .get_mctrl = sport_get_mctrl,
- .stop_tx = sport_stop_tx,
- .start_tx = sport_start_tx,
- .stop_rx = sport_stop_rx,
- .break_ctl = sport_break_ctl,
- .startup = sport_startup,
- .shutdown = sport_shutdown,
- .set_termios = sport_set_termios,
- .type = sport_type,
- .release_port = sport_release_port,
- .request_port = sport_request_port,
- .config_port = sport_config_port,
- .verify_port = sport_verify_port,
-};
-
-#define BFIN_SPORT_UART_MAX_PORTS 4
-
-static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
-
-#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
-#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
-
-static int __init
-sport_uart_console_setup(struct console *co, char *options)
-{
- struct sport_uart_port *up;
- int baud = 57600;
- int bits = 8;
- int parity = 'n';
-# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
- int flow = 'r';
-# else
- int flow = 'n';
-# endif
-
- /* Check whether an invalid uart number has been specified */
- if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
- return -ENODEV;
-
- up = bfin_sport_uart_ports[co->index];
- if (!up)
- return -ENODEV;
-
- if (options)
- uart_parse_options(options, &baud, &parity, &bits, &flow);
-
- return uart_set_options(&up->port, co, baud, parity, bits, flow);
-}
-
-static void sport_uart_console_putchar(struct uart_port *port, int ch)
-{
- struct sport_uart_port *up = (struct sport_uart_port *)port;
-
- while (SPORT_GET_STAT(up) & TXF)
- barrier();
-
- tx_one_byte(up, ch);
-}
-
-/*
- * Interrupts are disabled on entering
- */
-static void
-sport_uart_console_write(struct console *co, const char *s, unsigned int count)
-{
- struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
- unsigned long flags;
-
- spin_lock_irqsave(&up->port.lock, flags);
-
- if (SPORT_GET_TCR1(up) & TSPEN)
- uart_console_write(&up->port, s, count, sport_uart_console_putchar);
- else {
- /* dummy data to start sport */
- while (SPORT_GET_STAT(up) & TXF)
- barrier();
- SPORT_PUT_TX(up, 0xffff);
- /* Enable transmit, then an interrupt will generated */
- SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
- SSYNC();
-
- uart_console_write(&up->port, s, count, sport_uart_console_putchar);
-
- /* Although the hold register is empty, last byte is still in shift
- * register and not sent out yet. So, put a dummy data into TX FIFO.
- * Then, sport tx stops when last byte is shift out and the dummy
- * data is moved into the shift register.
- */
- while (SPORT_GET_STAT(up) & TXF)
- barrier();
- SPORT_PUT_TX(up, 0xffff);
- while (!(SPORT_GET_STAT(up) & TXHRE))
- barrier();
-
- /* Stop sport tx transfer */
- SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
- SSYNC();
- }
-
- spin_unlock_irqrestore(&up->port.lock, flags);
-}
-
-static struct uart_driver sport_uart_reg;
-
-static struct console sport_uart_console = {
- .name = DEVICE_NAME,
- .write = sport_uart_console_write,
- .device = uart_console_device,
- .setup = sport_uart_console_setup,
- .flags = CON_PRINTBUFFER,
- .index = -1,
- .data = &sport_uart_reg,
-};
-
-#define SPORT_UART_CONSOLE (&sport_uart_console)
-#else
-#define SPORT_UART_CONSOLE NULL
-#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
-
-
-static struct uart_driver sport_uart_reg = {
- .owner = THIS_MODULE,
- .driver_name = DRV_NAME,
- .dev_name = DEVICE_NAME,
- .major = 204,
- .minor = 84,
- .nr = BFIN_SPORT_UART_MAX_PORTS,
- .cons = SPORT_UART_CONSOLE,
-};
-
-#ifdef CONFIG_PM
-static int sport_uart_suspend(struct device *dev)
-{
- struct sport_uart_port *sport = dev_get_drvdata(dev);
-
- dev_dbg(dev, "%s enter\n", __func__);
- if (sport)
- uart_suspend_port(&sport_uart_reg, &sport->port);
-
- return 0;
-}
-
-static int sport_uart_resume(struct device *dev)
-{
- struct sport_uart_port *sport = dev_get_drvdata(dev);
-
- dev_dbg(dev, "%s enter\n", __func__);
- if (sport)
- uart_resume_port(&sport_uart_reg, &sport->port);
-
- return 0;
-}
-
-static const struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
- .suspend = sport_uart_suspend,
- .resume = sport_uart_resume,
-};
-#endif
-
-static int sport_uart_probe(struct platform_device *pdev)
-{
- struct resource *res;
- struct sport_uart_port *sport;
- int ret = 0;
-
- dev_dbg(&pdev->dev, "%s enter\n", __func__);
-
- if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
- dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
- return -ENOENT;
- }
-
- if (bfin_sport_uart_ports[pdev->id] == NULL) {
- bfin_sport_uart_ports[pdev->id] =
- kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
- sport = bfin_sport_uart_ports[pdev->id];
- if (!sport) {
- dev_err(&pdev->dev,
- "Fail to malloc sport_uart_port\n");
- return -ENOMEM;
- }
-
- ret = peripheral_request_list(dev_get_platdata(&pdev->dev),
- DRV_NAME);
- if (ret) {
- dev_err(&pdev->dev,
- "Fail to request SPORT peripherals\n");
- goto out_error_free_mem;
- }
-
- spin_lock_init(&sport->port.lock);
- sport->port.fifosize = SPORT_TX_FIFO_SIZE,
- sport->port.ops = &sport_uart_ops;
- sport->port.line = pdev->id;
- sport->port.iotype = UPIO_MEM;
- sport->port.flags = UPF_BOOT_AUTOCONF;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL) {
- dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
- ret = -ENOENT;
- goto out_error_free_peripherals;
- }
-
- sport->port.membase = ioremap(res->start, resource_size(res));
- if (!sport->port.membase) {
- dev_err(&pdev->dev, "Cannot map sport IO\n");
- ret = -ENXIO;
- goto out_error_free_peripherals;
- }
- sport->port.mapbase = res->start;
-
- sport->port.irq = platform_get_irq(pdev, 0);
- if ((int)sport->port.irq < 0) {
- dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
- ret = -ENOENT;
- goto out_error_unmap;
- }
-
- sport->err_irq = platform_get_irq(pdev, 1);
- if (sport->err_irq < 0) {
- dev_err(&pdev->dev, "No sport status IRQ specified\n");
- ret = -ENOENT;
- goto out_error_unmap;
- }
-#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
- res = platform_get_resource(pdev, IORESOURCE_IO, 0);
- if (res == NULL)
- sport->cts_pin = -1;
- else
- sport->cts_pin = res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_IO, 1);
- if (res == NULL)
- sport->rts_pin = -1;
- else
- sport->rts_pin = res->start;
-#endif
- }
-
-#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
- if (!is_early_platform_device(pdev)) {
-#endif
- sport = bfin_sport_uart_ports[pdev->id];
- sport->port.dev = &pdev->dev;
- dev_set_drvdata(&pdev->dev, sport);
- ret = uart_add_one_port(&sport_uart_reg, &sport->port);
-#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
- }
-#endif
- if (!ret)
- return 0;
-
- if (sport) {
-out_error_unmap:
- iounmap(sport->port.membase);
-out_error_free_peripherals:
- peripheral_free_list(dev_get_platdata(&pdev->dev));
-out_error_free_mem:
- kfree(sport);
- bfin_sport_uart_ports[pdev->id] = NULL;
- }
-
- return ret;
-}
-
-static int sport_uart_remove(struct platform_device *pdev)
-{
- struct sport_uart_port *sport = platform_get_drvdata(pdev);
-
- dev_dbg(&pdev->dev, "%s enter\n", __func__);
- dev_set_drvdata(&pdev->dev, NULL);
-
- if (sport) {
- uart_remove_one_port(&sport_uart_reg, &sport->port);
- iounmap(sport->port.membase);
- peripheral_free_list(dev_get_platdata(&pdev->dev));
- kfree(sport);
- bfin_sport_uart_ports[pdev->id] = NULL;
- }
-
- return 0;
-}
-
-static struct platform_driver sport_uart_driver = {
- .probe = sport_uart_probe,
- .remove = sport_uart_remove,
- .driver = {
- .name = DRV_NAME,
-#ifdef CONFIG_PM
- .pm = &bfin_sport_uart_dev_pm_ops,
-#endif
- },
-};
-
-#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
-static struct early_platform_driver early_sport_uart_driver __initdata = {
- .class_str = CLASS_BFIN_SPORT_CONSOLE,
- .pdrv = &sport_uart_driver,
- .requested_id = EARLY_PLATFORM_ID_UNSET,
-};
-
-static int __init sport_uart_rs_console_init(void)
-{
- early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
-
- early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
- BFIN_SPORT_UART_MAX_PORTS, 0);
-
- register_console(&sport_uart_console);
-
- return 0;
-}
-console_initcall(sport_uart_rs_console_init);
-#endif
-
-static int __init sport_uart_init(void)
-{
- int ret;
-
- pr_info("Blackfin uart over sport driver\n");
-
- ret = uart_register_driver(&sport_uart_reg);
- if (ret) {
- pr_err("failed to register %s:%d\n",
- sport_uart_reg.driver_name, ret);
- return ret;
- }
-
- ret = platform_driver_register(&sport_uart_driver);
- if (ret) {
- pr_err("failed to register sport uart driver:%d\n", ret);
- uart_unregister_driver(&sport_uart_reg);
- }
-
- return ret;
-}
-module_init(sport_uart_init);
-
-static void __exit sport_uart_exit(void)
-{
- platform_driver_unregister(&sport_uart_driver);
- uart_unregister_driver(&sport_uart_reg);
-}
-module_exit(sport_uart_exit);
-
-MODULE_AUTHOR("Sonic Zhang, Roy Huang");
-MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/bfin_sport_uart.h b/drivers/tty/serial/bfin_sport_uart.h
deleted file mode 100644
index 4b12f45..0000000
--- a/drivers/tty/serial/bfin_sport_uart.h
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Blackfin On-Chip Sport Emulated UART Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- */
-
-/*
- * This driver and the hardware supported are in term of EE-191 of ADI.
- * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
- * This application note describe how to implement a UART on a Sharc DSP,
- * but this driver is implemented on Blackfin Processor.
- * Transmit Frame Sync is not used by this driver to transfer data out.
- */
-
-#ifndef _BFIN_SPORT_UART_H
-#define _BFIN_SPORT_UART_H
-
-#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
-#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
-#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
-#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
-#define OFFSET_TX 0x10 /* Transmit Data Register */
-#define OFFSET_RX 0x18 /* Receive Data Register */
-#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
-#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
-#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
-#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
-#define OFFSET_STAT 0x30 /* Status Register */
-
-#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
-#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
-#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
-#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
-#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
-#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
-/*
- * If another interrupt fires while doing a 32-bit read from RX FIFO,
- * a fake RX underflow error will be generated. So disable interrupts
- * to prevent interruption while reading the FIFO.
- */
-#define SPORT_GET_RX32(sport) \
-({ \
- unsigned int __ret; \
- unsigned long flags; \
- if (ANOMALY_05000473) \
- local_irq_save(flags); \
- __ret = bfin_read32((sport)->port.membase + OFFSET_RX); \
- if (ANOMALY_05000473) \
- local_irq_restore(flags); \
- __ret; \
-})
-#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
-#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
-#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
-#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
-#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
-
-#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
-#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
-#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
-#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
-#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
-#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
-#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
-#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
-#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
-#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
-#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
-
-#define SPORT_TX_FIFO_SIZE 8
-
-#define SPORT_UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define SPORT_UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define SPORT_UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT0_UART_CTSRTS) \
- || defined(CONFIG_SERIAL_BFIN_SPORT1_UART_CTSRTS) \
- || defined(CONFIG_SERIAL_BFIN_SPORT2_UART_CTSRTS) \
- || defined(CONFIG_SERIAL_BFIN_SPORT3_UART_CTSRTS)
-# define CONFIG_SERIAL_BFIN_SPORT_CTSRTS
-#endif
-
-#endif /* _BFIN_SPORT_UART_H */
diff --git a/drivers/tty/serial/bfin_uart.c b/drivers/tty/serial/bfin_uart.c
deleted file mode 100644
index 4755fa6..0000000
--- a/drivers/tty/serial/bfin_uart.c
+++ /dev/null
@@ -1,1551 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Blackfin On-Chip Serial Driver
- *
- * Copyright 2006-2011 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- */
-
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-#define SUPPORT_SYSRQ
-#endif
-
-#define DRIVER_NAME "bfin-uart"
-#define pr_fmt(fmt) DRIVER_NAME ": " fmt
-
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/gfp.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/sysrq.h>
-#include <linux/platform_device.h>
-#include <linux/tty.h>
-#include <linux/tty_flip.h>
-#include <linux/serial_core.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/kgdb.h>
-#include <linux/slab.h>
-#include <linux/dma-mapping.h>
-
-#include <asm/portmux.h>
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <asm/bfin_serial.h>
-
-#ifdef CONFIG_SERIAL_BFIN_MODULE
-# undef CONFIG_EARLY_PRINTK
-#endif
-
-/* UART name and device definitions */
-#define BFIN_SERIAL_DEV_NAME "ttyBF"
-#define BFIN_SERIAL_MAJOR 204
-#define BFIN_SERIAL_MINOR 64
-
-static struct bfin_serial_port *bfin_serial_ports[BFIN_UART_NR_PORTS];
-
-#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
- defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
-
-# ifndef CONFIG_SERIAL_BFIN_PIO
-# error KGDB only support UART in PIO mode.
-# endif
-
-static int kgdboc_port_line;
-static int kgdboc_break_enabled;
-#endif
-/*
- * Setup for console. Argument comes from the menuconfig
- */
-#define DMA_RX_XCOUNT 512
-#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
-
-#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
-
-#ifdef CONFIG_SERIAL_BFIN_DMA
-static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
-#else
-static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
-#endif
-
-static void bfin_serial_reset_irda(struct uart_port *port);
-
-#if defined(SERIAL_BFIN_CTSRTS) || \
- defined(SERIAL_BFIN_HARD_CTSRTS)
-static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
- if (uart->cts_pin < 0)
- return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
-
- /* CTS PIN is negative assertive. */
- if (UART_GET_CTS(uart))
- return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
- else
- return TIOCM_DSR | TIOCM_CAR;
-}
-
-static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
- if (uart->rts_pin < 0)
- return;
-
- /* RTS PIN is negative assertive. */
- if (mctrl & TIOCM_RTS)
- UART_ENABLE_RTS(uart);
- else
- UART_DISABLE_RTS(uart);
-}
-
-/*
- * Handle any change of modem status signal.
- */
-static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
-{
- struct bfin_serial_port *uart = dev_id;
- struct uart_port *uport = &uart->port;
- unsigned int status = bfin_serial_get_mctrl(uport);
-#ifdef SERIAL_BFIN_HARD_CTSRTS
-
- UART_CLEAR_SCTS(uart);
- if (uport->hw_stopped) {
- if (status) {
- uport->hw_stopped = 0;
- uart_write_wakeup(uport);
- }
- } else {
- if (!status)
- uport->hw_stopped = 1;
- }
-#else
- uart_handle_cts_change(uport, status & TIOCM_CTS);
-#endif
-
- return IRQ_HANDLED;
-}
-#else
-static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
-{
- return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
-}
-
-static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
-{
-}
-#endif
-
-/*
- * interrupts are disabled on entry
- */
-static void bfin_serial_stop_tx(struct uart_port *port)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-#ifdef CONFIG_SERIAL_BFIN_DMA
- struct circ_buf *xmit = &uart->port.state->xmit;
-#endif
-
- while (!(UART_GET_LSR(uart) & TEMT))
- cpu_relax();
-
-#ifdef CONFIG_SERIAL_BFIN_DMA
- disable_dma(uart->tx_dma_channel);
- xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
- uart->port.icount.tx += uart->tx_count;
- uart->tx_count = 0;
- uart->tx_done = 1;
-#else
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
- /* Clear TFI bit */
- UART_PUT_LSR(uart, TFI);
-#endif
- UART_CLEAR_IER(uart, ETBEI);
-#endif
-}
-
-/*
- * port is locked and interrupts are disabled
- */
-static void bfin_serial_start_tx(struct uart_port *port)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
- struct tty_struct *tty = uart->port.state->port.tty;
-
- /*
- * To avoid losting RX interrupt, we reset IR function
- * before sending data.
- */
- if (tty->termios.c_line == N_IRDA)
- bfin_serial_reset_irda(port);
-
-#ifdef CONFIG_SERIAL_BFIN_DMA
- if (uart->tx_done)
- bfin_serial_dma_tx_chars(uart);
-#else
- UART_SET_IER(uart, ETBEI);
- bfin_serial_tx_chars(uart);
-#endif
-}
-
-/*
- * Interrupts are enabled
- */
-static void bfin_serial_stop_rx(struct uart_port *port)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-
- UART_CLEAR_IER(uart, ERBFI);
-}
-
-#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
-# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
-# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
-#else
-# define UART_GET_ANOMALY_THRESHOLD(uart) 0
-# define UART_SET_ANOMALY_THRESHOLD(uart, v)
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_PIO
-static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
-{
- unsigned int status, ch, flg;
- static u64 anomaly_start;
-
- status = UART_GET_LSR(uart);
- UART_CLEAR_LSR(uart);
-
- ch = UART_GET_CHAR(uart);
- uart->port.icount.rx++;
-
-#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
- defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
- if (kgdb_connected && kgdboc_port_line == uart->port.line
- && kgdboc_break_enabled)
- if (ch == 0x3) {/* Ctrl + C */
- kgdb_breakpoint();
- return;
- }
-
- if (!uart->port.state)
- return;
-#endif
- if (ANOMALY_05000363) {
- /* The BF533 (and BF561) family of processors have a nice anomaly
- * where they continuously generate characters for a "single" break.
- * We have to basically ignore this flood until the "next" valid
- * character comes across. Due to the nature of the flood, it is
- * not possible to reliably catch bytes that are sent too quickly
- * after this break. So application code talking to the Blackfin
- * which sends a break signal must allow at least 1.5 character
- * times after the end of the break for things to stabilize. This
- * timeout was picked as it must absolutely be larger than 1
- * character time +/- some percent. So 1.5 sounds good. All other
- * Blackfin families operate properly. Woo.
- */
- if (anomaly_start > 0) {
- u64 curr, nsecs, threshold_ns;
-
- if ((~ch & (~ch + 1)) & 0xff)
- goto known_good_char;
-
- curr = ktime_get_ns();
- nsecs = curr - anomaly_start;
- if (nsecs >> 32)
- goto known_good_char;
-
- threshold_ns = UART_GET_ANOMALY_THRESHOLD(uart)
- * NSEC_PER_USEC;
- if (nsecs > threshold_ns)
- goto known_good_char;
-
- if (ch)
- anomaly_start = 0;
- else
- anomaly_start = curr;
-
- return;
-
- known_good_char:
- status &= ~BI;
- anomaly_start = 0;
- }
- }
-
- if (status & BI) {
- if (ANOMALY_05000363)
- if (bfin_revid() < 5)
- anomaly_start = ktime_get_ns();
- uart->port.icount.brk++;
- if (uart_handle_break(&uart->port))
- goto ignore_char;
- status &= ~(PE | FE);
- }
- if (status & PE)
- uart->port.icount.parity++;
- if (status & OE)
- uart->port.icount.overrun++;
- if (status & FE)
- uart->port.icount.frame++;
-
- status &= uart->port.read_status_mask;
-
- if (status & BI)
- flg = TTY_BREAK;
- else if (status & PE)
- flg = TTY_PARITY;
- else if (status & FE)
- flg = TTY_FRAME;
- else
- flg = TTY_NORMAL;
-
- if (uart_handle_sysrq_char(&uart->port, ch))
- goto ignore_char;
-
- uart_insert_char(&uart->port, status, OE, ch, flg);
-
- ignore_char:
- tty_flip_buffer_push(&uart->port.state->port);
-}
-
-static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
-{
- struct circ_buf *xmit = &uart->port.state->xmit;
-
- if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
- /* Clear TFI bit */
- UART_PUT_LSR(uart, TFI);
-#endif
- /* Anomaly notes:
- * 05000215 - we always clear ETBEI within last UART TX
- * interrupt to end a string. It is always set
- * when start a new tx.
- */
- UART_CLEAR_IER(uart, ETBEI);
- return;
- }
-
- if (uart->port.x_char) {
- UART_PUT_CHAR(uart, uart->port.x_char);
- uart->port.icount.tx++;
- uart->port.x_char = 0;
- }
-
- while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
- UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
- uart->port.icount.tx++;
- }
-
- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
- uart_write_wakeup(&uart->port);
-}
-
-static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
-{
- struct bfin_serial_port *uart = dev_id;
-
- while (UART_GET_LSR(uart) & DR)
- bfin_serial_rx_chars(uart);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
-{
- struct bfin_serial_port *uart = dev_id;
-
- spin_lock(&uart->port.lock);
- if (UART_GET_LSR(uart) & THRE)
- bfin_serial_tx_chars(uart);
- spin_unlock(&uart->port.lock);
-
- return IRQ_HANDLED;
-}
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_DMA
-static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
-{
- struct circ_buf *xmit = &uart->port.state->xmit;
-
- uart->tx_done = 0;
-
- if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
- uart->tx_count = 0;
- uart->tx_done = 1;
- return;
- }
-
- if (uart->port.x_char) {
- UART_PUT_CHAR(uart, uart->port.x_char);
- uart->port.icount.tx++;
- uart->port.x_char = 0;
- }
-
- uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
- if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
- uart->tx_count = UART_XMIT_SIZE - xmit->tail;
- blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
- (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
- set_dma_config(uart->tx_dma_channel,
- set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
- INTR_ON_BUF,
- DIMENSION_LINEAR,
- DATA_SIZE_8,
- DMA_SYNC_RESTART));
- set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
- set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
- set_dma_x_modify(uart->tx_dma_channel, 1);
- SSYNC();
- enable_dma(uart->tx_dma_channel);
-
- UART_SET_IER(uart, ETBEI);
-}
-
-static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
-{
- int i, flg, status;
-
- status = UART_GET_LSR(uart);
- UART_CLEAR_LSR(uart);
-
- uart->port.icount.rx +=
- CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
- UART_XMIT_SIZE);
-
- if (status & BI) {
- uart->port.icount.brk++;
- if (uart_handle_break(&uart->port))
- goto dma_ignore_char;
- status &= ~(PE | FE);
- }
- if (status & PE)
- uart->port.icount.parity++;
- if (status & OE)
- uart->port.icount.overrun++;
- if (status & FE)
- uart->port.icount.frame++;
-
- status &= uart->port.read_status_mask;
-
- if (status & BI)
- flg = TTY_BREAK;
- else if (status & PE)
- flg = TTY_PARITY;
- else if (status & FE)
- flg = TTY_FRAME;
- else
- flg = TTY_NORMAL;
-
- for (i = uart->rx_dma_buf.tail; ; i++) {
- if (i >= UART_XMIT_SIZE)
- i = 0;
- if (i == uart->rx_dma_buf.head)
- break;
- if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
- uart_insert_char(&uart->port, status, OE,
- uart->rx_dma_buf.buf[i], flg);
- }
-
- dma_ignore_char:
- tty_flip_buffer_push(&uart->port.state->port);
-}
-
-void bfin_serial_rx_dma_timeout(struct timer_list *t)
-{
- struct bfin_serial_port *uart = from_timer(uart, t, rx_dma_timer);
- int x_pos, pos;
- unsigned long flags;
-
- dma_disable_irq_nosync(uart->rx_dma_channel);
- spin_lock_irqsave(&uart->rx_lock, flags);
-
- /* 2D DMA RX buffer ring is used. Because curr_y_count and
- * curr_x_count can't be read as an atomic operation,
- * curr_y_count should be read before curr_x_count. When
- * curr_x_count is read, curr_y_count may already indicate
- * next buffer line. But, the position calculated here is
- * still indicate the old line. The wrong position data may
- * be smaller than current buffer tail, which cause garbages
- * are received if it is not prohibit.
- */
- uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
- x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
- uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
- if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
- uart->rx_dma_nrows = 0;
- x_pos = DMA_RX_XCOUNT - x_pos;
- if (x_pos == DMA_RX_XCOUNT)
- x_pos = 0;
-
- pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
- /* Ignore receiving data if new position is in the same line of
- * current buffer tail and small.
- */
- if (pos > uart->rx_dma_buf.tail ||
- uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
- uart->rx_dma_buf.head = pos;
- bfin_serial_dma_rx_chars(uart);
- uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
- }
-
- spin_unlock_irqrestore(&uart->rx_lock, flags);
- dma_enable_irq(uart->rx_dma_channel);
-
- mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
-}
-
-static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
-{
- struct bfin_serial_port *uart = dev_id;
- struct circ_buf *xmit = &uart->port.state->xmit;
-
- spin_lock(&uart->port.lock);
- if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
- disable_dma(uart->tx_dma_channel);
- clear_dma_irqstat(uart->tx_dma_channel);
- /* Anomaly notes:
- * 05000215 - we always clear ETBEI within last UART TX
- * interrupt to end a string. It is always set
- * when start a new tx.
- */
- UART_CLEAR_IER(uart, ETBEI);
- uart->port.icount.tx += uart->tx_count;
- if (!(xmit->tail == 0 && xmit->head == 0)) {
- xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
-
- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
- uart_write_wakeup(&uart->port);
- }
-
- bfin_serial_dma_tx_chars(uart);
- }
-
- spin_unlock(&uart->port.lock);
- return IRQ_HANDLED;
-}
-
-static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
-{
- struct bfin_serial_port *uart = dev_id;
- unsigned int irqstat;
- int x_pos, pos;
-
- spin_lock(&uart->rx_lock);
- irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
- clear_dma_irqstat(uart->rx_dma_channel);
-
- uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
- x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
- uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
- if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
- uart->rx_dma_nrows = 0;
-
- pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
- if (pos > uart->rx_dma_buf.tail ||
- uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
- uart->rx_dma_buf.head = pos;
- bfin_serial_dma_rx_chars(uart);
- uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
- }
-
- spin_unlock(&uart->rx_lock);
-
- return IRQ_HANDLED;
-}
-#endif
-
-/*
- * Return TIOCSER_TEMT when transmitter is not busy.
- */
-static unsigned int bfin_serial_tx_empty(struct uart_port *port)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
- unsigned int lsr;
-
- lsr = UART_GET_LSR(uart);
- if (lsr & TEMT)
- return TIOCSER_TEMT;
- else
- return 0;
-}
-
-static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
- u32 lcr = UART_GET_LCR(uart);
- if (break_state)
- lcr |= SB;
- else
- lcr &= ~SB;
- UART_PUT_LCR(uart, lcr);
- SSYNC();
-}
-
-static int bfin_serial_startup(struct uart_port *port)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-
-#ifdef CONFIG_SERIAL_BFIN_DMA
- dma_addr_t dma_handle;
-
- if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
- printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
- return -EBUSY;
- }
-
- if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
- printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
- free_dma(uart->rx_dma_channel);
- return -EBUSY;
- }
-
- set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
- set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
-
- uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
- uart->rx_dma_buf.head = 0;
- uart->rx_dma_buf.tail = 0;
- uart->rx_dma_nrows = 0;
-
- set_dma_config(uart->rx_dma_channel,
- set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
- INTR_ON_ROW, DIMENSION_2D,
- DATA_SIZE_8,
- DMA_SYNC_RESTART));
- set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
- set_dma_x_modify(uart->rx_dma_channel, 1);
- set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
- set_dma_y_modify(uart->rx_dma_channel, 1);
- set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
- enable_dma(uart->rx_dma_channel);
-
- uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
- add_timer(&(uart->rx_dma_timer));
-#else
-# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
- defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
- if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
- kgdboc_break_enabled = 0;
- else {
-# endif
- if (request_irq(uart->rx_irq, bfin_serial_rx_int, 0,
- "BFIN_UART_RX", uart)) {
- printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
- return -EBUSY;
- }
-
- if (request_irq
- (uart->tx_irq, bfin_serial_tx_int, 0,
- "BFIN_UART_TX", uart)) {
- printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
- free_irq(uart->rx_irq, uart);
- return -EBUSY;
- }
-
-# ifdef CONFIG_BF54x
- {
- /*
- * UART2 and UART3 on BF548 share interrupt PINs and DMA
- * controllers with SPORT2 and SPORT3. UART rx and tx
- * interrupts are generated in PIO mode only when configure
- * their peripheral mapping registers properly, which means
- * request corresponding DMA channels in PIO mode as well.
- */
- unsigned uart_dma_ch_rx, uart_dma_ch_tx;
-
- switch (uart->rx_irq) {
- case IRQ_UART3_RX:
- uart_dma_ch_rx = CH_UART3_RX;
- uart_dma_ch_tx = CH_UART3_TX;
- break;
- case IRQ_UART2_RX:
- uart_dma_ch_rx = CH_UART2_RX;
- uart_dma_ch_tx = CH_UART2_TX;
- break;
- default:
- uart_dma_ch_rx = uart_dma_ch_tx = 0;
- break;
- }
-
- if (uart_dma_ch_rx &&
- request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
- printk(KERN_NOTICE"Fail to attach UART interrupt\n");
- free_irq(uart->rx_irq, uart);
- free_irq(uart->tx_irq, uart);
- return -EBUSY;
- }
- if (uart_dma_ch_tx &&
- request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
- printk(KERN_NOTICE "Fail to attach UART interrupt\n");
- free_dma(uart_dma_ch_rx);
- free_irq(uart->rx_irq, uart);
- free_irq(uart->tx_irq, uart);
- return -EBUSY;
- }
- }
-# endif
-# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
- defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
- }
-# endif
-#endif
-
-#ifdef SERIAL_BFIN_CTSRTS
- if (uart->cts_pin >= 0) {
- if (request_irq(gpio_to_irq(uart->cts_pin),
- bfin_serial_mctrl_cts_int,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
- 0, "BFIN_UART_CTS", uart)) {
- uart->cts_pin = -1;
- pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n");
- }
- }
- if (uart->rts_pin >= 0) {
- if (gpio_request(uart->rts_pin, DRIVER_NAME)) {
- pr_info("fail to request RTS PIN at GPIO_%d\n", uart->rts_pin);
- uart->rts_pin = -1;
- } else
- gpio_direction_output(uart->rts_pin, 0);
- }
-#endif
-#ifdef SERIAL_BFIN_HARD_CTSRTS
- if (uart->cts_pin >= 0) {
- if (request_irq(uart->status_irq, bfin_serial_mctrl_cts_int,
- 0, "BFIN_UART_MODEM_STATUS", uart)) {
- uart->cts_pin = -1;
- dev_info(port->dev, "Unable to attach BlackFin UART Modem Status interrupt.\n");
- }
-
- /* CTS RTS PINs are negative assertive. */
- UART_PUT_MCR(uart, UART_GET_MCR(uart) | ACTS);
- UART_SET_IER(uart, EDSSI);
- }
-#endif
-
- UART_SET_IER(uart, ERBFI);
- return 0;
-}
-
-static void bfin_serial_shutdown(struct uart_port *port)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-
-#ifdef CONFIG_SERIAL_BFIN_DMA
- disable_dma(uart->tx_dma_channel);
- free_dma(uart->tx_dma_channel);
- disable_dma(uart->rx_dma_channel);
- free_dma(uart->rx_dma_channel);
- del_timer(&(uart->rx_dma_timer));
- dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
-#else
-#ifdef CONFIG_BF54x
- switch (uart->port.irq) {
- case IRQ_UART3_RX:
- free_dma(CH_UART3_RX);
- free_dma(CH_UART3_TX);
- break;
- case IRQ_UART2_RX:
- free_dma(CH_UART2_RX);
- free_dma(CH_UART2_TX);
- break;
- default:
- break;
- }
-#endif
- free_irq(uart->rx_irq, uart);
- free_irq(uart->tx_irq, uart);
-#endif
-
-#ifdef SERIAL_BFIN_CTSRTS
- if (uart->cts_pin >= 0)
- free_irq(gpio_to_irq(uart->cts_pin), uart);
- if (uart->rts_pin >= 0)
- gpio_free(uart->rts_pin);
-#endif
-#ifdef SERIAL_BFIN_HARD_CTSRTS
- if (uart->cts_pin >= 0)
- free_irq(uart->status_irq, uart);
-#endif
-}
-
-static void
-bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
- struct ktermios *old)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
- unsigned long flags;
- unsigned int baud, quot;
- unsigned int ier, lcr = 0;
- unsigned long timeout;
-
-#ifdef SERIAL_BFIN_CTSRTS
- if (old == NULL && uart->cts_pin != -1)
- termios->c_cflag |= CRTSCTS;
- else if (uart->cts_pin == -1)
- termios->c_cflag &= ~CRTSCTS;
-#endif
-
- switch (termios->c_cflag & CSIZE) {
- case CS8:
- lcr = WLS(8);
- break;
- case CS7:
- lcr = WLS(7);
- break;
- case CS6:
- lcr = WLS(6);
- break;
- case CS5:
- lcr = WLS(5);
- break;
- default:
- printk(KERN_ERR "%s: word length not supported\n",
- __func__);
- }
-
- /* Anomaly notes:
- * 05000231 - STOP bit is always set to 1 whatever the user is set.
- */
- if (termios->c_cflag & CSTOPB) {
- if (ANOMALY_05000231)
- printk(KERN_WARNING "STOP bits other than 1 is not "
- "supported in case of anomaly 05000231.\n");
- else
- lcr |= STB;
- }
- if (termios->c_cflag & PARENB)
- lcr |= PEN;
- if (!(termios->c_cflag & PARODD))
- lcr |= EPS;
- if (termios->c_cflag & CMSPAR)
- lcr |= STP;
-
- spin_lock_irqsave(&uart->port.lock, flags);
-
- port->read_status_mask = OE;
- if (termios->c_iflag & INPCK)
- port->read_status_mask |= (FE | PE);
- if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
- port->read_status_mask |= BI;
-
- /*
- * Characters to ignore
- */
- port->ignore_status_mask = 0;
- if (termios->c_iflag & IGNPAR)
- port->ignore_status_mask |= FE | PE;
- if (termios->c_iflag & IGNBRK) {
- port->ignore_status_mask |= BI;
- /*
- * If we're ignoring parity and break indicators,
- * ignore overruns too (for real raw support).
- */
- if (termios->c_iflag & IGNPAR)
- port->ignore_status_mask |= OE;
- }
-
- baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
- quot = uart_get_divisor(port, baud);
-
- /* If discipline is not IRDA, apply ANOMALY_05000230 */
- if (termios->c_line != N_IRDA)
- quot -= ANOMALY_05000230;
-
- UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
-
- /* Wait till the transfer buffer is empty */
- timeout = jiffies + msecs_to_jiffies(10);
- while (UART_GET_GCTL(uart) & UCEN && !(UART_GET_LSR(uart) & TEMT))
- if (time_after(jiffies, timeout)) {
- dev_warn(port->dev, "timeout waiting for TX buffer empty\n");
- break;
- }
-
- /* Disable UART */
- ier = UART_GET_IER(uart);
- UART_PUT_GCTL(uart, UART_GET_GCTL(uart) & ~UCEN);
- UART_DISABLE_INTS(uart);
-
- /* Set DLAB in LCR to Access CLK */
- UART_SET_DLAB(uart);
-
- UART_PUT_CLK(uart, quot);
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- UART_CLEAR_DLAB(uart);
-
- UART_PUT_LCR(uart, (UART_GET_LCR(uart) & ~LCR_MASK) | lcr);
-
- /* Enable UART */
- UART_ENABLE_INTS(uart, ier);
- UART_PUT_GCTL(uart, UART_GET_GCTL(uart) | UCEN);
-
- /* Port speed changed, update the per-port timeout. */
- uart_update_timeout(port, termios->c_cflag, baud);
-
- spin_unlock_irqrestore(&uart->port.lock, flags);
-}
-
-static const char *bfin_serial_type(struct uart_port *port)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-
- return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
-}
-
-/*
- * Release the memory region(s) being used by 'port'.
- */
-static void bfin_serial_release_port(struct uart_port *port)
-{
-}
-
-/*
- * Request the memory region(s) being used by 'port'.
- */
-static int bfin_serial_request_port(struct uart_port *port)
-{
- return 0;
-}
-
-/*
- * Configure/autoconfigure the port.
- */
-static void bfin_serial_config_port(struct uart_port *port, int flags)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-
- if (flags & UART_CONFIG_TYPE &&
- bfin_serial_request_port(&uart->port) == 0)
- uart->port.type = PORT_BFIN;
-}
-
-/*
- * Verify the new serial_struct (for TIOCSSERIAL).
- * The only change we allow are to the flags and type, and
- * even then only between PORT_BFIN and PORT_UNKNOWN
- */
-static int
-bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
-{
- return 0;
-}
-
-/*
- * Enable the IrDA function if tty->ldisc.num is N_IRDA.
- * In other cases, disable IrDA function.
- */
-static void bfin_serial_set_ldisc(struct uart_port *port,
- struct ktermios *termios)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
- unsigned int val;
-
- switch (termios->c_line) {
- case N_IRDA:
- val = UART_GET_GCTL(uart);
- val |= (UMOD_IRDA | RPOLC);
- UART_PUT_GCTL(uart, val);
- break;
- default:
- val = UART_GET_GCTL(uart);
- val &= ~(UMOD_MASK | RPOLC);
- UART_PUT_GCTL(uart, val);
- }
-}
-
-static void bfin_serial_reset_irda(struct uart_port *port)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
- unsigned int val;
-
- val = UART_GET_GCTL(uart);
- val &= ~(UMOD_MASK | RPOLC);
- UART_PUT_GCTL(uart, val);
- SSYNC();
- val |= (UMOD_IRDA | RPOLC);
- UART_PUT_GCTL(uart, val);
- SSYNC();
-}
-
-#ifdef CONFIG_CONSOLE_POLL
-/* Anomaly notes:
- * 05000099 - Because we only use THRE in poll_put and DR in poll_get,
- * losing other bits of UART_LSR is not a problem here.
- */
-static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-
- while (!(UART_GET_LSR(uart) & THRE))
- cpu_relax();
-
- UART_CLEAR_DLAB(uart);
- UART_PUT_CHAR(uart, (unsigned char)chr);
-}
-
-static int bfin_serial_poll_get_char(struct uart_port *port)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
- unsigned char chr;
-
- while (!(UART_GET_LSR(uart) & DR))
- cpu_relax();
-
- UART_CLEAR_DLAB(uart);
- chr = UART_GET_CHAR(uart);
-
- return chr;
-}
-#endif
-
-static struct uart_ops bfin_serial_pops = {
- .tx_empty = bfin_serial_tx_empty,
- .set_mctrl = bfin_serial_set_mctrl,
- .get_mctrl = bfin_serial_get_mctrl,
- .stop_tx = bfin_serial_stop_tx,
- .start_tx = bfin_serial_start_tx,
- .stop_rx = bfin_serial_stop_rx,
- .break_ctl = bfin_serial_break_ctl,
- .startup = bfin_serial_startup,
- .shutdown = bfin_serial_shutdown,
- .set_termios = bfin_serial_set_termios,
- .set_ldisc = bfin_serial_set_ldisc,
- .type = bfin_serial_type,
- .release_port = bfin_serial_release_port,
- .request_port = bfin_serial_request_port,
- .config_port = bfin_serial_config_port,
- .verify_port = bfin_serial_verify_port,
-#ifdef CONFIG_CONSOLE_POLL
- .poll_put_char = bfin_serial_poll_put_char,
- .poll_get_char = bfin_serial_poll_get_char,
-#endif
-};
-
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-/*
- * If the port was already initialised (eg, by a boot loader),
- * try to determine the current setup.
- */
-static void __init
-bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
- int *parity, int *bits)
-{
- unsigned int status;
-
- status = UART_GET_IER(uart) & (ERBFI | ETBEI);
- if (status == (ERBFI | ETBEI)) {
- /* ok, the port was enabled */
- u32 lcr, clk;
-
- lcr = UART_GET_LCR(uart);
-
- *parity = 'n';
- if (lcr & PEN) {
- if (lcr & EPS)
- *parity = 'e';
- else
- *parity = 'o';
- }
- *bits = ((lcr & WLS_MASK) >> WLS_OFFSET) + 5;
-
- /* Set DLAB in LCR to Access CLK */
- UART_SET_DLAB(uart);
-
- clk = UART_GET_CLK(uart);
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- UART_CLEAR_DLAB(uart);
-
- *baud = get_sclk() / (16*clk);
- }
- pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
-}
-
-static struct uart_driver bfin_serial_reg;
-
-static void bfin_serial_console_putchar(struct uart_port *port, int ch)
-{
- struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
- while (!(UART_GET_LSR(uart) & THRE))
- barrier();
- UART_PUT_CHAR(uart, ch);
-}
-
-#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
- defined (CONFIG_EARLY_PRINTK) */
-
-#ifdef CONFIG_SERIAL_BFIN_CONSOLE
-#define CLASS_BFIN_CONSOLE "bfin-console"
-/*
- * Interrupts are disabled on entering
- */
-static void
-bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
-{
- struct bfin_serial_port *uart = bfin_serial_ports[co->index];
- unsigned long flags;
-
- spin_lock_irqsave(&uart->port.lock, flags);
- uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
- spin_unlock_irqrestore(&uart->port.lock, flags);
-
-}
-
-static int __init
-bfin_serial_console_setup(struct console *co, char *options)
-{
- struct bfin_serial_port *uart;
- int baud = 57600;
- int bits = 8;
- int parity = 'n';
-# if defined(SERIAL_BFIN_CTSRTS) || \
- defined(SERIAL_BFIN_HARD_CTSRTS)
- int flow = 'r';
-# else
- int flow = 'n';
-# endif
-
- /*
- * Check whether an invalid uart number has been specified, and
- * if so, search for the first available port that does have
- * console support.
- */
- if (co->index < 0 || co->index >= BFIN_UART_NR_PORTS)
- return -ENODEV;
-
- uart = bfin_serial_ports[co->index];
- if (!uart)
- return -ENODEV;
-
- if (options)
- uart_parse_options(options, &baud, &parity, &bits, &flow);
- else
- bfin_serial_console_get_options(uart, &baud, &parity, &bits);
-
- return uart_set_options(&uart->port, co, baud, parity, bits, flow);
-}
-
-static struct console bfin_serial_console = {
- .name = BFIN_SERIAL_DEV_NAME,
- .write = bfin_serial_console_write,
- .device = uart_console_device,
- .setup = bfin_serial_console_setup,
- .flags = CON_PRINTBUFFER,
- .index = -1,
- .data = &bfin_serial_reg,
-};
-#define BFIN_SERIAL_CONSOLE (&bfin_serial_console)
-#else
-#define BFIN_SERIAL_CONSOLE NULL
-#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
-
-#ifdef CONFIG_EARLY_PRINTK
-static struct bfin_serial_port bfin_earlyprintk_port;
-#define CLASS_BFIN_EARLYPRINTK "bfin-earlyprintk"
-
-/*
- * Interrupts are disabled on entering
- */
-static void
-bfin_earlyprintk_console_write(struct console *co, const char *s, unsigned int count)
-{
- unsigned long flags;
-
- if (bfin_earlyprintk_port.port.line != co->index)
- return;
-
- spin_lock_irqsave(&bfin_earlyprintk_port.port.lock, flags);
- uart_console_write(&bfin_earlyprintk_port.port, s, count,
- bfin_serial_console_putchar);
- spin_unlock_irqrestore(&bfin_earlyprintk_port.port.lock, flags);
-}
-
-/*
- * This should have a .setup or .early_setup in it, but then things get called
- * without the command line options, and the baud rate gets messed up - so
- * don't let the common infrastructure play with things. (see calls to setup
- * & earlysetup in ./kernel/printk.c:register_console()
- */
-static struct console bfin_early_serial_console __initdata = {
- .name = "early_BFuart",
- .write = bfin_earlyprintk_console_write,
- .device = uart_console_device,
- .flags = CON_PRINTBUFFER,
- .index = -1,
- .data = &bfin_serial_reg,
-};
-#endif
-
-static struct uart_driver bfin_serial_reg = {
- .owner = THIS_MODULE,
- .driver_name = DRIVER_NAME,
- .dev_name = BFIN_SERIAL_DEV_NAME,
- .major = BFIN_SERIAL_MAJOR,
- .minor = BFIN_SERIAL_MINOR,
- .nr = BFIN_UART_NR_PORTS,
- .cons = BFIN_SERIAL_CONSOLE,
-};
-
-static int bfin_serial_suspend(struct platform_device *pdev, pm_message_t state)
-{
- struct bfin_serial_port *uart = platform_get_drvdata(pdev);
-
- return uart_suspend_port(&bfin_serial_reg, &uart->port);
-}
-
-static int bfin_serial_resume(struct platform_device *pdev)
-{
- struct bfin_serial_port *uart = platform_get_drvdata(pdev);
-
- return uart_resume_port(&bfin_serial_reg, &uart->port);
-}
-
-static int bfin_serial_probe(struct platform_device *pdev)
-{
- struct resource *res;
- struct bfin_serial_port *uart = NULL;
- int ret = 0;
-
- if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
- dev_err(&pdev->dev, "Wrong bfin uart platform device id.\n");
- return -ENOENT;
- }
-
- if (bfin_serial_ports[pdev->id] == NULL) {
-
- uart = kzalloc(sizeof(*uart), GFP_KERNEL);
- if (!uart) {
- dev_err(&pdev->dev,
- "fail to malloc bfin_serial_port\n");
- return -ENOMEM;
- }
- bfin_serial_ports[pdev->id] = uart;
-
-#ifdef CONFIG_EARLY_PRINTK
- if (!(bfin_earlyprintk_port.port.membase
- && bfin_earlyprintk_port.port.line == pdev->id)) {
- /*
- * If the peripheral PINs of current port is allocated
- * in earlyprintk probe stage, don't do it again.
- */
-#endif
- ret = peripheral_request_list(
- dev_get_platdata(&pdev->dev),
- DRIVER_NAME);
- if (ret) {
- dev_err(&pdev->dev,
- "fail to request bfin serial peripherals\n");
- goto out_error_free_mem;
- }
-#ifdef CONFIG_EARLY_PRINTK
- }
-#endif
-
- spin_lock_init(&uart->port.lock);
- uart->port.uartclk = get_sclk();
- uart->port.fifosize = BFIN_UART_TX_FIFO_SIZE;
- uart->port.ops = &bfin_serial_pops;
- uart->port.line = pdev->id;
- uart->port.iotype = UPIO_MEM;
- uart->port.flags = UPF_BOOT_AUTOCONF;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL) {
- dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
- ret = -ENOENT;
- goto out_error_free_peripherals;
- }
-
- uart->port.membase = ioremap(res->start, resource_size(res));
- if (!uart->port.membase) {
- dev_err(&pdev->dev, "Cannot map uart IO\n");
- ret = -ENXIO;
- goto out_error_free_peripherals;
- }
- uart->port.mapbase = res->start;
-
- uart->tx_irq = platform_get_irq(pdev, 0);
- if (uart->tx_irq < 0) {
- dev_err(&pdev->dev, "No uart TX IRQ specified\n");
- ret = -ENOENT;
- goto out_error_unmap;
- }
-
- uart->rx_irq = platform_get_irq(pdev, 1);
- if (uart->rx_irq < 0) {
- dev_err(&pdev->dev, "No uart RX IRQ specified\n");
- ret = -ENOENT;
- goto out_error_unmap;
- }
- uart->port.irq = uart->rx_irq;
-
- uart->status_irq = platform_get_irq(pdev, 2);
- if (uart->status_irq < 0) {
- dev_err(&pdev->dev, "No uart status IRQ specified\n");
- ret = -ENOENT;
- goto out_error_unmap;
- }
-
-#ifdef CONFIG_SERIAL_BFIN_DMA
- spin_lock_init(&uart->rx_lock);
- uart->tx_done = 1;
- uart->tx_count = 0;
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (res == NULL) {
- dev_err(&pdev->dev, "No uart TX DMA channel specified\n");
- ret = -ENOENT;
- goto out_error_unmap;
- }
- uart->tx_dma_channel = res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
- if (res == NULL) {
- dev_err(&pdev->dev, "No uart RX DMA channel specified\n");
- ret = -ENOENT;
- goto out_error_unmap;
- }
- uart->rx_dma_channel = res->start;
-
- timer_setup(&uart->rx_dma_timer, bfin_serial_rx_dma_timeout, 0);
-#endif
-
-#if defined(SERIAL_BFIN_CTSRTS) || \
- defined(SERIAL_BFIN_HARD_CTSRTS)
- res = platform_get_resource(pdev, IORESOURCE_IO, 0);
- if (res == NULL)
- uart->cts_pin = -1;
- else
- uart->cts_pin = res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_IO, 1);
- if (res == NULL)
- uart->rts_pin = -1;
- else
- uart->rts_pin = res->start;
-#endif
- }
-
-#ifdef CONFIG_SERIAL_BFIN_CONSOLE
- if (!is_early_platform_device(pdev)) {
-#endif
- uart = bfin_serial_ports[pdev->id];
- uart->port.dev = &pdev->dev;
- dev_set_drvdata(&pdev->dev, uart);
- ret = uart_add_one_port(&bfin_serial_reg, &uart->port);
-#ifdef CONFIG_SERIAL_BFIN_CONSOLE
- }
-#endif
-
- if (!ret)
- return 0;
-
- if (uart) {
-out_error_unmap:
- iounmap(uart->port.membase);
-out_error_free_peripherals:
- peripheral_free_list(dev_get_platdata(&pdev->dev));
-out_error_free_mem:
- kfree(uart);
- bfin_serial_ports[pdev->id] = NULL;
- }
-
- return ret;
-}
-
-static int bfin_serial_remove(struct platform_device *pdev)
-{
- struct bfin_serial_port *uart = platform_get_drvdata(pdev);
-
- dev_set_drvdata(&pdev->dev, NULL);
-
- if (uart) {
- uart_remove_one_port(&bfin_serial_reg, &uart->port);
- iounmap(uart->port.membase);
- peripheral_free_list(dev_get_platdata(&pdev->dev));
- kfree(uart);
- bfin_serial_ports[pdev->id] = NULL;
- }
-
- return 0;
-}
-
-static struct platform_driver bfin_serial_driver = {
- .probe = bfin_serial_probe,
- .remove = bfin_serial_remove,
- .suspend = bfin_serial_suspend,
- .resume = bfin_serial_resume,
- .driver = {
- .name = DRIVER_NAME,
- },
-};
-
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE)
-static struct early_platform_driver early_bfin_serial_driver __initdata = {
- .class_str = CLASS_BFIN_CONSOLE,
- .pdrv = &bfin_serial_driver,
- .requested_id = EARLY_PLATFORM_ID_UNSET,
-};
-
-static int __init bfin_serial_rs_console_init(void)
-{
- early_platform_driver_register(&early_bfin_serial_driver, DRIVER_NAME);
-
- early_platform_driver_probe(CLASS_BFIN_CONSOLE, BFIN_UART_NR_PORTS, 0);
-
- register_console(&bfin_serial_console);
-
- return 0;
-}
-console_initcall(bfin_serial_rs_console_init);
-#endif
-
-#ifdef CONFIG_EARLY_PRINTK
-/*
- * Memory can't be allocated dynamically during earlyprink init stage.
- * So, do individual probe for earlyprink with a static uart port variable.
- */
-static int bfin_earlyprintk_probe(struct platform_device *pdev)
-{
- struct resource *res;
- int ret;
-
- if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
- dev_err(&pdev->dev, "Wrong earlyprintk platform device id.\n");
- return -ENOENT;
- }
-
- ret = peripheral_request_list(dev_get_platdata(&pdev->dev),
- DRIVER_NAME);
- if (ret) {
- dev_err(&pdev->dev,
- "fail to request bfin serial peripherals\n");
- return ret;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL) {
- dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
- ret = -ENOENT;
- goto out_error_free_peripherals;
- }
-
- bfin_earlyprintk_port.port.membase = ioremap(res->start,
- resource_size(res));
- if (!bfin_earlyprintk_port.port.membase) {
- dev_err(&pdev->dev, "Cannot map uart IO\n");
- ret = -ENXIO;
- goto out_error_free_peripherals;
- }
- bfin_earlyprintk_port.port.mapbase = res->start;
- bfin_earlyprintk_port.port.line = pdev->id;
- bfin_earlyprintk_port.port.uartclk = get_sclk();
- bfin_earlyprintk_port.port.fifosize = BFIN_UART_TX_FIFO_SIZE;
- spin_lock_init(&bfin_earlyprintk_port.port.lock);
-
- return 0;
-
-out_error_free_peripherals:
- peripheral_free_list(dev_get_platdata(&pdev->dev));
-
- return ret;
-}
-
-static struct platform_driver bfin_earlyprintk_driver = {
- .probe = bfin_earlyprintk_probe,
- .driver = {
- .name = DRIVER_NAME,
- .owner = THIS_MODULE,
- },
-};
-
-static struct early_platform_driver early_bfin_earlyprintk_driver __initdata = {
- .class_str = CLASS_BFIN_EARLYPRINTK,
- .pdrv = &bfin_earlyprintk_driver,
- .requested_id = EARLY_PLATFORM_ID_UNSET,
-};
-
-struct console __init *bfin_earlyserial_init(unsigned int port,
- unsigned int cflag)
-{
- struct ktermios t;
- char port_name[20];
-
- if (port < 0 || port >= BFIN_UART_NR_PORTS)
- return NULL;
-
- /*
- * Only probe resource of the given port in earlyprintk boot arg.
- * The expected port id should be indicated in port name string.
- */
- snprintf(port_name, 20, DRIVER_NAME ".%d", port);
- early_platform_driver_register(&early_bfin_earlyprintk_driver,
- port_name);
- early_platform_driver_probe(CLASS_BFIN_EARLYPRINTK, 1, 0);
-
- if (!bfin_earlyprintk_port.port.membase)
- return NULL;
-
-#ifdef CONFIG_SERIAL_BFIN_CONSOLE
- /*
- * If we are using early serial, don't let the normal console rewind
- * log buffer, since that causes things to be printed multiple times
- */
- bfin_serial_console.flags &= ~CON_PRINTBUFFER;
-#endif
-
- bfin_early_serial_console.index = port;
- t.c_cflag = cflag;
- t.c_iflag = 0;
- t.c_oflag = 0;
- t.c_lflag = ICANON;
- t.c_line = port;
- bfin_serial_set_termios(&bfin_earlyprintk_port.port, &t, &t);
-
- return &bfin_early_serial_console;
-}
-#endif /* CONFIG_EARLY_PRINTK */
-
-static int __init bfin_serial_init(void)
-{
- int ret;
-
- pr_info("Blackfin serial driver\n");
-
- ret = uart_register_driver(&bfin_serial_reg);
- if (ret) {
- pr_err("failed to register %s:%d\n",
- bfin_serial_reg.driver_name, ret);
- }
-
- ret = platform_driver_register(&bfin_serial_driver);
- if (ret) {
- pr_err("fail to register bfin uart\n");
- uart_unregister_driver(&bfin_serial_reg);
- }
-
- return ret;
-}
-
-static void __exit bfin_serial_exit(void)
-{
- platform_driver_unregister(&bfin_serial_driver);
- uart_unregister_driver(&bfin_serial_reg);
-}
-
-
-module_init(bfin_serial_init);
-module_exit(bfin_serial_exit);
-
-MODULE_AUTHOR("Sonic Zhang, Aubrey Li");
-MODULE_DESCRIPTION("Blackfin generic serial port driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
-MODULE_ALIAS("platform:bfin-uart");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 1c8413f..82712d0 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -155,9 +155,6 @@
/* Xilinx uartlite */
#define PORT_UARTLITE 74
-/* Blackfin bf5xx */
-#define PORT_BFIN 75
-
/* Micrel KS8695 */
#define PORT_KS8695 76
@@ -167,9 +164,6 @@
/* Freescale ColdFire */
#define PORT_MCF 78
-/* Blackfin SPORT */
-#define PORT_BFIN_SPORT 79
-
/* MN10300 on-chip UART numbers */
#define PORT_MN10300 80
#define PORT_MN10300_CTS 81
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 05/28] rtc: Remove Blackfin RTC support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (2 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 04/28] tty: Remove Blackfin tty and uart support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 06/28] mmc: Remove Blackfin SD host support Aaron Wu
` (22 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin RTC support
---
drivers/rtc/Kconfig | 10 --
drivers/rtc/Makefile | 1 -
drivers/rtc/rtc-bfin.c | 448 -------------------------------------------------
3 files changed, 459 deletions(-)
delete mode 100644 drivers/rtc/rtc-bfin.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8ab5f0a5..622d0ed2 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1434,16 +1434,6 @@ config RTC_DRV_AU1XXX
This driver can also be built as a module. If so, the module
will be called rtc-au1xxx.
-config RTC_DRV_BFIN
- tristate "Blackfin On-Chip RTC"
- depends on BLACKFIN && !BF561
- help
- If you say yes here you will get support for the
- Blackfin On-Chip Real Time Clock.
-
- This driver can also be built as a module. If so, the module
- will be called rtc-bfin.
-
config RTC_DRV_RS5C313
tristate "Ricoh RS5C313"
depends on SH_LANDISK
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4fbf87e4..014c8a8 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -36,7 +36,6 @@ obj-$(CONFIG_RTC_DRV_ASM9260) += rtc-asm9260.o
obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o
obj-$(CONFIG_RTC_DRV_AU1XXX) += rtc-au1xxx.o
-obj-$(CONFIG_RTC_DRV_BFIN) += rtc-bfin.o
obj-$(CONFIG_RTC_DRV_BRCMSTB) += rtc-brcmstb-waketimer.o
obj-$(CONFIG_RTC_DRV_BQ32K) += rtc-bq32k.o
obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o
diff --git a/drivers/rtc/rtc-bfin.c b/drivers/rtc/rtc-bfin.c
deleted file mode 100644
index 15344b7..0000000
--- a/drivers/rtc/rtc-bfin.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/*
- * Blackfin On-Chip Real Time Clock Driver
- * Supports BF51x/BF52x/BF53[123]/BF53[467]/BF54x
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* The biggest issue we deal with in this driver is that register writes are
- * synced to the RTC frequency of 1Hz. So if you write to a register and
- * attempt to write again before the first write has completed, the new write
- * is simply discarded. This can easily be troublesome if userspace disables
- * one event (say periodic) and then right after enables an event (say alarm).
- * Since all events are maintained in the same interrupt mask register, if
- * we wrote to it to disable the first event and then wrote to it again to
- * enable the second event, that second event would not be enabled as the
- * write would be discarded and things quickly fall apart.
- *
- * To keep this delay from significantly degrading performance (we, in theory,
- * would have to sleep for up to 1 second every time we wanted to write a
- * register), we only check the write pending status before we start to issue
- * a new write. We bank on the idea that it doesn't matter when the sync
- * happens so long as we don't attempt another write before it does. The only
- * time userspace would take this penalty is when they try and do multiple
- * operations right after another ... but in this case, they need to take the
- * sync penalty, so we should be OK.
- *
- * Also note that the RTC_ISTAT register does not suffer this penalty; its
- * writes to clear status registers complete immediately.
- */
-
-/* It may seem odd that there is no SWCNT code in here (which would be exposed
- * via the periodic interrupt event, or PIE). Since the Blackfin RTC peripheral
- * runs in units of seconds (N/HZ) but the Linux framework runs in units of HZ
- * (2^N HZ), there is no point in keeping code that only provides 1 HZ PIEs.
- * The same exact behavior can be accomplished by using the update interrupt
- * event (UIE). Maybe down the line the RTC peripheral will suck less in which
- * case we can re-introduce PIE support.
- */
-
-#include <linux/bcd.h>
-#include <linux/completion.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/rtc.h>
-#include <linux/seq_file.h>
-#include <linux/slab.h>
-
-#include <asm/blackfin.h>
-
-#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)
-
-struct bfin_rtc {
- struct rtc_device *rtc_dev;
- struct rtc_time rtc_alarm;
- u16 rtc_wrote_regs;
-};
-
-/* Bit values for the ISTAT / ICTL registers */
-#define RTC_ISTAT_WRITE_COMPLETE 0x8000
-#define RTC_ISTAT_WRITE_PENDING 0x4000
-#define RTC_ISTAT_ALARM_DAY 0x0040
-#define RTC_ISTAT_24HR 0x0020
-#define RTC_ISTAT_HOUR 0x0010
-#define RTC_ISTAT_MIN 0x0008
-#define RTC_ISTAT_SEC 0x0004
-#define RTC_ISTAT_ALARM 0x0002
-#define RTC_ISTAT_STOPWATCH 0x0001
-
-/* Shift values for RTC_STAT register */
-#define DAY_BITS_OFF 17
-#define HOUR_BITS_OFF 12
-#define MIN_BITS_OFF 6
-#define SEC_BITS_OFF 0
-
-/* Some helper functions to convert between the common RTC notion of time
- * and the internal Blackfin notion that is encoded in 32bits.
- */
-static inline u32 rtc_time_to_bfin(unsigned long now)
-{
- u32 sec = (now % 60);
- u32 min = (now % (60 * 60)) / 60;
- u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
- u32 days = (now / (60 * 60 * 24));
- return (sec << SEC_BITS_OFF) +
- (min << MIN_BITS_OFF) +
- (hour << HOUR_BITS_OFF) +
- (days << DAY_BITS_OFF);
-}
-static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
-{
- return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) +
- (((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) +
- (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
- (((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24);
-}
-static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
-{
- rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
-}
-
-/**
- * bfin_rtc_sync_pending - make sure pending writes have complete
- *
- * Wait for the previous write to a RTC register to complete.
- * Unfortunately, we can't sleep here as that introduces a race condition when
- * turning on interrupt events. Consider this:
- * - process sets alarm
- * - process enables alarm
- * - process sleeps while waiting for rtc write to sync
- * - interrupt fires while process is sleeping
- * - interrupt acks the event by writing to ISTAT
- * - interrupt sets the WRITE PENDING bit
- * - interrupt handler finishes
- * - process wakes up, sees WRITE PENDING bit set, goes to sleep
- * - interrupt fires while process is sleeping
- * If anyone can point out the obvious solution here, i'm listening :). This
- * shouldn't be an issue on an SMP or preempt system as this function should
- * only be called with the rtc lock held.
- *
- * Other options:
- * - disable PREN so the sync happens at 32.768kHZ ... but this changes the
- * inc rate for all RTC registers from 1HZ to 32.768kHZ ...
- * - use the write complete IRQ
- */
-/*
-static void bfin_rtc_sync_pending_polled(void)
-{
- while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE))
- if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
- break;
- bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
-}
-*/
-static DECLARE_COMPLETION(bfin_write_complete);
-static void bfin_rtc_sync_pending(struct device *dev)
-{
- dev_dbg_stamp(dev);
- while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
- wait_for_completion_timeout(&bfin_write_complete, HZ * 5);
- dev_dbg_stamp(dev);
-}
-
-/**
- * bfin_rtc_reset - set RTC to sane/known state
- *
- * Initialize the RTC. Enable pre-scaler to scale RTC clock
- * to 1Hz and clear interrupt/status registers.
- */
-static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl)
-{
- struct bfin_rtc *rtc = dev_get_drvdata(dev);
- dev_dbg_stamp(dev);
- bfin_rtc_sync_pending(dev);
- bfin_write_RTC_PREN(0x1);
- bfin_write_RTC_ICTL(rtc_ictl);
- bfin_write_RTC_ALARM(0);
- bfin_write_RTC_ISTAT(0xFFFF);
- rtc->rtc_wrote_regs = 0;
-}
-
-/**
- * bfin_rtc_interrupt - handle interrupt from RTC
- *
- * Since we handle all RTC events here, we have to make sure the requested
- * interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT)
- * always gets updated regardless of the interrupt being enabled. So when one
- * even we care about (e.g. stopwatch) goes off, we don't want to turn around
- * and say that other events have happened as well (e.g. second). We do not
- * have to worry about pending writes to the RTC_ICTL register as interrupts
- * only fire if they are enabled in the RTC_ICTL register.
- */
-static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
-{
- struct device *dev = dev_id;
- struct bfin_rtc *rtc = dev_get_drvdata(dev);
- unsigned long events = 0;
- bool write_complete = false;
- u16 rtc_istat, rtc_istat_clear, rtc_ictl, bits;
-
- dev_dbg_stamp(dev);
-
- rtc_istat = bfin_read_RTC_ISTAT();
- rtc_ictl = bfin_read_RTC_ICTL();
- rtc_istat_clear = 0;
-
- bits = RTC_ISTAT_WRITE_COMPLETE;
- if (rtc_istat & bits) {
- rtc_istat_clear |= bits;
- write_complete = true;
- complete(&bfin_write_complete);
- }
-
- bits = (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY);
- if (rtc_ictl & bits) {
- if (rtc_istat & bits) {
- rtc_istat_clear |= bits;
- events |= RTC_AF | RTC_IRQF;
- }
- }
-
- bits = RTC_ISTAT_SEC;
- if (rtc_ictl & bits) {
- if (rtc_istat & bits) {
- rtc_istat_clear |= bits;
- events |= RTC_UF | RTC_IRQF;
- }
- }
-
- if (events)
- rtc_update_irq(rtc->rtc_dev, 1, events);
-
- if (write_complete || events) {
- bfin_write_RTC_ISTAT(rtc_istat_clear);
- return IRQ_HANDLED;
- } else
- return IRQ_NONE;
-}
-
-static void bfin_rtc_int_set(u16 rtc_int)
-{
- bfin_write_RTC_ISTAT(rtc_int);
- bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int);
-}
-static void bfin_rtc_int_clear(u16 rtc_int)
-{
- bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int);
-}
-static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc)
-{
- /* Blackfin has different bits for whether the alarm is
- * more than 24 hours away.
- */
- bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY);
-}
-
-static int bfin_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
-{
- struct bfin_rtc *rtc = dev_get_drvdata(dev);
-
- dev_dbg_stamp(dev);
- if (enabled)
- bfin_rtc_int_set_alarm(rtc);
- else
- bfin_rtc_int_clear(~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
-
- return 0;
-}
-
-static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm)
-{
- struct bfin_rtc *rtc = dev_get_drvdata(dev);
-
- dev_dbg_stamp(dev);
-
- if (rtc->rtc_wrote_regs & 0x1)
- bfin_rtc_sync_pending(dev);
-
- rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);
-
- return 0;
-}
-
-static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm)
-{
- struct bfin_rtc *rtc = dev_get_drvdata(dev);
- int ret;
- unsigned long now;
-
- dev_dbg_stamp(dev);
-
- ret = rtc_tm_to_time(tm, &now);
- if (ret == 0) {
- if (rtc->rtc_wrote_regs & 0x1)
- bfin_rtc_sync_pending(dev);
- bfin_write_RTC_STAT(rtc_time_to_bfin(now));
- rtc->rtc_wrote_regs = 0x1;
- }
-
- return ret;
-}
-
-static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
-{
- struct bfin_rtc *rtc = dev_get_drvdata(dev);
- dev_dbg_stamp(dev);
- alrm->time = rtc->rtc_alarm;
- bfin_rtc_sync_pending(dev);
- alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
- return 0;
-}
-
-static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
-{
- struct bfin_rtc *rtc = dev_get_drvdata(dev);
- unsigned long rtc_alarm;
-
- dev_dbg_stamp(dev);
-
- if (rtc_tm_to_time(&alrm->time, &rtc_alarm))
- return -EINVAL;
-
- rtc->rtc_alarm = alrm->time;
-
- bfin_rtc_sync_pending(dev);
- bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
- if (alrm->enabled)
- bfin_rtc_int_set_alarm(rtc);
-
- return 0;
-}
-
-static int bfin_rtc_proc(struct device *dev, struct seq_file *seq)
-{
-#define yesno(x) ((x) ? "yes" : "no")
- u16 ictl = bfin_read_RTC_ICTL();
- dev_dbg_stamp(dev);
- seq_printf(seq,
- "alarm_IRQ\t: %s\n"
- "wkalarm_IRQ\t: %s\n"
- "seconds_IRQ\t: %s\n",
- yesno(ictl & RTC_ISTAT_ALARM),
- yesno(ictl & RTC_ISTAT_ALARM_DAY),
- yesno(ictl & RTC_ISTAT_SEC));
- return 0;
-#undef yesno
-}
-
-static const struct rtc_class_ops bfin_rtc_ops = {
- .read_time = bfin_rtc_read_time,
- .set_time = bfin_rtc_set_time,
- .read_alarm = bfin_rtc_read_alarm,
- .set_alarm = bfin_rtc_set_alarm,
- .proc = bfin_rtc_proc,
- .alarm_irq_enable = bfin_rtc_alarm_irq_enable,
-};
-
-static int bfin_rtc_probe(struct platform_device *pdev)
-{
- struct bfin_rtc *rtc;
- struct device *dev = &pdev->dev;
- int ret;
- unsigned long timeout = jiffies + HZ;
-
- dev_dbg_stamp(dev);
-
- /* Allocate memory for our RTC struct */
- rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
- if (unlikely(!rtc))
- return -ENOMEM;
- platform_set_drvdata(pdev, rtc);
- device_init_wakeup(dev, 1);
-
- /* Register our RTC with the RTC framework */
- rtc->rtc_dev = devm_rtc_device_register(dev, pdev->name, &bfin_rtc_ops,
- THIS_MODULE);
- if (IS_ERR(rtc->rtc_dev))
- return PTR_ERR(rtc->rtc_dev);
-
- /* Grab the IRQ and init the hardware */
- ret = devm_request_irq(dev, IRQ_RTC, bfin_rtc_interrupt, 0,
- pdev->name, dev);
- if (unlikely(ret))
- dev_err(&pdev->dev,
- "unable to request IRQ; alarm won't work, "
- "and writes will be delayed\n");
-
- /* sometimes the bootloader touched things, but the write complete was not
- * enabled, so let's just do a quick timeout here since the IRQ will not fire ...
- */
- while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
- if (time_after(jiffies, timeout))
- break;
- bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE);
- bfin_write_RTC_SWCNT(0);
-
- return 0;
-}
-
-static int bfin_rtc_remove(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
-
- bfin_rtc_reset(dev, 0);
-
- return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int bfin_rtc_suspend(struct device *dev)
-{
- dev_dbg_stamp(dev);
-
- if (device_may_wakeup(dev)) {
- enable_irq_wake(IRQ_RTC);
- bfin_rtc_sync_pending(dev);
- } else
- bfin_rtc_int_clear(0);
-
- return 0;
-}
-
-static int bfin_rtc_resume(struct device *dev)
-{
- dev_dbg_stamp(dev);
-
- if (device_may_wakeup(dev))
- disable_irq_wake(IRQ_RTC);
-
- /*
- * Since only some of the RTC bits are maintained externally in the
- * Vbat domain, we need to wait for the RTC MMRs to be synced into
- * the core after waking up. This happens every RTC 1HZ. Once that
- * has happened, we can go ahead and re-enable the important write
- * complete interrupt event.
- */
- while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_SEC))
- continue;
- bfin_rtc_int_set(RTC_ISTAT_WRITE_COMPLETE);
-
- return 0;
-}
-#endif
-
-static SIMPLE_DEV_PM_OPS(bfin_rtc_pm_ops, bfin_rtc_suspend, bfin_rtc_resume);
-
-static struct platform_driver bfin_rtc_driver = {
- .driver = {
- .name = "rtc-bfin",
- .pm = &bfin_rtc_pm_ops,
- },
- .probe = bfin_rtc_probe,
- .remove = bfin_rtc_remove,
-};
-
-module_platform_driver(bfin_rtc_driver);
-
-MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
-MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:rtc-bfin");
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 06/28] mmc: Remove Blackfin SD host support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (3 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 05/28] rtc: Remove Blackfin RTC support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 07/28] watchdog: Remove Blackfin watchdog support Aaron Wu
` (21 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin SD host support
---
drivers/mmc/host/Kconfig | 19 --
drivers/mmc/host/Makefile | 1 -
drivers/mmc/host/bfin_sdh.c | 679 --------------------------------------------
3 files changed, 699 deletions(-)
delete mode 100644 drivers/mmc/host/bfin_sdh.c
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 620c2d9..b4fd5d4 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -646,25 +646,6 @@ config MMC_VIA_SDMMC
If unsure, say N.
-config SDH_BFIN
- tristate "Blackfin Secure Digital Host support"
- depends on (BF54x && !BF544) || (BF51x && !BF512)
- help
- If you say yes here you will get support for the Blackfin on-chip
- Secure Digital Host interface. This includes support for MMC and
- SD cards.
-
- To compile this driver as a module, choose M here: the
- module will be called bfin_sdh.
-
- If unsure, say N.
-
-config SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
- bool "Blackfin EZkit Missing SDH_CMD Pull Up Resistor Workaround"
- depends on SDH_BFIN
- help
- If you say yes here SD-Cards may work on the EZkit.
-
config MMC_CAVIUM_OCTEON
tristate "Cavium OCTEON SD/MMC Card Interface support"
depends on CAVIUM_OCTEON_SOC
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 84cd138..f563cc0 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -43,7 +43,6 @@ obj-$(CONFIG_MMC_SDHI_SYS_DMAC) += renesas_sdhi_sys_dmac.o
obj-$(CONFIG_MMC_SDHI_INTERNAL_DMAC) += renesas_sdhi_internal_dmac.o
obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
-obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o
octeon-mmc-objs := cavium.o cavium-octeon.o
obj-$(CONFIG_MMC_CAVIUM_OCTEON) += octeon-mmc.o
thunderx-mmc-objs := cavium.o cavium-thunderx.o
diff --git a/drivers/mmc/host/bfin_sdh.c b/drivers/mmc/host/bfin_sdh.c
deleted file mode 100644
index 526231e..0000000
--- a/drivers/mmc/host/bfin_sdh.c
+++ /dev/null
@@ -1,679 +0,0 @@
-/*
- * bfin_sdh.c - Analog Devices Blackfin SDH Controller
- *
- * Copyright (C) 2007-2009 Analog Device Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define DRIVER_NAME "bfin-sdh"
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
-#include <linux/mmc/host.h>
-#include <linux/proc_fs.h>
-#include <linux/gfp.h>
-
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-
-#if defined(CONFIG_BF51x) || defined(__ADSPBF60x__)
-#define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CTL
-#define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CTL
-#define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
-#define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
-#define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
-#define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
-#define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
-#define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
-#define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
-#define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
-#define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CTL
-#define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CTL
-#define bfin_read_SDH_DATA_CNT bfin_read_RSI_DATA_CNT
-#define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUS_CLR
-#define bfin_read_SDH_E_STATUS bfin_read_RSI_E_STATUS
-#define bfin_write_SDH_E_STATUS bfin_write_RSI_E_STATUS
-#define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
-#define bfin_write_SDH_MASK0 bfin_write_RSI_MASK0
-#define bfin_write_SDH_E_MASK bfin_write_RSI_E_MASK
-#define bfin_read_SDH_CFG bfin_read_RSI_CFG
-#define bfin_write_SDH_CFG bfin_write_RSI_CFG
-# if defined(__ADSPBF60x__)
-# define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ
-# define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ
-# else
-# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CTL
-# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CTL
-# endif
-#endif
-
-struct sdh_host {
- struct mmc_host *mmc;
- spinlock_t lock;
- struct resource *res;
- void __iomem *base;
- int irq;
- int stat_irq;
- int dma_ch;
- int dma_dir;
- struct dma_desc_array *sg_cpu;
- dma_addr_t sg_dma;
- int dma_len;
-
- unsigned long sclk;
- unsigned int imask;
- unsigned int power_mode;
- unsigned int clk_div;
-
- struct mmc_request *mrq;
- struct mmc_command *cmd;
- struct mmc_data *data;
-};
-
-static struct bfin_sd_host *get_sdh_data(struct platform_device *pdev)
-{
- return pdev->dev.platform_data;
-}
-
-static void sdh_stop_clock(struct sdh_host *host)
-{
- bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
- SSYNC();
-}
-
-static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&host->lock, flags);
- host->imask |= mask;
- bfin_write_SDH_MASK0(mask);
- SSYNC();
- spin_unlock_irqrestore(&host->lock, flags);
-}
-
-static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&host->lock, flags);
- host->imask &= ~mask;
- bfin_write_SDH_MASK0(host->imask);
- SSYNC();
- spin_unlock_irqrestore(&host->lock, flags);
-}
-
-static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
-{
- unsigned int length;
- unsigned int data_ctl;
- unsigned int dma_cfg;
- unsigned int cycle_ns, timeout;
-
- dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
- host->data = data;
- data_ctl = 0;
- dma_cfg = 0;
-
- length = data->blksz * data->blocks;
- bfin_write_SDH_DATA_LGTH(length);
-
- if (data->flags & MMC_DATA_READ)
- data_ctl |= DTX_DIR;
- /* Only supports power-of-2 block size */
- if (data->blksz & (data->blksz - 1))
- return -EINVAL;
-#ifndef RSI_BLKSZ
- data_ctl |= ((ffs(data->blksz) - 1) << 4);
-#else
- bfin_write_SDH_BLK_SIZE(data->blksz);
-#endif
-
- bfin_write_SDH_DATA_CTL(data_ctl);
- /* the time of a host clock period in ns */
- cycle_ns = 1000000000 / (host->sclk / (2 * (host->clk_div + 1)));
- timeout = data->timeout_ns / cycle_ns;
- timeout += data->timeout_clks;
- bfin_write_SDH_DATA_TIMER(timeout);
- SSYNC();
-
- if (data->flags & MMC_DATA_READ) {
- host->dma_dir = DMA_FROM_DEVICE;
- dma_cfg |= WNR;
- } else
- host->dma_dir = DMA_TO_DEVICE;
-
- sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
- host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
- dma_cfg |= DMAFLOW_ARRAY | RESTART | WDSIZE_32 | DMAEN;
-# ifdef RSI_BLKSZ
- dma_cfg |= PSIZE_32 | NDSIZE_3;
-# else
- dma_cfg |= NDSIZE_5;
-# endif
- {
- struct scatterlist *sg;
- int i;
- for_each_sg(data->sg, sg, host->dma_len, i) {
- host->sg_cpu[i].start_addr = sg_dma_address(sg);
- host->sg_cpu[i].cfg = dma_cfg;
- host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
- host->sg_cpu[i].x_modify = 4;
- dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
- "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
- i, host->sg_cpu[i].start_addr,
- host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
- host->sg_cpu[i].x_modify);
- }
- }
- flush_dcache_range((unsigned int)host->sg_cpu,
- (unsigned int)host->sg_cpu +
- host->dma_len * sizeof(struct dma_desc_array));
- /* Set the last descriptor to stop mode */
- host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW | NDSIZE);
- host->sg_cpu[host->dma_len - 1].cfg |= DI_EN;
-
- set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
- set_dma_x_count(host->dma_ch, 0);
- set_dma_x_modify(host->dma_ch, 0);
- SSYNC();
- set_dma_config(host->dma_ch, dma_cfg);
-#elif defined(CONFIG_BF51x)
- /* RSI DMA doesn't work in array mode */
- dma_cfg |= WDSIZE_32 | DMAEN;
- set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
- set_dma_x_count(host->dma_ch, length / 4);
- set_dma_x_modify(host->dma_ch, 4);
- SSYNC();
- set_dma_config(host->dma_ch, dma_cfg);
-#endif
- bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
-
- SSYNC();
-
- dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
- return 0;
-}
-
-static void sdh_start_cmd(struct sdh_host *host, struct mmc_command *cmd)
-{
- unsigned int sdh_cmd;
- unsigned int stat_mask;
-
- dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
- WARN_ON(host->cmd != NULL);
- host->cmd = cmd;
-
- sdh_cmd = 0;
- stat_mask = 0;
-
- sdh_cmd |= cmd->opcode;
-
- if (cmd->flags & MMC_RSP_PRESENT) {
- sdh_cmd |= CMD_RSP;
- stat_mask |= CMD_RESP_END;
- } else {
- stat_mask |= CMD_SENT;
- }
-
- if (cmd->flags & MMC_RSP_136)
- sdh_cmd |= CMD_L_RSP;
-
- stat_mask |= CMD_CRC_FAIL | CMD_TIME_OUT;
-
- sdh_enable_stat_irq(host, stat_mask);
-
- bfin_write_SDH_ARGUMENT(cmd->arg);
- bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
- bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E);
- SSYNC();
-}
-
-static void sdh_finish_request(struct sdh_host *host, struct mmc_request *mrq)
-{
- dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
- host->mrq = NULL;
- host->cmd = NULL;
- host->data = NULL;
- mmc_request_done(host->mmc, mrq);
-}
-
-static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
-{
- struct mmc_command *cmd = host->cmd;
- int ret = 0;
-
- dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
- if (!cmd)
- return 0;
-
- host->cmd = NULL;
-
- if (cmd->flags & MMC_RSP_PRESENT) {
- cmd->resp[0] = bfin_read_SDH_RESPONSE0();
- if (cmd->flags & MMC_RSP_136) {
- cmd->resp[1] = bfin_read_SDH_RESPONSE1();
- cmd->resp[2] = bfin_read_SDH_RESPONSE2();
- cmd->resp[3] = bfin_read_SDH_RESPONSE3();
- }
- }
- if (stat & CMD_TIME_OUT)
- cmd->error = -ETIMEDOUT;
- else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
- cmd->error = -EILSEQ;
-
- sdh_disable_stat_irq(host, (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL));
-
- if (host->data && !cmd->error) {
- if (host->data->flags & MMC_DATA_WRITE) {
- ret = sdh_setup_data(host, host->data);
- if (ret)
- return 0;
- }
-
- sdh_enable_stat_irq(host, DAT_END | RX_OVERRUN | TX_UNDERRUN | DAT_TIME_OUT);
- } else
- sdh_finish_request(host, host->mrq);
-
- return 1;
-}
-
-static int sdh_data_done(struct sdh_host *host, unsigned int stat)
-{
- struct mmc_data *data = host->data;
-
- dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
- if (!data)
- return 0;
-
- disable_dma(host->dma_ch);
- dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
- host->dma_dir);
-
- if (stat & DAT_TIME_OUT)
- data->error = -ETIMEDOUT;
- else if (stat & DAT_CRC_FAIL)
- data->error = -EILSEQ;
- else if (stat & (RX_OVERRUN | TX_UNDERRUN))
- data->error = -EIO;
-
- if (!data->error)
- data->bytes_xfered = data->blocks * data->blksz;
- else
- data->bytes_xfered = 0;
-
- bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
- DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
- bfin_write_SDH_DATA_CTL(0);
- SSYNC();
-
- host->data = NULL;
- if (host->mrq->stop) {
- sdh_stop_clock(host);
- sdh_start_cmd(host, host->mrq->stop);
- } else {
- sdh_finish_request(host, host->mrq);
- }
-
- return 1;
-}
-
-static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
-{
- struct sdh_host *host = mmc_priv(mmc);
- int ret = 0;
-
- dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
- WARN_ON(host->mrq != NULL);
-
- spin_lock(&host->lock);
- host->mrq = mrq;
- host->data = mrq->data;
-
- if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
- ret = sdh_setup_data(host, mrq->data);
- if (ret)
- goto data_err;
- }
-
- sdh_start_cmd(host, mrq->cmd);
-data_err:
- spin_unlock(&host->lock);
-}
-
-static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-{
- struct sdh_host *host;
- u16 clk_ctl = 0;
-#ifndef RSI_BLKSZ
- u16 pwr_ctl = 0;
-#endif
- u16 cfg;
- host = mmc_priv(mmc);
-
- spin_lock(&host->lock);
-
- cfg = bfin_read_SDH_CFG();
- cfg |= MWE;
- switch (ios->bus_width) {
- case MMC_BUS_WIDTH_4:
-#ifndef RSI_BLKSZ
- cfg &= ~PD_SDDAT3;
-#endif
- cfg |= PUP_SDDAT3;
- /* Enable 4 bit SDIO */
- cfg |= SD4E;
- clk_ctl |= WIDE_BUS_4;
- break;
- case MMC_BUS_WIDTH_8:
-#ifndef RSI_BLKSZ
- cfg &= ~PD_SDDAT3;
-#endif
- cfg |= PUP_SDDAT3;
- /* Disable 4 bit SDIO */
- cfg &= ~SD4E;
- clk_ctl |= BYTE_BUS_8;
- break;
- default:
- cfg &= ~PUP_SDDAT3;
- /* Disable 4 bit SDIO */
- cfg &= ~SD4E;
- }
- bfin_write_SDH_CFG(cfg);
-
- host->power_mode = ios->power_mode;
-#ifndef RSI_BLKSZ
- if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
- pwr_ctl |= ROD_CTL;
-# ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
- pwr_ctl |= SD_CMD_OD;
-# endif
- }
-
- if (ios->power_mode != MMC_POWER_OFF)
- pwr_ctl |= PWR_ON;
- else
- pwr_ctl &= ~PWR_ON;
-
- bfin_write_SDH_PWR_CTL(pwr_ctl);
-#else
-# ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
- if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
- cfg |= SD_CMD_OD;
- else
- cfg &= ~SD_CMD_OD;
-# endif
-
- if (ios->power_mode != MMC_POWER_OFF)
- cfg |= PWR_ON;
- else
- cfg &= ~PWR_ON;
-
- bfin_write_SDH_CFG(cfg);
-#endif
- SSYNC();
-
- if (ios->power_mode == MMC_POWER_ON && ios->clock) {
- unsigned char clk_div;
- clk_div = (get_sclk() / ios->clock - 1) / 2;
- clk_div = min_t(unsigned char, clk_div, 0xFF);
- clk_ctl |= clk_div;
- clk_ctl |= CLK_E;
- host->clk_div = clk_div;
- bfin_write_SDH_CLK_CTL(clk_ctl);
- } else
- sdh_stop_clock(host);
-
- /* set up sdh interrupt mask*/
- if (ios->power_mode == MMC_POWER_ON)
- bfin_write_SDH_MASK0(DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
- RX_OVERRUN | TX_UNDERRUN | CMD_SENT | CMD_RESP_END |
- CMD_TIME_OUT | CMD_CRC_FAIL);
- else
- bfin_write_SDH_MASK0(0);
- SSYNC();
-
- spin_unlock(&host->lock);
-
- dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
- host->clk_div,
- host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
- ios->clock);
-}
-
-static const struct mmc_host_ops sdh_ops = {
- .request = sdh_request,
- .set_ios = sdh_set_ios,
-};
-
-static irqreturn_t sdh_dma_irq(int irq, void *devid)
-{
- struct sdh_host *host = devid;
-
- dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04lx\n", __func__,
- get_dma_curr_irqstat(host->dma_ch));
- clear_dma_irqstat(host->dma_ch);
- SSYNC();
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t sdh_stat_irq(int irq, void *devid)
-{
- struct sdh_host *host = devid;
- unsigned int status;
- int handled = 0;
-
- dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
-
- spin_lock(&host->lock);
-
- status = bfin_read_SDH_E_STATUS();
- if (status & SD_CARD_DET) {
- mmc_detect_change(host->mmc, 0);
- bfin_write_SDH_E_STATUS(SD_CARD_DET);
- }
- status = bfin_read_SDH_STATUS();
- if (status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL)) {
- handled |= sdh_cmd_done(host, status);
- bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | \
- CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
- SSYNC();
- }
-
- status = bfin_read_SDH_STATUS();
- if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
- handled |= sdh_data_done(host, status);
-
- spin_unlock(&host->lock);
-
- dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
-
- return IRQ_RETVAL(handled);
-}
-
-static void sdh_reset(void)
-{
-#if defined(CONFIG_BF54x)
- /* Secure Digital Host shares DMA with Nand controller */
- bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
-#endif
-
- bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
- SSYNC();
-
- /* Disable card inserting detection pin. set MMC_CAP_NEEDS_POLL, and
- * mmc stack will do the detection.
- */
- bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
- SSYNC();
-}
-
-static int sdh_probe(struct platform_device *pdev)
-{
- struct mmc_host *mmc;
- struct sdh_host *host;
- struct bfin_sd_host *drv_data = get_sdh_data(pdev);
- int ret;
-
- if (!drv_data) {
- dev_err(&pdev->dev, "missing platform driver data\n");
- ret = -EINVAL;
- goto out;
- }
-
- mmc = mmc_alloc_host(sizeof(struct sdh_host), &pdev->dev);
- if (!mmc) {
- ret = -ENOMEM;
- goto out;
- }
-
- mmc->ops = &sdh_ops;
-#if defined(CONFIG_BF51x)
- mmc->max_segs = 1;
-#else
- mmc->max_segs = PAGE_SIZE / sizeof(struct dma_desc_array);
-#endif
-#ifdef RSI_BLKSZ
- mmc->max_seg_size = -1;
-#else
- mmc->max_seg_size = 1 << 16;
-#endif
- mmc->max_blk_size = 1 << 11;
- mmc->max_blk_count = 1 << 11;
- mmc->max_req_size = PAGE_SIZE;
- mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
- mmc->f_max = get_sclk();
- mmc->f_min = mmc->f_max >> 9;
- mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
- host = mmc_priv(mmc);
- host->mmc = mmc;
- host->sclk = get_sclk();
-
- spin_lock_init(&host->lock);
- host->irq = drv_data->irq_int0;
- host->dma_ch = drv_data->dma_chan;
-
- ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
- if (ret) {
- dev_err(&pdev->dev, "unable to request DMA channel\n");
- goto out1;
- }
-
- ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
- if (ret) {
- dev_err(&pdev->dev, "unable to request DMA irq\n");
- goto out2;
- }
-
- host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
- if (host->sg_cpu == NULL) {
- ret = -ENOMEM;
- goto out2;
- }
-
- platform_set_drvdata(pdev, mmc);
-
- ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
- if (ret) {
- dev_err(&pdev->dev, "unable to request status irq\n");
- goto out3;
- }
-
- ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
- if (ret) {
- dev_err(&pdev->dev, "unable to request peripheral pins\n");
- goto out4;
- }
-
- sdh_reset();
-
- mmc_add_host(mmc);
- return 0;
-
-out4:
- free_irq(host->irq, host);
-out3:
- mmc_remove_host(mmc);
- dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
-out2:
- free_dma(host->dma_ch);
-out1:
- mmc_free_host(mmc);
- out:
- return ret;
-}
-
-static int sdh_remove(struct platform_device *pdev)
-{
- struct mmc_host *mmc = platform_get_drvdata(pdev);
-
- if (mmc) {
- struct sdh_host *host = mmc_priv(mmc);
-
- mmc_remove_host(mmc);
-
- sdh_stop_clock(host);
- free_irq(host->irq, host);
- free_dma(host->dma_ch);
- dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
-
- mmc_free_host(mmc);
- }
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int sdh_suspend(struct platform_device *dev, pm_message_t state)
-{
- struct bfin_sd_host *drv_data = get_sdh_data(dev);
-
- peripheral_free_list(drv_data->pin_req);
-
- return 0;
-}
-
-static int sdh_resume(struct platform_device *dev)
-{
- struct bfin_sd_host *drv_data = get_sdh_data(dev);
- int ret = 0;
-
- ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
- if (ret) {
- dev_err(&dev->dev, "unable to request peripheral pins\n");
- return ret;
- }
-
- sdh_reset();
- return ret;
-}
-#else
-# define sdh_suspend NULL
-# define sdh_resume NULL
-#endif
-
-static struct platform_driver sdh_driver = {
- .probe = sdh_probe,
- .remove = sdh_remove,
- .suspend = sdh_suspend,
- .resume = sdh_resume,
- .driver = {
- .name = DRIVER_NAME,
- },
-};
-
-module_platform_driver(sdh_driver);
-
-MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
-MODULE_AUTHOR("Cliff Cai, Roy Huang");
-MODULE_LICENSE("GPL");
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 07/28] watchdog: Remove Blackfin watchdog support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (4 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 06/28] mmc: Remove Blackfin SD host support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 14:43 ` Guenter Roeck
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 08/28] Asoc: Remove Blackfin ASOC support Aaron Wu
` (20 subsequent siblings)
26 siblings, 1 reply; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin watchdog support
---
drivers/watchdog/Kconfig | 13 --
drivers/watchdog/Makefile | 3 -
drivers/watchdog/bfin_wdt.c | 476 --------------------------------------------
3 files changed, 492 deletions(-)
delete mode 100644 drivers/watchdog/bfin_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 37460cd..6174e99 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -815,19 +815,6 @@ config SPRD_WATCHDOG
Say Y here to include watchdog timer supported
by Spreadtrum system.
-# BLACKFIN Architecture
-
-config BFIN_WDT
- tristate "Blackfin On-Chip Watchdog Timer"
- depends on BLACKFIN
- ---help---
- If you say yes here you will get support for the Blackfin On-Chip
- Watchdog Timer. If you have one of these processors and wish to
- have watchdog support enabled, say Y, otherwise say N.
-
- To compile this driver as a module, choose M here: the
- module will be called bfin_wdt.
-
# CRIS Architecture
# FRV Architecture
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 0474d38..1971f86 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -91,9 +91,6 @@ obj-$(CONFIG_UNIPHIER_WATCHDOG) += uniphier_wdt.o
obj-$(CONFIG_RTD119X_WATCHDOG) += rtd119x_wdt.o
obj-$(CONFIG_SPRD_WATCHDOG) += sprd_wdt.o
-# BLACKFIN Architecture
-obj-$(CONFIG_BFIN_WDT) += bfin_wdt.o
-
# CRIS Architecture
# FRV Architecture
diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c
deleted file mode 100644
index aa4d2e8..0000000
--- a/drivers/watchdog/bfin_wdt.c
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * Blackfin On-Chip Watchdog Driver
- *
- * Originally based on softdog.c
- * Copyright 2006-2010 Analog Devices Inc.
- * Copyright 2006-2007 Michele d'Amico
- * Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <linux/miscdevice.h>
-#include <linux/watchdog.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/uaccess.h>
-#include <asm/blackfin.h>
-#include <asm/bfin_watchdog.h>
-
-#define stamp(fmt, args...) \
- pr_debug("%s:%i: " fmt "\n", __func__, __LINE__, ## args)
-#define stampit() stamp("here i am")
-
-#define WATCHDOG_NAME "bfin-wdt"
-
-/* The BF561 has two watchdogs (one per core), but since Linux
- * only runs on core A, we'll just work with that one.
- */
-#ifdef BF561_FAMILY
-# define bfin_read_WDOG_CTL() bfin_read_WDOGA_CTL()
-# define bfin_read_WDOG_CNT() bfin_read_WDOGA_CNT()
-# define bfin_read_WDOG_STAT() bfin_read_WDOGA_STAT()
-# define bfin_write_WDOG_CTL(x) bfin_write_WDOGA_CTL(x)
-# define bfin_write_WDOG_CNT(x) bfin_write_WDOGA_CNT(x)
-# define bfin_write_WDOG_STAT(x) bfin_write_WDOGA_STAT(x)
-#endif
-
-/* some defaults */
-#define WATCHDOG_TIMEOUT 20
-
-static unsigned int timeout = WATCHDOG_TIMEOUT;
-static bool nowayout = WATCHDOG_NOWAYOUT;
-static const struct watchdog_info bfin_wdt_info;
-static unsigned long open_check;
-static char expect_close;
-static DEFINE_SPINLOCK(bfin_wdt_spinlock);
-
-/**
- * bfin_wdt_keepalive - Keep the Userspace Watchdog Alive
- *
- * The Userspace watchdog got a KeepAlive: schedule the next timeout.
- */
-static int bfin_wdt_keepalive(void)
-{
- stampit();
- bfin_write_WDOG_STAT(0);
- return 0;
-}
-
-/**
- * bfin_wdt_stop - Stop the Watchdog
- *
- * Stops the on-chip watchdog.
- */
-static int bfin_wdt_stop(void)
-{
- stampit();
- bfin_write_WDOG_CTL(WDEN_DISABLE);
- return 0;
-}
-
-/**
- * bfin_wdt_start - Start the Watchdog
- *
- * Starts the on-chip watchdog. Automatically loads WDOG_CNT
- * into WDOG_STAT for us.
- */
-static int bfin_wdt_start(void)
-{
- stampit();
- bfin_write_WDOG_CTL(WDEN_ENABLE | ICTL_RESET);
- return 0;
-}
-
-/**
- * bfin_wdt_running - Check Watchdog status
- *
- * See if the watchdog is running.
- */
-static int bfin_wdt_running(void)
-{
- stampit();
- return ((bfin_read_WDOG_CTL() & WDEN_MASK) != WDEN_DISABLE);
-}
-
-/**
- * bfin_wdt_set_timeout - Set the Userspace Watchdog timeout
- * @t: new timeout value (in seconds)
- *
- * Translate the specified timeout in seconds into System Clock
- * terms which is what the on-chip Watchdog requires.
- */
-static int bfin_wdt_set_timeout(unsigned long t)
-{
- u32 cnt, max_t, sclk;
- unsigned long flags;
-
- sclk = get_sclk();
- max_t = -1 / sclk;
- cnt = t * sclk;
- stamp("maxtimeout=%us newtimeout=%lus (cnt=%#x)", max_t, t, cnt);
-
- if (t > max_t) {
- pr_warn("timeout value is too large\n");
- return -EINVAL;
- }
-
- spin_lock_irqsave(&bfin_wdt_spinlock, flags);
- {
- int run = bfin_wdt_running();
- bfin_wdt_stop();
- bfin_write_WDOG_CNT(cnt);
- if (run)
- bfin_wdt_start();
- }
- spin_unlock_irqrestore(&bfin_wdt_spinlock, flags);
-
- timeout = t;
-
- return 0;
-}
-
-/**
- * bfin_wdt_open - Open the Device
- * @inode: inode of device
- * @file: file handle of device
- *
- * Watchdog device is opened and started.
- */
-static int bfin_wdt_open(struct inode *inode, struct file *file)
-{
- stampit();
-
- if (test_and_set_bit(0, &open_check))
- return -EBUSY;
-
- if (nowayout)
- __module_get(THIS_MODULE);
-
- bfin_wdt_keepalive();
- bfin_wdt_start();
-
- return nonseekable_open(inode, file);
-}
-
-/**
- * bfin_wdt_close - Close the Device
- * @inode: inode of device
- * @file: file handle of device
- *
- * Watchdog device is closed and stopped.
- */
-static int bfin_wdt_release(struct inode *inode, struct file *file)
-{
- stampit();
-
- if (expect_close == 42)
- bfin_wdt_stop();
- else {
- pr_crit("Unexpected close, not stopping watchdog!\n");
- bfin_wdt_keepalive();
- }
- expect_close = 0;
- clear_bit(0, &open_check);
- return 0;
-}
-
-/**
- * bfin_wdt_write - Write to Device
- * @file: file handle of device
- * @buf: buffer to write
- * @count: length of buffer
- * @ppos: offset
- *
- * Pings the watchdog on write.
- */
-static ssize_t bfin_wdt_write(struct file *file, const char __user *data,
- size_t len, loff_t *ppos)
-{
- stampit();
-
- if (len) {
- if (!nowayout) {
- size_t i;
-
- /* In case it was set long ago */
- expect_close = 0;
-
- for (i = 0; i != len; i++) {
- char c;
- if (get_user(c, data + i))
- return -EFAULT;
- if (c == 'V')
- expect_close = 42;
- }
- }
- bfin_wdt_keepalive();
- }
-
- return len;
-}
-
-/**
- * bfin_wdt_ioctl - Query Device
- * @file: file handle of device
- * @cmd: watchdog command
- * @arg: argument
- *
- * Query basic information from the device or ping it, as outlined by the
- * watchdog API.
- */
-static long bfin_wdt_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- void __user *argp = (void __user *)arg;
- int __user *p = argp;
-
- stampit();
-
- switch (cmd) {
- case WDIOC_GETSUPPORT:
- if (copy_to_user(argp, &bfin_wdt_info, sizeof(bfin_wdt_info)))
- return -EFAULT;
- else
- return 0;
- case WDIOC_GETSTATUS:
- case WDIOC_GETBOOTSTATUS:
- return put_user(!!(_bfin_swrst & SWRST_RESET_WDOG), p);
- case WDIOC_SETOPTIONS: {
- unsigned long flags;
- int options, ret = -EINVAL;
-
- if (get_user(options, p))
- return -EFAULT;
-
- spin_lock_irqsave(&bfin_wdt_spinlock, flags);
- if (options & WDIOS_DISABLECARD) {
- bfin_wdt_stop();
- ret = 0;
- }
- if (options & WDIOS_ENABLECARD) {
- bfin_wdt_start();
- ret = 0;
- }
- spin_unlock_irqrestore(&bfin_wdt_spinlock, flags);
- return ret;
- }
- case WDIOC_KEEPALIVE:
- bfin_wdt_keepalive();
- return 0;
- case WDIOC_SETTIMEOUT: {
- int new_timeout;
-
- if (get_user(new_timeout, p))
- return -EFAULT;
- if (bfin_wdt_set_timeout(new_timeout))
- return -EINVAL;
- }
- /* Fall */
- case WDIOC_GETTIMEOUT:
- return put_user(timeout, p);
- default:
- return -ENOTTY;
- }
-}
-
-#ifdef CONFIG_PM
-static int state_before_suspend;
-
-/**
- * bfin_wdt_suspend - suspend the watchdog
- * @pdev: device being suspended
- * @state: requested suspend state
- *
- * Remember if the watchdog was running and stop it.
- * TODO: is this even right? Doesn't seem to be any
- * standard in the watchdog world ...
- */
-static int bfin_wdt_suspend(struct platform_device *pdev, pm_message_t state)
-{
- stampit();
-
- state_before_suspend = bfin_wdt_running();
- bfin_wdt_stop();
-
- return 0;
-}
-
-/**
- * bfin_wdt_resume - resume the watchdog
- * @pdev: device being resumed
- *
- * If the watchdog was running, turn it back on.
- */
-static int bfin_wdt_resume(struct platform_device *pdev)
-{
- stampit();
-
- if (state_before_suspend) {
- bfin_wdt_set_timeout(timeout);
- bfin_wdt_start();
- }
-
- return 0;
-}
-#else
-# define bfin_wdt_suspend NULL
-# define bfin_wdt_resume NULL
-#endif
-
-static const struct file_operations bfin_wdt_fops = {
- .owner = THIS_MODULE,
- .llseek = no_llseek,
- .write = bfin_wdt_write,
- .unlocked_ioctl = bfin_wdt_ioctl,
- .open = bfin_wdt_open,
- .release = bfin_wdt_release,
-};
-
-static struct miscdevice bfin_wdt_miscdev = {
- .minor = WATCHDOG_MINOR,
- .name = "watchdog",
- .fops = &bfin_wdt_fops,
-};
-
-static const struct watchdog_info bfin_wdt_info = {
- .identity = "Blackfin Watchdog",
- .options = WDIOF_SETTIMEOUT |
- WDIOF_KEEPALIVEPING |
- WDIOF_MAGICCLOSE,
-};
-
-/**
- * bfin_wdt_probe - Initialize module
- *
- * Registers the misc device. Actual device
- * initialization is handled by bfin_wdt_open().
- */
-static int bfin_wdt_probe(struct platform_device *pdev)
-{
- int ret;
-
- ret = misc_register(&bfin_wdt_miscdev);
- if (ret) {
- pr_err("cannot register miscdev on minor=%d (err=%d)\n",
- WATCHDOG_MINOR, ret);
- return ret;
- }
-
- pr_info("initialized: timeout=%d sec (nowayout=%d)\n",
- timeout, nowayout);
-
- return 0;
-}
-
-/**
- * bfin_wdt_remove - Initialize module
- *
- * Unregisters the misc device. Actual device
- * deinitialization is handled by bfin_wdt_close().
- */
-static int bfin_wdt_remove(struct platform_device *pdev)
-{
- misc_deregister(&bfin_wdt_miscdev);
- return 0;
-}
-
-/**
- * bfin_wdt_shutdown - Soft Shutdown Handler
- *
- * Handles the soft shutdown event.
- */
-static void bfin_wdt_shutdown(struct platform_device *pdev)
-{
- stampit();
-
- bfin_wdt_stop();
-}
-
-static struct platform_device *bfin_wdt_device;
-
-static struct platform_driver bfin_wdt_driver = {
- .probe = bfin_wdt_probe,
- .remove = bfin_wdt_remove,
- .shutdown = bfin_wdt_shutdown,
- .suspend = bfin_wdt_suspend,
- .resume = bfin_wdt_resume,
- .driver = {
- .name = WATCHDOG_NAME,
- },
-};
-
-/**
- * bfin_wdt_init - Initialize module
- *
- * Checks the module params and registers the platform device & driver.
- * Real work is in the platform probe function.
- */
-static int __init bfin_wdt_init(void)
-{
- int ret;
-
- stampit();
-
- /* Check that the timeout value is within range */
- if (bfin_wdt_set_timeout(timeout))
- return -EINVAL;
-
- /* Since this is an on-chip device and needs no board-specific
- * resources, we'll handle all the platform device stuff here.
- */
- ret = platform_driver_register(&bfin_wdt_driver);
- if (ret) {
- pr_err("unable to register driver\n");
- return ret;
- }
-
- bfin_wdt_device = platform_device_register_simple(WATCHDOG_NAME,
- -1, NULL, 0);
- if (IS_ERR(bfin_wdt_device)) {
- pr_err("unable to register device\n");
- platform_driver_unregister(&bfin_wdt_driver);
- return PTR_ERR(bfin_wdt_device);
- }
-
- return 0;
-}
-
-/**
- * bfin_wdt_exit - Deinitialize module
- *
- * Back out the platform device & driver steps. Real work is in the
- * platform remove function.
- */
-static void __exit bfin_wdt_exit(void)
-{
- platform_device_unregister(bfin_wdt_device);
- platform_driver_unregister(&bfin_wdt_driver);
-}
-
-module_init(bfin_wdt_init);
-module_exit(bfin_wdt_exit);
-
-MODULE_AUTHOR("Michele d'Amico, Mike Frysinger <vapier@gentoo.org>");
-MODULE_DESCRIPTION("Blackfin Watchdog Device Driver");
-MODULE_LICENSE("GPL");
-
-module_param(timeout, uint, 0);
-MODULE_PARM_DESC(timeout,
- "Watchdog timeout in seconds. (1<=timeout<=((2^32)/SCLK), default="
- __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
-
-module_param(nowayout, bool, 0);
-MODULE_PARM_DESC(nowayout,
- "Watchdog cannot be stopped once started (default="
- __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 08/28] Asoc: Remove Blackfin ASOC support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (5 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 07/28] watchdog: Remove Blackfin watchdog support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 09/28] input: Remove Blackfin input support Aaron Wu
` (19 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin ASOC support
---
sound/soc/Kconfig | 1 -
sound/soc/Makefile | 1 -
sound/soc/blackfin/Kconfig | 205 ------
sound/soc/blackfin/Makefile | 40 --
sound/soc/blackfin/bf5xx-ac97-pcm.c | 480 --------------
sound/soc/blackfin/bf5xx-ac97.c | 388 -----------
sound/soc/blackfin/bf5xx-ac97.h | 57 --
sound/soc/blackfin/bf5xx-ad1836.c | 109 ---
sound/soc/blackfin/bf5xx-ad193x.c | 131 ----
sound/soc/blackfin/bf5xx-ad1980.c | 109 ---
sound/soc/blackfin/bf5xx-ad73311.c | 212 ------
sound/soc/blackfin/bf5xx-i2s-pcm.c | 373 -----------
sound/soc/blackfin/bf5xx-i2s-pcm.h | 17 -
sound/soc/blackfin/bf5xx-i2s.c | 391 -----------
sound/soc/blackfin/bf5xx-sport.c | 1102 -------------------------------
sound/soc/blackfin/bf5xx-sport.h | 174 -----
sound/soc/blackfin/bf5xx-ssm2602.c | 126 ----
sound/soc/blackfin/bf6xx-i2s.c | 239 -------
sound/soc/blackfin/bf6xx-sport.c | 425 ------------
sound/soc/blackfin/bf6xx-sport.h | 82 ---
sound/soc/blackfin/bfin-eval-adau1373.c | 173 -----
sound/soc/blackfin/bfin-eval-adau1701.c | 113 ----
sound/soc/blackfin/bfin-eval-adau1x61.c | 142 ----
sound/soc/blackfin/bfin-eval-adau1x81.c | 129 ----
sound/soc/blackfin/bfin-eval-adav80x.c | 145 ----
25 files changed, 5364 deletions(-)
delete mode 100644 sound/soc/blackfin/Kconfig
delete mode 100644 sound/soc/blackfin/Makefile
delete mode 100644 sound/soc/blackfin/bf5xx-ac97-pcm.c
delete mode 100644 sound/soc/blackfin/bf5xx-ac97.c
delete mode 100644 sound/soc/blackfin/bf5xx-ac97.h
delete mode 100644 sound/soc/blackfin/bf5xx-ad1836.c
delete mode 100644 sound/soc/blackfin/bf5xx-ad193x.c
delete mode 100644 sound/soc/blackfin/bf5xx-ad1980.c
delete mode 100644 sound/soc/blackfin/bf5xx-ad73311.c
delete mode 100644 sound/soc/blackfin/bf5xx-i2s-pcm.c
delete mode 100644 sound/soc/blackfin/bf5xx-i2s-pcm.h
delete mode 100644 sound/soc/blackfin/bf5xx-i2s.c
delete mode 100644 sound/soc/blackfin/bf5xx-sport.c
delete mode 100644 sound/soc/blackfin/bf5xx-sport.h
delete mode 100644 sound/soc/blackfin/bf5xx-ssm2602.c
delete mode 100644 sound/soc/blackfin/bf6xx-i2s.c
delete mode 100644 sound/soc/blackfin/bf6xx-sport.c
delete mode 100644 sound/soc/blackfin/bf6xx-sport.h
delete mode 100644 sound/soc/blackfin/bfin-eval-adau1373.c
delete mode 100644 sound/soc/blackfin/bfin-eval-adau1701.c
delete mode 100644 sound/soc/blackfin/bfin-eval-adau1x61.c
delete mode 100644 sound/soc/blackfin/bfin-eval-adau1x81.c
delete mode 100644 sound/soc/blackfin/bfin-eval-adav80x.c
diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 84c3582..41af6b9 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -45,7 +45,6 @@ source "sound/soc/amd/Kconfig"
source "sound/soc/atmel/Kconfig"
source "sound/soc/au1x/Kconfig"
source "sound/soc/bcm/Kconfig"
-source "sound/soc/blackfin/Kconfig"
source "sound/soc/cirrus/Kconfig"
source "sound/soc/davinci/Kconfig"
source "sound/soc/dwc/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 74cd185..8d92492 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_SND_SOC) += amd/
obj-$(CONFIG_SND_SOC) += atmel/
obj-$(CONFIG_SND_SOC) += au1x/
obj-$(CONFIG_SND_SOC) += bcm/
-obj-$(CONFIG_SND_SOC) += blackfin/
obj-$(CONFIG_SND_SOC) += cirrus/
obj-$(CONFIG_SND_SOC) += davinci/
obj-$(CONFIG_SND_SOC) += dwc/
diff --git a/sound/soc/blackfin/Kconfig b/sound/soc/blackfin/Kconfig
deleted file mode 100644
index 6410aa2..0000000
--- a/sound/soc/blackfin/Kconfig
+++ /dev/null
@@ -1,205 +0,0 @@
-config SND_BF5XX_I2S
- tristate "SoC I2S Audio for the ADI Blackfin chip"
- depends on BLACKFIN
- select SND_BF5XX_SOC_SPORT if !BF60x
- select SND_BF6XX_SOC_SPORT if BF60x
- help
- Say Y or M if you want to add support for codecs attached to
- the Blackfin SPORT (synchronous serial ports) interface in I2S
- mode (supports single stereo In/Out).
- You will also need to select the audio interfaces to support below.
-
-config SND_BF5XX_SOC_SSM2602
- tristate "SoC SSM2602 Audio Codec Add-On Card support"
- depends on SND_BF5XX_I2S && SND_SOC_I2C_AND_SPI
- select SND_BF5XX_SOC_I2S if !BF60x
- select SND_BF6XX_SOC_I2S if BF60x
- select SND_SOC_SSM2602_SPI if SPI_MASTER
- select SND_SOC_SSM2602_I2C if I2C
- help
- Say Y if you want to add support for the Analog Devices
- SSM2602 Audio Codec Add-On Card.
-
-config SND_SOC_BFIN_EVAL_ADAU1701
- tristate "Support for the EVAL-ADAU1701MINIZ board on Blackfin eval boards"
- depends on SND_BF5XX_I2S && I2C
- select SND_BF5XX_SOC_I2S
- select SND_SOC_ADAU1701
- help
- Say Y if you want to add support for the Analog Devices EVAL-ADAU1701MINIZ
- board connected to one of the Blackfin evaluation boards like the
- BF5XX-STAMP or BF5XX-EZKIT.
-
-config SND_SOC_BFIN_EVAL_ADAU1373
- tristate "Support for the EVAL-ADAU1373 board on Blackfin eval boards"
- depends on SND_BF5XX_I2S && I2C
- select SND_BF5XX_SOC_I2S
- select SND_SOC_ADAU1373
- help
- Say Y if you want to add support for the Analog Devices EVAL-ADAU1373
- board connected to one of the Blackfin evaluation boards like the
- BF5XX-STAMP or BF5XX-EZKIT.
-
- Note: This driver assumes that first ADAU1373 DAI is connected to the
- first SPORT port on the BF5XX board.
-
-config SND_SOC_BFIN_EVAL_ADAU1X61
- tristate "Support for the EVAL-ADAU1X61 board on Blackfin eval boards"
- depends on SND_BF5XX_I2S && I2C
- select SND_BF5XX_SOC_I2S
- select SND_SOC_ADAU1761_I2C
- help
- Say Y if you want to add support for the Analog Devices EVAL-ADAU1X61
- board connected to one of the Blackfin evaluation boards like the
- BF5XX-STAMP or BF5XX-EZKIT.
-
- Note: This driver assumes that the ADAU1X61 is connected to the
- first SPORT port on the BF5XX board.
-
-config SND_SOC_BFIN_EVAL_ADAU1X81
- tristate "Support for the EVAL-ADAU1X81 boards on Blackfin eval boards"
- depends on SND_BF5XX_I2S && I2C
- select SND_BF5XX_SOC_I2S
- select SND_SOC_ADAU1781_I2C
- help
- Say Y if you want to add support for the Analog Devices EVAL-ADAU1X81
- board connected to one of the Blackfin evaluation boards like the
- BF5XX-STAMP or BF5XX-EZKIT.
-
- Note: This driver assumes that the ADAU1X81 is connected to the
- first SPORT port on the BF5XX board.
-
-config SND_SOC_BFIN_EVAL_ADAV80X
- tristate "Support for the EVAL-ADAV80X boards on Blackfin eval boards"
- depends on SND_BF5XX_I2S && SND_SOC_I2C_AND_SPI
- select SND_BF5XX_SOC_I2S
- select SND_SOC_ADAV801 if SPI_MASTER
- select SND_SOC_ADAV803 if I2C
- help
- Say Y if you want to add support for the Analog Devices EVAL-ADAV801 or
- EVAL-ADAV803 board connected to one of the Blackfin evaluation boards
- like the BF5XX-STAMP or BF5XX-EZKIT.
-
- Note: This driver assumes that the ADAV80X digital record and playback
- interfaces are connected to the first SPORT port on the BF5XX board.
-
-config SND_BF5XX_SOC_AD1836
- tristate "SoC AD1836 Audio support for BF5xx"
- depends on SND_BF5XX_I2S && SPI_MASTER
- select SND_BF5XX_SOC_I2S
- select SND_SOC_AD1836
- help
- Say Y if you want to add support for SoC audio on BF5xx STAMP/EZKIT.
-
-config SND_BF5XX_SOC_AD193X
- tristate "SoC AD193X Audio support for Blackfin"
- depends on SND_BF5XX_I2S && SND_SOC_I2C_AND_SPI
- select SND_BF5XX_SOC_I2S
- select SND_SOC_AD193X_I2C if I2C
- select SND_SOC_AD193X_SPI if SPI_MASTER
- help
- Say Y if you want to add support for AD193X codec on Blackfin.
- This driver supports AD1936, AD1937, AD1938 and AD1939.
-
-config SND_BF5XX_SOC_AD73311
- tristate "SoC AD73311 Audio support for Blackfin"
- depends on SND_BF5XX_I2S
- select SND_BF5XX_SOC_I2S
- select SND_SOC_AD73311
- help
- Say Y if you want to add support for AD73311 codec on Blackfin.
-
-config SND_BFIN_AD73311_SE
- int "PF pin for AD73311L Chip Select"
- depends on SND_BF5XX_SOC_AD73311
- default 4
- help
- Enter the GPIO used to control AD73311's SE pin. Acceptable
- values are 0 to 7
-
-config SND_BF5XX_AC97
- tristate "SoC AC97 Audio for the ADI BF5xx chip"
- depends on BLACKFIN
- select AC97_BUS
- select SND_SOC_AC97_BUS
- select SND_BF5XX_SOC_SPORT
- select SND_BF5XX_SOC_AC97
- help
- Say Y or M if you want to add support for codecs attached to
- the Blackfin SPORT (synchronous serial ports) interface in slot 16
- mode (pseudo AC97 interface).
- You will also need to select the audio interfaces to support below.
-
- Note:
- AC97 codecs which do not implement the slot-16 mode will not function
- properly with this driver. This driver is known to work with the
- Analog Devices line of AC97 codecs.
-
-config SND_BF5XX_MMAP_SUPPORT
- bool "Enable MMAP Support"
- depends on SND_BF5XX_AC97
- default y
- help
- Say y if you want AC97 driver to support mmap mode.
- We introduce an intermediate buffer to simulate mmap.
-
-config SND_BF5XX_MULTICHAN_SUPPORT
- bool "Enable Multichannel Support"
- depends on SND_BF5XX_AC97
- default n
- help
- Say y if you want AC97 driver to support up to 5.1 channel audio.
- this mode will consume much more memory for DMA.
-
-config SND_BF5XX_HAVE_COLD_RESET
- bool "BOARD has COLD Reset GPIO"
- depends on SND_BF5XX_AC97
- default y if BFIN548_EZKIT
- default n if !BFIN548_EZKIT
-
-config SND_BF5XX_RESET_GPIO_NUM
- int "Set a GPIO for cold reset"
- depends on SND_BF5XX_HAVE_COLD_RESET
- range 0 159
- default 19 if BFIN548_EZKIT
- default 5 if BFIN537_STAMP
- default 0
- help
- Set the correct GPIO for RESET the sound chip.
-
-config SND_BF5XX_SOC_AD1980
- tristate "SoC AD1980/1 Audio support for BF5xx (Obsolete)"
- depends on SND_BF5XX_AC97
- select SND_BF5XX_SOC_AC97
- select SND_SOC_AD1980
- help
- Say Y if you want to add support for SoC audio on BF5xx STAMP/EZKIT.
-
- Warning:
- Because Analog Devices Inc. discontinued the ad1980 sound chip since
- Sep. 2009, this ad1980 driver is not maintained, tested and supported
- by ADI now.
-
-config SND_BF5XX_SOC_SPORT
- tristate
-
-config SND_BF6XX_SOC_SPORT
- tristate
-
-config SND_BF5XX_SOC_I2S
- tristate
-
-config SND_BF6XX_SOC_I2S
- tristate
-
-config SND_BF5XX_SOC_AC97
- tristate
-
-config SND_BF5XX_SPORT_NUM
- int "Set a SPORT for Sound chip"
- depends on (SND_BF5XX_SOC_SPORT || SND_BF6XX_SOC_SPORT)
- range 0 3 if BF54x
- range 0 1 if !BF54x
- default 0
- help
- Set the correct SPORT for sound chip.
diff --git a/sound/soc/blackfin/Makefile b/sound/soc/blackfin/Makefile
deleted file mode 100644
index ebeb6a9..0000000
--- a/sound/soc/blackfin/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-# Blackfin Platform Support
-snd-bf5xx-ac97-objs := bf5xx-ac97-pcm.o
-snd-bf5xx-i2s-objs := bf5xx-i2s-pcm.o
-snd-soc-bf5xx-sport-objs := bf5xx-sport.o
-snd-soc-bf6xx-sport-objs := bf6xx-sport.o
-snd-soc-bf5xx-ac97-objs := bf5xx-ac97.o
-snd-soc-bf5xx-i2s-objs := bf5xx-i2s.o
-snd-soc-bf6xx-i2s-objs := bf6xx-i2s.o
-
-obj-$(CONFIG_SND_BF5XX_AC97) += snd-bf5xx-ac97.o
-obj-$(CONFIG_SND_BF5XX_I2S) += snd-bf5xx-i2s.o
-obj-$(CONFIG_SND_BF5XX_SOC_SPORT) += snd-soc-bf5xx-sport.o
-obj-$(CONFIG_SND_BF6XX_SOC_SPORT) += snd-soc-bf6xx-sport.o
-obj-$(CONFIG_SND_BF5XX_SOC_AC97) += snd-soc-bf5xx-ac97.o
-obj-$(CONFIG_SND_BF5XX_SOC_I2S) += snd-soc-bf5xx-i2s.o
-obj-$(CONFIG_SND_BF6XX_SOC_I2S) += snd-soc-bf6xx-i2s.o
-
-# Blackfin Machine Support
-snd-ad1836-objs := bf5xx-ad1836.o
-snd-ad1980-objs := bf5xx-ad1980.o
-snd-ssm2602-objs := bf5xx-ssm2602.o
-snd-ad73311-objs := bf5xx-ad73311.o
-snd-ad193x-objs := bf5xx-ad193x.o
-snd-soc-bfin-eval-adau1373-objs := bfin-eval-adau1373.o
-snd-soc-bfin-eval-adau1x61-objs := bfin-eval-adau1x61.o
-snd-soc-bfin-eval-adau1x81-objs := bfin-eval-adau1x81.o
-snd-soc-bfin-eval-adau1701-objs := bfin-eval-adau1701.o
-snd-soc-bfin-eval-adav80x-objs := bfin-eval-adav80x.o
-
-obj-$(CONFIG_SND_BF5XX_SOC_AD1836) += snd-ad1836.o
-obj-$(CONFIG_SND_BF5XX_SOC_AD1980) += snd-ad1980.o
-obj-$(CONFIG_SND_BF5XX_SOC_SSM2602) += snd-ssm2602.o
-obj-$(CONFIG_SND_BF5XX_SOC_AD73311) += snd-ad73311.o
-obj-$(CONFIG_SND_BF5XX_SOC_AD193X) += snd-ad193x.o
-obj-$(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373) += snd-soc-bfin-eval-adau1373.o
-obj-$(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) += snd-soc-bfin-eval-adau1x61.o
-obj-$(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X81) += snd-soc-bfin-eval-adau1x81.o
-obj-$(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701) += snd-soc-bfin-eval-adau1701.o
-obj-$(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X) += snd-soc-bfin-eval-adav80x.o
diff --git a/sound/soc/blackfin/bf5xx-ac97-pcm.c b/sound/soc/blackfin/bf5xx-ac97-pcm.c
deleted file mode 100644
index 8c1d198..0000000
--- a/sound/soc/blackfin/bf5xx-ac97-pcm.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/*
- * File: sound/soc/blackfin/bf5xx-ac97-pcm.c
- * Author: Cliff Cai <Cliff.Cai@analog.com>
- *
- * Created: Tue June 06 2008
- * Description: DMA Driver for AC97 sound chip
- *
- * Modified:
- * Copyright 2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gfp.h>
-
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/pcm_params.h>
-#include <sound/soc.h>
-
-#include <asm/dma.h>
-
-#include "bf5xx-ac97.h"
-#include "bf5xx-sport.h"
-
-static unsigned int ac97_chan_mask[] = {
- SP_FL, /* Mono */
- SP_STEREO, /* Stereo */
- SP_2DOT1, /* 2.1*/
- SP_QUAD,/*Quadraquic*/
- SP_FL | SP_FR | SP_FC | SP_SL | SP_SR,/*5 channels */
- SP_5DOT1, /* 5.1 */
-};
-
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
-static void bf5xx_mmap_copy(struct snd_pcm_substream *substream,
- snd_pcm_uframes_t count)
-{
- struct snd_pcm_runtime *runtime = substream->runtime;
- struct sport_device *sport = runtime->private_data;
- unsigned int chan_mask = ac97_chan_mask[runtime->channels - 1];
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- bf5xx_pcm_to_ac97((struct ac97_frame *)sport->tx_dma_buf +
- sport->tx_pos, (__u16 *)runtime->dma_area + sport->tx_pos *
- runtime->channels, count, chan_mask);
- sport->tx_pos += runtime->period_size;
- if (sport->tx_pos >= runtime->buffer_size)
- sport->tx_pos %= runtime->buffer_size;
- sport->tx_delay_pos = sport->tx_pos;
- } else {
- bf5xx_ac97_to_pcm((struct ac97_frame *)sport->rx_dma_buf +
- sport->rx_pos, (__u16 *)runtime->dma_area + sport->rx_pos *
- runtime->channels, count);
- sport->rx_pos += runtime->period_size;
- if (sport->rx_pos >= runtime->buffer_size)
- sport->rx_pos %= runtime->buffer_size;
- }
-}
-#endif
-
-static void bf5xx_dma_irq(void *data)
-{
- struct snd_pcm_substream *pcm = data;
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- struct snd_pcm_runtime *runtime = pcm->runtime;
- struct sport_device *sport = runtime->private_data;
- bf5xx_mmap_copy(pcm, runtime->period_size);
- if (pcm->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- if (sport->once == 0) {
- snd_pcm_period_elapsed(pcm);
- bf5xx_mmap_copy(pcm, runtime->period_size);
- sport->once = 1;
- }
- }
-#endif
- snd_pcm_period_elapsed(pcm);
-}
-
-/* The memory size for pure pcm data is 128*1024 = 0x20000 bytes.
- * The total rx/tx buffer is for ac97 frame to hold all pcm data
- * is 0x20000 * sizeof(struct ac97_frame) / 4.
- */
-static const struct snd_pcm_hardware bf5xx_pcm_hardware = {
- .info = SNDRV_PCM_INFO_INTERLEAVED |
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- SNDRV_PCM_INFO_MMAP |
- SNDRV_PCM_INFO_MMAP_VALID |
-#endif
- SNDRV_PCM_INFO_BLOCK_TRANSFER,
-
- .period_bytes_min = 32,
- .period_bytes_max = 0x10000,
- .periods_min = 1,
- .periods_max = PAGE_SIZE/32,
- .buffer_bytes_max = 0x20000, /* 128 kbytes */
- .fifo_size = 16,
-};
-
-static int bf5xx_pcm_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params)
-{
- size_t size = bf5xx_pcm_hardware.buffer_bytes_max
- * sizeof(struct ac97_frame) / 4;
-
- snd_pcm_lib_malloc_pages(substream, size);
-
- return 0;
-}
-
-static int bf5xx_pcm_hw_free(struct snd_pcm_substream *substream)
-{
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- struct snd_pcm_runtime *runtime = substream->runtime;
- struct sport_device *sport = runtime->private_data;
-
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- sport->once = 0;
- if (runtime->dma_area)
- memset(runtime->dma_area, 0, runtime->buffer_size);
- memset(sport->tx_dma_buf, 0, runtime->buffer_size *
- sizeof(struct ac97_frame));
- } else
- memset(sport->rx_dma_buf, 0, runtime->buffer_size *
- sizeof(struct ac97_frame));
-#endif
- snd_pcm_lib_free_pages(substream);
- return 0;
-}
-
-static int bf5xx_pcm_prepare(struct snd_pcm_substream *substream)
-{
- struct snd_pcm_runtime *runtime = substream->runtime;
- struct sport_device *sport = runtime->private_data;
-
- /* An intermediate buffer is introduced for implementing mmap for
- * SPORT working in TMD mode(include AC97).
- */
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- sport_set_tx_callback(sport, bf5xx_dma_irq, substream);
- sport_config_tx_dma(sport, sport->tx_dma_buf, runtime->periods,
- runtime->period_size * sizeof(struct ac97_frame));
- } else {
- sport_set_rx_callback(sport, bf5xx_dma_irq, substream);
- sport_config_rx_dma(sport, sport->rx_dma_buf, runtime->periods,
- runtime->period_size * sizeof(struct ac97_frame));
- }
-#else
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- sport_set_tx_callback(sport, bf5xx_dma_irq, substream);
- sport_config_tx_dma(sport, runtime->dma_area, runtime->periods,
- runtime->period_size * sizeof(struct ac97_frame));
- } else {
- sport_set_rx_callback(sport, bf5xx_dma_irq, substream);
- sport_config_rx_dma(sport, runtime->dma_area, runtime->periods,
- runtime->period_size * sizeof(struct ac97_frame));
- }
-#endif
- return 0;
-}
-
-static int bf5xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
-{
- struct snd_pcm_runtime *runtime = substream->runtime;
- struct sport_device *sport = runtime->private_data;
- int ret = 0;
-
- pr_debug("%s enter\n", __func__);
- switch (cmd) {
- case SNDRV_PCM_TRIGGER_START:
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- bf5xx_mmap_copy(substream, runtime->period_size);
- sport->tx_delay_pos = 0;
-#endif
- sport_tx_start(sport);
- } else
- sport_rx_start(sport);
- break;
- case SNDRV_PCM_TRIGGER_STOP:
- case SNDRV_PCM_TRIGGER_SUSPEND:
- case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- sport->tx_pos = 0;
-#endif
- sport_tx_stop(sport);
- } else {
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- sport->rx_pos = 0;
-#endif
- sport_rx_stop(sport);
- }
- break;
- default:
- ret = -EINVAL;
- }
- return ret;
-}
-
-static snd_pcm_uframes_t bf5xx_pcm_pointer(struct snd_pcm_substream *substream)
-{
- struct snd_pcm_runtime *runtime = substream->runtime;
- struct sport_device *sport = runtime->private_data;
- unsigned int curr;
-
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- curr = sport->tx_delay_pos;
- else
- curr = sport->rx_pos;
-#else
-
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- curr = sport_curr_offset_tx(sport) / sizeof(struct ac97_frame);
- else
- curr = sport_curr_offset_rx(sport) / sizeof(struct ac97_frame);
-
-#endif
- return curr;
-}
-
-static int bf5xx_pcm_open(struct snd_pcm_substream *substream)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(cpu_dai);
- struct snd_pcm_runtime *runtime = substream->runtime;
- int ret;
-
- pr_debug("%s enter\n", __func__);
- snd_soc_set_runtime_hwparams(substream, &bf5xx_pcm_hardware);
-
- ret = snd_pcm_hw_constraint_integer(runtime,
- SNDRV_PCM_HW_PARAM_PERIODS);
- if (ret < 0)
- goto out;
-
- if (sport_handle != NULL)
- runtime->private_data = sport_handle;
- else {
- pr_err("sport_handle is NULL\n");
- return -1;
- }
- return 0;
-
- out:
- return ret;
-}
-
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
-static int bf5xx_pcm_mmap(struct snd_pcm_substream *substream,
- struct vm_area_struct *vma)
-{
- struct snd_pcm_runtime *runtime = substream->runtime;
- size_t size = vma->vm_end - vma->vm_start;
- vma->vm_start = (unsigned long)runtime->dma_area;
- vma->vm_end = vma->vm_start + size;
- vma->vm_flags |= VM_SHARED;
- return 0 ;
-}
-#else
-static int bf5xx_pcm_copy(struct snd_pcm_substream *substream,
- int channel, unsigned long pos,
- void *buf, unsigned long count)
-{
- struct snd_pcm_runtime *runtime = substream->runtime;
- unsigned int chan_mask = ac97_chan_mask[runtime->channels - 1];
- struct ac97_frame *dst;
-
- pr_debug("%s copy pos:0x%lx count:0x%lx\n",
- substream->stream ? "Capture" : "Playback", pos, count);
- dst = (struct ac97_frame *)runtime->dma_area +
- bytes_to_frames(runtime, pos);
- count = bytes_to_frames(runtime, count);
-
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- bf5xx_pcm_to_ac97(dst, buf, count, chan_mask);
- else
- bf5xx_ac97_to_pcm(dst, buf, count);
- return 0;
-}
-
-static int bf5xx_pcm_copy_user(struct snd_pcm_substream *substream,
- int channel, unsigned long pos,
- void __user *buf, unsigned long count)
-{
- return bf5xx_pcm_copy(substream, channel, pos, (void *)buf, count);
-}
-#endif
-
-static const struct snd_pcm_ops bf5xx_pcm_ac97_ops = {
- .open = bf5xx_pcm_open,
- .ioctl = snd_pcm_lib_ioctl,
- .hw_params = bf5xx_pcm_hw_params,
- .hw_free = bf5xx_pcm_hw_free,
- .prepare = bf5xx_pcm_prepare,
- .trigger = bf5xx_pcm_trigger,
- .pointer = bf5xx_pcm_pointer,
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- .mmap = bf5xx_pcm_mmap,
-#else
- .copy_user = bf5xx_pcm_copy_user,
- .copy_kernel = bf5xx_pcm_copy,
-#endif
-};
-
-static int bf5xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
-{
- struct snd_soc_pcm_runtime *rtd = pcm->private_data;
- struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(cpu_dai);
- struct snd_pcm_substream *substream = pcm->streams[stream].substream;
- struct snd_dma_buffer *buf = &substream->dma_buffer;
- size_t size = bf5xx_pcm_hardware.buffer_bytes_max
- * sizeof(struct ac97_frame) / 4;
-
- buf->dev.type = SNDRV_DMA_TYPE_DEV;
- buf->dev.dev = pcm->card->dev;
- buf->private_data = NULL;
- buf->area = dma_alloc_coherent(pcm->card->dev, size,
- &buf->addr, GFP_KERNEL);
- if (!buf->area) {
- pr_err("Failed to allocate dma memory\n");
- pr_err("Please increase uncached DMA memory region\n");
- return -ENOMEM;
- }
- buf->bytes = size;
-
- pr_debug("%s, area:%p, size:0x%08lx\n", __func__,
- buf->area, buf->bytes);
-
- if (stream == SNDRV_PCM_STREAM_PLAYBACK)
- sport_handle->tx_buf = buf->area;
- else
- sport_handle->rx_buf = buf->area;
-
-/*
- * Need to allocate local buffer when enable
- * MMAP for SPORT working in TMD mode (include AC97).
- */
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- if (!sport_handle->tx_dma_buf) {
- sport_handle->tx_dma_buf = dma_alloc_coherent(NULL, \
- size, &sport_handle->tx_dma_phy, GFP_KERNEL);
- if (!sport_handle->tx_dma_buf) {
- pr_err("Failed to allocate memory for tx dma buf - Please increase uncached DMA memory region\n");
- return -ENOMEM;
- } else
- memset(sport_handle->tx_dma_buf, 0, size);
- } else
- memset(sport_handle->tx_dma_buf, 0, size);
- } else {
- if (!sport_handle->rx_dma_buf) {
- sport_handle->rx_dma_buf = dma_alloc_coherent(NULL, \
- size, &sport_handle->rx_dma_phy, GFP_KERNEL);
- if (!sport_handle->rx_dma_buf) {
- pr_err("Failed to allocate memory for rx dma buf - Please increase uncached DMA memory region\n");
- return -ENOMEM;
- } else
- memset(sport_handle->rx_dma_buf, 0, size);
- } else
- memset(sport_handle->rx_dma_buf, 0, size);
- }
-#endif
- return 0;
-}
-
-static void bf5xx_pcm_free_dma_buffers(struct snd_pcm *pcm)
-{
- struct snd_pcm_substream *substream;
- struct snd_dma_buffer *buf;
- int stream;
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- struct snd_soc_pcm_runtime *rtd = pcm->private_data;
- struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(cpu_dai);
- size_t size = bf5xx_pcm_hardware.buffer_bytes_max *
- sizeof(struct ac97_frame) / 4;
-#endif
- for (stream = 0; stream < 2; stream++) {
- substream = pcm->streams[stream].substream;
- if (!substream)
- continue;
-
- buf = &substream->dma_buffer;
- if (!buf->area)
- continue;
- dma_free_coherent(NULL, buf->bytes, buf->area, 0);
- buf->area = NULL;
-#if defined(CONFIG_SND_BF5XX_MMAP_SUPPORT)
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- if (sport_handle->tx_dma_buf)
- dma_free_coherent(NULL, size, \
- sport_handle->tx_dma_buf, 0);
- sport_handle->tx_dma_buf = NULL;
- } else {
-
- if (sport_handle->rx_dma_buf)
- dma_free_coherent(NULL, size, \
- sport_handle->rx_dma_buf, 0);
- sport_handle->rx_dma_buf = NULL;
- }
-#endif
- }
-}
-
-static int bf5xx_pcm_ac97_new(struct snd_soc_pcm_runtime *rtd)
-{
- struct snd_card *card = rtd->card->snd_card;
- struct snd_pcm *pcm = rtd->pcm;
- int ret;
-
- pr_debug("%s enter\n", __func__);
- ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
- if (ret)
- return ret;
-
- if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
- ret = bf5xx_pcm_preallocate_dma_buffer(pcm,
- SNDRV_PCM_STREAM_PLAYBACK);
- if (ret)
- goto out;
- }
-
- if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
- ret = bf5xx_pcm_preallocate_dma_buffer(pcm,
- SNDRV_PCM_STREAM_CAPTURE);
- if (ret)
- goto out;
- }
- out:
- return ret;
-}
-
-static struct snd_soc_platform_driver bf5xx_ac97_soc_platform = {
- .ops = &bf5xx_pcm_ac97_ops,
- .pcm_new = bf5xx_pcm_ac97_new,
- .pcm_free = bf5xx_pcm_free_dma_buffers,
-};
-
-static int bf5xx_soc_platform_probe(struct platform_device *pdev)
-{
- return devm_snd_soc_register_platform(&pdev->dev,
- &bf5xx_ac97_soc_platform);
-}
-
-static struct platform_driver bf5xx_pcm_driver = {
- .driver = {
- .name = "bfin-ac97-pcm-audio",
- },
-
- .probe = bf5xx_soc_platform_probe,
-};
-
-module_platform_driver(bf5xx_pcm_driver);
-
-MODULE_AUTHOR("Cliff Cai");
-MODULE_DESCRIPTION("ADI Blackfin AC97 PCM DMA module");
-MODULE_LICENSE("GPL");
diff --git a/sound/soc/blackfin/bf5xx-ac97.c b/sound/soc/blackfin/bf5xx-ac97.c
deleted file mode 100644
index a040cfe..0000000
--- a/sound/soc/blackfin/bf5xx-ac97.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/*
- * bf5xx-ac97.c -- AC97 support for the ADI blackfin chip.
- *
- * Author: Roy Huang
- * Created: 11th. June 2007
- * Copyright: Analog Device Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/wait.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/ac97_codec.h>
-#include <sound/initval.h>
-#include <sound/soc.h>
-
-#include <asm/irq.h>
-#include <asm/portmux.h>
-#include <linux/mutex.h>
-#include <linux/gpio.h>
-
-#include "bf5xx-sport.h"
-#include "bf5xx-ac97.h"
-
-/* Anomaly notes:
- * 05000250 - AD1980 is running in TDM mode and RFS/TFS are generated by SPORT
- * contrtoller. But, RFSDIV and TFSDIV are always set to 16*16-1,
- * while the max AC97 data size is 13*16. The DIV is always larger
- * than data size. AD73311 and ad2602 are not running in TDM mode.
- * AD1836 and AD73322 depend on external RFS/TFS only. So, this
- * anomaly does not affect blackfin sound drivers.
-*/
-
-static struct sport_device *ac97_sport_handle;
-
-void bf5xx_pcm_to_ac97(struct ac97_frame *dst, const __u16 *src,
- size_t count, unsigned int chan_mask)
-{
- while (count--) {
- dst->ac97_tag = TAG_VALID;
- if (chan_mask & SP_FL) {
- dst->ac97_pcm_r = *src++;
- dst->ac97_tag |= TAG_PCM_RIGHT;
- }
- if (chan_mask & SP_FR) {
- dst->ac97_pcm_l = *src++;
- dst->ac97_tag |= TAG_PCM_LEFT;
-
- }
-#if defined(CONFIG_SND_BF5XX_MULTICHAN_SUPPORT)
- if (chan_mask & SP_SR) {
- dst->ac97_sl = *src++;
- dst->ac97_tag |= TAG_PCM_SL;
- }
- if (chan_mask & SP_SL) {
- dst->ac97_sr = *src++;
- dst->ac97_tag |= TAG_PCM_SR;
- }
- if (chan_mask & SP_LFE) {
- dst->ac97_lfe = *src++;
- dst->ac97_tag |= TAG_PCM_LFE;
- }
- if (chan_mask & SP_FC) {
- dst->ac97_center = *src++;
- dst->ac97_tag |= TAG_PCM_CENTER;
- }
-#endif
- dst++;
- }
-}
-EXPORT_SYMBOL(bf5xx_pcm_to_ac97);
-
-void bf5xx_ac97_to_pcm(const struct ac97_frame *src, __u16 *dst,
- size_t count)
-{
- while (count--) {
- *(dst++) = src->ac97_pcm_l;
- *(dst++) = src->ac97_pcm_r;
- src++;
- }
-}
-EXPORT_SYMBOL(bf5xx_ac97_to_pcm);
-
-static unsigned int sport_tx_curr_frag(struct sport_device *sport)
-{
- return sport->tx_curr_frag = sport_curr_offset_tx(sport) /
- sport->tx_fragsize;
-}
-
-static void enqueue_cmd(struct snd_ac97 *ac97, __u16 addr, __u16 data)
-{
- struct sport_device *sport = ac97_sport_handle;
- int *cmd_count = sport->private_data;
- int nextfrag = sport_tx_curr_frag(sport);
- struct ac97_frame *nextwrite;
-
- sport_incfrag(sport, &nextfrag, 1);
-
- nextwrite = (struct ac97_frame *)(sport->tx_buf +
- nextfrag * sport->tx_fragsize);
- pr_debug("sport->tx_buf:%p, nextfrag:0x%x nextwrite:%p, cmd_count:%d\n",
- sport->tx_buf, nextfrag, nextwrite, cmd_count[nextfrag]);
- nextwrite[cmd_count[nextfrag]].ac97_tag |= TAG_CMD;
- nextwrite[cmd_count[nextfrag]].ac97_addr = addr;
- nextwrite[cmd_count[nextfrag]].ac97_data = data;
- ++cmd_count[nextfrag];
- pr_debug("ac97_sport: Inserting %02x/%04x into fragment %d\n",
- addr >> 8, data, nextfrag);
-}
-
-static unsigned short bf5xx_ac97_read(struct snd_ac97 *ac97,
- unsigned short reg)
-{
- struct sport_device *sport_handle = ac97_sport_handle;
- struct ac97_frame out_frame[2], in_frame[2];
-
- pr_debug("%s enter 0x%x\n", __func__, reg);
-
- /* When dma descriptor is enabled, the register should not be read */
- if (sport_handle->tx_run || sport_handle->rx_run) {
- pr_err("Could you send a mail to cliff.cai at analog.com "
- "to report this?\n");
- return -EFAULT;
- }
-
- memset(&out_frame, 0, 2 * sizeof(struct ac97_frame));
- memset(&in_frame, 0, 2 * sizeof(struct ac97_frame));
- out_frame[0].ac97_tag = TAG_VALID | TAG_CMD;
- out_frame[0].ac97_addr = ((reg << 8) | 0x8000);
- sport_send_and_recv(sport_handle, (unsigned char *)&out_frame,
- (unsigned char *)&in_frame,
- 2 * sizeof(struct ac97_frame));
- return in_frame[1].ac97_data;
-}
-
-void bf5xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
- unsigned short val)
-{
- struct sport_device *sport_handle = ac97_sport_handle;
-
- pr_debug("%s enter 0x%x:0x%04x\n", __func__, reg, val);
-
- if (sport_handle->tx_run) {
- enqueue_cmd(ac97, (reg << 8), val); /* write */
- enqueue_cmd(ac97, (reg << 8) | 0x8000, 0); /* read back */
- } else {
- struct ac97_frame frame;
- memset(&frame, 0, sizeof(struct ac97_frame));
- frame.ac97_tag = TAG_VALID | TAG_CMD;
- frame.ac97_addr = (reg << 8);
- frame.ac97_data = val;
- sport_send_and_recv(sport_handle, (unsigned char *)&frame, \
- NULL, sizeof(struct ac97_frame));
- }
-}
-
-static void bf5xx_ac97_warm_reset(struct snd_ac97 *ac97)
-{
- struct sport_device *sport_handle = ac97_sport_handle;
- u16 gpio = P_IDENT(sport_handle->pin_req[3]);
-
- pr_debug("%s enter\n", __func__);
-
- peripheral_free_list(sport_handle->pin_req);
- gpio_request(gpio, "bf5xx-ac97");
- gpio_direction_output(gpio, 1);
- udelay(2);
- gpio_set_value(gpio, 0);
- udelay(1);
- gpio_free(gpio);
- peripheral_request_list(sport_handle->pin_req, "soc-audio");
-}
-
-static void bf5xx_ac97_cold_reset(struct snd_ac97 *ac97)
-{
-#ifdef CONFIG_SND_BF5XX_HAVE_COLD_RESET
- pr_debug("%s enter\n", __func__);
-
- /* It is specified for bf548-ezkit */
- gpio_set_value(CONFIG_SND_BF5XX_RESET_GPIO_NUM, 0);
- /* Keep reset pin low for 1 ms */
- mdelay(1);
- gpio_set_value(CONFIG_SND_BF5XX_RESET_GPIO_NUM, 1);
- /* Wait for bit clock recover */
- mdelay(1);
-#else
- pr_info("%s: Not implemented\n", __func__);
-#endif
-}
-
-static struct snd_ac97_bus_ops bf5xx_ac97_ops = {
- .read = bf5xx_ac97_read,
- .write = bf5xx_ac97_write,
- .warm_reset = bf5xx_ac97_warm_reset,
- .reset = bf5xx_ac97_cold_reset,
-};
-
-#ifdef CONFIG_PM
-static int bf5xx_ac97_suspend(struct snd_soc_dai *dai)
-{
- struct sport_device *sport = snd_soc_dai_get_drvdata(dai);
-
- pr_debug("%s : sport %d\n", __func__, dai->id);
- if (!dai->active)
- return 0;
- if (dai->capture_active)
- sport_rx_stop(sport);
- if (dai->playback_active)
- sport_tx_stop(sport);
- return 0;
-}
-
-static int bf5xx_ac97_resume(struct snd_soc_dai *dai)
-{
- int ret;
- struct sport_device *sport = snd_soc_dai_get_drvdata(dai);
-
- pr_debug("%s : sport %d\n", __func__, dai->id);
- if (!dai->active)
- return 0;
-
-#if defined(CONFIG_SND_BF5XX_MULTICHAN_SUPPORT)
- ret = sport_set_multichannel(sport, 16, 0x3FF, 0x3FF, 1);
-#else
- ret = sport_set_multichannel(sport, 16, 0x1F, 0x1F, 1);
-#endif
- if (ret) {
- pr_err("SPORT is busy!\n");
- return -EBUSY;
- }
-
- ret = sport_config_rx(sport, IRFS, 0xF, 0, (16*16-1));
- if (ret) {
- pr_err("SPORT is busy!\n");
- return -EBUSY;
- }
-
- ret = sport_config_tx(sport, ITFS, 0xF, 0, (16*16-1));
- if (ret) {
- pr_err("SPORT is busy!\n");
- return -EBUSY;
- }
-
- return 0;
-}
-
-#else
-#define bf5xx_ac97_suspend NULL
-#define bf5xx_ac97_resume NULL
-#endif
-
-static struct snd_soc_dai_driver bfin_ac97_dai = {
- .bus_control = true,
- .suspend = bf5xx_ac97_suspend,
- .resume = bf5xx_ac97_resume,
- .playback = {
- .stream_name = "AC97 Playback",
- .channels_min = 2,
-#if defined(CONFIG_SND_BF5XX_MULTICHAN_SUPPORT)
- .channels_max = 6,
-#else
- .channels_max = 2,
-#endif
- .rates = SNDRV_PCM_RATE_48000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE, },
- .capture = {
- .stream_name = "AC97 Capture",
- .channels_min = 2,
- .channels_max = 2,
- .rates = SNDRV_PCM_RATE_48000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE, },
-};
-
-static const struct snd_soc_component_driver bfin_ac97_component = {
- .name = "bfin-ac97",
-};
-
-static int asoc_bfin_ac97_probe(struct platform_device *pdev)
-{
- struct sport_device *sport_handle;
- int ret;
-
-#ifdef CONFIG_SND_BF5XX_HAVE_COLD_RESET
- /* Request PB3 as reset pin */
- ret = devm_gpio_request_one(&pdev->dev,
- CONFIG_SND_BF5XX_RESET_GPIO_NUM,
- GPIOF_OUT_INIT_HIGH, "SND_AD198x RESET");
- if (ret) {
- dev_err(&pdev->dev,
- "Failed to request GPIO_%d for reset: %d\n",
- CONFIG_SND_BF5XX_RESET_GPIO_NUM, ret);
- return ret;
- }
-#endif
-
- sport_handle = sport_init(pdev, 2, sizeof(struct ac97_frame),
- PAGE_SIZE);
- if (!sport_handle) {
- ret = -ENODEV;
- goto sport_err;
- }
-
- /*SPORT works in TDM mode to simulate AC97 transfers*/
-#if defined(CONFIG_SND_BF5XX_MULTICHAN_SUPPORT)
- ret = sport_set_multichannel(sport_handle, 16, 0x3FF, 0x3FF, 1);
-#else
- ret = sport_set_multichannel(sport_handle, 16, 0x1F, 0x1F, 1);
-#endif
- if (ret) {
- pr_err("SPORT is busy!\n");
- ret = -EBUSY;
- goto sport_config_err;
- }
-
- ret = sport_config_rx(sport_handle, IRFS, 0xF, 0, (16*16-1));
- if (ret) {
- pr_err("SPORT is busy!\n");
- ret = -EBUSY;
- goto sport_config_err;
- }
-
- ret = sport_config_tx(sport_handle, ITFS, 0xF, 0, (16*16-1));
- if (ret) {
- pr_err("SPORT is busy!\n");
- ret = -EBUSY;
- goto sport_config_err;
- }
-
- ret = snd_soc_set_ac97_ops(&bf5xx_ac97_ops);
- if (ret != 0) {
- dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
- goto sport_config_err;
- }
-
- ret = snd_soc_register_component(&pdev->dev, &bfin_ac97_component,
- &bfin_ac97_dai, 1);
- if (ret) {
- pr_err("Failed to register DAI: %d\n", ret);
- goto sport_config_err;
- }
-
- ac97_sport_handle = sport_handle;
-
- return 0;
-
-sport_config_err:
- sport_done(sport_handle);
-sport_err:
- snd_soc_set_ac97_ops(NULL);
-
- return ret;
-}
-
-static int asoc_bfin_ac97_remove(struct platform_device *pdev)
-{
- struct sport_device *sport_handle = platform_get_drvdata(pdev);
-
- snd_soc_unregister_component(&pdev->dev);
- sport_done(sport_handle);
- snd_soc_set_ac97_ops(NULL);
-
- return 0;
-}
-
-static struct platform_driver asoc_bfin_ac97_driver = {
- .driver = {
- .name = "bfin-ac97",
- },
-
- .probe = asoc_bfin_ac97_probe,
- .remove = asoc_bfin_ac97_remove,
-};
-
-module_platform_driver(asoc_bfin_ac97_driver);
-
-MODULE_AUTHOR("Roy Huang");
-MODULE_DESCRIPTION("AC97 driver for ADI Blackfin");
-MODULE_LICENSE("GPL");
diff --git a/sound/soc/blackfin/bf5xx-ac97.h b/sound/soc/blackfin/bf5xx-ac97.h
deleted file mode 100644
index a680fdc..0000000
--- a/sound/soc/blackfin/bf5xx-ac97.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * sound/soc/blackfin/bf5xx-ac97.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _BF5XX_AC97_H
-#define _BF5XX_AC97_H
-
-/* Frame format in memory, only support stereo currently */
-struct ac97_frame {
- u16 ac97_tag; /* slot 0 */
- u16 ac97_addr; /* slot 1 */
- u16 ac97_data; /* slot 2 */
- u16 ac97_pcm_l; /*slot 3:front left*/
- u16 ac97_pcm_r; /*slot 4:front left*/
-#if defined(CONFIG_SND_BF5XX_MULTICHAN_SUPPORT)
- u16 ac97_mdm_l1;
- u16 ac97_center; /*slot 6:center*/
- u16 ac97_sl; /*slot 7:surround left*/
- u16 ac97_sr; /*slot 8:surround right*/
- u16 ac97_lfe; /*slot 9:lfe*/
-#endif
-} __attribute__ ((packed));
-
-/* Speaker location */
-#define SP_FL 0x0001
-#define SP_FR 0x0010
-#define SP_FC 0x0002
-#define SP_LFE 0x0020
-#define SP_SL 0x0004
-#define SP_SR 0x0040
-
-#define SP_STEREO (SP_FL | SP_FR)
-#define SP_2DOT1 (SP_FL | SP_FR | SP_LFE)
-#define SP_QUAD (SP_FL | SP_FR | SP_SL | SP_SR)
-#define SP_5DOT1 (SP_FL | SP_FR | SP_FC | SP_LFE | SP_SL | SP_SR)
-
-#define TAG_VALID 0x8000
-#define TAG_CMD 0x6000
-#define TAG_PCM_LEFT 0x1000
-#define TAG_PCM_RIGHT 0x0800
-#define TAG_PCM_MDM_L1 0x0400
-#define TAG_PCM_CENTER 0x0200
-#define TAG_PCM_SL 0x0100
-#define TAG_PCM_SR 0x0080
-#define TAG_PCM_LFE 0x0040
-
-void bf5xx_pcm_to_ac97(struct ac97_frame *dst, const __u16 *src, \
- size_t count, unsigned int chan_mask);
-
-void bf5xx_ac97_to_pcm(const struct ac97_frame *src, __u16 *dst, \
- size_t count);
-
-#endif
diff --git a/sound/soc/blackfin/bf5xx-ad1836.c b/sound/soc/blackfin/bf5xx-ad1836.c
deleted file mode 100644
index 864df26..0000000
--- a/sound/soc/blackfin/bf5xx-ad1836.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * File: sound/soc/blackfin/bf5xx-ad1836.c
- * Author: Barry Song <Barry.Song@analog.com>
- *
- * Created: Aug 4 2009
- * Description: Board driver for ad1836 sound chip
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/device.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-#include <sound/pcm_params.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#include "../codecs/ad1836.h"
-
-static struct snd_soc_card bf5xx_ad1836;
-
-static int bf5xx_ad1836_init(struct snd_soc_pcm_runtime *rtd)
-{
- struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
- unsigned int channel_map[] = {0, 4, 1, 5, 2, 6, 3, 7};
- int ret = 0;
-
- /* set cpu DAI channel mapping */
- ret = snd_soc_dai_set_channel_map(cpu_dai, ARRAY_SIZE(channel_map),
- channel_map, ARRAY_SIZE(channel_map), channel_map);
- if (ret < 0)
- return ret;
-
- ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0xFF, 0xFF, 8, 32);
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-#define BF5XX_AD1836_DAIFMT (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_IF | \
- SND_SOC_DAIFMT_CBM_CFM)
-
-static struct snd_soc_dai_link bf5xx_ad1836_dai = {
- .name = "ad1836",
- .stream_name = "AD1836",
- .codec_dai_name = "ad1836-hifi",
- .platform_name = "bfin-i2s-pcm-audio",
- .dai_fmt = BF5XX_AD1836_DAIFMT,
- .init = bf5xx_ad1836_init,
-};
-
-static struct snd_soc_card bf5xx_ad1836 = {
- .name = "bfin-ad1836",
- .owner = THIS_MODULE,
- .dai_link = &bf5xx_ad1836_dai,
- .num_links = 1,
-};
-
-static int bf5xx_ad1836_driver_probe(struct platform_device *pdev)
-{
- struct snd_soc_card *card = &bf5xx_ad1836;
- const char **link_name;
- int ret;
-
- link_name = pdev->dev.platform_data;
- if (!link_name) {
- dev_err(&pdev->dev, "No platform data supplied\n");
- return -EINVAL;
- }
- bf5xx_ad1836_dai.cpu_dai_name = link_name[0];
- bf5xx_ad1836_dai.codec_name = link_name[1];
-
- card->dev = &pdev->dev;
- platform_set_drvdata(pdev, card);
-
- ret = devm_snd_soc_register_card(&pdev->dev, card);
- if (ret)
- dev_err(&pdev->dev, "Failed to register card\n");
- return ret;
-}
-
-static struct platform_driver bf5xx_ad1836_driver = {
- .driver = {
- .name = "bfin-snd-ad1836",
- .pm = &snd_soc_pm_ops,
- },
- .probe = bf5xx_ad1836_driver_probe,
-};
-module_platform_driver(bf5xx_ad1836_driver);
-
-/* Module information */
-MODULE_AUTHOR("Barry Song");
-MODULE_DESCRIPTION("ALSA SoC AD1836 board driver");
-MODULE_LICENSE("GPL");
-
diff --git a/sound/soc/blackfin/bf5xx-ad193x.c b/sound/soc/blackfin/bf5xx-ad193x.c
deleted file mode 100644
index 603ad1f..0000000
--- a/sound/soc/blackfin/bf5xx-ad193x.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * File: sound/soc/blackfin/bf5xx-ad193x.c
- * Author: Barry Song <Barry.Song@analog.com>
- *
- * Created: Thur June 4 2009
- * Description: Board driver for ad193x sound chip
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/device.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-#include <sound/pcm_params.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#include "../codecs/ad193x.h"
-
-static struct snd_soc_card bf5xx_ad193x;
-
-static int bf5xx_ad193x_link_init(struct snd_soc_pcm_runtime *rtd)
-{
- struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
- struct snd_soc_dai *codec_dai = rtd->codec_dai;
- int ret;
-
- /* set the codec system clock for DAC and ADC */
- ret = snd_soc_dai_set_sysclk(codec_dai, 0, 24576000, SND_SOC_CLOCK_IN);
- if (ret < 0)
- return ret;
-
- /* set codec DAI slots, 8 channels, all channels are enabled */
- ret = snd_soc_dai_set_tdm_slot(codec_dai, 0xFF, 0xFF, 8, 32);
- if (ret < 0)
- return ret;
-
- ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0xFF, 0xFF, 8, 32);
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-#define BF5XX_AD193X_DAIFMT (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_IF | \
- SND_SOC_DAIFMT_CBM_CFM)
-
-static struct snd_soc_dai_link bf5xx_ad193x_dai[] = {
- {
- .name = "ad193x",
- .stream_name = "AD193X",
- .cpu_dai_name = "bfin-i2s.0",
- .codec_dai_name ="ad193x-hifi",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "spi0.5",
- .dai_fmt = BF5XX_AD193X_DAIFMT,
- .init = bf5xx_ad193x_link_init,
- },
- {
- .name = "ad193x",
- .stream_name = "AD193X",
- .cpu_dai_name = "bfin-i2s.1",
- .codec_dai_name ="ad193x-hifi",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "spi0.5",
- .dai_fmt = BF5XX_AD193X_DAIFMT,
- .init = bf5xx_ad193x_link_init,
- },
-};
-
-static struct snd_soc_card bf5xx_ad193x = {
- .name = "bfin-ad193x",
- .owner = THIS_MODULE,
- .dai_link = &bf5xx_ad193x_dai[CONFIG_SND_BF5XX_SPORT_NUM],
- .num_links = 1,
-};
-
-static struct platform_device *bfxx_ad193x_snd_device;
-
-static int __init bf5xx_ad193x_init(void)
-{
- int ret;
-
- bfxx_ad193x_snd_device = platform_device_alloc("soc-audio", -1);
- if (!bfxx_ad193x_snd_device)
- return -ENOMEM;
-
- platform_set_drvdata(bfxx_ad193x_snd_device, &bf5xx_ad193x);
- ret = platform_device_add(bfxx_ad193x_snd_device);
-
- if (ret)
- platform_device_put(bfxx_ad193x_snd_device);
-
- return ret;
-}
-
-static void __exit bf5xx_ad193x_exit(void)
-{
- platform_device_unregister(bfxx_ad193x_snd_device);
-}
-
-module_init(bf5xx_ad193x_init);
-module_exit(bf5xx_ad193x_exit);
-
-/* Module information */
-MODULE_AUTHOR("Barry Song");
-MODULE_DESCRIPTION("ALSA SoC AD193X board driver");
-MODULE_LICENSE("GPL");
-
diff --git a/sound/soc/blackfin/bf5xx-ad1980.c b/sound/soc/blackfin/bf5xx-ad1980.c
deleted file mode 100644
index 0fa81a5..0000000
--- a/sound/soc/blackfin/bf5xx-ad1980.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * File: sound/soc/blackfin/bf5xx-ad1980.c
- * Author: Cliff Cai <Cliff.Cai@analog.com>
- *
- * Created: Tue June 06 2008
- * Description: Board driver for AD1980/1 audio codec
- *
- * Modified:
- * Copyright 2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * WARNING:
- *
- * Because Analog Devices Inc. discontinued the ad1980 sound chip since
- * Sep. 2009, this ad1980 driver is not maintained, tested and supported
- * by ADI now.
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/device.h>
-#include <asm/dma.h>
-
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-
-#include <linux/gpio.h>
-#include <asm/portmux.h>
-
-#include "bf5xx-ac97.h"
-
-static struct snd_soc_card bf5xx_board;
-
-static struct snd_soc_dai_link bf5xx_board_dai[] = {
- {
- .name = "AC97",
- .stream_name = "AC97 HiFi",
- .cpu_dai_name = "bfin-ac97.0",
- .codec_dai_name = "ad1980-hifi",
- .platform_name = "bfin-ac97-pcm-audio",
- .codec_name = "ad1980",
- },
- {
- .name = "AC97",
- .stream_name = "AC97 HiFi",
- .cpu_dai_name = "bfin-ac97.1",
- .codec_dai_name = "ad1980-hifi",
- .platform_name = "bfin-ac97-pcm-audio",
- .codec_name = "ad1980",
- },
-};
-
-static struct snd_soc_card bf5xx_board = {
- .name = "bfin-ad1980",
- .owner = THIS_MODULE,
- .dai_link = &bf5xx_board_dai[CONFIG_SND_BF5XX_SPORT_NUM],
- .num_links = 1,
-};
-
-static struct platform_device *bf5xx_board_snd_device;
-
-static int __init bf5xx_board_init(void)
-{
- int ret;
-
- bf5xx_board_snd_device = platform_device_alloc("soc-audio", -1);
- if (!bf5xx_board_snd_device)
- return -ENOMEM;
-
- platform_set_drvdata(bf5xx_board_snd_device, &bf5xx_board);
- ret = platform_device_add(bf5xx_board_snd_device);
-
- if (ret)
- platform_device_put(bf5xx_board_snd_device);
-
- return ret;
-}
-
-static void __exit bf5xx_board_exit(void)
-{
- platform_device_unregister(bf5xx_board_snd_device);
-}
-
-module_init(bf5xx_board_init);
-module_exit(bf5xx_board_exit);
-
-/* Module information */
-MODULE_AUTHOR("Cliff Cai");
-MODULE_DESCRIPTION("ALSA SoC AD1980/1 BF5xx board (Obsolete)");
-MODULE_LICENSE("GPL");
diff --git a/sound/soc/blackfin/bf5xx-ad73311.c b/sound/soc/blackfin/bf5xx-ad73311.c
deleted file mode 100644
index 786bbdd..0000000
--- a/sound/soc/blackfin/bf5xx-ad73311.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * File: sound/soc/blackfin/bf5xx-ad73311.c
- * Author: Cliff Cai <Cliff.Cai@analog.com>
- *
- * Created: Thur Sep 25 2008
- * Description: Board driver for ad73311 sound chip
- *
- * Modified:
- * Copyright 2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-#include <sound/pcm_params.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#include "../codecs/ad73311.h"
-#include "bf5xx-sport.h"
-
-#if CONFIG_SND_BF5XX_SPORT_NUM == 0
-#define bfin_write_SPORT_TCR1 bfin_write_SPORT0_TCR1
-#define bfin_read_SPORT_TCR1 bfin_read_SPORT0_TCR1
-#define bfin_write_SPORT_TCR2 bfin_write_SPORT0_TCR2
-#define bfin_write_SPORT_TX16 bfin_write_SPORT0_TX16
-#define bfin_read_SPORT_STAT bfin_read_SPORT0_STAT
-#else
-#define bfin_write_SPORT_TCR1 bfin_write_SPORT1_TCR1
-#define bfin_read_SPORT_TCR1 bfin_read_SPORT1_TCR1
-#define bfin_write_SPORT_TCR2 bfin_write_SPORT1_TCR2
-#define bfin_write_SPORT_TX16 bfin_write_SPORT1_TX16
-#define bfin_read_SPORT_STAT bfin_read_SPORT1_STAT
-#endif
-
-#define GPIO_SE CONFIG_SND_BFIN_AD73311_SE
-
-static struct snd_soc_card bf5xx_ad73311;
-
-static int snd_ad73311_startup(void)
-{
- pr_debug("%s enter\n", __func__);
-
- /* Pull up SE pin on AD73311L */
- gpio_set_value(GPIO_SE, 1);
- return 0;
-}
-
-static int snd_ad73311_configure(void)
-{
- unsigned short ctrl_regs[6];
- unsigned short status = 0;
- int count = 0;
-
- /* DMCLK = MCLK = 16.384 MHz
- * SCLK = DMCLK/8 = 2.048 MHz
- * Sample Rate = DMCLK/2048 = 8 KHz
- */
- ctrl_regs[0] = AD_CONTROL | AD_WRITE | CTRL_REG_B | REGB_MCDIV(0) | \
- REGB_SCDIV(0) | REGB_DIRATE(0);
- ctrl_regs[1] = AD_CONTROL | AD_WRITE | CTRL_REG_C | REGC_PUDEV | \
- REGC_PUADC | REGC_PUDAC | REGC_PUREF | REGC_REFUSE ;
- ctrl_regs[2] = AD_CONTROL | AD_WRITE | CTRL_REG_D | REGD_OGS(2) | \
- REGD_IGS(2);
- ctrl_regs[3] = AD_CONTROL | AD_WRITE | CTRL_REG_E | REGE_DA(0x1f);
- ctrl_regs[4] = AD_CONTROL | AD_WRITE | CTRL_REG_F | REGF_SEEN ;
- ctrl_regs[5] = AD_CONTROL | AD_WRITE | CTRL_REG_A | REGA_MODE_DATA;
-
- local_irq_disable();
- snd_ad73311_startup();
- udelay(1);
-
- bfin_write_SPORT_TCR1(TFSR);
- bfin_write_SPORT_TCR2(0xF);
- SSYNC();
-
- /* SPORT Tx Register is a 8 x 16 FIFO, all the data can be put to
- * FIFO before enable SPORT to transfer the data
- */
- for (count = 0; count < 6; count++)
- bfin_write_SPORT_TX16(ctrl_regs[count]);
- SSYNC();
- bfin_write_SPORT_TCR1(bfin_read_SPORT_TCR1() | TSPEN);
- SSYNC();
-
- /* When TUVF is set, the data is already send out */
- while (!(status & TUVF) && ++count < 10000) {
- udelay(1);
- status = bfin_read_SPORT_STAT();
- SSYNC();
- }
- bfin_write_SPORT_TCR1(bfin_read_SPORT_TCR1() & ~TSPEN);
- SSYNC();
- local_irq_enable();
-
- if (count >= 10000) {
- printk(KERN_ERR "ad73311: failed to configure codec\n");
- return -1;
- }
- return 0;
-}
-
-static int bf5xx_probe(struct snd_soc_card *card)
-{
- int err;
- if (gpio_request(GPIO_SE, "AD73311_SE")) {
- printk(KERN_ERR "%s: Failed ro request GPIO_%d\n", __func__, GPIO_SE);
- return -EBUSY;
- }
-
- gpio_direction_output(GPIO_SE, 0);
-
- err = snd_ad73311_configure();
- if (err < 0)
- return -EFAULT;
-
- return 0;
-}
-
-#define BF5XX_AD7311_DAI_FMT (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF | \
- SND_SOC_DAIFMT_CBM_CFM)
-
-static struct snd_soc_dai_link bf5xx_ad73311_dai[] = {
- {
- .name = "ad73311",
- .stream_name = "AD73311",
- .cpu_dai_name = "bfin-i2s.0",
- .codec_dai_name = "ad73311-hifi",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "ad73311",
- .dai_fmt = BF5XX_AD7311_DAI_FMT,
- },
- {
- .name = "ad73311",
- .stream_name = "AD73311",
- .cpu_dai_name = "bfin-i2s.1",
- .codec_dai_name = "ad73311-hifi",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "ad73311",
- .dai_fmt = BF5XX_AD7311_DAI_FMT,
- },
-};
-
-static struct snd_soc_card bf5xx_ad73311 = {
- .name = "bfin-ad73311",
- .owner = THIS_MODULE,
- .probe = bf5xx_probe,
- .dai_link = &bf5xx_ad73311_dai[CONFIG_SND_BF5XX_SPORT_NUM],
- .num_links = 1,
-};
-
-static struct platform_device *bf5xx_ad73311_snd_device;
-
-static int __init bf5xx_ad73311_init(void)
-{
- int ret;
-
- pr_debug("%s enter\n", __func__);
- bf5xx_ad73311_snd_device = platform_device_alloc("soc-audio", -1);
- if (!bf5xx_ad73311_snd_device)
- return -ENOMEM;
-
- platform_set_drvdata(bf5xx_ad73311_snd_device, &bf5xx_ad73311);
- ret = platform_device_add(bf5xx_ad73311_snd_device);
-
- if (ret)
- platform_device_put(bf5xx_ad73311_snd_device);
-
- return ret;
-}
-
-static void __exit bf5xx_ad73311_exit(void)
-{
- pr_debug("%s enter\n", __func__);
- platform_device_unregister(bf5xx_ad73311_snd_device);
-}
-
-module_init(bf5xx_ad73311_init);
-module_exit(bf5xx_ad73311_exit);
-
-/* Module information */
-MODULE_AUTHOR("Cliff Cai");
-MODULE_DESCRIPTION("ALSA SoC AD73311 Blackfin");
-MODULE_LICENSE("GPL");
-
diff --git a/sound/soc/blackfin/bf5xx-i2s-pcm.c b/sound/soc/blackfin/bf5xx-i2s-pcm.c
deleted file mode 100644
index 51cae76..0000000
--- a/sound/soc/blackfin/bf5xx-i2s-pcm.c
+++ /dev/null
@@ -1,373 +0,0 @@
-/*
- * File: sound/soc/blackfin/bf5xx-i2s-pcm.c
- * Author: Cliff Cai <Cliff.Cai@analog.com>
- *
- * Created: Tue June 06 2008
- * Description: DMA driver for i2s codec
- *
- * Modified:
- * Copyright 2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gfp.h>
-
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/pcm_params.h>
-#include <sound/soc.h>
-
-#include <asm/dma.h>
-
-#include "bf5xx-sport.h"
-#include "bf5xx-i2s-pcm.h"
-
-static void bf5xx_dma_irq(void *data)
-{
- struct snd_pcm_substream *pcm = data;
- snd_pcm_period_elapsed(pcm);
-}
-
-static const struct snd_pcm_hardware bf5xx_pcm_hardware = {
- .info = SNDRV_PCM_INFO_INTERLEAVED |
- SNDRV_PCM_INFO_MMAP_VALID |
- SNDRV_PCM_INFO_BLOCK_TRANSFER,
- .period_bytes_min = 32,
- .period_bytes_max = 0x10000,
- .periods_min = 1,
- .periods_max = PAGE_SIZE/32,
- .buffer_bytes_max = 0x20000, /* 128 kbytes */
- .fifo_size = 16,
-};
-
-static int bf5xx_pcm_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- unsigned int buffer_size = params_buffer_bytes(params);
- struct bf5xx_i2s_pcm_data *dma_data;
-
- dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
-
- if (dma_data->tdm_mode)
- buffer_size = buffer_size / params_channels(params) * 8;
-
- return snd_pcm_lib_malloc_pages(substream, buffer_size);
-}
-
-static int bf5xx_pcm_hw_free(struct snd_pcm_substream *substream)
-{
- snd_pcm_lib_free_pages(substream);
-
- return 0;
-}
-
-static int bf5xx_pcm_prepare(struct snd_pcm_substream *substream)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_pcm_runtime *runtime = substream->runtime;
- struct sport_device *sport = runtime->private_data;
- int period_bytes = frames_to_bytes(runtime, runtime->period_size);
- struct bf5xx_i2s_pcm_data *dma_data;
-
- dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
-
- if (dma_data->tdm_mode)
- period_bytes = period_bytes / runtime->channels * 8;
-
- pr_debug("%s enter\n", __func__);
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- sport_set_tx_callback(sport, bf5xx_dma_irq, substream);
- sport_config_tx_dma(sport, runtime->dma_area,
- runtime->periods, period_bytes);
- } else {
- sport_set_rx_callback(sport, bf5xx_dma_irq, substream);
- sport_config_rx_dma(sport, runtime->dma_area,
- runtime->periods, period_bytes);
- }
-
- return 0;
-}
-
-static int bf5xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
-{
- struct snd_pcm_runtime *runtime = substream->runtime;
- struct sport_device *sport = runtime->private_data;
- int ret = 0;
-
- pr_debug("%s enter\n", __func__);
- switch (cmd) {
- case SNDRV_PCM_TRIGGER_START:
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- sport_tx_start(sport);
- else
- sport_rx_start(sport);
- break;
- case SNDRV_PCM_TRIGGER_STOP:
- case SNDRV_PCM_TRIGGER_SUSPEND:
- case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- sport_tx_stop(sport);
- else
- sport_rx_stop(sport);
- break;
- default:
- ret = -EINVAL;
- }
-
- return ret;
-}
-
-static snd_pcm_uframes_t bf5xx_pcm_pointer(struct snd_pcm_substream *substream)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_pcm_runtime *runtime = substream->runtime;
- struct sport_device *sport = runtime->private_data;
- unsigned int diff;
- snd_pcm_uframes_t frames;
- struct bf5xx_i2s_pcm_data *dma_data;
-
- dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
-
- pr_debug("%s enter\n", __func__);
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- diff = sport_curr_offset_tx(sport);
- } else {
- diff = sport_curr_offset_rx(sport);
- }
-
- /*
- * TX at least can report one frame beyond the end of the
- * buffer if we hit the wraparound case - clamp to within the
- * buffer as the ALSA APIs require.
- */
- if (diff == snd_pcm_lib_buffer_bytes(substream))
- diff = 0;
-
- frames = bytes_to_frames(substream->runtime, diff);
- if (dma_data->tdm_mode)
- frames = frames * runtime->channels / 8;
-
- return frames;
-}
-
-static int bf5xx_pcm_open(struct snd_pcm_substream *substream)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(cpu_dai);
- struct snd_pcm_runtime *runtime = substream->runtime;
- struct snd_dma_buffer *buf = &substream->dma_buffer;
- struct bf5xx_i2s_pcm_data *dma_data;
- int ret;
-
- dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
-
- pr_debug("%s enter\n", __func__);
-
- snd_soc_set_runtime_hwparams(substream, &bf5xx_pcm_hardware);
- if (dma_data->tdm_mode)
- runtime->hw.buffer_bytes_max /= 4;
- else
- runtime->hw.info |= SNDRV_PCM_INFO_MMAP;
-
- ret = snd_pcm_hw_constraint_integer(runtime,
- SNDRV_PCM_HW_PARAM_PERIODS);
- if (ret < 0)
- goto out;
-
- if (sport_handle != NULL) {
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- sport_handle->tx_buf = buf->area;
- else
- sport_handle->rx_buf = buf->area;
-
- runtime->private_data = sport_handle;
- } else {
- pr_err("sport_handle is NULL\n");
- return -1;
- }
- return 0;
-
- out:
- return ret;
-}
-
-static int bf5xx_pcm_mmap(struct snd_pcm_substream *substream,
- struct vm_area_struct *vma)
-{
- struct snd_pcm_runtime *runtime = substream->runtime;
- size_t size = vma->vm_end - vma->vm_start;
- vma->vm_start = (unsigned long)runtime->dma_area;
- vma->vm_end = vma->vm_start + size;
- vma->vm_flags |= VM_SHARED;
-
- return 0 ;
-}
-
-static int bf5xx_pcm_copy(struct snd_pcm_substream *substream,
- int channel, unsigned long pos,
- void *buf, unsigned long count)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_pcm_runtime *runtime = substream->runtime;
- unsigned int sample_size = runtime->sample_bits / 8;
- struct bf5xx_i2s_pcm_data *dma_data;
- unsigned int i;
- void *src, *dst;
-
- dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
-
- if (dma_data->tdm_mode) {
- pos = bytes_to_frames(runtime, pos);
- count = bytes_to_frames(runtime, count);
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- src = buf;
- dst = runtime->dma_area;
- dst += pos * sample_size * 8;
-
- while (count--) {
- for (i = 0; i < runtime->channels; i++) {
- memcpy(dst + dma_data->map[i] *
- sample_size, src, sample_size);
- src += sample_size;
- }
- dst += 8 * sample_size;
- }
- } else {
- src = runtime->dma_area;
- src += pos * sample_size * 8;
- dst = buf;
-
- while (count--) {
- for (i = 0; i < runtime->channels; i++) {
- memcpy(dst, src + dma_data->map[i] *
- sample_size, sample_size);
- dst += sample_size;
- }
- src += 8 * sample_size;
- }
- }
- } else {
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- src = buf;
- dst = runtime->dma_area;
- dst += pos;
- } else {
- src = runtime->dma_area;
- src += pos;
- dst = buf;
- }
-
- memcpy(dst, src, count);
- }
-
- return 0;
-}
-
-static int bf5xx_pcm_copy_user(struct snd_pcm_substream *substream,
- int channel, unsigned long pos,
- void __user *buf, unsigned long count)
-{
- return bf5xx_pcm_copy(substream, channel, pos, (void *)buf, count);
-}
-
-static int bf5xx_pcm_silence(struct snd_pcm_substream *substream,
- int channel, unsigned long pos,
- unsigned long count)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_pcm_runtime *runtime = substream->runtime;
- unsigned int sample_size = runtime->sample_bits / 8;
- void *buf = runtime->dma_area;
- struct bf5xx_i2s_pcm_data *dma_data;
- unsigned int offset, samples;
-
- dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
-
- if (dma_data->tdm_mode) {
- offset = bytes_to_frames(runtime, pos) * 8 * sample_size;
- samples = bytes_to_frames(runtime, count) * 8;
- } else {
- offset = pos;
- samples = bytes_to_samples(runtime, count);
- }
-
- snd_pcm_format_set_silence(runtime->format, buf + offset, samples);
-
- return 0;
-}
-
-static const struct snd_pcm_ops bf5xx_pcm_i2s_ops = {
- .open = bf5xx_pcm_open,
- .ioctl = snd_pcm_lib_ioctl,
- .hw_params = bf5xx_pcm_hw_params,
- .hw_free = bf5xx_pcm_hw_free,
- .prepare = bf5xx_pcm_prepare,
- .trigger = bf5xx_pcm_trigger,
- .pointer = bf5xx_pcm_pointer,
- .mmap = bf5xx_pcm_mmap,
- .copy_user = bf5xx_pcm_copy_user,
- .copy_kernel = bf5xx_pcm_copy,
- .fill_silence = bf5xx_pcm_silence,
-};
-
-static int bf5xx_pcm_i2s_new(struct snd_soc_pcm_runtime *rtd)
-{
- struct snd_card *card = rtd->card->snd_card;
- size_t size = bf5xx_pcm_hardware.buffer_bytes_max;
- int ret;
-
- pr_debug("%s enter\n", __func__);
- ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
- if (ret)
- return ret;
-
- return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
- SNDRV_DMA_TYPE_DEV, card->dev, size, size);
-}
-
-static struct snd_soc_platform_driver bf5xx_i2s_soc_platform = {
- .ops = &bf5xx_pcm_i2s_ops,
- .pcm_new = bf5xx_pcm_i2s_new,
-};
-
-static int bfin_i2s_soc_platform_probe(struct platform_device *pdev)
-{
- return devm_snd_soc_register_platform(&pdev->dev,
- &bf5xx_i2s_soc_platform);
-}
-
-static struct platform_driver bfin_i2s_pcm_driver = {
- .driver = {
- .name = "bfin-i2s-pcm-audio",
- },
-
- .probe = bfin_i2s_soc_platform_probe,
-};
-
-module_platform_driver(bfin_i2s_pcm_driver);
-
-MODULE_AUTHOR("Cliff Cai");
-MODULE_DESCRIPTION("ADI Blackfin I2S PCM DMA module");
-MODULE_LICENSE("GPL");
diff --git a/sound/soc/blackfin/bf5xx-i2s-pcm.h b/sound/soc/blackfin/bf5xx-i2s-pcm.h
deleted file mode 100644
index 1f04352..0000000
--- a/sound/soc/blackfin/bf5xx-i2s-pcm.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _BF5XX_TDM_PCM_H
-#define _BF5XX_TDM_PCM_H
-
-#define BFIN_TDM_DAI_MAX_SLOTS 8
-
-struct bf5xx_i2s_pcm_data {
- unsigned int map[BFIN_TDM_DAI_MAX_SLOTS];
- bool tdm_mode;
-};
-
-#endif
diff --git a/sound/soc/blackfin/bf5xx-i2s.c b/sound/soc/blackfin/bf5xx-i2s.c
deleted file mode 100644
index b69aeef..0000000
--- a/sound/soc/blackfin/bf5xx-i2s.c
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
- * File: sound/soc/blackfin/bf5xx-i2s.c
- * Author: Cliff Cai <Cliff.Cai@analog.com>
- *
- * Created: Tue June 06 2008
- * Description: Blackfin I2S CPU DAI driver
- *
- * Modified:
- * Copyright 2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/pcm_params.h>
-#include <sound/initval.h>
-#include <sound/soc.h>
-
-#include <asm/irq.h>
-#include <asm/portmux.h>
-#include <linux/mutex.h>
-#include <linux/gpio.h>
-
-#include "bf5xx-sport.h"
-#include "bf5xx-i2s-pcm.h"
-
-struct bf5xx_i2s_port {
- u16 tcr1;
- u16 rcr1;
- u16 tcr2;
- u16 rcr2;
- int configured;
-
- unsigned int slots;
- unsigned int tx_mask;
- unsigned int rx_mask;
-
- struct bf5xx_i2s_pcm_data tx_dma_data;
- struct bf5xx_i2s_pcm_data rx_dma_data;
-};
-
-static int bf5xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
- unsigned int fmt)
-{
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(cpu_dai);
- struct bf5xx_i2s_port *bf5xx_i2s = sport_handle->private_data;
- int ret = 0;
-
- /* interface format:support I2S,slave mode */
- switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
- case SND_SOC_DAIFMT_I2S:
- bf5xx_i2s->tcr1 |= TFSR | TCKFE;
- bf5xx_i2s->rcr1 |= RFSR | RCKFE;
- bf5xx_i2s->tcr2 |= TSFSE;
- bf5xx_i2s->rcr2 |= RSFSE;
- break;
- case SND_SOC_DAIFMT_DSP_A:
- bf5xx_i2s->tcr1 |= TFSR;
- bf5xx_i2s->rcr1 |= RFSR;
- break;
- case SND_SOC_DAIFMT_LEFT_J:
- ret = -EINVAL;
- break;
- default:
- dev_err(cpu_dai->dev, "%s: Unknown DAI format type\n",
- __func__);
- ret = -EINVAL;
- break;
- }
-
- switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
- case SND_SOC_DAIFMT_CBM_CFM:
- break;
- case SND_SOC_DAIFMT_CBS_CFS:
- case SND_SOC_DAIFMT_CBM_CFS:
- case SND_SOC_DAIFMT_CBS_CFM:
- ret = -EINVAL;
- break;
- default:
- dev_err(cpu_dai->dev, "%s: Unknown DAI master type\n",
- __func__);
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-static int bf5xx_i2s_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params,
- struct snd_soc_dai *dai)
-{
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(dai);
- struct bf5xx_i2s_port *bf5xx_i2s = sport_handle->private_data;
- int ret = 0;
-
- bf5xx_i2s->tcr2 &= ~0x1f;
- bf5xx_i2s->rcr2 &= ~0x1f;
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S8:
- bf5xx_i2s->tcr2 |= 7;
- bf5xx_i2s->rcr2 |= 7;
- sport_handle->wdsize = 1;
- break;
- case SNDRV_PCM_FORMAT_S16_LE:
- bf5xx_i2s->tcr2 |= 15;
- bf5xx_i2s->rcr2 |= 15;
- sport_handle->wdsize = 2;
- break;
- case SNDRV_PCM_FORMAT_S24_LE:
- bf5xx_i2s->tcr2 |= 23;
- bf5xx_i2s->rcr2 |= 23;
- sport_handle->wdsize = 3;
- break;
- case SNDRV_PCM_FORMAT_S32_LE:
- bf5xx_i2s->tcr2 |= 31;
- bf5xx_i2s->rcr2 |= 31;
- sport_handle->wdsize = 4;
- break;
- }
-
- if (!bf5xx_i2s->configured) {
- /*
- * TX and RX are not independent,they are enabled at the
- * same time, even if only one side is running. So, we
- * need to configure both of them at the time when the first
- * stream is opened.
- *
- * CPU DAI:slave mode.
- */
- bf5xx_i2s->configured = 1;
- ret = sport_config_rx(sport_handle, bf5xx_i2s->rcr1,
- bf5xx_i2s->rcr2, 0, 0);
- if (ret) {
- dev_err(dai->dev, "SPORT is busy!\n");
- return -EBUSY;
- }
-
- ret = sport_config_tx(sport_handle, bf5xx_i2s->tcr1,
- bf5xx_i2s->tcr2, 0, 0);
- if (ret) {
- dev_err(dai->dev, "SPORT is busy!\n");
- return -EBUSY;
- }
- }
-
- return 0;
-}
-
-static void bf5xx_i2s_shutdown(struct snd_pcm_substream *substream,
- struct snd_soc_dai *dai)
-{
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(dai);
- struct bf5xx_i2s_port *bf5xx_i2s = sport_handle->private_data;
-
- dev_dbg(dai->dev, "%s enter\n", __func__);
- /* No active stream, SPORT is allowed to be configured again. */
- if (!dai->active)
- bf5xx_i2s->configured = 0;
-}
-
-static int bf5xx_i2s_set_channel_map(struct snd_soc_dai *dai,
- unsigned int tx_num, unsigned int *tx_slot,
- unsigned int rx_num, unsigned int *rx_slot)
-{
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(dai);
- struct bf5xx_i2s_port *bf5xx_i2s = sport_handle->private_data;
- unsigned int tx_mapped = 0, rx_mapped = 0;
- unsigned int slot;
- int i;
-
- if ((tx_num > BFIN_TDM_DAI_MAX_SLOTS) ||
- (rx_num > BFIN_TDM_DAI_MAX_SLOTS))
- return -EINVAL;
-
- for (i = 0; i < tx_num; i++) {
- slot = tx_slot[i];
- if ((slot < BFIN_TDM_DAI_MAX_SLOTS) &&
- (!(tx_mapped & (1 << slot)))) {
- bf5xx_i2s->tx_dma_data.map[i] = slot;
- tx_mapped |= 1 << slot;
- } else
- return -EINVAL;
- }
- for (i = 0; i < rx_num; i++) {
- slot = rx_slot[i];
- if ((slot < BFIN_TDM_DAI_MAX_SLOTS) &&
- (!(rx_mapped & (1 << slot)))) {
- bf5xx_i2s->rx_dma_data.map[i] = slot;
- rx_mapped |= 1 << slot;
- } else
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int bf5xx_i2s_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
- unsigned int rx_mask, int slots, int width)
-{
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(dai);
- struct bf5xx_i2s_port *bf5xx_i2s = sport_handle->private_data;
-
- if (slots % 8 != 0 || slots > 8)
- return -EINVAL;
-
- if (width != 32)
- return -EINVAL;
-
- bf5xx_i2s->slots = slots;
- bf5xx_i2s->tx_mask = tx_mask;
- bf5xx_i2s->rx_mask = rx_mask;
-
- bf5xx_i2s->tx_dma_data.tdm_mode = slots != 0;
- bf5xx_i2s->rx_dma_data.tdm_mode = slots != 0;
-
- return sport_set_multichannel(sport_handle, slots, tx_mask, rx_mask, 0);
-}
-
-#ifdef CONFIG_PM
-static int bf5xx_i2s_suspend(struct snd_soc_dai *dai)
-{
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(dai);
-
- dev_dbg(dai->dev, "%s : sport %d\n", __func__, dai->id);
-
- if (dai->capture_active)
- sport_rx_stop(sport_handle);
- if (dai->playback_active)
- sport_tx_stop(sport_handle);
- return 0;
-}
-
-static int bf5xx_i2s_resume(struct snd_soc_dai *dai)
-{
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(dai);
- struct bf5xx_i2s_port *bf5xx_i2s = sport_handle->private_data;
- int ret;
-
- dev_dbg(dai->dev, "%s : sport %d\n", __func__, dai->id);
-
- ret = sport_config_rx(sport_handle, bf5xx_i2s->rcr1,
- bf5xx_i2s->rcr2, 0, 0);
- if (ret) {
- dev_err(dai->dev, "SPORT is busy!\n");
- return -EBUSY;
- }
-
- ret = sport_config_tx(sport_handle, bf5xx_i2s->tcr1,
- bf5xx_i2s->tcr2, 0, 0);
- if (ret) {
- dev_err(dai->dev, "SPORT is busy!\n");
- return -EBUSY;
- }
-
- return sport_set_multichannel(sport_handle, bf5xx_i2s->slots,
- bf5xx_i2s->tx_mask, bf5xx_i2s->rx_mask, 0);
-}
-
-#else
-#define bf5xx_i2s_suspend NULL
-#define bf5xx_i2s_resume NULL
-#endif
-
-static int bf5xx_i2s_dai_probe(struct snd_soc_dai *dai)
-{
- struct sport_device *sport_handle = snd_soc_dai_get_drvdata(dai);
- struct bf5xx_i2s_port *bf5xx_i2s = sport_handle->private_data;
- unsigned int i;
-
- for (i = 0; i < BFIN_TDM_DAI_MAX_SLOTS; i++) {
- bf5xx_i2s->tx_dma_data.map[i] = i;
- bf5xx_i2s->rx_dma_data.map[i] = i;
- }
-
- dai->playback_dma_data = &bf5xx_i2s->tx_dma_data;
- dai->capture_dma_data = &bf5xx_i2s->rx_dma_data;
-
- return 0;
-}
-
-#define BF5XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
- SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
- SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
- SNDRV_PCM_RATE_96000)
-
-#define BF5XX_I2S_FORMATS \
- (SNDRV_PCM_FMTBIT_S8 | \
- SNDRV_PCM_FMTBIT_S16_LE | \
- SNDRV_PCM_FMTBIT_S24_LE | \
- SNDRV_PCM_FMTBIT_S32_LE)
-
-static const struct snd_soc_dai_ops bf5xx_i2s_dai_ops = {
- .shutdown = bf5xx_i2s_shutdown,
- .hw_params = bf5xx_i2s_hw_params,
- .set_fmt = bf5xx_i2s_set_dai_fmt,
- .set_tdm_slot = bf5xx_i2s_set_tdm_slot,
- .set_channel_map = bf5xx_i2s_set_channel_map,
-};
-
-static struct snd_soc_dai_driver bf5xx_i2s_dai = {
- .probe = bf5xx_i2s_dai_probe,
- .suspend = bf5xx_i2s_suspend,
- .resume = bf5xx_i2s_resume,
- .playback = {
- .channels_min = 2,
- .channels_max = 8,
- .rates = BF5XX_I2S_RATES,
- .formats = BF5XX_I2S_FORMATS,},
- .capture = {
- .channels_min = 2,
- .channels_max = 8,
- .rates = BF5XX_I2S_RATES,
- .formats = BF5XX_I2S_FORMATS,},
- .ops = &bf5xx_i2s_dai_ops,
-};
-
-static const struct snd_soc_component_driver bf5xx_i2s_component = {
- .name = "bf5xx-i2s",
-};
-
-static int bf5xx_i2s_probe(struct platform_device *pdev)
-{
- struct sport_device *sport_handle;
- int ret;
-
- /* configure SPORT for I2S */
- sport_handle = sport_init(pdev, 4, 8 * sizeof(u32),
- sizeof(struct bf5xx_i2s_port));
- if (!sport_handle)
- return -ENODEV;
-
- /* register with the ASoC layers */
- ret = snd_soc_register_component(&pdev->dev, &bf5xx_i2s_component,
- &bf5xx_i2s_dai, 1);
- if (ret) {
- dev_err(&pdev->dev, "Failed to register DAI: %d\n", ret);
- sport_done(sport_handle);
- return ret;
- }
-
- return 0;
-}
-
-static int bf5xx_i2s_remove(struct platform_device *pdev)
-{
- struct sport_device *sport_handle = platform_get_drvdata(pdev);
-
- dev_dbg(&pdev->dev, "%s enter\n", __func__);
-
- snd_soc_unregister_component(&pdev->dev);
- sport_done(sport_handle);
-
- return 0;
-}
-
-static struct platform_driver bfin_i2s_driver = {
- .probe = bf5xx_i2s_probe,
- .remove = bf5xx_i2s_remove,
- .driver = {
- .name = "bfin-i2s",
- },
-};
-
-module_platform_driver(bfin_i2s_driver);
-
-/* Module information */
-MODULE_AUTHOR("Cliff Cai");
-MODULE_DESCRIPTION("I2S driver for ADI Blackfin");
-MODULE_LICENSE("GPL");
-
diff --git a/sound/soc/blackfin/bf5xx-sport.c b/sound/soc/blackfin/bf5xx-sport.c
deleted file mode 100644
index 9dfa124..0000000
--- a/sound/soc/blackfin/bf5xx-sport.c
+++ /dev/null
@@ -1,1102 +0,0 @@
-/*
- * File: bf5xx_sport.c
- * Based on:
- * Author: Roy Huang <roy.huang@analog.com>
- *
- * Created: Tue Sep 21 10:52:42 CEST 2004
- * Description:
- * Blackfin SPORT Driver
- *
- * Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/bug.h>
-#include <linux/module.h>
-#include <asm/portmux.h>
-#include <asm/dma.h>
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-
-#include "bf5xx-sport.h"
-/* delay between frame sync pulse and first data bit in multichannel mode */
-#define FRAME_DELAY (1<<12)
-
-/* note: multichannel is in units of 8 channels,
- * tdm_count is # channels NOT / 8 ! */
-int sport_set_multichannel(struct sport_device *sport,
- int tdm_count, u32 tx_mask, u32 rx_mask, int packed)
-{
- pr_debug("%s tdm_count=%d tx_mask:0x%08x rx_mask:0x%08x packed=%d\n",
- __func__, tdm_count, tx_mask, rx_mask, packed);
-
- if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
- return -EBUSY;
-
- if (tdm_count & 0x7)
- return -EINVAL;
-
- if (tdm_count > 32)
- return -EINVAL; /* Only support less than 32 channels now */
-
- if (tdm_count) {
- sport->regs->mcmc1 = ((tdm_count>>3)-1) << 12;
- sport->regs->mcmc2 = FRAME_DELAY | MCMEN | \
- (packed ? (MCDTXPE|MCDRXPE) : 0);
-
- sport->regs->mtcs0 = tx_mask;
- sport->regs->mrcs0 = rx_mask;
- sport->regs->mtcs1 = 0;
- sport->regs->mrcs1 = 0;
- sport->regs->mtcs2 = 0;
- sport->regs->mrcs2 = 0;
- sport->regs->mtcs3 = 0;
- sport->regs->mrcs3 = 0;
- } else {
- sport->regs->mcmc1 = 0;
- sport->regs->mcmc2 = 0;
-
- sport->regs->mtcs0 = 0;
- sport->regs->mrcs0 = 0;
- }
-
- sport->regs->mtcs1 = 0; sport->regs->mtcs2 = 0; sport->regs->mtcs3 = 0;
- sport->regs->mrcs1 = 0; sport->regs->mrcs2 = 0; sport->regs->mrcs3 = 0;
-
- SSYNC();
-
- return 0;
-}
-EXPORT_SYMBOL(sport_set_multichannel);
-
-int sport_config_rx(struct sport_device *sport, unsigned int rcr1,
- unsigned int rcr2, unsigned int clkdiv, unsigned int fsdiv)
-{
- if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
- return -EBUSY;
-
- sport->regs->rcr1 = rcr1;
- sport->regs->rcr2 = rcr2;
- sport->regs->rclkdiv = clkdiv;
- sport->regs->rfsdiv = fsdiv;
-
- SSYNC();
-
- return 0;
-}
-EXPORT_SYMBOL(sport_config_rx);
-
-int sport_config_tx(struct sport_device *sport, unsigned int tcr1,
- unsigned int tcr2, unsigned int clkdiv, unsigned int fsdiv)
-{
- if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
- return -EBUSY;
-
- sport->regs->tcr1 = tcr1;
- sport->regs->tcr2 = tcr2;
- sport->regs->tclkdiv = clkdiv;
- sport->regs->tfsdiv = fsdiv;
-
- SSYNC();
-
- return 0;
-}
-EXPORT_SYMBOL(sport_config_tx);
-
-static void setup_desc(struct dmasg *desc, void *buf, int fragcount,
- size_t fragsize, unsigned int cfg,
- unsigned int x_count, unsigned int ycount, size_t wdsize)
-{
-
- int i;
-
- for (i = 0; i < fragcount; ++i) {
- desc[i].next_desc_addr = &(desc[i + 1]);
- desc[i].start_addr = (unsigned long)buf + i*fragsize;
- desc[i].cfg = cfg;
- desc[i].x_count = x_count;
- desc[i].x_modify = wdsize;
- desc[i].y_count = ycount;
- desc[i].y_modify = wdsize;
- }
-
- /* make circular */
- desc[fragcount-1].next_desc_addr = desc;
-
- pr_debug("setup desc: desc0=%p, next0=%p, desc1=%p,"
- "next1=%p\nx_count=%x,y_count=%x,addr=0x%lx,cfs=0x%x\n",
- desc, desc[0].next_desc_addr,
- desc+1, desc[1].next_desc_addr,
- desc[0].x_count, desc[0].y_count,
- desc[0].start_addr, desc[0].cfg);
-}
-
-static int sport_start(struct sport_device *sport)
-{
- enable_dma(sport->dma_rx_chan);
- enable_dma(sport->dma_tx_chan);
- sport->regs->rcr1 |= RSPEN;
- sport->regs->tcr1 |= TSPEN;
- SSYNC();
-
- return 0;
-}
-
-static int sport_stop(struct sport_device *sport)
-{
- sport->regs->tcr1 &= ~TSPEN;
- sport->regs->rcr1 &= ~RSPEN;
- SSYNC();
-
- disable_dma(sport->dma_rx_chan);
- disable_dma(sport->dma_tx_chan);
- return 0;
-}
-
-static inline int sport_hook_rx_dummy(struct sport_device *sport)
-{
- struct dmasg *desc, temp_desc;
- unsigned long flags;
-
- if (WARN_ON(!sport->dummy_rx_desc) ||
- WARN_ON(sport->curr_rx_desc == sport->dummy_rx_desc))
- return -EINVAL;
-
- /* Maybe the dummy buffer descriptor ring is damaged */
- sport->dummy_rx_desc->next_desc_addr = sport->dummy_rx_desc + 1;
-
- local_irq_save(flags);
- desc = get_dma_next_desc_ptr(sport->dma_rx_chan);
- /* Copy the descriptor which will be damaged to backup */
- temp_desc = *desc;
- desc->x_count = sport->dummy_count / 2;
- desc->y_count = 0;
- desc->next_desc_addr = sport->dummy_rx_desc;
- local_irq_restore(flags);
- /* Waiting for dummy buffer descriptor is already hooked*/
- while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) -
- sizeof(struct dmasg)) != sport->dummy_rx_desc)
- continue;
- sport->curr_rx_desc = sport->dummy_rx_desc;
- /* Restore the damaged descriptor */
- *desc = temp_desc;
-
- return 0;
-}
-
-static inline int sport_rx_dma_start(struct sport_device *sport, int dummy)
-{
- if (dummy) {
- sport->dummy_rx_desc->next_desc_addr = sport->dummy_rx_desc;
- sport->curr_rx_desc = sport->dummy_rx_desc;
- } else
- sport->curr_rx_desc = sport->dma_rx_desc;
-
- set_dma_next_desc_addr(sport->dma_rx_chan, sport->curr_rx_desc);
- set_dma_x_count(sport->dma_rx_chan, 0);
- set_dma_x_modify(sport->dma_rx_chan, 0);
- set_dma_config(sport->dma_rx_chan, (DMAFLOW_LARGE | NDSIZE_9 | \
- WDSIZE_32 | WNR));
- set_dma_curr_addr(sport->dma_rx_chan, sport->curr_rx_desc->start_addr);
- SSYNC();
-
- return 0;
-}
-
-static inline int sport_tx_dma_start(struct sport_device *sport, int dummy)
-{
- if (dummy) {
- sport->dummy_tx_desc->next_desc_addr = sport->dummy_tx_desc;
- sport->curr_tx_desc = sport->dummy_tx_desc;
- } else
- sport->curr_tx_desc = sport->dma_tx_desc;
-
- set_dma_next_desc_addr(sport->dma_tx_chan, sport->curr_tx_desc);
- set_dma_x_count(sport->dma_tx_chan, 0);
- set_dma_x_modify(sport->dma_tx_chan, 0);
- set_dma_config(sport->dma_tx_chan,
- (DMAFLOW_LARGE | NDSIZE_9 | WDSIZE_32));
- set_dma_curr_addr(sport->dma_tx_chan, sport->curr_tx_desc->start_addr);
- SSYNC();
-
- return 0;
-}
-
-int sport_rx_start(struct sport_device *sport)
-{
- unsigned long flags;
- pr_debug("%s enter\n", __func__);
- if (sport->rx_run)
- return -EBUSY;
- if (sport->tx_run) {
- /* tx is running, rx is not running */
- if (WARN_ON(!sport->dma_rx_desc) ||
- WARN_ON(sport->curr_rx_desc != sport->dummy_rx_desc))
- return -EINVAL;
- local_irq_save(flags);
- while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) -
- sizeof(struct dmasg)) != sport->dummy_rx_desc)
- continue;
- sport->dummy_rx_desc->next_desc_addr = sport->dma_rx_desc;
- local_irq_restore(flags);
- sport->curr_rx_desc = sport->dma_rx_desc;
- } else {
- sport_tx_dma_start(sport, 1);
- sport_rx_dma_start(sport, 0);
- sport_start(sport);
- }
-
- sport->rx_run = 1;
-
- return 0;
-}
-EXPORT_SYMBOL(sport_rx_start);
-
-int sport_rx_stop(struct sport_device *sport)
-{
- pr_debug("%s enter\n", __func__);
-
- if (!sport->rx_run)
- return 0;
- if (sport->tx_run) {
- /* TX dma is still running, hook the dummy buffer */
- sport_hook_rx_dummy(sport);
- } else {
- /* Both rx and tx dma will be stopped */
- sport_stop(sport);
- sport->curr_rx_desc = NULL;
- sport->curr_tx_desc = NULL;
- }
-
- sport->rx_run = 0;
-
- return 0;
-}
-EXPORT_SYMBOL(sport_rx_stop);
-
-static inline int sport_hook_tx_dummy(struct sport_device *sport)
-{
- struct dmasg *desc, temp_desc;
- unsigned long flags;
-
- if (WARN_ON(!sport->dummy_tx_desc) ||
- WARN_ON(sport->curr_tx_desc == sport->dummy_tx_desc))
- return -EINVAL;
-
- sport->dummy_tx_desc->next_desc_addr = sport->dummy_tx_desc + 1;
-
- /* Shorten the time on last normal descriptor */
- local_irq_save(flags);
- desc = get_dma_next_desc_ptr(sport->dma_tx_chan);
- /* Store the descriptor which will be damaged */
- temp_desc = *desc;
- desc->x_count = sport->dummy_count / 2;
- desc->y_count = 0;
- desc->next_desc_addr = sport->dummy_tx_desc;
- local_irq_restore(flags);
- /* Waiting for dummy buffer descriptor is already hooked*/
- while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) - \
- sizeof(struct dmasg)) != sport->dummy_tx_desc)
- continue;
- sport->curr_tx_desc = sport->dummy_tx_desc;
- /* Restore the damaged descriptor */
- *desc = temp_desc;
-
- return 0;
-}
-
-int sport_tx_start(struct sport_device *sport)
-{
- unsigned long flags;
- pr_debug("%s: tx_run:%d, rx_run:%d\n", __func__,
- sport->tx_run, sport->rx_run);
- if (sport->tx_run)
- return -EBUSY;
- if (sport->rx_run) {
- if (WARN_ON(!sport->dma_tx_desc) ||
- WARN_ON(sport->curr_tx_desc != sport->dummy_tx_desc))
- return -EINVAL;
- /* Hook the normal buffer descriptor */
- local_irq_save(flags);
- while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) -
- sizeof(struct dmasg)) != sport->dummy_tx_desc)
- continue;
- sport->dummy_tx_desc->next_desc_addr = sport->dma_tx_desc;
- local_irq_restore(flags);
- sport->curr_tx_desc = sport->dma_tx_desc;
- } else {
-
- sport_tx_dma_start(sport, 0);
- /* Let rx dma run the dummy buffer */
- sport_rx_dma_start(sport, 1);
- sport_start(sport);
- }
- sport->tx_run = 1;
- return 0;
-}
-EXPORT_SYMBOL(sport_tx_start);
-
-int sport_tx_stop(struct sport_device *sport)
-{
- if (!sport->tx_run)
- return 0;
- if (sport->rx_run) {
- /* RX is still running, hook the dummy buffer */
- sport_hook_tx_dummy(sport);
- } else {
- /* Both rx and tx dma stopped */
- sport_stop(sport);
- sport->curr_rx_desc = NULL;
- sport->curr_tx_desc = NULL;
- }
-
- sport->tx_run = 0;
-
- return 0;
-}
-EXPORT_SYMBOL(sport_tx_stop);
-
-static inline int compute_wdsize(size_t wdsize)
-{
- switch (wdsize) {
- case 1:
- return WDSIZE_8;
- case 2:
- return WDSIZE_16;
- case 4:
- default:
- return WDSIZE_32;
- }
-}
-
-int sport_config_rx_dma(struct sport_device *sport, void *buf,
- int fragcount, size_t fragsize)
-{
- unsigned int x_count;
- unsigned int y_count;
- unsigned int cfg;
- dma_addr_t addr;
-
- pr_debug("%s buf:%p, frag:%d, fragsize:0x%lx\n", __func__, \
- buf, fragcount, fragsize);
-
- x_count = fragsize / sport->wdsize;
- y_count = 0;
-
- /* for fragments larger than 64k words we use 2d dma,
- * denote fragecount as two numbers' mutliply and both of them
- * are less than 64k.*/
- if (x_count >= 0x10000) {
- int i, count = x_count;
-
- for (i = 16; i > 0; i--) {
- x_count = 1 << i;
- if ((count & (x_count - 1)) == 0) {
- y_count = count >> i;
- if (y_count < 0x10000)
- break;
- }
- }
- if (i == 0)
- return -EINVAL;
- }
- pr_debug("%s(x_count:0x%x, y_count:0x%x)\n", __func__,
- x_count, y_count);
-
- if (sport->dma_rx_desc)
- dma_free_coherent(NULL, sport->rx_desc_bytes,
- sport->dma_rx_desc, 0);
-
- /* Allocate a new descritor ring as current one. */
- sport->dma_rx_desc = dma_alloc_coherent(NULL, \
- fragcount * sizeof(struct dmasg), &addr, 0);
- sport->rx_desc_bytes = fragcount * sizeof(struct dmasg);
-
- if (!sport->dma_rx_desc) {
- pr_err("Failed to allocate memory for rx desc\n");
- return -ENOMEM;
- }
-
- sport->rx_buf = buf;
- sport->rx_fragsize = fragsize;
- sport->rx_frags = fragcount;
-
- cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | WNR | \
- (DESC_ELEMENT_COUNT << 8); /* large descriptor mode */
-
- if (y_count != 0)
- cfg |= DMA2D;
-
- setup_desc(sport->dma_rx_desc, buf, fragcount, fragsize,
- cfg|DMAEN, x_count, y_count, sport->wdsize);
-
- return 0;
-}
-EXPORT_SYMBOL(sport_config_rx_dma);
-
-int sport_config_tx_dma(struct sport_device *sport, void *buf, \
- int fragcount, size_t fragsize)
-{
- unsigned int x_count;
- unsigned int y_count;
- unsigned int cfg;
- dma_addr_t addr;
-
- pr_debug("%s buf:%p, fragcount:%d, fragsize:0x%lx\n",
- __func__, buf, fragcount, fragsize);
-
- x_count = fragsize/sport->wdsize;
- y_count = 0;
-
- /* for fragments larger than 64k words we use 2d dma,
- * denote fragecount as two numbers' mutliply and both of them
- * are less than 64k.*/
- if (x_count >= 0x10000) {
- int i, count = x_count;
-
- for (i = 16; i > 0; i--) {
- x_count = 1 << i;
- if ((count & (x_count - 1)) == 0) {
- y_count = count >> i;
- if (y_count < 0x10000)
- break;
- }
- }
- if (i == 0)
- return -EINVAL;
- }
- pr_debug("%s x_count:0x%x, y_count:0x%x\n", __func__,
- x_count, y_count);
-
-
- if (sport->dma_tx_desc) {
- dma_free_coherent(NULL, sport->tx_desc_bytes, \
- sport->dma_tx_desc, 0);
- }
-
- sport->dma_tx_desc = dma_alloc_coherent(NULL, \
- fragcount * sizeof(struct dmasg), &addr, 0);
- sport->tx_desc_bytes = fragcount * sizeof(struct dmasg);
- if (!sport->dma_tx_desc) {
- pr_err("Failed to allocate memory for tx desc\n");
- return -ENOMEM;
- }
-
- sport->tx_buf = buf;
- sport->tx_fragsize = fragsize;
- sport->tx_frags = fragcount;
- cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | \
- (DESC_ELEMENT_COUNT << 8); /* large descriptor mode */
-
- if (y_count != 0)
- cfg |= DMA2D;
-
- setup_desc(sport->dma_tx_desc, buf, fragcount, fragsize,
- cfg|DMAEN, x_count, y_count, sport->wdsize);
-
- return 0;
-}
-EXPORT_SYMBOL(sport_config_tx_dma);
-
-/* setup dummy dma descriptor ring, which don't generate interrupts,
- * the x_modify is set to 0 */
-static int sport_config_rx_dummy(struct sport_device *sport)
-{
- struct dmasg *desc;
- unsigned config;
-
- pr_debug("%s entered\n", __func__);
- if (L1_DATA_A_LENGTH)
- desc = l1_data_sram_zalloc(2 * sizeof(*desc));
- else {
- dma_addr_t addr;
- desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0);
- memset(desc, 0, 2 * sizeof(*desc));
- }
- if (desc == NULL) {
- pr_err("Failed to allocate memory for dummy rx desc\n");
- return -ENOMEM;
- }
- sport->dummy_rx_desc = desc;
- desc->start_addr = (unsigned long)sport->dummy_buf;
- config = DMAFLOW_LARGE | NDSIZE_9 | compute_wdsize(sport->wdsize)
- | WNR | DMAEN;
- desc->cfg = config;
- desc->x_count = sport->dummy_count/sport->wdsize;
- desc->x_modify = sport->wdsize;
- desc->y_count = 0;
- desc->y_modify = 0;
- memcpy(desc+1, desc, sizeof(*desc));
- desc->next_desc_addr = desc + 1;
- desc[1].next_desc_addr = desc;
- return 0;
-}
-
-static int sport_config_tx_dummy(struct sport_device *sport)
-{
- struct dmasg *desc;
- unsigned int config;
-
- pr_debug("%s entered\n", __func__);
-
- if (L1_DATA_A_LENGTH)
- desc = l1_data_sram_zalloc(2 * sizeof(*desc));
- else {
- dma_addr_t addr;
- desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0);
- memset(desc, 0, 2 * sizeof(*desc));
- }
- if (!desc) {
- pr_err("Failed to allocate memory for dummy tx desc\n");
- return -ENOMEM;
- }
- sport->dummy_tx_desc = desc;
- desc->start_addr = (unsigned long)sport->dummy_buf + \
- sport->dummy_count;
- config = DMAFLOW_LARGE | NDSIZE_9 |
- compute_wdsize(sport->wdsize) | DMAEN;
- desc->cfg = config;
- desc->x_count = sport->dummy_count/sport->wdsize;
- desc->x_modify = sport->wdsize;
- desc->y_count = 0;
- desc->y_modify = 0;
- memcpy(desc+1, desc, sizeof(*desc));
- desc->next_desc_addr = desc + 1;
- desc[1].next_desc_addr = desc;
- return 0;
-}
-
-unsigned long sport_curr_offset_rx(struct sport_device *sport)
-{
- unsigned long curr = get_dma_curr_addr(sport->dma_rx_chan);
-
- return (unsigned char *)curr - sport->rx_buf;
-}
-EXPORT_SYMBOL(sport_curr_offset_rx);
-
-unsigned long sport_curr_offset_tx(struct sport_device *sport)
-{
- unsigned long curr = get_dma_curr_addr(sport->dma_tx_chan);
-
- return (unsigned char *)curr - sport->tx_buf;
-}
-EXPORT_SYMBOL(sport_curr_offset_tx);
-
-void sport_incfrag(struct sport_device *sport, int *frag, int tx)
-{
- ++(*frag);
- if (tx == 1 && *frag == sport->tx_frags)
- *frag = 0;
-
- if (tx == 0 && *frag == sport->rx_frags)
- *frag = 0;
-}
-EXPORT_SYMBOL(sport_incfrag);
-
-void sport_decfrag(struct sport_device *sport, int *frag, int tx)
-{
- --(*frag);
- if (tx == 1 && *frag == 0)
- *frag = sport->tx_frags;
-
- if (tx == 0 && *frag == 0)
- *frag = sport->rx_frags;
-}
-EXPORT_SYMBOL(sport_decfrag);
-
-static int sport_check_status(struct sport_device *sport,
- unsigned int *sport_stat,
- unsigned int *rx_stat,
- unsigned int *tx_stat)
-{
- int status = 0;
-
- if (sport_stat) {
- SSYNC();
- status = sport->regs->stat;
- if (status & (TOVF|TUVF|ROVF|RUVF))
- sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF));
- SSYNC();
- *sport_stat = status;
- }
-
- if (rx_stat) {
- SSYNC();
- status = get_dma_curr_irqstat(sport->dma_rx_chan);
- if (status & (DMA_DONE|DMA_ERR))
- clear_dma_irqstat(sport->dma_rx_chan);
- SSYNC();
- *rx_stat = status;
- }
-
- if (tx_stat) {
- SSYNC();
- status = get_dma_curr_irqstat(sport->dma_tx_chan);
- if (status & (DMA_DONE|DMA_ERR))
- clear_dma_irqstat(sport->dma_tx_chan);
- SSYNC();
- *tx_stat = status;
- }
-
- return 0;
-}
-
-int sport_dump_stat(struct sport_device *sport, char *buf, size_t len)
-{
- int ret;
-
- ret = snprintf(buf, len,
- "sts: 0x%04x\n"
- "rx dma %d sts: 0x%04x tx dma %d sts: 0x%04x\n",
- sport->regs->stat,
- sport->dma_rx_chan,
- get_dma_curr_irqstat(sport->dma_rx_chan),
- sport->dma_tx_chan,
- get_dma_curr_irqstat(sport->dma_tx_chan));
- buf += ret;
- len -= ret;
-
- ret += snprintf(buf, len,
- "curr_rx_desc:0x%p, curr_tx_desc:0x%p\n"
- "dma_rx_desc:0x%p, dma_tx_desc:0x%p\n"
- "dummy_rx_desc:0x%p, dummy_tx_desc:0x%p\n",
- sport->curr_rx_desc, sport->curr_tx_desc,
- sport->dma_rx_desc, sport->dma_tx_desc,
- sport->dummy_rx_desc, sport->dummy_tx_desc);
-
- return ret;
-}
-
-static irqreturn_t rx_handler(int irq, void *dev_id)
-{
- unsigned int rx_stat;
- struct sport_device *sport = dev_id;
-
- pr_debug("%s enter\n", __func__);
- sport_check_status(sport, NULL, &rx_stat, NULL);
- if (!(rx_stat & DMA_DONE))
- pr_err("rx dma is already stopped\n");
-
- if (sport->rx_callback) {
- sport->rx_callback(sport->rx_data);
- return IRQ_HANDLED;
- }
-
- return IRQ_NONE;
-}
-
-static irqreturn_t tx_handler(int irq, void *dev_id)
-{
- unsigned int tx_stat;
- struct sport_device *sport = dev_id;
- pr_debug("%s enter\n", __func__);
- sport_check_status(sport, NULL, NULL, &tx_stat);
- if (!(tx_stat & DMA_DONE)) {
- pr_err("tx dma is already stopped\n");
- return IRQ_HANDLED;
- }
- if (sport->tx_callback) {
- sport->tx_callback(sport->tx_data);
- return IRQ_HANDLED;
- }
-
- return IRQ_NONE;
-}
-
-static irqreturn_t err_handler(int irq, void *dev_id)
-{
- unsigned int status = 0;
- struct sport_device *sport = dev_id;
-
- pr_debug("%s\n", __func__);
- if (sport_check_status(sport, &status, NULL, NULL)) {
- pr_err("error checking status ??");
- return IRQ_NONE;
- }
-
- if (status & (TOVF|TUVF|ROVF|RUVF)) {
- pr_info("sport status error:%s%s%s%s\n",
- status & TOVF ? " TOVF" : "",
- status & TUVF ? " TUVF" : "",
- status & ROVF ? " ROVF" : "",
- status & RUVF ? " RUVF" : "");
- if (status & TOVF || status & TUVF) {
- disable_dma(sport->dma_tx_chan);
- if (sport->tx_run)
- sport_tx_dma_start(sport, 0);
- else
- sport_tx_dma_start(sport, 1);
- enable_dma(sport->dma_tx_chan);
- } else {
- disable_dma(sport->dma_rx_chan);
- if (sport->rx_run)
- sport_rx_dma_start(sport, 0);
- else
- sport_rx_dma_start(sport, 1);
- enable_dma(sport->dma_rx_chan);
- }
- }
- status = sport->regs->stat;
- if (status & (TOVF|TUVF|ROVF|RUVF))
- sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF));
- SSYNC();
-
- if (sport->err_callback)
- sport->err_callback(sport->err_data);
-
- return IRQ_HANDLED;
-}
-
-int sport_set_rx_callback(struct sport_device *sport,
- void (*rx_callback)(void *), void *rx_data)
-{
- if (WARN_ON(!rx_callback))
- return -EINVAL;
- sport->rx_callback = rx_callback;
- sport->rx_data = rx_data;
-
- return 0;
-}
-EXPORT_SYMBOL(sport_set_rx_callback);
-
-int sport_set_tx_callback(struct sport_device *sport,
- void (*tx_callback)(void *), void *tx_data)
-{
- if (WARN_ON(!tx_callback))
- return -EINVAL;
- sport->tx_callback = tx_callback;
- sport->tx_data = tx_data;
-
- return 0;
-}
-EXPORT_SYMBOL(sport_set_tx_callback);
-
-int sport_set_err_callback(struct sport_device *sport,
- void (*err_callback)(void *), void *err_data)
-{
- if (WARN_ON(!err_callback))
- return -EINVAL;
- sport->err_callback = err_callback;
- sport->err_data = err_data;
-
- return 0;
-}
-EXPORT_SYMBOL(sport_set_err_callback);
-
-static int sport_config_pdev(struct platform_device *pdev, struct sport_param *param)
-{
- /* Extract settings from platform data */
- struct device *dev = &pdev->dev;
- struct bfin_snd_platform_data *pdata = dev->platform_data;
- struct resource *res;
-
- param->num = pdev->id;
-
- if (!pdata) {
- dev_err(dev, "no platform_data\n");
- return -ENODEV;
- }
- param->pin_req = pdata->pin_req;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(dev, "no MEM resource\n");
- return -ENODEV;
- }
- param->regs = (struct sport_register *)res->start;
-
- /* first RX, then TX */
- res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (!res) {
- dev_err(dev, "no rx DMA resource\n");
- return -ENODEV;
- }
- param->dma_rx_chan = res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
- if (!res) {
- dev_err(dev, "no tx DMA resource\n");
- return -ENODEV;
- }
- param->dma_tx_chan = res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res) {
- dev_err(dev, "no irq resource\n");
- return -ENODEV;
- }
- param->err_irq = res->start;
-
- return 0;
-}
-
-struct sport_device *sport_init(struct platform_device *pdev,
- unsigned int wdsize, unsigned int dummy_count, size_t priv_size)
-{
- struct device *dev = &pdev->dev;
- struct sport_param param;
- struct sport_device *sport;
- int ret;
-
- dev_dbg(dev, "%s enter\n", __func__);
-
- param.wdsize = wdsize;
- param.dummy_count = dummy_count;
- if (WARN_ON(param.wdsize == 0 || param.dummy_count == 0))
- return NULL;
-
- ret = sport_config_pdev(pdev, ¶m);
- if (ret)
- return NULL;
-
- if (peripheral_request_list(param.pin_req, "soc-audio")) {
- dev_err(dev, "requesting Peripherals failed\n");
- return NULL;
- }
-
- sport = kzalloc(sizeof(*sport), GFP_KERNEL);
- if (!sport) {
- dev_err(dev, "failed to allocate for sport device\n");
- goto __init_err0;
- }
-
- sport->num = param.num;
- sport->dma_rx_chan = param.dma_rx_chan;
- sport->dma_tx_chan = param.dma_tx_chan;
- sport->err_irq = param.err_irq;
- sport->regs = param.regs;
- sport->pin_req = param.pin_req;
-
- if (request_dma(sport->dma_rx_chan, "SPORT RX Data") == -EBUSY) {
- dev_err(dev, "failed to request RX dma %d\n", sport->dma_rx_chan);
- goto __init_err1;
- }
- if (set_dma_callback(sport->dma_rx_chan, rx_handler, sport) != 0) {
- dev_err(dev, "failed to request RX irq %d\n", sport->dma_rx_chan);
- goto __init_err2;
- }
-
- if (request_dma(sport->dma_tx_chan, "SPORT TX Data") == -EBUSY) {
- dev_err(dev, "failed to request TX dma %d\n", sport->dma_tx_chan);
- goto __init_err2;
- }
-
- if (set_dma_callback(sport->dma_tx_chan, tx_handler, sport) != 0) {
- dev_err(dev, "failed to request TX irq %d\n", sport->dma_tx_chan);
- goto __init_err3;
- }
-
- if (request_irq(sport->err_irq, err_handler, IRQF_SHARED, "SPORT err",
- sport) < 0) {
- dev_err(dev, "failed to request err irq %d\n", sport->err_irq);
- goto __init_err3;
- }
-
- dev_info(dev, "dma rx:%d tx:%d, err irq:%d, regs:%p\n",
- sport->dma_rx_chan, sport->dma_tx_chan,
- sport->err_irq, sport->regs);
-
- sport->wdsize = param.wdsize;
- sport->dummy_count = param.dummy_count;
-
- sport->private_data = kzalloc(priv_size, GFP_KERNEL);
- if (!sport->private_data) {
- dev_err(dev, "could not alloc priv data %zu bytes\n", priv_size);
- goto __init_err4;
- }
-
- if (L1_DATA_A_LENGTH)
- sport->dummy_buf = l1_data_sram_zalloc(param.dummy_count * 2);
- else
- sport->dummy_buf = kzalloc(param.dummy_count * 2, GFP_KERNEL);
- if (sport->dummy_buf == NULL) {
- dev_err(dev, "failed to allocate dummy buffer\n");
- goto __error1;
- }
-
- ret = sport_config_rx_dummy(sport);
- if (ret) {
- dev_err(dev, "failed to config rx dummy ring\n");
- goto __error2;
- }
- ret = sport_config_tx_dummy(sport);
- if (ret) {
- dev_err(dev, "failed to config tx dummy ring\n");
- goto __error3;
- }
-
- platform_set_drvdata(pdev, sport);
-
- return sport;
-__error3:
- if (L1_DATA_A_LENGTH)
- l1_data_sram_free(sport->dummy_rx_desc);
- else
- dma_free_coherent(NULL, 2*sizeof(struct dmasg),
- sport->dummy_rx_desc, 0);
-__error2:
- if (L1_DATA_A_LENGTH)
- l1_data_sram_free(sport->dummy_buf);
- else
- kfree(sport->dummy_buf);
-__error1:
- kfree(sport->private_data);
-__init_err4:
- free_irq(sport->err_irq, sport);
-__init_err3:
- free_dma(sport->dma_tx_chan);
-__init_err2:
- free_dma(sport->dma_rx_chan);
-__init_err1:
- kfree(sport);
-__init_err0:
- peripheral_free_list(param.pin_req);
- return NULL;
-}
-EXPORT_SYMBOL(sport_init);
-
-void sport_done(struct sport_device *sport)
-{
- if (sport == NULL)
- return;
-
- sport_stop(sport);
- if (sport->dma_rx_desc)
- dma_free_coherent(NULL, sport->rx_desc_bytes,
- sport->dma_rx_desc, 0);
- if (sport->dma_tx_desc)
- dma_free_coherent(NULL, sport->tx_desc_bytes,
- sport->dma_tx_desc, 0);
-
-#if L1_DATA_A_LENGTH != 0
- l1_data_sram_free(sport->dummy_rx_desc);
- l1_data_sram_free(sport->dummy_tx_desc);
- l1_data_sram_free(sport->dummy_buf);
-#else
- dma_free_coherent(NULL, 2*sizeof(struct dmasg),
- sport->dummy_rx_desc, 0);
- dma_free_coherent(NULL, 2*sizeof(struct dmasg),
- sport->dummy_tx_desc, 0);
- kfree(sport->dummy_buf);
-#endif
- free_dma(sport->dma_rx_chan);
- free_dma(sport->dma_tx_chan);
- free_irq(sport->err_irq, sport);
-
- kfree(sport->private_data);
- peripheral_free_list(sport->pin_req);
- kfree(sport);
-}
-EXPORT_SYMBOL(sport_done);
-
-/*
-* It is only used to send several bytes when dma is not enabled
- * sport controller is configured but not enabled.
- * Multichannel cannot works with pio mode */
-/* Used by ac97 to write and read codec register */
-int sport_send_and_recv(struct sport_device *sport, u8 *out_data, \
- u8 *in_data, int len)
-{
- unsigned short dma_config;
- unsigned short status;
- unsigned long flags;
- unsigned long wait = 0;
-
- pr_debug("%s enter, out_data:%p, in_data:%p len:%d\n", \
- __func__, out_data, in_data, len);
- pr_debug("tcr1:0x%04x, tcr2:0x%04x, tclkdiv:0x%04x, tfsdiv:0x%04x\n"
- "mcmc1:0x%04x, mcmc2:0x%04x\n",
- sport->regs->tcr1, sport->regs->tcr2,
- sport->regs->tclkdiv, sport->regs->tfsdiv,
- sport->regs->mcmc1, sport->regs->mcmc2);
- flush_dcache_range((unsigned)out_data, (unsigned)(out_data + len));
-
- /* Enable tx dma */
- dma_config = (RESTART | WDSIZE_16 | DI_EN);
- set_dma_start_addr(sport->dma_tx_chan, (unsigned long)out_data);
- set_dma_x_count(sport->dma_tx_chan, len/2);
- set_dma_x_modify(sport->dma_tx_chan, 2);
- set_dma_config(sport->dma_tx_chan, dma_config);
- enable_dma(sport->dma_tx_chan);
-
- if (in_data != NULL) {
- invalidate_dcache_range((unsigned)in_data, \
- (unsigned)(in_data + len));
- /* Enable rx dma */
- dma_config = (RESTART | WDSIZE_16 | WNR | DI_EN);
- set_dma_start_addr(sport->dma_rx_chan, (unsigned long)in_data);
- set_dma_x_count(sport->dma_rx_chan, len/2);
- set_dma_x_modify(sport->dma_rx_chan, 2);
- set_dma_config(sport->dma_rx_chan, dma_config);
- enable_dma(sport->dma_rx_chan);
- }
-
- local_irq_save(flags);
- sport->regs->tcr1 |= TSPEN;
- sport->regs->rcr1 |= RSPEN;
- SSYNC();
-
- status = get_dma_curr_irqstat(sport->dma_tx_chan);
- while (status & DMA_RUN) {
- udelay(1);
- status = get_dma_curr_irqstat(sport->dma_tx_chan);
- pr_debug("DMA status:0x%04x\n", status);
- if (wait++ > 100)
- goto __over;
- }
- status = sport->regs->stat;
- wait = 0;
-
- while (!(status & TXHRE)) {
- pr_debug("sport status:0x%04x\n", status);
- udelay(1);
- status = *(unsigned short *)&sport->regs->stat;
- if (wait++ > 1000)
- goto __over;
- }
- /* Wait for the last byte sent out */
- udelay(20);
- pr_debug("sport status:0x%04x\n", status);
-
-__over:
- sport->regs->tcr1 &= ~TSPEN;
- sport->regs->rcr1 &= ~RSPEN;
- SSYNC();
- disable_dma(sport->dma_tx_chan);
- /* Clear the status */
- clear_dma_irqstat(sport->dma_tx_chan);
- if (in_data != NULL) {
- disable_dma(sport->dma_rx_chan);
- clear_dma_irqstat(sport->dma_rx_chan);
- }
- SSYNC();
- local_irq_restore(flags);
-
- return 0;
-}
-EXPORT_SYMBOL(sport_send_and_recv);
-
-MODULE_AUTHOR("Roy Huang");
-MODULE_DESCRIPTION("SPORT driver for ADI Blackfin");
-MODULE_LICENSE("GPL");
diff --git a/sound/soc/blackfin/bf5xx-sport.h b/sound/soc/blackfin/bf5xx-sport.h
deleted file mode 100644
index 9fc2192..0000000
--- a/sound/soc/blackfin/bf5xx-sport.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * File: bf5xx_sport.h
- * Based on:
- * Author: Roy Huang <roy.huang@analog.com>
- *
- * Created:
- * Description:
- *
- * Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef __BF5XX_SPORT_H__
-#define __BF5XX_SPORT_H__
-
-#include <linux/types.h>
-#include <linux/wait.h>
-#include <linux/workqueue.h>
-#include <linux/platform_device.h>
-#include <asm/dma.h>
-#include <asm/bfin_sport.h>
-
-#define DESC_ELEMENT_COUNT 9
-
-struct sport_device {
- int num;
- int dma_rx_chan;
- int dma_tx_chan;
- int err_irq;
- const unsigned short *pin_req;
- struct sport_register *regs;
-
- unsigned char *rx_buf;
- unsigned char *tx_buf;
- unsigned int rx_fragsize;
- unsigned int tx_fragsize;
- unsigned int rx_frags;
- unsigned int tx_frags;
- unsigned int wdsize;
-
- /* for dummy dma transfer */
- void *dummy_buf;
- unsigned int dummy_count;
-
- /* DMA descriptor ring head of current audio stream*/
- struct dmasg *dma_rx_desc;
- struct dmasg *dma_tx_desc;
- unsigned int rx_desc_bytes;
- unsigned int tx_desc_bytes;
-
- unsigned int rx_run:1; /* rx is running */
- unsigned int tx_run:1; /* tx is running */
-
- struct dmasg *dummy_rx_desc;
- struct dmasg *dummy_tx_desc;
-
- struct dmasg *curr_rx_desc;
- struct dmasg *curr_tx_desc;
-
- int rx_curr_frag;
- int tx_curr_frag;
-
- unsigned int rcr1;
- unsigned int rcr2;
- int rx_tdm_count;
-
- unsigned int tcr1;
- unsigned int tcr2;
- int tx_tdm_count;
-
- void (*rx_callback)(void *data);
- void *rx_data;
- void (*tx_callback)(void *data);
- void *tx_data;
- void (*err_callback)(void *data);
- void *err_data;
- unsigned char *tx_dma_buf;
- unsigned char *rx_dma_buf;
-#ifdef CONFIG_SND_BF5XX_MMAP_SUPPORT
- dma_addr_t tx_dma_phy;
- dma_addr_t rx_dma_phy;
- int tx_pos;/*pcm sample count*/
- int rx_pos;
- unsigned int tx_buffer_size;
- unsigned int rx_buffer_size;
- int tx_delay_pos;
- int once;
-#endif
- void *private_data;
-};
-
-struct sport_param {
- int num;
- int dma_rx_chan;
- int dma_tx_chan;
- int err_irq;
- const unsigned short *pin_req;
- struct sport_register *regs;
- unsigned int wdsize;
- unsigned int dummy_count;
- void *private_data;
-};
-
-struct sport_device *sport_init(struct platform_device *pdev,
- unsigned int wdsize, unsigned int dummy_count, size_t priv_size);
-
-void sport_done(struct sport_device *sport);
-
-/* first use these ...*/
-
-/* note: multichannel is in units of 8 channels, tdm_count is number of channels
- * NOT / 8 ! all channels are enabled by default */
-int sport_set_multichannel(struct sport_device *sport, int tdm_count,
- u32 tx_mask, u32 rx_mask, int packed);
-
-int sport_config_rx(struct sport_device *sport,
- unsigned int rcr1, unsigned int rcr2,
- unsigned int clkdiv, unsigned int fsdiv);
-
-int sport_config_tx(struct sport_device *sport,
- unsigned int tcr1, unsigned int tcr2,
- unsigned int clkdiv, unsigned int fsdiv);
-
-/* ... then these: */
-
-/* buffer size (in bytes) == fragcount * fragsize_bytes */
-
-/* this is not a very general api, it sets the dma to 2d autobuffer mode */
-
-int sport_config_rx_dma(struct sport_device *sport, void *buf,
- int fragcount, size_t fragsize_bytes);
-
-int sport_config_tx_dma(struct sport_device *sport, void *buf,
- int fragcount, size_t fragsize_bytes);
-
-int sport_tx_start(struct sport_device *sport);
-int sport_tx_stop(struct sport_device *sport);
-int sport_rx_start(struct sport_device *sport);
-int sport_rx_stop(struct sport_device *sport);
-
-/* for use in interrupt handler */
-unsigned long sport_curr_offset_rx(struct sport_device *sport);
-unsigned long sport_curr_offset_tx(struct sport_device *sport);
-
-void sport_incfrag(struct sport_device *sport, int *frag, int tx);
-void sport_decfrag(struct sport_device *sport, int *frag, int tx);
-
-int sport_set_rx_callback(struct sport_device *sport,
- void (*rx_callback)(void *), void *rx_data);
-int sport_set_tx_callback(struct sport_device *sport,
- void (*tx_callback)(void *), void *tx_data);
-int sport_set_err_callback(struct sport_device *sport,
- void (*err_callback)(void *), void *err_data);
-
-int sport_send_and_recv(struct sport_device *sport, u8 *out_data, \
- u8 *in_data, int len);
-#endif /* BF53X_SPORT_H */
diff --git a/sound/soc/blackfin/bf5xx-ssm2602.c b/sound/soc/blackfin/bf5xx-ssm2602.c
deleted file mode 100644
index 9c19ccc..0000000
--- a/sound/soc/blackfin/bf5xx-ssm2602.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * File: sound/soc/blackfin/bf5xx-ssm2602.c
- * Author: Cliff Cai <Cliff.Cai@analog.com>
- *
- * Created: Tue June 06 2008
- * Description: board driver for SSM2602 sound chip
- *
- * Modified:
- * Copyright 2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/device.h>
-
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-#include <sound/pcm_params.h>
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-#include <linux/gpio.h>
-#include "../codecs/ssm2602.h"
-#include "bf5xx-sport.h"
-
-static struct snd_soc_card bf5xx_ssm2602;
-
-static int bf5xx_ssm2602_dai_init(struct snd_soc_pcm_runtime *rtd)
-{
- /*
- * If you are using a crystal source which frequency is not 12MHz
- * then modify the below case statement with frequency of the crystal.
- *
- * If you are using the SPORT to generate clocking then this is
- * where to do it.
- */
- return snd_soc_dai_set_sysclk(rtd->codec_dai, SSM2602_SYSCLK, 12000000,
- SND_SOC_CLOCK_IN);
-}
-
-/* CODEC is master for BCLK and LRC in this configuration. */
-#define BF5XX_SSM2602_DAIFMT (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | \
- SND_SOC_DAIFMT_CBM_CFM)
-
-static struct snd_soc_dai_link bf5xx_ssm2602_dai[] = {
- {
- .name = "ssm2602",
- .stream_name = "SSM2602",
- .cpu_dai_name = "bfin-i2s.0",
- .codec_dai_name = "ssm2602-hifi",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "ssm2602.0-001b",
- .init = bf5xx_ssm2602_dai_init,
- .dai_fmt = BF5XX_SSM2602_DAIFMT,
- },
- {
- .name = "ssm2602",
- .stream_name = "SSM2602",
- .cpu_dai_name = "bfin-i2s.1",
- .codec_dai_name = "ssm2602-hifi",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "ssm2602.0-001b",
- .init = bf5xx_ssm2602_dai_init,
- .dai_fmt = BF5XX_SSM2602_DAIFMT,
- },
-};
-
-static struct snd_soc_card bf5xx_ssm2602 = {
- .name = "bfin-ssm2602",
- .owner = THIS_MODULE,
- .dai_link = &bf5xx_ssm2602_dai[CONFIG_SND_BF5XX_SPORT_NUM],
- .num_links = 1,
-};
-
-static struct platform_device *bf5xx_ssm2602_snd_device;
-
-static int __init bf5xx_ssm2602_init(void)
-{
- int ret;
-
- pr_debug("%s enter\n", __func__);
- bf5xx_ssm2602_snd_device = platform_device_alloc("soc-audio", -1);
- if (!bf5xx_ssm2602_snd_device)
- return -ENOMEM;
-
- platform_set_drvdata(bf5xx_ssm2602_snd_device, &bf5xx_ssm2602);
- ret = platform_device_add(bf5xx_ssm2602_snd_device);
-
- if (ret)
- platform_device_put(bf5xx_ssm2602_snd_device);
-
- return ret;
-}
-
-static void __exit bf5xx_ssm2602_exit(void)
-{
- pr_debug("%s enter\n", __func__);
- platform_device_unregister(bf5xx_ssm2602_snd_device);
-}
-
-module_init(bf5xx_ssm2602_init);
-module_exit(bf5xx_ssm2602_exit);
-
-/* Module information */
-MODULE_AUTHOR("Cliff Cai");
-MODULE_DESCRIPTION("ALSA SoC SSM2602 BF527-EZKIT");
-MODULE_LICENSE("GPL");
-
diff --git a/sound/soc/blackfin/bf6xx-i2s.c b/sound/soc/blackfin/bf6xx-i2s.c
deleted file mode 100644
index 819cff1..0000000
--- a/sound/soc/blackfin/bf6xx-i2s.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * bf6xx-i2s.c - Analog Devices BF6XX i2s interface driver
- *
- * Copyright (c) 2012 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <sound/pcm.h>
-#include <sound/pcm_params.h>
-#include <sound/soc.h>
-#include <sound/soc-dai.h>
-
-#include "bf6xx-sport.h"
-
-struct sport_params param;
-
-static int bfin_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
- unsigned int fmt)
-{
- struct sport_device *sport = snd_soc_dai_get_drvdata(cpu_dai);
- struct device *dev = &sport->pdev->dev;
- int ret = 0;
-
- param.spctl &= ~(SPORT_CTL_OPMODE | SPORT_CTL_CKRE | SPORT_CTL_FSR
- | SPORT_CTL_LFS | SPORT_CTL_LAFS);
- switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
- case SND_SOC_DAIFMT_I2S:
- param.spctl |= SPORT_CTL_OPMODE | SPORT_CTL_CKRE
- | SPORT_CTL_LFS;
- break;
- case SND_SOC_DAIFMT_DSP_A:
- param.spctl |= SPORT_CTL_FSR;
- break;
- case SND_SOC_DAIFMT_LEFT_J:
- param.spctl |= SPORT_CTL_OPMODE | SPORT_CTL_LFS
- | SPORT_CTL_LAFS;
- break;
- default:
- dev_err(dev, "%s: Unknown DAI format type\n", __func__);
- ret = -EINVAL;
- break;
- }
-
- param.spctl &= ~(SPORT_CTL_ICLK | SPORT_CTL_IFS);
- switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
- case SND_SOC_DAIFMT_CBM_CFM:
- break;
- case SND_SOC_DAIFMT_CBS_CFS:
- case SND_SOC_DAIFMT_CBM_CFS:
- case SND_SOC_DAIFMT_CBS_CFM:
- ret = -EINVAL;
- break;
- default:
- dev_err(dev, "%s: Unknown DAI master type\n", __func__);
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-static int bfin_i2s_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params,
- struct snd_soc_dai *dai)
-{
- struct sport_device *sport = snd_soc_dai_get_drvdata(dai);
- struct device *dev = &sport->pdev->dev;
- int ret = 0;
-
- param.spctl &= ~SPORT_CTL_SLEN;
- switch (params_format(params)) {
- case SNDRV_PCM_FORMAT_S8:
- param.spctl |= 0x70;
- sport->wdsize = 1;
- break;
- case SNDRV_PCM_FORMAT_S16_LE:
- param.spctl |= 0xf0;
- sport->wdsize = 2;
- break;
- case SNDRV_PCM_FORMAT_S24_LE:
- param.spctl |= 0x170;
- sport->wdsize = 3;
- break;
- case SNDRV_PCM_FORMAT_S32_LE:
- param.spctl |= 0x1f0;
- sport->wdsize = 4;
- break;
- }
-
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- ret = sport_set_tx_params(sport, ¶m);
- if (ret) {
- dev_err(dev, "SPORT tx is busy!\n");
- return ret;
- }
- } else {
- ret = sport_set_rx_params(sport, ¶m);
- if (ret) {
- dev_err(dev, "SPORT rx is busy!\n");
- return ret;
- }
- }
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int bfin_i2s_suspend(struct snd_soc_dai *dai)
-{
- struct sport_device *sport = snd_soc_dai_get_drvdata(dai);
-
- if (dai->capture_active)
- sport_rx_stop(sport);
- if (dai->playback_active)
- sport_tx_stop(sport);
- return 0;
-}
-
-static int bfin_i2s_resume(struct snd_soc_dai *dai)
-{
- struct sport_device *sport = snd_soc_dai_get_drvdata(dai);
- struct device *dev = &sport->pdev->dev;
- int ret;
-
- ret = sport_set_tx_params(sport, ¶m);
- if (ret) {
- dev_err(dev, "SPORT tx is busy!\n");
- return ret;
- }
- ret = sport_set_rx_params(sport, ¶m);
- if (ret) {
- dev_err(dev, "SPORT rx is busy!\n");
- return ret;
- }
-
- return 0;
-}
-
-#else
-#define bfin_i2s_suspend NULL
-#define bfin_i2s_resume NULL
-#endif
-
-#define BFIN_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
- SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
- SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
- SNDRV_PCM_RATE_96000)
-
-#define BFIN_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
- SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
-
-static const struct snd_soc_dai_ops bfin_i2s_dai_ops = {
- .hw_params = bfin_i2s_hw_params,
- .set_fmt = bfin_i2s_set_dai_fmt,
-};
-
-static struct snd_soc_dai_driver bfin_i2s_dai = {
- .suspend = bfin_i2s_suspend,
- .resume = bfin_i2s_resume,
- .playback = {
- .channels_min = 1,
- .channels_max = 2,
- .rates = BFIN_I2S_RATES,
- .formats = BFIN_I2S_FORMATS,
- },
- .capture = {
- .channels_min = 1,
- .channels_max = 2,
- .rates = BFIN_I2S_RATES,
- .formats = BFIN_I2S_FORMATS,
- },
- .ops = &bfin_i2s_dai_ops,
-};
-
-static const struct snd_soc_component_driver bfin_i2s_component = {
- .name = "bfin-i2s",
-};
-
-static int bfin_i2s_probe(struct platform_device *pdev)
-{
- struct sport_device *sport;
- struct device *dev = &pdev->dev;
- int ret;
-
- sport = sport_create(pdev);
- if (!sport)
- return -ENODEV;
-
- /* register with the ASoC layers */
- ret = snd_soc_register_component(dev, &bfin_i2s_component,
- &bfin_i2s_dai, 1);
- if (ret) {
- dev_err(dev, "Failed to register DAI: %d\n", ret);
- sport_delete(sport);
- return ret;
- }
- platform_set_drvdata(pdev, sport);
-
- return 0;
-}
-
-static int bfin_i2s_remove(struct platform_device *pdev)
-{
- struct sport_device *sport = platform_get_drvdata(pdev);
-
- snd_soc_unregister_component(&pdev->dev);
- sport_delete(sport);
-
- return 0;
-}
-
-static struct platform_driver bfin_i2s_driver = {
- .probe = bfin_i2s_probe,
- .remove = bfin_i2s_remove,
- .driver = {
- .name = "bfin-i2s",
- },
-};
-
-module_platform_driver(bfin_i2s_driver);
-
-MODULE_DESCRIPTION("Analog Devices BF6XX i2s interface driver");
-MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
-MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/blackfin/bf6xx-sport.c b/sound/soc/blackfin/bf6xx-sport.c
deleted file mode 100644
index d2caadf..0000000
--- a/sound/soc/blackfin/bf6xx-sport.c
+++ /dev/null
@@ -1,425 +0,0 @@
-/*
- * bf6xx_sport.c Analog Devices BF6XX SPORT driver
- *
- * Copyright (c) 2012 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#include "bf6xx-sport.h"
-
-int sport_set_tx_params(struct sport_device *sport,
- struct sport_params *params)
-{
- if (sport->tx_regs->spctl & SPORT_CTL_SPENPRI)
- return -EBUSY;
- sport->tx_regs->spctl = params->spctl | SPORT_CTL_SPTRAN;
- sport->tx_regs->div = params->div;
- SSYNC();
- return 0;
-}
-EXPORT_SYMBOL(sport_set_tx_params);
-
-int sport_set_rx_params(struct sport_device *sport,
- struct sport_params *params)
-{
- if (sport->rx_regs->spctl & SPORT_CTL_SPENPRI)
- return -EBUSY;
- sport->rx_regs->spctl = params->spctl & ~SPORT_CTL_SPTRAN;
- sport->rx_regs->div = params->div;
- SSYNC();
- return 0;
-}
-EXPORT_SYMBOL(sport_set_rx_params);
-
-static int compute_wdsize(size_t wdsize)
-{
- switch (wdsize) {
- case 1:
- return WDSIZE_8 | PSIZE_8;
- case 2:
- return WDSIZE_16 | PSIZE_16;
- default:
- return WDSIZE_32 | PSIZE_32;
- }
-}
-
-void sport_tx_start(struct sport_device *sport)
-{
- set_dma_next_desc_addr(sport->tx_dma_chan, sport->tx_desc);
- set_dma_config(sport->tx_dma_chan, DMAFLOW_LIST | DI_EN
- | compute_wdsize(sport->wdsize) | NDSIZE_6);
- enable_dma(sport->tx_dma_chan);
- sport->tx_regs->spctl |= SPORT_CTL_SPENPRI;
- SSYNC();
-}
-EXPORT_SYMBOL(sport_tx_start);
-
-void sport_rx_start(struct sport_device *sport)
-{
- set_dma_next_desc_addr(sport->rx_dma_chan, sport->rx_desc);
- set_dma_config(sport->rx_dma_chan, DMAFLOW_LIST | DI_EN | WNR
- | compute_wdsize(sport->wdsize) | NDSIZE_6);
- enable_dma(sport->rx_dma_chan);
- sport->rx_regs->spctl |= SPORT_CTL_SPENPRI;
- SSYNC();
-}
-EXPORT_SYMBOL(sport_rx_start);
-
-void sport_tx_stop(struct sport_device *sport)
-{
- sport->tx_regs->spctl &= ~SPORT_CTL_SPENPRI;
- SSYNC();
- disable_dma(sport->tx_dma_chan);
-}
-EXPORT_SYMBOL(sport_tx_stop);
-
-void sport_rx_stop(struct sport_device *sport)
-{
- sport->rx_regs->spctl &= ~SPORT_CTL_SPENPRI;
- SSYNC();
- disable_dma(sport->rx_dma_chan);
-}
-EXPORT_SYMBOL(sport_rx_stop);
-
-void sport_set_tx_callback(struct sport_device *sport,
- void (*tx_callback)(void *), void *tx_data)
-{
- sport->tx_callback = tx_callback;
- sport->tx_data = tx_data;
-}
-EXPORT_SYMBOL(sport_set_tx_callback);
-
-void sport_set_rx_callback(struct sport_device *sport,
- void (*rx_callback)(void *), void *rx_data)
-{
- sport->rx_callback = rx_callback;
- sport->rx_data = rx_data;
-}
-EXPORT_SYMBOL(sport_set_rx_callback);
-
-static void setup_desc(struct dmasg *desc, void *buf, int fragcount,
- size_t fragsize, unsigned int cfg,
- unsigned int count, size_t wdsize)
-{
-
- int i;
-
- for (i = 0; i < fragcount; ++i) {
- desc[i].next_desc_addr = &(desc[i + 1]);
- desc[i].start_addr = (unsigned long)buf + i * fragsize;
- desc[i].cfg = cfg;
- desc[i].x_count = count;
- desc[i].x_modify = wdsize;
- desc[i].y_count = 0;
- desc[i].y_modify = 0;
- }
-
- /* make circular */
- desc[fragcount - 1].next_desc_addr = desc;
-}
-
-int sport_config_tx_dma(struct sport_device *sport, void *buf,
- int fragcount, size_t fragsize)
-{
- unsigned int count;
- unsigned int cfg;
- dma_addr_t addr;
-
- count = fragsize / sport->wdsize;
-
- if (sport->tx_desc)
- dma_free_coherent(NULL, sport->tx_desc_size,
- sport->tx_desc, 0);
-
- sport->tx_desc = dma_alloc_coherent(NULL,
- fragcount * sizeof(struct dmasg), &addr, 0);
- sport->tx_desc_size = fragcount * sizeof(struct dmasg);
- if (!sport->tx_desc)
- return -ENOMEM;
-
- sport->tx_buf = buf;
- sport->tx_fragsize = fragsize;
- sport->tx_frags = fragcount;
- cfg = DMAFLOW_LIST | DI_EN | compute_wdsize(sport->wdsize) | NDSIZE_6;
-
- setup_desc(sport->tx_desc, buf, fragcount, fragsize,
- cfg | DMAEN, count, sport->wdsize);
- return 0;
-}
-EXPORT_SYMBOL(sport_config_tx_dma);
-
-int sport_config_rx_dma(struct sport_device *sport, void *buf,
- int fragcount, size_t fragsize)
-{
- unsigned int count;
- unsigned int cfg;
- dma_addr_t addr;
-
- count = fragsize / sport->wdsize;
-
- if (sport->rx_desc)
- dma_free_coherent(NULL, sport->rx_desc_size,
- sport->rx_desc, 0);
-
- sport->rx_desc = dma_alloc_coherent(NULL,
- fragcount * sizeof(struct dmasg), &addr, 0);
- sport->rx_desc_size = fragcount * sizeof(struct dmasg);
- if (!sport->rx_desc)
- return -ENOMEM;
-
- sport->rx_buf = buf;
- sport->rx_fragsize = fragsize;
- sport->rx_frags = fragcount;
- cfg = DMAFLOW_LIST | DI_EN | compute_wdsize(sport->wdsize)
- | WNR | NDSIZE_6;
-
- setup_desc(sport->rx_desc, buf, fragcount, fragsize,
- cfg | DMAEN, count, sport->wdsize);
- return 0;
-}
-EXPORT_SYMBOL(sport_config_rx_dma);
-
-unsigned long sport_curr_offset_tx(struct sport_device *sport)
-{
- unsigned long curr = get_dma_curr_addr(sport->tx_dma_chan);
-
- return (unsigned char *)curr - sport->tx_buf;
-}
-EXPORT_SYMBOL(sport_curr_offset_tx);
-
-unsigned long sport_curr_offset_rx(struct sport_device *sport)
-{
- unsigned long curr = get_dma_curr_addr(sport->rx_dma_chan);
-
- return (unsigned char *)curr - sport->rx_buf;
-}
-EXPORT_SYMBOL(sport_curr_offset_rx);
-
-static irqreturn_t sport_tx_irq(int irq, void *dev_id)
-{
- struct sport_device *sport = dev_id;
- static unsigned long status;
-
- status = get_dma_curr_irqstat(sport->tx_dma_chan);
- if (status & (DMA_DONE | DMA_ERR)) {
- clear_dma_irqstat(sport->tx_dma_chan);
- SSYNC();
- }
- if (sport->tx_callback)
- sport->tx_callback(sport->tx_data);
- return IRQ_HANDLED;
-}
-
-static irqreturn_t sport_rx_irq(int irq, void *dev_id)
-{
- struct sport_device *sport = dev_id;
- unsigned long status;
-
- status = get_dma_curr_irqstat(sport->rx_dma_chan);
- if (status & (DMA_DONE | DMA_ERR)) {
- clear_dma_irqstat(sport->rx_dma_chan);
- SSYNC();
- }
- if (sport->rx_callback)
- sport->rx_callback(sport->rx_data);
- return IRQ_HANDLED;
-}
-
-static irqreturn_t sport_err_irq(int irq, void *dev_id)
-{
- struct sport_device *sport = dev_id;
- struct device *dev = &sport->pdev->dev;
-
- if (sport->tx_regs->spctl & SPORT_CTL_DERRPRI)
- dev_err(dev, "sport error: TUVF\n");
- if (sport->rx_regs->spctl & SPORT_CTL_DERRPRI)
- dev_err(dev, "sport error: ROVF\n");
-
- return IRQ_HANDLED;
-}
-
-static int sport_get_resource(struct sport_device *sport)
-{
- struct platform_device *pdev = sport->pdev;
- struct device *dev = &pdev->dev;
- struct bfin_snd_platform_data *pdata = dev->platform_data;
- struct resource *res;
-
- if (!pdata) {
- dev_err(dev, "No platform data\n");
- return -ENODEV;
- }
- sport->pin_req = pdata->pin_req;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(dev, "No tx MEM resource\n");
- return -ENODEV;
- }
- sport->tx_regs = (struct sport_register *)res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (!res) {
- dev_err(dev, "No rx MEM resource\n");
- return -ENODEV;
- }
- sport->rx_regs = (struct sport_register *)res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (!res) {
- dev_err(dev, "No tx DMA resource\n");
- return -ENODEV;
- }
- sport->tx_dma_chan = res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
- if (!res) {
- dev_err(dev, "No rx DMA resource\n");
- return -ENODEV;
- }
- sport->rx_dma_chan = res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res) {
- dev_err(dev, "No tx error irq resource\n");
- return -ENODEV;
- }
- sport->tx_err_irq = res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
- if (!res) {
- dev_err(dev, "No rx error irq resource\n");
- return -ENODEV;
- }
- sport->rx_err_irq = res->start;
-
- return 0;
-}
-
-static int sport_request_resource(struct sport_device *sport)
-{
- struct device *dev = &sport->pdev->dev;
- int ret;
-
- ret = peripheral_request_list(sport->pin_req, "soc-audio");
- if (ret) {
- dev_err(dev, "Unable to request sport pin\n");
- return ret;
- }
-
- ret = request_dma(sport->tx_dma_chan, "SPORT TX Data");
- if (ret) {
- dev_err(dev, "Unable to allocate DMA channel for sport tx\n");
- goto err_tx_dma;
- }
- set_dma_callback(sport->tx_dma_chan, sport_tx_irq, sport);
-
- ret = request_dma(sport->rx_dma_chan, "SPORT RX Data");
- if (ret) {
- dev_err(dev, "Unable to allocate DMA channel for sport rx\n");
- goto err_rx_dma;
- }
- set_dma_callback(sport->rx_dma_chan, sport_rx_irq, sport);
-
- ret = request_irq(sport->tx_err_irq, sport_err_irq,
- 0, "SPORT TX ERROR", sport);
- if (ret) {
- dev_err(dev, "Unable to allocate tx error IRQ for sport\n");
- goto err_tx_irq;
- }
-
- ret = request_irq(sport->rx_err_irq, sport_err_irq,
- 0, "SPORT RX ERROR", sport);
- if (ret) {
- dev_err(dev, "Unable to allocate rx error IRQ for sport\n");
- goto err_rx_irq;
- }
-
- return 0;
-err_rx_irq:
- free_irq(sport->tx_err_irq, sport);
-err_tx_irq:
- free_dma(sport->rx_dma_chan);
-err_rx_dma:
- free_dma(sport->tx_dma_chan);
-err_tx_dma:
- peripheral_free_list(sport->pin_req);
- return ret;
-}
-
-static void sport_free_resource(struct sport_device *sport)
-{
- free_irq(sport->rx_err_irq, sport);
- free_irq(sport->tx_err_irq, sport);
- free_dma(sport->rx_dma_chan);
- free_dma(sport->tx_dma_chan);
- peripheral_free_list(sport->pin_req);
-}
-
-struct sport_device *sport_create(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct sport_device *sport;
- int ret;
-
- sport = kzalloc(sizeof(*sport), GFP_KERNEL);
- if (!sport)
- return NULL;
-
- sport->pdev = pdev;
-
- ret = sport_get_resource(sport);
- if (ret)
- goto free_data;
-
- ret = sport_request_resource(sport);
- if (ret)
- goto free_data;
-
- dev_dbg(dev, "SPORT create success\n");
- return sport;
-free_data:
- kfree(sport);
- return NULL;
-}
-EXPORT_SYMBOL(sport_create);
-
-void sport_delete(struct sport_device *sport)
-{
- if (sport->tx_desc)
- dma_free_coherent(NULL, sport->tx_desc_size,
- sport->tx_desc, 0);
- if (sport->rx_desc)
- dma_free_coherent(NULL, sport->rx_desc_size,
- sport->rx_desc, 0);
- sport_free_resource(sport);
- kfree(sport);
-}
-EXPORT_SYMBOL(sport_delete);
-
-MODULE_DESCRIPTION("Analog Devices BF6XX SPORT driver");
-MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
-MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/blackfin/bf6xx-sport.h b/sound/soc/blackfin/bf6xx-sport.h
deleted file mode 100644
index 307d193..0000000
--- a/sound/soc/blackfin/bf6xx-sport.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * bf6xx_sport - Analog Devices BF6XX SPORT driver
- *
- * Copyright (c) 2012 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _BF6XX_SPORT_H_
-#define _BF6XX_SPORT_H_
-
-#include <linux/platform_device.h>
-#include <asm/bfin_sport3.h>
-
-struct sport_device {
- struct platform_device *pdev;
- const unsigned short *pin_req;
- struct sport_register *tx_regs;
- struct sport_register *rx_regs;
- int tx_dma_chan;
- int rx_dma_chan;
- int tx_err_irq;
- int rx_err_irq;
-
- void (*tx_callback)(void *data);
- void *tx_data;
- void (*rx_callback)(void *data);
- void *rx_data;
-
- struct dmasg *tx_desc;
- struct dmasg *rx_desc;
- unsigned int tx_desc_size;
- unsigned int rx_desc_size;
- unsigned char *tx_buf;
- unsigned char *rx_buf;
- unsigned int tx_fragsize;
- unsigned int rx_fragsize;
- unsigned int tx_frags;
- unsigned int rx_frags;
- unsigned int wdsize;
-};
-
-struct sport_params {
- u32 spctl;
- u32 div;
-};
-
-struct sport_device *sport_create(struct platform_device *pdev);
-void sport_delete(struct sport_device *sport);
-int sport_set_tx_params(struct sport_device *sport,
- struct sport_params *params);
-int sport_set_rx_params(struct sport_device *sport,
- struct sport_params *params);
-void sport_tx_start(struct sport_device *sport);
-void sport_rx_start(struct sport_device *sport);
-void sport_tx_stop(struct sport_device *sport);
-void sport_rx_stop(struct sport_device *sport);
-void sport_set_tx_callback(struct sport_device *sport,
- void (*tx_callback)(void *), void *tx_data);
-void sport_set_rx_callback(struct sport_device *sport,
- void (*rx_callback)(void *), void *rx_data);
-int sport_config_tx_dma(struct sport_device *sport, void *buf,
- int fragcount, size_t fragsize);
-int sport_config_rx_dma(struct sport_device *sport, void *buf,
- int fragcount, size_t fragsize);
-unsigned long sport_curr_offset_tx(struct sport_device *sport);
-unsigned long sport_curr_offset_rx(struct sport_device *sport);
-
-
-
-#endif
diff --git a/sound/soc/blackfin/bfin-eval-adau1373.c b/sound/soc/blackfin/bfin-eval-adau1373.c
deleted file mode 100644
index 64b88fd..0000000
--- a/sound/soc/blackfin/bfin-eval-adau1373.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Machine driver for EVAL-ADAU1373 on Analog Devices bfin
- * evaluation boards.
- *
- * Copyright 2011 Analog Devices Inc.
- * Author: Lars-Peter Clausen <lars@metafoo.de>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-#include <sound/pcm_params.h>
-
-#include "../codecs/adau1373.h"
-
-static const struct snd_soc_dapm_widget bfin_eval_adau1373_dapm_widgets[] = {
- SND_SOC_DAPM_LINE("Line In1", NULL),
- SND_SOC_DAPM_LINE("Line In2", NULL),
- SND_SOC_DAPM_LINE("Line In3", NULL),
- SND_SOC_DAPM_LINE("Line In4", NULL),
-
- SND_SOC_DAPM_LINE("Line Out1", NULL),
- SND_SOC_DAPM_LINE("Line Out2", NULL),
- SND_SOC_DAPM_LINE("Stereo Out", NULL),
- SND_SOC_DAPM_HP("Headphone", NULL),
- SND_SOC_DAPM_HP("Earpiece", NULL),
- SND_SOC_DAPM_SPK("Speaker", NULL),
-};
-
-static const struct snd_soc_dapm_route bfin_eval_adau1373_dapm_routes[] = {
- { "AIN1L", NULL, "Line In1" },
- { "AIN1R", NULL, "Line In1" },
- { "AIN2L", NULL, "Line In2" },
- { "AIN2R", NULL, "Line In2" },
- { "AIN3L", NULL, "Line In3" },
- { "AIN3R", NULL, "Line In3" },
- { "AIN4L", NULL, "Line In4" },
- { "AIN4R", NULL, "Line In4" },
-
- /* MICBIAS can be connected via a jumper to the line-in jack, since w
- don't know which one is going to be used, just power both. */
- { "Line In1", NULL, "MICBIAS1" },
- { "Line In2", NULL, "MICBIAS1" },
- { "Line In3", NULL, "MICBIAS1" },
- { "Line In4", NULL, "MICBIAS1" },
- { "Line In1", NULL, "MICBIAS2" },
- { "Line In2", NULL, "MICBIAS2" },
- { "Line In3", NULL, "MICBIAS2" },
- { "Line In4", NULL, "MICBIAS2" },
-
- { "Line Out1", NULL, "LOUT1L" },
- { "Line Out1", NULL, "LOUT1R" },
- { "Line Out2", NULL, "LOUT2L" },
- { "Line Out2", NULL, "LOUT2R" },
- { "Headphone", NULL, "HPL" },
- { "Headphone", NULL, "HPR" },
- { "Earpiece", NULL, "EP" },
- { "Speaker", NULL, "SPKL" },
- { "Stereo Out", NULL, "SPKR" },
-};
-
-static int bfin_eval_adau1373_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_dai *codec_dai = rtd->codec_dai;
- int ret;
- int pll_rate;
-
- switch (params_rate(params)) {
- case 48000:
- case 8000:
- case 12000:
- case 16000:
- case 24000:
- case 32000:
- pll_rate = 48000 * 1024;
- break;
- case 44100:
- case 7350:
- case 11025:
- case 14700:
- case 22050:
- case 29400:
- pll_rate = 44100 * 1024;
- break;
- default:
- return -EINVAL;
- }
-
- ret = snd_soc_dai_set_pll(codec_dai, ADAU1373_PLL1,
- ADAU1373_PLL_SRC_MCLK1, 12288000, pll_rate);
- if (ret)
- return ret;
-
- ret = snd_soc_dai_set_sysclk(codec_dai, ADAU1373_CLK_SRC_PLL1, pll_rate,
- SND_SOC_CLOCK_IN);
-
- return ret;
-}
-
-static int bfin_eval_adau1373_codec_init(struct snd_soc_pcm_runtime *rtd)
-{
- struct snd_soc_dai *codec_dai = rtd->codec_dai;
- unsigned int pll_rate = 48000 * 1024;
- int ret;
-
- ret = snd_soc_dai_set_pll(codec_dai, ADAU1373_PLL1,
- ADAU1373_PLL_SRC_MCLK1, 12288000, pll_rate);
- if (ret)
- return ret;
-
- ret = snd_soc_dai_set_sysclk(codec_dai, ADAU1373_CLK_SRC_PLL1, pll_rate,
- SND_SOC_CLOCK_IN);
-
- return ret;
-}
-static const struct snd_soc_ops bfin_eval_adau1373_ops = {
- .hw_params = bfin_eval_adau1373_hw_params,
-};
-
-static struct snd_soc_dai_link bfin_eval_adau1373_dai = {
- .name = "adau1373",
- .stream_name = "adau1373",
- .cpu_dai_name = "bfin-i2s.0",
- .codec_dai_name = "adau1373-aif1",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "adau1373.0-001a",
- .ops = &bfin_eval_adau1373_ops,
- .init = bfin_eval_adau1373_codec_init,
- .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
- SND_SOC_DAIFMT_CBM_CFM,
-};
-
-static struct snd_soc_card bfin_eval_adau1373 = {
- .name = "bfin-eval-adau1373",
- .owner = THIS_MODULE,
- .dai_link = &bfin_eval_adau1373_dai,
- .num_links = 1,
-
- .dapm_widgets = bfin_eval_adau1373_dapm_widgets,
- .num_dapm_widgets = ARRAY_SIZE(bfin_eval_adau1373_dapm_widgets),
- .dapm_routes = bfin_eval_adau1373_dapm_routes,
- .num_dapm_routes = ARRAY_SIZE(bfin_eval_adau1373_dapm_routes),
-};
-
-static int bfin_eval_adau1373_probe(struct platform_device *pdev)
-{
- struct snd_soc_card *card = &bfin_eval_adau1373;
-
- card->dev = &pdev->dev;
-
- return devm_snd_soc_register_card(&pdev->dev, &bfin_eval_adau1373);
-}
-
-static struct platform_driver bfin_eval_adau1373_driver = {
- .driver = {
- .name = "bfin-eval-adau1373",
- .pm = &snd_soc_pm_ops,
- },
- .probe = bfin_eval_adau1373_probe,
-};
-
-module_platform_driver(bfin_eval_adau1373_driver);
-
-MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
-MODULE_DESCRIPTION("ALSA SoC bfin adau1373 driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:bfin-eval-adau1373");
diff --git a/sound/soc/blackfin/bfin-eval-adau1701.c b/sound/soc/blackfin/bfin-eval-adau1701.c
deleted file mode 100644
index 5c67f72..0000000
--- a/sound/soc/blackfin/bfin-eval-adau1701.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Machine driver for EVAL-ADAU1701MINIZ on Analog Devices bfin
- * evaluation boards.
- *
- * Copyright 2011 Analog Devices Inc.
- * Author: Lars-Peter Clausen <lars@metafoo.de>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-#include <sound/pcm_params.h>
-
-#include "../codecs/adau1701.h"
-
-static const struct snd_soc_dapm_widget bfin_eval_adau1701_dapm_widgets[] = {
- SND_SOC_DAPM_SPK("Speaker", NULL),
- SND_SOC_DAPM_LINE("Line Out", NULL),
- SND_SOC_DAPM_LINE("Line In", NULL),
-};
-
-static const struct snd_soc_dapm_route bfin_eval_adau1701_dapm_routes[] = {
- { "Speaker", NULL, "OUT0" },
- { "Speaker", NULL, "OUT1" },
- { "Line Out", NULL, "OUT2" },
- { "Line Out", NULL, "OUT3" },
-
- { "IN0", NULL, "Line In" },
- { "IN1", NULL, "Line In" },
-};
-
-static int bfin_eval_adau1701_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_dai *codec_dai = rtd->codec_dai;
- int ret;
-
- ret = snd_soc_dai_set_sysclk(codec_dai, ADAU1701_CLK_SRC_OSC, 12288000,
- SND_SOC_CLOCK_IN);
-
- return ret;
-}
-
-static struct snd_soc_ops bfin_eval_adau1701_ops = {
- .hw_params = bfin_eval_adau1701_hw_params,
-};
-
-#define BFIN_EVAL_ADAU1701_DAI_FMT (SND_SOC_DAIFMT_I2S | \
- SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM)
-
-static struct snd_soc_dai_link bfin_eval_adau1701_dai[] = {
- {
- .name = "adau1701",
- .stream_name = "adau1701",
- .cpu_dai_name = "bfin-i2s.0",
- .codec_dai_name = "adau1701",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "adau1701.0-0034",
- .ops = &bfin_eval_adau1701_ops,
- .dai_fmt = BFIN_EVAL_ADAU1701_DAI_FMT,
- },
- {
- .name = "adau1701",
- .stream_name = "adau1701",
- .cpu_dai_name = "bfin-i2s.1",
- .codec_dai_name = "adau1701",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "adau1701.0-0034",
- .ops = &bfin_eval_adau1701_ops,
- .dai_fmt = BFIN_EVAL_ADAU1701_DAI_FMT,
- },
-};
-
-static struct snd_soc_card bfin_eval_adau1701 = {
- .name = "bfin-eval-adau1701",
- .owner = THIS_MODULE,
- .dai_link = &bfin_eval_adau1701_dai[CONFIG_SND_BF5XX_SPORT_NUM],
- .num_links = 1,
-
- .dapm_widgets = bfin_eval_adau1701_dapm_widgets,
- .num_dapm_widgets = ARRAY_SIZE(bfin_eval_adau1701_dapm_widgets),
- .dapm_routes = bfin_eval_adau1701_dapm_routes,
- .num_dapm_routes = ARRAY_SIZE(bfin_eval_adau1701_dapm_routes),
-};
-
-static int bfin_eval_adau1701_probe(struct platform_device *pdev)
-{
- struct snd_soc_card *card = &bfin_eval_adau1701;
-
- card->dev = &pdev->dev;
-
- return devm_snd_soc_register_card(&pdev->dev, &bfin_eval_adau1701);
-}
-
-static struct platform_driver bfin_eval_adau1701_driver = {
- .driver = {
- .name = "bfin-eval-adau1701",
- .pm = &snd_soc_pm_ops,
- },
- .probe = bfin_eval_adau1701_probe,
-};
-
-module_platform_driver(bfin_eval_adau1701_driver);
-
-MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
-MODULE_DESCRIPTION("ALSA SoC bfin ADAU1701 driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:bfin-eval-adau1701");
diff --git a/sound/soc/blackfin/bfin-eval-adau1x61.c b/sound/soc/blackfin/bfin-eval-adau1x61.c
deleted file mode 100644
index fddfe00c..0000000
--- a/sound/soc/blackfin/bfin-eval-adau1x61.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Machine driver for EVAL-ADAU1x61MINIZ on Analog Devices bfin
- * evaluation boards.
- *
- * Copyright 2011-2014 Analog Devices Inc.
- * Author: Lars-Peter Clausen <lars@metafoo.de>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/slab.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-#include <sound/pcm_params.h>
-
-#include "../codecs/adau17x1.h"
-
-static const struct snd_soc_dapm_widget bfin_eval_adau1x61_dapm_widgets[] = {
- SND_SOC_DAPM_LINE("In 1", NULL),
- SND_SOC_DAPM_LINE("In 2", NULL),
- SND_SOC_DAPM_LINE("In 3-4", NULL),
-
- SND_SOC_DAPM_LINE("Diff Out L", NULL),
- SND_SOC_DAPM_LINE("Diff Out R", NULL),
- SND_SOC_DAPM_LINE("Stereo Out", NULL),
- SND_SOC_DAPM_HP("Capless HP Out", NULL),
-};
-
-static const struct snd_soc_dapm_route bfin_eval_adau1x61_dapm_routes[] = {
- { "LAUX", NULL, "In 3-4" },
- { "RAUX", NULL, "In 3-4" },
- { "LINP", NULL, "In 1" },
- { "LINN", NULL, "In 1"},
- { "RINP", NULL, "In 2" },
- { "RINN", NULL, "In 2" },
-
- { "In 1", NULL, "MICBIAS" },
- { "In 2", NULL, "MICBIAS" },
-
- { "Capless HP Out", NULL, "LHP" },
- { "Capless HP Out", NULL, "RHP" },
- { "Diff Out L", NULL, "LOUT" },
- { "Diff Out R", NULL, "ROUT" },
- { "Stereo Out", NULL, "LOUT" },
- { "Stereo Out", NULL, "ROUT" },
-};
-
-static int bfin_eval_adau1x61_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_dai *codec_dai = rtd->codec_dai;
- int pll_rate;
- int ret;
-
- switch (params_rate(params)) {
- case 48000:
- case 8000:
- case 12000:
- case 16000:
- case 24000:
- case 32000:
- case 96000:
- pll_rate = 48000 * 1024;
- break;
- case 44100:
- case 7350:
- case 11025:
- case 14700:
- case 22050:
- case 29400:
- case 88200:
- pll_rate = 44100 * 1024;
- break;
- default:
- return -EINVAL;
- }
-
- ret = snd_soc_dai_set_pll(codec_dai, ADAU17X1_PLL,
- ADAU17X1_PLL_SRC_MCLK, 12288000, pll_rate);
- if (ret)
- return ret;
-
- ret = snd_soc_dai_set_sysclk(codec_dai, ADAU17X1_CLK_SRC_PLL, pll_rate,
- SND_SOC_CLOCK_IN);
-
- return ret;
-}
-
-static const struct snd_soc_ops bfin_eval_adau1x61_ops = {
- .hw_params = bfin_eval_adau1x61_hw_params,
-};
-
-static struct snd_soc_dai_link bfin_eval_adau1x61_dai = {
- .name = "adau1x61",
- .stream_name = "adau1x61",
- .cpu_dai_name = "bfin-i2s.0",
- .codec_dai_name = "adau-hifi",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "adau1761.0-0038",
- .ops = &bfin_eval_adau1x61_ops,
- .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
- SND_SOC_DAIFMT_CBM_CFM,
-};
-
-static struct snd_soc_card bfin_eval_adau1x61 = {
- .name = "bfin-eval-adau1x61",
- .owner = THIS_MODULE,
- .driver_name = "eval-adau1x61",
- .dai_link = &bfin_eval_adau1x61_dai,
- .num_links = 1,
-
- .dapm_widgets = bfin_eval_adau1x61_dapm_widgets,
- .num_dapm_widgets = ARRAY_SIZE(bfin_eval_adau1x61_dapm_widgets),
- .dapm_routes = bfin_eval_adau1x61_dapm_routes,
- .num_dapm_routes = ARRAY_SIZE(bfin_eval_adau1x61_dapm_routes),
- .fully_routed = true,
-};
-
-static int bfin_eval_adau1x61_probe(struct platform_device *pdev)
-{
- bfin_eval_adau1x61.dev = &pdev->dev;
-
- return devm_snd_soc_register_card(&pdev->dev, &bfin_eval_adau1x61);
-}
-
-static struct platform_driver bfin_eval_adau1x61_driver = {
- .driver = {
- .name = "bfin-eval-adau1x61",
- .pm = &snd_soc_pm_ops,
- },
- .probe = bfin_eval_adau1x61_probe,
-};
-module_platform_driver(bfin_eval_adau1x61_driver);
-
-MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
-MODULE_DESCRIPTION("ALSA SoC bfin adau1x61 driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:bfin-eval-adau1x61");
diff --git a/sound/soc/blackfin/bfin-eval-adau1x81.c b/sound/soc/blackfin/bfin-eval-adau1x81.c
deleted file mode 100644
index 3e01cbe..0000000
--- a/sound/soc/blackfin/bfin-eval-adau1x81.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Machine driver for EVAL-ADAU1x81 on Analog Devices bfin
- * evaluation boards.
- *
- * Copyright 2011-2014 Analog Devices Inc.
- * Author: Lars-Peter Clausen <lars@metafoo.de>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/slab.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-#include <sound/pcm_params.h>
-
-#include "../codecs/adau17x1.h"
-
-static const struct snd_soc_dapm_widget bfin_eval_adau1x81_dapm_widgets[] = {
- SND_SOC_DAPM_LINE("Stereo In", NULL),
- SND_SOC_DAPM_LINE("Beep", NULL),
-
- SND_SOC_DAPM_SPK("Speaker", NULL),
- SND_SOC_DAPM_HP("Headphone", NULL),
-};
-
-static const struct snd_soc_dapm_route bfin_eval_adau1x81_dapm_routes[] = {
- { "BEEP", NULL, "Beep" },
- { "LMIC", NULL, "Stereo In" },
- { "LMIC", NULL, "Stereo In" },
-
- { "Headphone", NULL, "AOUTL" },
- { "Headphone", NULL, "AOUTR" },
- { "Speaker", NULL, "SP" },
-};
-
-static int bfin_eval_adau1x81_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_dai *codec_dai = rtd->codec_dai;
- int pll_rate;
- int ret;
-
- switch (params_rate(params)) {
- case 48000:
- case 8000:
- case 12000:
- case 16000:
- case 24000:
- case 32000:
- case 96000:
- pll_rate = 48000 * 1024;
- break;
- case 44100:
- case 7350:
- case 11025:
- case 14700:
- case 22050:
- case 29400:
- case 88200:
- pll_rate = 44100 * 1024;
- break;
- default:
- return -EINVAL;
- }
-
- ret = snd_soc_dai_set_pll(codec_dai, ADAU17X1_PLL,
- ADAU17X1_PLL_SRC_MCLK, 12288000, pll_rate);
- if (ret)
- return ret;
-
- ret = snd_soc_dai_set_sysclk(codec_dai, ADAU17X1_CLK_SRC_PLL, pll_rate,
- SND_SOC_CLOCK_IN);
-
- return ret;
-}
-
-static const struct snd_soc_ops bfin_eval_adau1x81_ops = {
- .hw_params = bfin_eval_adau1x81_hw_params,
-};
-
-static struct snd_soc_dai_link bfin_eval_adau1x81_dai = {
- .name = "adau1x81",
- .stream_name = "adau1x81",
- .cpu_dai_name = "bfin-i2s.0",
- .codec_dai_name = "adau-hifi",
- .platform_name = "bfin-i2s-pcm-audio",
- .codec_name = "adau1781.0-0038",
- .ops = &bfin_eval_adau1x81_ops,
- .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
- SND_SOC_DAIFMT_CBM_CFM,
-};
-
-static struct snd_soc_card bfin_eval_adau1x81 = {
- .name = "bfin-eval-adau1x81",
- .driver_name = "eval-adau1x81",
- .dai_link = &bfin_eval_adau1x81_dai,
- .num_links = 1,
-
- .dapm_widgets = bfin_eval_adau1x81_dapm_widgets,
- .num_dapm_widgets = ARRAY_SIZE(bfin_eval_adau1x81_dapm_widgets),
- .dapm_routes = bfin_eval_adau1x81_dapm_routes,
- .num_dapm_routes = ARRAY_SIZE(bfin_eval_adau1x81_dapm_routes),
- .fully_routed = true,
-};
-
-static int bfin_eval_adau1x81_probe(struct platform_device *pdev)
-{
- bfin_eval_adau1x81.dev = &pdev->dev;
-
- return devm_snd_soc_register_card(&pdev->dev, &bfin_eval_adau1x81);
-}
-
-static struct platform_driver bfin_eval_adau1x81_driver = {
- .driver = {
- .name = "bfin-eval-adau1x81",
- .pm = &snd_soc_pm_ops,
- },
- .probe = bfin_eval_adau1x81_probe,
-};
-module_platform_driver(bfin_eval_adau1x81_driver);
-
-MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
-MODULE_DESCRIPTION("ALSA SoC bfin adau1x81 driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:bfin-eval-adau1x81");
diff --git a/sound/soc/blackfin/bfin-eval-adav80x.c b/sound/soc/blackfin/bfin-eval-adav80x.c
deleted file mode 100644
index 99e5eca..0000000
--- a/sound/soc/blackfin/bfin-eval-adav80x.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Machine driver for EVAL-ADAV801 and EVAL-ADAV803 on Analog Devices bfin
- * evaluation boards.
- *
- * Copyright 2011 Analog Devices Inc.
- * Author: Lars-Peter Clausen <lars@metafoo.de>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-
-#include "../codecs/adav80x.h"
-
-static const struct snd_soc_dapm_widget bfin_eval_adav80x_dapm_widgets[] = {
- SND_SOC_DAPM_LINE("Line Out", NULL),
- SND_SOC_DAPM_LINE("Line In", NULL),
-};
-
-static const struct snd_soc_dapm_route bfin_eval_adav80x_dapm_routes[] = {
- { "Line Out", NULL, "VOUTL" },
- { "Line Out", NULL, "VOUTR" },
-
- { "VINL", NULL, "Line In" },
- { "VINR", NULL, "Line In" },
-};
-
-static int bfin_eval_adav80x_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_dai *codec_dai = rtd->codec_dai;
- int ret;
-
- ret = snd_soc_dai_set_pll(codec_dai, ADAV80X_PLL1, ADAV80X_PLL_SRC_XTAL,
- 27000000, params_rate(params) * 256);
- if (ret)
- return ret;
-
- ret = snd_soc_dai_set_sysclk(codec_dai, ADAV80X_CLK_PLL1,
- params_rate(params) * 256, SND_SOC_CLOCK_IN);
-
- return ret;
-}
-
-static int bfin_eval_adav80x_codec_init(struct snd_soc_pcm_runtime *rtd)
-{
- struct snd_soc_dai *codec_dai = rtd->codec_dai;
-
- snd_soc_dai_set_sysclk(codec_dai, ADAV80X_CLK_SYSCLK1, 0,
- SND_SOC_CLOCK_OUT);
- snd_soc_dai_set_sysclk(codec_dai, ADAV80X_CLK_SYSCLK2, 0,
- SND_SOC_CLOCK_OUT);
- snd_soc_dai_set_sysclk(codec_dai, ADAV80X_CLK_SYSCLK3, 0,
- SND_SOC_CLOCK_OUT);
-
- snd_soc_dai_set_sysclk(codec_dai, ADAV80X_CLK_XTAL, 2700000, 0);
-
- return 0;
-}
-
-static const struct snd_soc_ops bfin_eval_adav80x_ops = {
- .hw_params = bfin_eval_adav80x_hw_params,
-};
-
-static struct snd_soc_dai_link bfin_eval_adav80x_dais[] = {
- {
- .name = "adav80x",
- .stream_name = "ADAV80x HiFi",
- .cpu_dai_name = "bfin-i2s.0",
- .codec_dai_name = "adav80x-hifi",
- .platform_name = "bfin-i2s-pcm-audio",
- .init = bfin_eval_adav80x_codec_init,
- .ops = &bfin_eval_adav80x_ops,
- .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
- SND_SOC_DAIFMT_CBM_CFM,
- },
-};
-
-static struct snd_soc_card bfin_eval_adav80x = {
- .name = "bfin-eval-adav80x",
- .owner = THIS_MODULE,
- .dai_link = bfin_eval_adav80x_dais,
- .num_links = ARRAY_SIZE(bfin_eval_adav80x_dais),
-
- .dapm_widgets = bfin_eval_adav80x_dapm_widgets,
- .num_dapm_widgets = ARRAY_SIZE(bfin_eval_adav80x_dapm_widgets),
- .dapm_routes = bfin_eval_adav80x_dapm_routes,
- .num_dapm_routes = ARRAY_SIZE(bfin_eval_adav80x_dapm_routes),
-};
-
-enum bfin_eval_adav80x_type {
- BFIN_EVAL_ADAV801,
- BFIN_EVAL_ADAV803,
-};
-
-static int bfin_eval_adav80x_probe(struct platform_device *pdev)
-{
- struct snd_soc_card *card = &bfin_eval_adav80x;
- const char *codec_name;
-
- switch (platform_get_device_id(pdev)->driver_data) {
- case BFIN_EVAL_ADAV801:
- codec_name = "spi0.1";
- break;
- case BFIN_EVAL_ADAV803:
- codec_name = "adav803.0-0034";
- break;
- default:
- return -EINVAL;
- }
-
- bfin_eval_adav80x_dais[0].codec_name = codec_name;
-
- card->dev = &pdev->dev;
-
- return devm_snd_soc_register_card(&pdev->dev, &bfin_eval_adav80x);
-}
-
-static const struct platform_device_id bfin_eval_adav80x_ids[] = {
- { "bfin-eval-adav801", BFIN_EVAL_ADAV801 },
- { "bfin-eval-adav803", BFIN_EVAL_ADAV803 },
- { },
-};
-MODULE_DEVICE_TABLE(platform, bfin_eval_adav80x_ids);
-
-static struct platform_driver bfin_eval_adav80x_driver = {
- .driver = {
- .name = "bfin-eval-adav80x",
- .pm = &snd_soc_pm_ops,
- },
- .probe = bfin_eval_adav80x_probe,
- .id_table = bfin_eval_adav80x_ids,
-};
-
-module_platform_driver(bfin_eval_adav80x_driver);
-
-MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
-MODULE_DESCRIPTION("ALSA SoC bfin adav80x driver");
-MODULE_LICENSE("GPL");
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 09/28] input: Remove Blackfin input support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (6 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 08/28] Asoc: Remove Blackfin ASOC support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 10/28] i2c: Remove Blackfin I2C bus support Aaron Wu
` (18 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin input support
---
drivers/input/keyboard/Kconfig | 9 -
drivers/input/keyboard/Makefile | 1 -
drivers/input/keyboard/bf54x-keys.c | 396 ------------------------------
drivers/input/misc/Kconfig | 9 -
drivers/input/misc/Makefile | 1 -
drivers/input/misc/bfin_rotary.c | 294 ----------------------
include/linux/platform_data/bfin_rotary.h | 117 ---------
7 files changed, 827 deletions(-)
delete mode 100644 drivers/input/keyboard/bf54x-keys.c
delete mode 100644 drivers/input/misc/bfin_rotary.c
delete mode 100644 include/linux/platform_data/bfin_rotary.h
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index 4c4ab1c..2b469cc 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -157,15 +157,6 @@ config KEYBOARD_QT2160
This driver can also be built as a module. If so, the module
will be called qt2160.
-config KEYBOARD_BFIN
- tristate "Blackfin BF54x keypad support"
- depends on (BF54x && !BF544)
- help
- Say Y here if you want to use the BF54x keypad.
-
- To compile this driver as a module, choose M here: the
- module will be called bf54x-keys.
-
config KEYBOARD_CLPS711X
tristate "CLPS711X Keypad support"
depends on OF_GPIO && (ARCH_CLPS711X || COMPILE_TEST)
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 526e682..8fab920 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_KEYBOARD_AMIGA) += amikbd.o
obj-$(CONFIG_KEYBOARD_ATARI) += atakbd.o
obj-$(CONFIG_KEYBOARD_ATKBD) += atkbd.o
obj-$(CONFIG_KEYBOARD_BCM) += bcm-keypad.o
-obj-$(CONFIG_KEYBOARD_BFIN) += bf54x-keys.o
obj-$(CONFIG_KEYBOARD_CAP11XX) += cap11xx.o
obj-$(CONFIG_KEYBOARD_CLPS711X) += clps711x-keypad.o
obj-$(CONFIG_KEYBOARD_CROS_EC) += cros_ec_keyb.o
diff --git a/drivers/input/keyboard/bf54x-keys.c b/drivers/input/keyboard/bf54x-keys.c
deleted file mode 100644
index 8a07a42..0000000
--- a/drivers/input/keyboard/bf54x-keys.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * File: drivers/input/keyboard/bf54x-keys.c
- * Based on:
- * Author: Michael Hennerich <hennerich@blackfin.uclinux.org>
- *
- * Created:
- * Description: keypad driver for Analog Devices Blackfin BF54x Processors
- *
- *
- * Modified:
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-
-#include <linux/fs.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/pm.h>
-#include <linux/sysctl.h>
-#include <linux/proc_fs.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-
-#include <asm/portmux.h>
-#include <mach/bf54x_keys.h>
-
-#define DRV_NAME "bf54x-keys"
-#define TIME_SCALE 100 /* 100 ns */
-#define MAX_MULT (0xFF * TIME_SCALE)
-#define MAX_RC 8 /* Max Row/Col */
-
-static const u16 per_rows[] = {
- P_KEY_ROW7,
- P_KEY_ROW6,
- P_KEY_ROW5,
- P_KEY_ROW4,
- P_KEY_ROW3,
- P_KEY_ROW2,
- P_KEY_ROW1,
- P_KEY_ROW0,
- 0
-};
-
-static const u16 per_cols[] = {
- P_KEY_COL7,
- P_KEY_COL6,
- P_KEY_COL5,
- P_KEY_COL4,
- P_KEY_COL3,
- P_KEY_COL2,
- P_KEY_COL1,
- P_KEY_COL0,
- 0
-};
-
-struct bf54x_kpad {
- struct input_dev *input;
- int irq;
- unsigned short lastkey;
- unsigned short *keycode;
- struct timer_list timer;
- unsigned int keyup_test_jiffies;
- unsigned short kpad_msel;
- unsigned short kpad_prescale;
- unsigned short kpad_ctl;
-};
-
-static inline int bfin_kpad_find_key(struct bf54x_kpad *bf54x_kpad,
- struct input_dev *input, u16 keyident)
-{
- u16 i;
-
- for (i = 0; i < input->keycodemax; i++)
- if (bf54x_kpad->keycode[i + input->keycodemax] == keyident)
- return bf54x_kpad->keycode[i];
- return -1;
-}
-
-static inline void bfin_keycodecpy(unsigned short *keycode,
- const unsigned int *pdata_kc,
- unsigned short keymapsize)
-{
- unsigned int i;
-
- for (i = 0; i < keymapsize; i++) {
- keycode[i] = pdata_kc[i] & 0xffff;
- keycode[i + keymapsize] = pdata_kc[i] >> 16;
- }
-}
-
-static inline u16 bfin_kpad_get_prescale(u32 timescale)
-{
- u32 sclk = get_sclk();
-
- return ((((sclk / 1000) * timescale) / 1024) - 1);
-}
-
-static inline u16 bfin_kpad_get_keypressed(struct bf54x_kpad *bf54x_kpad)
-{
- return (bfin_read_KPAD_STAT() & KPAD_PRESSED);
-}
-
-static inline void bfin_kpad_clear_irq(void)
-{
- bfin_write_KPAD_STAT(0xFFFF);
- bfin_write_KPAD_ROWCOL(0xFFFF);
-}
-
-static void bfin_kpad_timer(struct timer_list *t)
-{
- struct bf54x_kpad *bf54x_kpad = from_timer(bf54x_kpad, t, timer);
-
- if (bfin_kpad_get_keypressed(bf54x_kpad)) {
- /* Try again later */
- mod_timer(&bf54x_kpad->timer,
- jiffies + bf54x_kpad->keyup_test_jiffies);
- return;
- }
-
- input_report_key(bf54x_kpad->input, bf54x_kpad->lastkey, 0);
- input_sync(bf54x_kpad->input);
-
- /* Clear IRQ Status */
-
- bfin_kpad_clear_irq();
- enable_irq(bf54x_kpad->irq);
-}
-
-static irqreturn_t bfin_kpad_isr(int irq, void *dev_id)
-{
- struct platform_device *pdev = dev_id;
- struct bf54x_kpad *bf54x_kpad = platform_get_drvdata(pdev);
- struct input_dev *input = bf54x_kpad->input;
- int key;
- u16 rowcol = bfin_read_KPAD_ROWCOL();
-
- key = bfin_kpad_find_key(bf54x_kpad, input, rowcol);
-
- input_report_key(input, key, 1);
- input_sync(input);
-
- if (bfin_kpad_get_keypressed(bf54x_kpad)) {
- disable_irq_nosync(bf54x_kpad->irq);
- bf54x_kpad->lastkey = key;
- mod_timer(&bf54x_kpad->timer,
- jiffies + bf54x_kpad->keyup_test_jiffies);
- } else {
- input_report_key(input, key, 0);
- input_sync(input);
-
- bfin_kpad_clear_irq();
- }
-
- return IRQ_HANDLED;
-}
-
-static int bfin_kpad_probe(struct platform_device *pdev)
-{
- struct bf54x_kpad *bf54x_kpad;
- struct bfin_kpad_platform_data *pdata = dev_get_platdata(&pdev->dev);
- struct input_dev *input;
- int i, error;
-
- if (!pdata->rows || !pdata->cols || !pdata->keymap) {
- dev_err(&pdev->dev, "no rows, cols or keymap from pdata\n");
- return -EINVAL;
- }
-
- if (!pdata->keymapsize ||
- pdata->keymapsize > (pdata->rows * pdata->cols)) {
- dev_err(&pdev->dev, "invalid keymapsize\n");
- return -EINVAL;
- }
-
- bf54x_kpad = kzalloc(sizeof(struct bf54x_kpad), GFP_KERNEL);
- if (!bf54x_kpad)
- return -ENOMEM;
-
- platform_set_drvdata(pdev, bf54x_kpad);
-
- /* Allocate memory for keymap followed by private LUT */
- bf54x_kpad->keycode = kmalloc(pdata->keymapsize *
- sizeof(unsigned short) * 2, GFP_KERNEL);
- if (!bf54x_kpad->keycode) {
- error = -ENOMEM;
- goto out;
- }
-
- if (!pdata->debounce_time || pdata->debounce_time > MAX_MULT ||
- !pdata->coldrive_time || pdata->coldrive_time > MAX_MULT) {
- dev_warn(&pdev->dev,
- "invalid platform debounce/columndrive time\n");
- bfin_write_KPAD_MSEL(0xFF0); /* Default MSEL */
- } else {
- bfin_write_KPAD_MSEL(
- ((pdata->debounce_time / TIME_SCALE)
- & DBON_SCALE) |
- (((pdata->coldrive_time / TIME_SCALE) << 8)
- & COLDRV_SCALE));
-
- }
-
- if (!pdata->keyup_test_interval)
- bf54x_kpad->keyup_test_jiffies = msecs_to_jiffies(50);
- else
- bf54x_kpad->keyup_test_jiffies =
- msecs_to_jiffies(pdata->keyup_test_interval);
-
- if (peripheral_request_list((u16 *)&per_rows[MAX_RC - pdata->rows],
- DRV_NAME)) {
- dev_err(&pdev->dev, "requesting peripherals failed\n");
- error = -EFAULT;
- goto out0;
- }
-
- if (peripheral_request_list((u16 *)&per_cols[MAX_RC - pdata->cols],
- DRV_NAME)) {
- dev_err(&pdev->dev, "requesting peripherals failed\n");
- error = -EFAULT;
- goto out1;
- }
-
- bf54x_kpad->irq = platform_get_irq(pdev, 0);
- if (bf54x_kpad->irq < 0) {
- error = -ENODEV;
- goto out2;
- }
-
- error = request_irq(bf54x_kpad->irq, bfin_kpad_isr,
- 0, DRV_NAME, pdev);
- if (error) {
- dev_err(&pdev->dev, "unable to claim irq %d\n",
- bf54x_kpad->irq);
- goto out2;
- }
-
- input = input_allocate_device();
- if (!input) {
- error = -ENOMEM;
- goto out3;
- }
-
- bf54x_kpad->input = input;
-
- input->name = pdev->name;
- input->phys = "bf54x-keys/input0";
- input->dev.parent = &pdev->dev;
-
- input->id.bustype = BUS_HOST;
- input->id.vendor = 0x0001;
- input->id.product = 0x0001;
- input->id.version = 0x0100;
-
- input->keycodesize = sizeof(unsigned short);
- input->keycodemax = pdata->keymapsize;
- input->keycode = bf54x_kpad->keycode;
-
- bfin_keycodecpy(bf54x_kpad->keycode, pdata->keymap, pdata->keymapsize);
-
- /* setup input device */
- __set_bit(EV_KEY, input->evbit);
-
- if (pdata->repeat)
- __set_bit(EV_REP, input->evbit);
-
- for (i = 0; i < input->keycodemax; i++)
- if (bf54x_kpad->keycode[i] <= KEY_MAX)
- __set_bit(bf54x_kpad->keycode[i], input->keybit);
- __clear_bit(KEY_RESERVED, input->keybit);
-
- error = input_register_device(input);
- if (error) {
- dev_err(&pdev->dev, "unable to register input device\n");
- goto out4;
- }
-
- /* Init Keypad Key Up/Release test timer */
-
- timer_setup(&bf54x_kpad->timer, bfin_kpad_timer, 0);
-
- bfin_write_KPAD_PRESCALE(bfin_kpad_get_prescale(TIME_SCALE));
-
- bfin_write_KPAD_CTL((((pdata->cols - 1) << 13) & KPAD_COLEN) |
- (((pdata->rows - 1) << 10) & KPAD_ROWEN) |
- (2 & KPAD_IRQMODE));
-
- bfin_write_KPAD_CTL(bfin_read_KPAD_CTL() | KPAD_EN);
-
- device_init_wakeup(&pdev->dev, 1);
-
- return 0;
-
-out4:
- input_free_device(input);
-out3:
- free_irq(bf54x_kpad->irq, pdev);
-out2:
- peripheral_free_list((u16 *)&per_cols[MAX_RC - pdata->cols]);
-out1:
- peripheral_free_list((u16 *)&per_rows[MAX_RC - pdata->rows]);
-out0:
- kfree(bf54x_kpad->keycode);
-out:
- kfree(bf54x_kpad);
-
- return error;
-}
-
-static int bfin_kpad_remove(struct platform_device *pdev)
-{
- struct bfin_kpad_platform_data *pdata = dev_get_platdata(&pdev->dev);
- struct bf54x_kpad *bf54x_kpad = platform_get_drvdata(pdev);
-
- del_timer_sync(&bf54x_kpad->timer);
- free_irq(bf54x_kpad->irq, pdev);
-
- input_unregister_device(bf54x_kpad->input);
-
- peripheral_free_list((u16 *)&per_rows[MAX_RC - pdata->rows]);
- peripheral_free_list((u16 *)&per_cols[MAX_RC - pdata->cols]);
-
- kfree(bf54x_kpad->keycode);
- kfree(bf54x_kpad);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int bfin_kpad_suspend(struct platform_device *pdev, pm_message_t state)
-{
- struct bf54x_kpad *bf54x_kpad = platform_get_drvdata(pdev);
-
- bf54x_kpad->kpad_msel = bfin_read_KPAD_MSEL();
- bf54x_kpad->kpad_prescale = bfin_read_KPAD_PRESCALE();
- bf54x_kpad->kpad_ctl = bfin_read_KPAD_CTL();
-
- if (device_may_wakeup(&pdev->dev))
- enable_irq_wake(bf54x_kpad->irq);
-
- return 0;
-}
-
-static int bfin_kpad_resume(struct platform_device *pdev)
-{
- struct bf54x_kpad *bf54x_kpad = platform_get_drvdata(pdev);
-
- bfin_write_KPAD_MSEL(bf54x_kpad->kpad_msel);
- bfin_write_KPAD_PRESCALE(bf54x_kpad->kpad_prescale);
- bfin_write_KPAD_CTL(bf54x_kpad->kpad_ctl);
-
- if (device_may_wakeup(&pdev->dev))
- disable_irq_wake(bf54x_kpad->irq);
-
- return 0;
-}
-#else
-# define bfin_kpad_suspend NULL
-# define bfin_kpad_resume NULL
-#endif
-
-static struct platform_driver bfin_kpad_device_driver = {
- .driver = {
- .name = DRV_NAME,
- },
- .probe = bfin_kpad_probe,
- .remove = bfin_kpad_remove,
- .suspend = bfin_kpad_suspend,
- .resume = bfin_kpad_resume,
-};
-module_platform_driver(bfin_kpad_device_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("Keypad driver for BF54x Processors");
-MODULE_ALIAS("platform:bf54x-keys");
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 62a1312..e9770f5 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -655,15 +655,6 @@ config INPUT_DM355EVM
To compile this driver as a module, choose M here: the
module will be called dm355evm_keys.
-config INPUT_BFIN_ROTARY
- tristate "Blackfin Rotary support"
- depends on BF54x || BF52x
- help
- Say Y here if you want to use the Blackfin Rotary.
-
- To compile this driver as a module, choose M here: the
- module will be called bfin-rotary.
-
config INPUT_WM831X_ON
tristate "WM831X ON pin"
depends on MFD_WM831X
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index a8f61af..eb9c6c3 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_INPUT_ARIZONA_HAPTICS) += arizona-haptics.o
obj-$(CONFIG_INPUT_ATI_REMOTE2) += ati_remote2.o
obj-$(CONFIG_INPUT_ATLAS_BTNS) += atlas_btns.o
obj-$(CONFIG_INPUT_ATMEL_CAPTOUCH) += atmel_captouch.o
-obj-$(CONFIG_INPUT_BFIN_ROTARY) += bfin_rotary.o
obj-$(CONFIG_INPUT_BMA150) += bma150.o
obj-$(CONFIG_INPUT_CM109) += cm109.o
obj-$(CONFIG_INPUT_CMA3000) += cma3000_d0x.o
diff --git a/drivers/input/misc/bfin_rotary.c b/drivers/input/misc/bfin_rotary.c
deleted file mode 100644
index 799ce3d..0000000
--- a/drivers/input/misc/bfin_rotary.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * Rotary counter driver for Analog Devices Blackfin Processors
- *
- * Copyright 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/pm.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/slab.h>
-#include <linux/platform_data/bfin_rotary.h>
-
-#include <asm/portmux.h>
-
-#define CNT_CONFIG_OFF 0 /* CNT Config Offset */
-#define CNT_IMASK_OFF 4 /* CNT Interrupt Mask Offset */
-#define CNT_STATUS_OFF 8 /* CNT Status Offset */
-#define CNT_COMMAND_OFF 12 /* CNT Command Offset */
-#define CNT_DEBOUNCE_OFF 16 /* CNT Debounce Offset */
-#define CNT_COUNTER_OFF 20 /* CNT Counter Offset */
-#define CNT_MAX_OFF 24 /* CNT Maximum Count Offset */
-#define CNT_MIN_OFF 28 /* CNT Minimum Count Offset */
-
-struct bfin_rot {
- struct input_dev *input;
- void __iomem *base;
- int irq;
- unsigned int up_key;
- unsigned int down_key;
- unsigned int button_key;
- unsigned int rel_code;
-
- unsigned short mode;
- unsigned short debounce;
-
- unsigned short cnt_config;
- unsigned short cnt_imask;
- unsigned short cnt_debounce;
-};
-
-static void report_key_event(struct input_dev *input, int keycode)
-{
- /* simulate a press-n-release */
- input_report_key(input, keycode, 1);
- input_sync(input);
- input_report_key(input, keycode, 0);
- input_sync(input);
-}
-
-static void report_rotary_event(struct bfin_rot *rotary, int delta)
-{
- struct input_dev *input = rotary->input;
-
- if (rotary->up_key) {
- report_key_event(input,
- delta > 0 ? rotary->up_key : rotary->down_key);
- } else {
- input_report_rel(input, rotary->rel_code, delta);
- input_sync(input);
- }
-}
-
-static irqreturn_t bfin_rotary_isr(int irq, void *dev_id)
-{
- struct bfin_rot *rotary = dev_id;
- int delta;
-
- switch (readw(rotary->base + CNT_STATUS_OFF)) {
-
- case ICII:
- break;
-
- case UCII:
- case DCII:
- delta = readl(rotary->base + CNT_COUNTER_OFF);
- if (delta)
- report_rotary_event(rotary, delta);
- break;
-
- case CZMII:
- report_key_event(rotary->input, rotary->button_key);
- break;
-
- default:
- break;
- }
-
- writew(W1LCNT_ZERO, rotary->base + CNT_COMMAND_OFF); /* Clear COUNTER */
- writew(-1, rotary->base + CNT_STATUS_OFF); /* Clear STATUS */
-
- return IRQ_HANDLED;
-}
-
-static int bfin_rotary_open(struct input_dev *input)
-{
- struct bfin_rot *rotary = input_get_drvdata(input);
- unsigned short val;
-
- if (rotary->mode & ROT_DEBE)
- writew(rotary->debounce & DPRESCALE,
- rotary->base + CNT_DEBOUNCE_OFF);
-
- writew(rotary->mode & ~CNTE, rotary->base + CNT_CONFIG_OFF);
-
- val = UCIE | DCIE;
- if (rotary->button_key)
- val |= CZMIE;
- writew(val, rotary->base + CNT_IMASK_OFF);
-
- writew(rotary->mode | CNTE, rotary->base + CNT_CONFIG_OFF);
-
- return 0;
-}
-
-static void bfin_rotary_close(struct input_dev *input)
-{
- struct bfin_rot *rotary = input_get_drvdata(input);
-
- writew(0, rotary->base + CNT_CONFIG_OFF);
- writew(0, rotary->base + CNT_IMASK_OFF);
-}
-
-static void bfin_rotary_free_action(void *data)
-{
- peripheral_free_list(data);
-}
-
-static int bfin_rotary_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- const struct bfin_rotary_platform_data *pdata = dev_get_platdata(dev);
- struct bfin_rot *rotary;
- struct resource *res;
- struct input_dev *input;
- int error;
-
- /* Basic validation */
- if ((pdata->rotary_up_key && !pdata->rotary_down_key) ||
- (!pdata->rotary_up_key && pdata->rotary_down_key)) {
- return -EINVAL;
- }
-
- if (pdata->pin_list) {
- error = peripheral_request_list(pdata->pin_list,
- dev_name(dev));
- if (error) {
- dev_err(dev, "requesting peripherals failed: %d\n",
- error);
- return error;
- }
-
- error = devm_add_action_or_reset(dev, bfin_rotary_free_action,
- pdata->pin_list);
- if (error) {
- dev_err(dev, "setting cleanup action failed: %d\n",
- error);
- return error;
- }
- }
-
- rotary = devm_kzalloc(dev, sizeof(struct bfin_rot), GFP_KERNEL);
- if (!rotary)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- rotary->base = devm_ioremap_resource(dev, res);
- if (IS_ERR(rotary->base))
- return PTR_ERR(rotary->base);
-
- input = devm_input_allocate_device(dev);
- if (!input)
- return -ENOMEM;
-
- rotary->input = input;
-
- rotary->up_key = pdata->rotary_up_key;
- rotary->down_key = pdata->rotary_down_key;
- rotary->button_key = pdata->rotary_button_key;
- rotary->rel_code = pdata->rotary_rel_code;
-
- rotary->mode = pdata->mode;
- rotary->debounce = pdata->debounce;
-
- input->name = pdev->name;
- input->phys = "bfin-rotary/input0";
- input->dev.parent = dev;
-
- input_set_drvdata(input, rotary);
-
- input->id.bustype = BUS_HOST;
- input->id.vendor = 0x0001;
- input->id.product = 0x0001;
- input->id.version = 0x0100;
-
- input->open = bfin_rotary_open;
- input->close = bfin_rotary_close;
-
- if (rotary->up_key) {
- __set_bit(EV_KEY, input->evbit);
- __set_bit(rotary->up_key, input->keybit);
- __set_bit(rotary->down_key, input->keybit);
- } else {
- __set_bit(EV_REL, input->evbit);
- __set_bit(rotary->rel_code, input->relbit);
- }
-
- if (rotary->button_key) {
- __set_bit(EV_KEY, input->evbit);
- __set_bit(rotary->button_key, input->keybit);
- }
-
- /* Quiesce the device before requesting irq */
- bfin_rotary_close(input);
-
- rotary->irq = platform_get_irq(pdev, 0);
- if (rotary->irq < 0) {
- dev_err(dev, "No rotary IRQ specified\n");
- return -ENOENT;
- }
-
- error = devm_request_irq(dev, rotary->irq, bfin_rotary_isr,
- 0, dev_name(dev), rotary);
- if (error) {
- dev_err(dev, "unable to claim irq %d; error %d\n",
- rotary->irq, error);
- return error;
- }
-
- error = input_register_device(input);
- if (error) {
- dev_err(dev, "unable to register input device (%d)\n", error);
- return error;
- }
-
- platform_set_drvdata(pdev, rotary);
- device_init_wakeup(dev, 1);
-
- return 0;
-}
-
-static int __maybe_unused bfin_rotary_suspend(struct device *dev)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct bfin_rot *rotary = platform_get_drvdata(pdev);
-
- rotary->cnt_config = readw(rotary->base + CNT_CONFIG_OFF);
- rotary->cnt_imask = readw(rotary->base + CNT_IMASK_OFF);
- rotary->cnt_debounce = readw(rotary->base + CNT_DEBOUNCE_OFF);
-
- if (device_may_wakeup(&pdev->dev))
- enable_irq_wake(rotary->irq);
-
- return 0;
-}
-
-static int __maybe_unused bfin_rotary_resume(struct device *dev)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct bfin_rot *rotary = platform_get_drvdata(pdev);
-
- writew(rotary->cnt_debounce, rotary->base + CNT_DEBOUNCE_OFF);
- writew(rotary->cnt_imask, rotary->base + CNT_IMASK_OFF);
- writew(rotary->cnt_config & ~CNTE, rotary->base + CNT_CONFIG_OFF);
-
- if (device_may_wakeup(&pdev->dev))
- disable_irq_wake(rotary->irq);
-
- if (rotary->cnt_config & CNTE)
- writew(rotary->cnt_config, rotary->base + CNT_CONFIG_OFF);
-
- return 0;
-}
-
-static SIMPLE_DEV_PM_OPS(bfin_rotary_pm_ops,
- bfin_rotary_suspend, bfin_rotary_resume);
-
-static struct platform_driver bfin_rotary_device_driver = {
- .probe = bfin_rotary_probe,
- .driver = {
- .name = "bfin-rotary",
- .pm = &bfin_rotary_pm_ops,
- },
-};
-module_platform_driver(bfin_rotary_device_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("Rotary Counter driver for Blackfin Processors");
-MODULE_ALIAS("platform:bfin-rotary");
diff --git a/include/linux/platform_data/bfin_rotary.h b/include/linux/platform_data/bfin_rotary.h
deleted file mode 100644
index 9882937..0000000
--- a/include/linux/platform_data/bfin_rotary.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * board initialization should put one of these structures into platform_data
- * and place the bfin-rotary onto platform_bus named "bfin-rotary".
- *
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_ROTARY_H
-#define _BFIN_ROTARY_H
-
-/* mode bitmasks */
-#define ROT_QUAD_ENC CNTMODE_QUADENC /* quadrature/grey code encoder mode */
-#define ROT_BIN_ENC CNTMODE_BINENC /* binary encoder mode */
-#define ROT_UD_CNT CNTMODE_UDCNT /* rotary counter mode */
-#define ROT_DIR_CNT CNTMODE_DIRCNT /* direction counter mode */
-
-#define ROT_DEBE DEBE /* Debounce Enable */
-
-#define ROT_CDGINV CDGINV /* CDG Pin Polarity Invert */
-#define ROT_CUDINV CUDINV /* CUD Pin Polarity Invert */
-#define ROT_CZMINV CZMINV /* CZM Pin Polarity Invert */
-
-struct bfin_rotary_platform_data {
- /* set rotary UP KEY_### or BTN_### in case you prefer
- * bfin-rotary to send EV_KEY otherwise set 0
- */
- unsigned int rotary_up_key;
- /* set rotary DOWN KEY_### or BTN_### in case you prefer
- * bfin-rotary to send EV_KEY otherwise set 0
- */
- unsigned int rotary_down_key;
- /* set rotary BUTTON KEY_### or BTN_### */
- unsigned int rotary_button_key;
- /* set rotary Relative Axis REL_### in case you prefer
- * bfin-rotary to send EV_REL otherwise set 0
- */
- unsigned int rotary_rel_code;
- unsigned short debounce; /* 0..17 */
- unsigned short mode;
- unsigned short pm_wakeup;
- unsigned short *pin_list;
-};
-
-/* CNT_CONFIG bitmasks */
-#define CNTE (1 << 0) /* Counter Enable */
-#define DEBE (1 << 1) /* Debounce Enable */
-#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */
-#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */
-#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */
-#define CNTMODE_SHIFT 8
-#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */
-#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */
-#define BNDMODE_SHIFT 12
-#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */
-#define INPDIS (1 << 15) /* CUG and CDG Input Disable */
-
-#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */
-#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */
-#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */
-#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */
-#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */
-
-#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */
-#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */
-#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */
-#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */
-
-/* CNT_IMASK bitmasks */
-#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */
-#define UCIE (1 << 1) /* Up count Interrupt Enable */
-#define DCIE (1 << 2) /* Down count Interrupt Enable */
-#define MINCIE (1 << 3) /* Min Count Interrupt Enable */
-#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */
-#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */
-#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */
-#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */
-#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */
-#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */
-#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */
-
-/* CNT_STATUS bitmasks */
-#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */
-#define UCII (1 << 1) /* Up count Interrupt Identifier */
-#define DCII (1 << 2) /* Down count Interrupt Identifier */
-#define MINCII (1 << 3) /* Min Count Interrupt Identifier */
-#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */
-#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */
-#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */
-#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */
-#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */
-#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */
-#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */
-
-/* CNT_COMMAND bitmasks */
-#define W1LCNT 0xf /* Load Counter Register */
-#define W1LMIN 0xf0 /* Load Min Register */
-#define W1LMAX 0xf00 /* Load Max Register */
-#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */
-
-#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */
-#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */
-#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */
-
-#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */
-#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */
-#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */
-
-#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */
-#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */
-#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */
-
-/* CNT_DEBOUNCE bitmasks */
-#define DPRESCALE 0xf /* Load Counter Register */
-
-#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 10/28] i2c: Remove Blackfin I2C bus support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (7 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 09/28] input: Remove Blackfin input support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 11/28] misc: Remove Blackfin DSP echo support Aaron Wu
` (17 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin I2C bus support
---
drivers/i2c/busses/Kconfig | 18 -
drivers/i2c/busses/Makefile | 1 -
drivers/i2c/busses/i2c-bfin-twi.c | 737 --------------------------------------
3 files changed, 756 deletions(-)
delete mode 100644 drivers/i2c/busses/i2c-bfin-twi.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e2954fb..8ffe2bc 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -445,24 +445,6 @@ config I2C_BRCMSTB
If you do not need I2C interface, say N.
-config I2C_BLACKFIN_TWI
- tristate "Blackfin TWI I2C support"
- depends on BLACKFIN
- depends on !BF561 && !BF531 && !BF532 && !BF533
- help
- This is the I2C bus driver for Blackfin on-chip TWI interface.
-
- This driver can also be built as a module. If so, the module
- will be called i2c-bfin-twi.
-
-config I2C_BLACKFIN_TWI_CLK_KHZ
- int "Blackfin TWI I2C clock (kHz)"
- depends on I2C_BLACKFIN_TWI
- range 21 400
- default 50
- help
- The unit of the TWI clock is kHz.
-
config I2C_CADENCE
tristate "Cadence I2C Controller"
depends on ARCH_ZYNQ || ARM64 || XTENSA
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 2ce8576..9e475a5 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -38,7 +38,6 @@ obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
obj-$(CONFIG_I2C_AXXIA) += i2c-axxia.o
obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o
obj-$(CONFIG_I2C_BCM_IPROC) += i2c-bcm-iproc.o
-obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
obj-$(CONFIG_I2C_CADENCE) += i2c-cadence.o
obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o
obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
deleted file mode 100644
index ff33431..0000000
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ /dev/null
@@ -1,737 +0,0 @@
-/*
- * Blackfin On-Chip Two Wire Interface Driver
- *
- * Copyright 2005-2007 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/i2c.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/mm.h>
-#include <linux/timer.h>
-#include <linux/spinlock.h>
-#include <linux/completion.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-
-#include <asm/irq.h>
-#include <asm/portmux.h>
-#include <asm/bfin_twi.h>
-
-/* SMBus mode*/
-#define TWI_I2C_MODE_STANDARD 1
-#define TWI_I2C_MODE_STANDARDSUB 2
-#define TWI_I2C_MODE_COMBINED 3
-#define TWI_I2C_MODE_REPEAT 4
-
-static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
- unsigned short twi_int_status)
-{
- unsigned short mast_stat = read_MASTER_STAT(iface);
-
- if (twi_int_status & XMTSERV) {
- if (iface->writeNum <= 0) {
- /* start receive immediately after complete sending in
- * combine mode.
- */
- if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) | MDIR);
- else if (iface->manual_stop)
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) | STOP);
- else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
- iface->cur_msg + 1 < iface->msg_num) {
- if (iface->pmsg[iface->cur_msg + 1].flags &
- I2C_M_RD)
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) |
- MDIR);
- else
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) &
- ~MDIR);
- }
- }
- /* Transmit next data */
- while (iface->writeNum > 0 &&
- (read_FIFO_STAT(iface) & XMTSTAT) != XMT_FULL) {
- write_XMT_DATA8(iface, *(iface->transPtr++));
- iface->writeNum--;
- }
- }
- if (twi_int_status & RCVSERV) {
- while (iface->readNum > 0 &&
- (read_FIFO_STAT(iface) & RCVSTAT)) {
- /* Receive next data */
- *(iface->transPtr) = read_RCV_DATA8(iface);
- if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
- /* Change combine mode into sub mode after
- * read first data.
- */
- iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
- /* Get read number from first byte in block
- * combine mode.
- */
- if (iface->readNum == 1 && iface->manual_stop)
- iface->readNum = *iface->transPtr + 1;
- }
- iface->transPtr++;
- iface->readNum--;
- }
-
- if (iface->readNum == 0) {
- if (iface->manual_stop) {
- /* Temporary workaround to avoid possible bus stall -
- * Flush FIFO before issuing the STOP condition
- */
- read_RCV_DATA16(iface);
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) | STOP);
- } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
- iface->cur_msg + 1 < iface->msg_num) {
- if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) | MDIR);
- else
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) & ~MDIR);
- }
- }
- }
- if (twi_int_status & MERR) {
- write_INT_MASK(iface, 0);
- write_MASTER_STAT(iface, 0x3e);
- write_MASTER_CTL(iface, 0);
- iface->result = -EIO;
-
- if (mast_stat & LOSTARB)
- dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
- if (mast_stat & ANAK)
- dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
- if (mast_stat & DNAK)
- dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
- if (mast_stat & BUFRDERR)
- dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
- if (mast_stat & BUFWRERR)
- dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
-
- /* Faulty slave devices, may drive SDA low after a transfer
- * finishes. To release the bus this code generates up to 9
- * extra clocks until SDA is released.
- */
-
- if (read_MASTER_STAT(iface) & SDASEN) {
- int cnt = 9;
- do {
- write_MASTER_CTL(iface, SCLOVR);
- udelay(6);
- write_MASTER_CTL(iface, 0);
- udelay(6);
- } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
-
- write_MASTER_CTL(iface, SDAOVR | SCLOVR);
- udelay(6);
- write_MASTER_CTL(iface, SDAOVR);
- udelay(6);
- write_MASTER_CTL(iface, 0);
- }
-
- /* If it is a quick transfer, only address without data,
- * not an err, return 1.
- */
- if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
- iface->transPtr == NULL &&
- (twi_int_status & MCOMP) && (mast_stat & DNAK))
- iface->result = 1;
-
- complete(&iface->complete);
- return;
- }
- if (twi_int_status & MCOMP) {
- if (twi_int_status & (XMTSERV | RCVSERV) &&
- (read_MASTER_CTL(iface) & MEN) == 0 &&
- (iface->cur_mode == TWI_I2C_MODE_REPEAT ||
- iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
- iface->result = -1;
- write_INT_MASK(iface, 0);
- write_MASTER_CTL(iface, 0);
- } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
- if (iface->readNum == 0) {
- /* set the read number to 1 and ask for manual
- * stop in block combine mode
- */
- iface->readNum = 1;
- iface->manual_stop = 1;
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) | (0xff << 6));
- } else {
- /* set the readd number in other
- * combine mode.
- */
- write_MASTER_CTL(iface,
- (read_MASTER_CTL(iface) &
- (~(0xff << 6))) |
- (iface->readNum << 6));
- }
- /* remove restart bit and enable master receive */
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) & ~RSTART);
- } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
- iface->cur_msg + 1 < iface->msg_num) {
- iface->cur_msg++;
- iface->transPtr = iface->pmsg[iface->cur_msg].buf;
- iface->writeNum = iface->readNum =
- iface->pmsg[iface->cur_msg].len;
- /* Set Transmit device address */
- write_MASTER_ADDR(iface,
- iface->pmsg[iface->cur_msg].addr);
- if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
- iface->read_write = I2C_SMBUS_READ;
- else {
- iface->read_write = I2C_SMBUS_WRITE;
- /* Transmit first data */
- if (iface->writeNum > 0) {
- write_XMT_DATA8(iface,
- *(iface->transPtr++));
- iface->writeNum--;
- }
- }
-
- if (iface->pmsg[iface->cur_msg].len <= 255) {
- write_MASTER_CTL(iface,
- (read_MASTER_CTL(iface) &
- (~(0xff << 6))) |
- (iface->pmsg[iface->cur_msg].len << 6));
- iface->manual_stop = 0;
- } else {
- write_MASTER_CTL(iface,
- (read_MASTER_CTL(iface) |
- (0xff << 6)));
- iface->manual_stop = 1;
- }
- /* remove restart bit before last message */
- if (iface->cur_msg + 1 == iface->msg_num)
- write_MASTER_CTL(iface,
- read_MASTER_CTL(iface) & ~RSTART);
- } else {
- iface->result = 1;
- write_INT_MASK(iface, 0);
- write_MASTER_CTL(iface, 0);
- }
- complete(&iface->complete);
- }
-}
-
-/* Interrupt handler */
-static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
-{
- struct bfin_twi_iface *iface = dev_id;
- unsigned long flags;
- unsigned short twi_int_status;
-
- spin_lock_irqsave(&iface->lock, flags);
- while (1) {
- twi_int_status = read_INT_STAT(iface);
- if (!twi_int_status)
- break;
- /* Clear interrupt status */
- write_INT_STAT(iface, twi_int_status);
- bfin_twi_handle_interrupt(iface, twi_int_status);
- }
- spin_unlock_irqrestore(&iface->lock, flags);
- return IRQ_HANDLED;
-}
-
-/*
- * One i2c master transfer
- */
-static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
- struct i2c_msg *msgs, int num)
-{
- struct bfin_twi_iface *iface = adap->algo_data;
- struct i2c_msg *pmsg;
- int rc = 0;
-
- if (!(read_CONTROL(iface) & TWI_ENA))
- return -ENXIO;
-
- if (read_MASTER_STAT(iface) & BUSBUSY)
- return -EAGAIN;
-
- iface->pmsg = msgs;
- iface->msg_num = num;
- iface->cur_msg = 0;
-
- pmsg = &msgs[0];
- if (pmsg->flags & I2C_M_TEN) {
- dev_err(&adap->dev, "10 bits addr not supported!\n");
- return -EINVAL;
- }
-
- if (iface->msg_num > 1)
- iface->cur_mode = TWI_I2C_MODE_REPEAT;
- iface->manual_stop = 0;
- iface->transPtr = pmsg->buf;
- iface->writeNum = iface->readNum = pmsg->len;
- iface->result = 0;
- init_completion(&(iface->complete));
- /* Set Transmit device address */
- write_MASTER_ADDR(iface, pmsg->addr);
-
- /* FIFO Initiation. Data in FIFO should be
- * discarded before start a new operation.
- */
- write_FIFO_CTL(iface, 0x3);
- write_FIFO_CTL(iface, 0);
-
- if (pmsg->flags & I2C_M_RD)
- iface->read_write = I2C_SMBUS_READ;
- else {
- iface->read_write = I2C_SMBUS_WRITE;
- /* Transmit first data */
- if (iface->writeNum > 0) {
- write_XMT_DATA8(iface, *(iface->transPtr++));
- iface->writeNum--;
- }
- }
-
- /* clear int stat */
- write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
-
- /* Interrupt mask . Enable XMT, RCV interrupt */
- write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
-
- if (pmsg->len <= 255)
- write_MASTER_CTL(iface, pmsg->len << 6);
- else {
- write_MASTER_CTL(iface, 0xff << 6);
- iface->manual_stop = 1;
- }
-
- /* Master enable */
- write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
- (iface->msg_num > 1 ? RSTART : 0) |
- ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
- ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
-
- while (!iface->result) {
- if (!wait_for_completion_timeout(&iface->complete,
- adap->timeout)) {
- iface->result = -1;
- dev_err(&adap->dev, "master transfer timeout\n");
- }
- }
-
- if (iface->result == 1)
- rc = iface->cur_msg + 1;
- else
- rc = iface->result;
-
- return rc;
-}
-
-/*
- * Generic i2c master transfer entrypoint
- */
-static int bfin_twi_master_xfer(struct i2c_adapter *adap,
- struct i2c_msg *msgs, int num)
-{
- return bfin_twi_do_master_xfer(adap, msgs, num);
-}
-
-/*
- * One I2C SMBus transfer
- */
-int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
- unsigned short flags, char read_write,
- u8 command, int size, union i2c_smbus_data *data)
-{
- struct bfin_twi_iface *iface = adap->algo_data;
- int rc = 0;
-
- if (!(read_CONTROL(iface) & TWI_ENA))
- return -ENXIO;
-
- if (read_MASTER_STAT(iface) & BUSBUSY)
- return -EAGAIN;
-
- iface->writeNum = 0;
- iface->readNum = 0;
-
- /* Prepare datas & select mode */
- switch (size) {
- case I2C_SMBUS_QUICK:
- iface->transPtr = NULL;
- iface->cur_mode = TWI_I2C_MODE_STANDARD;
- break;
- case I2C_SMBUS_BYTE:
- if (data == NULL)
- iface->transPtr = NULL;
- else {
- if (read_write == I2C_SMBUS_READ)
- iface->readNum = 1;
- else
- iface->writeNum = 1;
- iface->transPtr = &data->byte;
- }
- iface->cur_mode = TWI_I2C_MODE_STANDARD;
- break;
- case I2C_SMBUS_BYTE_DATA:
- if (read_write == I2C_SMBUS_READ) {
- iface->readNum = 1;
- iface->cur_mode = TWI_I2C_MODE_COMBINED;
- } else {
- iface->writeNum = 1;
- iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
- }
- iface->transPtr = &data->byte;
- break;
- case I2C_SMBUS_WORD_DATA:
- if (read_write == I2C_SMBUS_READ) {
- iface->readNum = 2;
- iface->cur_mode = TWI_I2C_MODE_COMBINED;
- } else {
- iface->writeNum = 2;
- iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
- }
- iface->transPtr = (u8 *)&data->word;
- break;
- case I2C_SMBUS_PROC_CALL:
- iface->writeNum = 2;
- iface->readNum = 2;
- iface->cur_mode = TWI_I2C_MODE_COMBINED;
- iface->transPtr = (u8 *)&data->word;
- break;
- case I2C_SMBUS_BLOCK_DATA:
- if (read_write == I2C_SMBUS_READ) {
- iface->readNum = 0;
- iface->cur_mode = TWI_I2C_MODE_COMBINED;
- } else {
- iface->writeNum = data->block[0] + 1;
- iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
- }
- iface->transPtr = data->block;
- break;
- case I2C_SMBUS_I2C_BLOCK_DATA:
- if (read_write == I2C_SMBUS_READ) {
- iface->readNum = data->block[0];
- iface->cur_mode = TWI_I2C_MODE_COMBINED;
- } else {
- iface->writeNum = data->block[0];
- iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
- }
- iface->transPtr = (u8 *)&data->block[1];
- break;
- default:
- return -1;
- }
-
- iface->result = 0;
- iface->manual_stop = 0;
- iface->read_write = read_write;
- iface->command = command;
- init_completion(&(iface->complete));
-
- /* FIFO Initiation. Data in FIFO should be discarded before
- * start a new operation.
- */
- write_FIFO_CTL(iface, 0x3);
- write_FIFO_CTL(iface, 0);
-
- /* clear int stat */
- write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
-
- /* Set Transmit device address */
- write_MASTER_ADDR(iface, addr);
-
- switch (iface->cur_mode) {
- case TWI_I2C_MODE_STANDARDSUB:
- write_XMT_DATA8(iface, iface->command);
- write_INT_MASK(iface, MCOMP | MERR |
- ((iface->read_write == I2C_SMBUS_READ) ?
- RCVSERV : XMTSERV));
-
- if (iface->writeNum + 1 <= 255)
- write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
- else {
- write_MASTER_CTL(iface, 0xff << 6);
- iface->manual_stop = 1;
- }
- /* Master enable */
- write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
- ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
- break;
- case TWI_I2C_MODE_COMBINED:
- write_XMT_DATA8(iface, iface->command);
- write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
-
- if (iface->writeNum > 0)
- write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
- else
- write_MASTER_CTL(iface, 0x1 << 6);
- /* Master enable */
- write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART |
- ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
- break;
- default:
- write_MASTER_CTL(iface, 0);
- if (size != I2C_SMBUS_QUICK) {
- /* Don't access xmit data register when this is a
- * read operation.
- */
- if (iface->read_write != I2C_SMBUS_READ) {
- if (iface->writeNum > 0) {
- write_XMT_DATA8(iface,
- *(iface->transPtr++));
- if (iface->writeNum <= 255)
- write_MASTER_CTL(iface,
- iface->writeNum << 6);
- else {
- write_MASTER_CTL(iface,
- 0xff << 6);
- iface->manual_stop = 1;
- }
- iface->writeNum--;
- } else {
- write_XMT_DATA8(iface, iface->command);
- write_MASTER_CTL(iface, 1 << 6);
- }
- } else {
- if (iface->readNum > 0 && iface->readNum <= 255)
- write_MASTER_CTL(iface,
- iface->readNum << 6);
- else if (iface->readNum > 255) {
- write_MASTER_CTL(iface, 0xff << 6);
- iface->manual_stop = 1;
- } else
- break;
- }
- }
- write_INT_MASK(iface, MCOMP | MERR |
- ((iface->read_write == I2C_SMBUS_READ) ?
- RCVSERV : XMTSERV));
-
- /* Master enable */
- write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
- ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
- ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
- break;
- }
-
- while (!iface->result) {
- if (!wait_for_completion_timeout(&iface->complete,
- adap->timeout)) {
- iface->result = -1;
- dev_err(&adap->dev, "smbus transfer timeout\n");
- }
- }
-
- rc = (iface->result >= 0) ? 0 : -1;
-
- return rc;
-}
-
-/*
- * Generic I2C SMBus transfer entrypoint
- */
-int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
- unsigned short flags, char read_write,
- u8 command, int size, union i2c_smbus_data *data)
-{
- return bfin_twi_do_smbus_xfer(adap, addr, flags,
- read_write, command, size, data);
-}
-
-/*
- * Return what the adapter supports
- */
-static u32 bfin_twi_functionality(struct i2c_adapter *adap)
-{
- return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
- I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
- I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
- I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
-}
-
-static const struct i2c_algorithm bfin_twi_algorithm = {
- .master_xfer = bfin_twi_master_xfer,
- .smbus_xfer = bfin_twi_smbus_xfer,
- .functionality = bfin_twi_functionality,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int i2c_bfin_twi_suspend(struct device *dev)
-{
- struct bfin_twi_iface *iface = dev_get_drvdata(dev);
-
- iface->saved_clkdiv = read_CLKDIV(iface);
- iface->saved_control = read_CONTROL(iface);
-
- free_irq(iface->irq, iface);
-
- /* Disable TWI */
- write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
-
- return 0;
-}
-
-static int i2c_bfin_twi_resume(struct device *dev)
-{
- struct bfin_twi_iface *iface = dev_get_drvdata(dev);
-
- int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
- 0, to_platform_device(dev)->name, iface);
- if (rc) {
- dev_err(dev, "Can't get IRQ %d !\n", iface->irq);
- return -ENODEV;
- }
-
- /* Resume TWI interface clock as specified */
- write_CLKDIV(iface, iface->saved_clkdiv);
-
- /* Resume TWI */
- write_CONTROL(iface, iface->saved_control);
-
- return 0;
-}
-
-static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm,
- i2c_bfin_twi_suspend, i2c_bfin_twi_resume);
-#define I2C_BFIN_TWI_PM_OPS (&i2c_bfin_twi_pm)
-#else
-#define I2C_BFIN_TWI_PM_OPS NULL
-#endif
-
-static int i2c_bfin_twi_probe(struct platform_device *pdev)
-{
- struct bfin_twi_iface *iface;
- struct i2c_adapter *p_adap;
- struct resource *res;
- int rc;
- unsigned int clkhilow;
-
- iface = devm_kzalloc(&pdev->dev, sizeof(struct bfin_twi_iface),
- GFP_KERNEL);
- if (!iface) {
- dev_err(&pdev->dev, "Cannot allocate memory\n");
- return -ENOMEM;
- }
-
- spin_lock_init(&(iface->lock));
-
- /* Find and map our resources */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- iface->regs_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(iface->regs_base)) {
- dev_err(&pdev->dev, "Cannot map IO\n");
- return PTR_ERR(iface->regs_base);
- }
-
- iface->irq = platform_get_irq(pdev, 0);
- if (iface->irq < 0) {
- dev_err(&pdev->dev, "No IRQ specified\n");
- return -ENOENT;
- }
-
- p_adap = &iface->adap;
- p_adap->nr = pdev->id;
- strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
- p_adap->algo = &bfin_twi_algorithm;
- p_adap->algo_data = iface;
- p_adap->class = I2C_CLASS_DEPRECATED;
- p_adap->dev.parent = &pdev->dev;
- p_adap->timeout = 5 * HZ;
- p_adap->retries = 3;
-
- rc = peripheral_request_list(
- dev_get_platdata(&pdev->dev),
- "i2c-bfin-twi");
- if (rc) {
- dev_err(&pdev->dev, "Can't setup pin mux!\n");
- return -EBUSY;
- }
-
- rc = devm_request_irq(&pdev->dev, iface->irq, bfin_twi_interrupt_entry,
- 0, pdev->name, iface);
- if (rc) {
- dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
- rc = -ENODEV;
- goto out_error;
- }
-
- /* Set TWI internal clock as 10MHz */
- write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
-
- /*
- * We will not end up with a CLKDIV=0 because no one will specify
- * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
- */
- clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
-
- /* Set Twi interface clock as specified */
- write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
-
- /* Enable TWI */
- write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
-
- rc = i2c_add_numbered_adapter(p_adap);
- if (rc < 0)
- goto out_error;
-
- platform_set_drvdata(pdev, iface);
-
- dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Controller, "
- "regs_base@%p\n", iface->regs_base);
-
- return 0;
-
-out_error:
- peripheral_free_list(dev_get_platdata(&pdev->dev));
- return rc;
-}
-
-static int i2c_bfin_twi_remove(struct platform_device *pdev)
-{
- struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
-
- i2c_del_adapter(&(iface->adap));
- peripheral_free_list(dev_get_platdata(&pdev->dev));
-
- return 0;
-}
-
-static struct platform_driver i2c_bfin_twi_driver = {
- .probe = i2c_bfin_twi_probe,
- .remove = i2c_bfin_twi_remove,
- .driver = {
- .name = "i2c-bfin-twi",
- .pm = I2C_BFIN_TWI_PM_OPS,
- },
-};
-
-static int __init i2c_bfin_twi_init(void)
-{
- return platform_driver_register(&i2c_bfin_twi_driver);
-}
-
-static void __exit i2c_bfin_twi_exit(void)
-{
- platform_driver_unregister(&i2c_bfin_twi_driver);
-}
-
-subsys_initcall(i2c_bfin_twi_init);
-module_exit(i2c_bfin_twi_exit);
-
-MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
-MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Controller Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:i2c-bfin-twi");
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 11/28] misc: Remove Blackfin DSP echo support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (8 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 10/28] i2c: Remove Blackfin I2C bus support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 12/28] video: Remove Blackfin video support Aaron Wu
` (16 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin DSP echo support
---
drivers/misc/echo/echo.c | 73 ------------------------------------------------
drivers/misc/echo/fir.h | 50 ---------------------------------
2 files changed, 123 deletions(-)
diff --git a/drivers/misc/echo/echo.c b/drivers/misc/echo/echo.c
index 9597e95..8a5adc0 100644
--- a/drivers/misc/echo/echo.c
+++ b/drivers/misc/echo/echo.c
@@ -115,78 +115,6 @@
/* adapting coeffs using the traditional stochastic descent (N)LMS algorithm */
-#ifdef __bfin__
-static inline void lms_adapt_bg(struct oslec_state *ec, int clean, int shift)
-{
- int i;
- int offset1;
- int offset2;
- int factor;
- int exp;
- int16_t *phist;
- int n;
-
- if (shift > 0)
- factor = clean << shift;
- else
- factor = clean >> -shift;
-
- /* Update the FIR taps */
-
- offset2 = ec->curr_pos;
- offset1 = ec->taps - offset2;
- phist = &ec->fir_state_bg.history[offset2];
-
- /* st: and en: help us locate the assembler in echo.s */
-
- /* asm("st:"); */
- n = ec->taps;
- for (i = 0; i < n; i++) {
- exp = *phist++ * factor;
- ec->fir_taps16[1][i] += (int16_t) ((exp + (1 << 14)) >> 15);
- }
- /* asm("en:"); */
-
- /* Note the asm for the inner loop above generated by Blackfin gcc
- 4.1.1 is pretty good (note even parallel instructions used):
-
- R0 = W [P0++] (X);
- R0 *= R2;
- R0 = R0 + R3 (NS) ||
- R1 = W [P1] (X) ||
- nop;
- R0 >>>= 15;
- R0 = R0 + R1;
- W [P1++] = R0;
-
- A block based update algorithm would be much faster but the
- above can't be improved on much. Every instruction saved in
- the loop above is 2 MIPs/ch! The for loop above is where the
- Blackfin spends most of it's time - about 17 MIPs/ch measured
- with speedtest.c with 256 taps (32ms). Write-back and
- Write-through cache gave about the same performance.
- */
-}
-
-/*
- IDEAS for further optimisation of lms_adapt_bg():
-
- 1/ The rounding is quite costly. Could we keep as 32 bit coeffs
- then make filter pluck the MS 16-bits of the coeffs when filtering?
- However this would lower potential optimisation of filter, as I
- think the dual-MAC architecture requires packed 16 bit coeffs.
-
- 2/ Block based update would be more efficient, as per comments above,
- could use dual MAC architecture.
-
- 3/ Look for same sample Blackfin LMS code, see if we can get dual-MAC
- packing.
-
- 4/ Execute the whole e/c in a block of say 20ms rather than sample
- by sample. Processing a few samples every ms is inefficient.
-*/
-
-#else
static inline void lms_adapt_bg(struct oslec_state *ec, int clean, int shift)
{
int i;
@@ -215,7 +143,6 @@ static inline void lms_adapt_bg(struct oslec_state *ec, int clean, int shift)
ec->fir_taps16[1][i] += (int16_t) ((exp + (1 << 14)) >> 15);
}
}
-#endif
static inline int top_bit(unsigned int bits)
{
diff --git a/drivers/misc/echo/fir.h b/drivers/misc/echo/fir.h
index 7b9fabf..4e0f365 100644
--- a/drivers/misc/echo/fir.h
+++ b/drivers/misc/echo/fir.h
@@ -27,14 +27,6 @@
#define _FIR_H_
/*
- Blackfin NOTES & IDEAS:
-
- A simple dot product function is used to implement the filter. This performs
- just one MAC/cycle which is inefficient but was easy to implement as a first
- pass. The current Blackfin code also uses an unrolled form of the filter
- history to avoid 0 length hardware loop issues. This is wasteful of
- memory.
-
Ideas for improvement:
1/ Rewrite filter for dual MAC inner loop. The issue here is handling
@@ -94,21 +86,13 @@ static inline const int16_t *fir16_create(struct fir16_state_t *fir,
fir->taps = taps;
fir->curr_pos = taps - 1;
fir->coeffs = coeffs;
-#if defined(__bfin__)
- fir->history = kcalloc(2 * taps, sizeof(int16_t), GFP_KERNEL);
-#else
fir->history = kcalloc(taps, sizeof(int16_t), GFP_KERNEL);
-#endif
return fir->history;
}
static inline void fir16_flush(struct fir16_state_t *fir)
{
-#if defined(__bfin__)
- memset(fir->history, 0, 2 * fir->taps * sizeof(int16_t));
-#else
memset(fir->history, 0, fir->taps * sizeof(int16_t));
-#endif
}
static inline void fir16_free(struct fir16_state_t *fir)
@@ -116,42 +100,9 @@ static inline void fir16_free(struct fir16_state_t *fir)
kfree(fir->history);
}
-#ifdef __bfin__
-static inline int32_t dot_asm(short *x, short *y, int len)
-{
- int dot;
-
- len--;
-
- __asm__("I0 = %1;\n\t"
- "I1 = %2;\n\t"
- "A0 = 0;\n\t"
- "R0.L = W[I0++] || R1.L = W[I1++];\n\t"
- "LOOP dot%= LC0 = %3;\n\t"
- "LOOP_BEGIN dot%=;\n\t"
- "A0 += R0.L * R1.L (IS) || R0.L = W[I0++] || R1.L = W[I1++];\n\t"
- "LOOP_END dot%=;\n\t"
- "A0 += R0.L*R1.L (IS);\n\t"
- "R0 = A0;\n\t"
- "%0 = R0;\n\t"
- : "=&d"(dot)
- : "a"(x), "a"(y), "a"(len)
- : "I0", "I1", "A1", "A0", "R0", "R1"
- );
-
- return dot;
-}
-#endif
-
static inline int16_t fir16(struct fir16_state_t *fir, int16_t sample)
{
int32_t y;
-#if defined(__bfin__)
- fir->history[fir->curr_pos] = sample;
- fir->history[fir->curr_pos + fir->taps] = sample;
- y = dot_asm((int16_t *) fir->coeffs, &fir->history[fir->curr_pos],
- fir->taps);
-#else
int i;
int offset1;
int offset2;
@@ -165,7 +116,6 @@ static inline int16_t fir16(struct fir16_state_t *fir, int16_t sample)
y += fir->coeffs[i] * fir->history[i - offset1];
for (; i >= 0; i--)
y += fir->coeffs[i] * fir->history[i + offset2];
-#endif
if (fir->curr_pos <= 0)
fir->curr_pos = fir->taps;
fir->curr_pos--;
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 12/28] video: Remove Blackfin video support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (9 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 11/28] misc: Remove Blackfin DSP echo support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 13/28] cpufreq: Remove Blackfin CPU frequency support Aaron Wu
` (15 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin video support
---
drivers/video/console/Kconfig | 2 +-
drivers/video/fbdev/Kconfig | 83 --
drivers/video/fbdev/Makefile | 5 -
drivers/video/fbdev/bf537-lq035.c | 891 --------------------
drivers/video/fbdev/bf54x-lq043fb.c | 764 -----------------
drivers/video/fbdev/bfin-lq035q1-fb.c | 864 --------------------
drivers/video/fbdev/bfin-t350mcqb-fb.c | 669 ---------------
drivers/video/fbdev/bfin_adv7393fb.c | 828 -------------------
drivers/video/fbdev/bfin_adv7393fb.h | 319 --------
drivers/video/logo/Kconfig | 10 -
drivers/video/logo/Makefile | 2 -
drivers/video/logo/logo.c | 8 -
drivers/video/logo/logo_blackfin_clut224.ppm | 1127 --------------------------
drivers/video/logo/logo_blackfin_vga16.ppm | 1127 --------------------------
include/linux/fb.h | 3 +-
include/linux/linux_logo.h | 2 -
16 files changed, 2 insertions(+), 6702 deletions(-)
delete mode 100644 drivers/video/fbdev/bf537-lq035.c
delete mode 100644 drivers/video/fbdev/bf54x-lq043fb.c
delete mode 100644 drivers/video/fbdev/bfin-lq035q1-fb.c
delete mode 100644 drivers/video/fbdev/bfin-t350mcqb-fb.c
delete mode 100644 drivers/video/fbdev/bfin_adv7393fb.c
delete mode 100644 drivers/video/fbdev/bfin_adv7393fb.h
delete mode 100644 drivers/video/logo/logo_blackfin_clut224.ppm
delete mode 100644 drivers/video/logo/logo_blackfin_vga16.ppm
diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 7f1f1fb..8309b04 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -7,7 +7,7 @@ menu "Console display driver support"
config VGA_CONSOLE
bool "VGA text console" if EXPERT || !X86
depends on !4xx && !PPC_8xx && !SPARC && !M68K && !PARISC && !FRV && \
- !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && !CRIS && \
+ !SUPERH && !AVR32 && !MN10300 && !CRIS && \
(!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) && \
!ARM64 && !ARC && !MICROBLAZE && !OPENRISC
default y
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index 11e699f..b52a459 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -580,77 +580,6 @@ config FB_VGA16
To compile this driver as a module, choose M here: the
module will be called vga16fb.
-config FB_BF54X_LQ043
- tristate "SHARP LQ043 TFT LCD (BF548 EZKIT)"
- depends on FB && (BF54x) && !BF542
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
- help
- This is the framebuffer device driver for a SHARP LQ043T1DG01 TFT LCD
-
-config FB_BFIN_T350MCQB
- tristate "Varitronix COG-T350MCQB TFT LCD display (BF527 EZKIT)"
- depends on FB && BLACKFIN
- select BFIN_GPTIMERS
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
- help
- This is the framebuffer device driver for a Varitronix VL-PS-COG-T350MCQB-01 display TFT LCD
- This display is a QVGA 320x240 24-bit RGB display interfaced by an 8-bit wide PPI
- It uses PPI[0..7] PPI_FS1, PPI_FS2 and PPI_CLK.
-
-config FB_BFIN_LQ035Q1
- tristate "SHARP LQ035Q1DH02 TFT LCD"
- depends on FB && BLACKFIN && SPI
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
- select BFIN_GPTIMERS
- help
- This is the framebuffer device driver for a SHARP LQ035Q1DH02 TFT display found on
- the Blackfin Landscape LCD EZ-Extender Card.
- This display is a QVGA 320x240 18-bit RGB display interfaced by an 16-bit wide PPI
- It uses PPI[0..15] PPI_FS1, PPI_FS2 and PPI_CLK.
-
- To compile this driver as a module, choose M here: the
- module will be called bfin-lq035q1-fb.
-
-config FB_BF537_LQ035
- tristate "SHARP LQ035 TFT LCD (BF537 STAMP)"
- depends on FB && (BF534 || BF536 || BF537) && I2C_BLACKFIN_TWI
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
- select BFIN_GPTIMERS
- help
- This is the framebuffer device for a SHARP LQ035Q7DB03 TFT LCD
- attached to a BF537.
-
- To compile this driver as a module, choose M here: the
- module will be called bf537-lq035.
-
-config FB_BFIN_7393
- tristate "Blackfin ADV7393 Video encoder"
- depends on FB && BLACKFIN
- select I2C
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
- help
- This is the framebuffer device for a ADV7393 video encoder
- attached to a Blackfin on the PPI port.
- If your Blackfin board has a ADV7393 select Y.
-
- To compile this driver as a module, choose M here: the
- module will be called bfin_adv7393fb.
-
-choice
- prompt "Video mode support"
- depends on FB_BFIN_7393
- default NTSC
-
config NTSC
bool 'NTSC 720x480'
@@ -671,18 +600,6 @@ config PAL_YCBCR
endchoice
-choice
- prompt "Size of ADV7393 frame buffer memory Single/Double Size"
- depends on (FB_BFIN_7393)
- default ADV7393_1XMEM
-
-config ADV7393_1XMEM
- bool 'Single'
-
-config ADV7393_2XMEM
- bool 'Double'
-endchoice
-
config FB_STI
tristate "HP STI frame buffer device support"
depends on FB && PARISC
diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile
index 115961e..55282a2 100644
--- a/drivers/video/fbdev/Makefile
+++ b/drivers/video/fbdev/Makefile
@@ -136,11 +136,6 @@ obj-$(CONFIG_FB_VESA) += vesafb.o
obj-$(CONFIG_FB_EFI) += efifb.o
obj-$(CONFIG_FB_VGA16) += vga16fb.o
obj-$(CONFIG_FB_OF) += offb.o
-obj-$(CONFIG_FB_BF537_LQ035) += bf537-lq035.o
-obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o
-obj-$(CONFIG_FB_BFIN_LQ035Q1) += bfin-lq035q1-fb.o
-obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o
-obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o
obj-$(CONFIG_FB_MX3) += mx3fb.o
obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o
obj-$(CONFIG_FB_MXS) += mxsfb.o
diff --git a/drivers/video/fbdev/bf537-lq035.c b/drivers/video/fbdev/bf537-lq035.c
deleted file mode 100644
index ef29fb4..0000000
--- a/drivers/video/fbdev/bf537-lq035.c
+++ /dev/null
@@ -1,891 +0,0 @@
-/*
- * Analog Devices Blackfin(BF537 STAMP) + SHARP TFT LCD.
- * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:tft-lcd
- *
- * Copyright 2006-2010 Analog Devices Inc.
- * Licensed under the GPL-2.
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/fb.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/timer.h>
-#include <linux/device.h>
-#include <linux/backlight.h>
-#include <linux/lcd.h>
-#include <linux/i2c.h>
-#include <linux/spinlock.h>
-#include <linux/dma-mapping.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-
-#include <asm/blackfin.h>
-#include <asm/irq.h>
-#include <asm/dpmc.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define NO_BL 1
-
-#define MAX_BRIGHENESS 95
-#define MIN_BRIGHENESS 5
-#define NBR_PALETTE 256
-
-static const unsigned short ppi_pins[] = {
- P_PPI0_CLK, P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, 0
-};
-
-static unsigned char *fb_buffer; /* RGB Buffer */
-static unsigned long *dma_desc_table;
-static int t_conf_done, lq035_open_cnt;
-static DEFINE_SPINLOCK(bfin_lq035_lock);
-
-static int landscape;
-module_param(landscape, int, 0);
-MODULE_PARM_DESC(landscape,
- "LANDSCAPE use 320x240 instead of Native 240x320 Resolution");
-
-static int bgr;
-module_param(bgr, int, 0);
-MODULE_PARM_DESC(bgr,
- "BGR use 16-bit BGR-565 instead of RGB-565");
-
-static int nocursor = 1;
-module_param(nocursor, int, 0644);
-MODULE_PARM_DESC(nocursor, "cursor enable/disable");
-
-static unsigned long current_brightness; /* backlight */
-
-/* AD5280 vcomm */
-static unsigned char vcomm_value = 150;
-static struct i2c_client *ad5280_client;
-
-static void set_vcomm(void)
-{
- int nr;
-
- if (!ad5280_client)
- return;
-
- nr = i2c_smbus_write_byte_data(ad5280_client, 0x00, vcomm_value);
- if (nr)
- pr_err("i2c_smbus_write_byte_data fail: %d\n", nr);
-}
-
-static int ad5280_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int ret;
- if (!i2c_check_functionality(client->adapter,
- I2C_FUNC_SMBUS_BYTE_DATA)) {
- dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
- return -EIO;
- }
-
- ret = i2c_smbus_write_byte_data(client, 0x00, vcomm_value);
- if (ret) {
- dev_err(&client->dev, "write fail: %d\n", ret);
- return ret;
- }
-
- ad5280_client = client;
-
- return 0;
-}
-
-static int ad5280_remove(struct i2c_client *client)
-{
- ad5280_client = NULL;
- return 0;
-}
-
-static const struct i2c_device_id ad5280_id[] = {
- {"bf537-lq035-ad5280", 0},
- {}
-};
-
-MODULE_DEVICE_TABLE(i2c, ad5280_id);
-
-static struct i2c_driver ad5280_driver = {
- .driver = {
- .name = "bf537-lq035-ad5280",
- },
- .probe = ad5280_probe,
- .remove = ad5280_remove,
- .id_table = ad5280_id,
-};
-
-#ifdef CONFIG_PNAV10
-#define MOD GPIO_PH13
-
-#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER0_CONFIG
-#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER0_WIDTH
-#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER0_PERIOD
-#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER0_COUNTER
-#define TIMDIS_LP TIMDIS0
-#define TIMEN_LP TIMEN0
-
-#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
-#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
-#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
-#define TIMDIS_SPS TIMDIS1
-#define TIMEN_SPS TIMEN1
-
-#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER5_CONFIG
-#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER5_WIDTH
-#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER5_PERIOD
-#define TIMDIS_SP TIMDIS5
-#define TIMEN_SP TIMEN5
-
-#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER2_CONFIG
-#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER2_WIDTH
-#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER2_PERIOD
-#define TIMDIS_PS_CLS TIMDIS2
-#define TIMEN_PS_CLS TIMEN2
-
-#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER3_CONFIG
-#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER3_WIDTH
-#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER3_PERIOD
-#define TIMDIS_REV TIMDIS3
-#define TIMEN_REV TIMEN3
-#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER3_COUNTER
-
-#define FREQ_PPI_CLK (5*1024*1024) /* PPI_CLK 5MHz */
-
-#define TIMERS {P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR5, 0}
-
-#else
-
-#define UD GPIO_PF13 /* Up / Down */
-#define MOD GPIO_PF10
-#define LBR GPIO_PF14 /* Left Right */
-
-#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER6_CONFIG
-#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER6_WIDTH
-#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER6_PERIOD
-#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER6_COUNTER
-#define TIMDIS_LP TIMDIS6
-#define TIMEN_LP TIMEN6
-
-#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
-#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
-#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
-#define TIMDIS_SPS TIMDIS1
-#define TIMEN_SPS TIMEN1
-
-#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER0_CONFIG
-#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER0_WIDTH
-#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER0_PERIOD
-#define TIMDIS_SP TIMDIS0
-#define TIMEN_SP TIMEN0
-
-#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER7_CONFIG
-#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER7_WIDTH
-#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER7_PERIOD
-#define TIMDIS_PS_CLS TIMDIS7
-#define TIMEN_PS_CLS TIMEN7
-
-#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER5_CONFIG
-#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER5_WIDTH
-#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER5_PERIOD
-#define TIMDIS_REV TIMDIS5
-#define TIMEN_REV TIMEN5
-#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER5_COUNTER
-
-#define FREQ_PPI_CLK (6*1000*1000) /* PPI_CLK 6MHz */
-#define TIMERS {P_TMR0, P_TMR1, P_TMR5, P_TMR6, P_TMR7, 0}
-
-#endif
-
-#define LCD_X_RES 240 /* Horizontal Resolution */
-#define LCD_Y_RES 320 /* Vertical Resolution */
-
-#define LCD_BBP 16 /* Bit Per Pixel */
-
-/* the LCD and the DMA start counting differently;
- * since one starts at 0 and the other starts at 1,
- * we have a difference of 1 between START_LINES
- * and U_LINES.
- */
-#define START_LINES 8 /* lines for field flyback or field blanking signal */
-#define U_LINES 9 /* number of undisplayed blanking lines */
-
-#define FRAMES_PER_SEC (60)
-
-#define DCLKS_PER_FRAME (FREQ_PPI_CLK/FRAMES_PER_SEC)
-#define DCLKS_PER_LINE (DCLKS_PER_FRAME/(LCD_Y_RES+U_LINES))
-
-#define PPI_CONFIG_VALUE (PORT_DIR|XFR_TYPE|DLEN_16|POLS)
-#define PPI_DELAY_VALUE (0)
-#define TIMER_CONFIG (PWM_OUT|PERIOD_CNT|TIN_SEL|CLK_SEL)
-
-#define ACTIVE_VIDEO_MEM_OFFSET (LCD_X_RES*START_LINES*(LCD_BBP/8))
-#define ACTIVE_VIDEO_MEM_SIZE (LCD_Y_RES*LCD_X_RES*(LCD_BBP/8))
-#define TOTAL_VIDEO_MEM_SIZE ((LCD_Y_RES+U_LINES)*LCD_X_RES*(LCD_BBP/8))
-#define TOTAL_DMA_DESC_SIZE (2 * sizeof(u32) * (LCD_Y_RES + U_LINES))
-
-static void start_timers(void) /* CHECK with HW */
-{
- unsigned long flags;
-
- local_irq_save(flags);
-
- bfin_write_TIMER_ENABLE(TIMEN_REV);
- SSYNC();
-
- while (bfin_read_TIMER_REV_COUNTER() <= 11)
- continue;
- bfin_write_TIMER_ENABLE(TIMEN_LP);
- SSYNC();
-
- while (bfin_read_TIMER_LP_COUNTER() < 3)
- continue;
- bfin_write_TIMER_ENABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS);
- SSYNC();
- t_conf_done = 1;
- local_irq_restore(flags);
-}
-
-static void config_timers(void)
-{
- /* Stop timers */
- bfin_write_TIMER_DISABLE(TIMDIS_SP|TIMDIS_SPS|TIMDIS_REV|
- TIMDIS_LP|TIMDIS_PS_CLS);
- SSYNC();
-
- /* LP, timer 6 */
- bfin_write_TIMER_LP_CONFIG(TIMER_CONFIG|PULSE_HI);
- bfin_write_TIMER_LP_WIDTH(1);
-
- bfin_write_TIMER_LP_PERIOD(DCLKS_PER_LINE);
- SSYNC();
-
- /* SPS, timer 1 */
- bfin_write_TIMER_SPS_CONFIG(TIMER_CONFIG|PULSE_HI);
- bfin_write_TIMER_SPS_WIDTH(DCLKS_PER_LINE*2);
- bfin_write_TIMER_SPS_PERIOD((DCLKS_PER_LINE * (LCD_Y_RES+U_LINES)));
- SSYNC();
-
- /* SP, timer 0 */
- bfin_write_TIMER_SP_CONFIG(TIMER_CONFIG|PULSE_HI);
- bfin_write_TIMER_SP_WIDTH(1);
- bfin_write_TIMER_SP_PERIOD(DCLKS_PER_LINE);
- SSYNC();
-
- /* PS & CLS, timer 7 */
- bfin_write_TIMER_PS_CLS_CONFIG(TIMER_CONFIG);
- bfin_write_TIMER_PS_CLS_WIDTH(LCD_X_RES + START_LINES);
- bfin_write_TIMER_PS_CLS_PERIOD(DCLKS_PER_LINE);
-
- SSYNC();
-
-#ifdef NO_BL
- /* REV, timer 5 */
- bfin_write_TIMER_REV_CONFIG(TIMER_CONFIG|PULSE_HI);
-
- bfin_write_TIMER_REV_WIDTH(DCLKS_PER_LINE);
- bfin_write_TIMER_REV_PERIOD(DCLKS_PER_LINE*2);
-
- SSYNC();
-#endif
-}
-
-static void config_ppi(void)
-{
- bfin_write_PPI_DELAY(PPI_DELAY_VALUE);
- bfin_write_PPI_COUNT(LCD_X_RES-1);
- /* 0x10 -> PORT_CFG -> 2 or 3 frame syncs */
- bfin_write_PPI_CONTROL((PPI_CONFIG_VALUE|0x10) & (~POLS));
-}
-
-static int config_dma(void)
-{
- u32 i;
-
- if (landscape) {
-
- for (i = 0; i < U_LINES; ++i) {
- /* blanking lines point to first line of fb_buffer */
- dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2];
- dma_desc_table[2*i+1] = (unsigned long)fb_buffer;
- }
-
- for (i = U_LINES; i < U_LINES + LCD_Y_RES; ++i) {
- /* visible lines */
- dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2];
- dma_desc_table[2*i+1] = (unsigned long)fb_buffer +
- (LCD_Y_RES+U_LINES-1-i)*2;
- }
-
- /* last descriptor points to first */
- dma_desc_table[2*(LCD_Y_RES+U_LINES-1)] = (unsigned long)&dma_desc_table[0];
-
- set_dma_x_count(CH_PPI, LCD_X_RES);
- set_dma_x_modify(CH_PPI, LCD_Y_RES * (LCD_BBP / 8));
- set_dma_y_count(CH_PPI, 0);
- set_dma_y_modify(CH_PPI, 0);
- set_dma_next_desc_addr(CH_PPI, (void *)dma_desc_table[0]);
- set_dma_config(CH_PPI, DMAFLOW_LARGE | NDSIZE_4 | WDSIZE_16);
-
- } else {
-
- set_dma_config(CH_PPI, set_bfin_dma_config(DIR_READ,
- DMA_FLOW_AUTO,
- INTR_DISABLE,
- DIMENSION_2D,
- DATA_SIZE_16,
- DMA_NOSYNC_KEEP_DMA_BUF));
- set_dma_x_count(CH_PPI, LCD_X_RES);
- set_dma_x_modify(CH_PPI, LCD_BBP / 8);
- set_dma_y_count(CH_PPI, LCD_Y_RES+U_LINES);
- set_dma_y_modify(CH_PPI, LCD_BBP / 8);
- set_dma_start_addr(CH_PPI, (unsigned long) fb_buffer);
- }
-
- return 0;
-}
-
-static int request_ports(void)
-{
- u16 tmr_req[] = TIMERS;
-
- /*
- UD: PF13
- MOD: PF10
- LBR: PF14
- PPI_CLK: PF15
- */
-
- if (peripheral_request_list(ppi_pins, KBUILD_MODNAME)) {
- pr_err("requesting PPI peripheral failed\n");
- return -EBUSY;
- }
-
- if (peripheral_request_list(tmr_req, KBUILD_MODNAME)) {
- peripheral_free_list(ppi_pins);
- pr_err("requesting timer peripheral failed\n");
- return -EBUSY;
- }
-
-#if (defined(UD) && defined(LBR))
- if (gpio_request_one(UD, GPIOF_OUT_INIT_LOW, KBUILD_MODNAME)) {
- pr_err("requesting GPIO %d failed\n", UD);
- return -EBUSY;
- }
-
- if (gpio_request_one(LBR, GPIOF_OUT_INIT_HIGH, KBUILD_MODNAME)) {
- pr_err("requesting GPIO %d failed\n", LBR);
- gpio_free(UD);
- return -EBUSY;
- }
-#endif
-
- if (gpio_request_one(MOD, GPIOF_OUT_INIT_HIGH, KBUILD_MODNAME)) {
- pr_err("requesting GPIO %d failed\n", MOD);
-#if (defined(UD) && defined(LBR))
- gpio_free(LBR);
- gpio_free(UD);
-#endif
- return -EBUSY;
- }
-
- SSYNC();
- return 0;
-}
-
-static void free_ports(void)
-{
- u16 tmr_req[] = TIMERS;
-
- peripheral_free_list(ppi_pins);
- peripheral_free_list(tmr_req);
-
-#if defined(UD) && defined(LBR)
- gpio_free(LBR);
- gpio_free(UD);
-#endif
- gpio_free(MOD);
-}
-
-static struct fb_info bfin_lq035_fb;
-
-static struct fb_var_screeninfo bfin_lq035_fb_defined = {
- .bits_per_pixel = LCD_BBP,
- .activate = FB_ACTIVATE_TEST,
- .xres = LCD_X_RES, /*default portrait mode RGB*/
- .yres = LCD_Y_RES,
- .xres_virtual = LCD_X_RES,
- .yres_virtual = LCD_Y_RES,
- .height = -1,
- .width = -1,
- .left_margin = 0,
- .right_margin = 0,
- .upper_margin = 0,
- .lower_margin = 0,
- .red = {11, 5, 0},
- .green = {5, 6, 0},
- .blue = {0, 5, 0},
- .transp = {0, 0, 0},
-};
-
-static struct fb_fix_screeninfo bfin_lq035_fb_fix = {
- .id = KBUILD_MODNAME,
- .smem_len = ACTIVE_VIDEO_MEM_SIZE,
- .type = FB_TYPE_PACKED_PIXELS,
- .visual = FB_VISUAL_TRUECOLOR,
- .xpanstep = 0,
- .ypanstep = 0,
- .line_length = LCD_X_RES*(LCD_BBP/8),
- .accel = FB_ACCEL_NONE,
-};
-
-
-static int bfin_lq035_fb_open(struct fb_info *info, int user)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&bfin_lq035_lock, flags);
- lq035_open_cnt++;
- spin_unlock_irqrestore(&bfin_lq035_lock, flags);
-
- if (lq035_open_cnt <= 1) {
- bfin_write_PPI_CONTROL(0);
- SSYNC();
-
- set_vcomm();
- config_dma();
- config_ppi();
-
- /* start dma */
- enable_dma(CH_PPI);
- SSYNC();
- bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
- SSYNC();
-
- if (!t_conf_done) {
- config_timers();
- start_timers();
- }
- /* gpio_set_value(MOD,1); */
- }
-
- return 0;
-}
-
-static int bfin_lq035_fb_release(struct fb_info *info, int user)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&bfin_lq035_lock, flags);
- lq035_open_cnt--;
- spin_unlock_irqrestore(&bfin_lq035_lock, flags);
-
-
- if (lq035_open_cnt <= 0) {
-
- bfin_write_PPI_CONTROL(0);
- SSYNC();
-
- disable_dma(CH_PPI);
- }
-
- return 0;
-}
-
-
-static int bfin_lq035_fb_check_var(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
- switch (var->bits_per_pixel) {
- case 16:/* DIRECTCOLOUR, 64k */
- var->red.offset = info->var.red.offset;
- var->green.offset = info->var.green.offset;
- var->blue.offset = info->var.blue.offset;
- var->red.length = info->var.red.length;
- var->green.length = info->var.green.length;
- var->blue.length = info->var.blue.length;
- var->transp.offset = 0;
- var->transp.length = 0;
- var->transp.msb_right = 0;
- var->red.msb_right = 0;
- var->green.msb_right = 0;
- var->blue.msb_right = 0;
- break;
- default:
- pr_debug("%s: depth not supported: %u BPP\n", __func__,
- var->bits_per_pixel);
- return -EINVAL;
- }
-
- if (info->var.xres != var->xres ||
- info->var.yres != var->yres ||
- info->var.xres_virtual != var->xres_virtual ||
- info->var.yres_virtual != var->yres_virtual) {
- pr_debug("%s: Resolution not supported: X%u x Y%u\n",
- __func__, var->xres, var->yres);
- return -EINVAL;
- }
-
- /*
- * Memory limit
- */
-
- if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
- pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
- __func__, var->yres_virtual);
- return -ENOMEM;
- }
-
- return 0;
-}
-
-static int bfin_lq035_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
-{
- if (nocursor)
- return 0;
- else
- return -EINVAL; /* just to force soft_cursor() call */
-}
-
-static int bfin_lq035_fb_setcolreg(u_int regno, u_int red, u_int green,
- u_int blue, u_int transp,
- struct fb_info *info)
-{
- if (regno >= NBR_PALETTE)
- return -EINVAL;
-
- if (info->var.grayscale)
- /* grayscale = 0.30*R + 0.59*G + 0.11*B */
- red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
-
- if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
-
- u32 value;
- /* Place color in the pseudopalette */
- if (regno > 16)
- return -EINVAL;
-
- red >>= (16 - info->var.red.length);
- green >>= (16 - info->var.green.length);
- blue >>= (16 - info->var.blue.length);
-
- value = (red << info->var.red.offset) |
- (green << info->var.green.offset)|
- (blue << info->var.blue.offset);
- value &= 0xFFFF;
-
- ((u32 *) (info->pseudo_palette))[regno] = value;
-
- }
-
- return 0;
-}
-
-static struct fb_ops bfin_lq035_fb_ops = {
- .owner = THIS_MODULE,
- .fb_open = bfin_lq035_fb_open,
- .fb_release = bfin_lq035_fb_release,
- .fb_check_var = bfin_lq035_fb_check_var,
- .fb_fillrect = cfb_fillrect,
- .fb_copyarea = cfb_copyarea,
- .fb_imageblit = cfb_imageblit,
- .fb_cursor = bfin_lq035_fb_cursor,
- .fb_setcolreg = bfin_lq035_fb_setcolreg,
-};
-
-static int bl_get_brightness(struct backlight_device *bd)
-{
- return current_brightness;
-}
-
-static const struct backlight_ops bfin_lq035fb_bl_ops = {
- .get_brightness = bl_get_brightness,
-};
-
-static struct backlight_device *bl_dev;
-
-static int bfin_lcd_get_power(struct lcd_device *dev)
-{
- return 0;
-}
-
-static int bfin_lcd_set_power(struct lcd_device *dev, int power)
-{
- return 0;
-}
-
-static int bfin_lcd_get_contrast(struct lcd_device *dev)
-{
- return (int)vcomm_value;
-}
-
-static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast)
-{
- if (contrast > 255)
- contrast = 255;
- if (contrast < 0)
- contrast = 0;
-
- vcomm_value = (unsigned char)contrast;
- set_vcomm();
- return 0;
-}
-
-static int bfin_lcd_check_fb(struct lcd_device *lcd, struct fb_info *fi)
-{
- if (!fi || (fi == &bfin_lq035_fb))
- return 1;
- return 0;
-}
-
-static struct lcd_ops bfin_lcd_ops = {
- .get_power = bfin_lcd_get_power,
- .set_power = bfin_lcd_set_power,
- .get_contrast = bfin_lcd_get_contrast,
- .set_contrast = bfin_lcd_set_contrast,
- .check_fb = bfin_lcd_check_fb,
-};
-
-static struct lcd_device *lcd_dev;
-
-static int bfin_lq035_probe(struct platform_device *pdev)
-{
- struct backlight_properties props;
- dma_addr_t dma_handle;
- int ret;
-
- if (request_dma(CH_PPI, KBUILD_MODNAME)) {
- pr_err("couldn't request PPI DMA\n");
- return -EFAULT;
- }
-
- if (request_ports()) {
- pr_err("couldn't request gpio port\n");
- ret = -EFAULT;
- goto out_ports;
- }
-
- fb_buffer = dma_alloc_coherent(NULL, TOTAL_VIDEO_MEM_SIZE,
- &dma_handle, GFP_KERNEL);
- if (fb_buffer == NULL) {
- pr_err("couldn't allocate dma buffer\n");
- ret = -ENOMEM;
- goto out_dma_coherent;
- }
-
- if (L1_DATA_A_LENGTH)
- dma_desc_table = l1_data_sram_zalloc(TOTAL_DMA_DESC_SIZE);
- else
- dma_desc_table = dma_alloc_coherent(NULL, TOTAL_DMA_DESC_SIZE,
- &dma_handle, 0);
-
- if (dma_desc_table == NULL) {
- pr_err("couldn't allocate dma descriptor\n");
- ret = -ENOMEM;
- goto out_table;
- }
-
- bfin_lq035_fb.screen_base = (void *)fb_buffer;
- bfin_lq035_fb_fix.smem_start = (int)fb_buffer;
- if (landscape) {
- bfin_lq035_fb_defined.xres = LCD_Y_RES;
- bfin_lq035_fb_defined.yres = LCD_X_RES;
- bfin_lq035_fb_defined.xres_virtual = LCD_Y_RES;
- bfin_lq035_fb_defined.yres_virtual = LCD_X_RES;
-
- bfin_lq035_fb_fix.line_length = LCD_Y_RES*(LCD_BBP/8);
- } else {
- bfin_lq035_fb.screen_base += ACTIVE_VIDEO_MEM_OFFSET;
- bfin_lq035_fb_fix.smem_start += ACTIVE_VIDEO_MEM_OFFSET;
- }
-
- bfin_lq035_fb_defined.green.msb_right = 0;
- bfin_lq035_fb_defined.red.msb_right = 0;
- bfin_lq035_fb_defined.blue.msb_right = 0;
- bfin_lq035_fb_defined.green.offset = 5;
- bfin_lq035_fb_defined.green.length = 6;
- bfin_lq035_fb_defined.red.length = 5;
- bfin_lq035_fb_defined.blue.length = 5;
-
- if (bgr) {
- bfin_lq035_fb_defined.red.offset = 0;
- bfin_lq035_fb_defined.blue.offset = 11;
- } else {
- bfin_lq035_fb_defined.red.offset = 11;
- bfin_lq035_fb_defined.blue.offset = 0;
- }
-
- bfin_lq035_fb.fbops = &bfin_lq035_fb_ops;
- bfin_lq035_fb.var = bfin_lq035_fb_defined;
-
- bfin_lq035_fb.fix = bfin_lq035_fb_fix;
- bfin_lq035_fb.flags = FBINFO_DEFAULT;
-
-
- bfin_lq035_fb.pseudo_palette = devm_kzalloc(&pdev->dev,
- sizeof(u32) * 16,
- GFP_KERNEL);
- if (bfin_lq035_fb.pseudo_palette == NULL) {
- pr_err("failed to allocate pseudo_palette\n");
- ret = -ENOMEM;
- goto out_table;
- }
-
- if (fb_alloc_cmap(&bfin_lq035_fb.cmap, NBR_PALETTE, 0) < 0) {
- pr_err("failed to allocate colormap (%d entries)\n",
- NBR_PALETTE);
- ret = -EFAULT;
- goto out_table;
- }
-
- if (register_framebuffer(&bfin_lq035_fb) < 0) {
- pr_err("unable to register framebuffer\n");
- ret = -EINVAL;
- goto out_reg;
- }
-
- i2c_add_driver(&ad5280_driver);
-
- memset(&props, 0, sizeof(props));
- props.type = BACKLIGHT_RAW;
- props.max_brightness = MAX_BRIGHENESS;
- bl_dev = backlight_device_register("bf537-bl", NULL, NULL,
- &bfin_lq035fb_bl_ops, &props);
-
- lcd_dev = lcd_device_register(KBUILD_MODNAME, &pdev->dev, NULL,
- &bfin_lcd_ops);
- if (IS_ERR(lcd_dev)) {
- pr_err("unable to register lcd\n");
- ret = PTR_ERR(lcd_dev);
- goto out_lcd;
- }
- lcd_dev->props.max_contrast = 255,
-
- pr_info("initialized");
-
- return 0;
-out_lcd:
- unregister_framebuffer(&bfin_lq035_fb);
-out_reg:
- fb_dealloc_cmap(&bfin_lq035_fb.cmap);
-out_table:
- dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
- fb_buffer = NULL;
-out_dma_coherent:
- free_ports();
-out_ports:
- free_dma(CH_PPI);
- return ret;
-}
-
-static int bfin_lq035_remove(struct platform_device *pdev)
-{
- if (fb_buffer != NULL)
- dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
-
- if (L1_DATA_A_LENGTH)
- l1_data_sram_free(dma_desc_table);
- else
- dma_free_coherent(NULL, TOTAL_DMA_DESC_SIZE, NULL, 0);
-
- bfin_write_TIMER_DISABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS|
- TIMEN_LP|TIMEN_REV);
- t_conf_done = 0;
-
- free_dma(CH_PPI);
-
-
- fb_dealloc_cmap(&bfin_lq035_fb.cmap);
-
-
- lcd_device_unregister(lcd_dev);
- backlight_device_unregister(bl_dev);
-
- unregister_framebuffer(&bfin_lq035_fb);
- i2c_del_driver(&ad5280_driver);
-
- free_ports();
-
- pr_info("unregistered LCD driver\n");
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int bfin_lq035_suspend(struct platform_device *pdev, pm_message_t state)
-{
- if (lq035_open_cnt > 0) {
- bfin_write_PPI_CONTROL(0);
- SSYNC();
- disable_dma(CH_PPI);
- }
-
- return 0;
-}
-
-static int bfin_lq035_resume(struct platform_device *pdev)
-{
- if (lq035_open_cnt > 0) {
- bfin_write_PPI_CONTROL(0);
- SSYNC();
-
- config_dma();
- config_ppi();
-
- enable_dma(CH_PPI);
- bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
- SSYNC();
-
- config_timers();
- start_timers();
- } else {
- t_conf_done = 0;
- }
-
- return 0;
-}
-#else
-# define bfin_lq035_suspend NULL
-# define bfin_lq035_resume NULL
-#endif
-
-static struct platform_driver bfin_lq035_driver = {
- .probe = bfin_lq035_probe,
- .remove = bfin_lq035_remove,
- .suspend = bfin_lq035_suspend,
- .resume = bfin_lq035_resume,
- .driver = {
- .name = KBUILD_MODNAME,
- },
-};
-
-static int __init bfin_lq035_driver_init(void)
-{
- request_module("i2c-bfin-twi");
- return platform_driver_register(&bfin_lq035_driver);
-}
-module_init(bfin_lq035_driver_init);
-
-static void __exit bfin_lq035_driver_cleanup(void)
-{
- platform_driver_unregister(&bfin_lq035_driver);
-}
-module_exit(bfin_lq035_driver_cleanup);
-
-MODULE_DESCRIPTION("SHARP LQ035Q7DB03 TFT LCD Driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/bf54x-lq043fb.c b/drivers/video/fbdev/bf54x-lq043fb.c
deleted file mode 100644
index 8f1f97c..0000000
--- a/drivers/video/fbdev/bf54x-lq043fb.c
+++ /dev/null
@@ -1,764 +0,0 @@
-/*
- * File: drivers/video/bf54x-lq043.c
- * Based on:
- * Author: Michael Hennerich <hennerich@blackfin.uclinux.org>
- *
- * Created:
- * Description: ADSP-BF54x Framebuffer driver
- *
- *
- * Modified:
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/fb.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/timer.h>
-#include <linux/device.h>
-#include <linux/backlight.h>
-#include <linux/lcd.h>
-#include <linux/spinlock.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-
-#include <asm/blackfin.h>
-#include <asm/irq.h>
-#include <asm/dpmc.h>
-#include <asm/dma-mapping.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#include <mach/bf54x-lq043.h>
-
-#define NO_BL_SUPPORT
-
-#define DRIVER_NAME "bf54x-lq043"
-static char driver_name[] = DRIVER_NAME;
-
-#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
-
-#define EPPI0_18 {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, \
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, \
- P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, P_PPI0_D16, P_PPI0_D17, 0}
-
-#define EPPI0_24 {P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23, 0}
-
-struct bfin_bf54xfb_info {
- struct fb_info *fb;
- struct device *dev;
-
- struct bfin_bf54xfb_mach_info *mach_info;
-
- unsigned char *fb_buffer; /* RGB Buffer */
-
- dma_addr_t dma_handle;
- int lq043_open_cnt;
- int irq;
- spinlock_t lock; /* lock */
-};
-
-static int nocursor;
-module_param(nocursor, int, 0644);
-MODULE_PARM_DESC(nocursor, "cursor enable/disable");
-
-static int outp_rgb666;
-module_param(outp_rgb666, int, 0);
-MODULE_PARM_DESC(outp_rgb666, "Output 18-bit RGB666");
-
-#define LCD_X_RES 480 /*Horizontal Resolution */
-#define LCD_Y_RES 272 /* Vertical Resolution */
-
-#define LCD_BPP 24 /* Bit Per Pixel */
-#define DMA_BUS_SIZE 32
-
-/* -- Horizontal synchronizing --
- *
- * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
- * (LCY-W-06602A Page 9 of 22)
- *
- * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
- *
- * Period TH - 525 - Clock
- * Pulse width THp - 41 - Clock
- * Horizontal period THd - 480 - Clock
- * Back porch THb - 2 - Clock
- * Front porch THf - 2 - Clock
- *
- * -- Vertical synchronizing --
- * Period TV - 286 - Line
- * Pulse width TVp - 10 - Line
- * Vertical period TVd - 272 - Line
- * Back porch TVb - 2 - Line
- * Front porch TVf - 2 - Line
- */
-
-#define LCD_CLK (8*1000*1000) /* 8MHz */
-
-/* # active data to transfer after Horizontal Delay clock */
-#define EPPI_HCOUNT LCD_X_RES
-
-/* # active lines to transfer after Vertical Delay clock */
-#define EPPI_VCOUNT LCD_Y_RES
-
-/* Samples per Line = 480 (active data) + 45 (padding) */
-#define EPPI_LINE 525
-
-/* Lines per Frame = 272 (active data) + 14 (padding) */
-#define EPPI_FRAME 286
-
-/* FS1 (Hsync) Width (Typical)*/
-#define EPPI_FS1W_HBL 41
-
-/* FS1 (Hsync) Period (Typical) */
-#define EPPI_FS1P_AVPL EPPI_LINE
-
-/* Horizontal Delay clock after assertion of Hsync (Typical) */
-#define EPPI_HDELAY 43
-
-/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
-#define EPPI_FS2W_LVB (EPPI_LINE * 10)
-
- /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
-#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
-
-/* Vertical Delay after assertion of Vsync (2 Lines) */
-#define EPPI_VDELAY 12
-
-#define EPPI_CLIP 0xFF00FF00
-
-/* EPPI Control register configuration value for RGB out
- * - EPPI as Output
- * GP 2 frame sync mode,
- * Internal Clock generation disabled, Internal FS generation enabled,
- * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
- * FS1 & FS2 are active high,
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
- * Swapping Enabled,
- * One (DMA) Channel Mode,
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- * Regular watermark - when FIFO is 100% full,
- * Urgent watermark - when FIFO is 75% full
- */
-
-#define EPPI_CONTROL (0x20136E2E | SWAPEN)
-
-static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
-{
- u32 sclk = get_sclk();
-
- /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
-
- return (((sclk / target_ppi_clk) / 2) - 1);
-}
-
-static void config_ppi(struct bfin_bf54xfb_info *fbi)
-{
-
- u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
-
- bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
- bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
- bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
- bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
- bfin_write_EPPI0_CLIP(EPPI_CLIP);
-
- bfin_write_EPPI0_FRAME(EPPI_FRAME);
- bfin_write_EPPI0_LINE(EPPI_LINE);
-
- bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
- bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
- bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
- bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
-
- bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
-
-/*
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- */
- if (outp_rgb666)
- bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
- RGB_FMT_EN);
- else
- bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
- ~RGB_FMT_EN);
-
-
-}
-
-static int config_dma(struct bfin_bf54xfb_info *fbi)
-{
-
- set_dma_config(CH_EPPI0,
- set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
- INTR_DISABLE, DIMENSION_2D,
- DATA_SIZE_32,
- DMA_NOSYNC_KEEP_DMA_BUF));
- set_dma_x_count(CH_EPPI0, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
- set_dma_x_modify(CH_EPPI0, DMA_BUS_SIZE / 8);
- set_dma_y_count(CH_EPPI0, LCD_Y_RES);
- set_dma_y_modify(CH_EPPI0, DMA_BUS_SIZE / 8);
- set_dma_start_addr(CH_EPPI0, (unsigned long)fbi->fb_buffer);
-
- return 0;
-}
-
-static int request_ports(struct bfin_bf54xfb_info *fbi)
-{
-
- u16 eppi_req_18[] = EPPI0_18;
- u16 disp = fbi->mach_info->disp;
-
- if (gpio_request_one(disp, GPIOF_OUT_INIT_HIGH, DRIVER_NAME)) {
- printk(KERN_ERR "Requesting GPIO %d failed\n", disp);
- return -EFAULT;
- }
-
- if (peripheral_request_list(eppi_req_18, DRIVER_NAME)) {
- printk(KERN_ERR "Requesting Peripherals failed\n");
- gpio_free(disp);
- return -EFAULT;
- }
-
- if (!outp_rgb666) {
-
- u16 eppi_req_24[] = EPPI0_24;
-
- if (peripheral_request_list(eppi_req_24, DRIVER_NAME)) {
- printk(KERN_ERR "Requesting Peripherals failed\n");
- peripheral_free_list(eppi_req_18);
- gpio_free(disp);
- return -EFAULT;
- }
- }
-
- return 0;
-}
-
-static void free_ports(struct bfin_bf54xfb_info *fbi)
-{
-
- u16 eppi_req_18[] = EPPI0_18;
-
- gpio_free(fbi->mach_info->disp);
-
- peripheral_free_list(eppi_req_18);
-
- if (!outp_rgb666) {
- u16 eppi_req_24[] = EPPI0_24;
- peripheral_free_list(eppi_req_24);
- }
-}
-
-static int bfin_bf54x_fb_open(struct fb_info *info, int user)
-{
- struct bfin_bf54xfb_info *fbi = info->par;
-
- spin_lock(&fbi->lock);
- fbi->lq043_open_cnt++;
-
- if (fbi->lq043_open_cnt <= 1) {
-
- bfin_write_EPPI0_CONTROL(0);
- SSYNC();
-
- config_dma(fbi);
- config_ppi(fbi);
-
- /* start dma */
- enable_dma(CH_EPPI0);
- bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
- }
-
- spin_unlock(&fbi->lock);
-
- return 0;
-}
-
-static int bfin_bf54x_fb_release(struct fb_info *info, int user)
-{
- struct bfin_bf54xfb_info *fbi = info->par;
-
- spin_lock(&fbi->lock);
-
- fbi->lq043_open_cnt--;
-
- if (fbi->lq043_open_cnt <= 0) {
-
- bfin_write_EPPI0_CONTROL(0);
- SSYNC();
- disable_dma(CH_EPPI0);
- }
-
- spin_unlock(&fbi->lock);
-
- return 0;
-}
-
-static int bfin_bf54x_fb_check_var(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
-
- switch (var->bits_per_pixel) {
- case 24:/* TRUECOLOUR, 16m */
- var->red.offset = 16;
- var->green.offset = 8;
- var->blue.offset = 0;
- var->red.length = var->green.length = var->blue.length = 8;
- var->transp.offset = 0;
- var->transp.length = 0;
- var->transp.msb_right = 0;
- var->red.msb_right = 0;
- var->green.msb_right = 0;
- var->blue.msb_right = 0;
- break;
- default:
- pr_debug("%s: depth not supported: %u BPP\n", __func__,
- var->bits_per_pixel);
- return -EINVAL;
- }
-
- if (info->var.xres != var->xres || info->var.yres != var->yres ||
- info->var.xres_virtual != var->xres_virtual ||
- info->var.yres_virtual != var->yres_virtual) {
- pr_debug("%s: Resolution not supported: X%u x Y%u \n",
- __func__, var->xres, var->yres);
- return -EINVAL;
- }
-
- /*
- * Memory limit
- */
-
- if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
- pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
- __func__, var->yres_virtual);
- return -ENOMEM;
- }
-
- return 0;
-}
-
-int bfin_bf54x_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
-{
- if (nocursor)
- return 0;
- else
- return -EINVAL; /* just to force soft_cursor() call */
-}
-
-static int bfin_bf54x_fb_setcolreg(u_int regno, u_int red, u_int green,
- u_int blue, u_int transp,
- struct fb_info *info)
-{
- if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
- return -EINVAL;
-
- if (info->var.grayscale) {
- /* grayscale = 0.30*R + 0.59*G + 0.11*B */
- red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
- }
-
- if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
-
- u32 value;
- /* Place color in the pseudopalette */
- if (regno > 16)
- return -EINVAL;
-
- red >>= (16 - info->var.red.length);
- green >>= (16 - info->var.green.length);
- blue >>= (16 - info->var.blue.length);
-
- value = (red << info->var.red.offset) |
- (green << info->var.green.offset) |
- (blue << info->var.blue.offset);
- value &= 0xFFFFFF;
-
- ((u32 *) (info->pseudo_palette))[regno] = value;
-
- }
-
- return 0;
-}
-
-static struct fb_ops bfin_bf54x_fb_ops = {
- .owner = THIS_MODULE,
- .fb_open = bfin_bf54x_fb_open,
- .fb_release = bfin_bf54x_fb_release,
- .fb_check_var = bfin_bf54x_fb_check_var,
- .fb_fillrect = cfb_fillrect,
- .fb_copyarea = cfb_copyarea,
- .fb_imageblit = cfb_imageblit,
- .fb_cursor = bfin_bf54x_fb_cursor,
- .fb_setcolreg = bfin_bf54x_fb_setcolreg,
-};
-
-#ifndef NO_BL_SUPPORT
-static int bl_get_brightness(struct backlight_device *bd)
-{
- return 0;
-}
-
-static const struct backlight_ops bfin_lq043fb_bl_ops = {
- .get_brightness = bl_get_brightness,
-};
-
-static struct backlight_device *bl_dev;
-
-static int bfin_lcd_get_power(struct lcd_device *dev)
-{
- return 0;
-}
-
-static int bfin_lcd_set_power(struct lcd_device *dev, int power)
-{
- return 0;
-}
-
-static int bfin_lcd_get_contrast(struct lcd_device *dev)
-{
- return 0;
-}
-
-static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast)
-{
-
- return 0;
-}
-
-static int bfin_lcd_check_fb(struct lcd_device *dev, struct fb_info *fi)
-{
- if (!fi || (fi == &bfin_bf54x_fb))
- return 1;
- return 0;
-}
-
-static struct lcd_ops bfin_lcd_ops = {
- .get_power = bfin_lcd_get_power,
- .set_power = bfin_lcd_set_power,
- .get_contrast = bfin_lcd_get_contrast,
- .set_contrast = bfin_lcd_set_contrast,
- .check_fb = bfin_lcd_check_fb,
-};
-
-static struct lcd_device *lcd_dev;
-#endif
-
-static irqreturn_t bfin_bf54x_irq_error(int irq, void *dev_id)
-{
- /*struct bfin_bf54xfb_info *info = dev_id;*/
-
- u16 status = bfin_read_EPPI0_STATUS();
-
- bfin_write_EPPI0_STATUS(0xFFFF);
-
- if (status) {
- bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
- disable_dma(CH_EPPI0);
-
- /* start dma */
- enable_dma(CH_EPPI0);
- bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
- bfin_write_EPPI0_STATUS(0xFFFF);
- }
-
- return IRQ_HANDLED;
-}
-
-static int bfin_bf54x_probe(struct platform_device *pdev)
-{
-#ifndef NO_BL_SUPPORT
- struct backlight_properties props;
-#endif
- struct bfin_bf54xfb_info *info;
- struct fb_info *fbinfo;
- int ret;
-
- printk(KERN_INFO DRIVER_NAME ": FrameBuffer initializing...\n");
-
- if (request_dma(CH_EPPI0, "CH_EPPI0") < 0) {
- printk(KERN_ERR DRIVER_NAME
- ": couldn't request CH_EPPI0 DMA\n");
- ret = -EFAULT;
- goto out1;
- }
-
- fbinfo =
- framebuffer_alloc(sizeof(struct bfin_bf54xfb_info), &pdev->dev);
- if (!fbinfo) {
- ret = -ENOMEM;
- goto out2;
- }
-
- info = fbinfo->par;
- info->fb = fbinfo;
- info->dev = &pdev->dev;
- spin_lock_init(&info->lock);
-
- platform_set_drvdata(pdev, fbinfo);
-
- strcpy(fbinfo->fix.id, driver_name);
-
- info->mach_info = pdev->dev.platform_data;
-
- if (info->mach_info == NULL) {
- dev_err(&pdev->dev,
- "no platform data for lcd, cannot attach\n");
- ret = -EINVAL;
- goto out3;
- }
-
- fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
- fbinfo->fix.type_aux = 0;
- fbinfo->fix.xpanstep = 0;
- fbinfo->fix.ypanstep = 0;
- fbinfo->fix.ywrapstep = 0;
- fbinfo->fix.accel = FB_ACCEL_NONE;
- fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
-
- fbinfo->var.nonstd = 0;
- fbinfo->var.activate = FB_ACTIVATE_NOW;
- fbinfo->var.height = info->mach_info->height;
- fbinfo->var.width = info->mach_info->width;
- fbinfo->var.accel_flags = 0;
- fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
-
- fbinfo->fbops = &bfin_bf54x_fb_ops;
- fbinfo->flags = FBINFO_FLAG_DEFAULT;
-
- fbinfo->var.xres = info->mach_info->xres.defval;
- fbinfo->var.xres_virtual = info->mach_info->xres.defval;
- fbinfo->var.yres = info->mach_info->yres.defval;
- fbinfo->var.yres_virtual = info->mach_info->yres.defval;
- fbinfo->var.bits_per_pixel = info->mach_info->bpp.defval;
-
- fbinfo->var.upper_margin = 0;
- fbinfo->var.lower_margin = 0;
- fbinfo->var.vsync_len = 0;
-
- fbinfo->var.left_margin = 0;
- fbinfo->var.right_margin = 0;
- fbinfo->var.hsync_len = 0;
-
- fbinfo->var.red.offset = 16;
- fbinfo->var.green.offset = 8;
- fbinfo->var.blue.offset = 0;
- fbinfo->var.transp.offset = 0;
- fbinfo->var.red.length = 8;
- fbinfo->var.green.length = 8;
- fbinfo->var.blue.length = 8;
- fbinfo->var.transp.length = 0;
- fbinfo->fix.smem_len = info->mach_info->xres.max *
- info->mach_info->yres.max * info->mach_info->bpp.max / 8;
-
- fbinfo->fix.line_length = fbinfo->var.xres_virtual *
- fbinfo->var.bits_per_pixel / 8;
-
- info->fb_buffer =
- dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle,
- GFP_KERNEL);
-
- if (NULL == info->fb_buffer) {
- printk(KERN_ERR DRIVER_NAME
- ": couldn't allocate dma buffer.\n");
- ret = -ENOMEM;
- goto out3;
- }
-
- fbinfo->screen_base = (void *)info->fb_buffer;
- fbinfo->fix.smem_start = (int)info->fb_buffer;
-
- fbinfo->fbops = &bfin_bf54x_fb_ops;
-
- fbinfo->pseudo_palette = devm_kzalloc(&pdev->dev, sizeof(u32) * 16,
- GFP_KERNEL);
- if (!fbinfo->pseudo_palette) {
- printk(KERN_ERR DRIVER_NAME
- "Fail to allocate pseudo_palette\n");
-
- ret = -ENOMEM;
- goto out4;
- }
-
- if (fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0)
- < 0) {
- printk(KERN_ERR DRIVER_NAME
- "Fail to allocate colormap (%d entries)\n",
- BFIN_LCD_NBR_PALETTE_ENTRIES);
- ret = -EFAULT;
- goto out4;
- }
-
- if (request_ports(info)) {
- printk(KERN_ERR DRIVER_NAME ": couldn't request gpio port.\n");
- ret = -EFAULT;
- goto out6;
- }
-
- info->irq = platform_get_irq(pdev, 0);
- if (info->irq < 0) {
- ret = -EINVAL;
- goto out7;
- }
-
- if (request_irq(info->irq, bfin_bf54x_irq_error, 0,
- "PPI ERROR", info) < 0) {
- printk(KERN_ERR DRIVER_NAME
- ": unable to request PPI ERROR IRQ\n");
- ret = -EFAULT;
- goto out7;
- }
-
- if (register_framebuffer(fbinfo) < 0) {
- printk(KERN_ERR DRIVER_NAME
- ": unable to register framebuffer.\n");
- ret = -EINVAL;
- goto out8;
- }
-#ifndef NO_BL_SUPPORT
- memset(&props, 0, sizeof(struct backlight_properties));
- props.type = BACKLIGHT_RAW;
- props.max_brightness = 255;
- bl_dev = backlight_device_register("bf54x-bl", NULL, NULL,
- &bfin_lq043fb_bl_ops, &props);
- if (IS_ERR(bl_dev)) {
- printk(KERN_ERR DRIVER_NAME
- ": unable to register backlight.\n");
- ret = -EINVAL;
- unregister_framebuffer(fbinfo);
- goto out8;
- }
-
- lcd_dev = lcd_device_register(DRIVER_NAME, &pdev->dev, NULL, &bfin_lcd_ops);
- lcd_dev->props.max_contrast = 255, printk(KERN_INFO "Done.\n");
-#endif
-
- return 0;
-
-out8:
- free_irq(info->irq, info);
-out7:
- free_ports(info);
-out6:
- fb_dealloc_cmap(&fbinfo->cmap);
-out4:
- dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
- info->dma_handle);
-out3:
- framebuffer_release(fbinfo);
-out2:
- free_dma(CH_EPPI0);
-out1:
-
- return ret;
-}
-
-static int bfin_bf54x_remove(struct platform_device *pdev)
-{
-
- struct fb_info *fbinfo = platform_get_drvdata(pdev);
- struct bfin_bf54xfb_info *info = fbinfo->par;
-
- free_dma(CH_EPPI0);
- free_irq(info->irq, info);
-
- if (info->fb_buffer != NULL)
- dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
- info->dma_handle);
-
- fb_dealloc_cmap(&fbinfo->cmap);
-
-#ifndef NO_BL_SUPPORT
- lcd_device_unregister(lcd_dev);
- backlight_device_unregister(bl_dev);
-#endif
-
- unregister_framebuffer(fbinfo);
-
- free_ports(info);
-
- printk(KERN_INFO DRIVER_NAME ": Unregister LCD driver.\n");
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int bfin_bf54x_suspend(struct platform_device *pdev, pm_message_t state)
-{
- bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
- disable_dma(CH_EPPI0);
- bfin_write_EPPI0_STATUS(0xFFFF);
-
- return 0;
-}
-
-static int bfin_bf54x_resume(struct platform_device *pdev)
-{
- struct fb_info *fbinfo = platform_get_drvdata(pdev);
- struct bfin_bf54xfb_info *info = fbinfo->par;
-
- if (info->lq043_open_cnt) {
-
- bfin_write_EPPI0_CONTROL(0);
- SSYNC();
-
- config_dma(info);
- config_ppi(info);
-
- /* start dma */
- enable_dma(CH_EPPI0);
- bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
- }
-
- return 0;
-}
-#else
-#define bfin_bf54x_suspend NULL
-#define bfin_bf54x_resume NULL
-#endif
-
-static struct platform_driver bfin_bf54x_driver = {
- .probe = bfin_bf54x_probe,
- .remove = bfin_bf54x_remove,
- .suspend = bfin_bf54x_suspend,
- .resume = bfin_bf54x_resume,
- .driver = {
- .name = DRIVER_NAME,
- },
-};
-module_platform_driver(bfin_bf54x_driver);
-
-MODULE_DESCRIPTION("Blackfin BF54x TFT LCD Driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/bfin-lq035q1-fb.c b/drivers/video/fbdev/bfin-lq035q1-fb.c
deleted file mode 100644
index b459354..0000000
--- a/drivers/video/fbdev/bfin-lq035q1-fb.c
+++ /dev/null
@@ -1,864 +0,0 @@
-/*
- * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
- *
- * Copyright 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#define DRIVER_NAME "bfin-lq035q1"
-#define pr_fmt(fmt) DRIVER_NAME ": " fmt
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/fb.h>
-#include <linux/gpio.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/device.h>
-#include <linux/backlight.h>
-#include <linux/lcd.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-
-#include <asm/blackfin.h>
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-#include <asm/gptimers.h>
-
-#include <asm/bfin-lq035q1.h>
-
-#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
-#define TIMER_HSYNC_id TIMER1_id
-#define TIMER_HSYNCbit TIMER1bit
-#define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN1
-#define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1
-#define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF1
-
-#define TIMER_VSYNC_id TIMER2_id
-#define TIMER_VSYNCbit TIMER2bit
-#define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN2
-#define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL2
-#define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF2
-#else
-#define TIMER_HSYNC_id TIMER0_id
-#define TIMER_HSYNCbit TIMER0bit
-#define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN0
-#define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL0
-#define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF0
-
-#define TIMER_VSYNC_id TIMER1_id
-#define TIMER_VSYNCbit TIMER1bit
-#define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN1
-#define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1
-#define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF1
-#endif
-
-#define LCD_X_RES 320 /* Horizontal Resolution */
-#define LCD_Y_RES 240 /* Vertical Resolution */
-#define DMA_BUS_SIZE 16
-#define U_LINE 4 /* Blanking Lines */
-
-
-/* Interface 16/18-bit TFT over an 8-bit wide PPI using a small Programmable Logic Device (CPLD)
- * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
- */
-
-
-#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
-
-#define PPI_TX_MODE 0x2
-#define PPI_XFER_TYPE_11 0xC
-#define PPI_PORT_CFG_01 0x10
-#define PPI_POLS_1 0x8000
-
-#define LQ035_INDEX 0x74
-#define LQ035_DATA 0x76
-
-#define LQ035_DRIVER_OUTPUT_CTL 0x1
-#define LQ035_SHUT_CTL 0x11
-
-#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
-#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
-
-#define LQ035_SHUT (1 << 0) /* Shutdown */
-#define LQ035_ON (0 << 0) /* Shutdown */
-
-struct bfin_lq035q1fb_info {
- struct fb_info *fb;
- struct device *dev;
- struct spi_driver spidrv;
- struct bfin_lq035q1fb_disp_info *disp_info;
- unsigned char *fb_buffer; /* RGB Buffer */
- dma_addr_t dma_handle;
- int lq035_open_cnt;
- int irq;
- spinlock_t lock; /* lock */
- u32 pseudo_pal[16];
-
- u32 lcd_bpp;
- u32 h_actpix;
- u32 h_period;
- u32 h_pulse;
- u32 h_start;
- u32 v_lines;
- u32 v_pulse;
- u32 v_period;
-};
-
-static int nocursor;
-module_param(nocursor, int, 0644);
-MODULE_PARM_DESC(nocursor, "cursor enable/disable");
-
-struct spi_control {
- unsigned short mode;
-};
-
-static int lq035q1_control(struct spi_device *spi, unsigned char reg, unsigned short value)
-{
- int ret;
- u8 regs[3] = { LQ035_INDEX, 0, 0 };
- u8 dat[3] = { LQ035_DATA, 0, 0 };
-
- if (!spi)
- return -ENODEV;
-
- regs[2] = reg;
- dat[1] = value >> 8;
- dat[2] = value & 0xFF;
-
- ret = spi_write(spi, regs, ARRAY_SIZE(regs));
- ret |= spi_write(spi, dat, ARRAY_SIZE(dat));
- return ret;
-}
-
-static int lq035q1_spidev_probe(struct spi_device *spi)
-{
- int ret;
- struct spi_control *ctl;
- struct bfin_lq035q1fb_info *info = container_of(spi->dev.driver,
- struct bfin_lq035q1fb_info,
- spidrv.driver);
-
- ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
-
- if (!ctl)
- return -ENOMEM;
-
- ctl->mode = (info->disp_info->mode &
- LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT;
-
- ret = lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON);
- ret |= lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode);
- if (ret) {
- kfree(ctl);
- return ret;
- }
-
- spi_set_drvdata(spi, ctl);
-
- return 0;
-}
-
-static int lq035q1_spidev_remove(struct spi_device *spi)
-{
- return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int lq035q1_spidev_suspend(struct device *dev)
-{
- struct spi_device *spi = to_spi_device(dev);
-
- return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
-}
-
-static int lq035q1_spidev_resume(struct device *dev)
-{
- struct spi_device *spi = to_spi_device(dev);
- struct spi_control *ctl = spi_get_drvdata(spi);
- int ret;
-
- ret = lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode);
- if (ret)
- return ret;
-
- return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON);
-}
-
-static SIMPLE_DEV_PM_OPS(lq035q1_spidev_pm_ops, lq035q1_spidev_suspend,
- lq035q1_spidev_resume);
-#define LQ035Q1_SPIDEV_PM_OPS (&lq035q1_spidev_pm_ops)
-
-#else
-#define LQ035Q1_SPIDEV_PM_OPS NULL
-#endif
-
-/* Power down all displays on reboot, poweroff or halt */
-static void lq035q1_spidev_shutdown(struct spi_device *spi)
-{
- lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
-}
-
-static int lq035q1_backlight(struct bfin_lq035q1fb_info *info, unsigned arg)
-{
- if (info->disp_info->use_bl)
- gpio_set_value(info->disp_info->gpio_bl, arg);
-
- return 0;
-}
-
-static int bfin_lq035q1_calc_timing(struct bfin_lq035q1fb_info *fbi)
-{
- unsigned long clocks_per_pix, cpld_pipeline_delay_cor;
-
- /*
- * Interface 16/18-bit TFT over an 8-bit wide PPI using a small
- * Programmable Logic Device (CPLD)
- * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
- */
-
- switch (fbi->disp_info->ppi_mode) {
- case USE_RGB565_16_BIT_PPI:
- fbi->lcd_bpp = 16;
- clocks_per_pix = 1;
- cpld_pipeline_delay_cor = 0;
- break;
- case USE_RGB565_8_BIT_PPI:
- fbi->lcd_bpp = 16;
- clocks_per_pix = 2;
- cpld_pipeline_delay_cor = 3;
- break;
- case USE_RGB888_8_BIT_PPI:
- fbi->lcd_bpp = 24;
- clocks_per_pix = 3;
- cpld_pipeline_delay_cor = 5;
- break;
- default:
- return -EINVAL;
- }
-
- /*
- * HS and VS timing parameters (all in number of PPI clk ticks)
- */
-
- fbi->h_actpix = (LCD_X_RES * clocks_per_pix); /* active horizontal pixel */
- fbi->h_period = (336 * clocks_per_pix); /* HS period */
- fbi->h_pulse = (2 * clocks_per_pix); /* HS pulse width */
- fbi->h_start = (7 * clocks_per_pix + cpld_pipeline_delay_cor); /* first valid pixel */
-
- fbi->v_lines = (LCD_Y_RES + U_LINE); /* total vertical lines */
- fbi->v_pulse = (2 * clocks_per_pix); /* VS pulse width (1-5 H_PERIODs) */
- fbi->v_period = (fbi->h_period * fbi->v_lines); /* VS period */
-
- return 0;
-}
-
-static void bfin_lq035q1_config_ppi(struct bfin_lq035q1fb_info *fbi)
-{
- unsigned ppi_pmode;
-
- if (fbi->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI)
- ppi_pmode = DLEN_16;
- else
- ppi_pmode = (DLEN_8 | PACK_EN);
-
- bfin_write_PPI_DELAY(fbi->h_start);
- bfin_write_PPI_COUNT(fbi->h_actpix - 1);
- bfin_write_PPI_FRAME(fbi->v_lines);
-
- bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */
- PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
- PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
- ppi_pmode | /* 8/16 bit data length / PACK_EN? */
- PPI_POLS_1); /* faling edge syncs POLS */
-}
-
-static inline void bfin_lq035q1_disable_ppi(void)
-{
- bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
-}
-
-static inline void bfin_lq035q1_enable_ppi(void)
-{
- bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
-}
-
-static void bfin_lq035q1_start_timers(void)
-{
- enable_gptimers(TIMER_VSYNCbit | TIMER_HSYNCbit);
-}
-
-static void bfin_lq035q1_stop_timers(void)
-{
- disable_gptimers(TIMER_HSYNCbit | TIMER_VSYNCbit);
-
- set_gptimer_status(0, TIMER_HSYNC_STATUS_TRUN | TIMER_VSYNC_STATUS_TRUN |
- TIMER_HSYNC_STATUS_TIMIL | TIMER_VSYNC_STATUS_TIMIL |
- TIMER_HSYNC_STATUS_TOVF | TIMER_VSYNC_STATUS_TOVF);
-
-}
-
-static void bfin_lq035q1_init_timers(struct bfin_lq035q1fb_info *fbi)
-{
-
- bfin_lq035q1_stop_timers();
-
- set_gptimer_period(TIMER_HSYNC_id, fbi->h_period);
- set_gptimer_pwidth(TIMER_HSYNC_id, fbi->h_pulse);
- set_gptimer_config(TIMER_HSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
- TIMER_TIN_SEL | TIMER_CLK_SEL|
- TIMER_EMU_RUN);
-
- set_gptimer_period(TIMER_VSYNC_id, fbi->v_period);
- set_gptimer_pwidth(TIMER_VSYNC_id, fbi->v_pulse);
- set_gptimer_config(TIMER_VSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
- TIMER_TIN_SEL | TIMER_CLK_SEL |
- TIMER_EMU_RUN);
-
-}
-
-static void bfin_lq035q1_config_dma(struct bfin_lq035q1fb_info *fbi)
-{
-
-
- set_dma_config(CH_PPI,
- set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
- INTR_DISABLE, DIMENSION_2D,
- DATA_SIZE_16,
- DMA_NOSYNC_KEEP_DMA_BUF));
- set_dma_x_count(CH_PPI, (LCD_X_RES * fbi->lcd_bpp) / DMA_BUS_SIZE);
- set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8);
- set_dma_y_count(CH_PPI, fbi->v_lines);
-
- set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8);
- set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer);
-
-}
-
-static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
- P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
- P_PPI0_D6, P_PPI0_D7, P_PPI0_D8,
- P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
- P_PPI0_D15, 0};
-
-static const u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
- P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
- P_PPI0_D6, P_PPI0_D7, 0};
-
-static inline void bfin_lq035q1_free_ports(unsigned ppi16)
-{
- if (ppi16)
- peripheral_free_list(ppi0_req_16);
- else
- peripheral_free_list(ppi0_req_8);
-
- if (ANOMALY_05000400)
- gpio_free(P_IDENT(P_PPI0_FS3));
-}
-
-static int bfin_lq035q1_request_ports(struct platform_device *pdev,
- unsigned ppi16)
-{
- int ret;
- /* ANOMALY_05000400 - PPI Does Not Start Properly In Specific Mode:
- * Drive PPI_FS3 Low
- */
- if (ANOMALY_05000400) {
- int ret = gpio_request_one(P_IDENT(P_PPI0_FS3),
- GPIOF_OUT_INIT_LOW, "PPI_FS3");
- if (ret)
- return ret;
- }
-
- if (ppi16)
- ret = peripheral_request_list(ppi0_req_16, DRIVER_NAME);
- else
- ret = peripheral_request_list(ppi0_req_8, DRIVER_NAME);
-
- if (ret) {
- dev_err(&pdev->dev, "requesting peripherals failed\n");
- return -EFAULT;
- }
-
- return 0;
-}
-
-static int bfin_lq035q1_fb_open(struct fb_info *info, int user)
-{
- struct bfin_lq035q1fb_info *fbi = info->par;
-
- spin_lock(&fbi->lock);
- fbi->lq035_open_cnt++;
-
- if (fbi->lq035_open_cnt <= 1) {
-
- bfin_lq035q1_disable_ppi();
- SSYNC();
-
- bfin_lq035q1_config_dma(fbi);
- bfin_lq035q1_config_ppi(fbi);
- bfin_lq035q1_init_timers(fbi);
-
- /* start dma */
- enable_dma(CH_PPI);
- bfin_lq035q1_enable_ppi();
- bfin_lq035q1_start_timers();
- lq035q1_backlight(fbi, 1);
- }
-
- spin_unlock(&fbi->lock);
-
- return 0;
-}
-
-static int bfin_lq035q1_fb_release(struct fb_info *info, int user)
-{
- struct bfin_lq035q1fb_info *fbi = info->par;
-
- spin_lock(&fbi->lock);
-
- fbi->lq035_open_cnt--;
-
- if (fbi->lq035_open_cnt <= 0) {
- lq035q1_backlight(fbi, 0);
- bfin_lq035q1_disable_ppi();
- SSYNC();
- disable_dma(CH_PPI);
- bfin_lq035q1_stop_timers();
- }
-
- spin_unlock(&fbi->lock);
-
- return 0;
-}
-
-static int bfin_lq035q1_fb_check_var(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
- struct bfin_lq035q1fb_info *fbi = info->par;
-
- if (var->bits_per_pixel == fbi->lcd_bpp) {
- var->red.offset = info->var.red.offset;
- var->green.offset = info->var.green.offset;
- var->blue.offset = info->var.blue.offset;
- var->red.length = info->var.red.length;
- var->green.length = info->var.green.length;
- var->blue.length = info->var.blue.length;
- var->transp.offset = 0;
- var->transp.length = 0;
- var->transp.msb_right = 0;
- var->red.msb_right = 0;
- var->green.msb_right = 0;
- var->blue.msb_right = 0;
- } else {
- pr_debug("%s: depth not supported: %u BPP\n", __func__,
- var->bits_per_pixel);
- return -EINVAL;
- }
-
- if (info->var.xres != var->xres || info->var.yres != var->yres ||
- info->var.xres_virtual != var->xres_virtual ||
- info->var.yres_virtual != var->yres_virtual) {
- pr_debug("%s: Resolution not supported: X%u x Y%u \n",
- __func__, var->xres, var->yres);
- return -EINVAL;
- }
-
- /*
- * Memory limit
- */
-
- if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
- pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
- __func__, var->yres_virtual);
- return -ENOMEM;
- }
-
-
- return 0;
-}
-
-int bfin_lq035q1_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
-{
- if (nocursor)
- return 0;
- else
- return -EINVAL; /* just to force soft_cursor() call */
-}
-
-static int bfin_lq035q1_fb_setcolreg(u_int regno, u_int red, u_int green,
- u_int blue, u_int transp,
- struct fb_info *info)
-{
- if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
- return -EINVAL;
-
- if (info->var.grayscale) {
- /* grayscale = 0.30*R + 0.59*G + 0.11*B */
- red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
- }
-
- if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
-
- u32 value;
- /* Place color in the pseudopalette */
- if (regno > 16)
- return -EINVAL;
-
- red >>= (16 - info->var.red.length);
- green >>= (16 - info->var.green.length);
- blue >>= (16 - info->var.blue.length);
-
- value = (red << info->var.red.offset) |
- (green << info->var.green.offset) |
- (blue << info->var.blue.offset);
- value &= 0xFFFFFF;
-
- ((u32 *) (info->pseudo_palette))[regno] = value;
-
- }
-
- return 0;
-}
-
-static struct fb_ops bfin_lq035q1_fb_ops = {
- .owner = THIS_MODULE,
- .fb_open = bfin_lq035q1_fb_open,
- .fb_release = bfin_lq035q1_fb_release,
- .fb_check_var = bfin_lq035q1_fb_check_var,
- .fb_fillrect = cfb_fillrect,
- .fb_copyarea = cfb_copyarea,
- .fb_imageblit = cfb_imageblit,
- .fb_cursor = bfin_lq035q1_fb_cursor,
- .fb_setcolreg = bfin_lq035q1_fb_setcolreg,
-};
-
-static irqreturn_t bfin_lq035q1_irq_error(int irq, void *dev_id)
-{
- /*struct bfin_lq035q1fb_info *info = (struct bfin_lq035q1fb_info *)dev_id;*/
-
- u16 status = bfin_read_PPI_STATUS();
- bfin_write_PPI_STATUS(-1);
-
- if (status) {
- bfin_lq035q1_disable_ppi();
- disable_dma(CH_PPI);
-
- /* start dma */
- enable_dma(CH_PPI);
- bfin_lq035q1_enable_ppi();
- bfin_write_PPI_STATUS(-1);
- }
-
- return IRQ_HANDLED;
-}
-
-static int bfin_lq035q1_probe(struct platform_device *pdev)
-{
- struct bfin_lq035q1fb_info *info;
- struct fb_info *fbinfo;
- u32 active_video_mem_offset;
- int ret;
-
- ret = request_dma(CH_PPI, DRIVER_NAME"_CH_PPI");
- if (ret < 0) {
- dev_err(&pdev->dev, "PPI DMA unavailable\n");
- goto out1;
- }
-
- fbinfo = framebuffer_alloc(sizeof(*info), &pdev->dev);
- if (!fbinfo) {
- ret = -ENOMEM;
- goto out2;
- }
-
- info = fbinfo->par;
- info->fb = fbinfo;
- info->dev = &pdev->dev;
- spin_lock_init(&info->lock);
-
- info->disp_info = pdev->dev.platform_data;
-
- platform_set_drvdata(pdev, fbinfo);
-
- ret = bfin_lq035q1_calc_timing(info);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed PPI Mode\n");
- goto out3;
- }
-
- strcpy(fbinfo->fix.id, DRIVER_NAME);
-
- fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
- fbinfo->fix.type_aux = 0;
- fbinfo->fix.xpanstep = 0;
- fbinfo->fix.ypanstep = 0;
- fbinfo->fix.ywrapstep = 0;
- fbinfo->fix.accel = FB_ACCEL_NONE;
- fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
-
- fbinfo->var.nonstd = 0;
- fbinfo->var.activate = FB_ACTIVATE_NOW;
- fbinfo->var.height = -1;
- fbinfo->var.width = -1;
- fbinfo->var.accel_flags = 0;
- fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
-
- fbinfo->var.xres = LCD_X_RES;
- fbinfo->var.xres_virtual = LCD_X_RES;
- fbinfo->var.yres = LCD_Y_RES;
- fbinfo->var.yres_virtual = LCD_Y_RES;
- fbinfo->var.bits_per_pixel = info->lcd_bpp;
-
- if (info->disp_info->mode & LQ035_BGR) {
- if (info->lcd_bpp == 24) {
- fbinfo->var.red.offset = 0;
- fbinfo->var.green.offset = 8;
- fbinfo->var.blue.offset = 16;
- } else {
- fbinfo->var.red.offset = 0;
- fbinfo->var.green.offset = 5;
- fbinfo->var.blue.offset = 11;
- }
- } else {
- if (info->lcd_bpp == 24) {
- fbinfo->var.red.offset = 16;
- fbinfo->var.green.offset = 8;
- fbinfo->var.blue.offset = 0;
- } else {
- fbinfo->var.red.offset = 11;
- fbinfo->var.green.offset = 5;
- fbinfo->var.blue.offset = 0;
- }
- }
-
- fbinfo->var.transp.offset = 0;
-
- if (info->lcd_bpp == 24) {
- fbinfo->var.red.length = 8;
- fbinfo->var.green.length = 8;
- fbinfo->var.blue.length = 8;
- } else {
- fbinfo->var.red.length = 5;
- fbinfo->var.green.length = 6;
- fbinfo->var.blue.length = 5;
- }
-
- fbinfo->var.transp.length = 0;
-
- active_video_mem_offset = ((U_LINE / 2) * LCD_X_RES * (info->lcd_bpp / 8));
-
- fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * info->lcd_bpp / 8
- + active_video_mem_offset;
-
- fbinfo->fix.line_length = fbinfo->var.xres_virtual *
- fbinfo->var.bits_per_pixel / 8;
-
-
- fbinfo->fbops = &bfin_lq035q1_fb_ops;
- fbinfo->flags = FBINFO_FLAG_DEFAULT;
-
- info->fb_buffer =
- dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle,
- GFP_KERNEL);
-
- if (NULL == info->fb_buffer) {
- dev_err(&pdev->dev, "couldn't allocate dma buffer\n");
- ret = -ENOMEM;
- goto out3;
- }
-
- fbinfo->screen_base = (void *)info->fb_buffer + active_video_mem_offset;
- fbinfo->fix.smem_start = (int)info->fb_buffer + active_video_mem_offset;
-
- fbinfo->fbops = &bfin_lq035q1_fb_ops;
-
- fbinfo->pseudo_palette = &info->pseudo_pal;
-
- ret = fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to allocate colormap (%d entries)\n",
- BFIN_LCD_NBR_PALETTE_ENTRIES);
- goto out4;
- }
-
- ret = bfin_lq035q1_request_ports(pdev,
- info->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI);
- if (ret) {
- dev_err(&pdev->dev, "couldn't request gpio port\n");
- goto out6;
- }
-
- info->irq = platform_get_irq(pdev, 0);
- if (info->irq < 0) {
- ret = -EINVAL;
- goto out7;
- }
-
- ret = request_irq(info->irq, bfin_lq035q1_irq_error, 0,
- DRIVER_NAME" PPI ERROR", info);
- if (ret < 0) {
- dev_err(&pdev->dev, "unable to request PPI ERROR IRQ\n");
- goto out7;
- }
-
- info->spidrv.driver.name = DRIVER_NAME"-spi";
- info->spidrv.probe = lq035q1_spidev_probe;
- info->spidrv.remove = lq035q1_spidev_remove;
- info->spidrv.shutdown = lq035q1_spidev_shutdown;
- info->spidrv.driver.pm = LQ035Q1_SPIDEV_PM_OPS;
-
- ret = spi_register_driver(&info->spidrv);
- if (ret < 0) {
- dev_err(&pdev->dev, "couldn't register SPI Interface\n");
- goto out8;
- }
-
- if (info->disp_info->use_bl) {
- ret = gpio_request_one(info->disp_info->gpio_bl,
- GPIOF_OUT_INIT_LOW, "LQ035 Backlight");
-
- if (ret) {
- dev_err(&pdev->dev, "failed to request GPIO %d\n",
- info->disp_info->gpio_bl);
- goto out9;
- }
- }
-
- ret = register_framebuffer(fbinfo);
- if (ret < 0) {
- dev_err(&pdev->dev, "unable to register framebuffer\n");
- goto out10;
- }
-
- dev_info(&pdev->dev, "%dx%d %d-bit RGB FrameBuffer initialized\n",
- LCD_X_RES, LCD_Y_RES, info->lcd_bpp);
-
- return 0;
-
- out10:
- if (info->disp_info->use_bl)
- gpio_free(info->disp_info->gpio_bl);
- out9:
- spi_unregister_driver(&info->spidrv);
- out8:
- free_irq(info->irq, info);
- out7:
- bfin_lq035q1_free_ports(info->disp_info->ppi_mode ==
- USE_RGB565_16_BIT_PPI);
- out6:
- fb_dealloc_cmap(&fbinfo->cmap);
- out4:
- dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
- info->dma_handle);
- out3:
- framebuffer_release(fbinfo);
- out2:
- free_dma(CH_PPI);
- out1:
-
- return ret;
-}
-
-static int bfin_lq035q1_remove(struct platform_device *pdev)
-{
- struct fb_info *fbinfo = platform_get_drvdata(pdev);
- struct bfin_lq035q1fb_info *info = fbinfo->par;
-
- if (info->disp_info->use_bl)
- gpio_free(info->disp_info->gpio_bl);
-
- spi_unregister_driver(&info->spidrv);
-
- unregister_framebuffer(fbinfo);
-
- free_dma(CH_PPI);
- free_irq(info->irq, info);
-
- if (info->fb_buffer != NULL)
- dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
- info->dma_handle);
-
- fb_dealloc_cmap(&fbinfo->cmap);
-
- bfin_lq035q1_free_ports(info->disp_info->ppi_mode ==
- USE_RGB565_16_BIT_PPI);
-
- framebuffer_release(fbinfo);
-
- dev_info(&pdev->dev, "unregistered LCD driver\n");
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int bfin_lq035q1_suspend(struct device *dev)
-{
- struct fb_info *fbinfo = dev_get_drvdata(dev);
- struct bfin_lq035q1fb_info *info = fbinfo->par;
-
- if (info->lq035_open_cnt) {
- lq035q1_backlight(info, 0);
- bfin_lq035q1_disable_ppi();
- SSYNC();
- disable_dma(CH_PPI);
- bfin_lq035q1_stop_timers();
- bfin_write_PPI_STATUS(-1);
- }
-
- return 0;
-}
-
-static int bfin_lq035q1_resume(struct device *dev)
-{
- struct fb_info *fbinfo = dev_get_drvdata(dev);
- struct bfin_lq035q1fb_info *info = fbinfo->par;
-
- if (info->lq035_open_cnt) {
- bfin_lq035q1_disable_ppi();
- SSYNC();
-
- bfin_lq035q1_config_dma(info);
- bfin_lq035q1_config_ppi(info);
- bfin_lq035q1_init_timers(info);
-
- /* start dma */
- enable_dma(CH_PPI);
- bfin_lq035q1_enable_ppi();
- bfin_lq035q1_start_timers();
- lq035q1_backlight(info, 1);
- }
-
- return 0;
-}
-
-static const struct dev_pm_ops bfin_lq035q1_dev_pm_ops = {
- .suspend = bfin_lq035q1_suspend,
- .resume = bfin_lq035q1_resume,
-};
-#endif
-
-static struct platform_driver bfin_lq035q1_driver = {
- .probe = bfin_lq035q1_probe,
- .remove = bfin_lq035q1_remove,
- .driver = {
- .name = DRIVER_NAME,
-#ifdef CONFIG_PM
- .pm = &bfin_lq035q1_dev_pm_ops,
-#endif
- },
-};
-
-module_platform_driver(bfin_lq035q1_driver);
-
-MODULE_DESCRIPTION("Blackfin TFT LCD Driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/bfin-t350mcqb-fb.c b/drivers/video/fbdev/bfin-t350mcqb-fb.c
deleted file mode 100644
index e5ee4d9..0000000
--- a/drivers/video/fbdev/bfin-t350mcqb-fb.c
+++ /dev/null
@@ -1,669 +0,0 @@
-/*
- * File: drivers/video/bfin-t350mcqb-fb.c
- * Based on:
- * Author: Michael Hennerich <hennerich@blackfin.uclinux.org>
- *
- * Created:
- * Description: Blackfin LCD Framebuffer driver
- *
- *
- * Modified:
- * Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/gfp.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/device.h>
-#include <linux/backlight.h>
-#include <linux/lcd.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-
-#include <asm/blackfin.h>
-#include <asm/irq.h>
-#include <asm/dma-mapping.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-#include <asm/gptimers.h>
-
-#define NO_BL_SUPPORT
-
-#define LCD_X_RES 320 /* Horizontal Resolution */
-#define LCD_Y_RES 240 /* Vertical Resolution */
-#define LCD_BPP 24 /* Bit Per Pixel */
-
-#define DMA_BUS_SIZE 16
-#define LCD_CLK (12*1000*1000) /* 12MHz */
-
-#define CLOCKS_PER_PIX 3
-
- /*
- * HS and VS timing parameters (all in number of PPI clk ticks)
- */
-
-#define U_LINE 1 /* Blanking Lines */
-
-#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */
-#define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */
-#define H_PULSE 90 /* HS pulse width */
-#define H_START 204 /* first valid pixel */
-
-#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
-#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
-#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
-
-#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
-
-#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
-
-#define DRIVER_NAME "bfin-t350mcqb"
-static char driver_name[] = DRIVER_NAME;
-
-struct bfin_t350mcqbfb_info {
- struct fb_info *fb;
- struct device *dev;
- unsigned char *fb_buffer; /* RGB Buffer */
- dma_addr_t dma_handle;
- int lq043_open_cnt;
- int irq;
- spinlock_t lock; /* lock */
- u32 pseudo_pal[16];
-};
-
-static int nocursor;
-module_param(nocursor, int, 0644);
-MODULE_PARM_DESC(nocursor, "cursor enable/disable");
-
-#define PPI_TX_MODE 0x2
-#define PPI_XFER_TYPE_11 0xC
-#define PPI_PORT_CFG_01 0x10
-#define PPI_PACK_EN 0x80
-#define PPI_POLS_1 0x8000
-
-static void bfin_t350mcqb_config_ppi(struct bfin_t350mcqbfb_info *fbi)
-{
- bfin_write_PPI_DELAY(H_START);
- bfin_write_PPI_COUNT(H_ACTPIX-1);
- bfin_write_PPI_FRAME(V_LINES);
-
- bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */
- PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
- PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
- PPI_PACK_EN | /* packing enabled PACK_EN */
- PPI_POLS_1); /* faling edge syncs POLS */
-}
-
-static inline void bfin_t350mcqb_disable_ppi(void)
-{
- bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
-}
-
-static inline void bfin_t350mcqb_enable_ppi(void)
-{
- bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
-}
-
-static void bfin_t350mcqb_start_timers(void)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- enable_gptimers(TIMER1bit);
- enable_gptimers(TIMER0bit);
- local_irq_restore(flags);
-}
-
-static void bfin_t350mcqb_stop_timers(void)
-{
- disable_gptimers(TIMER0bit | TIMER1bit);
-
- set_gptimer_status(0, TIMER_STATUS_TRUN0 | TIMER_STATUS_TRUN1 |
- TIMER_STATUS_TIMIL0 | TIMER_STATUS_TIMIL1 |
- TIMER_STATUS_TOVF0 | TIMER_STATUS_TOVF1);
-
-}
-
-static void bfin_t350mcqb_init_timers(void)
-{
-
- bfin_t350mcqb_stop_timers();
-
- set_gptimer_period(TIMER0_id, H_PERIOD);
- set_gptimer_pwidth(TIMER0_id, H_PULSE);
- set_gptimer_config(TIMER0_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
- TIMER_TIN_SEL | TIMER_CLK_SEL|
- TIMER_EMU_RUN);
-
- set_gptimer_period(TIMER1_id, V_PERIOD);
- set_gptimer_pwidth(TIMER1_id, V_PULSE);
- set_gptimer_config(TIMER1_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
- TIMER_TIN_SEL | TIMER_CLK_SEL |
- TIMER_EMU_RUN);
-
-}
-
-static void bfin_t350mcqb_config_dma(struct bfin_t350mcqbfb_info *fbi)
-{
-
- set_dma_config(CH_PPI,
- set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
- INTR_DISABLE, DIMENSION_2D,
- DATA_SIZE_16,
- DMA_NOSYNC_KEEP_DMA_BUF));
- set_dma_x_count(CH_PPI, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
- set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8);
- set_dma_y_count(CH_PPI, V_LINES);
-
- set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8);
- set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer);
-
-}
-
-static u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
- P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
- P_PPI0_D6, P_PPI0_D7, 0};
-
-static int bfin_t350mcqb_request_ports(int action)
-{
- if (action) {
- if (peripheral_request_list(ppi0_req_8, DRIVER_NAME)) {
- printk(KERN_ERR "Requesting Peripherals failed\n");
- return -EFAULT;
- }
- } else
- peripheral_free_list(ppi0_req_8);
-
- return 0;
-}
-
-static int bfin_t350mcqb_fb_open(struct fb_info *info, int user)
-{
- struct bfin_t350mcqbfb_info *fbi = info->par;
-
- spin_lock(&fbi->lock);
- fbi->lq043_open_cnt++;
-
- if (fbi->lq043_open_cnt <= 1) {
-
- bfin_t350mcqb_disable_ppi();
- SSYNC();
-
- bfin_t350mcqb_config_dma(fbi);
- bfin_t350mcqb_config_ppi(fbi);
- bfin_t350mcqb_init_timers();
-
- /* start dma */
- enable_dma(CH_PPI);
- bfin_t350mcqb_enable_ppi();
- bfin_t350mcqb_start_timers();
- }
-
- spin_unlock(&fbi->lock);
-
- return 0;
-}
-
-static int bfin_t350mcqb_fb_release(struct fb_info *info, int user)
-{
- struct bfin_t350mcqbfb_info *fbi = info->par;
-
- spin_lock(&fbi->lock);
-
- fbi->lq043_open_cnt--;
-
- if (fbi->lq043_open_cnt <= 0) {
- bfin_t350mcqb_disable_ppi();
- SSYNC();
- disable_dma(CH_PPI);
- bfin_t350mcqb_stop_timers();
- }
-
- spin_unlock(&fbi->lock);
-
- return 0;
-}
-
-static int bfin_t350mcqb_fb_check_var(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
-
- switch (var->bits_per_pixel) {
- case 24:/* TRUECOLOUR, 16m */
- var->red.offset = 0;
- var->green.offset = 8;
- var->blue.offset = 16;
- var->red.length = var->green.length = var->blue.length = 8;
- var->transp.offset = 0;
- var->transp.length = 0;
- var->transp.msb_right = 0;
- var->red.msb_right = 0;
- var->green.msb_right = 0;
- var->blue.msb_right = 0;
- break;
- default:
- pr_debug("%s: depth not supported: %u BPP\n", __func__,
- var->bits_per_pixel);
- return -EINVAL;
- }
-
- if (info->var.xres != var->xres || info->var.yres != var->yres ||
- info->var.xres_virtual != var->xres_virtual ||
- info->var.yres_virtual != var->yres_virtual) {
- pr_debug("%s: Resolution not supported: X%u x Y%u \n",
- __func__, var->xres, var->yres);
- return -EINVAL;
- }
-
- /*
- * Memory limit
- */
-
- if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
- pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
- __func__, var->yres_virtual);
- return -ENOMEM;
- }
-
- return 0;
-}
-
-int bfin_t350mcqb_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
-{
- if (nocursor)
- return 0;
- else
- return -EINVAL; /* just to force soft_cursor() call */
-}
-
-static int bfin_t350mcqb_fb_setcolreg(u_int regno, u_int red, u_int green,
- u_int blue, u_int transp,
- struct fb_info *info)
-{
- if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
- return -EINVAL;
-
- if (info->var.grayscale) {
- /* grayscale = 0.30*R + 0.59*G + 0.11*B */
- red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
- }
-
- if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
-
- u32 value;
- /* Place color in the pseudopalette */
- if (regno > 16)
- return -EINVAL;
-
- red >>= (16 - info->var.red.length);
- green >>= (16 - info->var.green.length);
- blue >>= (16 - info->var.blue.length);
-
- value = (red << info->var.red.offset) |
- (green << info->var.green.offset) |
- (blue << info->var.blue.offset);
- value &= 0xFFFFFF;
-
- ((u32 *) (info->pseudo_palette))[regno] = value;
-
- }
-
- return 0;
-}
-
-static struct fb_ops bfin_t350mcqb_fb_ops = {
- .owner = THIS_MODULE,
- .fb_open = bfin_t350mcqb_fb_open,
- .fb_release = bfin_t350mcqb_fb_release,
- .fb_check_var = bfin_t350mcqb_fb_check_var,
- .fb_fillrect = cfb_fillrect,
- .fb_copyarea = cfb_copyarea,
- .fb_imageblit = cfb_imageblit,
- .fb_cursor = bfin_t350mcqb_fb_cursor,
- .fb_setcolreg = bfin_t350mcqb_fb_setcolreg,
-};
-
-#ifndef NO_BL_SUPPORT
-static int bl_get_brightness(struct backlight_device *bd)
-{
- return 0;
-}
-
-static const struct backlight_ops bfin_lq043fb_bl_ops = {
- .get_brightness = bl_get_brightness,
-};
-
-static struct backlight_device *bl_dev;
-
-static int bfin_lcd_get_power(struct lcd_device *dev)
-{
- return 0;
-}
-
-static int bfin_lcd_set_power(struct lcd_device *dev, int power)
-{
- return 0;
-}
-
-static int bfin_lcd_get_contrast(struct lcd_device *dev)
-{
- return 0;
-}
-
-static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast)
-{
-
- return 0;
-}
-
-static int bfin_lcd_check_fb(struct lcd_device *dev, struct fb_info *fi)
-{
- if (!fi || (fi == &bfin_t350mcqb_fb))
- return 1;
- return 0;
-}
-
-static struct lcd_ops bfin_lcd_ops = {
- .get_power = bfin_lcd_get_power,
- .set_power = bfin_lcd_set_power,
- .get_contrast = bfin_lcd_get_contrast,
- .set_contrast = bfin_lcd_set_contrast,
- .check_fb = bfin_lcd_check_fb,
-};
-
-static struct lcd_device *lcd_dev;
-#endif
-
-static irqreturn_t bfin_t350mcqb_irq_error(int irq, void *dev_id)
-{
- /*struct bfin_t350mcqbfb_info *info = (struct bfin_t350mcqbfb_info *)dev_id;*/
-
- u16 status = bfin_read_PPI_STATUS();
- bfin_write_PPI_STATUS(0xFFFF);
-
- if (status) {
- bfin_t350mcqb_disable_ppi();
- disable_dma(CH_PPI);
-
- /* start dma */
- enable_dma(CH_PPI);
- bfin_t350mcqb_enable_ppi();
- bfin_write_PPI_STATUS(0xFFFF);
- }
-
- return IRQ_HANDLED;
-}
-
-static int bfin_t350mcqb_probe(struct platform_device *pdev)
-{
-#ifndef NO_BL_SUPPORT
- struct backlight_properties props;
-#endif
- struct bfin_t350mcqbfb_info *info;
- struct fb_info *fbinfo;
- int ret;
-
- printk(KERN_INFO DRIVER_NAME ": %dx%d %d-bit RGB FrameBuffer initializing...\n",
- LCD_X_RES, LCD_Y_RES, LCD_BPP);
-
- if (request_dma(CH_PPI, "CH_PPI") < 0) {
- printk(KERN_ERR DRIVER_NAME
- ": couldn't request CH_PPI DMA\n");
- ret = -EFAULT;
- goto out1;
- }
-
- fbinfo =
- framebuffer_alloc(sizeof(struct bfin_t350mcqbfb_info), &pdev->dev);
- if (!fbinfo) {
- ret = -ENOMEM;
- goto out2;
- }
-
- info = fbinfo->par;
- info->fb = fbinfo;
- info->dev = &pdev->dev;
- spin_lock_init(&info->lock);
-
- platform_set_drvdata(pdev, fbinfo);
-
- strcpy(fbinfo->fix.id, driver_name);
-
- fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
- fbinfo->fix.type_aux = 0;
- fbinfo->fix.xpanstep = 0;
- fbinfo->fix.ypanstep = 0;
- fbinfo->fix.ywrapstep = 0;
- fbinfo->fix.accel = FB_ACCEL_NONE;
- fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
-
- fbinfo->var.nonstd = 0;
- fbinfo->var.activate = FB_ACTIVATE_NOW;
- fbinfo->var.height = 53;
- fbinfo->var.width = 70;
- fbinfo->var.accel_flags = 0;
- fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
-
- fbinfo->var.xres = LCD_X_RES;
- fbinfo->var.xres_virtual = LCD_X_RES;
- fbinfo->var.yres = LCD_Y_RES;
- fbinfo->var.yres_virtual = LCD_Y_RES;
- fbinfo->var.bits_per_pixel = LCD_BPP;
-
- fbinfo->var.red.offset = 0;
- fbinfo->var.green.offset = 8;
- fbinfo->var.blue.offset = 16;
- fbinfo->var.transp.offset = 0;
- fbinfo->var.red.length = 8;
- fbinfo->var.green.length = 8;
- fbinfo->var.blue.length = 8;
- fbinfo->var.transp.length = 0;
- fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * LCD_BPP / 8;
-
- fbinfo->fix.line_length = fbinfo->var.xres_virtual *
- fbinfo->var.bits_per_pixel / 8;
-
-
- fbinfo->fbops = &bfin_t350mcqb_fb_ops;
- fbinfo->flags = FBINFO_FLAG_DEFAULT;
-
- info->fb_buffer = dma_alloc_coherent(NULL, fbinfo->fix.smem_len +
- ACTIVE_VIDEO_MEM_OFFSET,
- &info->dma_handle, GFP_KERNEL);
-
- if (NULL == info->fb_buffer) {
- printk(KERN_ERR DRIVER_NAME
- ": couldn't allocate dma buffer.\n");
- ret = -ENOMEM;
- goto out3;
- }
-
- fbinfo->screen_base = (void *)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET;
- fbinfo->fix.smem_start = (int)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET;
-
- fbinfo->fbops = &bfin_t350mcqb_fb_ops;
-
- fbinfo->pseudo_palette = &info->pseudo_pal;
-
- if (fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0)
- < 0) {
- printk(KERN_ERR DRIVER_NAME
- "Fail to allocate colormap (%d entries)\n",
- BFIN_LCD_NBR_PALETTE_ENTRIES);
- ret = -EFAULT;
- goto out4;
- }
-
- if (bfin_t350mcqb_request_ports(1)) {
- printk(KERN_ERR DRIVER_NAME ": couldn't request gpio port.\n");
- ret = -EFAULT;
- goto out6;
- }
-
- info->irq = platform_get_irq(pdev, 0);
- if (info->irq < 0) {
- ret = -EINVAL;
- goto out7;
- }
-
- ret = request_irq(info->irq, bfin_t350mcqb_irq_error, 0,
- "PPI ERROR", info);
- if (ret < 0) {
- printk(KERN_ERR DRIVER_NAME
- ": unable to request PPI ERROR IRQ\n");
- goto out7;
- }
-
- if (register_framebuffer(fbinfo) < 0) {
- printk(KERN_ERR DRIVER_NAME
- ": unable to register framebuffer.\n");
- ret = -EINVAL;
- goto out8;
- }
-#ifndef NO_BL_SUPPORT
- memset(&props, 0, sizeof(struct backlight_properties));
- props.type = BACKLIGHT_RAW;
- props.max_brightness = 255;
- bl_dev = backlight_device_register("bf52x-bl", NULL, NULL,
- &bfin_lq043fb_bl_ops, &props);
- if (IS_ERR(bl_dev)) {
- printk(KERN_ERR DRIVER_NAME
- ": unable to register backlight.\n");
- ret = -EINVAL;
- unregister_framebuffer(fbinfo);
- goto out8;
- }
-
- lcd_dev = lcd_device_register(DRIVER_NAME, NULL, &bfin_lcd_ops);
- lcd_dev->props.max_contrast = 255, printk(KERN_INFO "Done.\n");
-#endif
-
- return 0;
-
-out8:
- free_irq(info->irq, info);
-out7:
- bfin_t350mcqb_request_ports(0);
-out6:
- fb_dealloc_cmap(&fbinfo->cmap);
-out4:
- dma_free_coherent(NULL, fbinfo->fix.smem_len + ACTIVE_VIDEO_MEM_OFFSET,
- info->fb_buffer, info->dma_handle);
-out3:
- framebuffer_release(fbinfo);
-out2:
- free_dma(CH_PPI);
-out1:
-
- return ret;
-}
-
-static int bfin_t350mcqb_remove(struct platform_device *pdev)
-{
-
- struct fb_info *fbinfo = platform_get_drvdata(pdev);
- struct bfin_t350mcqbfb_info *info = fbinfo->par;
-
- unregister_framebuffer(fbinfo);
-
- free_dma(CH_PPI);
- free_irq(info->irq, info);
-
- if (info->fb_buffer != NULL)
- dma_free_coherent(NULL, fbinfo->fix.smem_len +
- ACTIVE_VIDEO_MEM_OFFSET, info->fb_buffer,
- info->dma_handle);
-
- fb_dealloc_cmap(&fbinfo->cmap);
-
-#ifndef NO_BL_SUPPORT
- lcd_device_unregister(lcd_dev);
- backlight_device_unregister(bl_dev);
-#endif
-
- bfin_t350mcqb_request_ports(0);
-
- framebuffer_release(fbinfo);
-
- printk(KERN_INFO DRIVER_NAME ": Unregister LCD driver.\n");
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int bfin_t350mcqb_suspend(struct platform_device *pdev, pm_message_t state)
-{
- struct fb_info *fbinfo = platform_get_drvdata(pdev);
- struct bfin_t350mcqbfb_info *fbi = fbinfo->par;
-
- if (fbi->lq043_open_cnt) {
- bfin_t350mcqb_disable_ppi();
- disable_dma(CH_PPI);
- bfin_t350mcqb_stop_timers();
- bfin_write_PPI_STATUS(-1);
- }
-
-
- return 0;
-}
-
-static int bfin_t350mcqb_resume(struct platform_device *pdev)
-{
- struct fb_info *fbinfo = platform_get_drvdata(pdev);
- struct bfin_t350mcqbfb_info *fbi = fbinfo->par;
-
- if (fbi->lq043_open_cnt) {
- bfin_t350mcqb_config_dma(fbi);
- bfin_t350mcqb_config_ppi(fbi);
- bfin_t350mcqb_init_timers();
-
- /* start dma */
- enable_dma(CH_PPI);
- bfin_t350mcqb_enable_ppi();
- bfin_t350mcqb_start_timers();
- }
-
- return 0;
-}
-#else
-#define bfin_t350mcqb_suspend NULL
-#define bfin_t350mcqb_resume NULL
-#endif
-
-static struct platform_driver bfin_t350mcqb_driver = {
- .probe = bfin_t350mcqb_probe,
- .remove = bfin_t350mcqb_remove,
- .suspend = bfin_t350mcqb_suspend,
- .resume = bfin_t350mcqb_resume,
- .driver = {
- .name = DRIVER_NAME,
- },
-};
-module_platform_driver(bfin_t350mcqb_driver);
-
-MODULE_DESCRIPTION("Blackfin TFT LCD Driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/bfin_adv7393fb.c b/drivers/video/fbdev/bfin_adv7393fb.c
deleted file mode 100644
index 542ffad..0000000
--- a/drivers/video/fbdev/bfin_adv7393fb.c
+++ /dev/null
@@ -1,828 +0,0 @@
-/*
- * Frame buffer driver for ADV7393/2 video encoder
- *
- * Copyright 2006-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or late.
- */
-
-/*
- * TODO: Remove Globals
- * TODO: Code Cleanup
- */
-
-#define DRIVER_NAME "bfin-adv7393"
-
-#define pr_fmt(fmt) DRIVER_NAME ": " fmt
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/fb.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <asm/blackfin.h>
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <linux/uaccess.h>
-#include <linux/gpio.h>
-#include <asm/portmux.h>
-
-#include <linux/dma-mapping.h>
-#include <linux/proc_fs.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-
-#include "bfin_adv7393fb.h"
-
-static int mode = VMODE;
-static int mem = VMEM;
-static int nocursor = 1;
-
-static const unsigned short ppi_pins[] = {
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
- 0
-};
-
-/*
- * card parameters
- */
-
-static struct bfin_adv7393_fb_par {
- /* structure holding blackfin / adv7393 parameters when
- screen is blanked */
- struct {
- u8 Mode; /* ntsc/pal/? */
- } vga_state;
- atomic_t ref_count;
-} bfin_par;
-
-/* --------------------------------------------------------------------- */
-
-static struct fb_var_screeninfo bfin_adv7393_fb_defined = {
- .xres = 720,
- .yres = 480,
- .xres_virtual = 720,
- .yres_virtual = 480,
- .bits_per_pixel = 16,
- .activate = FB_ACTIVATE_TEST,
- .height = -1,
- .width = -1,
- .left_margin = 0,
- .right_margin = 0,
- .upper_margin = 0,
- .lower_margin = 0,
- .vmode = FB_VMODE_INTERLACED,
- .red = {11, 5, 0},
- .green = {5, 6, 0},
- .blue = {0, 5, 0},
- .transp = {0, 0, 0},
-};
-
-static struct fb_fix_screeninfo bfin_adv7393_fb_fix = {
- .id = "BFIN ADV7393",
- .smem_len = 720 * 480 * 2,
- .type = FB_TYPE_PACKED_PIXELS,
- .visual = FB_VISUAL_TRUECOLOR,
- .xpanstep = 0,
- .ypanstep = 0,
- .line_length = 720 * 2,
- .accel = FB_ACCEL_NONE
-};
-
-static struct fb_ops bfin_adv7393_fb_ops = {
- .owner = THIS_MODULE,
- .fb_open = bfin_adv7393_fb_open,
- .fb_release = bfin_adv7393_fb_release,
- .fb_check_var = bfin_adv7393_fb_check_var,
- .fb_pan_display = bfin_adv7393_fb_pan_display,
- .fb_blank = bfin_adv7393_fb_blank,
- .fb_fillrect = cfb_fillrect,
- .fb_copyarea = cfb_copyarea,
- .fb_imageblit = cfb_imageblit,
- .fb_cursor = bfin_adv7393_fb_cursor,
- .fb_setcolreg = bfin_adv7393_fb_setcolreg,
-};
-
-static int dma_desc_list(struct adv7393fb_device *fbdev, u16 arg)
-{
- if (arg == BUILD) { /* Build */
- fbdev->vb1 = l1_data_sram_zalloc(sizeof(struct dmasg));
- if (fbdev->vb1 == NULL)
- goto error;
-
- fbdev->av1 = l1_data_sram_zalloc(sizeof(struct dmasg));
- if (fbdev->av1 == NULL)
- goto error;
-
- fbdev->vb2 = l1_data_sram_zalloc(sizeof(struct dmasg));
- if (fbdev->vb2 == NULL)
- goto error;
-
- fbdev->av2 = l1_data_sram_zalloc(sizeof(struct dmasg));
- if (fbdev->av2 == NULL)
- goto error;
-
- /* Build linked DMA descriptor list */
- fbdev->vb1->next_desc_addr = fbdev->av1;
- fbdev->av1->next_desc_addr = fbdev->vb2;
- fbdev->vb2->next_desc_addr = fbdev->av2;
- fbdev->av2->next_desc_addr = fbdev->vb1;
-
- /* Save list head */
- fbdev->descriptor_list_head = fbdev->av2;
-
- /* Vertical Blanking Field 1 */
- fbdev->vb1->start_addr = VB_DUMMY_MEMORY_SOURCE;
- fbdev->vb1->cfg = DMA_CFG_VAL;
-
- fbdev->vb1->x_count =
- fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
-
- fbdev->vb1->x_modify = 0;
- fbdev->vb1->y_count = fbdev->modes[mode].vb1_lines;
- fbdev->vb1->y_modify = 0;
-
- /* Active Video Field 1 */
-
- fbdev->av1->start_addr = (unsigned long)fbdev->fb_mem;
- fbdev->av1->cfg = DMA_CFG_VAL;
- fbdev->av1->x_count =
- fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
- fbdev->av1->x_modify = fbdev->modes[mode].bpp / 8;
- fbdev->av1->y_count = fbdev->modes[mode].a_lines;
- fbdev->av1->y_modify =
- (fbdev->modes[mode].xres - fbdev->modes[mode].boeft_blank +
- 1) * (fbdev->modes[mode].bpp / 8);
-
- /* Vertical Blanking Field 2 */
-
- fbdev->vb2->start_addr = VB_DUMMY_MEMORY_SOURCE;
- fbdev->vb2->cfg = DMA_CFG_VAL;
- fbdev->vb2->x_count =
- fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
-
- fbdev->vb2->x_modify = 0;
- fbdev->vb2->y_count = fbdev->modes[mode].vb2_lines;
- fbdev->vb2->y_modify = 0;
-
- /* Active Video Field 2 */
-
- fbdev->av2->start_addr =
- (unsigned long)fbdev->fb_mem + fbdev->line_len;
-
- fbdev->av2->cfg = DMA_CFG_VAL;
-
- fbdev->av2->x_count =
- fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
-
- fbdev->av2->x_modify = (fbdev->modes[mode].bpp / 8);
- fbdev->av2->y_count = fbdev->modes[mode].a_lines;
-
- fbdev->av2->y_modify =
- (fbdev->modes[mode].xres - fbdev->modes[mode].boeft_blank +
- 1) * (fbdev->modes[mode].bpp / 8);
-
- return 1;
- }
-
-error:
- l1_data_sram_free(fbdev->vb1);
- l1_data_sram_free(fbdev->av1);
- l1_data_sram_free(fbdev->vb2);
- l1_data_sram_free(fbdev->av2);
-
- return 0;
-}
-
-static int bfin_config_dma(struct adv7393fb_device *fbdev)
-{
- BUG_ON(!(fbdev->fb_mem));
-
- set_dma_x_count(CH_PPI, fbdev->descriptor_list_head->x_count);
- set_dma_x_modify(CH_PPI, fbdev->descriptor_list_head->x_modify);
- set_dma_y_count(CH_PPI, fbdev->descriptor_list_head->y_count);
- set_dma_y_modify(CH_PPI, fbdev->descriptor_list_head->y_modify);
- set_dma_start_addr(CH_PPI, fbdev->descriptor_list_head->start_addr);
- set_dma_next_desc_addr(CH_PPI,
- fbdev->descriptor_list_head->next_desc_addr);
- set_dma_config(CH_PPI, fbdev->descriptor_list_head->cfg);
-
- return 1;
-}
-
-static void bfin_disable_dma(void)
-{
- bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
-}
-
-static void bfin_config_ppi(struct adv7393fb_device *fbdev)
-{
- if (ANOMALY_05000183) {
- bfin_write_TIMER2_CONFIG(WDTH_CAP);
- bfin_write_TIMER_ENABLE(TIMEN2);
- }
-
- bfin_write_PPI_CONTROL(0x381E);
- bfin_write_PPI_FRAME(fbdev->modes[mode].tot_lines);
- bfin_write_PPI_COUNT(fbdev->modes[mode].xres +
- fbdev->modes[mode].boeft_blank - 1);
- bfin_write_PPI_DELAY(fbdev->modes[mode].aoeft_blank - 1);
-}
-
-static void bfin_enable_ppi(void)
-{
- bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
-}
-
-static void bfin_disable_ppi(void)
-{
- bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
-}
-
-static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value)
-{
- return i2c_smbus_write_byte_data(client, reg, value);
-}
-
-static inline int adv7393_read(struct i2c_client *client, u8 reg)
-{
- return i2c_smbus_read_byte_data(client, reg);
-}
-
-static int
-adv7393_write_block(struct i2c_client *client,
- const u8 *data, unsigned int len)
-{
- int ret = -1;
- u8 reg;
-
- while (len >= 2) {
- reg = *data++;
- ret = adv7393_write(client, reg, *data++);
- if (ret < 0)
- break;
- len -= 2;
- }
-
- return ret;
-}
-
-static int adv7393_mode(struct i2c_client *client, u16 mode)
-{
- switch (mode) {
- case POWER_ON: /* ADV7393 Sleep mode OFF */
- adv7393_write(client, 0x00, 0x1E);
- break;
- case POWER_DOWN: /* ADV7393 Sleep mode ON */
- adv7393_write(client, 0x00, 0x1F);
- break;
- case BLANK_OFF: /* Pixel Data Valid */
- adv7393_write(client, 0x82, 0xCB);
- break;
- case BLANK_ON: /* Pixel Data Invalid */
- adv7393_write(client, 0x82, 0x8B);
- break;
- default:
- return -EINVAL;
- break;
- }
- return 0;
-}
-
-static irqreturn_t ppi_irq_error(int irq, void *dev_id)
-{
-
- struct adv7393fb_device *fbdev = (struct adv7393fb_device *)dev_id;
-
- u16 status = bfin_read_PPI_STATUS();
-
- pr_debug("%s: PPI Status = 0x%X\n", __func__, status);
-
- if (status) {
- bfin_disable_dma(); /* TODO: Check Sequence */
- bfin_disable_ppi();
- bfin_clear_PPI_STATUS();
- bfin_config_dma(fbdev);
- bfin_enable_ppi();
- }
-
- return IRQ_HANDLED;
-
-}
-
-static int proc_output(char *buf)
-{
- char *p = buf;
-
- p += sprintf(p,
- "Usage:\n"
- "echo 0x[REG][Value] > adv7393\n"
- "example: echo 0x1234 >adv7393\n"
- "writes 0x34 into Register 0x12\n");
-
- return p - buf;
-}
-
-static ssize_t
-adv7393_read_proc(struct file *file, char __user *buf,
- size_t size, loff_t *ppos)
-{
- static const char message[] = "Usage:\n"
- "echo 0x[REG][Value] > adv7393\n"
- "example: echo 0x1234 >adv7393\n"
- "writes 0x34 into Register 0x12\n";
- return simple_read_from_buffer(buf, size, ppos, message,
- sizeof(message));
-}
-
-static ssize_t
-adv7393_write_proc(struct file *file, const char __user * buffer,
- size_t count, loff_t *ppos)
-{
- struct adv7393fb_device *fbdev = PDE_DATA(file_inode(file));
- unsigned int val;
- int ret;
-
- ret = kstrtouint_from_user(buffer, count, 0, &val);
- if (ret)
- return -EFAULT;
-
- adv7393_write(fbdev->client, val >> 8, val & 0xff);
-
- return count;
-}
-
-static const struct file_operations fops = {
- .read = adv7393_read_proc,
- .write = adv7393_write_proc,
- .llseek = default_llseek,
-};
-
-static int bfin_adv7393_fb_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int ret = 0;
- struct proc_dir_entry *entry;
-
- struct adv7393fb_device *fbdev = NULL;
-
- if (mem > 2) {
- dev_err(&client->dev, "mem out of allowed range [1;2]\n");
- return -EINVAL;
- }
-
- if (mode >= ARRAY_SIZE(known_modes)) {
- dev_err(&client->dev, "mode %d: not supported", mode);
- return -EFAULT;
- }
-
- fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
- if (!fbdev) {
- dev_err(&client->dev, "failed to allocate device private record");
- return -ENOMEM;
- }
-
- i2c_set_clientdata(client, fbdev);
-
- fbdev->modes = known_modes;
- fbdev->client = client;
-
- fbdev->fb_len =
- mem * fbdev->modes[mode].xres * fbdev->modes[mode].xres *
- (fbdev->modes[mode].bpp / 8);
-
- fbdev->line_len =
- fbdev->modes[mode].xres * (fbdev->modes[mode].bpp / 8);
-
- /* Workaround "PPI Does Not Start Properly In Specific Mode" */
- if (ANOMALY_05000400) {
- ret = gpio_request_one(P_IDENT(P_PPI0_FS3), GPIOF_OUT_INIT_LOW,
- "PPI0_FS3");
- if (ret) {
- dev_err(&client->dev, "PPI0_FS3 GPIO request failed\n");
- ret = -EBUSY;
- goto free_fbdev;
- }
- }
-
- if (peripheral_request_list(ppi_pins, DRIVER_NAME)) {
- dev_err(&client->dev, "requesting PPI peripheral failed\n");
- ret = -EFAULT;
- goto free_gpio;
- }
-
- fbdev->fb_mem =
- dma_alloc_coherent(NULL, fbdev->fb_len, &fbdev->dma_handle,
- GFP_KERNEL);
-
- if (NULL == fbdev->fb_mem) {
- dev_err(&client->dev, "couldn't allocate dma buffer (%d bytes)\n",
- (u32) fbdev->fb_len);
- ret = -ENOMEM;
- goto free_ppi_pins;
- }
-
- fbdev->info.screen_base = (void *)fbdev->fb_mem;
- bfin_adv7393_fb_fix.smem_start = (int)fbdev->fb_mem;
-
- bfin_adv7393_fb_fix.smem_len = fbdev->fb_len;
- bfin_adv7393_fb_fix.line_length = fbdev->line_len;
-
- if (mem > 1)
- bfin_adv7393_fb_fix.ypanstep = 1;
-
- bfin_adv7393_fb_defined.red.length = 5;
- bfin_adv7393_fb_defined.green.length = 6;
- bfin_adv7393_fb_defined.blue.length = 5;
-
- bfin_adv7393_fb_defined.xres = fbdev->modes[mode].xres;
- bfin_adv7393_fb_defined.yres = fbdev->modes[mode].yres;
- bfin_adv7393_fb_defined.xres_virtual = fbdev->modes[mode].xres;
- bfin_adv7393_fb_defined.yres_virtual = mem * fbdev->modes[mode].yres;
- bfin_adv7393_fb_defined.bits_per_pixel = fbdev->modes[mode].bpp;
-
- fbdev->info.fbops = &bfin_adv7393_fb_ops;
- fbdev->info.var = bfin_adv7393_fb_defined;
- fbdev->info.fix = bfin_adv7393_fb_fix;
- fbdev->info.par = &bfin_par;
- fbdev->info.flags = FBINFO_DEFAULT;
-
- fbdev->info.pseudo_palette = kzalloc(sizeof(u32) * 16, GFP_KERNEL);
- if (!fbdev->info.pseudo_palette) {
- dev_err(&client->dev, "failed to allocate pseudo_palette\n");
- ret = -ENOMEM;
- goto free_fb_mem;
- }
-
- if (fb_alloc_cmap(&fbdev->info.cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
- dev_err(&client->dev, "failed to allocate colormap (%d entries)\n",
- BFIN_LCD_NBR_PALETTE_ENTRIES);
- ret = -EFAULT;
- goto free_palette;
- }
-
- if (request_dma(CH_PPI, "BF5xx_PPI_DMA") < 0) {
- dev_err(&client->dev, "unable to request PPI DMA\n");
- ret = -EFAULT;
- goto free_cmap;
- }
-
- if (request_irq(IRQ_PPI_ERROR, ppi_irq_error, 0,
- "PPI ERROR", fbdev) < 0) {
- dev_err(&client->dev, "unable to request PPI ERROR IRQ\n");
- ret = -EFAULT;
- goto free_ch_ppi;
- }
-
- fbdev->open = 0;
-
- ret = adv7393_write_block(client, fbdev->modes[mode].adv7393_i2c_initd,
- fbdev->modes[mode].adv7393_i2c_initd_len);
-
- if (ret) {
- dev_err(&client->dev, "i2c attach: init error\n");
- goto free_irq_ppi;
- }
-
-
- if (register_framebuffer(&fbdev->info) < 0) {
- dev_err(&client->dev, "unable to register framebuffer\n");
- ret = -EFAULT;
- goto free_irq_ppi;
- }
-
- dev_info(&client->dev, "fb%d: %s frame buffer device\n",
- fbdev->info.node, fbdev->info.fix.id);
- dev_info(&client->dev, "fb memory address : 0x%p\n", fbdev->fb_mem);
-
- entry = proc_create_data("driver/adv7393", 0, NULL, &fops, fbdev);
- if (!entry) {
- dev_err(&client->dev, "unable to create /proc entry\n");
- ret = -EFAULT;
- goto free_fb;
- }
- return 0;
-
-free_fb:
- unregister_framebuffer(&fbdev->info);
-free_irq_ppi:
- free_irq(IRQ_PPI_ERROR, fbdev);
-free_ch_ppi:
- free_dma(CH_PPI);
-free_cmap:
- fb_dealloc_cmap(&fbdev->info.cmap);
-free_palette:
- kfree(fbdev->info.pseudo_palette);
-free_fb_mem:
- dma_free_coherent(NULL, fbdev->fb_len, fbdev->fb_mem,
- fbdev->dma_handle);
-free_ppi_pins:
- peripheral_free_list(ppi_pins);
-free_gpio:
- if (ANOMALY_05000400)
- gpio_free(P_IDENT(P_PPI0_FS3));
-free_fbdev:
- kfree(fbdev);
-
- return ret;
-}
-
-static int bfin_adv7393_fb_open(struct fb_info *info, int user)
-{
- struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
-
- fbdev->info.screen_base = (void *)fbdev->fb_mem;
- if (!fbdev->info.screen_base) {
- dev_err(&fbdev->client->dev, "unable to map device\n");
- return -ENOMEM;
- }
-
- fbdev->open = 1;
- dma_desc_list(fbdev, BUILD);
- adv7393_mode(fbdev->client, BLANK_OFF);
- bfin_config_ppi(fbdev);
- bfin_config_dma(fbdev);
- bfin_enable_ppi();
-
- return 0;
-}
-
-static int bfin_adv7393_fb_release(struct fb_info *info, int user)
-{
- struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
-
- adv7393_mode(fbdev->client, BLANK_ON);
- bfin_disable_dma();
- bfin_disable_ppi();
- dma_desc_list(fbdev, DESTRUCT);
- fbdev->open = 0;
- return 0;
-}
-
-static int
-bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
-{
-
- switch (var->bits_per_pixel) {
- case 16:/* DIRECTCOLOUR, 64k */
- var->red.offset = info->var.red.offset;
- var->green.offset = info->var.green.offset;
- var->blue.offset = info->var.blue.offset;
- var->red.length = info->var.red.length;
- var->green.length = info->var.green.length;
- var->blue.length = info->var.blue.length;
- var->transp.offset = 0;
- var->transp.length = 0;
- var->transp.msb_right = 0;
- var->red.msb_right = 0;
- var->green.msb_right = 0;
- var->blue.msb_right = 0;
- break;
- default:
- pr_debug("%s: depth not supported: %u BPP\n", __func__,
- var->bits_per_pixel);
- return -EINVAL;
- }
-
- if (info->var.xres != var->xres ||
- info->var.yres != var->yres ||
- info->var.xres_virtual != var->xres_virtual ||
- info->var.yres_virtual != var->yres_virtual) {
- pr_debug("%s: Resolution not supported: X%u x Y%u\n",
- __func__, var->xres, var->yres);
- return -EINVAL;
- }
-
- /*
- * Memory limit
- */
-
- if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
- pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
- __func__, var->yres_virtual);
- return -ENOMEM;
- }
-
- return 0;
-}
-
-static int
-bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
-{
- int dy;
- u32 dmaaddr;
- struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
-
- if (!var || !info)
- return -EINVAL;
-
- if (var->xoffset - info->var.xoffset) {
- /* No support for X panning for now! */
- return -EINVAL;
- }
- dy = var->yoffset - info->var.yoffset;
-
- if (dy) {
- pr_debug("%s: Panning screen of %d lines\n", __func__, dy);
-
- dmaaddr = fbdev->av1->start_addr;
- dmaaddr += (info->fix.line_length * dy);
- /* TODO: Wait for current frame to finished */
-
- fbdev->av1->start_addr = (unsigned long)dmaaddr;
- fbdev->av2->start_addr = (unsigned long)dmaaddr + fbdev->line_len;
- }
-
- return 0;
-
-}
-
-/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
-static int bfin_adv7393_fb_blank(int blank, struct fb_info *info)
-{
- struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
-
- switch (blank) {
-
- case VESA_NO_BLANKING:
- /* Turn on panel */
- adv7393_mode(fbdev->client, BLANK_OFF);
- break;
-
- case VESA_VSYNC_SUSPEND:
- case VESA_HSYNC_SUSPEND:
- case VESA_POWERDOWN:
- /* Turn off panel */
- adv7393_mode(fbdev->client, BLANK_ON);
- break;
-
- default:
- return -EINVAL;
- break;
- }
- return 0;
-}
-
-int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
-{
- if (nocursor)
- return 0;
- else
- return -EINVAL; /* just to force soft_cursor() call */
-}
-
-static int bfin_adv7393_fb_setcolreg(u_int regno, u_int red, u_int green,
- u_int blue, u_int transp,
- struct fb_info *info)
-{
- if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
- return -EINVAL;
-
- if (info->var.grayscale)
- /* grayscale = 0.30*R + 0.59*G + 0.11*B */
- red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
-
- if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
- u32 value;
- /* Place color in the pseudopalette */
- if (regno > 16)
- return -EINVAL;
-
- red >>= (16 - info->var.red.length);
- green >>= (16 - info->var.green.length);
- blue >>= (16 - info->var.blue.length);
-
- value = (red << info->var.red.offset) |
- (green << info->var.green.offset)|
- (blue << info->var.blue.offset);
- value &= 0xFFFF;
-
- ((u32 *) (info->pseudo_palette))[regno] = value;
- }
-
- return 0;
-}
-
-static int bfin_adv7393_fb_remove(struct i2c_client *client)
-{
- struct adv7393fb_device *fbdev = i2c_get_clientdata(client);
-
- adv7393_mode(client, POWER_DOWN);
-
- if (fbdev->fb_mem)
- dma_free_coherent(NULL, fbdev->fb_len, fbdev->fb_mem, fbdev->dma_handle);
- free_dma(CH_PPI);
- free_irq(IRQ_PPI_ERROR, fbdev);
- unregister_framebuffer(&fbdev->info);
- remove_proc_entry("driver/adv7393", NULL);
- fb_dealloc_cmap(&fbdev->info.cmap);
- kfree(fbdev->info.pseudo_palette);
-
- if (ANOMALY_05000400)
- gpio_free(P_IDENT(P_PPI0_FS3)); /* FS3 */
- peripheral_free_list(ppi_pins);
- kfree(fbdev);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int bfin_adv7393_fb_suspend(struct device *dev)
-{
- struct adv7393fb_device *fbdev = dev_get_drvdata(dev);
-
- if (fbdev->open) {
- bfin_disable_dma();
- bfin_disable_ppi();
- dma_desc_list(fbdev, DESTRUCT);
- }
- adv7393_mode(fbdev->client, POWER_DOWN);
-
- return 0;
-}
-
-static int bfin_adv7393_fb_resume(struct device *dev)
-{
- struct adv7393fb_device *fbdev = dev_get_drvdata(dev);
-
- adv7393_mode(fbdev->client, POWER_ON);
-
- if (fbdev->open) {
- dma_desc_list(fbdev, BUILD);
- bfin_config_ppi(fbdev);
- bfin_config_dma(fbdev);
- bfin_enable_ppi();
- }
-
- return 0;
-}
-
-static const struct dev_pm_ops bfin_adv7393_dev_pm_ops = {
- .suspend = bfin_adv7393_fb_suspend,
- .resume = bfin_adv7393_fb_resume,
-};
-#endif
-
-static const struct i2c_device_id bfin_adv7393_id[] = {
- {DRIVER_NAME, 0},
- {}
-};
-
-MODULE_DEVICE_TABLE(i2c, bfin_adv7393_id);
-
-static struct i2c_driver bfin_adv7393_fb_driver = {
- .driver = {
- .name = DRIVER_NAME,
-#ifdef CONFIG_PM
- .pm = &bfin_adv7393_dev_pm_ops,
-#endif
- },
- .probe = bfin_adv7393_fb_probe,
- .remove = bfin_adv7393_fb_remove,
- .id_table = bfin_adv7393_id,
-};
-
-static int __init bfin_adv7393_fb_driver_init(void)
-{
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- request_module("i2c-bfin-twi");
-#else
- request_module("i2c-gpio");
-#endif
-
- return i2c_add_driver(&bfin_adv7393_fb_driver);
-}
-module_init(bfin_adv7393_fb_driver_init);
-
-static void __exit bfin_adv7393_fb_driver_cleanup(void)
-{
- i2c_del_driver(&bfin_adv7393_fb_driver);
-}
-module_exit(bfin_adv7393_fb_driver_cleanup);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("Frame buffer driver for ADV7393/2 Video Encoder");
-
-module_param(mode, int, 0);
-MODULE_PARM_DESC(mode,
- "Video Mode (0=NTSC,1=PAL,2=NTSC 640x480,3=PAL 640x480,4=NTSC YCbCr input,5=PAL YCbCr input)");
-
-module_param(mem, int, 0);
-MODULE_PARM_DESC(mem,
- "Size of frame buffer memory 1=Single 2=Double Size (allows y-panning / frame stacking)");
-
-module_param(nocursor, int, 0644);
-MODULE_PARM_DESC(nocursor, "cursor enable/disable");
diff --git a/drivers/video/fbdev/bfin_adv7393fb.h b/drivers/video/fbdev/bfin_adv7393fb.h
deleted file mode 100644
index afd0380..0000000
--- a/drivers/video/fbdev/bfin_adv7393fb.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Frame buffer driver for ADV7393/2 video encoder
- *
- * Copyright 2006-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or late.
- */
-
-#ifndef __BFIN_ADV7393FB_H__
-#define __BFIN_ADV7393FB_H__
-
-#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
-
-#ifdef CONFIG_NTSC
-# define VMODE 0
-#endif
-#ifdef CONFIG_PAL
-# define VMODE 1
-#endif
-#ifdef CONFIG_NTSC_640x480
-# define VMODE 2
-#endif
-#ifdef CONFIG_PAL_640x480
-# define VMODE 3
-#endif
-#ifdef CONFIG_NTSC_YCBCR
-# define VMODE 4
-#endif
-#ifdef CONFIG_PAL_YCBCR
-# define VMODE 5
-#endif
-
-#ifndef VMODE
-# define VMODE 1
-#endif
-
-#ifdef CONFIG_ADV7393_2XMEM
-# define VMEM 2
-#else
-# define VMEM 1
-#endif
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
-# define DMA_CFG_VAL 0x7935 /* Set Sync Bit */
-# define VB_DUMMY_MEMORY_SOURCE L1_DATA_B_START
-#else
-# define DMA_CFG_VAL 0x7915
-# define VB_DUMMY_MEMORY_SOURCE BOOT_ROM_START
-#endif
-
-enum {
- DESTRUCT,
- BUILD,
-};
-
-enum {
- POWER_ON,
- POWER_DOWN,
- BLANK_ON,
- BLANK_OFF,
-};
-
-struct adv7393fb_modes {
- const s8 name[25]; /* Full name */
- u16 xres; /* Active Horizonzal Pixels */
- u16 yres; /* Active Vertical Pixels */
- u16 bpp;
- u16 vmode;
- u16 a_lines; /* Active Lines per Field */
- u16 vb1_lines; /* Vertical Blanking Field 1 Lines */
- u16 vb2_lines; /* Vertical Blanking Field 2 Lines */
- u16 tot_lines; /* Total Lines per Frame */
- u16 boeft_blank; /* Before Odd/Even Field Transition No. of Blank Pixels */
- u16 aoeft_blank; /* After Odd/Even Field Transition No. of Blank Pixels */
- const s8 *adv7393_i2c_initd;
- u16 adv7393_i2c_initd_len;
-};
-
-static const u8 init_NTSC_TESTPATTERN[] = {
- 0x00, 0x1E, /* Power up all DACs and PLL */
- 0x01, 0x00, /* SD-Only Mode */
- 0x80, 0x10, /* SSAF Luma Filter Enabled, NTSC Mode */
- 0x82, 0xCB, /* Step control on, pixel data valid, pedestal on, PrPb SSAF on, CVBS/YC output */
- 0x84, 0x40, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
-};
-
-static const u8 init_NTSC[] = {
- 0x00, 0x1E, /* Power up all DACs and PLL */
- 0xC3, 0x26, /* Program RGB->YCrCb Color Space conversion matrix */
- 0xC5, 0x12, /* Program RGB->YCrCb Color Space conversion matrix */
- 0xC2, 0x4A, /* Program RGB->YCrCb Color Space conversion matrix */
- 0xC6, 0x5E, /* Program RGB->YCrCb Color Space conversion matrix */
- 0xBD, 0x19, /* Program RGB->YCrCb Color Space conversion matrix */
- 0xBF, 0x42, /* Program RGB->YCrCb Color Space conversion matrix */
- 0x8C, 0x1F, /* NTSC Subcarrier Frequency */
- 0x8D, 0x7C, /* NTSC Subcarrier Frequency */
- 0x8E, 0xF0, /* NTSC Subcarrier Frequency */
- 0x8F, 0x21, /* NTSC Subcarrier Frequency */
- 0x01, 0x00, /* SD-Only Mode */
- 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
- 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
- 0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
- 0x86, 0x82,
- 0x8B, 0x11,
- 0x88, 0x20,
- 0x8A, 0x0d,
-};
-
-static const u8 init_PAL[] = {
- 0x00, 0x1E, /* Power up all DACs and PLL */
- 0xC3, 0x26, /* Program RGB->YCrCb Color Space conversion matrix */
- 0xC5, 0x12, /* Program RGB->YCrCb Color Space conversion matrix */
- 0xC2, 0x4A, /* Program RGB->YCrCb Color Space conversion matrix */
- 0xC6, 0x5E, /* Program RGB->YCrCb Color Space conversion matrix */
- 0xBD, 0x19, /* Program RGB->YCrCb Color Space conversion matrix */
- 0xBF, 0x42, /* Program RGB->YCrCb Color Space conversion matrix */
- 0x8C, 0xCB, /* PAL Subcarrier Frequency */
- 0x8D, 0x8A, /* PAL Subcarrier Frequency */
- 0x8E, 0x09, /* PAL Subcarrier Frequency */
- 0x8F, 0x2A, /* PAL Subcarrier Frequency */
- 0x01, 0x00, /* SD-Only Mode */
- 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
- 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
- 0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
- 0x86, 0x82,
- 0x8B, 0x11,
- 0x88, 0x20,
- 0x8A, 0x0d,
-};
-
-static const u8 init_NTSC_YCbCr[] = {
- 0x00, 0x1E, /* Power up all DACs and PLL */
- 0x8C, 0x1F, /* NTSC Subcarrier Frequency */
- 0x8D, 0x7C, /* NTSC Subcarrier Frequency */
- 0x8E, 0xF0, /* NTSC Subcarrier Frequency */
- 0x8F, 0x21, /* NTSC Subcarrier Frequency */
- 0x01, 0x00, /* SD-Only Mode */
- 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
- 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
- 0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */
- 0x86, 0x82,
- 0x8B, 0x11,
- 0x88, 0x08,
- 0x8A, 0x0d,
-};
-
-static const u8 init_PAL_YCbCr[] = {
- 0x00, 0x1E, /* Power up all DACs and PLL */
- 0x8C, 0xCB, /* PAL Subcarrier Frequency */
- 0x8D, 0x8A, /* PAL Subcarrier Frequency */
- 0x8E, 0x09, /* PAL Subcarrier Frequency */
- 0x8F, 0x2A, /* PAL Subcarrier Frequency */
- 0x01, 0x00, /* SD-Only Mode */
- 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
- 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
- 0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */
- 0x86, 0x82,
- 0x8B, 0x11,
- 0x88, 0x08,
- 0x8A, 0x0d,
-};
-
-static struct adv7393fb_modes known_modes[] = {
- /* NTSC 720x480 CRT */
- {
- .name = "NTSC 720x480",
- .xres = 720,
- .yres = 480,
- .bpp = 16,
- .vmode = FB_VMODE_INTERLACED,
- .a_lines = 240,
- .vb1_lines = 22,
- .vb2_lines = 23,
- .tot_lines = 525,
- .boeft_blank = 16,
- .aoeft_blank = 122,
- .adv7393_i2c_initd = init_NTSC,
- .adv7393_i2c_initd_len = sizeof(init_NTSC)
- },
- /* PAL 720x480 CRT */
- {
- .name = "PAL 720x576",
- .xres = 720,
- .yres = 576,
- .bpp = 16,
- .vmode = FB_VMODE_INTERLACED,
- .a_lines = 288,
- .vb1_lines = 24,
- .vb2_lines = 25,
- .tot_lines = 625,
- .boeft_blank = 12,
- .aoeft_blank = 132,
- .adv7393_i2c_initd = init_PAL,
- .adv7393_i2c_initd_len = sizeof(init_PAL)
- },
- /* NTSC 640x480 CRT Experimental */
- {
- .name = "NTSC 640x480",
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .vmode = FB_VMODE_INTERLACED,
- .a_lines = 240,
- .vb1_lines = 22,
- .vb2_lines = 23,
- .tot_lines = 525,
- .boeft_blank = 16 + 40,
- .aoeft_blank = 122 + 40,
- .adv7393_i2c_initd = init_NTSC,
- .adv7393_i2c_initd_len = sizeof(init_NTSC)
- },
- /* PAL 640x480 CRT Experimental */
- {
- .name = "PAL 640x480",
- .xres = 640,
- .yres = 480,
- .bpp = 16,
- .vmode = FB_VMODE_INTERLACED,
- .a_lines = 288 - 20,
- .vb1_lines = 24 + 20,
- .vb2_lines = 25 + 20,
- .tot_lines = 625,
- .boeft_blank = 12 + 40,
- .aoeft_blank = 132 + 40,
- .adv7393_i2c_initd = init_PAL,
- .adv7393_i2c_initd_len = sizeof(init_PAL)
- },
- /* NTSC 720x480 YCbCR */
- {
- .name = "NTSC 720x480 YCbCR",
- .xres = 720,
- .yres = 480,
- .bpp = 16,
- .vmode = FB_VMODE_INTERLACED,
- .a_lines = 240,
- .vb1_lines = 22,
- .vb2_lines = 23,
- .tot_lines = 525,
- .boeft_blank = 16,
- .aoeft_blank = 122,
- .adv7393_i2c_initd = init_NTSC_YCbCr,
- .adv7393_i2c_initd_len = sizeof(init_NTSC_YCbCr)
- },
- /* PAL 720x480 CRT */
- {
- .name = "PAL 720x576 YCbCR",
- .xres = 720,
- .yres = 576,
- .bpp = 16,
- .vmode = FB_VMODE_INTERLACED,
- .a_lines = 288,
- .vb1_lines = 24,
- .vb2_lines = 25,
- .tot_lines = 625,
- .boeft_blank = 12,
- .aoeft_blank = 132,
- .adv7393_i2c_initd = init_PAL_YCbCr,
- .adv7393_i2c_initd_len = sizeof(init_PAL_YCbCr)
- }
-};
-
-struct adv7393fb_regs {
-
-};
-
-struct adv7393fb_device {
- struct fb_info info; /* FB driver info record */
-
- struct i2c_client *client;
-
- struct dmasg *descriptor_list_head;
- struct dmasg *vb1;
- struct dmasg *av1;
- struct dmasg *vb2;
- struct dmasg *av2;
-
- dma_addr_t dma_handle;
-
- struct fb_info bfin_adv7393_fb;
-
- struct adv7393fb_modes *modes;
-
- struct adv7393fb_regs *regs; /* Registers memory map */
- size_t regs_len;
- size_t fb_len;
- size_t line_len;
- u16 open;
- u16 *fb_mem; /* RGB Buffer */
-
-};
-
-#define to_adv7393fb_device(_info) \
- (_info ? container_of(_info, struct adv7393fb_device, info) : NULL);
-
-static int bfin_adv7393_fb_open(struct fb_info *info, int user);
-static int bfin_adv7393_fb_release(struct fb_info *info, int user);
-static int bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var,
- struct fb_info *info);
-
-static int bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var,
- struct fb_info *info);
-
-static int bfin_adv7393_fb_blank(int blank, struct fb_info *info);
-
-static void bfin_config_ppi(struct adv7393fb_device *fbdev);
-static int bfin_config_dma(struct adv7393fb_device *fbdev);
-static void bfin_disable_dma(void);
-static void bfin_enable_ppi(void);
-static void bfin_disable_ppi(void);
-
-static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value);
-static inline int adv7393_read(struct i2c_client *client, u8 reg);
-static int adv7393_write_block(struct i2c_client *client, const u8 *data,
- unsigned int len);
-
-int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor);
-static int bfin_adv7393_fb_setcolreg(u_int, u_int, u_int, u_int,
- u_int, struct fb_info *info);
-
-#endif
diff --git a/drivers/video/logo/Kconfig b/drivers/video/logo/Kconfig
index 0037104..723a649 100644
--- a/drivers/video/logo/Kconfig
+++ b/drivers/video/logo/Kconfig
@@ -27,16 +27,6 @@ config LOGO_LINUX_CLUT224
bool "Standard 224-color Linux logo"
default y
-config LOGO_BLACKFIN_VGA16
- bool "16-colour Blackfin Processor Linux logo"
- depends on BLACKFIN
- default y
-
-config LOGO_BLACKFIN_CLUT224
- bool "224-colour Blackfin Processor Linux logo"
- depends on BLACKFIN
- default y
-
config LOGO_DEC_CLUT224
bool "224-color Digital Equipment Corporation Linux logo"
depends on MACH_DECSTATION || ALPHA
diff --git a/drivers/video/logo/Makefile b/drivers/video/logo/Makefile
index 6194373..7bba02c 100644
--- a/drivers/video/logo/Makefile
+++ b/drivers/video/logo/Makefile
@@ -5,8 +5,6 @@ obj-$(CONFIG_LOGO) += logo.o
obj-$(CONFIG_LOGO_LINUX_MONO) += logo_linux_mono.o
obj-$(CONFIG_LOGO_LINUX_VGA16) += logo_linux_vga16.o
obj-$(CONFIG_LOGO_LINUX_CLUT224) += logo_linux_clut224.o
-obj-$(CONFIG_LOGO_BLACKFIN_CLUT224) += logo_blackfin_clut224.o
-obj-$(CONFIG_LOGO_BLACKFIN_VGA16) += logo_blackfin_vga16.o
obj-$(CONFIG_LOGO_DEC_CLUT224) += logo_dec_clut224.o
obj-$(CONFIG_LOGO_MAC_CLUT224) += logo_mac_clut224.o
obj-$(CONFIG_LOGO_PARISC_CLUT224) += logo_parisc_clut224.o
diff --git a/drivers/video/logo/logo.c b/drivers/video/logo/logo.c
index 4d50bfd..05b613e 100644
--- a/drivers/video/logo/logo.c
+++ b/drivers/video/logo/logo.c
@@ -63,10 +63,6 @@ const struct linux_logo * __ref fb_find_logo(int depth)
/* Generic Linux logo */
logo = &logo_linux_vga16;
#endif
-#ifdef CONFIG_LOGO_BLACKFIN_VGA16
- /* Blackfin processor logo */
- logo = &logo_blackfin_vga16;
-#endif
#ifdef CONFIG_LOGO_SUPERH_VGA16
/* SuperH Linux logo */
logo = &logo_superh_vga16;
@@ -78,10 +74,6 @@ const struct linux_logo * __ref fb_find_logo(int depth)
/* Generic Linux logo */
logo = &logo_linux_clut224;
#endif
-#ifdef CONFIG_LOGO_BLACKFIN_CLUT224
- /* Blackfin Linux logo */
- logo = &logo_blackfin_clut224;
-#endif
#ifdef CONFIG_LOGO_DEC_CLUT224
/* DEC Linux logo on MIPS/MIPS64 or ALPHA */
logo = &logo_dec_clut224;
diff --git a/drivers/video/logo/logo_blackfin_clut224.ppm b/drivers/video/logo/logo_blackfin_clut224.ppm
deleted file mode 100644
index dc9a50a..0000000
--- a/drivers/video/logo/logo_blackfin_clut224.ppm
+++ /dev/null
@@ -1,1127 +0,0 @@
-P3
-# This was generated by the GIMP & Netpbm tools
-# gimp linux_bf.svg (create 80x80 save as linux_bf.ppm)
-# pnmquant 224 linux_bf.ppm | pnmnoraw > logo_blackfin_clut224.ppm
-#
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diff --git a/include/linux/fb.h b/include/linux/fb.h
index f577d3c..0c20da7 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -571,8 +571,7 @@ static inline struct apertures_struct *alloc_apertures(unsigned int max_num) {
#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || \
defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || \
- defined(__avr32__) || defined(__bfin__) || defined(__arm__) || \
- defined(__aarch64__)
+ defined(__avr32__) || defined(__arm__) || defined(__aarch64__)
#define fb_readb __raw_readb
#define fb_readw __raw_readw
diff --git a/include/linux/linux_logo.h b/include/linux/linux_logo.h
index 5e3581d..9e1ec52 100644
--- a/include/linux/linux_logo.h
+++ b/include/linux/linux_logo.h
@@ -36,8 +36,6 @@ struct linux_logo {
extern const struct linux_logo logo_linux_mono;
extern const struct linux_logo logo_linux_vga16;
extern const struct linux_logo logo_linux_clut224;
-extern const struct linux_logo logo_blackfin_vga16;
-extern const struct linux_logo logo_blackfin_clut224;
extern const struct linux_logo logo_dec_clut224;
extern const struct linux_logo logo_mac_clut224;
extern const struct linux_logo logo_parisc_clut224;
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 13/28] cpufreq: Remove Blackfin CPU frequency support
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2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 12/28] video: Remove Blackfin video support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 14/28] mtd: Remove Blackfin MTD support Aaron Wu
` (14 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin CPU frequency support
---
drivers/cpufreq/Makefile | 1 -
drivers/cpufreq/blackfin-cpufreq.c | 217 ---
drivers/cpufreq/cpufreq.c | 2612 ------------------------------------
3 files changed, 2830 deletions(-)
delete mode 100644 drivers/cpufreq/blackfin-cpufreq.c
delete mode 100644 drivers/cpufreq/cpufreq.c
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index c60c1e1..43e4254 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -100,7 +100,6 @@ obj-$(CONFIG_POWERNV_CPUFREQ) += powernv-cpufreq.o
##################################################################################
# Other platform drivers
-obj-$(CONFIG_BFIN_CPU_FREQ) += blackfin-cpufreq.o
obj-$(CONFIG_BMIPS_CPUFREQ) += bmips-cpufreq.o
obj-$(CONFIG_CRIS_MACH_ARTPEC3) += cris-artpec3-cpufreq.o
obj-$(CONFIG_ETRAXFS) += cris-etraxfs-cpufreq.o
diff --git a/drivers/cpufreq/blackfin-cpufreq.c b/drivers/cpufreq/blackfin-cpufreq.c
deleted file mode 100644
index 12e97d8..0000000
--- a/drivers/cpufreq/blackfin-cpufreq.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * Blackfin core clock scaling
- *
- * Copyright 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/fs.h>
-#include <linux/delay.h>
-#include <asm/blackfin.h>
-#include <asm/time.h>
-#include <asm/dpmc.h>
-
-
-/* this is the table of CCLK frequencies, in Hz */
-/* .driver_data is the entry in the auxiliary dpm_state_table[] */
-static struct cpufreq_frequency_table bfin_freq_table[] = {
- {
- .frequency = CPUFREQ_TABLE_END,
- .driver_data = 0,
- },
- {
- .frequency = CPUFREQ_TABLE_END,
- .driver_data = 1,
- },
- {
- .frequency = CPUFREQ_TABLE_END,
- .driver_data = 2,
- },
- {
- .frequency = CPUFREQ_TABLE_END,
- .driver_data = 0,
- },
-};
-
-static struct bfin_dpm_state {
- unsigned int csel; /* system clock divider */
- unsigned int tscale; /* change the divider on the core timer interrupt */
-} dpm_state_table[3];
-
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
-/*
- * normalized to maximum frequency offset for CYCLES,
- * used in time-ts cycles clock source, but could be used
- * somewhere also.
- */
-unsigned long long __bfin_cycles_off;
-unsigned int __bfin_cycles_mod;
-#endif
-
-/**************************************************************************/
-static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
-{
-
- unsigned long csel, min_cclk;
- int index;
-
- /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
-#if ANOMALY_05000273 || ANOMALY_05000274 || \
- (!(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) \
- && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
- min_cclk = sclk * 2;
-#else
- min_cclk = sclk;
-#endif
-
-#ifndef CONFIG_BF60x
- csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
-#else
- csel = bfin_read32(CGU0_DIV) & 0x1F;
-#endif
-
- for (index = 0; (cclk >> index) >= min_cclk && csel <= 3 && index < 3; index++, csel++) {
- bfin_freq_table[index].frequency = cclk >> index;
-#ifndef CONFIG_BF60x
- dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
-#else
- dpm_state_table[index].csel = csel;
-#endif
- dpm_state_table[index].tscale = (TIME_SCALE >> index) - 1;
-
- pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
- bfin_freq_table[index].frequency,
- dpm_state_table[index].csel,
- dpm_state_table[index].tscale);
- }
- return;
-}
-
-static void bfin_adjust_core_timer(void *info)
-{
- unsigned int tscale;
- unsigned int index = *(unsigned int *)info;
-
- /* we have to adjust the core timer, because it is using cclk */
- tscale = dpm_state_table[index].tscale;
- bfin_write_TSCALE(tscale);
- return;
-}
-
-static unsigned int bfin_getfreq_khz(unsigned int cpu)
-{
- /* Both CoreA/B have the same core clock */
- return get_cclk() / 1000;
-}
-
-#ifdef CONFIG_BF60x
-static int cpu_set_cclk(int cpu, unsigned long new)
-{
- struct clk *clk;
- int ret;
-
- clk = clk_get(NULL, "CCLK");
- if (IS_ERR(clk))
- return -ENODEV;
-
- ret = clk_set_rate(clk, new);
- clk_put(clk);
- return ret;
-}
-#endif
-
-static int bfin_target(struct cpufreq_policy *policy, unsigned int index)
-{
-#ifndef CONFIG_BF60x
- unsigned int plldiv;
-#endif
- static unsigned long lpj_ref;
- static unsigned int lpj_ref_freq;
- unsigned int old_freq, new_freq;
- int ret = 0;
-
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
- cycles_t cycles;
-#endif
-
- old_freq = bfin_getfreq_khz(0);
- new_freq = bfin_freq_table[index].frequency;
-
-#ifndef CONFIG_BF60x
- plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
- bfin_write_PLL_DIV(plldiv);
-#else
- ret = cpu_set_cclk(policy->cpu, new_freq * 1000);
- if (ret != 0) {
- WARN_ONCE(ret, "cpufreq set freq failed %d\n", ret);
- return ret;
- }
-#endif
- on_each_cpu(bfin_adjust_core_timer, &index, 1);
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
- cycles = get_cycles();
- SSYNC();
- cycles += 10; /* ~10 cycles we lose after get_cycles() */
- __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index);
- __bfin_cycles_mod = index;
-#endif
- if (!lpj_ref_freq) {
- lpj_ref = loops_per_jiffy;
- lpj_ref_freq = old_freq;
- }
- if (new_freq != old_freq) {
- loops_per_jiffy = cpufreq_scale(lpj_ref,
- lpj_ref_freq, new_freq);
- }
-
- return ret;
-}
-
-static int __bfin_cpu_init(struct cpufreq_policy *policy)
-{
-
- unsigned long cclk, sclk;
-
- cclk = get_cclk() / 1000;
- sclk = get_sclk() / 1000;
-
- if (policy->cpu == CPUFREQ_CPU)
- bfin_init_tables(cclk, sclk);
-
- policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
-
- return cpufreq_table_validate_and_show(policy, bfin_freq_table);
-}
-
-static struct cpufreq_driver bfin_driver = {
- .verify = cpufreq_generic_frequency_table_verify,
- .target_index = bfin_target,
- .get = bfin_getfreq_khz,
- .init = __bfin_cpu_init,
- .name = "bfin cpufreq",
- .attr = cpufreq_generic_attr,
-};
-
-static int __init bfin_cpu_init(void)
-{
- return cpufreq_register_driver(&bfin_driver);
-}
-
-static void __exit bfin_cpu_exit(void)
-{
- cpufreq_unregister_driver(&bfin_driver);
-}
-
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("cpufreq driver for Blackfin");
-MODULE_LICENSE("GPL");
-
-module_init(bfin_cpu_init);
-module_exit(bfin_cpu_exit);
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
deleted file mode 100644
index de33ebf..0000000
--- a/drivers/cpufreq/cpufreq.c
+++ /dev/null
@@ -1,2612 +0,0 @@
-/*
- * linux/drivers/cpufreq/cpufreq.c
- *
- * Copyright (C) 2001 Russell King
- * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
- * (C) 2013 Viresh Kumar <viresh.kumar@linaro.org>
- *
- * Oct 2005 - Ashok Raj <ashok.raj@intel.com>
- * Added handling for CPU hotplug
- * Feb 2006 - Jacob Shin <jacob.shin@amd.com>
- * Fix handling for CPU hotplug -- affected CPUs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/cpu.h>
-#include <linux/cpufreq.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/slab.h>
-#include <linux/suspend.h>
-#include <linux/syscore_ops.h>
-#include <linux/tick.h>
-#include <trace/events/power.h>
-
-static LIST_HEAD(cpufreq_policy_list);
-
-static inline bool policy_is_inactive(struct cpufreq_policy *policy)
-{
- return cpumask_empty(policy->cpus);
-}
-
-/* Macros to iterate over CPU policies */
-#define for_each_suitable_policy(__policy, __active) \
- list_for_each_entry(__policy, &cpufreq_policy_list, policy_list) \
- if ((__active) == !policy_is_inactive(__policy))
-
-#define for_each_active_policy(__policy) \
- for_each_suitable_policy(__policy, true)
-#define for_each_inactive_policy(__policy) \
- for_each_suitable_policy(__policy, false)
-
-#define for_each_policy(__policy) \
- list_for_each_entry(__policy, &cpufreq_policy_list, policy_list)
-
-/* Iterate over governors */
-static LIST_HEAD(cpufreq_governor_list);
-#define for_each_governor(__governor) \
- list_for_each_entry(__governor, &cpufreq_governor_list, governor_list)
-
-/**
- * The "cpufreq driver" - the arch- or hardware-dependent low
- * level driver of CPUFreq support, and its spinlock. This lock
- * also protects the cpufreq_cpu_data array.
- */
-static struct cpufreq_driver *cpufreq_driver;
-static DEFINE_PER_CPU(struct cpufreq_policy *, cpufreq_cpu_data);
-static DEFINE_RWLOCK(cpufreq_driver_lock);
-
-/* Flag to suspend/resume CPUFreq governors */
-static bool cpufreq_suspended;
-
-static inline bool has_target(void)
-{
- return cpufreq_driver->target_index || cpufreq_driver->target;
-}
-
-/* internal prototypes */
-static unsigned int __cpufreq_get(struct cpufreq_policy *policy);
-static int cpufreq_init_governor(struct cpufreq_policy *policy);
-static void cpufreq_exit_governor(struct cpufreq_policy *policy);
-static int cpufreq_start_governor(struct cpufreq_policy *policy);
-static void cpufreq_stop_governor(struct cpufreq_policy *policy);
-static void cpufreq_governor_limits(struct cpufreq_policy *policy);
-
-/**
- * Two notifier lists: the "policy" list is involved in the
- * validation process for a new CPU frequency policy; the
- * "transition" list for kernel code that needs to handle
- * changes to devices when the CPU clock speed changes.
- * The mutex locks both lists.
- */
-static BLOCKING_NOTIFIER_HEAD(cpufreq_policy_notifier_list);
-static struct srcu_notifier_head cpufreq_transition_notifier_list;
-
-static bool init_cpufreq_transition_notifier_list_called;
-static int __init init_cpufreq_transition_notifier_list(void)
-{
- srcu_init_notifier_head(&cpufreq_transition_notifier_list);
- init_cpufreq_transition_notifier_list_called = true;
- return 0;
-}
-pure_initcall(init_cpufreq_transition_notifier_list);
-
-static int off __read_mostly;
-static int cpufreq_disabled(void)
-{
- return off;
-}
-void disable_cpufreq(void)
-{
- off = 1;
-}
-static DEFINE_MUTEX(cpufreq_governor_mutex);
-
-bool have_governor_per_policy(void)
-{
- return !!(cpufreq_driver->flags & CPUFREQ_HAVE_GOVERNOR_PER_POLICY);
-}
-EXPORT_SYMBOL_GPL(have_governor_per_policy);
-
-struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy)
-{
- if (have_governor_per_policy())
- return &policy->kobj;
- else
- return cpufreq_global_kobject;
-}
-EXPORT_SYMBOL_GPL(get_governor_parent_kobj);
-
-static inline u64 get_cpu_idle_time_jiffy(unsigned int cpu, u64 *wall)
-{
- u64 idle_time;
- u64 cur_wall_time;
- u64 busy_time;
-
- cur_wall_time = jiffies64_to_nsecs(get_jiffies_64());
-
- busy_time = kcpustat_cpu(cpu).cpustat[CPUTIME_USER];
- busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_SYSTEM];
- busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_IRQ];
- busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_SOFTIRQ];
- busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_STEAL];
- busy_time += kcpustat_cpu(cpu).cpustat[CPUTIME_NICE];
-
- idle_time = cur_wall_time - busy_time;
- if (wall)
- *wall = div_u64(cur_wall_time, NSEC_PER_USEC);
-
- return div_u64(idle_time, NSEC_PER_USEC);
-}
-
-u64 get_cpu_idle_time(unsigned int cpu, u64 *wall, int io_busy)
-{
- u64 idle_time = get_cpu_idle_time_us(cpu, io_busy ? wall : NULL);
-
- if (idle_time == -1ULL)
- return get_cpu_idle_time_jiffy(cpu, wall);
- else if (!io_busy)
- idle_time += get_cpu_iowait_time_us(cpu, wall);
-
- return idle_time;
-}
-EXPORT_SYMBOL_GPL(get_cpu_idle_time);
-
-__weak void arch_set_freq_scale(struct cpumask *cpus, unsigned long cur_freq,
- unsigned long max_freq)
-{
-}
-EXPORT_SYMBOL_GPL(arch_set_freq_scale);
-
-/*
- * This is a generic cpufreq init() routine which can be used by cpufreq
- * drivers of SMP systems. It will do following:
- * - validate & show freq table passed
- * - set policies transition latency
- * - policy->cpus with all possible CPUs
- */
-int cpufreq_generic_init(struct cpufreq_policy *policy,
- struct cpufreq_frequency_table *table,
- unsigned int transition_latency)
-{
- int ret;
-
- ret = cpufreq_table_validate_and_show(policy, table);
- if (ret) {
- pr_err("%s: invalid frequency table: %d\n", __func__, ret);
- return ret;
- }
-
- policy->cpuinfo.transition_latency = transition_latency;
-
- /*
- * The driver only supports the SMP configuration where all processors
- * share the clock and voltage and clock.
- */
- cpumask_setall(policy->cpus);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(cpufreq_generic_init);
-
-struct cpufreq_policy *cpufreq_cpu_get_raw(unsigned int cpu)
-{
- struct cpufreq_policy *policy = per_cpu(cpufreq_cpu_data, cpu);
-
- return policy && cpumask_test_cpu(cpu, policy->cpus) ? policy : NULL;
-}
-EXPORT_SYMBOL_GPL(cpufreq_cpu_get_raw);
-
-unsigned int cpufreq_generic_get(unsigned int cpu)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get_raw(cpu);
-
- if (!policy || IS_ERR(policy->clk)) {
- pr_err("%s: No %s associated to cpu: %d\n",
- __func__, policy ? "clk" : "policy", cpu);
- return 0;
- }
-
- return clk_get_rate(policy->clk) / 1000;
-}
-EXPORT_SYMBOL_GPL(cpufreq_generic_get);
-
-/**
- * cpufreq_cpu_get: returns policy for a cpu and marks it busy.
- *
- * @cpu: cpu to find policy for.
- *
- * This returns policy for 'cpu', returns NULL if it doesn't exist.
- * It also increments the kobject reference count to mark it busy and so would
- * require a corresponding call to cpufreq_cpu_put() to decrement it back.
- * If corresponding call cpufreq_cpu_put() isn't made, the policy wouldn't be
- * freed as that depends on the kobj count.
- *
- * Return: A valid policy on success, otherwise NULL on failure.
- */
-struct cpufreq_policy *cpufreq_cpu_get(unsigned int cpu)
-{
- struct cpufreq_policy *policy = NULL;
- unsigned long flags;
-
- if (WARN_ON(cpu >= nr_cpu_ids))
- return NULL;
-
- /* get the cpufreq driver */
- read_lock_irqsave(&cpufreq_driver_lock, flags);
-
- if (cpufreq_driver) {
- /* get the CPU */
- policy = cpufreq_cpu_get_raw(cpu);
- if (policy)
- kobject_get(&policy->kobj);
- }
-
- read_unlock_irqrestore(&cpufreq_driver_lock, flags);
-
- return policy;
-}
-EXPORT_SYMBOL_GPL(cpufreq_cpu_get);
-
-/**
- * cpufreq_cpu_put: Decrements the usage count of a policy
- *
- * @policy: policy earlier returned by cpufreq_cpu_get().
- *
- * This decrements the kobject reference count incremented earlier by calling
- * cpufreq_cpu_get().
- */
-void cpufreq_cpu_put(struct cpufreq_policy *policy)
-{
- kobject_put(&policy->kobj);
-}
-EXPORT_SYMBOL_GPL(cpufreq_cpu_put);
-
-/*********************************************************************
- * EXTERNALLY AFFECTING FREQUENCY CHANGES *
- *********************************************************************/
-
-/**
- * adjust_jiffies - adjust the system "loops_per_jiffy"
- *
- * This function alters the system "loops_per_jiffy" for the clock
- * speed change. Note that loops_per_jiffy cannot be updated on SMP
- * systems as each CPU might be scaled differently. So, use the arch
- * per-CPU loops_per_jiffy value wherever possible.
- */
-static void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci)
-{
-#ifndef CONFIG_SMP
- static unsigned long l_p_j_ref;
- static unsigned int l_p_j_ref_freq;
-
- if (ci->flags & CPUFREQ_CONST_LOOPS)
- return;
-
- if (!l_p_j_ref_freq) {
- l_p_j_ref = loops_per_jiffy;
- l_p_j_ref_freq = ci->old;
- pr_debug("saving %lu as reference value for loops_per_jiffy; freq is %u kHz\n",
- l_p_j_ref, l_p_j_ref_freq);
- }
- if (val == CPUFREQ_POSTCHANGE && ci->old != ci->new) {
- loops_per_jiffy = cpufreq_scale(l_p_j_ref, l_p_j_ref_freq,
- ci->new);
- pr_debug("scaling loops_per_jiffy to %lu for frequency %u kHz\n",
- loops_per_jiffy, ci->new);
- }
-#endif
-}
-
-static void __cpufreq_notify_transition(struct cpufreq_policy *policy,
- struct cpufreq_freqs *freqs, unsigned int state)
-{
- BUG_ON(irqs_disabled());
-
- if (cpufreq_disabled())
- return;
-
- freqs->flags = cpufreq_driver->flags;
- pr_debug("notification %u of frequency transition to %u kHz\n",
- state, freqs->new);
-
- switch (state) {
-
- case CPUFREQ_PRECHANGE:
- /* detect if the driver reported a value as "old frequency"
- * which is not equal to what the cpufreq core thinks is
- * "old frequency".
- */
- if (!(cpufreq_driver->flags & CPUFREQ_CONST_LOOPS)) {
- if ((policy) && (policy->cpu == freqs->cpu) &&
- (policy->cur) && (policy->cur != freqs->old)) {
- pr_debug("Warning: CPU frequency is %u, cpufreq assumed %u kHz\n",
- freqs->old, policy->cur);
- freqs->old = policy->cur;
- }
- }
- srcu_notifier_call_chain(&cpufreq_transition_notifier_list,
- CPUFREQ_PRECHANGE, freqs);
- adjust_jiffies(CPUFREQ_PRECHANGE, freqs);
- break;
-
- case CPUFREQ_POSTCHANGE:
- adjust_jiffies(CPUFREQ_POSTCHANGE, freqs);
- pr_debug("FREQ: %lu - CPU: %lu\n",
- (unsigned long)freqs->new, (unsigned long)freqs->cpu);
- trace_cpu_frequency(freqs->new, freqs->cpu);
- cpufreq_stats_record_transition(policy, freqs->new);
- srcu_notifier_call_chain(&cpufreq_transition_notifier_list,
- CPUFREQ_POSTCHANGE, freqs);
- if (likely(policy) && likely(policy->cpu == freqs->cpu))
- policy->cur = freqs->new;
- break;
- }
-}
-
-/**
- * cpufreq_notify_transition - call notifier chain and adjust_jiffies
- * on frequency transition.
- *
- * This function calls the transition notifiers and the "adjust_jiffies"
- * function. It is called twice on all CPU frequency changes that have
- * external effects.
- */
-static void cpufreq_notify_transition(struct cpufreq_policy *policy,
- struct cpufreq_freqs *freqs, unsigned int state)
-{
- for_each_cpu(freqs->cpu, policy->cpus)
- __cpufreq_notify_transition(policy, freqs, state);
-}
-
-/* Do post notifications when there are chances that transition has failed */
-static void cpufreq_notify_post_transition(struct cpufreq_policy *policy,
- struct cpufreq_freqs *freqs, int transition_failed)
-{
- cpufreq_notify_transition(policy, freqs, CPUFREQ_POSTCHANGE);
- if (!transition_failed)
- return;
-
- swap(freqs->old, freqs->new);
- cpufreq_notify_transition(policy, freqs, CPUFREQ_PRECHANGE);
- cpufreq_notify_transition(policy, freqs, CPUFREQ_POSTCHANGE);
-}
-
-void cpufreq_freq_transition_begin(struct cpufreq_policy *policy,
- struct cpufreq_freqs *freqs)
-{
-
- /*
- * Catch double invocations of _begin() which lead to self-deadlock.
- * ASYNC_NOTIFICATION drivers are left out because the cpufreq core
- * doesn't invoke _begin() on their behalf, and hence the chances of
- * double invocations are very low. Moreover, there are scenarios
- * where these checks can emit false-positive warnings in these
- * drivers; so we avoid that by skipping them altogether.
- */
- WARN_ON(!(cpufreq_driver->flags & CPUFREQ_ASYNC_NOTIFICATION)
- && current == policy->transition_task);
-
-wait:
- wait_event(policy->transition_wait, !policy->transition_ongoing);
-
- spin_lock(&policy->transition_lock);
-
- if (unlikely(policy->transition_ongoing)) {
- spin_unlock(&policy->transition_lock);
- goto wait;
- }
-
- policy->transition_ongoing = true;
- policy->transition_task = current;
-
- spin_unlock(&policy->transition_lock);
-
- cpufreq_notify_transition(policy, freqs, CPUFREQ_PRECHANGE);
-}
-EXPORT_SYMBOL_GPL(cpufreq_freq_transition_begin);
-
-void cpufreq_freq_transition_end(struct cpufreq_policy *policy,
- struct cpufreq_freqs *freqs, int transition_failed)
-{
- if (unlikely(WARN_ON(!policy->transition_ongoing)))
- return;
-
- cpufreq_notify_post_transition(policy, freqs, transition_failed);
-
- policy->transition_ongoing = false;
- policy->transition_task = NULL;
-
- wake_up(&policy->transition_wait);
-}
-EXPORT_SYMBOL_GPL(cpufreq_freq_transition_end);
-
-/*
- * Fast frequency switching status count. Positive means "enabled", negative
- * means "disabled" and 0 means "not decided yet".
- */
-static int cpufreq_fast_switch_count;
-static DEFINE_MUTEX(cpufreq_fast_switch_lock);
-
-static void cpufreq_list_transition_notifiers(void)
-{
- struct notifier_block *nb;
-
- pr_info("Registered transition notifiers:\n");
-
- mutex_lock(&cpufreq_transition_notifier_list.mutex);
-
- for (nb = cpufreq_transition_notifier_list.head; nb; nb = nb->next)
- pr_info("%pF\n", nb->notifier_call);
-
- mutex_unlock(&cpufreq_transition_notifier_list.mutex);
-}
-
-/**
- * cpufreq_enable_fast_switch - Enable fast frequency switching for policy.
- * @policy: cpufreq policy to enable fast frequency switching for.
- *
- * Try to enable fast frequency switching for @policy.
- *
- * The attempt will fail if there is at least one transition notifier registered
- * at this point, as fast frequency switching is quite fundamentally at odds
- * with transition notifiers. Thus if successful, it will make registration of
- * transition notifiers fail going forward.
- */
-void cpufreq_enable_fast_switch(struct cpufreq_policy *policy)
-{
- lockdep_assert_held(&policy->rwsem);
-
- if (!policy->fast_switch_possible)
- return;
-
- mutex_lock(&cpufreq_fast_switch_lock);
- if (cpufreq_fast_switch_count >= 0) {
- cpufreq_fast_switch_count++;
- policy->fast_switch_enabled = true;
- } else {
- pr_warn("CPU%u: Fast frequency switching not enabled\n",
- policy->cpu);
- cpufreq_list_transition_notifiers();
- }
- mutex_unlock(&cpufreq_fast_switch_lock);
-}
-EXPORT_SYMBOL_GPL(cpufreq_enable_fast_switch);
-
-/**
- * cpufreq_disable_fast_switch - Disable fast frequency switching for policy.
- * @policy: cpufreq policy to disable fast frequency switching for.
- */
-void cpufreq_disable_fast_switch(struct cpufreq_policy *policy)
-{
- mutex_lock(&cpufreq_fast_switch_lock);
- if (policy->fast_switch_enabled) {
- policy->fast_switch_enabled = false;
- if (!WARN_ON(cpufreq_fast_switch_count <= 0))
- cpufreq_fast_switch_count--;
- }
- mutex_unlock(&cpufreq_fast_switch_lock);
-}
-EXPORT_SYMBOL_GPL(cpufreq_disable_fast_switch);
-
-/**
- * cpufreq_driver_resolve_freq - Map a target frequency to a driver-supported
- * one.
- * @target_freq: target frequency to resolve.
- *
- * The target to driver frequency mapping is cached in the policy.
- *
- * Return: Lowest driver-supported frequency greater than or equal to the
- * given target_freq, subject to policy (min/max) and driver limitations.
- */
-unsigned int cpufreq_driver_resolve_freq(struct cpufreq_policy *policy,
- unsigned int target_freq)
-{
- target_freq = clamp_val(target_freq, policy->min, policy->max);
- policy->cached_target_freq = target_freq;
-
- if (cpufreq_driver->target_index) {
- int idx;
-
- idx = cpufreq_frequency_table_target(policy, target_freq,
- CPUFREQ_RELATION_L);
- policy->cached_resolved_idx = idx;
- return policy->freq_table[idx].frequency;
- }
-
- if (cpufreq_driver->resolve_freq)
- return cpufreq_driver->resolve_freq(policy, target_freq);
-
- return target_freq;
-}
-EXPORT_SYMBOL_GPL(cpufreq_driver_resolve_freq);
-
-unsigned int cpufreq_policy_transition_delay_us(struct cpufreq_policy *policy)
-{
- unsigned int latency;
-
- if (policy->transition_delay_us)
- return policy->transition_delay_us;
-
- latency = policy->cpuinfo.transition_latency / NSEC_PER_USEC;
- if (latency) {
- /*
- * For platforms that can change the frequency very fast (< 10
- * us), the above formula gives a decent transition delay. But
- * for platforms where transition_latency is in milliseconds, it
- * ends up giving unrealistic values.
- *
- * Cap the default transition delay to 10 ms, which seems to be
- * a reasonable amount of time after which we should reevaluate
- * the frequency.
- */
- return min(latency * LATENCY_MULTIPLIER, (unsigned int)10000);
- }
-
- return LATENCY_MULTIPLIER;
-}
-EXPORT_SYMBOL_GPL(cpufreq_policy_transition_delay_us);
-
-/*********************************************************************
- * SYSFS INTERFACE *
- *********************************************************************/
-static ssize_t show_boost(struct kobject *kobj,
- struct attribute *attr, char *buf)
-{
- return sprintf(buf, "%d\n", cpufreq_driver->boost_enabled);
-}
-
-static ssize_t store_boost(struct kobject *kobj, struct attribute *attr,
- const char *buf, size_t count)
-{
- int ret, enable;
-
- ret = sscanf(buf, "%d", &enable);
- if (ret != 1 || enable < 0 || enable > 1)
- return -EINVAL;
-
- if (cpufreq_boost_trigger_state(enable)) {
- pr_err("%s: Cannot %s BOOST!\n",
- __func__, enable ? "enable" : "disable");
- return -EINVAL;
- }
-
- pr_debug("%s: cpufreq BOOST %s\n",
- __func__, enable ? "enabled" : "disabled");
-
- return count;
-}
-define_one_global_rw(boost);
-
-static struct cpufreq_governor *find_governor(const char *str_governor)
-{
- struct cpufreq_governor *t;
-
- for_each_governor(t)
- if (!strncasecmp(str_governor, t->name, CPUFREQ_NAME_LEN))
- return t;
-
- return NULL;
-}
-
-/**
- * cpufreq_parse_governor - parse a governor string
- */
-static int cpufreq_parse_governor(char *str_governor,
- struct cpufreq_policy *policy)
-{
- if (cpufreq_driver->setpolicy) {
- if (!strncasecmp(str_governor, "performance", CPUFREQ_NAME_LEN)) {
- policy->policy = CPUFREQ_POLICY_PERFORMANCE;
- return 0;
- }
-
- if (!strncasecmp(str_governor, "powersave", CPUFREQ_NAME_LEN)) {
- policy->policy = CPUFREQ_POLICY_POWERSAVE;
- return 0;
- }
- } else {
- struct cpufreq_governor *t;
-
- mutex_lock(&cpufreq_governor_mutex);
-
- t = find_governor(str_governor);
- if (!t) {
- int ret;
-
- mutex_unlock(&cpufreq_governor_mutex);
-
- ret = request_module("cpufreq_%s", str_governor);
- if (ret)
- return -EINVAL;
-
- mutex_lock(&cpufreq_governor_mutex);
-
- t = find_governor(str_governor);
- }
- if (t && !try_module_get(t->owner))
- t = NULL;
-
- mutex_unlock(&cpufreq_governor_mutex);
-
- if (t) {
- policy->governor = t;
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-/**
- * cpufreq_per_cpu_attr_read() / show_##file_name() -
- * print out cpufreq information
- *
- * Write out information from cpufreq_driver->policy[cpu]; object must be
- * "unsigned int".
- */
-
-#define show_one(file_name, object) \
-static ssize_t show_##file_name \
-(struct cpufreq_policy *policy, char *buf) \
-{ \
- return sprintf(buf, "%u\n", policy->object); \
-}
-
-show_one(cpuinfo_min_freq, cpuinfo.min_freq);
-show_one(cpuinfo_max_freq, cpuinfo.max_freq);
-show_one(cpuinfo_transition_latency, cpuinfo.transition_latency);
-show_one(scaling_min_freq, min);
-show_one(scaling_max_freq, max);
-
-__weak unsigned int arch_freq_get_on_cpu(int cpu)
-{
- return 0;
-}
-
-static ssize_t show_scaling_cur_freq(struct cpufreq_policy *policy, char *buf)
-{
- ssize_t ret;
- unsigned int freq;
-
- freq = arch_freq_get_on_cpu(policy->cpu);
- if (freq)
- ret = sprintf(buf, "%u\n", freq);
- else if (cpufreq_driver && cpufreq_driver->setpolicy &&
- cpufreq_driver->get)
- ret = sprintf(buf, "%u\n", cpufreq_driver->get(policy->cpu));
- else
- ret = sprintf(buf, "%u\n", policy->cur);
- return ret;
-}
-
-static int cpufreq_set_policy(struct cpufreq_policy *policy,
- struct cpufreq_policy *new_policy);
-
-/**
- * cpufreq_per_cpu_attr_write() / store_##file_name() - sysfs write access
- */
-#define store_one(file_name, object) \
-static ssize_t store_##file_name \
-(struct cpufreq_policy *policy, const char *buf, size_t count) \
-{ \
- int ret, temp; \
- struct cpufreq_policy new_policy; \
- \
- memcpy(&new_policy, policy, sizeof(*policy)); \
- \
- ret = sscanf(buf, "%u", &new_policy.object); \
- if (ret != 1) \
- return -EINVAL; \
- \
- temp = new_policy.object; \
- ret = cpufreq_set_policy(policy, &new_policy); \
- if (!ret) \
- policy->user_policy.object = temp; \
- \
- return ret ? ret : count; \
-}
-
-store_one(scaling_min_freq, min);
-store_one(scaling_max_freq, max);
-
-/**
- * show_cpuinfo_cur_freq - current CPU frequency as detected by hardware
- */
-static ssize_t show_cpuinfo_cur_freq(struct cpufreq_policy *policy,
- char *buf)
-{
- unsigned int cur_freq = __cpufreq_get(policy);
-
- if (cur_freq)
- return sprintf(buf, "%u\n", cur_freq);
-
- return sprintf(buf, "<unknown>\n");
-}
-
-/**
- * show_scaling_governor - show the current policy for the specified CPU
- */
-static ssize_t show_scaling_governor(struct cpufreq_policy *policy, char *buf)
-{
- if (policy->policy == CPUFREQ_POLICY_POWERSAVE)
- return sprintf(buf, "powersave\n");
- else if (policy->policy == CPUFREQ_POLICY_PERFORMANCE)
- return sprintf(buf, "performance\n");
- else if (policy->governor)
- return scnprintf(buf, CPUFREQ_NAME_PLEN, "%s\n",
- policy->governor->name);
- return -EINVAL;
-}
-
-/**
- * store_scaling_governor - store policy for the specified CPU
- */
-static ssize_t store_scaling_governor(struct cpufreq_policy *policy,
- const char *buf, size_t count)
-{
- int ret;
- char str_governor[16];
- struct cpufreq_policy new_policy;
-
- memcpy(&new_policy, policy, sizeof(*policy));
-
- ret = sscanf(buf, "%15s", str_governor);
- if (ret != 1)
- return -EINVAL;
-
- if (cpufreq_parse_governor(str_governor, &new_policy))
- return -EINVAL;
-
- ret = cpufreq_set_policy(policy, &new_policy);
-
- if (new_policy.governor)
- module_put(new_policy.governor->owner);
-
- return ret ? ret : count;
-}
-
-/**
- * show_scaling_driver - show the cpufreq driver currently loaded
- */
-static ssize_t show_scaling_driver(struct cpufreq_policy *policy, char *buf)
-{
- return scnprintf(buf, CPUFREQ_NAME_PLEN, "%s\n", cpufreq_driver->name);
-}
-
-/**
- * show_scaling_available_governors - show the available CPUfreq governors
- */
-static ssize_t show_scaling_available_governors(struct cpufreq_policy *policy,
- char *buf)
-{
- ssize_t i = 0;
- struct cpufreq_governor *t;
-
- if (!has_target()) {
- i += sprintf(buf, "performance powersave");
- goto out;
- }
-
- for_each_governor(t) {
- if (i >= (ssize_t) ((PAGE_SIZE / sizeof(char))
- - (CPUFREQ_NAME_LEN + 2)))
- goto out;
- i += scnprintf(&buf[i], CPUFREQ_NAME_PLEN, "%s ", t->name);
- }
-out:
- i += sprintf(&buf[i], "\n");
- return i;
-}
-
-ssize_t cpufreq_show_cpus(const struct cpumask *mask, char *buf)
-{
- ssize_t i = 0;
- unsigned int cpu;
-
- for_each_cpu(cpu, mask) {
- if (i)
- i += scnprintf(&buf[i], (PAGE_SIZE - i - 2), " ");
- i += scnprintf(&buf[i], (PAGE_SIZE - i - 2), "%u", cpu);
- if (i >= (PAGE_SIZE - 5))
- break;
- }
- i += sprintf(&buf[i], "\n");
- return i;
-}
-EXPORT_SYMBOL_GPL(cpufreq_show_cpus);
-
-/**
- * show_related_cpus - show the CPUs affected by each transition even if
- * hw coordination is in use
- */
-static ssize_t show_related_cpus(struct cpufreq_policy *policy, char *buf)
-{
- return cpufreq_show_cpus(policy->related_cpus, buf);
-}
-
-/**
- * show_affected_cpus - show the CPUs affected by each transition
- */
-static ssize_t show_affected_cpus(struct cpufreq_policy *policy, char *buf)
-{
- return cpufreq_show_cpus(policy->cpus, buf);
-}
-
-static ssize_t store_scaling_setspeed(struct cpufreq_policy *policy,
- const char *buf, size_t count)
-{
- unsigned int freq = 0;
- unsigned int ret;
-
- if (!policy->governor || !policy->governor->store_setspeed)
- return -EINVAL;
-
- ret = sscanf(buf, "%u", &freq);
- if (ret != 1)
- return -EINVAL;
-
- policy->governor->store_setspeed(policy, freq);
-
- return count;
-}
-
-static ssize_t show_scaling_setspeed(struct cpufreq_policy *policy, char *buf)
-{
- if (!policy->governor || !policy->governor->show_setspeed)
- return sprintf(buf, "<unsupported>\n");
-
- return policy->governor->show_setspeed(policy, buf);
-}
-
-/**
- * show_bios_limit - show the current cpufreq HW/BIOS limitation
- */
-static ssize_t show_bios_limit(struct cpufreq_policy *policy, char *buf)
-{
- unsigned int limit;
- int ret;
- if (cpufreq_driver->bios_limit) {
- ret = cpufreq_driver->bios_limit(policy->cpu, &limit);
- if (!ret)
- return sprintf(buf, "%u\n", limit);
- }
- return sprintf(buf, "%u\n", policy->cpuinfo.max_freq);
-}
-
-cpufreq_freq_attr_ro_perm(cpuinfo_cur_freq, 0400);
-cpufreq_freq_attr_ro(cpuinfo_min_freq);
-cpufreq_freq_attr_ro(cpuinfo_max_freq);
-cpufreq_freq_attr_ro(cpuinfo_transition_latency);
-cpufreq_freq_attr_ro(scaling_available_governors);
-cpufreq_freq_attr_ro(scaling_driver);
-cpufreq_freq_attr_ro(scaling_cur_freq);
-cpufreq_freq_attr_ro(bios_limit);
-cpufreq_freq_attr_ro(related_cpus);
-cpufreq_freq_attr_ro(affected_cpus);
-cpufreq_freq_attr_rw(scaling_min_freq);
-cpufreq_freq_attr_rw(scaling_max_freq);
-cpufreq_freq_attr_rw(scaling_governor);
-cpufreq_freq_attr_rw(scaling_setspeed);
-
-static struct attribute *default_attrs[] = {
- &cpuinfo_min_freq.attr,
- &cpuinfo_max_freq.attr,
- &cpuinfo_transition_latency.attr,
- &scaling_min_freq.attr,
- &scaling_max_freq.attr,
- &affected_cpus.attr,
- &related_cpus.attr,
- &scaling_governor.attr,
- &scaling_driver.attr,
- &scaling_available_governors.attr,
- &scaling_setspeed.attr,
- NULL
-};
-
-#define to_policy(k) container_of(k, struct cpufreq_policy, kobj)
-#define to_attr(a) container_of(a, struct freq_attr, attr)
-
-static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
-{
- struct cpufreq_policy *policy = to_policy(kobj);
- struct freq_attr *fattr = to_attr(attr);
- ssize_t ret;
-
- down_read(&policy->rwsem);
- ret = fattr->show(policy, buf);
- up_read(&policy->rwsem);
-
- return ret;
-}
-
-static ssize_t store(struct kobject *kobj, struct attribute *attr,
- const char *buf, size_t count)
-{
- struct cpufreq_policy *policy = to_policy(kobj);
- struct freq_attr *fattr = to_attr(attr);
- ssize_t ret = -EINVAL;
-
- cpus_read_lock();
-
- if (cpu_online(policy->cpu)) {
- down_write(&policy->rwsem);
- ret = fattr->store(policy, buf, count);
- up_write(&policy->rwsem);
- }
-
- cpus_read_unlock();
-
- return ret;
-}
-
-static void cpufreq_sysfs_release(struct kobject *kobj)
-{
- struct cpufreq_policy *policy = to_policy(kobj);
- pr_debug("last reference is dropped\n");
- complete(&policy->kobj_unregister);
-}
-
-static const struct sysfs_ops sysfs_ops = {
- .show = show,
- .store = store,
-};
-
-static struct kobj_type ktype_cpufreq = {
- .sysfs_ops = &sysfs_ops,
- .default_attrs = default_attrs,
- .release = cpufreq_sysfs_release,
-};
-
-static void add_cpu_dev_symlink(struct cpufreq_policy *policy, unsigned int cpu)
-{
- struct device *dev = get_cpu_device(cpu);
-
- if (!dev)
- return;
-
- if (cpumask_test_and_set_cpu(cpu, policy->real_cpus))
- return;
-
- dev_dbg(dev, "%s: Adding symlink\n", __func__);
- if (sysfs_create_link(&dev->kobj, &policy->kobj, "cpufreq"))
- dev_err(dev, "cpufreq symlink creation failed\n");
-}
-
-static void remove_cpu_dev_symlink(struct cpufreq_policy *policy,
- struct device *dev)
-{
- dev_dbg(dev, "%s: Removing symlink\n", __func__);
- sysfs_remove_link(&dev->kobj, "cpufreq");
-}
-
-static int cpufreq_add_dev_interface(struct cpufreq_policy *policy)
-{
- struct freq_attr **drv_attr;
- int ret = 0;
-
- /* set up files for this cpu device */
- drv_attr = cpufreq_driver->attr;
- while (drv_attr && *drv_attr) {
- ret = sysfs_create_file(&policy->kobj, &((*drv_attr)->attr));
- if (ret)
- return ret;
- drv_attr++;
- }
- if (cpufreq_driver->get) {
- ret = sysfs_create_file(&policy->kobj, &cpuinfo_cur_freq.attr);
- if (ret)
- return ret;
- }
-
- ret = sysfs_create_file(&policy->kobj, &scaling_cur_freq.attr);
- if (ret)
- return ret;
-
- if (cpufreq_driver->bios_limit) {
- ret = sysfs_create_file(&policy->kobj, &bios_limit.attr);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-__weak struct cpufreq_governor *cpufreq_default_governor(void)
-{
- return NULL;
-}
-
-static int cpufreq_init_policy(struct cpufreq_policy *policy)
-{
- struct cpufreq_governor *gov = NULL;
- struct cpufreq_policy new_policy;
-
- memcpy(&new_policy, policy, sizeof(*policy));
-
- /* Update governor of new_policy to the governor used before hotplug */
- gov = find_governor(policy->last_governor);
- if (gov) {
- pr_debug("Restoring governor %s for cpu %d\n",
- policy->governor->name, policy->cpu);
- } else {
- gov = cpufreq_default_governor();
- if (!gov)
- return -ENODATA;
- }
-
- new_policy.governor = gov;
-
- /* Use the default policy if there is no last_policy. */
- if (cpufreq_driver->setpolicy) {
- if (policy->last_policy)
- new_policy.policy = policy->last_policy;
- else
- cpufreq_parse_governor(gov->name, &new_policy);
- }
- /* set default policy */
- return cpufreq_set_policy(policy, &new_policy);
-}
-
-static int cpufreq_add_policy_cpu(struct cpufreq_policy *policy, unsigned int cpu)
-{
- int ret = 0;
-
- /* Has this CPU been taken care of already? */
- if (cpumask_test_cpu(cpu, policy->cpus))
- return 0;
-
- down_write(&policy->rwsem);
- if (has_target())
- cpufreq_stop_governor(policy);
-
- cpumask_set_cpu(cpu, policy->cpus);
-
- if (has_target()) {
- ret = cpufreq_start_governor(policy);
- if (ret)
- pr_err("%s: Failed to start governor\n", __func__);
- }
- up_write(&policy->rwsem);
- return ret;
-}
-
-static void handle_update(struct work_struct *work)
-{
- struct cpufreq_policy *policy =
- container_of(work, struct cpufreq_policy, update);
- unsigned int cpu = policy->cpu;
- pr_debug("handle_update for cpu %u called\n", cpu);
- cpufreq_update_policy(cpu);
-}
-
-static struct cpufreq_policy *cpufreq_policy_alloc(unsigned int cpu)
-{
- struct cpufreq_policy *policy;
- int ret;
-
- policy = kzalloc(sizeof(*policy), GFP_KERNEL);
- if (!policy)
- return NULL;
-
- if (!alloc_cpumask_var(&policy->cpus, GFP_KERNEL))
- goto err_free_policy;
-
- if (!zalloc_cpumask_var(&policy->related_cpus, GFP_KERNEL))
- goto err_free_cpumask;
-
- if (!zalloc_cpumask_var(&policy->real_cpus, GFP_KERNEL))
- goto err_free_rcpumask;
-
- ret = kobject_init_and_add(&policy->kobj, &ktype_cpufreq,
- cpufreq_global_kobject, "policy%u", cpu);
- if (ret) {
- pr_err("%s: failed to init policy->kobj: %d\n", __func__, ret);
- goto err_free_real_cpus;
- }
-
- INIT_LIST_HEAD(&policy->policy_list);
- init_rwsem(&policy->rwsem);
- spin_lock_init(&policy->transition_lock);
- init_waitqueue_head(&policy->transition_wait);
- init_completion(&policy->kobj_unregister);
- INIT_WORK(&policy->update, handle_update);
-
- policy->cpu = cpu;
- return policy;
-
-err_free_real_cpus:
- free_cpumask_var(policy->real_cpus);
-err_free_rcpumask:
- free_cpumask_var(policy->related_cpus);
-err_free_cpumask:
- free_cpumask_var(policy->cpus);
-err_free_policy:
- kfree(policy);
-
- return NULL;
-}
-
-static void cpufreq_policy_put_kobj(struct cpufreq_policy *policy)
-{
- struct kobject *kobj;
- struct completion *cmp;
-
- down_write(&policy->rwsem);
- cpufreq_stats_free_table(policy);
- kobj = &policy->kobj;
- cmp = &policy->kobj_unregister;
- up_write(&policy->rwsem);
- kobject_put(kobj);
-
- /*
- * We need to make sure that the underlying kobj is
- * actually not referenced anymore by anybody before we
- * proceed with unloading.
- */
- pr_debug("waiting for dropping of refcount\n");
- wait_for_completion(cmp);
- pr_debug("wait complete\n");
-}
-
-static void cpufreq_policy_free(struct cpufreq_policy *policy)
-{
- unsigned long flags;
- int cpu;
-
- /* Remove policy from list */
- write_lock_irqsave(&cpufreq_driver_lock, flags);
- list_del(&policy->policy_list);
-
- for_each_cpu(cpu, policy->related_cpus)
- per_cpu(cpufreq_cpu_data, cpu) = NULL;
- write_unlock_irqrestore(&cpufreq_driver_lock, flags);
-
- cpufreq_policy_put_kobj(policy);
- free_cpumask_var(policy->real_cpus);
- free_cpumask_var(policy->related_cpus);
- free_cpumask_var(policy->cpus);
- kfree(policy);
-}
-
-static int cpufreq_online(unsigned int cpu)
-{
- struct cpufreq_policy *policy;
- bool new_policy;
- unsigned long flags;
- unsigned int j;
- int ret;
-
- pr_debug("%s: bringing CPU%u online\n", __func__, cpu);
-
- /* Check if this CPU already has a policy to manage it */
- policy = per_cpu(cpufreq_cpu_data, cpu);
- if (policy) {
- WARN_ON(!cpumask_test_cpu(cpu, policy->related_cpus));
- if (!policy_is_inactive(policy))
- return cpufreq_add_policy_cpu(policy, cpu);
-
- /* This is the only online CPU for the policy. Start over. */
- new_policy = false;
- down_write(&policy->rwsem);
- policy->cpu = cpu;
- policy->governor = NULL;
- up_write(&policy->rwsem);
- } else {
- new_policy = true;
- policy = cpufreq_policy_alloc(cpu);
- if (!policy)
- return -ENOMEM;
- }
-
- cpumask_copy(policy->cpus, cpumask_of(cpu));
-
- /* call driver. From then on the cpufreq must be able
- * to accept all calls to ->verify and ->setpolicy for this CPU
- */
- ret = cpufreq_driver->init(policy);
- if (ret) {
- pr_debug("initialization failed\n");
- goto out_free_policy;
- }
-
- down_write(&policy->rwsem);
-
- if (new_policy) {
- /* related_cpus should at least include policy->cpus. */
- cpumask_copy(policy->related_cpus, policy->cpus);
- }
-
- /*
- * affected cpus must always be the one, which are online. We aren't
- * managing offline cpus here.
- */
- cpumask_and(policy->cpus, policy->cpus, cpu_online_mask);
-
- if (new_policy) {
- policy->user_policy.min = policy->min;
- policy->user_policy.max = policy->max;
-
- for_each_cpu(j, policy->related_cpus) {
- per_cpu(cpufreq_cpu_data, j) = policy;
- add_cpu_dev_symlink(policy, j);
- }
- } else {
- policy->min = policy->user_policy.min;
- policy->max = policy->user_policy.max;
- }
-
- if (cpufreq_driver->get && !cpufreq_driver->setpolicy) {
- policy->cur = cpufreq_driver->get(policy->cpu);
- if (!policy->cur) {
- pr_err("%s: ->get() failed\n", __func__);
- goto out_exit_policy;
- }
- }
-
- /*
- * Sometimes boot loaders set CPU frequency to a value outside of
- * frequency table present with cpufreq core. In such cases CPU might be
- * unstable if it has to run on that frequency for long duration of time
- * and so its better to set it to a frequency which is specified in
- * freq-table. This also makes cpufreq stats inconsistent as
- * cpufreq-stats would fail to register because current frequency of CPU
- * isn't found in freq-table.
- *
- * Because we don't want this change to effect boot process badly, we go
- * for the next freq which is >= policy->cur ('cur' must be set by now,
- * otherwise we will end up setting freq to lowest of the table as 'cur'
- * is initialized to zero).
- *
- * We are passing target-freq as "policy->cur - 1" otherwise
- * __cpufreq_driver_target() would simply fail, as policy->cur will be
- * equal to target-freq.
- */
- if ((cpufreq_driver->flags & CPUFREQ_NEED_INITIAL_FREQ_CHECK)
- && has_target()) {
- /* Are we running at unknown frequency ? */
- ret = cpufreq_frequency_table_get_index(policy, policy->cur);
- if (ret == -EINVAL) {
- /* Warn user and fix it */
- pr_warn("%s: CPU%d: Running at unlisted freq: %u KHz\n",
- __func__, policy->cpu, policy->cur);
- ret = __cpufreq_driver_target(policy, policy->cur - 1,
- CPUFREQ_RELATION_L);
-
- /*
- * Reaching here after boot in a few seconds may not
- * mean that system will remain stable at "unknown"
- * frequency for longer duration. Hence, a BUG_ON().
- */
- BUG_ON(ret);
- pr_warn("%s: CPU%d: Unlisted initial frequency changed to: %u KHz\n",
- __func__, policy->cpu, policy->cur);
- }
- }
-
- if (new_policy) {
- ret = cpufreq_add_dev_interface(policy);
- if (ret)
- goto out_exit_policy;
-
- cpufreq_stats_create_table(policy);
-
- write_lock_irqsave(&cpufreq_driver_lock, flags);
- list_add(&policy->policy_list, &cpufreq_policy_list);
- write_unlock_irqrestore(&cpufreq_driver_lock, flags);
- }
-
- ret = cpufreq_init_policy(policy);
- if (ret) {
- pr_err("%s: Failed to initialize policy for cpu: %d (%d)\n",
- __func__, cpu, ret);
- /* cpufreq_policy_free() will notify based on this */
- new_policy = false;
- goto out_exit_policy;
- }
-
- up_write(&policy->rwsem);
-
- kobject_uevent(&policy->kobj, KOBJ_ADD);
-
- /* Callback for handling stuff after policy is ready */
- if (cpufreq_driver->ready)
- cpufreq_driver->ready(policy);
-
- pr_debug("initialization complete\n");
-
- return 0;
-
-out_exit_policy:
- up_write(&policy->rwsem);
-
- if (cpufreq_driver->exit)
- cpufreq_driver->exit(policy);
-
- for_each_cpu(j, policy->real_cpus)
- remove_cpu_dev_symlink(policy, get_cpu_device(j));
-
-out_free_policy:
- cpufreq_policy_free(policy);
- return ret;
-}
-
-/**
- * cpufreq_add_dev - the cpufreq interface for a CPU device.
- * @dev: CPU device.
- * @sif: Subsystem interface structure pointer (not used)
- */
-static int cpufreq_add_dev(struct device *dev, struct subsys_interface *sif)
-{
- struct cpufreq_policy *policy;
- unsigned cpu = dev->id;
- int ret;
-
- dev_dbg(dev, "%s: adding CPU%u\n", __func__, cpu);
-
- if (cpu_online(cpu)) {
- ret = cpufreq_online(cpu);
- if (ret)
- return ret;
- }
-
- /* Create sysfs link on CPU registration */
- policy = per_cpu(cpufreq_cpu_data, cpu);
- if (policy)
- add_cpu_dev_symlink(policy, cpu);
-
- return 0;
-}
-
-static int cpufreq_offline(unsigned int cpu)
-{
- struct cpufreq_policy *policy;
- int ret;
-
- pr_debug("%s: unregistering CPU %u\n", __func__, cpu);
-
- policy = cpufreq_cpu_get_raw(cpu);
- if (!policy) {
- pr_debug("%s: No cpu_data found\n", __func__);
- return 0;
- }
-
- down_write(&policy->rwsem);
- if (has_target())
- cpufreq_stop_governor(policy);
-
- cpumask_clear_cpu(cpu, policy->cpus);
-
- if (policy_is_inactive(policy)) {
- if (has_target())
- strncpy(policy->last_governor, policy->governor->name,
- CPUFREQ_NAME_LEN);
- else
- policy->last_policy = policy->policy;
- } else if (cpu == policy->cpu) {
- /* Nominate new CPU */
- policy->cpu = cpumask_any(policy->cpus);
- }
-
- /* Start governor again for active policy */
- if (!policy_is_inactive(policy)) {
- if (has_target()) {
- ret = cpufreq_start_governor(policy);
- if (ret)
- pr_err("%s: Failed to start governor\n", __func__);
- }
-
- goto unlock;
- }
-
- if (cpufreq_driver->stop_cpu)
- cpufreq_driver->stop_cpu(policy);
-
- if (has_target())
- cpufreq_exit_governor(policy);
-
- /*
- * Perform the ->exit() even during light-weight tear-down,
- * since this is a core component, and is essential for the
- * subsequent light-weight ->init() to succeed.
- */
- if (cpufreq_driver->exit) {
- cpufreq_driver->exit(policy);
- policy->freq_table = NULL;
- }
-
-unlock:
- up_write(&policy->rwsem);
- return 0;
-}
-
-/**
- * cpufreq_remove_dev - remove a CPU device
- *
- * Removes the cpufreq interface for a CPU device.
- */
-static void cpufreq_remove_dev(struct device *dev, struct subsys_interface *sif)
-{
- unsigned int cpu = dev->id;
- struct cpufreq_policy *policy = per_cpu(cpufreq_cpu_data, cpu);
-
- if (!policy)
- return;
-
- if (cpu_online(cpu))
- cpufreq_offline(cpu);
-
- cpumask_clear_cpu(cpu, policy->real_cpus);
- remove_cpu_dev_symlink(policy, dev);
-
- if (cpumask_empty(policy->real_cpus))
- cpufreq_policy_free(policy);
-}
-
-/**
- * cpufreq_out_of_sync - If actual and saved CPU frequency differs, we're
- * in deep trouble.
- * @policy: policy managing CPUs
- * @new_freq: CPU frequency the CPU actually runs at
- *
- * We adjust to current frequency first, and need to clean up later.
- * So either call to cpufreq_update_policy() or schedule handle_update()).
- */
-static void cpufreq_out_of_sync(struct cpufreq_policy *policy,
- unsigned int new_freq)
-{
- struct cpufreq_freqs freqs;
-
- pr_debug("Warning: CPU frequency out of sync: cpufreq and timing core thinks of %u, is %u kHz\n",
- policy->cur, new_freq);
-
- freqs.old = policy->cur;
- freqs.new = new_freq;
-
- cpufreq_freq_transition_begin(policy, &freqs);
- cpufreq_freq_transition_end(policy, &freqs, 0);
-}
-
-/**
- * cpufreq_quick_get - get the CPU frequency (in kHz) from policy->cur
- * @cpu: CPU number
- *
- * This is the last known freq, without actually getting it from the driver.
- * Return value will be same as what is shown in scaling_cur_freq in sysfs.
- */
-unsigned int cpufreq_quick_get(unsigned int cpu)
-{
- struct cpufreq_policy *policy;
- unsigned int ret_freq = 0;
- unsigned long flags;
-
- read_lock_irqsave(&cpufreq_driver_lock, flags);
-
- if (cpufreq_driver && cpufreq_driver->setpolicy && cpufreq_driver->get) {
- ret_freq = cpufreq_driver->get(cpu);
- read_unlock_irqrestore(&cpufreq_driver_lock, flags);
- return ret_freq;
- }
-
- read_unlock_irqrestore(&cpufreq_driver_lock, flags);
-
- policy = cpufreq_cpu_get(cpu);
- if (policy) {
- ret_freq = policy->cur;
- cpufreq_cpu_put(policy);
- }
-
- return ret_freq;
-}
-EXPORT_SYMBOL(cpufreq_quick_get);
-
-/**
- * cpufreq_quick_get_max - get the max reported CPU frequency for this CPU
- * @cpu: CPU number
- *
- * Just return the max possible frequency for a given CPU.
- */
-unsigned int cpufreq_quick_get_max(unsigned int cpu)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
- unsigned int ret_freq = 0;
-
- if (policy) {
- ret_freq = policy->max;
- cpufreq_cpu_put(policy);
- }
-
- return ret_freq;
-}
-EXPORT_SYMBOL(cpufreq_quick_get_max);
-
-static unsigned int __cpufreq_get(struct cpufreq_policy *policy)
-{
- unsigned int ret_freq = 0;
-
- if (!cpufreq_driver->get)
- return ret_freq;
-
- ret_freq = cpufreq_driver->get(policy->cpu);
-
- /*
- * Updating inactive policies is invalid, so avoid doing that. Also
- * if fast frequency switching is used with the given policy, the check
- * against policy->cur is pointless, so skip it in that case too.
- */
- if (unlikely(policy_is_inactive(policy)) || policy->fast_switch_enabled)
- return ret_freq;
-
- if (ret_freq && policy->cur &&
- !(cpufreq_driver->flags & CPUFREQ_CONST_LOOPS)) {
- /* verify no discrepancy between actual and
- saved value exists */
- if (unlikely(ret_freq != policy->cur)) {
- cpufreq_out_of_sync(policy, ret_freq);
- schedule_work(&policy->update);
- }
- }
-
- return ret_freq;
-}
-
-/**
- * cpufreq_get - get the current CPU frequency (in kHz)
- * @cpu: CPU number
- *
- * Get the CPU current (static) CPU frequency
- */
-unsigned int cpufreq_get(unsigned int cpu)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
- unsigned int ret_freq = 0;
-
- if (policy) {
- down_read(&policy->rwsem);
-
- if (!policy_is_inactive(policy))
- ret_freq = __cpufreq_get(policy);
-
- up_read(&policy->rwsem);
-
- cpufreq_cpu_put(policy);
- }
-
- return ret_freq;
-}
-EXPORT_SYMBOL(cpufreq_get);
-
-static unsigned int cpufreq_update_current_freq(struct cpufreq_policy *policy)
-{
- unsigned int new_freq;
-
- new_freq = cpufreq_driver->get(policy->cpu);
- if (!new_freq)
- return 0;
-
- if (!policy->cur) {
- pr_debug("cpufreq: Driver did not initialize current freq\n");
- policy->cur = new_freq;
- } else if (policy->cur != new_freq && has_target()) {
- cpufreq_out_of_sync(policy, new_freq);
- }
-
- return new_freq;
-}
-
-static struct subsys_interface cpufreq_interface = {
- .name = "cpufreq",
- .subsys = &cpu_subsys,
- .add_dev = cpufreq_add_dev,
- .remove_dev = cpufreq_remove_dev,
-};
-
-/*
- * In case platform wants some specific frequency to be configured
- * during suspend..
- */
-int cpufreq_generic_suspend(struct cpufreq_policy *policy)
-{
- int ret;
-
- if (!policy->suspend_freq) {
- pr_debug("%s: suspend_freq not defined\n", __func__);
- return 0;
- }
-
- pr_debug("%s: Setting suspend-freq: %u\n", __func__,
- policy->suspend_freq);
-
- ret = __cpufreq_driver_target(policy, policy->suspend_freq,
- CPUFREQ_RELATION_H);
- if (ret)
- pr_err("%s: unable to set suspend-freq: %u. err: %d\n",
- __func__, policy->suspend_freq, ret);
-
- return ret;
-}
-EXPORT_SYMBOL(cpufreq_generic_suspend);
-
-/**
- * cpufreq_suspend() - Suspend CPUFreq governors
- *
- * Called during system wide Suspend/Hibernate cycles for suspending governors
- * as some platforms can't change frequency after this point in suspend cycle.
- * Because some of the devices (like: i2c, regulators, etc) they use for
- * changing frequency are suspended quickly after this point.
- */
-void cpufreq_suspend(void)
-{
- struct cpufreq_policy *policy;
-
- if (!cpufreq_driver)
- return;
-
- if (!has_target() && !cpufreq_driver->suspend)
- goto suspend;
-
- pr_debug("%s: Suspending Governors\n", __func__);
-
- for_each_active_policy(policy) {
- if (has_target()) {
- down_write(&policy->rwsem);
- cpufreq_stop_governor(policy);
- up_write(&policy->rwsem);
- }
-
- if (cpufreq_driver->suspend && cpufreq_driver->suspend(policy))
- pr_err("%s: Failed to suspend driver: %p\n", __func__,
- policy);
- }
-
-suspend:
- cpufreq_suspended = true;
-}
-
-/**
- * cpufreq_resume() - Resume CPUFreq governors
- *
- * Called during system wide Suspend/Hibernate cycle for resuming governors that
- * are suspended with cpufreq_suspend().
- */
-void cpufreq_resume(void)
-{
- struct cpufreq_policy *policy;
- int ret;
-
- if (!cpufreq_driver)
- return;
-
- if (unlikely(!cpufreq_suspended))
- return;
-
- cpufreq_suspended = false;
-
- if (!has_target() && !cpufreq_driver->resume)
- return;
-
- pr_debug("%s: Resuming Governors\n", __func__);
-
- for_each_active_policy(policy) {
- if (cpufreq_driver->resume && cpufreq_driver->resume(policy)) {
- pr_err("%s: Failed to resume driver: %p\n", __func__,
- policy);
- } else if (has_target()) {
- down_write(&policy->rwsem);
- ret = cpufreq_start_governor(policy);
- up_write(&policy->rwsem);
-
- if (ret)
- pr_err("%s: Failed to start governor for policy: %p\n",
- __func__, policy);
- }
- }
-}
-
-/**
- * cpufreq_get_current_driver - return current driver's name
- *
- * Return the name string of the currently loaded cpufreq driver
- * or NULL, if none.
- */
-const char *cpufreq_get_current_driver(void)
-{
- if (cpufreq_driver)
- return cpufreq_driver->name;
-
- return NULL;
-}
-EXPORT_SYMBOL_GPL(cpufreq_get_current_driver);
-
-/**
- * cpufreq_get_driver_data - return current driver data
- *
- * Return the private data of the currently loaded cpufreq
- * driver, or NULL if no cpufreq driver is loaded.
- */
-void *cpufreq_get_driver_data(void)
-{
- if (cpufreq_driver)
- return cpufreq_driver->driver_data;
-
- return NULL;
-}
-EXPORT_SYMBOL_GPL(cpufreq_get_driver_data);
-
-/*********************************************************************
- * NOTIFIER LISTS INTERFACE *
- *********************************************************************/
-
-/**
- * cpufreq_register_notifier - register a driver with cpufreq
- * @nb: notifier function to register
- * @list: CPUFREQ_TRANSITION_NOTIFIER or CPUFREQ_POLICY_NOTIFIER
- *
- * Add a driver to one of two lists: either a list of drivers that
- * are notified about clock rate changes (once before and once after
- * the transition), or a list of drivers that are notified about
- * changes in cpufreq policy.
- *
- * This function may sleep, and has the same return conditions as
- * blocking_notifier_chain_register.
- */
-int cpufreq_register_notifier(struct notifier_block *nb, unsigned int list)
-{
- int ret;
-
- if (cpufreq_disabled())
- return -EINVAL;
-
- WARN_ON(!init_cpufreq_transition_notifier_list_called);
-
- switch (list) {
- case CPUFREQ_TRANSITION_NOTIFIER:
- mutex_lock(&cpufreq_fast_switch_lock);
-
- if (cpufreq_fast_switch_count > 0) {
- mutex_unlock(&cpufreq_fast_switch_lock);
- return -EBUSY;
- }
- ret = srcu_notifier_chain_register(
- &cpufreq_transition_notifier_list, nb);
- if (!ret)
- cpufreq_fast_switch_count--;
-
- mutex_unlock(&cpufreq_fast_switch_lock);
- break;
- case CPUFREQ_POLICY_NOTIFIER:
- ret = blocking_notifier_chain_register(
- &cpufreq_policy_notifier_list, nb);
- break;
- default:
- ret = -EINVAL;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(cpufreq_register_notifier);
-
-/**
- * cpufreq_unregister_notifier - unregister a driver with cpufreq
- * @nb: notifier block to be unregistered
- * @list: CPUFREQ_TRANSITION_NOTIFIER or CPUFREQ_POLICY_NOTIFIER
- *
- * Remove a driver from the CPU frequency notifier list.
- *
- * This function may sleep, and has the same return conditions as
- * blocking_notifier_chain_unregister.
- */
-int cpufreq_unregister_notifier(struct notifier_block *nb, unsigned int list)
-{
- int ret;
-
- if (cpufreq_disabled())
- return -EINVAL;
-
- switch (list) {
- case CPUFREQ_TRANSITION_NOTIFIER:
- mutex_lock(&cpufreq_fast_switch_lock);
-
- ret = srcu_notifier_chain_unregister(
- &cpufreq_transition_notifier_list, nb);
- if (!ret && !WARN_ON(cpufreq_fast_switch_count >= 0))
- cpufreq_fast_switch_count++;
-
- mutex_unlock(&cpufreq_fast_switch_lock);
- break;
- case CPUFREQ_POLICY_NOTIFIER:
- ret = blocking_notifier_chain_unregister(
- &cpufreq_policy_notifier_list, nb);
- break;
- default:
- ret = -EINVAL;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(cpufreq_unregister_notifier);
-
-
-/*********************************************************************
- * GOVERNORS *
- *********************************************************************/
-
-/**
- * cpufreq_driver_fast_switch - Carry out a fast CPU frequency switch.
- * @policy: cpufreq policy to switch the frequency for.
- * @target_freq: New frequency to set (may be approximate).
- *
- * Carry out a fast frequency switch without sleeping.
- *
- * The driver's ->fast_switch() callback invoked by this function must be
- * suitable for being called from within RCU-sched read-side critical sections
- * and it is expected to select the minimum available frequency greater than or
- * equal to @target_freq (CPUFREQ_RELATION_L).
- *
- * This function must not be called if policy->fast_switch_enabled is unset.
- *
- * Governors calling this function must guarantee that it will never be invoked
- * twice in parallel for the same policy and that it will never be called in
- * parallel with either ->target() or ->target_index() for the same policy.
- *
- * Returns the actual frequency set for the CPU.
- *
- * If 0 is returned by the driver's ->fast_switch() callback to indicate an
- * error condition, the hardware configuration must be preserved.
- */
-unsigned int cpufreq_driver_fast_switch(struct cpufreq_policy *policy,
- unsigned int target_freq)
-{
- target_freq = clamp_val(target_freq, policy->min, policy->max);
-
- return cpufreq_driver->fast_switch(policy, target_freq);
-}
-EXPORT_SYMBOL_GPL(cpufreq_driver_fast_switch);
-
-/* Must set freqs->new to intermediate frequency */
-static int __target_intermediate(struct cpufreq_policy *policy,
- struct cpufreq_freqs *freqs, int index)
-{
- int ret;
-
- freqs->new = cpufreq_driver->get_intermediate(policy, index);
-
- /* We don't need to switch to intermediate freq */
- if (!freqs->new)
- return 0;
-
- pr_debug("%s: cpu: %d, switching to intermediate freq: oldfreq: %u, intermediate freq: %u\n",
- __func__, policy->cpu, freqs->old, freqs->new);
-
- cpufreq_freq_transition_begin(policy, freqs);
- ret = cpufreq_driver->target_intermediate(policy, index);
- cpufreq_freq_transition_end(policy, freqs, ret);
-
- if (ret)
- pr_err("%s: Failed to change to intermediate frequency: %d\n",
- __func__, ret);
-
- return ret;
-}
-
-static int __target_index(struct cpufreq_policy *policy, int index)
-{
- struct cpufreq_freqs freqs = {.old = policy->cur, .flags = 0};
- unsigned int intermediate_freq = 0;
- unsigned int newfreq = policy->freq_table[index].frequency;
- int retval = -EINVAL;
- bool notify;
-
- if (newfreq == policy->cur)
- return 0;
-
- notify = !(cpufreq_driver->flags & CPUFREQ_ASYNC_NOTIFICATION);
- if (notify) {
- /* Handle switching to intermediate frequency */
- if (cpufreq_driver->get_intermediate) {
- retval = __target_intermediate(policy, &freqs, index);
- if (retval)
- return retval;
-
- intermediate_freq = freqs.new;
- /* Set old freq to intermediate */
- if (intermediate_freq)
- freqs.old = freqs.new;
- }
-
- freqs.new = newfreq;
- pr_debug("%s: cpu: %d, oldfreq: %u, new freq: %u\n",
- __func__, policy->cpu, freqs.old, freqs.new);
-
- cpufreq_freq_transition_begin(policy, &freqs);
- }
-
- retval = cpufreq_driver->target_index(policy, index);
- if (retval)
- pr_err("%s: Failed to change cpu frequency: %d\n", __func__,
- retval);
-
- if (notify) {
- cpufreq_freq_transition_end(policy, &freqs, retval);
-
- /*
- * Failed after setting to intermediate freq? Driver should have
- * reverted back to initial frequency and so should we. Check
- * here for intermediate_freq instead of get_intermediate, in
- * case we haven't switched to intermediate freq at all.
- */
- if (unlikely(retval && intermediate_freq)) {
- freqs.old = intermediate_freq;
- freqs.new = policy->restore_freq;
- cpufreq_freq_transition_begin(policy, &freqs);
- cpufreq_freq_transition_end(policy, &freqs, 0);
- }
- }
-
- return retval;
-}
-
-int __cpufreq_driver_target(struct cpufreq_policy *policy,
- unsigned int target_freq,
- unsigned int relation)
-{
- unsigned int old_target_freq = target_freq;
- int index;
-
- if (cpufreq_disabled())
- return -ENODEV;
-
- /* Make sure that target_freq is within supported range */
- target_freq = clamp_val(target_freq, policy->min, policy->max);
-
- pr_debug("target for CPU %u: %u kHz, relation %u, requested %u kHz\n",
- policy->cpu, target_freq, relation, old_target_freq);
-
- /*
- * This might look like a redundant call as we are checking it again
- * after finding index. But it is left intentionally for cases where
- * exactly same freq is called again and so we can save on few function
- * calls.
- */
- if (target_freq == policy->cur)
- return 0;
-
- /* Save last value to restore later on errors */
- policy->restore_freq = policy->cur;
-
- if (cpufreq_driver->target)
- return cpufreq_driver->target(policy, target_freq, relation);
-
- if (!cpufreq_driver->target_index)
- return -EINVAL;
-
- index = cpufreq_frequency_table_target(policy, target_freq, relation);
-
- return __target_index(policy, index);
-}
-EXPORT_SYMBOL_GPL(__cpufreq_driver_target);
-
-int cpufreq_driver_target(struct cpufreq_policy *policy,
- unsigned int target_freq,
- unsigned int relation)
-{
- int ret = -EINVAL;
-
- down_write(&policy->rwsem);
-
- ret = __cpufreq_driver_target(policy, target_freq, relation);
-
- up_write(&policy->rwsem);
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(cpufreq_driver_target);
-
-__weak struct cpufreq_governor *cpufreq_fallback_governor(void)
-{
- return NULL;
-}
-
-static int cpufreq_init_governor(struct cpufreq_policy *policy)
-{
- int ret;
-
- /* Don't start any governor operations if we are entering suspend */
- if (cpufreq_suspended)
- return 0;
- /*
- * Governor might not be initiated here if ACPI _PPC changed
- * notification happened, so check it.
- */
- if (!policy->governor)
- return -EINVAL;
-
- /* Platform doesn't want dynamic frequency switching ? */
- if (policy->governor->dynamic_switching &&
- cpufreq_driver->flags & CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING) {
- struct cpufreq_governor *gov = cpufreq_fallback_governor();
-
- if (gov) {
- pr_warn("Can't use %s governor as dynamic switching is disallowed. Fallback to %s governor\n",
- policy->governor->name, gov->name);
- policy->governor = gov;
- } else {
- return -EINVAL;
- }
- }
-
- if (!try_module_get(policy->governor->owner))
- return -EINVAL;
-
- pr_debug("%s: for CPU %u\n", __func__, policy->cpu);
-
- if (policy->governor->init) {
- ret = policy->governor->init(policy);
- if (ret) {
- module_put(policy->governor->owner);
- return ret;
- }
- }
-
- return 0;
-}
-
-static void cpufreq_exit_governor(struct cpufreq_policy *policy)
-{
- if (cpufreq_suspended || !policy->governor)
- return;
-
- pr_debug("%s: for CPU %u\n", __func__, policy->cpu);
-
- if (policy->governor->exit)
- policy->governor->exit(policy);
-
- module_put(policy->governor->owner);
-}
-
-static int cpufreq_start_governor(struct cpufreq_policy *policy)
-{
- int ret;
-
- if (cpufreq_suspended)
- return 0;
-
- if (!policy->governor)
- return -EINVAL;
-
- pr_debug("%s: for CPU %u\n", __func__, policy->cpu);
-
- if (cpufreq_driver->get && !cpufreq_driver->setpolicy)
- cpufreq_update_current_freq(policy);
-
- if (policy->governor->start) {
- ret = policy->governor->start(policy);
- if (ret)
- return ret;
- }
-
- if (policy->governor->limits)
- policy->governor->limits(policy);
-
- return 0;
-}
-
-static void cpufreq_stop_governor(struct cpufreq_policy *policy)
-{
- if (cpufreq_suspended || !policy->governor)
- return;
-
- pr_debug("%s: for CPU %u\n", __func__, policy->cpu);
-
- if (policy->governor->stop)
- policy->governor->stop(policy);
-}
-
-static void cpufreq_governor_limits(struct cpufreq_policy *policy)
-{
- if (cpufreq_suspended || !policy->governor)
- return;
-
- pr_debug("%s: for CPU %u\n", __func__, policy->cpu);
-
- if (policy->governor->limits)
- policy->governor->limits(policy);
-}
-
-int cpufreq_register_governor(struct cpufreq_governor *governor)
-{
- int err;
-
- if (!governor)
- return -EINVAL;
-
- if (cpufreq_disabled())
- return -ENODEV;
-
- mutex_lock(&cpufreq_governor_mutex);
-
- err = -EBUSY;
- if (!find_governor(governor->name)) {
- err = 0;
- list_add(&governor->governor_list, &cpufreq_governor_list);
- }
-
- mutex_unlock(&cpufreq_governor_mutex);
- return err;
-}
-EXPORT_SYMBOL_GPL(cpufreq_register_governor);
-
-void cpufreq_unregister_governor(struct cpufreq_governor *governor)
-{
- struct cpufreq_policy *policy;
- unsigned long flags;
-
- if (!governor)
- return;
-
- if (cpufreq_disabled())
- return;
-
- /* clear last_governor for all inactive policies */
- read_lock_irqsave(&cpufreq_driver_lock, flags);
- for_each_inactive_policy(policy) {
- if (!strcmp(policy->last_governor, governor->name)) {
- policy->governor = NULL;
- strcpy(policy->last_governor, "\0");
- }
- }
- read_unlock_irqrestore(&cpufreq_driver_lock, flags);
-
- mutex_lock(&cpufreq_governor_mutex);
- list_del(&governor->governor_list);
- mutex_unlock(&cpufreq_governor_mutex);
-}
-EXPORT_SYMBOL_GPL(cpufreq_unregister_governor);
-
-
-/*********************************************************************
- * POLICY INTERFACE *
- *********************************************************************/
-
-/**
- * cpufreq_get_policy - get the current cpufreq_policy
- * @policy: struct cpufreq_policy into which the current cpufreq_policy
- * is written
- *
- * Reads the current cpufreq policy.
- */
-int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu)
-{
- struct cpufreq_policy *cpu_policy;
- if (!policy)
- return -EINVAL;
-
- cpu_policy = cpufreq_cpu_get(cpu);
- if (!cpu_policy)
- return -EINVAL;
-
- memcpy(policy, cpu_policy, sizeof(*policy));
-
- cpufreq_cpu_put(cpu_policy);
- return 0;
-}
-EXPORT_SYMBOL(cpufreq_get_policy);
-
-/*
- * policy : current policy.
- * new_policy: policy to be set.
- */
-static int cpufreq_set_policy(struct cpufreq_policy *policy,
- struct cpufreq_policy *new_policy)
-{
- struct cpufreq_governor *old_gov;
- int ret;
-
- pr_debug("setting new policy for CPU %u: %u - %u kHz\n",
- new_policy->cpu, new_policy->min, new_policy->max);
-
- memcpy(&new_policy->cpuinfo, &policy->cpuinfo, sizeof(policy->cpuinfo));
-
- /*
- * This check works well when we store new min/max freq attributes,
- * because new_policy is a copy of policy with one field updated.
- */
- if (new_policy->min > new_policy->max)
- return -EINVAL;
-
- /* verify the cpu speed can be set within this limit */
- ret = cpufreq_driver->verify(new_policy);
- if (ret)
- return ret;
-
- /* adjust if necessary - all reasons */
- blocking_notifier_call_chain(&cpufreq_policy_notifier_list,
- CPUFREQ_ADJUST, new_policy);
-
- /*
- * verify the cpu speed can be set within this limit, which might be
- * different to the first one
- */
- ret = cpufreq_driver->verify(new_policy);
- if (ret)
- return ret;
-
- /* notification of the new policy */
- blocking_notifier_call_chain(&cpufreq_policy_notifier_list,
- CPUFREQ_NOTIFY, new_policy);
-
- policy->min = new_policy->min;
- policy->max = new_policy->max;
-
- policy->cached_target_freq = UINT_MAX;
-
- pr_debug("new min and max freqs are %u - %u kHz\n",
- policy->min, policy->max);
-
- if (cpufreq_driver->setpolicy) {
- policy->policy = new_policy->policy;
- pr_debug("setting range\n");
- return cpufreq_driver->setpolicy(new_policy);
- }
-
- if (new_policy->governor == policy->governor) {
- pr_debug("cpufreq: governor limits update\n");
- cpufreq_governor_limits(policy);
- return 0;
- }
-
- pr_debug("governor switch\n");
-
- /* save old, working values */
- old_gov = policy->governor;
- /* end old governor */
- if (old_gov) {
- cpufreq_stop_governor(policy);
- cpufreq_exit_governor(policy);
- }
-
- /* start new governor */
- policy->governor = new_policy->governor;
- ret = cpufreq_init_governor(policy);
- if (!ret) {
- ret = cpufreq_start_governor(policy);
- if (!ret) {
- pr_debug("cpufreq: governor change\n");
- return 0;
- }
- cpufreq_exit_governor(policy);
- }
-
- /* new governor failed, so re-start old one */
- pr_debug("starting governor %s failed\n", policy->governor->name);
- if (old_gov) {
- policy->governor = old_gov;
- if (cpufreq_init_governor(policy))
- policy->governor = NULL;
- else
- cpufreq_start_governor(policy);
- }
-
- return ret;
-}
-
-/**
- * cpufreq_update_policy - re-evaluate an existing cpufreq policy
- * @cpu: CPU which shall be re-evaluated
- *
- * Useful for policy notifiers which have different necessities
- * at different times.
- */
-void cpufreq_update_policy(unsigned int cpu)
-{
- struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
- struct cpufreq_policy new_policy;
-
- if (!policy)
- return;
-
- down_write(&policy->rwsem);
-
- if (policy_is_inactive(policy))
- goto unlock;
-
- pr_debug("updating policy for CPU %u\n", cpu);
- memcpy(&new_policy, policy, sizeof(*policy));
- new_policy.min = policy->user_policy.min;
- new_policy.max = policy->user_policy.max;
-
- /*
- * BIOS might change freq behind our back
- * -> ask driver for current freq and notify governors about a change
- */
- if (cpufreq_driver->get && !cpufreq_driver->setpolicy) {
- if (cpufreq_suspended)
- goto unlock;
-
- new_policy.cur = cpufreq_update_current_freq(policy);
- if (WARN_ON(!new_policy.cur))
- goto unlock;
- }
-
- cpufreq_set_policy(policy, &new_policy);
-
-unlock:
- up_write(&policy->rwsem);
-
- cpufreq_cpu_put(policy);
-}
-EXPORT_SYMBOL(cpufreq_update_policy);
-
-/*********************************************************************
- * BOOST *
- *********************************************************************/
-static int cpufreq_boost_set_sw(int state)
-{
- struct cpufreq_policy *policy;
- int ret = -EINVAL;
-
- for_each_active_policy(policy) {
- if (!policy->freq_table)
- continue;
-
- ret = cpufreq_frequency_table_cpuinfo(policy,
- policy->freq_table);
- if (ret) {
- pr_err("%s: Policy frequency update failed\n",
- __func__);
- break;
- }
-
- down_write(&policy->rwsem);
- policy->user_policy.max = policy->max;
- cpufreq_governor_limits(policy);
- up_write(&policy->rwsem);
- }
-
- return ret;
-}
-
-int cpufreq_boost_trigger_state(int state)
-{
- unsigned long flags;
- int ret = 0;
-
- if (cpufreq_driver->boost_enabled == state)
- return 0;
-
- write_lock_irqsave(&cpufreq_driver_lock, flags);
- cpufreq_driver->boost_enabled = state;
- write_unlock_irqrestore(&cpufreq_driver_lock, flags);
-
- ret = cpufreq_driver->set_boost(state);
- if (ret) {
- write_lock_irqsave(&cpufreq_driver_lock, flags);
- cpufreq_driver->boost_enabled = !state;
- write_unlock_irqrestore(&cpufreq_driver_lock, flags);
-
- pr_err("%s: Cannot %s BOOST\n",
- __func__, state ? "enable" : "disable");
- }
-
- return ret;
-}
-
-static bool cpufreq_boost_supported(void)
-{
- return likely(cpufreq_driver) && cpufreq_driver->set_boost;
-}
-
-static int create_boost_sysfs_file(void)
-{
- int ret;
-
- ret = sysfs_create_file(cpufreq_global_kobject, &boost.attr);
- if (ret)
- pr_err("%s: cannot register global BOOST sysfs file\n",
- __func__);
-
- return ret;
-}
-
-static void remove_boost_sysfs_file(void)
-{
- if (cpufreq_boost_supported())
- sysfs_remove_file(cpufreq_global_kobject, &boost.attr);
-}
-
-int cpufreq_enable_boost_support(void)
-{
- if (!cpufreq_driver)
- return -EINVAL;
-
- if (cpufreq_boost_supported())
- return 0;
-
- cpufreq_driver->set_boost = cpufreq_boost_set_sw;
-
- /* This will get removed on driver unregister */
- return create_boost_sysfs_file();
-}
-EXPORT_SYMBOL_GPL(cpufreq_enable_boost_support);
-
-int cpufreq_boost_enabled(void)
-{
- return cpufreq_driver->boost_enabled;
-}
-EXPORT_SYMBOL_GPL(cpufreq_boost_enabled);
-
-/*********************************************************************
- * REGISTER / UNREGISTER CPUFREQ DRIVER *
- *********************************************************************/
-static enum cpuhp_state hp_online;
-
-static int cpuhp_cpufreq_online(unsigned int cpu)
-{
- cpufreq_online(cpu);
-
- return 0;
-}
-
-static int cpuhp_cpufreq_offline(unsigned int cpu)
-{
- cpufreq_offline(cpu);
-
- return 0;
-}
-
-/**
- * cpufreq_register_driver - register a CPU Frequency driver
- * @driver_data: A struct cpufreq_driver containing the values#
- * submitted by the CPU Frequency driver.
- *
- * Registers a CPU Frequency driver to this core code. This code
- * returns zero on success, -EEXIST when another driver got here first
- * (and isn't unregistered in the meantime).
- *
- */
-int cpufreq_register_driver(struct cpufreq_driver *driver_data)
-{
- unsigned long flags;
- int ret;
-
- if (cpufreq_disabled())
- return -ENODEV;
-
- if (!driver_data || !driver_data->verify || !driver_data->init ||
- !(driver_data->setpolicy || driver_data->target_index ||
- driver_data->target) ||
- (driver_data->setpolicy && (driver_data->target_index ||
- driver_data->target)) ||
- (!!driver_data->get_intermediate != !!driver_data->target_intermediate))
- return -EINVAL;
-
- pr_debug("trying to register driver %s\n", driver_data->name);
-
- /* Protect against concurrent CPU online/offline. */
- cpus_read_lock();
-
- write_lock_irqsave(&cpufreq_driver_lock, flags);
- if (cpufreq_driver) {
- write_unlock_irqrestore(&cpufreq_driver_lock, flags);
- ret = -EEXIST;
- goto out;
- }
- cpufreq_driver = driver_data;
- write_unlock_irqrestore(&cpufreq_driver_lock, flags);
-
- if (driver_data->setpolicy)
- driver_data->flags |= CPUFREQ_CONST_LOOPS;
-
- if (cpufreq_boost_supported()) {
- ret = create_boost_sysfs_file();
- if (ret)
- goto err_null_driver;
- }
-
- ret = subsys_interface_register(&cpufreq_interface);
- if (ret)
- goto err_boost_unreg;
-
- if (!(cpufreq_driver->flags & CPUFREQ_STICKY) &&
- list_empty(&cpufreq_policy_list)) {
- /* if all ->init() calls failed, unregister */
- ret = -ENODEV;
- pr_debug("%s: No CPU initialized for driver %s\n", __func__,
- driver_data->name);
- goto err_if_unreg;
- }
-
- ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
- "cpufreq:online",
- cpuhp_cpufreq_online,
- cpuhp_cpufreq_offline);
- if (ret < 0)
- goto err_if_unreg;
- hp_online = ret;
- ret = 0;
-
- pr_debug("driver %s up and running\n", driver_data->name);
- goto out;
-
-err_if_unreg:
- subsys_interface_unregister(&cpufreq_interface);
-err_boost_unreg:
- remove_boost_sysfs_file();
-err_null_driver:
- write_lock_irqsave(&cpufreq_driver_lock, flags);
- cpufreq_driver = NULL;
- write_unlock_irqrestore(&cpufreq_driver_lock, flags);
-out:
- cpus_read_unlock();
- return ret;
-}
-EXPORT_SYMBOL_GPL(cpufreq_register_driver);
-
-/**
- * cpufreq_unregister_driver - unregister the current CPUFreq driver
- *
- * Unregister the current CPUFreq driver. Only call this if you have
- * the right to do so, i.e. if you have succeeded in initialising before!
- * Returns zero if successful, and -EINVAL if the cpufreq_driver is
- * currently not initialised.
- */
-int cpufreq_unregister_driver(struct cpufreq_driver *driver)
-{
- unsigned long flags;
-
- if (!cpufreq_driver || (driver != cpufreq_driver))
- return -EINVAL;
-
- pr_debug("unregistering driver %s\n", driver->name);
-
- /* Protect against concurrent cpu hotplug */
- cpus_read_lock();
- subsys_interface_unregister(&cpufreq_interface);
- remove_boost_sysfs_file();
- cpuhp_remove_state_nocalls_cpuslocked(hp_online);
-
- write_lock_irqsave(&cpufreq_driver_lock, flags);
-
- cpufreq_driver = NULL;
-
- write_unlock_irqrestore(&cpufreq_driver_lock, flags);
- cpus_read_unlock();
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(cpufreq_unregister_driver);
-
-/*
- * Stop cpufreq at shutdown to make sure it isn't holding any locks
- * or mutexes when secondary CPUs are halted.
- */
-static struct syscore_ops cpufreq_syscore_ops = {
- .shutdown = cpufreq_suspend,
-};
-
-struct kobject *cpufreq_global_kobject;
-EXPORT_SYMBOL(cpufreq_global_kobject);
-
-static int __init cpufreq_core_init(void)
-{
- if (cpufreq_disabled())
- return -ENODEV;
-
- cpufreq_global_kobject = kobject_create_and_add("cpufreq", &cpu_subsys.dev_root->kobj);
- BUG_ON(!cpufreq_global_kobject);
-
- register_syscore_ops(&cpufreq_syscore_ops);
-
- return 0;
-}
-module_param(off, int, 0444);
-core_initcall(cpufreq_core_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 14/28] mtd: Remove Blackfin MTD support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (11 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 13/28] cpufreq: Remove Blackfin CPU frequency support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 15/28] spi: Remove Blackfin SPI bus support Aaron Wu
` (13 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin MTD support
---
drivers/mtd/maps/Kconfig | 10 -
drivers/mtd/maps/Makefile | 1 -
drivers/mtd/maps/bfin-async-flash.c | 196 --------
drivers/mtd/nand/Kconfig | 32 --
drivers/mtd/nand/Makefile | 1 -
drivers/mtd/nand/bf5xx_nand.c | 862 ------------------------------------
6 files changed, 1102 deletions(-)
delete mode 100644 drivers/mtd/maps/bfin-async-flash.c
delete mode 100644 drivers/mtd/nand/bf5xx_nand.c
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 542fdf8..bdc1283 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -334,16 +334,6 @@ config MTD_PCMCIA_ANONYMOUS
If unsure, say N.
-config MTD_BFIN_ASYNC
- tristate "Blackfin BF533-STAMP Flash Chip Support"
- depends on BFIN533_STAMP && MTD_CFI && MTD_COMPLEX_MAPPINGS
- default y
- help
- Map driver which allows for simultaneous utilization of
- ethernet and CFI parallel flash.
-
- If compiled as a module, it will be called bfin-async-flash.
-
config MTD_GPIO_ADDR
tristate "GPIO-assisted Flash Chip Support"
depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index b849aaf..51acf1f 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o
obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o
obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o
-obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-async-flash.o
obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o
obj-$(CONFIG_MTD_VMU) += vmu-flash.o
obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
diff --git a/drivers/mtd/maps/bfin-async-flash.c b/drivers/mtd/maps/bfin-async-flash.c
deleted file mode 100644
index 41730fe..0000000
--- a/drivers/mtd/maps/bfin-async-flash.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * drivers/mtd/maps/bfin-async-flash.c
- *
- * Handle the case where flash memory and ethernet mac/phy are
- * mapped onto the same async bank. The BF533-STAMP does this
- * for example. All board-specific configuration goes in your
- * board resources file.
- *
- * Copyright 2000 Nicolas Pitre <nico@fluxnic.net>
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-
-#include <asm/blackfin.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <asm/unaligned.h>
-
-#define pr_devinit(fmt, args...) \
- ({ static const char __fmt[] = fmt; printk(__fmt, ## args); })
-
-#define DRIVER_NAME "bfin-async-flash"
-
-struct async_state {
- struct mtd_info *mtd;
- struct map_info map;
- int enet_flash_pin;
- uint32_t flash_ambctl0, flash_ambctl1;
- uint32_t save_ambctl0, save_ambctl1;
- unsigned long irq_flags;
-};
-
-static void switch_to_flash(struct async_state *state)
-{
- local_irq_save(state->irq_flags);
-
- gpio_set_value(state->enet_flash_pin, 0);
-
- state->save_ambctl0 = bfin_read_EBIU_AMBCTL0();
- state->save_ambctl1 = bfin_read_EBIU_AMBCTL1();
- bfin_write_EBIU_AMBCTL0(state->flash_ambctl0);
- bfin_write_EBIU_AMBCTL1(state->flash_ambctl1);
- SSYNC();
-}
-
-static void switch_back(struct async_state *state)
-{
- bfin_write_EBIU_AMBCTL0(state->save_ambctl0);
- bfin_write_EBIU_AMBCTL1(state->save_ambctl1);
- SSYNC();
-
- gpio_set_value(state->enet_flash_pin, 1);
-
- local_irq_restore(state->irq_flags);
-}
-
-static map_word bfin_flash_read(struct map_info *map, unsigned long ofs)
-{
- struct async_state *state = (struct async_state *)map->map_priv_1;
- uint16_t word;
- map_word test;
-
- switch_to_flash(state);
-
- word = readw(map->virt + ofs);
-
- switch_back(state);
-
- test.x[0] = word;
- return test;
-}
-
-static void bfin_flash_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
-{
- struct async_state *state = (struct async_state *)map->map_priv_1;
-
- switch_to_flash(state);
-
- memcpy(to, map->virt + from, len);
-
- switch_back(state);
-}
-
-static void bfin_flash_write(struct map_info *map, map_word d1, unsigned long ofs)
-{
- struct async_state *state = (struct async_state *)map->map_priv_1;
- uint16_t d;
-
- d = d1.x[0];
-
- switch_to_flash(state);
-
- writew(d, map->virt + ofs);
- SSYNC();
-
- switch_back(state);
-}
-
-static void bfin_flash_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
-{
- struct async_state *state = (struct async_state *)map->map_priv_1;
-
- switch_to_flash(state);
-
- memcpy(map->virt + to, from, len);
- SSYNC();
-
- switch_back(state);
-}
-
-static const char * const part_probe_types[] = {
- "cmdlinepart", "RedBoot", NULL };
-
-static int bfin_flash_probe(struct platform_device *pdev)
-{
- struct physmap_flash_data *pdata = dev_get_platdata(&pdev->dev);
- struct resource *memory = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- struct resource *flash_ambctl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- struct async_state *state;
-
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (!state)
- return -ENOMEM;
-
- state->map.name = DRIVER_NAME;
- state->map.read = bfin_flash_read;
- state->map.copy_from = bfin_flash_copy_from;
- state->map.write = bfin_flash_write;
- state->map.copy_to = bfin_flash_copy_to;
- state->map.bankwidth = pdata->width;
- state->map.size = resource_size(memory);
- state->map.virt = (void __iomem *)memory->start;
- state->map.phys = memory->start;
- state->map.map_priv_1 = (unsigned long)state;
- state->enet_flash_pin = platform_get_irq(pdev, 0);
- state->flash_ambctl0 = flash_ambctl->start;
- state->flash_ambctl1 = flash_ambctl->end;
-
- if (gpio_request(state->enet_flash_pin, DRIVER_NAME)) {
- pr_devinit(KERN_ERR DRIVER_NAME ": Failed to request gpio %d\n", state->enet_flash_pin);
- kfree(state);
- return -EBUSY;
- }
- gpio_direction_output(state->enet_flash_pin, 1);
-
- pr_devinit(KERN_NOTICE DRIVER_NAME ": probing %d-bit flash bus\n", state->map.bankwidth * 8);
- state->mtd = do_map_probe(memory->name, &state->map);
- if (!state->mtd) {
- gpio_free(state->enet_flash_pin);
- kfree(state);
- return -ENXIO;
- }
-
- mtd_device_parse_register(state->mtd, part_probe_types, NULL,
- pdata->parts, pdata->nr_parts);
-
- platform_set_drvdata(pdev, state);
-
- return 0;
-}
-
-static int bfin_flash_remove(struct platform_device *pdev)
-{
- struct async_state *state = platform_get_drvdata(pdev);
- gpio_free(state->enet_flash_pin);
- mtd_device_unregister(state->mtd);
- map_destroy(state->mtd);
- kfree(state);
- return 0;
-}
-
-static struct platform_driver bfin_flash_driver = {
- .probe = bfin_flash_probe,
- .remove = bfin_flash_remove,
- .driver = {
- .name = DRIVER_NAME,
- },
-};
-
-module_platform_driver(bfin_flash_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("MTD map driver for Blackfins with flash/ethernet on same async bank");
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 736ac88..c0bee1f0 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -116,38 +116,6 @@ config MTD_NAND_AU1550
This enables the driver for the NAND flash controller on the
AMD/Alchemy 1550 SOC.
-config MTD_NAND_BF5XX
- tristate "Blackfin on-chip NAND Flash Controller driver"
- depends on BF54x || BF52x
- help
- This enables the Blackfin on-chip NAND flash controller
-
- No board specific support is done by this driver, each board
- must advertise a platform_device for the driver to attach.
-
- This driver can also be built as a module. If so, the module
- will be called bf5xx-nand.
-
-config MTD_NAND_BF5XX_HWECC
- bool "BF5XX NAND Hardware ECC"
- default y
- depends on MTD_NAND_BF5XX
- help
- Enable the use of the BF5XX's internal ECC generator when
- using NAND.
-
-config MTD_NAND_BF5XX_BOOTROM_ECC
- bool "Use Blackfin BootROM ECC Layout"
- default n
- depends on MTD_NAND_BF5XX_HWECC
- help
- If you wish to modify NAND pages and allow the Blackfin on-chip
- BootROM to boot from them, say Y here. This is only necessary
- if you are booting U-Boot out of NAND and you wish to update
- U-Boot from Linux' userspace. Otherwise, you should say N here.
-
- If unsure, say N.
-
config MTD_NAND_S3C2410
tristate "NAND Flash support for Samsung S3C SoCs"
depends on ARCH_S3C24XX || ARCH_S3C64XX
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 921634b..08fc018 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_MTD_NAND_DENALI) += denali.o
obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o
obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o
obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
-obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o
obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
obj-$(CONFIG_MTD_NAND_TANGO) += tango_nand.o
obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o
diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c
deleted file mode 100644
index 87bbd17..0000000
--- a/drivers/mtd/nand/bf5xx_nand.c
+++ /dev/null
@@ -1,862 +0,0 @@
-/* linux/drivers/mtd/nand/bf5xx_nand.c
- *
- * Copyright 2006-2008 Analog Devices Inc.
- * http://blackfin.uclinux.org/
- * Bryan Wu <bryan.wu@analog.com>
- *
- * Blackfin BF5xx on-chip NAND flash controller driver
- *
- * Derived from drivers/mtd/nand/s3c2410.c
- * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
- *
- * Derived from drivers/mtd/nand/cafe.c
- * Copyright © 2006 Red Hat, Inc.
- * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
- *
- * Changelog:
- * 12-Jun-2007 Bryan Wu: Initial version
- * 18-Jul-2007 Bryan Wu:
- * - ECC_HW and ECC_SW supported
- * - DMA supported in ECC_HW
- * - YAFFS tested as rootfs in both ECC_HW and ECC_SW
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/bitops.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-#include <asm/cacheflush.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-
-#define DRV_NAME "bf5xx-nand"
-#define DRV_VERSION "1.2"
-#define DRV_AUTHOR "Bryan Wu <bryan.wu@analog.com>"
-#define DRV_DESC "BF5xx on-chip NAND FLash Controller Driver"
-
-/* NFC_STAT Masks */
-#define NBUSY 0x01 /* Not Busy */
-#define WB_FULL 0x02 /* Write Buffer Full */
-#define PG_WR_STAT 0x04 /* Page Write Pending */
-#define PG_RD_STAT 0x08 /* Page Read Pending */
-#define WB_EMPTY 0x10 /* Write Buffer Empty */
-
-/* NFC_IRQSTAT Masks */
-#define NBUSYIRQ 0x01 /* Not Busy IRQ */
-#define WB_OVF 0x02 /* Write Buffer Overflow */
-#define WB_EDGE 0x04 /* Write Buffer Edge Detect */
-#define RD_RDY 0x08 /* Read Data Ready */
-#define WR_DONE 0x10 /* Page Write Done */
-
-/* NFC_RST Masks */
-#define ECC_RST 0x01 /* ECC (and NFC counters) Reset */
-
-/* NFC_PGCTL Masks */
-#define PG_RD_START 0x01 /* Page Read Start */
-#define PG_WR_START 0x02 /* Page Write Start */
-
-#ifdef CONFIG_MTD_NAND_BF5XX_HWECC
-static int hardware_ecc = 1;
-#else
-static int hardware_ecc;
-#endif
-
-static const unsigned short bfin_nfc_pin_req[] =
- {P_NAND_CE,
- P_NAND_RB,
- P_NAND_D0,
- P_NAND_D1,
- P_NAND_D2,
- P_NAND_D3,
- P_NAND_D4,
- P_NAND_D5,
- P_NAND_D6,
- P_NAND_D7,
- P_NAND_WE,
- P_NAND_RE,
- P_NAND_CLE,
- P_NAND_ALE,
- 0};
-
-#ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
-static int bootrom_ooblayout_ecc(struct mtd_info *mtd, int section,
- struct mtd_oob_region *oobregion)
-{
- if (section > 7)
- return -ERANGE;
-
- oobregion->offset = section * 8;
- oobregion->length = 3;
-
- return 0;
-}
-
-static int bootrom_ooblayout_free(struct mtd_info *mtd, int section,
- struct mtd_oob_region *oobregion)
-{
- if (section > 7)
- return -ERANGE;
-
- oobregion->offset = (section * 8) + 3;
- oobregion->length = 5;
-
- return 0;
-}
-
-static const struct mtd_ooblayout_ops bootrom_ooblayout_ops = {
- .ecc = bootrom_ooblayout_ecc,
- .free = bootrom_ooblayout_free,
-};
-#endif
-
-/*
- * Data structures for bf5xx nand flash controller driver
- */
-
-/* bf5xx nand info */
-struct bf5xx_nand_info {
- /* mtd info */
- struct nand_hw_control controller;
- struct nand_chip chip;
-
- /* platform info */
- struct bf5xx_nand_platform *platform;
-
- /* device info */
- struct device *device;
-
- /* DMA stuff */
- struct completion dma_completion;
-};
-
-/*
- * Conversion functions
- */
-static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
-{
- return container_of(mtd_to_nand(mtd), struct bf5xx_nand_info,
- chip);
-}
-
-static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
-{
- return platform_get_drvdata(pdev);
-}
-
-static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
-{
- return dev_get_platdata(&pdev->dev);
-}
-
-/*
- * struct nand_chip interface function pointers
- */
-
-/*
- * bf5xx_nand_hwcontrol
- *
- * Issue command and address cycles to the chip
- */
-static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- if (cmd == NAND_CMD_NONE)
- return;
-
- while (bfin_read_NFC_STAT() & WB_FULL)
- cpu_relax();
-
- if (ctrl & NAND_CLE)
- bfin_write_NFC_CMD(cmd);
- else if (ctrl & NAND_ALE)
- bfin_write_NFC_ADDR(cmd);
- SSYNC();
-}
-
-/*
- * bf5xx_nand_devready()
- *
- * returns 0 if the nand is busy, 1 if it is ready
- */
-static int bf5xx_nand_devready(struct mtd_info *mtd)
-{
- unsigned short val = bfin_read_NFC_STAT();
-
- if ((val & NBUSY) == NBUSY)
- return 1;
- else
- return 0;
-}
-
-/*
- * ECC functions
- * These allow the bf5xx to use the controller's ECC
- * generator block to ECC the data as it passes through
- */
-
-/*
- * ECC error correction function
- */
-static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
- u_char *read_ecc, u_char *calc_ecc)
-{
- struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
- u32 syndrome[5];
- u32 calced, stored;
- int i;
- unsigned short failing_bit, failing_byte;
- u_char data;
-
- calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
- stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
-
- syndrome[0] = (calced ^ stored);
-
- /*
- * syndrome 0: all zero
- * No error in data
- * No action
- */
- if (!syndrome[0] || !calced || !stored)
- return 0;
-
- /*
- * sysdrome 0: only one bit is one
- * ECC data was incorrect
- * No action
- */
- if (hweight32(syndrome[0]) == 1) {
- dev_err(info->device, "ECC data was incorrect!\n");
- return -EBADMSG;
- }
-
- syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
- syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
- syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
- syndrome[4] = syndrome[2] ^ syndrome[3];
-
- for (i = 0; i < 5; i++)
- dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
-
- dev_info(info->device,
- "calced[0x%08x], stored[0x%08x]\n",
- calced, stored);
-
- /*
- * sysdrome 0: exactly 11 bits are one, each parity
- * and parity' pair is 1 & 0 or 0 & 1.
- * 1-bit correctable error
- * Correct the error
- */
- if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
- dev_info(info->device,
- "1-bit correctable error, correct it.\n");
- dev_info(info->device,
- "syndrome[1] 0x%08x\n", syndrome[1]);
-
- failing_bit = syndrome[1] & 0x7;
- failing_byte = syndrome[1] >> 0x3;
- data = *(dat + failing_byte);
- data = data ^ (0x1 << failing_bit);
- *(dat + failing_byte) = data;
-
- return 1;
- }
-
- /*
- * sysdrome 0: random data
- * More than 1-bit error, non-correctable error
- * Discard data, mark bad block
- */
- dev_err(info->device,
- "More than 1-bit error, non-correctable error.\n");
- dev_err(info->device,
- "Please discard data, mark bad block\n");
-
- return -EBADMSG;
-}
-
-static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
- u_char *read_ecc, u_char *calc_ecc)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- int ret, bitflips = 0;
-
- ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
- if (ret < 0)
- return ret;
-
- bitflips = ret;
-
- /* If ecc size is 512, correct second 256 bytes */
- if (chip->ecc.size == 512) {
- dat += 256;
- read_ecc += 3;
- calc_ecc += 3;
- ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
- if (ret < 0)
- return ret;
-
- bitflips += ret;
- }
-
- return bitflips;
-}
-
-static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- return;
-}
-
-static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
- const u_char *dat, u_char *ecc_code)
-{
- struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
- struct nand_chip *chip = mtd_to_nand(mtd);
- u16 ecc0, ecc1;
- u32 code[2];
- u8 *p;
-
- /* first 3 bytes ECC code for 256 page size */
- ecc0 = bfin_read_NFC_ECC0();
- ecc1 = bfin_read_NFC_ECC1();
-
- code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
-
- dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
-
- p = (u8 *) code;
- memcpy(ecc_code, p, 3);
-
- /* second 3 bytes ECC code for 512 ecc size */
- if (chip->ecc.size == 512) {
- ecc0 = bfin_read_NFC_ECC2();
- ecc1 = bfin_read_NFC_ECC3();
- code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
-
- /* second 3 bytes in ecc_code for second 256
- * bytes of 512 page size
- */
- p = (u8 *) (code + 1);
- memcpy((ecc_code + 3), p, 3);
- dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
- }
-
- return 0;
-}
-
-/*
- * PIO mode for buffer writing and reading
- */
-static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- int i;
- unsigned short val;
-
- /*
- * Data reads are requested by first writing to NFC_DATA_RD
- * and then reading back from NFC_READ.
- */
- for (i = 0; i < len; i++) {
- while (bfin_read_NFC_STAT() & WB_FULL)
- cpu_relax();
-
- /* Contents do not matter */
- bfin_write_NFC_DATA_RD(0x0000);
- SSYNC();
-
- while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
- cpu_relax();
-
- buf[i] = bfin_read_NFC_READ();
-
- val = bfin_read_NFC_IRQSTAT();
- val |= RD_RDY;
- bfin_write_NFC_IRQSTAT(val);
- SSYNC();
- }
-}
-
-static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
-{
- uint8_t val;
-
- bf5xx_nand_read_buf(mtd, &val, 1);
-
- return val;
-}
-
-static void bf5xx_nand_write_buf(struct mtd_info *mtd,
- const uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++) {
- while (bfin_read_NFC_STAT() & WB_FULL)
- cpu_relax();
-
- bfin_write_NFC_DATA_WR(buf[i]);
- SSYNC();
- }
-}
-
-static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- int i;
- u16 *p = (u16 *) buf;
- len >>= 1;
-
- /*
- * Data reads are requested by first writing to NFC_DATA_RD
- * and then reading back from NFC_READ.
- */
- bfin_write_NFC_DATA_RD(0x5555);
-
- SSYNC();
-
- for (i = 0; i < len; i++)
- p[i] = bfin_read_NFC_READ();
-}
-
-static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
- const uint8_t *buf, int len)
-{
- int i;
- u16 *p = (u16 *) buf;
- len >>= 1;
-
- for (i = 0; i < len; i++)
- bfin_write_NFC_DATA_WR(p[i]);
-
- SSYNC();
-}
-
-/*
- * DMA functions for buffer writing and reading
- */
-static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
-{
- struct bf5xx_nand_info *info = dev_id;
-
- clear_dma_irqstat(CH_NFC);
- disable_dma(CH_NFC);
- complete(&info->dma_completion);
-
- return IRQ_HANDLED;
-}
-
-static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
- uint8_t *buf, int is_read)
-{
- struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
- struct nand_chip *chip = mtd_to_nand(mtd);
- unsigned short val;
-
- dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
- mtd, buf, is_read);
-
- /*
- * Before starting a dma transfer, be sure to invalidate/flush
- * the cache over the address range of your DMA buffer to
- * prevent cache coherency problems. Otherwise very subtle bugs
- * can be introduced to your driver.
- */
- if (is_read)
- invalidate_dcache_range((unsigned int)buf,
- (unsigned int)(buf + chip->ecc.size));
- else
- flush_dcache_range((unsigned int)buf,
- (unsigned int)(buf + chip->ecc.size));
-
- /*
- * This register must be written before each page is
- * transferred to generate the correct ECC register
- * values.
- */
- bfin_write_NFC_RST(ECC_RST);
- SSYNC();
- while (bfin_read_NFC_RST() & ECC_RST)
- cpu_relax();
-
- disable_dma(CH_NFC);
- clear_dma_irqstat(CH_NFC);
-
- /* setup DMA register with Blackfin DMA API */
- set_dma_config(CH_NFC, 0x0);
- set_dma_start_addr(CH_NFC, (unsigned long) buf);
-
- /* The DMAs have different size on BF52x and BF54x */
-#ifdef CONFIG_BF52x
- set_dma_x_count(CH_NFC, (chip->ecc.size >> 1));
- set_dma_x_modify(CH_NFC, 2);
- val = DI_EN | WDSIZE_16;
-#endif
-
-#ifdef CONFIG_BF54x
- set_dma_x_count(CH_NFC, (chip->ecc.size >> 2));
- set_dma_x_modify(CH_NFC, 4);
- val = DI_EN | WDSIZE_32;
-#endif
- /* setup write or read operation */
- if (is_read)
- val |= WNR;
- set_dma_config(CH_NFC, val);
- enable_dma(CH_NFC);
-
- /* Start PAGE read/write operation */
- if (is_read)
- bfin_write_NFC_PGCTL(PG_RD_START);
- else
- bfin_write_NFC_PGCTL(PG_WR_START);
- wait_for_completion(&info->dma_completion);
-}
-
-static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
- uint8_t *buf, int len)
-{
- struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
- struct nand_chip *chip = mtd_to_nand(mtd);
-
- dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
-
- if (len == chip->ecc.size)
- bf5xx_nand_dma_rw(mtd, buf, 1);
- else
- bf5xx_nand_read_buf(mtd, buf, len);
-}
-
-static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
- const uint8_t *buf, int len)
-{
- struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
- struct nand_chip *chip = mtd_to_nand(mtd);
-
- dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
-
- if (len == chip->ecc.size)
- bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
- else
- bf5xx_nand_write_buf(mtd, buf, len);
-}
-
-static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
- uint8_t *buf, int oob_required, int page)
-{
- nand_read_page_op(chip, page, 0, NULL, 0);
-
- bf5xx_nand_read_buf(mtd, buf, mtd->writesize);
- bf5xx_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
-
- return 0;
-}
-
-static int bf5xx_nand_write_page_raw(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required,
- int page)
-{
- nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
- bf5xx_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
-
- return nand_prog_page_end_op(chip);
-}
-
-/*
- * System initialization functions
- */
-static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
-{
- int ret;
-
- /* Do not use dma */
- if (!hardware_ecc)
- return 0;
-
- init_completion(&info->dma_completion);
-
- /* Request NFC DMA channel */
- ret = request_dma(CH_NFC, "BF5XX NFC driver");
- if (ret < 0) {
- dev_err(info->device, " unable to get DMA channel\n");
- return ret;
- }
-
-#ifdef CONFIG_BF54x
- /* Setup DMAC1 channel mux for NFC which shared with SDH */
- bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() & ~1);
- SSYNC();
-#endif
-
- set_dma_callback(CH_NFC, bf5xx_nand_dma_irq, info);
-
- /* Turn off the DMA channel first */
- disable_dma(CH_NFC);
- return 0;
-}
-
-static void bf5xx_nand_dma_remove(struct bf5xx_nand_info *info)
-{
- /* Free NFC DMA channel */
- if (hardware_ecc)
- free_dma(CH_NFC);
-}
-
-/*
- * BF5XX NFC hardware initialization
- * - pin mux setup
- * - clear interrupt status
- */
-static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
-{
- int err = 0;
- unsigned short val;
- struct bf5xx_nand_platform *plat = info->platform;
-
- /* setup NFC_CTL register */
- dev_info(info->device,
- "data_width=%d, wr_dly=%d, rd_dly=%d\n",
- (plat->data_width ? 16 : 8),
- plat->wr_dly, plat->rd_dly);
-
- val = (1 << NFC_PG_SIZE_OFFSET) |
- (plat->data_width << NFC_NWIDTH_OFFSET) |
- (plat->rd_dly << NFC_RDDLY_OFFSET) |
- (plat->wr_dly << NFC_WRDLY_OFFSET);
- dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
-
- bfin_write_NFC_CTL(val);
- SSYNC();
-
- /* clear interrupt status */
- bfin_write_NFC_IRQMASK(0x0);
- SSYNC();
- val = bfin_read_NFC_IRQSTAT();
- bfin_write_NFC_IRQSTAT(val);
- SSYNC();
-
- /* DMA initialization */
- if (bf5xx_nand_dma_init(info))
- err = -ENXIO;
-
- return err;
-}
-
-/*
- * Device management interface
- */
-static int bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
-{
- struct mtd_info *mtd = nand_to_mtd(&info->chip);
- struct mtd_partition *parts = info->platform->partitions;
- int nr = info->platform->nr_partitions;
-
- return mtd_device_register(mtd, parts, nr);
-}
-
-static int bf5xx_nand_remove(struct platform_device *pdev)
-{
- struct bf5xx_nand_info *info = to_nand_info(pdev);
-
- /* first thing we need to do is release all our mtds
- * and their partitions, then go through freeing the
- * resources used
- */
- nand_release(nand_to_mtd(&info->chip));
-
- peripheral_free_list(bfin_nfc_pin_req);
- bf5xx_nand_dma_remove(info);
-
- return 0;
-}
-
-static int bf5xx_nand_scan(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- int ret;
-
- ret = nand_scan_ident(mtd, 1, NULL);
- if (ret)
- return ret;
-
- if (hardware_ecc) {
- /*
- * for nand with page size > 512B, think it as several sections with 512B
- */
- if (likely(mtd->writesize >= 512)) {
- chip->ecc.size = 512;
- chip->ecc.bytes = 6;
- chip->ecc.strength = 2;
- } else {
- chip->ecc.size = 256;
- chip->ecc.bytes = 3;
- chip->ecc.strength = 1;
- bfin_write_NFC_CTL(bfin_read_NFC_CTL() & ~(1 << NFC_PG_SIZE_OFFSET));
- SSYNC();
- }
- }
-
- return nand_scan_tail(mtd);
-}
-
-/*
- * bf5xx_nand_probe
- *
- * called by device layer when it finds a device matching
- * one our driver can handled. This code checks to see if
- * it can allocate all necessary resources then calls the
- * nand layer to look for devices
- */
-static int bf5xx_nand_probe(struct platform_device *pdev)
-{
- struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
- struct bf5xx_nand_info *info = NULL;
- struct nand_chip *chip = NULL;
- struct mtd_info *mtd = NULL;
- int err = 0;
-
- dev_dbg(&pdev->dev, "(%p)\n", pdev);
-
- if (!plat) {
- dev_err(&pdev->dev, "no platform specific information\n");
- return -EINVAL;
- }
-
- if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
- dev_err(&pdev->dev, "requesting Peripherals failed\n");
- return -EFAULT;
- }
-
- info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
- if (info == NULL) {
- err = -ENOMEM;
- goto out_err;
- }
-
- platform_set_drvdata(pdev, info);
-
- nand_hw_control_init(&info->controller);
-
- info->device = &pdev->dev;
- info->platform = plat;
-
- /* initialise chip data struct */
- chip = &info->chip;
- mtd = nand_to_mtd(&info->chip);
-
- if (plat->data_width)
- chip->options |= NAND_BUSWIDTH_16;
-
- chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
-
- chip->read_buf = (plat->data_width) ?
- bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
- chip->write_buf = (plat->data_width) ?
- bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
-
- chip->read_byte = bf5xx_nand_read_byte;
-
- chip->cmd_ctrl = bf5xx_nand_hwcontrol;
- chip->dev_ready = bf5xx_nand_devready;
-
- nand_set_controller_data(chip, mtd);
- chip->controller = &info->controller;
-
- chip->IO_ADDR_R = (void __iomem *) NFC_READ;
- chip->IO_ADDR_W = (void __iomem *) NFC_DATA_WR;
-
- chip->chip_delay = 0;
-
- /* initialise mtd info data struct */
- mtd->dev.parent = &pdev->dev;
-
- /* initialise the hardware */
- err = bf5xx_nand_hw_init(info);
- if (err)
- goto out_err;
-
- /* setup hardware ECC data struct */
- if (hardware_ecc) {
-#ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
- mtd_set_ooblayout(mtd, &bootrom_ooblayout_ops);
-#endif
- chip->read_buf = bf5xx_nand_dma_read_buf;
- chip->write_buf = bf5xx_nand_dma_write_buf;
- chip->ecc.calculate = bf5xx_nand_calculate_ecc;
- chip->ecc.correct = bf5xx_nand_correct_data;
- chip->ecc.mode = NAND_ECC_HW;
- chip->ecc.hwctl = bf5xx_nand_enable_hwecc;
- chip->ecc.read_page_raw = bf5xx_nand_read_page_raw;
- chip->ecc.write_page_raw = bf5xx_nand_write_page_raw;
- } else {
- chip->ecc.mode = NAND_ECC_SOFT;
- chip->ecc.algo = NAND_ECC_HAMMING;
- }
-
- /* scan hardware nand chip and setup mtd info data struct */
- if (bf5xx_nand_scan(mtd)) {
- err = -ENXIO;
- goto out_err_nand_scan;
- }
-
-#ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
- chip->badblockpos = 63;
-#endif
-
- /* add NAND partition */
- bf5xx_nand_add_partition(info);
-
- dev_dbg(&pdev->dev, "initialised ok\n");
- return 0;
-
-out_err_nand_scan:
- bf5xx_nand_dma_remove(info);
-out_err:
- peripheral_free_list(bfin_nfc_pin_req);
-
- return err;
-}
-
-/* driver device registration */
-static struct platform_driver bf5xx_nand_driver = {
- .probe = bf5xx_nand_probe,
- .remove = bf5xx_nand_remove,
- .driver = {
- .name = DRV_NAME,
- },
-};
-
-module_platform_driver(bf5xx_nand_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR(DRV_AUTHOR);
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_ALIAS("platform:" DRV_NAME);
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 15/28] spi: Remove Blackfin SPI bus support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (12 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 14/28] mtd: Remove Blackfin MTD support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 16/28] irda: Remove Blackfin IRDA support Aaron Wu
` (12 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin SPI bus support
---
drivers/spi/Kconfig | 19 -
drivers/spi/Makefile | 2 -
drivers/spi/spi-adi-v3.c | 984 ----------------------------
drivers/spi/spi-bfin-sport.c | 919 --------------------------
drivers/spi/spi-bfin5xx.c | 1462 ------------------------------------------
5 files changed, 3386 deletions(-)
delete mode 100644 drivers/spi/spi-adi-v3.c
delete mode 100644 drivers/spi/spi-bfin-sport.c
delete mode 100644 drivers/spi/spi-bfin5xx.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 6037839..1263014 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -115,25 +115,6 @@ config SPI_BCM2835AUX
"universal SPI master", and the regular SPI controller.
This driver is for the universal/auxiliary SPI controller.
-config SPI_BFIN5XX
- tristate "SPI controller driver for ADI Blackfin5xx"
- depends on BLACKFIN && !BF60x
- help
- This is the SPI controller master driver for Blackfin 5xx processor.
-
-config SPI_ADI_V3
- tristate "SPI controller v3 for ADI"
- depends on BF60x
- help
- This is the SPI controller v3 master driver
- found on Blackfin 60x processor.
-
-config SPI_BFIN_SPORT
- tristate "SPI bus via Blackfin SPORT"
- depends on BLACKFIN
- help
- Enable support for a SPI bus via the Blackfin SPORT peripheral.
-
config SPI_BCM53XX
tristate "Broadcom BCM53xx SPI controller"
depends on ARCH_BCM_5301X
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 34c5f28..31ee30d 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -24,9 +24,7 @@ obj-$(CONFIG_SPI_BCM53XX) += spi-bcm53xx.o
obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
obj-$(CONFIG_SPI_BCM_QSPI) += spi-iproc-qspi.o spi-brcmstb-qspi.o spi-bcm-qspi.o
-obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o
-obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o
diff --git a/drivers/spi/spi-adi-v3.c b/drivers/spi/spi-adi-v3.c
deleted file mode 100644
index a16b25d..0000000
--- a/drivers/spi/spi-adi-v3.c
+++ /dev/null
@@ -1,984 +0,0 @@
-/*
- * Analog Devices SPI3 controller driver
- *
- * Copyright (c) 2014 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/errno.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/adi_spi3.h>
-#include <linux/types.h>
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-enum adi_spi_state {
- START_STATE,
- RUNNING_STATE,
- DONE_STATE,
- ERROR_STATE
-};
-
-struct adi_spi_master;
-
-struct adi_spi_transfer_ops {
- void (*write) (struct adi_spi_master *);
- void (*read) (struct adi_spi_master *);
- void (*duplex) (struct adi_spi_master *);
-};
-
-/* runtime info for spi master */
-struct adi_spi_master {
- /* SPI framework hookup */
- struct spi_master *master;
-
- /* Regs base of SPI controller */
- struct adi_spi_regs __iomem *regs;
-
- /* Pin request list */
- u16 *pin_req;
-
- /* Message Transfer pump */
- struct tasklet_struct pump_transfers;
-
- /* Current message transfer state info */
- struct spi_message *cur_msg;
- struct spi_transfer *cur_transfer;
- struct adi_spi_device *cur_chip;
- unsigned transfer_len;
-
- /* transfer buffer */
- void *tx;
- void *tx_end;
- void *rx;
- void *rx_end;
-
- /* dma info */
- unsigned int tx_dma;
- unsigned int rx_dma;
- dma_addr_t tx_dma_addr;
- dma_addr_t rx_dma_addr;
- unsigned long dummy_buffer; /* used in unidirectional transfer */
- unsigned long tx_dma_size;
- unsigned long rx_dma_size;
- int tx_num;
- int rx_num;
-
- /* store register value for suspend/resume */
- u32 control;
- u32 ssel;
-
- unsigned long sclk;
- enum adi_spi_state state;
-
- const struct adi_spi_transfer_ops *ops;
-};
-
-struct adi_spi_device {
- u32 control;
- u32 clock;
- u32 ssel;
-
- u8 cs;
- u16 cs_chg_udelay; /* Some devices require > 255usec delay */
- u32 cs_gpio;
- u32 tx_dummy_val; /* tx value for rx only transfer */
- bool enable_dma;
- const struct adi_spi_transfer_ops *ops;
-};
-
-static void adi_spi_enable(struct adi_spi_master *drv_data)
-{
- u32 ctl;
-
- ctl = ioread32(&drv_data->regs->control);
- ctl |= SPI_CTL_EN;
- iowrite32(ctl, &drv_data->regs->control);
-}
-
-static void adi_spi_disable(struct adi_spi_master *drv_data)
-{
- u32 ctl;
-
- ctl = ioread32(&drv_data->regs->control);
- ctl &= ~SPI_CTL_EN;
- iowrite32(ctl, &drv_data->regs->control);
-}
-
-/* Caculate the SPI_CLOCK register value based on input HZ */
-static u32 hz_to_spi_clock(u32 sclk, u32 speed_hz)
-{
- u32 spi_clock = sclk / speed_hz;
-
- if (spi_clock)
- spi_clock--;
- return spi_clock;
-}
-
-static int adi_spi_flush(struct adi_spi_master *drv_data)
-{
- unsigned long limit = loops_per_jiffy << 1;
-
- /* wait for stop and clear stat */
- while (!(ioread32(&drv_data->regs->status) & SPI_STAT_SPIF) && --limit)
- cpu_relax();
-
- iowrite32(0xFFFFFFFF, &drv_data->regs->status);
-
- return limit;
-}
-
-/* Chip select operation functions for cs_change flag */
-static void adi_spi_cs_active(struct adi_spi_master *drv_data, struct adi_spi_device *chip)
-{
- if (likely(chip->cs < MAX_CTRL_CS)) {
- u32 reg;
- reg = ioread32(&drv_data->regs->ssel);
- reg &= ~chip->ssel;
- iowrite32(reg, &drv_data->regs->ssel);
- } else {
- gpio_set_value(chip->cs_gpio, 0);
- }
-}
-
-static void adi_spi_cs_deactive(struct adi_spi_master *drv_data,
- struct adi_spi_device *chip)
-{
- if (likely(chip->cs < MAX_CTRL_CS)) {
- u32 reg;
- reg = ioread32(&drv_data->regs->ssel);
- reg |= chip->ssel;
- iowrite32(reg, &drv_data->regs->ssel);
- } else {
- gpio_set_value(chip->cs_gpio, 1);
- }
-
- /* Move delay here for consistency */
- if (chip->cs_chg_udelay)
- udelay(chip->cs_chg_udelay);
-}
-
-/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
-static inline void adi_spi_cs_enable(struct adi_spi_master *drv_data,
- struct adi_spi_device *chip)
-{
- if (chip->cs < MAX_CTRL_CS) {
- u32 reg;
- reg = ioread32(&drv_data->regs->ssel);
- reg |= chip->ssel >> 8;
- iowrite32(reg, &drv_data->regs->ssel);
- }
-}
-
-static inline void adi_spi_cs_disable(struct adi_spi_master *drv_data,
- struct adi_spi_device *chip)
-{
- if (chip->cs < MAX_CTRL_CS) {
- u32 reg;
- reg = ioread32(&drv_data->regs->ssel);
- reg &= ~(chip->ssel >> 8);
- iowrite32(reg, &drv_data->regs->ssel);
- }
-}
-
-/* stop controller and re-config current chip*/
-static void adi_spi_restore_state(struct adi_spi_master *drv_data)
-{
- struct adi_spi_device *chip = drv_data->cur_chip;
-
- /* Clear status and disable clock */
- iowrite32(0xFFFFFFFF, &drv_data->regs->status);
- iowrite32(0x0, &drv_data->regs->rx_control);
- iowrite32(0x0, &drv_data->regs->tx_control);
- adi_spi_disable(drv_data);
-
- /* Load the registers */
- iowrite32(chip->control, &drv_data->regs->control);
- iowrite32(chip->clock, &drv_data->regs->clock);
-
- adi_spi_enable(drv_data);
- drv_data->tx_num = drv_data->rx_num = 0;
- /* we always choose tx transfer initiate */
- iowrite32(SPI_RXCTL_REN, &drv_data->regs->rx_control);
- iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI, &drv_data->regs->tx_control);
- adi_spi_cs_active(drv_data, chip);
-}
-
-/* discard invalid rx data and empty rfifo */
-static inline void dummy_read(struct adi_spi_master *drv_data)
-{
- while (!(ioread32(&drv_data->regs->status) & SPI_STAT_RFE))
- ioread32(&drv_data->regs->rfifo);
-}
-
-static void adi_spi_u8_write(struct adi_spi_master *drv_data)
-{
- dummy_read(drv_data);
- while (drv_data->tx < drv_data->tx_end) {
- iowrite32(*(u8 *)(drv_data->tx++), &drv_data->regs->tfifo);
- while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
- cpu_relax();
- ioread32(&drv_data->regs->rfifo);
- }
-}
-
-static void adi_spi_u8_read(struct adi_spi_master *drv_data)
-{
- u32 tx_val = drv_data->cur_chip->tx_dummy_val;
-
- dummy_read(drv_data);
- while (drv_data->rx < drv_data->rx_end) {
- iowrite32(tx_val, &drv_data->regs->tfifo);
- while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
- cpu_relax();
- *(u8 *)(drv_data->rx++) = ioread32(&drv_data->regs->rfifo);
- }
-}
-
-static void adi_spi_u8_duplex(struct adi_spi_master *drv_data)
-{
- dummy_read(drv_data);
- while (drv_data->rx < drv_data->rx_end) {
- iowrite32(*(u8 *)(drv_data->tx++), &drv_data->regs->tfifo);
- while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
- cpu_relax();
- *(u8 *)(drv_data->rx++) = ioread32(&drv_data->regs->rfifo);
- }
-}
-
-static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u8 = {
- .write = adi_spi_u8_write,
- .read = adi_spi_u8_read,
- .duplex = adi_spi_u8_duplex,
-};
-
-static void adi_spi_u16_write(struct adi_spi_master *drv_data)
-{
- dummy_read(drv_data);
- while (drv_data->tx < drv_data->tx_end) {
- iowrite32(*(u16 *)drv_data->tx, &drv_data->regs->tfifo);
- drv_data->tx += 2;
- while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
- cpu_relax();
- ioread32(&drv_data->regs->rfifo);
- }
-}
-
-static void adi_spi_u16_read(struct adi_spi_master *drv_data)
-{
- u32 tx_val = drv_data->cur_chip->tx_dummy_val;
-
- dummy_read(drv_data);
- while (drv_data->rx < drv_data->rx_end) {
- iowrite32(tx_val, &drv_data->regs->tfifo);
- while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
- cpu_relax();
- *(u16 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
- drv_data->rx += 2;
- }
-}
-
-static void adi_spi_u16_duplex(struct adi_spi_master *drv_data)
-{
- dummy_read(drv_data);
- while (drv_data->rx < drv_data->rx_end) {
- iowrite32(*(u16 *)drv_data->tx, &drv_data->regs->tfifo);
- drv_data->tx += 2;
- while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
- cpu_relax();
- *(u16 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
- drv_data->rx += 2;
- }
-}
-
-static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u16 = {
- .write = adi_spi_u16_write,
- .read = adi_spi_u16_read,
- .duplex = adi_spi_u16_duplex,
-};
-
-static void adi_spi_u32_write(struct adi_spi_master *drv_data)
-{
- dummy_read(drv_data);
- while (drv_data->tx < drv_data->tx_end) {
- iowrite32(*(u32 *)drv_data->tx, &drv_data->regs->tfifo);
- drv_data->tx += 4;
- while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
- cpu_relax();
- ioread32(&drv_data->regs->rfifo);
- }
-}
-
-static void adi_spi_u32_read(struct adi_spi_master *drv_data)
-{
- u32 tx_val = drv_data->cur_chip->tx_dummy_val;
-
- dummy_read(drv_data);
- while (drv_data->rx < drv_data->rx_end) {
- iowrite32(tx_val, &drv_data->regs->tfifo);
- while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
- cpu_relax();
- *(u32 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
- drv_data->rx += 4;
- }
-}
-
-static void adi_spi_u32_duplex(struct adi_spi_master *drv_data)
-{
- dummy_read(drv_data);
- while (drv_data->rx < drv_data->rx_end) {
- iowrite32(*(u32 *)drv_data->tx, &drv_data->regs->tfifo);
- drv_data->tx += 4;
- while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE)
- cpu_relax();
- *(u32 *)drv_data->rx = ioread32(&drv_data->regs->rfifo);
- drv_data->rx += 4;
- }
-}
-
-static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u32 = {
- .write = adi_spi_u32_write,
- .read = adi_spi_u32_read,
- .duplex = adi_spi_u32_duplex,
-};
-
-
-/* test if there is more transfer to be done */
-static void adi_spi_next_transfer(struct adi_spi_master *drv)
-{
- struct spi_message *msg = drv->cur_msg;
- struct spi_transfer *t = drv->cur_transfer;
-
- /* Move to next transfer */
- if (t->transfer_list.next != &msg->transfers) {
- drv->cur_transfer = list_entry(t->transfer_list.next,
- struct spi_transfer, transfer_list);
- drv->state = RUNNING_STATE;
- } else {
- drv->state = DONE_STATE;
- drv->cur_transfer = NULL;
- }
-}
-
-static void adi_spi_giveback(struct adi_spi_master *drv_data)
-{
- struct adi_spi_device *chip = drv_data->cur_chip;
-
- adi_spi_cs_deactive(drv_data, chip);
- spi_finalize_current_message(drv_data->master);
-}
-
-static int adi_spi_setup_transfer(struct adi_spi_master *drv)
-{
- struct spi_transfer *t = drv->cur_transfer;
- u32 cr, cr_width;
-
- if (t->tx_buf) {
- drv->tx = (void *)t->tx_buf;
- drv->tx_end = drv->tx + t->len;
- } else {
- drv->tx = NULL;
- }
-
- if (t->rx_buf) {
- drv->rx = t->rx_buf;
- drv->rx_end = drv->rx + t->len;
- } else {
- drv->rx = NULL;
- }
-
- drv->transfer_len = t->len;
-
- /* bits per word setup */
- switch (t->bits_per_word) {
- case 8:
- cr_width = SPI_CTL_SIZE08;
- drv->ops = &adi_spi_transfer_ops_u8;
- break;
- case 16:
- cr_width = SPI_CTL_SIZE16;
- drv->ops = &adi_spi_transfer_ops_u16;
- break;
- case 32:
- cr_width = SPI_CTL_SIZE32;
- drv->ops = &adi_spi_transfer_ops_u32;
- break;
- default:
- return -EINVAL;
- }
- cr = ioread32(&drv->regs->control) & ~SPI_CTL_SIZE;
- cr |= cr_width;
- iowrite32(cr, &drv->regs->control);
-
- /* speed setup */
- iowrite32(hz_to_spi_clock(drv->sclk, t->speed_hz), &drv->regs->clock);
- return 0;
-}
-
-static int adi_spi_dma_xfer(struct adi_spi_master *drv_data)
-{
- struct spi_transfer *t = drv_data->cur_transfer;
- struct spi_message *msg = drv_data->cur_msg;
- struct adi_spi_device *chip = drv_data->cur_chip;
- u32 dma_config;
- unsigned long word_count, word_size;
- void *tx_buf, *rx_buf;
-
- switch (t->bits_per_word) {
- case 8:
- dma_config = WDSIZE_8 | PSIZE_8;
- word_count = drv_data->transfer_len;
- word_size = 1;
- break;
- case 16:
- dma_config = WDSIZE_16 | PSIZE_16;
- word_count = drv_data->transfer_len / 2;
- word_size = 2;
- break;
- default:
- dma_config = WDSIZE_32 | PSIZE_32;
- word_count = drv_data->transfer_len / 4;
- word_size = 4;
- break;
- }
-
- if (!drv_data->rx) {
- tx_buf = drv_data->tx;
- rx_buf = &drv_data->dummy_buffer;
- drv_data->tx_dma_size = drv_data->transfer_len;
- drv_data->rx_dma_size = sizeof(drv_data->dummy_buffer);
- set_dma_x_modify(drv_data->tx_dma, word_size);
- set_dma_x_modify(drv_data->rx_dma, 0);
- } else if (!drv_data->tx) {
- drv_data->dummy_buffer = chip->tx_dummy_val;
- tx_buf = &drv_data->dummy_buffer;
- rx_buf = drv_data->rx;
- drv_data->tx_dma_size = sizeof(drv_data->dummy_buffer);
- drv_data->rx_dma_size = drv_data->transfer_len;
- set_dma_x_modify(drv_data->tx_dma, 0);
- set_dma_x_modify(drv_data->rx_dma, word_size);
- } else {
- tx_buf = drv_data->tx;
- rx_buf = drv_data->rx;
- drv_data->tx_dma_size = drv_data->rx_dma_size
- = drv_data->transfer_len;
- set_dma_x_modify(drv_data->tx_dma, word_size);
- set_dma_x_modify(drv_data->rx_dma, word_size);
- }
-
- drv_data->tx_dma_addr = dma_map_single(&msg->spi->dev,
- (void *)tx_buf,
- drv_data->tx_dma_size,
- DMA_TO_DEVICE);
- if (dma_mapping_error(&msg->spi->dev,
- drv_data->tx_dma_addr))
- return -ENOMEM;
-
- drv_data->rx_dma_addr = dma_map_single(&msg->spi->dev,
- (void *)rx_buf,
- drv_data->rx_dma_size,
- DMA_FROM_DEVICE);
- if (dma_mapping_error(&msg->spi->dev,
- drv_data->rx_dma_addr)) {
- dma_unmap_single(&msg->spi->dev,
- drv_data->tx_dma_addr,
- drv_data->tx_dma_size,
- DMA_TO_DEVICE);
- return -ENOMEM;
- }
-
- dummy_read(drv_data);
- set_dma_x_count(drv_data->tx_dma, word_count);
- set_dma_x_count(drv_data->rx_dma, word_count);
- set_dma_start_addr(drv_data->tx_dma, drv_data->tx_dma_addr);
- set_dma_start_addr(drv_data->rx_dma, drv_data->rx_dma_addr);
- dma_config |= DMAFLOW_STOP | RESTART | DI_EN;
- set_dma_config(drv_data->tx_dma, dma_config);
- set_dma_config(drv_data->rx_dma, dma_config | WNR);
- enable_dma(drv_data->tx_dma);
- enable_dma(drv_data->rx_dma);
-
- iowrite32(SPI_RXCTL_REN | SPI_RXCTL_RDR_NE,
- &drv_data->regs->rx_control);
- iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI | SPI_TXCTL_TDR_NF,
- &drv_data->regs->tx_control);
-
- return 0;
-}
-
-static int adi_spi_pio_xfer(struct adi_spi_master *drv_data)
-{
- struct spi_message *msg = drv_data->cur_msg;
-
- if (!drv_data->rx) {
- /* write only half duplex */
- drv_data->ops->write(drv_data);
- if (drv_data->tx != drv_data->tx_end)
- return -EIO;
- } else if (!drv_data->tx) {
- /* read only half duplex */
- drv_data->ops->read(drv_data);
- if (drv_data->rx != drv_data->rx_end)
- return -EIO;
- } else {
- /* full duplex mode */
- drv_data->ops->duplex(drv_data);
- if (drv_data->tx != drv_data->tx_end)
- return -EIO;
- }
-
- if (!adi_spi_flush(drv_data))
- return -EIO;
- msg->actual_length += drv_data->transfer_len;
- tasklet_schedule(&drv_data->pump_transfers);
- return 0;
-}
-
-static void adi_spi_pump_transfers(unsigned long data)
-{
- struct adi_spi_master *drv_data = (struct adi_spi_master *)data;
- struct spi_message *msg = NULL;
- struct spi_transfer *t = NULL;
- struct adi_spi_device *chip = NULL;
- int ret;
-
- /* Get current state information */
- msg = drv_data->cur_msg;
- t = drv_data->cur_transfer;
- chip = drv_data->cur_chip;
-
- /* Handle for abort */
- if (drv_data->state == ERROR_STATE) {
- msg->status = -EIO;
- adi_spi_giveback(drv_data);
- return;
- }
-
- if (drv_data->state == RUNNING_STATE) {
- if (t->delay_usecs)
- udelay(t->delay_usecs);
- if (t->cs_change)
- adi_spi_cs_deactive(drv_data, chip);
- adi_spi_next_transfer(drv_data);
- t = drv_data->cur_transfer;
- }
- /* Handle end of message */
- if (drv_data->state == DONE_STATE) {
- msg->status = 0;
- adi_spi_giveback(drv_data);
- return;
- }
-
- if ((t->len == 0) || (t->tx_buf == NULL && t->rx_buf == NULL)) {
- /* Schedule next transfer tasklet */
- tasklet_schedule(&drv_data->pump_transfers);
- return;
- }
-
- ret = adi_spi_setup_transfer(drv_data);
- if (ret) {
- msg->status = ret;
- adi_spi_giveback(drv_data);
- }
-
- iowrite32(0xFFFFFFFF, &drv_data->regs->status);
- adi_spi_cs_active(drv_data, chip);
- drv_data->state = RUNNING_STATE;
-
- if (chip->enable_dma)
- ret = adi_spi_dma_xfer(drv_data);
- else
- ret = adi_spi_pio_xfer(drv_data);
- if (ret) {
- msg->status = ret;
- adi_spi_giveback(drv_data);
- }
-}
-
-static int adi_spi_transfer_one_message(struct spi_master *master,
- struct spi_message *m)
-{
- struct adi_spi_master *drv_data = spi_master_get_devdata(master);
-
- drv_data->cur_msg = m;
- drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
- adi_spi_restore_state(drv_data);
-
- drv_data->state = START_STATE;
- drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
- struct spi_transfer, transfer_list);
-
- tasklet_schedule(&drv_data->pump_transfers);
- return 0;
-}
-
-#define MAX_SPI_SSEL 7
-
-static const u16 ssel[][MAX_SPI_SSEL] = {
- {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
- P_SPI0_SSEL4, P_SPI0_SSEL5,
- P_SPI0_SSEL6, P_SPI0_SSEL7},
-
- {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
- P_SPI1_SSEL4, P_SPI1_SSEL5,
- P_SPI1_SSEL6, P_SPI1_SSEL7},
-
- {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
- P_SPI2_SSEL4, P_SPI2_SSEL5,
- P_SPI2_SSEL6, P_SPI2_SSEL7},
-};
-
-static int adi_spi_setup(struct spi_device *spi)
-{
- struct adi_spi_master *drv_data = spi_master_get_devdata(spi->master);
- struct adi_spi_device *chip = spi_get_ctldata(spi);
- u32 ctl_reg = SPI_CTL_ODM | SPI_CTL_PSSE;
- int ret = -EINVAL;
-
- if (!chip) {
- struct adi_spi3_chip *chip_info = spi->controller_data;
-
- chip = kzalloc(sizeof(*chip), GFP_KERNEL);
- if (!chip)
- return -ENOMEM;
-
- if (chip_info) {
- if (chip_info->control & ~ctl_reg) {
- dev_err(&spi->dev,
- "do not set bits that the SPI framework manages\n");
- goto error;
- }
- chip->control = chip_info->control;
- chip->cs_chg_udelay = chip_info->cs_chg_udelay;
- chip->tx_dummy_val = chip_info->tx_dummy_val;
- chip->enable_dma = chip_info->enable_dma;
- }
- chip->cs = spi->chip_select;
-
- if (chip->cs < MAX_CTRL_CS) {
- chip->ssel = (1 << chip->cs) << 8;
- ret = peripheral_request(ssel[spi->master->bus_num]
- [chip->cs-1], dev_name(&spi->dev));
- if (ret) {
- dev_err(&spi->dev, "peripheral_request() error\n");
- goto error;
- }
- } else {
- chip->cs_gpio = chip->cs - MAX_CTRL_CS;
- ret = gpio_request_one(chip->cs_gpio, GPIOF_OUT_INIT_HIGH,
- dev_name(&spi->dev));
- if (ret) {
- dev_err(&spi->dev, "gpio_request_one() error\n");
- goto error;
- }
- }
- spi_set_ctldata(spi, chip);
- }
-
- /* force a default base state */
- chip->control &= ctl_reg;
-
- if (spi->mode & SPI_CPOL)
- chip->control |= SPI_CTL_CPOL;
- if (spi->mode & SPI_CPHA)
- chip->control |= SPI_CTL_CPHA;
- if (spi->mode & SPI_LSB_FIRST)
- chip->control |= SPI_CTL_LSBF;
- chip->control |= SPI_CTL_MSTR;
- /* we choose software to controll cs */
- chip->control &= ~SPI_CTL_ASSEL;
-
- chip->clock = hz_to_spi_clock(drv_data->sclk, spi->max_speed_hz);
-
- adi_spi_cs_enable(drv_data, chip);
- adi_spi_cs_deactive(drv_data, chip);
-
- return 0;
-error:
- if (chip) {
- kfree(chip);
- spi_set_ctldata(spi, NULL);
- }
-
- return ret;
-}
-
-static void adi_spi_cleanup(struct spi_device *spi)
-{
- struct adi_spi_device *chip = spi_get_ctldata(spi);
- struct adi_spi_master *drv_data = spi_master_get_devdata(spi->master);
-
- if (!chip)
- return;
-
- if (chip->cs < MAX_CTRL_CS) {
- peripheral_free(ssel[spi->master->bus_num]
- [chip->cs-1]);
- adi_spi_cs_disable(drv_data, chip);
- } else {
- gpio_free(chip->cs_gpio);
- }
-
- kfree(chip);
- spi_set_ctldata(spi, NULL);
-}
-
-static irqreturn_t adi_spi_tx_dma_isr(int irq, void *dev_id)
-{
- struct adi_spi_master *drv_data = dev_id;
- u32 dma_stat = get_dma_curr_irqstat(drv_data->tx_dma);
- u32 tx_ctl;
-
- clear_dma_irqstat(drv_data->tx_dma);
- if (dma_stat & DMA_DONE) {
- drv_data->tx_num++;
- } else {
- dev_err(&drv_data->master->dev,
- "spi tx dma error: %d\n", dma_stat);
- if (drv_data->tx)
- drv_data->state = ERROR_STATE;
- }
- tx_ctl = ioread32(&drv_data->regs->tx_control);
- tx_ctl &= ~SPI_TXCTL_TDR_NF;
- iowrite32(tx_ctl, &drv_data->regs->tx_control);
- return IRQ_HANDLED;
-}
-
-static irqreturn_t adi_spi_rx_dma_isr(int irq, void *dev_id)
-{
- struct adi_spi_master *drv_data = dev_id;
- struct spi_message *msg = drv_data->cur_msg;
- u32 dma_stat = get_dma_curr_irqstat(drv_data->rx_dma);
-
- clear_dma_irqstat(drv_data->rx_dma);
- if (dma_stat & DMA_DONE) {
- drv_data->rx_num++;
- /* we may fail on tx dma */
- if (drv_data->state != ERROR_STATE)
- msg->actual_length += drv_data->transfer_len;
- } else {
- drv_data->state = ERROR_STATE;
- dev_err(&drv_data->master->dev,
- "spi rx dma error: %d\n", dma_stat);
- }
- iowrite32(0, &drv_data->regs->tx_control);
- iowrite32(0, &drv_data->regs->rx_control);
- if (drv_data->rx_num != drv_data->tx_num)
- dev_dbg(&drv_data->master->dev,
- "dma interrupt missing: tx=%d,rx=%d\n",
- drv_data->tx_num, drv_data->rx_num);
- tasklet_schedule(&drv_data->pump_transfers);
- return IRQ_HANDLED;
-}
-
-static int adi_spi_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct adi_spi3_master *info = dev_get_platdata(dev);
- struct spi_master *master;
- struct adi_spi_master *drv_data;
- struct resource *mem, *res;
- unsigned int tx_dma, rx_dma;
- struct clk *sclk;
- int ret;
-
- if (!info) {
- dev_err(dev, "platform data missing!\n");
- return -ENODEV;
- }
-
- sclk = devm_clk_get(dev, "spi");
- if (IS_ERR(sclk)) {
- dev_err(dev, "can not get spi clock\n");
- return PTR_ERR(sclk);
- }
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (!res) {
- dev_err(dev, "can not get tx dma resource\n");
- return -ENXIO;
- }
- tx_dma = res->start;
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
- if (!res) {
- dev_err(dev, "can not get rx dma resource\n");
- return -ENXIO;
- }
- rx_dma = res->start;
-
- /* allocate master with space for drv_data */
- master = spi_alloc_master(dev, sizeof(*drv_data));
- if (!master) {
- dev_err(dev, "can not alloc spi_master\n");
- return -ENOMEM;
- }
- platform_set_drvdata(pdev, master);
-
- /* the mode bits supported by this driver */
- master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
-
- master->bus_num = pdev->id;
- master->num_chipselect = info->num_chipselect;
- master->cleanup = adi_spi_cleanup;
- master->setup = adi_spi_setup;
- master->transfer_one_message = adi_spi_transfer_one_message;
- master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
- SPI_BPW_MASK(8);
-
- drv_data = spi_master_get_devdata(master);
- drv_data->master = master;
- drv_data->tx_dma = tx_dma;
- drv_data->rx_dma = rx_dma;
- drv_data->pin_req = info->pin_req;
- drv_data->sclk = clk_get_rate(sclk);
-
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- drv_data->regs = devm_ioremap_resource(dev, mem);
- if (IS_ERR(drv_data->regs)) {
- ret = PTR_ERR(drv_data->regs);
- goto err_put_master;
- }
-
- /* request tx and rx dma */
- ret = request_dma(tx_dma, "SPI_TX_DMA");
- if (ret) {
- dev_err(dev, "can not request SPI TX DMA channel\n");
- goto err_put_master;
- }
- set_dma_callback(tx_dma, adi_spi_tx_dma_isr, drv_data);
-
- ret = request_dma(rx_dma, "SPI_RX_DMA");
- if (ret) {
- dev_err(dev, "can not request SPI RX DMA channel\n");
- goto err_free_tx_dma;
- }
- set_dma_callback(drv_data->rx_dma, adi_spi_rx_dma_isr, drv_data);
-
- /* request CLK, MOSI and MISO */
- ret = peripheral_request_list(drv_data->pin_req, "adi-spi3");
- if (ret < 0) {
- dev_err(dev, "can not request spi pins\n");
- goto err_free_rx_dma;
- }
-
- iowrite32(SPI_CTL_MSTR | SPI_CTL_CPHA, &drv_data->regs->control);
- iowrite32(0x0000FE00, &drv_data->regs->ssel);
- iowrite32(0x0, &drv_data->regs->delay);
-
- tasklet_init(&drv_data->pump_transfers,
- adi_spi_pump_transfers, (unsigned long)drv_data);
- /* register with the SPI framework */
- ret = devm_spi_register_master(dev, master);
- if (ret) {
- dev_err(dev, "can not register spi master\n");
- goto err_free_peripheral;
- }
-
- return ret;
-
-err_free_peripheral:
- peripheral_free_list(drv_data->pin_req);
-err_free_rx_dma:
- free_dma(rx_dma);
-err_free_tx_dma:
- free_dma(tx_dma);
-err_put_master:
- spi_master_put(master);
-
- return ret;
-}
-
-static int adi_spi_remove(struct platform_device *pdev)
-{
- struct spi_master *master = platform_get_drvdata(pdev);
- struct adi_spi_master *drv_data = spi_master_get_devdata(master);
-
- adi_spi_disable(drv_data);
- peripheral_free_list(drv_data->pin_req);
- free_dma(drv_data->rx_dma);
- free_dma(drv_data->tx_dma);
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int adi_spi_suspend(struct device *dev)
-{
- struct spi_master *master = dev_get_drvdata(dev);
- struct adi_spi_master *drv_data = spi_master_get_devdata(master);
-
- spi_master_suspend(master);
-
- drv_data->control = ioread32(&drv_data->regs->control);
- drv_data->ssel = ioread32(&drv_data->regs->ssel);
-
- iowrite32(SPI_CTL_MSTR | SPI_CTL_CPHA, &drv_data->regs->control);
- iowrite32(0x0000FE00, &drv_data->regs->ssel);
- dma_disable_irq(drv_data->rx_dma);
- dma_disable_irq(drv_data->tx_dma);
-
- return 0;
-}
-
-static int adi_spi_resume(struct device *dev)
-{
- struct spi_master *master = dev_get_drvdata(dev);
- struct adi_spi_master *drv_data = spi_master_get_devdata(master);
- int ret = 0;
-
- /* bootrom may modify spi and dma status when resume in spi boot mode */
- disable_dma(drv_data->rx_dma);
-
- dma_enable_irq(drv_data->rx_dma);
- dma_enable_irq(drv_data->tx_dma);
- iowrite32(drv_data->control, &drv_data->regs->control);
- iowrite32(drv_data->ssel, &drv_data->regs->ssel);
-
- ret = spi_master_resume(master);
- if (ret) {
- free_dma(drv_data->rx_dma);
- free_dma(drv_data->tx_dma);
- }
-
- return ret;
-}
-#endif
-static const struct dev_pm_ops adi_spi_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(adi_spi_suspend, adi_spi_resume)
-};
-
-MODULE_ALIAS("platform:adi-spi3");
-static struct platform_driver adi_spi_driver = {
- .driver = {
- .name = "adi-spi3",
- .pm = &adi_spi_pm_ops,
- },
- .remove = adi_spi_remove,
-};
-
-module_platform_driver_probe(adi_spi_driver, adi_spi_probe);
-
-MODULE_DESCRIPTION("Analog Devices SPI3 controller driver");
-MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-bfin-sport.c b/drivers/spi/spi-bfin-sport.c
deleted file mode 100644
index 01d0ba9..0000000
--- a/drivers/spi/spi-bfin-sport.c
+++ /dev/null
@@ -1,919 +0,0 @@
-/*
- * SPI bus via the Blackfin SPORT peripheral
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright 2009-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/irq.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/workqueue.h>
-
-#include <asm/portmux.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/blackfin.h>
-#include <asm/bfin_sport.h>
-#include <asm/cacheflush.h>
-
-#define DRV_NAME "bfin-sport-spi"
-#define DRV_DESC "SPI bus via the Blackfin SPORT"
-
-MODULE_AUTHOR("Cliff Cai");
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:bfin-sport-spi");
-
-enum bfin_sport_spi_state {
- START_STATE,
- RUNNING_STATE,
- DONE_STATE,
- ERROR_STATE,
-};
-
-struct bfin_sport_spi_master_data;
-
-struct bfin_sport_transfer_ops {
- void (*write) (struct bfin_sport_spi_master_data *);
- void (*read) (struct bfin_sport_spi_master_data *);
- void (*duplex) (struct bfin_sport_spi_master_data *);
-};
-
-struct bfin_sport_spi_master_data {
- /* Driver model hookup */
- struct device *dev;
-
- /* SPI framework hookup */
- struct spi_master *master;
-
- /* Regs base of SPI controller */
- struct sport_register __iomem *regs;
- int err_irq;
-
- /* Pin request list */
- u16 *pin_req;
-
- struct work_struct pump_messages;
- spinlock_t lock;
- struct list_head queue;
- int busy;
- bool run;
-
- /* Message Transfer pump */
- struct tasklet_struct pump_transfers;
-
- /* Current message transfer state info */
- enum bfin_sport_spi_state state;
- struct spi_message *cur_msg;
- struct spi_transfer *cur_transfer;
- struct bfin_sport_spi_slave_data *cur_chip;
- union {
- void *tx;
- u8 *tx8;
- u16 *tx16;
- };
- void *tx_end;
- union {
- void *rx;
- u8 *rx8;
- u16 *rx16;
- };
- void *rx_end;
-
- int cs_change;
- struct bfin_sport_transfer_ops *ops;
-};
-
-struct bfin_sport_spi_slave_data {
- u16 ctl_reg;
- u16 baud;
- u16 cs_chg_udelay; /* Some devices require > 255usec delay */
- u32 cs_gpio;
- u16 idle_tx_val;
- struct bfin_sport_transfer_ops *ops;
-};
-
-static void
-bfin_sport_spi_enable(struct bfin_sport_spi_master_data *drv_data)
-{
- bfin_write_or(&drv_data->regs->tcr1, TSPEN);
- bfin_write_or(&drv_data->regs->rcr1, TSPEN);
- SSYNC();
-}
-
-static void
-bfin_sport_spi_disable(struct bfin_sport_spi_master_data *drv_data)
-{
- bfin_write_and(&drv_data->regs->tcr1, ~TSPEN);
- bfin_write_and(&drv_data->regs->rcr1, ~TSPEN);
- SSYNC();
-}
-
-/* Caculate the SPI_BAUD register value based on input HZ */
-static u16
-bfin_sport_hz_to_spi_baud(u32 speed_hz)
-{
- u_long clk, sclk = get_sclk();
- int div = (sclk / (2 * speed_hz)) - 1;
-
- if (div < 0)
- div = 0;
-
- clk = sclk / (2 * (div + 1));
-
- if (clk > speed_hz)
- div++;
-
- return div;
-}
-
-/* Chip select operation functions for cs_change flag */
-static void
-bfin_sport_spi_cs_active(struct bfin_sport_spi_slave_data *chip)
-{
- gpio_direction_output(chip->cs_gpio, 0);
-}
-
-static void
-bfin_sport_spi_cs_deactive(struct bfin_sport_spi_slave_data *chip)
-{
- gpio_direction_output(chip->cs_gpio, 1);
- /* Move delay here for consistency */
- if (chip->cs_chg_udelay)
- udelay(chip->cs_chg_udelay);
-}
-
-static void
-bfin_sport_spi_stat_poll_complete(struct bfin_sport_spi_master_data *drv_data)
-{
- unsigned long timeout = jiffies + HZ;
- while (!(bfin_read(&drv_data->regs->stat) & RXNE)) {
- if (!time_before(jiffies, timeout))
- break;
- }
-}
-
-static void
-bfin_sport_spi_u8_writer(struct bfin_sport_spi_master_data *drv_data)
-{
- u16 dummy;
-
- while (drv_data->tx < drv_data->tx_end) {
- bfin_write(&drv_data->regs->tx16, *drv_data->tx8++);
- bfin_sport_spi_stat_poll_complete(drv_data);
- dummy = bfin_read(&drv_data->regs->rx16);
- }
-}
-
-static void
-bfin_sport_spi_u8_reader(struct bfin_sport_spi_master_data *drv_data)
-{
- u16 tx_val = drv_data->cur_chip->idle_tx_val;
-
- while (drv_data->rx < drv_data->rx_end) {
- bfin_write(&drv_data->regs->tx16, tx_val);
- bfin_sport_spi_stat_poll_complete(drv_data);
- *drv_data->rx8++ = bfin_read(&drv_data->regs->rx16);
- }
-}
-
-static void
-bfin_sport_spi_u8_duplex(struct bfin_sport_spi_master_data *drv_data)
-{
- while (drv_data->rx < drv_data->rx_end) {
- bfin_write(&drv_data->regs->tx16, *drv_data->tx8++);
- bfin_sport_spi_stat_poll_complete(drv_data);
- *drv_data->rx8++ = bfin_read(&drv_data->regs->rx16);
- }
-}
-
-static struct bfin_sport_transfer_ops bfin_sport_transfer_ops_u8 = {
- .write = bfin_sport_spi_u8_writer,
- .read = bfin_sport_spi_u8_reader,
- .duplex = bfin_sport_spi_u8_duplex,
-};
-
-static void
-bfin_sport_spi_u16_writer(struct bfin_sport_spi_master_data *drv_data)
-{
- u16 dummy;
-
- while (drv_data->tx < drv_data->tx_end) {
- bfin_write(&drv_data->regs->tx16, *drv_data->tx16++);
- bfin_sport_spi_stat_poll_complete(drv_data);
- dummy = bfin_read(&drv_data->regs->rx16);
- }
-}
-
-static void
-bfin_sport_spi_u16_reader(struct bfin_sport_spi_master_data *drv_data)
-{
- u16 tx_val = drv_data->cur_chip->idle_tx_val;
-
- while (drv_data->rx < drv_data->rx_end) {
- bfin_write(&drv_data->regs->tx16, tx_val);
- bfin_sport_spi_stat_poll_complete(drv_data);
- *drv_data->rx16++ = bfin_read(&drv_data->regs->rx16);
- }
-}
-
-static void
-bfin_sport_spi_u16_duplex(struct bfin_sport_spi_master_data *drv_data)
-{
- while (drv_data->rx < drv_data->rx_end) {
- bfin_write(&drv_data->regs->tx16, *drv_data->tx16++);
- bfin_sport_spi_stat_poll_complete(drv_data);
- *drv_data->rx16++ = bfin_read(&drv_data->regs->rx16);
- }
-}
-
-static struct bfin_sport_transfer_ops bfin_sport_transfer_ops_u16 = {
- .write = bfin_sport_spi_u16_writer,
- .read = bfin_sport_spi_u16_reader,
- .duplex = bfin_sport_spi_u16_duplex,
-};
-
-/* stop controller and re-config current chip */
-static void
-bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data *drv_data)
-{
- struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip;
-
- bfin_sport_spi_disable(drv_data);
- dev_dbg(drv_data->dev, "restoring spi ctl state\n");
-
- bfin_write(&drv_data->regs->tcr1, chip->ctl_reg);
- bfin_write(&drv_data->regs->tclkdiv, chip->baud);
- SSYNC();
-
- bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS));
- SSYNC();
-
- bfin_sport_spi_cs_active(chip);
-}
-
-/* test if there is more transfer to be done */
-static enum bfin_sport_spi_state
-bfin_sport_spi_next_transfer(struct bfin_sport_spi_master_data *drv_data)
-{
- struct spi_message *msg = drv_data->cur_msg;
- struct spi_transfer *trans = drv_data->cur_transfer;
-
- /* Move to next transfer */
- if (trans->transfer_list.next != &msg->transfers) {
- drv_data->cur_transfer =
- list_entry(trans->transfer_list.next,
- struct spi_transfer, transfer_list);
- return RUNNING_STATE;
- }
-
- return DONE_STATE;
-}
-
-/*
- * caller already set message->status;
- * dma and pio irqs are blocked give finished message back
- */
-static void
-bfin_sport_spi_giveback(struct bfin_sport_spi_master_data *drv_data)
-{
- struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip;
- unsigned long flags;
- struct spi_message *msg;
-
- spin_lock_irqsave(&drv_data->lock, flags);
- msg = drv_data->cur_msg;
- drv_data->state = START_STATE;
- drv_data->cur_msg = NULL;
- drv_data->cur_transfer = NULL;
- drv_data->cur_chip = NULL;
- schedule_work(&drv_data->pump_messages);
- spin_unlock_irqrestore(&drv_data->lock, flags);
-
- if (!drv_data->cs_change)
- bfin_sport_spi_cs_deactive(chip);
-
- if (msg->complete)
- msg->complete(msg->context);
-}
-
-static irqreturn_t
-sport_err_handler(int irq, void *dev_id)
-{
- struct bfin_sport_spi_master_data *drv_data = dev_id;
- u16 status;
-
- dev_dbg(drv_data->dev, "%s enter\n", __func__);
- status = bfin_read(&drv_data->regs->stat) & (TOVF | TUVF | ROVF | RUVF);
-
- if (status) {
- bfin_write(&drv_data->regs->stat, status);
- SSYNC();
-
- bfin_sport_spi_disable(drv_data);
- dev_err(drv_data->dev, "status error:%s%s%s%s\n",
- status & TOVF ? " TOVF" : "",
- status & TUVF ? " TUVF" : "",
- status & ROVF ? " ROVF" : "",
- status & RUVF ? " RUVF" : "");
- }
-
- return IRQ_HANDLED;
-}
-
-static void
-bfin_sport_spi_pump_transfers(unsigned long data)
-{
- struct bfin_sport_spi_master_data *drv_data = (void *)data;
- struct spi_message *message = NULL;
- struct spi_transfer *transfer = NULL;
- struct spi_transfer *previous = NULL;
- struct bfin_sport_spi_slave_data *chip = NULL;
- unsigned int bits_per_word;
- u32 tranf_success = 1;
- u32 transfer_speed;
- u8 full_duplex = 0;
-
- /* Get current state information */
- message = drv_data->cur_msg;
- transfer = drv_data->cur_transfer;
- chip = drv_data->cur_chip;
-
- transfer_speed = bfin_sport_hz_to_spi_baud(transfer->speed_hz);
- bfin_write(&drv_data->regs->tclkdiv, transfer_speed);
- SSYNC();
-
- /*
- * if msg is error or done, report it back using complete() callback
- */
-
- /* Handle for abort */
- if (drv_data->state == ERROR_STATE) {
- dev_dbg(drv_data->dev, "transfer: we've hit an error\n");
- message->status = -EIO;
- bfin_sport_spi_giveback(drv_data);
- return;
- }
-
- /* Handle end of message */
- if (drv_data->state == DONE_STATE) {
- dev_dbg(drv_data->dev, "transfer: all done!\n");
- message->status = 0;
- bfin_sport_spi_giveback(drv_data);
- return;
- }
-
- /* Delay if requested at end of transfer */
- if (drv_data->state == RUNNING_STATE) {
- dev_dbg(drv_data->dev, "transfer: still running ...\n");
- previous = list_entry(transfer->transfer_list.prev,
- struct spi_transfer, transfer_list);
- if (previous->delay_usecs)
- udelay(previous->delay_usecs);
- }
-
- if (transfer->len == 0) {
- /* Move to next transfer of this msg */
- drv_data->state = bfin_sport_spi_next_transfer(drv_data);
- /* Schedule next transfer tasklet */
- tasklet_schedule(&drv_data->pump_transfers);
- }
-
- if (transfer->tx_buf != NULL) {
- drv_data->tx = (void *)transfer->tx_buf;
- drv_data->tx_end = drv_data->tx + transfer->len;
- dev_dbg(drv_data->dev, "tx_buf is %p, tx_end is %p\n",
- transfer->tx_buf, drv_data->tx_end);
- } else
- drv_data->tx = NULL;
-
- if (transfer->rx_buf != NULL) {
- full_duplex = transfer->tx_buf != NULL;
- drv_data->rx = transfer->rx_buf;
- drv_data->rx_end = drv_data->rx + transfer->len;
- dev_dbg(drv_data->dev, "rx_buf is %p, rx_end is %p\n",
- transfer->rx_buf, drv_data->rx_end);
- } else
- drv_data->rx = NULL;
-
- drv_data->cs_change = transfer->cs_change;
-
- /* Bits per word setup */
- bits_per_word = transfer->bits_per_word;
- if (bits_per_word == 16)
- drv_data->ops = &bfin_sport_transfer_ops_u16;
- else
- drv_data->ops = &bfin_sport_transfer_ops_u8;
- bfin_write(&drv_data->regs->tcr2, bits_per_word - 1);
- bfin_write(&drv_data->regs->tfsdiv, bits_per_word - 1);
- bfin_write(&drv_data->regs->rcr2, bits_per_word - 1);
-
- drv_data->state = RUNNING_STATE;
-
- if (drv_data->cs_change)
- bfin_sport_spi_cs_active(chip);
-
- dev_dbg(drv_data->dev,
- "now pumping a transfer: width is %d, len is %d\n",
- bits_per_word, transfer->len);
-
- /* PIO mode write then read */
- dev_dbg(drv_data->dev, "doing IO transfer\n");
-
- bfin_sport_spi_enable(drv_data);
- if (full_duplex) {
- /* full duplex mode */
- BUG_ON((drv_data->tx_end - drv_data->tx) !=
- (drv_data->rx_end - drv_data->rx));
- drv_data->ops->duplex(drv_data);
-
- if (drv_data->tx != drv_data->tx_end)
- tranf_success = 0;
- } else if (drv_data->tx != NULL) {
- /* write only half duplex */
-
- drv_data->ops->write(drv_data);
-
- if (drv_data->tx != drv_data->tx_end)
- tranf_success = 0;
- } else if (drv_data->rx != NULL) {
- /* read only half duplex */
-
- drv_data->ops->read(drv_data);
- if (drv_data->rx != drv_data->rx_end)
- tranf_success = 0;
- }
- bfin_sport_spi_disable(drv_data);
-
- if (!tranf_success) {
- dev_dbg(drv_data->dev, "IO write error!\n");
- drv_data->state = ERROR_STATE;
- } else {
- /* Update total byte transferred */
- message->actual_length += transfer->len;
- /* Move to next transfer of this msg */
- drv_data->state = bfin_sport_spi_next_transfer(drv_data);
- if (drv_data->cs_change)
- bfin_sport_spi_cs_deactive(chip);
- }
-
- /* Schedule next transfer tasklet */
- tasklet_schedule(&drv_data->pump_transfers);
-}
-
-/* pop a msg from queue and kick off real transfer */
-static void
-bfin_sport_spi_pump_messages(struct work_struct *work)
-{
- struct bfin_sport_spi_master_data *drv_data;
- unsigned long flags;
- struct spi_message *next_msg;
-
- drv_data = container_of(work, struct bfin_sport_spi_master_data, pump_messages);
-
- /* Lock queue and check for queue work */
- spin_lock_irqsave(&drv_data->lock, flags);
- if (list_empty(&drv_data->queue) || !drv_data->run) {
- /* pumper kicked off but no work to do */
- drv_data->busy = 0;
- spin_unlock_irqrestore(&drv_data->lock, flags);
- return;
- }
-
- /* Make sure we are not already running a message */
- if (drv_data->cur_msg) {
- spin_unlock_irqrestore(&drv_data->lock, flags);
- return;
- }
-
- /* Extract head of queue */
- next_msg = list_entry(drv_data->queue.next,
- struct spi_message, queue);
-
- drv_data->cur_msg = next_msg;
-
- /* Setup the SSP using the per chip configuration */
- drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
-
- list_del_init(&drv_data->cur_msg->queue);
-
- /* Initialize message state */
- drv_data->cur_msg->state = START_STATE;
- drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
- struct spi_transfer, transfer_list);
- bfin_sport_spi_restore_state(drv_data);
- dev_dbg(drv_data->dev, "got a message to pump, "
- "state is set to: baud %d, cs_gpio %i, ctl 0x%x\n",
- drv_data->cur_chip->baud, drv_data->cur_chip->cs_gpio,
- drv_data->cur_chip->ctl_reg);
-
- dev_dbg(drv_data->dev,
- "the first transfer len is %d\n",
- drv_data->cur_transfer->len);
-
- /* Mark as busy and launch transfers */
- tasklet_schedule(&drv_data->pump_transfers);
-
- drv_data->busy = 1;
- spin_unlock_irqrestore(&drv_data->lock, flags);
-}
-
-/*
- * got a msg to transfer, queue it in drv_data->queue.
- * And kick off message pumper
- */
-static int
-bfin_sport_spi_transfer(struct spi_device *spi, struct spi_message *msg)
-{
- struct bfin_sport_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
- unsigned long flags;
-
- spin_lock_irqsave(&drv_data->lock, flags);
-
- if (!drv_data->run) {
- spin_unlock_irqrestore(&drv_data->lock, flags);
- return -ESHUTDOWN;
- }
-
- msg->actual_length = 0;
- msg->status = -EINPROGRESS;
- msg->state = START_STATE;
-
- dev_dbg(&spi->dev, "adding an msg in transfer()\n");
- list_add_tail(&msg->queue, &drv_data->queue);
-
- if (drv_data->run && !drv_data->busy)
- schedule_work(&drv_data->pump_messages);
-
- spin_unlock_irqrestore(&drv_data->lock, flags);
-
- return 0;
-}
-
-/* Called every time common spi devices change state */
-static int
-bfin_sport_spi_setup(struct spi_device *spi)
-{
- struct bfin_sport_spi_slave_data *chip, *first = NULL;
- int ret;
-
- /* Only alloc (or use chip_info) on first setup */
- chip = spi_get_ctldata(spi);
- if (chip == NULL) {
- struct bfin5xx_spi_chip *chip_info;
-
- chip = first = kzalloc(sizeof(*chip), GFP_KERNEL);
- if (!chip)
- return -ENOMEM;
-
- /* platform chip_info isn't required */
- chip_info = spi->controller_data;
- if (chip_info) {
- /*
- * DITFS and TDTYPE are only thing we don't set, but
- * they probably shouldn't be changed by people.
- */
- if (chip_info->ctl_reg || chip_info->enable_dma) {
- ret = -EINVAL;
- dev_err(&spi->dev, "don't set ctl_reg/enable_dma fields\n");
- goto error;
- }
- chip->cs_chg_udelay = chip_info->cs_chg_udelay;
- chip->idle_tx_val = chip_info->idle_tx_val;
- }
- }
-
- /* translate common spi framework into our register
- * following configure contents are same for tx and rx.
- */
-
- if (spi->mode & SPI_CPHA)
- chip->ctl_reg &= ~TCKFE;
- else
- chip->ctl_reg |= TCKFE;
-
- if (spi->mode & SPI_LSB_FIRST)
- chip->ctl_reg |= TLSBIT;
- else
- chip->ctl_reg &= ~TLSBIT;
-
- /* Sport in master mode */
- chip->ctl_reg |= ITCLK | ITFS | TFSR | LATFS | LTFS;
-
- chip->baud = bfin_sport_hz_to_spi_baud(spi->max_speed_hz);
-
- chip->cs_gpio = spi->chip_select;
- ret = gpio_request(chip->cs_gpio, spi->modalias);
- if (ret)
- goto error;
-
- dev_dbg(&spi->dev, "setup spi chip %s, width is %d\n",
- spi->modalias, spi->bits_per_word);
- dev_dbg(&spi->dev, "ctl_reg is 0x%x, GPIO is %i\n",
- chip->ctl_reg, spi->chip_select);
-
- spi_set_ctldata(spi, chip);
-
- bfin_sport_spi_cs_deactive(chip);
-
- return ret;
-
- error:
- kfree(first);
- return ret;
-}
-
-/*
- * callback for spi framework.
- * clean driver specific data
- */
-static void
-bfin_sport_spi_cleanup(struct spi_device *spi)
-{
- struct bfin_sport_spi_slave_data *chip = spi_get_ctldata(spi);
-
- if (!chip)
- return;
-
- gpio_free(chip->cs_gpio);
-
- kfree(chip);
-}
-
-static int
-bfin_sport_spi_init_queue(struct bfin_sport_spi_master_data *drv_data)
-{
- INIT_LIST_HEAD(&drv_data->queue);
- spin_lock_init(&drv_data->lock);
-
- drv_data->run = false;
- drv_data->busy = 0;
-
- /* init transfer tasklet */
- tasklet_init(&drv_data->pump_transfers,
- bfin_sport_spi_pump_transfers, (unsigned long)drv_data);
-
- INIT_WORK(&drv_data->pump_messages, bfin_sport_spi_pump_messages);
-
- return 0;
-}
-
-static int
-bfin_sport_spi_start_queue(struct bfin_sport_spi_master_data *drv_data)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&drv_data->lock, flags);
-
- if (drv_data->run || drv_data->busy) {
- spin_unlock_irqrestore(&drv_data->lock, flags);
- return -EBUSY;
- }
-
- drv_data->run = true;
- drv_data->cur_msg = NULL;
- drv_data->cur_transfer = NULL;
- drv_data->cur_chip = NULL;
- spin_unlock_irqrestore(&drv_data->lock, flags);
-
- schedule_work(&drv_data->pump_messages);
-
- return 0;
-}
-
-static inline int
-bfin_sport_spi_stop_queue(struct bfin_sport_spi_master_data *drv_data)
-{
- unsigned long flags;
- unsigned limit = 500;
- int status = 0;
-
- spin_lock_irqsave(&drv_data->lock, flags);
-
- /*
- * This is a bit lame, but is optimized for the common execution path.
- * A wait_queue on the drv_data->busy could be used, but then the common
- * execution path (pump_messages) would be required to call wake_up or
- * friends on every SPI message. Do this instead
- */
- drv_data->run = false;
- while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
- spin_unlock_irqrestore(&drv_data->lock, flags);
- msleep(10);
- spin_lock_irqsave(&drv_data->lock, flags);
- }
-
- if (!list_empty(&drv_data->queue) || drv_data->busy)
- status = -EBUSY;
-
- spin_unlock_irqrestore(&drv_data->lock, flags);
-
- return status;
-}
-
-static inline int
-bfin_sport_spi_destroy_queue(struct bfin_sport_spi_master_data *drv_data)
-{
- int status;
-
- status = bfin_sport_spi_stop_queue(drv_data);
- if (status)
- return status;
-
- flush_work(&drv_data->pump_messages);
-
- return 0;
-}
-
-static int bfin_sport_spi_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct bfin5xx_spi_master *platform_info;
- struct spi_master *master;
- struct resource *res, *ires;
- struct bfin_sport_spi_master_data *drv_data;
- int status;
-
- platform_info = dev_get_platdata(dev);
-
- /* Allocate master with space for drv_data */
- master = spi_alloc_master(dev, sizeof(*master) + 16);
- if (!master) {
- dev_err(dev, "cannot alloc spi_master\n");
- return -ENOMEM;
- }
-
- drv_data = spi_master_get_devdata(master);
- drv_data->master = master;
- drv_data->dev = dev;
- drv_data->pin_req = platform_info->pin_req;
-
- master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
- master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
- master->bus_num = pdev->id;
- master->num_chipselect = platform_info->num_chipselect;
- master->cleanup = bfin_sport_spi_cleanup;
- master->setup = bfin_sport_spi_setup;
- master->transfer = bfin_sport_spi_transfer;
-
- /* Find and map our resources */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL) {
- dev_err(dev, "cannot get IORESOURCE_MEM\n");
- status = -ENOENT;
- goto out_error_get_res;
- }
-
- drv_data->regs = ioremap(res->start, resource_size(res));
- if (drv_data->regs == NULL) {
- dev_err(dev, "cannot map registers\n");
- status = -ENXIO;
- goto out_error_ioremap;
- }
-
- ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!ires) {
- dev_err(dev, "cannot get IORESOURCE_IRQ\n");
- status = -ENODEV;
- goto out_error_get_ires;
- }
- drv_data->err_irq = ires->start;
-
- /* Initial and start queue */
- status = bfin_sport_spi_init_queue(drv_data);
- if (status) {
- dev_err(dev, "problem initializing queue\n");
- goto out_error_queue_alloc;
- }
-
- status = bfin_sport_spi_start_queue(drv_data);
- if (status) {
- dev_err(dev, "problem starting queue\n");
- goto out_error_queue_alloc;
- }
-
- status = request_irq(drv_data->err_irq, sport_err_handler,
- 0, "sport_spi_err", drv_data);
- if (status) {
- dev_err(dev, "unable to request sport err irq\n");
- goto out_error_irq;
- }
-
- status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
- if (status) {
- dev_err(dev, "requesting peripherals failed\n");
- goto out_error_peripheral;
- }
-
- /* Register with the SPI framework */
- platform_set_drvdata(pdev, drv_data);
- status = spi_register_master(master);
- if (status) {
- dev_err(dev, "problem registering spi master\n");
- goto out_error_master;
- }
-
- dev_info(dev, "%s, regs_base@%p\n", DRV_DESC, drv_data->regs);
- return 0;
-
- out_error_master:
- peripheral_free_list(drv_data->pin_req);
- out_error_peripheral:
- free_irq(drv_data->err_irq, drv_data);
- out_error_irq:
- out_error_queue_alloc:
- bfin_sport_spi_destroy_queue(drv_data);
- out_error_get_ires:
- iounmap(drv_data->regs);
- out_error_ioremap:
- out_error_get_res:
- spi_master_put(master);
-
- return status;
-}
-
-/* stop hardware and remove the driver */
-static int bfin_sport_spi_remove(struct platform_device *pdev)
-{
- struct bfin_sport_spi_master_data *drv_data = platform_get_drvdata(pdev);
- int status = 0;
-
- if (!drv_data)
- return 0;
-
- /* Remove the queue */
- status = bfin_sport_spi_destroy_queue(drv_data);
- if (status)
- return status;
-
- /* Disable the SSP at the peripheral and SOC level */
- bfin_sport_spi_disable(drv_data);
-
- /* Disconnect from the SPI framework */
- spi_unregister_master(drv_data->master);
-
- peripheral_free_list(drv_data->pin_req);
-
- return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int bfin_sport_spi_suspend(struct device *dev)
-{
- struct bfin_sport_spi_master_data *drv_data = dev_get_drvdata(dev);
- int status;
-
- status = bfin_sport_spi_stop_queue(drv_data);
- if (status)
- return status;
-
- /* stop hardware */
- bfin_sport_spi_disable(drv_data);
-
- return status;
-}
-
-static int bfin_sport_spi_resume(struct device *dev)
-{
- struct bfin_sport_spi_master_data *drv_data = dev_get_drvdata(dev);
- int status;
-
- /* Enable the SPI interface */
- bfin_sport_spi_enable(drv_data);
-
- /* Start the queue running */
- status = bfin_sport_spi_start_queue(drv_data);
- if (status)
- dev_err(drv_data->dev, "problem resuming queue\n");
-
- return status;
-}
-
-static SIMPLE_DEV_PM_OPS(bfin_sport_spi_pm_ops, bfin_sport_spi_suspend,
- bfin_sport_spi_resume);
-
-#define BFIN_SPORT_SPI_PM_OPS (&bfin_sport_spi_pm_ops)
-#else
-#define BFIN_SPORT_SPI_PM_OPS NULL
-#endif
-
-static struct platform_driver bfin_sport_spi_driver = {
- .driver = {
- .name = DRV_NAME,
- .pm = BFIN_SPORT_SPI_PM_OPS,
- },
- .probe = bfin_sport_spi_probe,
- .remove = bfin_sport_spi_remove,
-};
-module_platform_driver(bfin_sport_spi_driver);
diff --git a/drivers/spi/spi-bfin5xx.c b/drivers/spi/spi-bfin5xx.c
deleted file mode 100644
index 249c7a3..0000000
--- a/drivers/spi/spi-bfin5xx.c
+++ /dev/null
@@ -1,1462 +0,0 @@
-/*
- * Blackfin On-Chip SPI Driver
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/gpio.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/irq.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/spi/spi.h>
-#include <linux/workqueue.h>
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/cacheflush.h>
-
-#define DRV_NAME "bfin-spi"
-#define DRV_AUTHOR "Bryan Wu, Luke Yang"
-#define DRV_DESC "Blackfin on-chip SPI Controller Driver"
-#define DRV_VERSION "1.0"
-
-MODULE_AUTHOR(DRV_AUTHOR);
-MODULE_DESCRIPTION(DRV_DESC);
-MODULE_LICENSE("GPL");
-
-#define START_STATE ((void *)0)
-#define RUNNING_STATE ((void *)1)
-#define DONE_STATE ((void *)2)
-#define ERROR_STATE ((void *)-1)
-
-struct bfin_spi_master_data;
-
-struct bfin_spi_transfer_ops {
- void (*write) (struct bfin_spi_master_data *);
- void (*read) (struct bfin_spi_master_data *);
- void (*duplex) (struct bfin_spi_master_data *);
-};
-
-struct bfin_spi_master_data {
- /* Driver model hookup */
- struct platform_device *pdev;
-
- /* SPI framework hookup */
- struct spi_master *master;
-
- /* Regs base of SPI controller */
- struct bfin_spi_regs __iomem *regs;
-
- /* Pin request list */
- u16 *pin_req;
-
- /* BFIN hookup */
- struct bfin5xx_spi_master *master_info;
-
- struct work_struct pump_messages;
- spinlock_t lock;
- struct list_head queue;
- int busy;
- bool running;
-
- /* Message Transfer pump */
- struct tasklet_struct pump_transfers;
-
- /* Current message transfer state info */
- struct spi_message *cur_msg;
- struct spi_transfer *cur_transfer;
- struct bfin_spi_slave_data *cur_chip;
- size_t len_in_bytes;
- size_t len;
- void *tx;
- void *tx_end;
- void *rx;
- void *rx_end;
-
- /* DMA stuffs */
- int dma_channel;
- int dma_mapped;
- int dma_requested;
- dma_addr_t rx_dma;
- dma_addr_t tx_dma;
-
- int irq_requested;
- int spi_irq;
-
- size_t rx_map_len;
- size_t tx_map_len;
- u8 n_bytes;
- u16 ctrl_reg;
- u16 flag_reg;
-
- int cs_change;
- const struct bfin_spi_transfer_ops *ops;
-};
-
-struct bfin_spi_slave_data {
- u16 ctl_reg;
- u16 baud;
- u16 flag;
-
- u8 chip_select_num;
- u8 enable_dma;
- u16 cs_chg_udelay; /* Some devices require > 255usec delay */
- u32 cs_gpio;
- u16 idle_tx_val;
- u8 pio_interrupt; /* use spi data irq */
- const struct bfin_spi_transfer_ops *ops;
-};
-
-static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
-{
- bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE);
-}
-
-static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
-{
- bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE);
-}
-
-/* Caculate the SPI_BAUD register value based on input HZ */
-static u16 hz_to_spi_baud(u32 speed_hz)
-{
- u_long sclk = get_sclk();
- u16 spi_baud = (sclk / (2 * speed_hz));
-
- if ((sclk % (2 * speed_hz)) > 0)
- spi_baud++;
-
- if (spi_baud < MIN_SPI_BAUD_VAL)
- spi_baud = MIN_SPI_BAUD_VAL;
-
- return spi_baud;
-}
-
-static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
-{
- unsigned long limit = loops_per_jiffy << 1;
-
- /* wait for stop and clear stat */
- while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit)
- cpu_relax();
-
- bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
-
- return limit;
-}
-
-/* Chip select operation functions for cs_change flag */
-static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
-{
- if (likely(chip->chip_select_num < MAX_CTRL_CS))
- bfin_write_and(&drv_data->regs->flg, ~chip->flag);
- else
- gpio_set_value(chip->cs_gpio, 0);
-}
-
-static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
- struct bfin_spi_slave_data *chip)
-{
- if (likely(chip->chip_select_num < MAX_CTRL_CS))
- bfin_write_or(&drv_data->regs->flg, chip->flag);
- else
- gpio_set_value(chip->cs_gpio, 1);
-
- /* Move delay here for consistency */
- if (chip->cs_chg_udelay)
- udelay(chip->cs_chg_udelay);
-}
-
-/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
-static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
- struct bfin_spi_slave_data *chip)
-{
- if (chip->chip_select_num < MAX_CTRL_CS)
- bfin_write_or(&drv_data->regs->flg, chip->flag >> 8);
-}
-
-static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
- struct bfin_spi_slave_data *chip)
-{
- if (chip->chip_select_num < MAX_CTRL_CS)
- bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8));
-}
-
-/* stop controller and re-config current chip*/
-static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
-{
- struct bfin_spi_slave_data *chip = drv_data->cur_chip;
-
- /* Clear status and disable clock */
- bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
- bfin_spi_disable(drv_data);
- dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
-
- SSYNC();
-
- /* Load the registers */
- bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
- bfin_write(&drv_data->regs->baud, chip->baud);
-
- bfin_spi_enable(drv_data);
- bfin_spi_cs_active(drv_data, chip);
-}
-
-/* used to kick off transfer in rx mode and read unwanted RX data */
-static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
-{
- (void) bfin_read(&drv_data->regs->rdbr);
-}
-
-static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
-{
- /* clear RXS (we check for RXS inside the loop) */
- bfin_spi_dummy_read(drv_data);
-
- while (drv_data->tx < drv_data->tx_end) {
- bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
- /* wait until transfer finished.
- checking SPIF or TXS may not guarantee transfer completion */
- while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
- cpu_relax();
- /* discard RX data and clear RXS */
- bfin_spi_dummy_read(drv_data);
- }
-}
-
-static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
-{
- u16 tx_val = drv_data->cur_chip->idle_tx_val;
-
- /* discard old RX data and clear RXS */
- bfin_spi_dummy_read(drv_data);
-
- while (drv_data->rx < drv_data->rx_end) {
- bfin_write(&drv_data->regs->tdbr, tx_val);
- while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
- cpu_relax();
- *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
- }
-}
-
-static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
-{
- /* discard old RX data and clear RXS */
- bfin_spi_dummy_read(drv_data);
-
- while (drv_data->rx < drv_data->rx_end) {
- bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
- while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
- cpu_relax();
- *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
- }
-}
-
-static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
- .write = bfin_spi_u8_writer,
- .read = bfin_spi_u8_reader,
- .duplex = bfin_spi_u8_duplex,
-};
-
-static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
-{
- /* clear RXS (we check for RXS inside the loop) */
- bfin_spi_dummy_read(drv_data);
-
- while (drv_data->tx < drv_data->tx_end) {
- bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
- drv_data->tx += 2;
- /* wait until transfer finished.
- checking SPIF or TXS may not guarantee transfer completion */
- while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
- cpu_relax();
- /* discard RX data and clear RXS */
- bfin_spi_dummy_read(drv_data);
- }
-}
-
-static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
-{
- u16 tx_val = drv_data->cur_chip->idle_tx_val;
-
- /* discard old RX data and clear RXS */
- bfin_spi_dummy_read(drv_data);
-
- while (drv_data->rx < drv_data->rx_end) {
- bfin_write(&drv_data->regs->tdbr, tx_val);
- while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
- cpu_relax();
- *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
- drv_data->rx += 2;
- }
-}
-
-static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
-{
- /* discard old RX data and clear RXS */
- bfin_spi_dummy_read(drv_data);
-
- while (drv_data->rx < drv_data->rx_end) {
- bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
- drv_data->tx += 2;
- while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
- cpu_relax();
- *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
- drv_data->rx += 2;
- }
-}
-
-static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
- .write = bfin_spi_u16_writer,
- .read = bfin_spi_u16_reader,
- .duplex = bfin_spi_u16_duplex,
-};
-
-/* test if there is more transfer to be done */
-static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
-{
- struct spi_message *msg = drv_data->cur_msg;
- struct spi_transfer *trans = drv_data->cur_transfer;
-
- /* Move to next transfer */
- if (trans->transfer_list.next != &msg->transfers) {
- drv_data->cur_transfer =
- list_entry(trans->transfer_list.next,
- struct spi_transfer, transfer_list);
- return RUNNING_STATE;
- } else
- return DONE_STATE;
-}
-
-/*
- * caller already set message->status;
- * dma and pio irqs are blocked give finished message back
- */
-static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
-{
- struct bfin_spi_slave_data *chip = drv_data->cur_chip;
- unsigned long flags;
- struct spi_message *msg;
-
- spin_lock_irqsave(&drv_data->lock, flags);
- msg = drv_data->cur_msg;
- drv_data->cur_msg = NULL;
- drv_data->cur_transfer = NULL;
- drv_data->cur_chip = NULL;
- schedule_work(&drv_data->pump_messages);
- spin_unlock_irqrestore(&drv_data->lock, flags);
-
- msg->state = NULL;
-
- if (!drv_data->cs_change)
- bfin_spi_cs_deactive(drv_data, chip);
-
- /* Not stop spi in autobuffer mode */
- if (drv_data->tx_dma != 0xFFFF)
- bfin_spi_disable(drv_data);
-
- if (msg->complete)
- msg->complete(msg->context);
-}
-
-/* spi data irq handler */
-static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
-{
- struct bfin_spi_master_data *drv_data = dev_id;
- struct bfin_spi_slave_data *chip = drv_data->cur_chip;
- struct spi_message *msg = drv_data->cur_msg;
- int n_bytes = drv_data->n_bytes;
- int loop = 0;
-
- /* wait until transfer finished. */
- while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
- cpu_relax();
-
- if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
- (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
- /* last read */
- if (drv_data->rx) {
- dev_dbg(&drv_data->pdev->dev, "last read\n");
- if (!(n_bytes % 2)) {
- u16 *buf = (u16 *)drv_data->rx;
- for (loop = 0; loop < n_bytes / 2; loop++)
- *buf++ = bfin_read(&drv_data->regs->rdbr);
- } else {
- u8 *buf = (u8 *)drv_data->rx;
- for (loop = 0; loop < n_bytes; loop++)
- *buf++ = bfin_read(&drv_data->regs->rdbr);
- }
- drv_data->rx += n_bytes;
- }
-
- msg->actual_length += drv_data->len_in_bytes;
- if (drv_data->cs_change)
- bfin_spi_cs_deactive(drv_data, chip);
- /* Move to next transfer */
- msg->state = bfin_spi_next_transfer(drv_data);
-
- disable_irq_nosync(drv_data->spi_irq);
-
- /* Schedule transfer tasklet */
- tasklet_schedule(&drv_data->pump_transfers);
- return IRQ_HANDLED;
- }
-
- if (drv_data->rx && drv_data->tx) {
- /* duplex */
- dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
- if (!(n_bytes % 2)) {
- u16 *buf = (u16 *)drv_data->rx;
- u16 *buf2 = (u16 *)drv_data->tx;
- for (loop = 0; loop < n_bytes / 2; loop++) {
- *buf++ = bfin_read(&drv_data->regs->rdbr);
- bfin_write(&drv_data->regs->tdbr, *buf2++);
- }
- } else {
- u8 *buf = (u8 *)drv_data->rx;
- u8 *buf2 = (u8 *)drv_data->tx;
- for (loop = 0; loop < n_bytes; loop++) {
- *buf++ = bfin_read(&drv_data->regs->rdbr);
- bfin_write(&drv_data->regs->tdbr, *buf2++);
- }
- }
- } else if (drv_data->rx) {
- /* read */
- dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
- if (!(n_bytes % 2)) {
- u16 *buf = (u16 *)drv_data->rx;
- for (loop = 0; loop < n_bytes / 2; loop++) {
- *buf++ = bfin_read(&drv_data->regs->rdbr);
- bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
- }
- } else {
- u8 *buf = (u8 *)drv_data->rx;
- for (loop = 0; loop < n_bytes; loop++) {
- *buf++ = bfin_read(&drv_data->regs->rdbr);
- bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
- }
- }
- } else if (drv_data->tx) {
- /* write */
- dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
- if (!(n_bytes % 2)) {
- u16 *buf = (u16 *)drv_data->tx;
- for (loop = 0; loop < n_bytes / 2; loop++) {
- bfin_read(&drv_data->regs->rdbr);
- bfin_write(&drv_data->regs->tdbr, *buf++);
- }
- } else {
- u8 *buf = (u8 *)drv_data->tx;
- for (loop = 0; loop < n_bytes; loop++) {
- bfin_read(&drv_data->regs->rdbr);
- bfin_write(&drv_data->regs->tdbr, *buf++);
- }
- }
- }
-
- if (drv_data->tx)
- drv_data->tx += n_bytes;
- if (drv_data->rx)
- drv_data->rx += n_bytes;
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
-{
- struct bfin_spi_master_data *drv_data = dev_id;
- struct bfin_spi_slave_data *chip = drv_data->cur_chip;
- struct spi_message *msg = drv_data->cur_msg;
- unsigned long timeout;
- unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
- u16 spistat = bfin_read(&drv_data->regs->stat);
-
- dev_dbg(&drv_data->pdev->dev,
- "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
- dmastat, spistat);
-
- if (drv_data->rx != NULL) {
- u16 cr = bfin_read(&drv_data->regs->ctl);
- /* discard old RX data and clear RXS */
- bfin_spi_dummy_read(drv_data);
- bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
- bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */
- bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */
- }
-
- clear_dma_irqstat(drv_data->dma_channel);
-
- /*
- * wait for the last transaction shifted out. HRM states:
- * at this point there may still be data in the SPI DMA FIFO waiting
- * to be transmitted ... software needs to poll TXS in the SPI_STAT
- * register until it goes low for 2 successive reads
- */
- if (drv_data->tx != NULL) {
- while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) ||
- (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS))
- cpu_relax();
- }
-
- dev_dbg(&drv_data->pdev->dev,
- "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
- dmastat, bfin_read(&drv_data->regs->stat));
-
- timeout = jiffies + HZ;
- while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
- if (!time_before(jiffies, timeout)) {
- dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF\n");
- break;
- } else
- cpu_relax();
-
- if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
- msg->state = ERROR_STATE;
- dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
- } else {
- msg->actual_length += drv_data->len_in_bytes;
-
- if (drv_data->cs_change)
- bfin_spi_cs_deactive(drv_data, chip);
-
- /* Move to next transfer */
- msg->state = bfin_spi_next_transfer(drv_data);
- }
-
- /* Schedule transfer tasklet */
- tasklet_schedule(&drv_data->pump_transfers);
-
- /* free the irq handler before next transfer */
- dev_dbg(&drv_data->pdev->dev,
- "disable dma channel irq%d\n",
- drv_data->dma_channel);
- dma_disable_irq_nosync(drv_data->dma_channel);
-
- return IRQ_HANDLED;
-}
-
-static void bfin_spi_pump_transfers(unsigned long data)
-{
- struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
- struct spi_message *message = NULL;
- struct spi_transfer *transfer = NULL;
- struct spi_transfer *previous = NULL;
- struct bfin_spi_slave_data *chip = NULL;
- unsigned int bits_per_word;
- u16 cr, cr_width = 0, dma_width, dma_config;
- u32 tranf_success = 1;
- u8 full_duplex = 0;
-
- /* Get current state information */
- message = drv_data->cur_msg;
- transfer = drv_data->cur_transfer;
- chip = drv_data->cur_chip;
-
- /*
- * if msg is error or done, report it back using complete() callback
- */
-
- /* Handle for abort */
- if (message->state == ERROR_STATE) {
- dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
- message->status = -EIO;
- bfin_spi_giveback(drv_data);
- return;
- }
-
- /* Handle end of message */
- if (message->state == DONE_STATE) {
- dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
- message->status = 0;
- bfin_spi_flush(drv_data);
- bfin_spi_giveback(drv_data);
- return;
- }
-
- /* Delay if requested at end of transfer */
- if (message->state == RUNNING_STATE) {
- dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
- previous = list_entry(transfer->transfer_list.prev,
- struct spi_transfer, transfer_list);
- if (previous->delay_usecs)
- udelay(previous->delay_usecs);
- }
-
- /* Flush any existing transfers that may be sitting in the hardware */
- if (bfin_spi_flush(drv_data) == 0) {
- dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
- message->status = -EIO;
- bfin_spi_giveback(drv_data);
- return;
- }
-
- if (transfer->len == 0) {
- /* Move to next transfer of this msg */
- message->state = bfin_spi_next_transfer(drv_data);
- /* Schedule next transfer tasklet */
- tasklet_schedule(&drv_data->pump_transfers);
- return;
- }
-
- if (transfer->tx_buf != NULL) {
- drv_data->tx = (void *)transfer->tx_buf;
- drv_data->tx_end = drv_data->tx + transfer->len;
- dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
- transfer->tx_buf, drv_data->tx_end);
- } else {
- drv_data->tx = NULL;
- }
-
- if (transfer->rx_buf != NULL) {
- full_duplex = transfer->tx_buf != NULL;
- drv_data->rx = transfer->rx_buf;
- drv_data->rx_end = drv_data->rx + transfer->len;
- dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
- transfer->rx_buf, drv_data->rx_end);
- } else {
- drv_data->rx = NULL;
- }
-
- drv_data->rx_dma = transfer->rx_dma;
- drv_data->tx_dma = transfer->tx_dma;
- drv_data->len_in_bytes = transfer->len;
- drv_data->cs_change = transfer->cs_change;
-
- /* Bits per word setup */
- bits_per_word = transfer->bits_per_word;
- if (bits_per_word == 16) {
- drv_data->n_bytes = bits_per_word/8;
- drv_data->len = (transfer->len) >> 1;
- cr_width = BIT_CTL_WORDSIZE;
- drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
- } else if (bits_per_word == 8) {
- drv_data->n_bytes = bits_per_word/8;
- drv_data->len = transfer->len;
- drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
- }
- cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
- cr |= cr_width;
- bfin_write(&drv_data->regs->ctl, cr);
-
- dev_dbg(&drv_data->pdev->dev,
- "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
- drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
-
- message->state = RUNNING_STATE;
- dma_config = 0;
-
- bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));
-
- bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
- bfin_spi_cs_active(drv_data, chip);
-
- dev_dbg(&drv_data->pdev->dev,
- "now pumping a transfer: width is %d, len is %d\n",
- cr_width, transfer->len);
-
- /*
- * Try to map dma buffer and do a dma transfer. If successful use,
- * different way to r/w according to the enable_dma settings and if
- * we are not doing a full duplex transfer (since the hardware does
- * not support full duplex DMA transfers).
- */
- if (!full_duplex && drv_data->cur_chip->enable_dma
- && drv_data->len > 6) {
-
- unsigned long dma_start_addr, flags;
-
- disable_dma(drv_data->dma_channel);
- clear_dma_irqstat(drv_data->dma_channel);
-
- /* config dma channel */
- dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
- set_dma_x_count(drv_data->dma_channel, drv_data->len);
- if (cr_width == BIT_CTL_WORDSIZE) {
- set_dma_x_modify(drv_data->dma_channel, 2);
- dma_width = WDSIZE_16;
- } else {
- set_dma_x_modify(drv_data->dma_channel, 1);
- dma_width = WDSIZE_8;
- }
-
- /* poll for SPI completion before start */
- while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
- cpu_relax();
-
- /* dirty hack for autobuffer DMA mode */
- if (drv_data->tx_dma == 0xFFFF) {
- dev_dbg(&drv_data->pdev->dev,
- "doing autobuffer DMA out.\n");
-
- /* no irq in autobuffer mode */
- dma_config =
- (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
- set_dma_config(drv_data->dma_channel, dma_config);
- set_dma_start_addr(drv_data->dma_channel,
- (unsigned long)drv_data->tx);
- enable_dma(drv_data->dma_channel);
-
- /* start SPI transfer */
- bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);
-
- /* just return here, there can only be one transfer
- * in this mode
- */
- message->status = 0;
- bfin_spi_giveback(drv_data);
- return;
- }
-
- /* In dma mode, rx or tx must be NULL in one transfer */
- dma_config = (RESTART | dma_width | DI_EN);
- if (drv_data->rx != NULL) {
- /* set transfer mode, and enable SPI */
- dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
- drv_data->rx, drv_data->len_in_bytes);
-
- /* invalidate caches, if needed */
- if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
- invalidate_dcache_range((unsigned long) drv_data->rx,
- (unsigned long) (drv_data->rx +
- drv_data->len_in_bytes));
-
- dma_config |= WNR;
- dma_start_addr = (unsigned long)drv_data->rx;
- cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
-
- } else if (drv_data->tx != NULL) {
- dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
-
- /* flush caches, if needed */
- if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
- flush_dcache_range((unsigned long) drv_data->tx,
- (unsigned long) (drv_data->tx +
- drv_data->len_in_bytes));
-
- dma_start_addr = (unsigned long)drv_data->tx;
- cr |= BIT_CTL_TIMOD_DMA_TX;
-
- } else
- BUG();
-
- /* oh man, here there be monsters ... and i dont mean the
- * fluffy cute ones from pixar, i mean the kind that'll eat
- * your data, kick your dog, and love it all. do *not* try
- * and change these lines unless you (1) heavily test DMA
- * with SPI flashes on a loaded system (e.g. ping floods),
- * (2) know just how broken the DMA engine interaction with
- * the SPI peripheral is, and (3) have someone else to blame
- * when you screw it all up anyways.
- */
- set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
- set_dma_config(drv_data->dma_channel, dma_config);
- local_irq_save(flags);
- SSYNC();
- bfin_write(&drv_data->regs->ctl, cr);
- enable_dma(drv_data->dma_channel);
- dma_enable_irq(drv_data->dma_channel);
- local_irq_restore(flags);
-
- return;
- }
-
- /*
- * We always use SPI_WRITE mode (transfer starts with TDBR write).
- * SPI_READ mode (transfer starts with RDBR read) seems to have
- * problems with setting up the output value in TDBR prior to the
- * start of the transfer.
- */
- bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);
-
- if (chip->pio_interrupt) {
- /* SPI irq should have been disabled by now */
-
- /* discard old RX data and clear RXS */
- bfin_spi_dummy_read(drv_data);
-
- /* start transfer */
- if (drv_data->tx == NULL)
- bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
- else {
- int loop;
- if (bits_per_word == 16) {
- u16 *buf = (u16 *)drv_data->tx;
- for (loop = 0; loop < bits_per_word / 16;
- loop++) {
- bfin_write(&drv_data->regs->tdbr, *buf++);
- }
- } else if (bits_per_word == 8) {
- u8 *buf = (u8 *)drv_data->tx;
- for (loop = 0; loop < bits_per_word / 8; loop++)
- bfin_write(&drv_data->regs->tdbr, *buf++);
- }
-
- drv_data->tx += drv_data->n_bytes;
- }
-
- /* once TDBR is empty, interrupt is triggered */
- enable_irq(drv_data->spi_irq);
- return;
- }
-
- /* IO mode */
- dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
-
- if (full_duplex) {
- /* full duplex mode */
- BUG_ON((drv_data->tx_end - drv_data->tx) !=
- (drv_data->rx_end - drv_data->rx));
- dev_dbg(&drv_data->pdev->dev,
- "IO duplex: cr is 0x%x\n", cr);
-
- drv_data->ops->duplex(drv_data);
-
- if (drv_data->tx != drv_data->tx_end)
- tranf_success = 0;
- } else if (drv_data->tx != NULL) {
- /* write only half duplex */
- dev_dbg(&drv_data->pdev->dev,
- "IO write: cr is 0x%x\n", cr);
-
- drv_data->ops->write(drv_data);
-
- if (drv_data->tx != drv_data->tx_end)
- tranf_success = 0;
- } else if (drv_data->rx != NULL) {
- /* read only half duplex */
- dev_dbg(&drv_data->pdev->dev,
- "IO read: cr is 0x%x\n", cr);
-
- drv_data->ops->read(drv_data);
- if (drv_data->rx != drv_data->rx_end)
- tranf_success = 0;
- }
-
- if (!tranf_success) {
- dev_dbg(&drv_data->pdev->dev,
- "IO write error!\n");
- message->state = ERROR_STATE;
- } else {
- /* Update total byte transferred */
- message->actual_length += drv_data->len_in_bytes;
- /* Move to next transfer of this msg */
- message->state = bfin_spi_next_transfer(drv_data);
- if (drv_data->cs_change && message->state != DONE_STATE) {
- bfin_spi_flush(drv_data);
- bfin_spi_cs_deactive(drv_data, chip);
- }
- }
-
- /* Schedule next transfer tasklet */
- tasklet_schedule(&drv_data->pump_transfers);
-}
-
-/* pop a msg from queue and kick off real transfer */
-static void bfin_spi_pump_messages(struct work_struct *work)
-{
- struct bfin_spi_master_data *drv_data;
- unsigned long flags;
-
- drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
-
- /* Lock queue and check for queue work */
- spin_lock_irqsave(&drv_data->lock, flags);
- if (list_empty(&drv_data->queue) || !drv_data->running) {
- /* pumper kicked off but no work to do */
- drv_data->busy = 0;
- spin_unlock_irqrestore(&drv_data->lock, flags);
- return;
- }
-
- /* Make sure we are not already running a message */
- if (drv_data->cur_msg) {
- spin_unlock_irqrestore(&drv_data->lock, flags);
- return;
- }
-
- /* Extract head of queue */
- drv_data->cur_msg = list_entry(drv_data->queue.next,
- struct spi_message, queue);
-
- /* Setup the SSP using the per chip configuration */
- drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
- bfin_spi_restore_state(drv_data);
-
- list_del_init(&drv_data->cur_msg->queue);
-
- /* Initial message state */
- drv_data->cur_msg->state = START_STATE;
- drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
- struct spi_transfer, transfer_list);
-
- dev_dbg(&drv_data->pdev->dev,
- "got a message to pump, state is set to: baud "
- "%d, flag 0x%x, ctl 0x%x\n",
- drv_data->cur_chip->baud, drv_data->cur_chip->flag,
- drv_data->cur_chip->ctl_reg);
-
- dev_dbg(&drv_data->pdev->dev,
- "the first transfer len is %d\n",
- drv_data->cur_transfer->len);
-
- /* Mark as busy and launch transfers */
- tasklet_schedule(&drv_data->pump_transfers);
-
- drv_data->busy = 1;
- spin_unlock_irqrestore(&drv_data->lock, flags);
-}
-
-/*
- * got a msg to transfer, queue it in drv_data->queue.
- * And kick off message pumper
- */
-static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
-{
- struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
- unsigned long flags;
-
- spin_lock_irqsave(&drv_data->lock, flags);
-
- if (!drv_data->running) {
- spin_unlock_irqrestore(&drv_data->lock, flags);
- return -ESHUTDOWN;
- }
-
- msg->actual_length = 0;
- msg->status = -EINPROGRESS;
- msg->state = START_STATE;
-
- dev_dbg(&spi->dev, "adding an msg in transfer() \n");
- list_add_tail(&msg->queue, &drv_data->queue);
-
- if (drv_data->running && !drv_data->busy)
- schedule_work(&drv_data->pump_messages);
-
- spin_unlock_irqrestore(&drv_data->lock, flags);
-
- return 0;
-}
-
-#define MAX_SPI_SSEL 7
-
-static const u16 ssel[][MAX_SPI_SSEL] = {
- {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
- P_SPI0_SSEL4, P_SPI0_SSEL5,
- P_SPI0_SSEL6, P_SPI0_SSEL7},
-
- {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
- P_SPI1_SSEL4, P_SPI1_SSEL5,
- P_SPI1_SSEL6, P_SPI1_SSEL7},
-
- {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
- P_SPI2_SSEL4, P_SPI2_SSEL5,
- P_SPI2_SSEL6, P_SPI2_SSEL7},
-};
-
-/* setup for devices (may be called multiple times -- not just first setup) */
-static int bfin_spi_setup(struct spi_device *spi)
-{
- struct bfin5xx_spi_chip *chip_info;
- struct bfin_spi_slave_data *chip = NULL;
- struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
- u16 bfin_ctl_reg;
- int ret = -EINVAL;
-
- /* Only alloc (or use chip_info) on first setup */
- chip_info = NULL;
- chip = spi_get_ctldata(spi);
- if (chip == NULL) {
- chip = kzalloc(sizeof(*chip), GFP_KERNEL);
- if (!chip) {
- dev_err(&spi->dev, "cannot allocate chip data\n");
- ret = -ENOMEM;
- goto error;
- }
-
- chip->enable_dma = 0;
- chip_info = spi->controller_data;
- }
-
- /* Let people set non-standard bits directly */
- bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
- BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
-
- /* chip_info isn't always needed */
- if (chip_info) {
- /* Make sure people stop trying to set fields via ctl_reg
- * when they should actually be using common SPI framework.
- * Currently we let through: WOM EMISO PSSE GM SZ.
- * Not sure if a user actually needs/uses any of these,
- * but let's assume (for now) they do.
- */
- if (chip_info->ctl_reg & ~bfin_ctl_reg) {
- dev_err(&spi->dev,
- "do not set bits in ctl_reg that the SPI framework manages\n");
- goto error;
- }
- chip->enable_dma = chip_info->enable_dma != 0
- && drv_data->master_info->enable_dma;
- chip->ctl_reg = chip_info->ctl_reg;
- chip->cs_chg_udelay = chip_info->cs_chg_udelay;
- chip->idle_tx_val = chip_info->idle_tx_val;
- chip->pio_interrupt = chip_info->pio_interrupt;
- } else {
- /* force a default base state */
- chip->ctl_reg &= bfin_ctl_reg;
- }
-
- /* translate common spi framework into our register */
- if (spi->mode & SPI_CPOL)
- chip->ctl_reg |= BIT_CTL_CPOL;
- if (spi->mode & SPI_CPHA)
- chip->ctl_reg |= BIT_CTL_CPHA;
- if (spi->mode & SPI_LSB_FIRST)
- chip->ctl_reg |= BIT_CTL_LSBF;
- /* we dont support running in slave mode (yet?) */
- chip->ctl_reg |= BIT_CTL_MASTER;
-
- /*
- * Notice: for blackfin, the speed_hz is the value of register
- * SPI_BAUD, not the real baudrate
- */
- chip->baud = hz_to_spi_baud(spi->max_speed_hz);
- chip->chip_select_num = spi->chip_select;
- if (chip->chip_select_num < MAX_CTRL_CS) {
- if (!(spi->mode & SPI_CPHA))
- dev_warn(&spi->dev,
- "Warning: SPI CPHA not set: Slave Select not under software control!\n"
- "See Documentation/blackfin/bfin-spi-notes.txt\n");
-
- chip->flag = (1 << spi->chip_select) << 8;
- } else
- chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
-
- if (chip->enable_dma && chip->pio_interrupt) {
- dev_err(&spi->dev,
- "enable_dma is set, do not set pio_interrupt\n");
- goto error;
- }
- /*
- * if any one SPI chip is registered and wants DMA, request the
- * DMA channel for it
- */
- if (chip->enable_dma && !drv_data->dma_requested) {
- /* register dma irq handler */
- ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
- if (ret) {
- dev_err(&spi->dev,
- "Unable to request BlackFin SPI DMA channel\n");
- goto error;
- }
- drv_data->dma_requested = 1;
-
- ret = set_dma_callback(drv_data->dma_channel,
- bfin_spi_dma_irq_handler, drv_data);
- if (ret) {
- dev_err(&spi->dev, "Unable to set dma callback\n");
- goto error;
- }
- dma_disable_irq(drv_data->dma_channel);
- }
-
- if (chip->pio_interrupt && !drv_data->irq_requested) {
- ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
- 0, "BFIN_SPI", drv_data);
- if (ret) {
- dev_err(&spi->dev, "Unable to register spi IRQ\n");
- goto error;
- }
- drv_data->irq_requested = 1;
- /* we use write mode, spi irq has to be disabled here */
- disable_irq(drv_data->spi_irq);
- }
-
- if (chip->chip_select_num >= MAX_CTRL_CS) {
- /* Only request on first setup */
- if (spi_get_ctldata(spi) == NULL) {
- ret = gpio_request(chip->cs_gpio, spi->modalias);
- if (ret) {
- dev_err(&spi->dev, "gpio_request() error\n");
- goto pin_error;
- }
- gpio_direction_output(chip->cs_gpio, 1);
- }
- }
-
- dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
- spi->modalias, spi->bits_per_word, chip->enable_dma);
- dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
- chip->ctl_reg, chip->flag);
-
- spi_set_ctldata(spi, chip);
-
- dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
- if (chip->chip_select_num < MAX_CTRL_CS) {
- ret = peripheral_request(ssel[spi->master->bus_num]
- [chip->chip_select_num-1], spi->modalias);
- if (ret) {
- dev_err(&spi->dev, "peripheral_request() error\n");
- goto pin_error;
- }
- }
-
- bfin_spi_cs_enable(drv_data, chip);
- bfin_spi_cs_deactive(drv_data, chip);
-
- return 0;
-
- pin_error:
- if (chip->chip_select_num >= MAX_CTRL_CS)
- gpio_free(chip->cs_gpio);
- else
- peripheral_free(ssel[spi->master->bus_num]
- [chip->chip_select_num - 1]);
- error:
- if (chip) {
- if (drv_data->dma_requested)
- free_dma(drv_data->dma_channel);
- drv_data->dma_requested = 0;
-
- kfree(chip);
- /* prevent free 'chip' twice */
- spi_set_ctldata(spi, NULL);
- }
-
- return ret;
-}
-
-/*
- * callback for spi framework.
- * clean driver specific data
- */
-static void bfin_spi_cleanup(struct spi_device *spi)
-{
- struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
- struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
-
- if (!chip)
- return;
-
- if (chip->chip_select_num < MAX_CTRL_CS) {
- peripheral_free(ssel[spi->master->bus_num]
- [chip->chip_select_num-1]);
- bfin_spi_cs_disable(drv_data, chip);
- } else
- gpio_free(chip->cs_gpio);
-
- kfree(chip);
- /* prevent free 'chip' twice */
- spi_set_ctldata(spi, NULL);
-}
-
-static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
-{
- INIT_LIST_HEAD(&drv_data->queue);
- spin_lock_init(&drv_data->lock);
-
- drv_data->running = false;
- drv_data->busy = 0;
-
- /* init transfer tasklet */
- tasklet_init(&drv_data->pump_transfers,
- bfin_spi_pump_transfers, (unsigned long)drv_data);
-
- INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
-
- return 0;
-}
-
-static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&drv_data->lock, flags);
-
- if (drv_data->running || drv_data->busy) {
- spin_unlock_irqrestore(&drv_data->lock, flags);
- return -EBUSY;
- }
-
- drv_data->running = true;
- drv_data->cur_msg = NULL;
- drv_data->cur_transfer = NULL;
- drv_data->cur_chip = NULL;
- spin_unlock_irqrestore(&drv_data->lock, flags);
-
- schedule_work(&drv_data->pump_messages);
-
- return 0;
-}
-
-static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
-{
- unsigned long flags;
- unsigned limit = 500;
- int status = 0;
-
- spin_lock_irqsave(&drv_data->lock, flags);
-
- /*
- * This is a bit lame, but is optimized for the common execution path.
- * A wait_queue on the drv_data->busy could be used, but then the common
- * execution path (pump_messages) would be required to call wake_up or
- * friends on every SPI message. Do this instead
- */
- drv_data->running = false;
- while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
- spin_unlock_irqrestore(&drv_data->lock, flags);
- msleep(10);
- spin_lock_irqsave(&drv_data->lock, flags);
- }
-
- if (!list_empty(&drv_data->queue) || drv_data->busy)
- status = -EBUSY;
-
- spin_unlock_irqrestore(&drv_data->lock, flags);
-
- return status;
-}
-
-static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
-{
- int status;
-
- status = bfin_spi_stop_queue(drv_data);
- if (status != 0)
- return status;
-
- flush_work(&drv_data->pump_messages);
-
- return 0;
-}
-
-static int bfin_spi_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct bfin5xx_spi_master *platform_info;
- struct spi_master *master;
- struct bfin_spi_master_data *drv_data;
- struct resource *res;
- int status = 0;
-
- platform_info = dev_get_platdata(dev);
-
- /* Allocate master with space for drv_data */
- master = spi_alloc_master(dev, sizeof(*drv_data));
- if (!master) {
- dev_err(&pdev->dev, "can not alloc spi_master\n");
- return -ENOMEM;
- }
-
- drv_data = spi_master_get_devdata(master);
- drv_data->master = master;
- drv_data->master_info = platform_info;
- drv_data->pdev = pdev;
- drv_data->pin_req = platform_info->pin_req;
-
- /* the spi->mode bits supported by this driver: */
- master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
- master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
- master->bus_num = pdev->id;
- master->num_chipselect = platform_info->num_chipselect;
- master->cleanup = bfin_spi_cleanup;
- master->setup = bfin_spi_setup;
- master->transfer = bfin_spi_transfer;
-
- /* Find and map our resources */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL) {
- dev_err(dev, "Cannot get IORESOURCE_MEM\n");
- status = -ENOENT;
- goto out_error_get_res;
- }
-
- drv_data->regs = ioremap(res->start, resource_size(res));
- if (drv_data->regs == NULL) {
- dev_err(dev, "Cannot map IO\n");
- status = -ENXIO;
- goto out_error_ioremap;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (res == NULL) {
- dev_err(dev, "No DMA channel specified\n");
- status = -ENOENT;
- goto out_error_free_io;
- }
- drv_data->dma_channel = res->start;
-
- drv_data->spi_irq = platform_get_irq(pdev, 0);
- if (drv_data->spi_irq < 0) {
- dev_err(dev, "No spi pio irq specified\n");
- status = -ENOENT;
- goto out_error_free_io;
- }
-
- /* Initial and start queue */
- status = bfin_spi_init_queue(drv_data);
- if (status != 0) {
- dev_err(dev, "problem initializing queue\n");
- goto out_error_queue_alloc;
- }
-
- status = bfin_spi_start_queue(drv_data);
- if (status != 0) {
- dev_err(dev, "problem starting queue\n");
- goto out_error_queue_alloc;
- }
-
- status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
- if (status != 0) {
- dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
- goto out_error_queue_alloc;
- }
-
- /* Reset SPI registers. If these registers were used by the boot loader,
- * the sky may fall on your head if you enable the dma controller.
- */
- bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
- bfin_write(&drv_data->regs->flg, 0xFF00);
-
- /* Register with the SPI framework */
- platform_set_drvdata(pdev, drv_data);
- status = spi_register_master(master);
- if (status != 0) {
- dev_err(dev, "problem registering spi master\n");
- goto out_error_queue_alloc;
- }
-
- dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n",
- DRV_DESC, DRV_VERSION, drv_data->regs,
- drv_data->dma_channel);
- return status;
-
-out_error_queue_alloc:
- bfin_spi_destroy_queue(drv_data);
-out_error_free_io:
- iounmap(drv_data->regs);
-out_error_ioremap:
-out_error_get_res:
- spi_master_put(master);
-
- return status;
-}
-
-/* stop hardware and remove the driver */
-static int bfin_spi_remove(struct platform_device *pdev)
-{
- struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
- int status = 0;
-
- if (!drv_data)
- return 0;
-
- /* Remove the queue */
- status = bfin_spi_destroy_queue(drv_data);
- if (status != 0)
- return status;
-
- /* Disable the SSP at the peripheral and SOC level */
- bfin_spi_disable(drv_data);
-
- /* Release DMA */
- if (drv_data->master_info->enable_dma) {
- if (dma_channel_active(drv_data->dma_channel))
- free_dma(drv_data->dma_channel);
- }
-
- if (drv_data->irq_requested) {
- free_irq(drv_data->spi_irq, drv_data);
- drv_data->irq_requested = 0;
- }
-
- /* Disconnect from the SPI framework */
- spi_unregister_master(drv_data->master);
-
- peripheral_free_list(drv_data->pin_req);
-
- return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int bfin_spi_suspend(struct device *dev)
-{
- struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev);
- int status = 0;
-
- status = bfin_spi_stop_queue(drv_data);
- if (status != 0)
- return status;
-
- drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl);
- drv_data->flag_reg = bfin_read(&drv_data->regs->flg);
-
- /*
- * reset SPI_CTL and SPI_FLG registers
- */
- bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
- bfin_write(&drv_data->regs->flg, 0xFF00);
-
- return 0;
-}
-
-static int bfin_spi_resume(struct device *dev)
-{
- struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev);
- int status = 0;
-
- bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);
- bfin_write(&drv_data->regs->flg, drv_data->flag_reg);
-
- /* Start the queue running */
- status = bfin_spi_start_queue(drv_data);
- if (status != 0) {
- dev_err(dev, "problem starting queue (%d)\n", status);
- return status;
- }
-
- return 0;
-}
-
-static SIMPLE_DEV_PM_OPS(bfin_spi_pm_ops, bfin_spi_suspend, bfin_spi_resume);
-
-#define BFIN_SPI_PM_OPS (&bfin_spi_pm_ops)
-#else
-#define BFIN_SPI_PM_OPS NULL
-#endif
-
-MODULE_ALIAS("platform:bfin-spi");
-static struct platform_driver bfin_spi_driver = {
- .driver = {
- .name = DRV_NAME,
- .pm = BFIN_SPI_PM_OPS,
- },
- .probe = bfin_spi_probe,
- .remove = bfin_spi_remove,
-};
-
-static int __init bfin_spi_init(void)
-{
- return platform_driver_register(&bfin_spi_driver);
-}
-subsys_initcall(bfin_spi_init);
-
-static void __exit bfin_spi_exit(void)
-{
- platform_driver_unregister(&bfin_spi_driver);
-}
-module_exit(bfin_spi_exit);
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 16/28] irda: Remove Blackfin IRDA support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (13 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 15/28] spi: Remove Blackfin SPI bus support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 17/28] usb: Remove Blackfin USB support Aaron Wu
` (11 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin IRDA support
---
drivers/staging/irda/drivers/Kconfig | 45 --
drivers/staging/irda/drivers/Makefile | 1 -
drivers/staging/irda/drivers/bfin_sir.c | 819 --------------------------------
drivers/staging/irda/drivers/bfin_sir.h | 93 ----
4 files changed, 958 deletions(-)
delete mode 100644 drivers/staging/irda/drivers/bfin_sir.c
delete mode 100644 drivers/staging/irda/drivers/bfin_sir.h
diff --git a/drivers/staging/irda/drivers/Kconfig b/drivers/staging/irda/drivers/Kconfig
index e070e12..71ac76c 100644
--- a/drivers/staging/irda/drivers/Kconfig
+++ b/drivers/staging/irda/drivers/Kconfig
@@ -17,51 +17,6 @@ config IRTTY_SIR
If unsure, say Y.
-config BFIN_SIR
- tristate "Blackfin SIR on UART"
- depends on BLACKFIN && IRDA
- default n
- help
- Say Y here if your want to enable SIR function on Blackfin UART
- devices.
-
- To activate this driver you can start irattach like:
- "irattach irda0 -s"
-
- Saying M, it will be built as a module named bfin_sir.
-
- Note that you need to turn off one of the serial drivers for SIR
- to use that UART.
-
-config BFIN_SIR0
- bool "Blackfin SIR on UART0"
- depends on BFIN_SIR && !SERIAL_BFIN_UART0
-
-config BFIN_SIR1
- bool "Blackfin SIR on UART1"
- depends on BFIN_SIR && !SERIAL_BFIN_UART1 && (!BF531 && !BF532 && !BF533 && !BF561)
-
-config BFIN_SIR2
- bool "Blackfin SIR on UART2"
- depends on BFIN_SIR && !SERIAL_BFIN_UART2 && (BF54x || BF538 || BF539)
-
-config BFIN_SIR3
- bool "Blackfin SIR on UART3"
- depends on BFIN_SIR && !SERIAL_BFIN_UART3 && (BF54x)
-
-choice
- prompt "SIR Mode"
- depends on BFIN_SIR
- default SIR_BFIN_DMA
-
-config SIR_BFIN_DMA
- bool "DMA mode"
- depends on !DMA_UNCACHED_NONE
-
-config SIR_BFIN_PIO
- bool "PIO mode"
-endchoice
-
config SH_SIR
tristate "SuperH SIR on UART"
depends on IRDA && SUPERH && \
diff --git a/drivers/staging/irda/drivers/Makefile b/drivers/staging/irda/drivers/Makefile
index e2901b1..d5307ed 100644
--- a/drivers/staging/irda/drivers/Makefile
+++ b/drivers/staging/irda/drivers/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_MCS_FIR) += mcs7780.o
obj-$(CONFIG_AU1000_FIR) += au1k_ir.o
# SIR drivers
obj-$(CONFIG_IRTTY_SIR) += irtty-sir.o sir-dev.o
-obj-$(CONFIG_BFIN_SIR) += bfin_sir.o
obj-$(CONFIG_SH_SIR) += sh_sir.o
# dongle drivers for SIR drivers
obj-$(CONFIG_ESI_DONGLE) += esi-sir.o
diff --git a/drivers/staging/irda/drivers/bfin_sir.c b/drivers/staging/irda/drivers/bfin_sir.c
deleted file mode 100644
index 59e409b..0000000
--- a/drivers/staging/irda/drivers/bfin_sir.c
+++ /dev/null
@@ -1,819 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-#include "bfin_sir.h"
-
-#ifdef CONFIG_SIR_BFIN_DMA
-#define DMA_SIR_RX_XCNT 10
-#define DMA_SIR_RX_YCNT (PAGE_SIZE / DMA_SIR_RX_XCNT)
-#define DMA_SIR_RX_FLUSH_JIFS (HZ * 4 / 250)
-#endif
-
-#if ANOMALY_05000447
-static int max_rate = 57600;
-#else
-static int max_rate = 115200;
-#endif
-
-static void bfin_sir_rx_dma_timeout(struct timer_list *t);
-
-static void turnaround_delay(int mtt)
-{
- long ticks;
-
- mtt = mtt < 10000 ? 10000 : mtt;
- ticks = 1 + mtt / (USEC_PER_SEC / HZ);
- schedule_timeout_uninterruptible(ticks);
-}
-
-static void bfin_sir_init_ports(struct bfin_sir_port *sp, struct platform_device *pdev)
-{
- int i;
- struct resource *res;
-
- for (i = 0; i < pdev->num_resources; i++) {
- res = &pdev->resource[i];
- switch (res->flags) {
- case IORESOURCE_MEM:
- sp->membase = (void __iomem *)res->start;
- break;
- case IORESOURCE_IRQ:
- sp->irq = res->start;
- break;
- case IORESOURCE_DMA:
- sp->rx_dma_channel = res->start;
- sp->tx_dma_channel = res->end;
- break;
- default:
- break;
- }
- }
-
- sp->clk = get_sclk();
-#ifdef CONFIG_SIR_BFIN_DMA
- sp->tx_done = 1;
- timer_setup(&sp->rx_dma_timer, bfin_sir_rx_dma_timeout, 0);
-#endif
-}
-
-static void bfin_sir_stop_tx(struct bfin_sir_port *port)
-{
-#ifdef CONFIG_SIR_BFIN_DMA
- disable_dma(port->tx_dma_channel);
-#endif
-
- while (!(UART_GET_LSR(port) & THRE)) {
- cpu_relax();
- continue;
- }
-
- UART_CLEAR_IER(port, ETBEI);
-}
-
-static void bfin_sir_enable_tx(struct bfin_sir_port *port)
-{
- UART_SET_IER(port, ETBEI);
-}
-
-static void bfin_sir_stop_rx(struct bfin_sir_port *port)
-{
- UART_CLEAR_IER(port, ERBFI);
-}
-
-static void bfin_sir_enable_rx(struct bfin_sir_port *port)
-{
- UART_SET_IER(port, ERBFI);
-}
-
-static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
-{
- int ret = -EINVAL;
- unsigned int quot;
- unsigned short val, lsr, lcr;
- static int utime;
- int count = 10;
-
- lcr = WLS(8);
-
- switch (speed) {
- case 9600:
- case 19200:
- case 38400:
- case 57600:
- case 115200:
-
- /*
- * IRDA is not affected by anomaly 05000230, so there is no
- * need to tweak the divisor like he UART driver (which will
- * slightly speed up the baud rate on us).
- */
- quot = (port->clk + (8 * speed)) / (16 * speed);
-
- do {
- udelay(utime);
- lsr = UART_GET_LSR(port);
- } while (!(lsr & TEMT) && count--);
-
- /* The useconds for 1 bits to transmit */
- utime = 1000000 / speed + 1;
-
- /* Clear UCEN bit to reset the UART state machine
- * and control registers
- */
- val = UART_GET_GCTL(port);
- val &= ~UCEN;
- UART_PUT_GCTL(port, val);
-
- /* Set DLAB in LCR to Access THR RBR IER */
- UART_SET_DLAB(port);
- SSYNC();
-
- UART_PUT_DLL(port, quot & 0xFF);
- UART_PUT_DLH(port, (quot >> 8) & 0xFF);
- SSYNC();
-
- /* Clear DLAB in LCR */
- UART_CLEAR_DLAB(port);
- SSYNC();
-
- UART_PUT_LCR(port, lcr);
-
- val = UART_GET_GCTL(port);
- val |= UCEN;
- UART_PUT_GCTL(port, val);
-
- ret = 0;
- break;
- default:
- printk(KERN_WARNING "bfin_sir: Invalid speed %d\n", speed);
- break;
- }
-
- val = UART_GET_GCTL(port);
- /* If not add the 'RPOLC', we can't catch the receive interrupt.
- * It's related with the HW layout and the IR transiver.
- */
- val |= UMOD_IRDA | RPOLC;
- UART_PUT_GCTL(port, val);
- return ret;
-}
-
-static int bfin_sir_is_receiving(struct net_device *dev)
-{
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
-
- if (!(UART_GET_IER(port) & ERBFI))
- return 0;
- return self->rx_buff.state != OUTSIDE_FRAME;
-}
-
-#ifdef CONFIG_SIR_BFIN_PIO
-static void bfin_sir_tx_chars(struct net_device *dev)
-{
- unsigned int chr;
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
-
- if (self->tx_buff.len != 0) {
- chr = *(self->tx_buff.data);
- UART_PUT_CHAR(port, chr);
- self->tx_buff.data++;
- self->tx_buff.len--;
- } else {
- self->stats.tx_packets++;
- self->stats.tx_bytes += self->tx_buff.data - self->tx_buff.head;
- if (self->newspeed) {
- bfin_sir_set_speed(port, self->newspeed);
- self->speed = self->newspeed;
- self->newspeed = 0;
- }
- bfin_sir_stop_tx(port);
- bfin_sir_enable_rx(port);
- /* I'm hungry! */
- netif_wake_queue(dev);
- }
-}
-
-static void bfin_sir_rx_chars(struct net_device *dev)
-{
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
- unsigned char ch;
-
- UART_CLEAR_LSR(port);
- ch = UART_GET_CHAR(port);
- async_unwrap_char(dev, &self->stats, &self->rx_buff, ch);
-}
-
-static irqreturn_t bfin_sir_rx_int(int irq, void *dev_id)
-{
- struct net_device *dev = dev_id;
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
-
- spin_lock(&self->lock);
- while ((UART_GET_LSR(port) & DR))
- bfin_sir_rx_chars(dev);
- spin_unlock(&self->lock);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t bfin_sir_tx_int(int irq, void *dev_id)
-{
- struct net_device *dev = dev_id;
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
-
- spin_lock(&self->lock);
- if (UART_GET_LSR(port) & THRE)
- bfin_sir_tx_chars(dev);
- spin_unlock(&self->lock);
-
- return IRQ_HANDLED;
-}
-#endif /* CONFIG_SIR_BFIN_PIO */
-
-#ifdef CONFIG_SIR_BFIN_DMA
-static void bfin_sir_dma_tx_chars(struct net_device *dev)
-{
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
-
- if (!port->tx_done)
- return;
- port->tx_done = 0;
-
- if (self->tx_buff.len == 0) {
- self->stats.tx_packets++;
- if (self->newspeed) {
- bfin_sir_set_speed(port, self->newspeed);
- self->speed = self->newspeed;
- self->newspeed = 0;
- }
- bfin_sir_enable_rx(port);
- port->tx_done = 1;
- netif_wake_queue(dev);
- return;
- }
-
- blackfin_dcache_flush_range((unsigned long)(self->tx_buff.data),
- (unsigned long)(self->tx_buff.data+self->tx_buff.len));
- set_dma_config(port->tx_dma_channel,
- set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
- INTR_ON_BUF, DIMENSION_LINEAR, DATA_SIZE_8,
- DMA_SYNC_RESTART));
- set_dma_start_addr(port->tx_dma_channel,
- (unsigned long)(self->tx_buff.data));
- set_dma_x_count(port->tx_dma_channel, self->tx_buff.len);
- set_dma_x_modify(port->tx_dma_channel, 1);
- enable_dma(port->tx_dma_channel);
-}
-
-static irqreturn_t bfin_sir_dma_tx_int(int irq, void *dev_id)
-{
- struct net_device *dev = dev_id;
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
-
- spin_lock(&self->lock);
- if (!(get_dma_curr_irqstat(port->tx_dma_channel) & DMA_RUN)) {
- clear_dma_irqstat(port->tx_dma_channel);
- bfin_sir_stop_tx(port);
-
- self->stats.tx_packets++;
- self->stats.tx_bytes += self->tx_buff.len;
- self->tx_buff.len = 0;
- if (self->newspeed) {
- bfin_sir_set_speed(port, self->newspeed);
- self->speed = self->newspeed;
- self->newspeed = 0;
- }
- bfin_sir_enable_rx(port);
- /* I'm hungry! */
- netif_wake_queue(dev);
- port->tx_done = 1;
- }
- spin_unlock(&self->lock);
-
- return IRQ_HANDLED;
-}
-
-static void bfin_sir_dma_rx_chars(struct net_device *dev)
-{
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
- int i;
-
- UART_CLEAR_LSR(port);
-
- for (i = port->rx_dma_buf.head; i < port->rx_dma_buf.tail; i++)
- async_unwrap_char(dev, &self->stats, &self->rx_buff, port->rx_dma_buf.buf[i]);
-}
-
-static void bfin_sir_rx_dma_timeout(struct timer_list *t)
-{
- struct bfin_sir_port *port = from_timer(port, t, rx_dma_timer);
- struct net_device *dev = port->dev;
- struct bfin_sir_self *self = netdev_priv(dev);
-
- int x_pos, pos;
- unsigned long flags;
-
- spin_lock_irqsave(&self->lock, flags);
- x_pos = DMA_SIR_RX_XCNT - get_dma_curr_xcount(port->rx_dma_channel);
- if (x_pos == DMA_SIR_RX_XCNT)
- x_pos = 0;
-
- pos = port->rx_dma_nrows * DMA_SIR_RX_XCNT + x_pos;
-
- if (pos > port->rx_dma_buf.tail) {
- port->rx_dma_buf.tail = pos;
- bfin_sir_dma_rx_chars(dev);
- port->rx_dma_buf.head = port->rx_dma_buf.tail;
- }
- spin_unlock_irqrestore(&self->lock, flags);
-}
-
-static irqreturn_t bfin_sir_dma_rx_int(int irq, void *dev_id)
-{
- struct net_device *dev = dev_id;
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
- unsigned short irqstat;
-
- spin_lock(&self->lock);
-
- port->rx_dma_nrows++;
- port->rx_dma_buf.tail = DMA_SIR_RX_XCNT * port->rx_dma_nrows;
- bfin_sir_dma_rx_chars(dev);
- if (port->rx_dma_nrows >= DMA_SIR_RX_YCNT) {
- port->rx_dma_nrows = 0;
- port->rx_dma_buf.tail = 0;
- }
- port->rx_dma_buf.head = port->rx_dma_buf.tail;
-
- irqstat = get_dma_curr_irqstat(port->rx_dma_channel);
- clear_dma_irqstat(port->rx_dma_channel);
- spin_unlock(&self->lock);
-
- mod_timer(&port->rx_dma_timer, jiffies + DMA_SIR_RX_FLUSH_JIFS);
- return IRQ_HANDLED;
-}
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-static int bfin_sir_startup(struct bfin_sir_port *port, struct net_device *dev)
-{
-#ifdef CONFIG_SIR_BFIN_DMA
- dma_addr_t dma_handle;
-#endif /* CONFIG_SIR_BFIN_DMA */
-
- if (request_dma(port->rx_dma_channel, "BFIN_UART_RX") < 0) {
- dev_warn(&dev->dev, "Unable to attach SIR RX DMA channel\n");
- return -EBUSY;
- }
-
- if (request_dma(port->tx_dma_channel, "BFIN_UART_TX") < 0) {
- dev_warn(&dev->dev, "Unable to attach SIR TX DMA channel\n");
- free_dma(port->rx_dma_channel);
- return -EBUSY;
- }
-
-#ifdef CONFIG_SIR_BFIN_DMA
-
- set_dma_callback(port->rx_dma_channel, bfin_sir_dma_rx_int, dev);
- set_dma_callback(port->tx_dma_channel, bfin_sir_dma_tx_int, dev);
-
- port->rx_dma_buf.buf = dma_alloc_coherent(NULL, PAGE_SIZE,
- &dma_handle, GFP_DMA);
- port->rx_dma_buf.head = 0;
- port->rx_dma_buf.tail = 0;
- port->rx_dma_nrows = 0;
-
- set_dma_config(port->rx_dma_channel,
- set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
- INTR_ON_ROW, DIMENSION_2D,
- DATA_SIZE_8, DMA_SYNC_RESTART));
- set_dma_x_count(port->rx_dma_channel, DMA_SIR_RX_XCNT);
- set_dma_x_modify(port->rx_dma_channel, 1);
- set_dma_y_count(port->rx_dma_channel, DMA_SIR_RX_YCNT);
- set_dma_y_modify(port->rx_dma_channel, 1);
- set_dma_start_addr(port->rx_dma_channel, (unsigned long)port->rx_dma_buf.buf);
- enable_dma(port->rx_dma_channel);
-
-
-#else
-
- if (request_irq(port->irq, bfin_sir_rx_int, 0, "BFIN_SIR_RX", dev)) {
- dev_warn(&dev->dev, "Unable to attach SIR RX interrupt\n");
- return -EBUSY;
- }
-
- if (request_irq(port->irq+1, bfin_sir_tx_int, 0, "BFIN_SIR_TX", dev)) {
- dev_warn(&dev->dev, "Unable to attach SIR TX interrupt\n");
- free_irq(port->irq, dev);
- return -EBUSY;
- }
-#endif
-
- return 0;
-}
-
-static void bfin_sir_shutdown(struct bfin_sir_port *port, struct net_device *dev)
-{
- unsigned short val;
-
- bfin_sir_stop_rx(port);
-
- val = UART_GET_GCTL(port);
- val &= ~(UCEN | UMOD_MASK | RPOLC);
- UART_PUT_GCTL(port, val);
-
-#ifdef CONFIG_SIR_BFIN_DMA
- disable_dma(port->tx_dma_channel);
- disable_dma(port->rx_dma_channel);
- del_timer(&(port->rx_dma_timer));
- dma_free_coherent(NULL, PAGE_SIZE, port->rx_dma_buf.buf, 0);
-#else
- free_irq(port->irq+1, dev);
- free_irq(port->irq, dev);
-#endif
- free_dma(port->tx_dma_channel);
- free_dma(port->rx_dma_channel);
-}
-
-#ifdef CONFIG_PM
-static int bfin_sir_suspend(struct platform_device *pdev, pm_message_t state)
-{
- struct bfin_sir_port *sir_port;
- struct net_device *dev;
- struct bfin_sir_self *self;
-
- sir_port = platform_get_drvdata(pdev);
- if (!sir_port)
- return 0;
-
- dev = sir_port->dev;
- self = netdev_priv(dev);
- if (self->open) {
- flush_work(&self->work);
- bfin_sir_shutdown(self->sir_port, dev);
- netif_device_detach(dev);
- }
-
- return 0;
-}
-static int bfin_sir_resume(struct platform_device *pdev)
-{
- struct bfin_sir_port *sir_port;
- struct net_device *dev;
- struct bfin_sir_self *self;
- struct bfin_sir_port *port;
-
- sir_port = platform_get_drvdata(pdev);
- if (!sir_port)
- return 0;
-
- dev = sir_port->dev;
- self = netdev_priv(dev);
- port = self->sir_port;
- if (self->open) {
- if (self->newspeed) {
- self->speed = self->newspeed;
- self->newspeed = 0;
- }
- bfin_sir_startup(port, dev);
- bfin_sir_set_speed(port, 9600);
- bfin_sir_enable_rx(port);
- netif_device_attach(dev);
- }
- return 0;
-}
-#else
-#define bfin_sir_suspend NULL
-#define bfin_sir_resume NULL
-#endif
-
-static void bfin_sir_send_work(struct work_struct *work)
-{
- struct bfin_sir_self *self = container_of(work, struct bfin_sir_self, work);
- struct net_device *dev = self->sir_port->dev;
- struct bfin_sir_port *port = self->sir_port;
- unsigned short val;
- int tx_cnt = 10;
-
- while (bfin_sir_is_receiving(dev) && --tx_cnt)
- turnaround_delay(self->mtt);
-
- bfin_sir_stop_rx(port);
-
- /* To avoid losting RX interrupt, we reset IR function before
- * sending data. We also can set the speed, which will
- * reset all the UART.
- */
- val = UART_GET_GCTL(port);
- val &= ~(UMOD_MASK | RPOLC);
- UART_PUT_GCTL(port, val);
- SSYNC();
- val |= UMOD_IRDA | RPOLC;
- UART_PUT_GCTL(port, val);
- SSYNC();
- /* bfin_sir_set_speed(port, self->speed); */
-
-#ifdef CONFIG_SIR_BFIN_DMA
- bfin_sir_dma_tx_chars(dev);
-#endif
- bfin_sir_enable_tx(port);
- netif_trans_update(dev);
-}
-
-static int bfin_sir_hard_xmit(struct sk_buff *skb, struct net_device *dev)
-{
- struct bfin_sir_self *self = netdev_priv(dev);
- int speed = irda_get_next_speed(skb);
-
- netif_stop_queue(dev);
-
- self->mtt = irda_get_mtt(skb);
-
- if (speed != self->speed && speed != -1)
- self->newspeed = speed;
-
- self->tx_buff.data = self->tx_buff.head;
- if (skb->len == 0)
- self->tx_buff.len = 0;
- else
- self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, self->tx_buff.truesize);
-
- schedule_work(&self->work);
- dev_kfree_skb(skb);
-
- return 0;
-}
-
-static int bfin_sir_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
-{
- struct if_irda_req *rq = (struct if_irda_req *)ifreq;
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
- int ret = 0;
-
- switch (cmd) {
- case SIOCSBANDWIDTH:
- if (capable(CAP_NET_ADMIN)) {
- if (self->open) {
- ret = bfin_sir_set_speed(port, rq->ifr_baudrate);
- bfin_sir_enable_rx(port);
- } else {
- dev_warn(&dev->dev, "SIOCSBANDWIDTH: !netif_running\n");
- ret = 0;
- }
- }
- break;
-
- case SIOCSMEDIABUSY:
- ret = -EPERM;
- if (capable(CAP_NET_ADMIN)) {
- irda_device_set_media_busy(dev, TRUE);
- ret = 0;
- }
- break;
-
- case SIOCGRECEIVING:
- rq->ifr_receiving = bfin_sir_is_receiving(dev);
- break;
-
- default:
- ret = -EOPNOTSUPP;
- break;
- }
-
- return ret;
-}
-
-static struct net_device_stats *bfin_sir_stats(struct net_device *dev)
-{
- struct bfin_sir_self *self = netdev_priv(dev);
-
- return &self->stats;
-}
-
-static int bfin_sir_open(struct net_device *dev)
-{
- struct bfin_sir_self *self = netdev_priv(dev);
- struct bfin_sir_port *port = self->sir_port;
- int err;
-
- self->newspeed = 0;
- self->speed = 9600;
-
- spin_lock_init(&self->lock);
-
- err = bfin_sir_startup(port, dev);
- if (err)
- goto err_startup;
-
- bfin_sir_set_speed(port, 9600);
-
- self->irlap = irlap_open(dev, &self->qos, DRIVER_NAME);
- if (!self->irlap) {
- err = -ENOMEM;
- goto err_irlap;
- }
-
- INIT_WORK(&self->work, bfin_sir_send_work);
-
- /*
- * Now enable the interrupt then start the queue
- */
- self->open = 1;
- bfin_sir_enable_rx(port);
-
- netif_start_queue(dev);
-
- return 0;
-
-err_irlap:
- self->open = 0;
- bfin_sir_shutdown(port, dev);
-err_startup:
- return err;
-}
-
-static int bfin_sir_stop(struct net_device *dev)
-{
- struct bfin_sir_self *self = netdev_priv(dev);
-
- flush_work(&self->work);
- bfin_sir_shutdown(self->sir_port, dev);
-
- if (self->rxskb) {
- dev_kfree_skb(self->rxskb);
- self->rxskb = NULL;
- }
-
- /* Stop IrLAP */
- if (self->irlap) {
- irlap_close(self->irlap);
- self->irlap = NULL;
- }
-
- netif_stop_queue(dev);
- self->open = 0;
-
- return 0;
-}
-
-static int bfin_sir_init_iobuf(iobuff_t *io, int size)
-{
- io->head = kmalloc(size, GFP_KERNEL);
- if (!io->head)
- return -ENOMEM;
- io->truesize = size;
- io->in_frame = FALSE;
- io->state = OUTSIDE_FRAME;
- io->data = io->head;
- return 0;
-}
-
-static const struct net_device_ops bfin_sir_ndo = {
- .ndo_open = bfin_sir_open,
- .ndo_stop = bfin_sir_stop,
- .ndo_start_xmit = bfin_sir_hard_xmit,
- .ndo_do_ioctl = bfin_sir_ioctl,
- .ndo_get_stats = bfin_sir_stats,
-};
-
-static int bfin_sir_probe(struct platform_device *pdev)
-{
- struct net_device *dev;
- struct bfin_sir_self *self;
- unsigned int baudrate_mask;
- struct bfin_sir_port *sir_port;
- int err;
-
- if (pdev->id >= 0 && pdev->id < ARRAY_SIZE(per) && \
- per[pdev->id][3] == pdev->id) {
- err = peripheral_request_list(per[pdev->id], DRIVER_NAME);
- if (err)
- return err;
- } else {
- dev_err(&pdev->dev, "Invalid pdev id, please check board file\n");
- return -ENODEV;
- }
-
- err = -ENOMEM;
- sir_port = kmalloc(sizeof(*sir_port), GFP_KERNEL);
- if (!sir_port)
- goto err_mem_0;
-
- bfin_sir_init_ports(sir_port, pdev);
-
- dev = alloc_irdadev(sizeof(*self));
- if (!dev)
- goto err_mem_1;
-
- self = netdev_priv(dev);
- self->dev = &pdev->dev;
- self->sir_port = sir_port;
- sir_port->dev = dev;
-
- err = bfin_sir_init_iobuf(&self->rx_buff, IRDA_SKB_MAX_MTU);
- if (err)
- goto err_mem_2;
- err = bfin_sir_init_iobuf(&self->tx_buff, IRDA_SIR_MAX_FRAME);
- if (err)
- goto err_mem_3;
-
- dev->netdev_ops = &bfin_sir_ndo;
- dev->irq = sir_port->irq;
-
- irda_init_max_qos_capabilies(&self->qos);
-
- baudrate_mask = IR_9600;
-
- switch (max_rate) {
- case 115200:
- baudrate_mask |= IR_115200;
- case 57600:
- baudrate_mask |= IR_57600;
- case 38400:
- baudrate_mask |= IR_38400;
- case 19200:
- baudrate_mask |= IR_19200;
- case 9600:
- break;
- default:
- dev_warn(&pdev->dev, "Invalid maximum baud rate, using 9600\n");
- }
-
- self->qos.baud_rate.bits &= baudrate_mask;
-
- self->qos.min_turn_time.bits = 1; /* 10 ms or more */
-
- irda_qos_bits_to_value(&self->qos);
-
- err = register_netdev(dev);
-
- if (err) {
- kfree(self->tx_buff.head);
-err_mem_3:
- kfree(self->rx_buff.head);
-err_mem_2:
- free_netdev(dev);
-err_mem_1:
- kfree(sir_port);
-err_mem_0:
- peripheral_free_list(per[pdev->id]);
- } else
- platform_set_drvdata(pdev, sir_port);
-
- return err;
-}
-
-static int bfin_sir_remove(struct platform_device *pdev)
-{
- struct bfin_sir_port *sir_port;
- struct net_device *dev = NULL;
- struct bfin_sir_self *self;
-
- sir_port = platform_get_drvdata(pdev);
- if (!sir_port)
- return 0;
- dev = sir_port->dev;
- self = netdev_priv(dev);
- unregister_netdev(dev);
- kfree(self->tx_buff.head);
- kfree(self->rx_buff.head);
- free_netdev(dev);
- kfree(sir_port);
-
- return 0;
-}
-
-static struct platform_driver bfin_ir_driver = {
- .probe = bfin_sir_probe,
- .remove = bfin_sir_remove,
- .suspend = bfin_sir_suspend,
- .resume = bfin_sir_resume,
- .driver = {
- .name = DRIVER_NAME,
- },
-};
-
-module_platform_driver(bfin_ir_driver);
-
-module_param(max_rate, int, 0);
-MODULE_PARM_DESC(max_rate, "Maximum baud rate (115200, 57600, 38400, 19200, 9600)");
-
-MODULE_AUTHOR("Graf Yang <graf.yang@analog.com>");
-MODULE_DESCRIPTION("Blackfin IrDA driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/staging/irda/drivers/bfin_sir.h b/drivers/staging/irda/drivers/bfin_sir.h
deleted file mode 100644
index d47cf14..0000000
--- a/drivers/staging/irda/drivers/bfin_sir.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <linux/module.h>
-#include <linux/netdevice.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/slab.h>
-
-#include <net/irda/irda.h>
-#include <net/irda/wrapper.h>
-#include <net/irda/irda_device.h>
-
-#include <asm/irq.h>
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-#undef DRIVER_NAME
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
- char *buf;
- int head;
- int tail;
-};
-#endif
-
-struct bfin_sir_port {
- unsigned char __iomem *membase;
- unsigned int irq;
- unsigned int lsr;
- unsigned long clk;
- struct net_device *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
- int tx_done;
- struct dma_rx_buf rx_dma_buf;
- struct timer_list rx_dma_timer;
- int rx_dma_nrows;
-#endif
- unsigned int tx_dma_channel;
- unsigned int rx_dma_channel;
-};
-
-struct bfin_sir_port_res {
- unsigned long base_addr;
- int irq;
- unsigned int rx_dma_channel;
- unsigned int tx_dma_channel;
-};
-
-struct bfin_sir_self {
- struct bfin_sir_port *sir_port;
- spinlock_t lock;
- unsigned int open;
- int speed;
- int newspeed;
-
- struct sk_buff *txskb;
- struct sk_buff *rxskb;
- struct net_device_stats stats;
- struct device *dev;
- struct irlap_cb *irlap;
- struct qos_info qos;
-
- iobuff_t tx_buff;
- iobuff_t rx_buff;
-
- struct work_struct work;
- int mtt;
-};
-
-#define DRIVER_NAME "bfin_sir"
-
-#include <asm/bfin_serial.h>
-
-static const unsigned short per[][4] = {
- /* rx pin tx pin NULL uart_number */
- {P_UART0_RX, P_UART0_TX, 0, 0},
- {P_UART1_RX, P_UART1_TX, 0, 1},
- {P_UART2_RX, P_UART2_TX, 0, 2},
- {P_UART3_RX, P_UART3_TX, 0, 3},
-};
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 17/28] usb: Remove Blackfin USB support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (14 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 16/28] irda: Remove Blackfin IRDA support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 18/28] crypto: Remove Blackfin crypto support Aaron Wu
` (10 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin USB support
---
drivers/usb/gadget/function/f_uac1_legacy.c | 2 -
drivers/usb/gadget/function/u_uac1_legacy.c | 2 -
drivers/usb/gadget/function/u_uac1_legacy.h | 2 -
drivers/usb/gadget/legacy/audio.c | 2 -
drivers/usb/host/isp1362.h | 45 --
drivers/usb/musb/Kconfig | 12 +-
drivers/usb/musb/Makefile | 1 -
drivers/usb/musb/blackfin.c | 623 ----------------------------
drivers/usb/musb/blackfin.h | 81 ----
drivers/usb/musb/musb_core.c | 7 +-
drivers/usb/musb/musb_core.h | 42 --
drivers/usb/musb/musb_debugfs.c | 2 -
drivers/usb/musb/musb_dma.h | 11 -
drivers/usb/musb/musb_gadget.c | 32 --
drivers/usb/musb/musb_regs.h | 182 --------
drivers/usb/musb/musbhsdma.c | 5 -
drivers/usb/musb/musbhsdma.h | 90 ----
drivers/usb/serial/ftdi_sio_ids.h | 8 -
include/linux/usb/musb.h | 7 -
19 files changed, 3 insertions(+), 1153 deletions(-)
delete mode 100644 drivers/usb/musb/blackfin.c
delete mode 100644 drivers/usb/musb/blackfin.h
diff --git a/drivers/usb/gadget/function/f_uac1_legacy.c b/drivers/usb/gadget/function/f_uac1_legacy.c
index 04f4b28..24c086b 100644
--- a/drivers/usb/gadget/function/f_uac1_legacy.c
+++ b/drivers/usb/gadget/function/f_uac1_legacy.c
@@ -4,8 +4,6 @@
*
* Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
* Copyright (C) 2008 Analog Devices, Inc
- *
- * Enter bugs at http://blackfin.uclinux.org/
*/
#include <linux/slab.h>
diff --git a/drivers/usb/gadget/function/u_uac1_legacy.c b/drivers/usb/gadget/function/u_uac1_legacy.c
index cbc868d..5393e5c 100644
--- a/drivers/usb/gadget/function/u_uac1_legacy.c
+++ b/drivers/usb/gadget/function/u_uac1_legacy.c
@@ -4,8 +4,6 @@
*
* Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
* Copyright (C) 2008 Analog Devices, Inc
- *
- * Enter bugs at http://blackfin.uclinux.org/
*/
#include <linux/kernel.h>
diff --git a/drivers/usb/gadget/function/u_uac1_legacy.h b/drivers/usb/gadget/function/u_uac1_legacy.h
index dd69e40..5c1bdf4 100644
--- a/drivers/usb/gadget/function/u_uac1_legacy.h
+++ b/drivers/usb/gadget/function/u_uac1_legacy.h
@@ -4,8 +4,6 @@
*
* Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
* Copyright (C) 2008 Analog Devices, Inc
- *
- * Enter bugs at http://blackfin.uclinux.org/
*/
#ifndef __U_UAC1_LEGACY_H
diff --git a/drivers/usb/gadget/legacy/audio.c b/drivers/usb/gadget/legacy/audio.c
index 7b11dce..dd81fd5 100644
--- a/drivers/usb/gadget/legacy/audio.c
+++ b/drivers/usb/gadget/legacy/audio.c
@@ -4,8 +4,6 @@
*
* Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
* Copyright (C) 2008 Analog Devices, Inc
- *
- * Enter bugs at http://blackfin.uclinux.org/
*/
/* #define VERBOSE_DEBUG */
diff --git a/drivers/usb/host/isp1362.h b/drivers/usb/host/isp1362.h
index da79e36..891402a 100644
--- a/drivers/usb/host/isp1362.h
+++ b/drivers/usb/host/isp1362.h
@@ -6,49 +6,6 @@
*/
/* ------------------------------------------------------------------------- */
-/*
- * Platform specific compile time options
- */
-#if defined(CONFIG_BLACKFIN)
-
-#include <linux/io.h>
-#define USE_32BIT 0
-#define MAX_ROOT_PORTS 2
-#define USE_PLATFORM_DELAY 0
-#define USE_NDELAY 1
-
-#define DUMMY_DELAY_ACCESS \
- do { \
- bfin_read16(ASYNC_BANK0_BASE); \
- bfin_read16(ASYNC_BANK0_BASE); \
- bfin_read16(ASYNC_BANK0_BASE); \
- } while (0)
-
-#undef insw
-#undef outsw
-
-#define insw delayed_insw
-#define outsw delayed_outsw
-
-static inline void delayed_outsw(unsigned int addr, void *buf, int len)
-{
- unsigned short *bp = (unsigned short *)buf;
- while (len--) {
- DUMMY_DELAY_ACCESS;
- outw(*bp++, addr);
- }
-}
-
-static inline void delayed_insw(unsigned int addr, void *buf, int len)
-{
- unsigned short *bp = (unsigned short *)buf;
- while (len--) {
- DUMMY_DELAY_ACCESS;
- *bp++ = inw(addr);
- }
-}
-
-#else
#define MAX_ROOT_PORTS 2
@@ -60,8 +17,6 @@ static inline void delayed_insw(unsigned int addr, void *buf, int len)
#define DUMMY_DELAY_ACCESS do {} while (0)
-#endif
-
/* ------------------------------------------------------------------------- */
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 5506a9c..a424cc5 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -18,9 +18,6 @@ config USB_MUSB_HDRC
Texas Instruments families using this IP include DaVinci
(35x, 644x ...), OMAP 243x, OMAP 3, and TUSB 6010.
- Analog Devices parts using this IP include Blackfin BF54x,
- BF525 and BF527.
-
Allwinner SoCs using this IP include A10, A13, A20, ...
If you do not know what this is, please say N.
@@ -87,7 +84,7 @@ config USB_MUSB_DA8XX
config USB_MUSB_TUSB6010
tristate "TUSB6010"
depends on HAS_IOMEM
- depends on (ARCH_OMAP2PLUS || COMPILE_TEST) && !BLACKFIN
+ depends on (ARCH_OMAP2PLUS || COMPILE_TEST)
depends on NOP_USB_XCEIV = USB_MUSB_HDRC # both built-in or both modules
config USB_MUSB_OMAP2PLUS
@@ -107,11 +104,6 @@ config USB_MUSB_DSPS
depends on ARCH_OMAP2PLUS || COMPILE_TEST
depends on OF_IRQ
-config USB_MUSB_BLACKFIN
- tristate "Blackfin"
- depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
- depends on NOP_USB_XCEIV
-
config USB_MUSB_UX500
tristate "Ux500 platforms"
depends on ARCH_U8500 || COMPILE_TEST
@@ -149,7 +141,7 @@ config USB_UX500_DMA
config USB_INVENTRA_DMA
bool 'Inventra'
- depends on USB_MUSB_OMAP2PLUS || USB_MUSB_BLACKFIN
+ depends on USB_MUSB_OMAP2PLUS
help
Enable DMA transfers using Mentor's engine.
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 79d4d54..3a88c79 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
obj-$(CONFIG_USB_MUSB_TUSB6010) += tusb6010.o
obj-$(CONFIG_USB_MUSB_DAVINCI) += davinci.o
obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
-obj-$(CONFIG_USB_MUSB_BLACKFIN) += blackfin.o
obj-$(CONFIG_USB_MUSB_UX500) += ux500.o
obj-$(CONFIG_USB_MUSB_JZ4740) += jz4740.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
deleted file mode 100644
index 0a98dcd..0000000
--- a/drivers/usb/musb/blackfin.c
+++ /dev/null
@@ -1,623 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * MUSB OTG controller driver for Blackfin Processors
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/list.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/prefetch.h>
-#include <linux/usb/usb_phy_generic.h>
-
-#include <asm/cacheflush.h>
-
-#include "musb_core.h"
-#include "musbhsdma.h"
-#include "blackfin.h"
-
-struct bfin_glue {
- struct device *dev;
- struct platform_device *musb;
- struct platform_device *phy;
-};
-#define glue_to_musb(g) platform_get_drvdata(g->musb)
-
-static u32 bfin_fifo_offset(u8 epnum)
-{
- return USB_OFFSET(USB_EP0_FIFO) + (epnum * 8);
-}
-
-static u8 bfin_readb(const void __iomem *addr, unsigned offset)
-{
- return (u8)(bfin_read16(addr + offset));
-}
-
-static u16 bfin_readw(const void __iomem *addr, unsigned offset)
-{
- return bfin_read16(addr + offset);
-}
-
-static u32 bfin_readl(const void __iomem *addr, unsigned offset)
-{
- return (u32)(bfin_read16(addr + offset));
-}
-
-static void bfin_writeb(void __iomem *addr, unsigned offset, u8 data)
-{
- bfin_write16(addr + offset, (u16)data);
-}
-
-static void bfin_writew(void __iomem *addr, unsigned offset, u16 data)
-{
- bfin_write16(addr + offset, data);
-}
-
-static void bfin_writel(void __iomem *addr, unsigned offset, u32 data)
-{
- bfin_write16(addr + offset, (u16)data);
-}
-
-/*
- * Load an endpoint's FIFO
- */
-static void bfin_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
-{
- struct musb *musb = hw_ep->musb;
- void __iomem *fifo = hw_ep->fifo;
- void __iomem *epio = hw_ep->regs;
- u8 epnum = hw_ep->epnum;
-
- prefetch((u8 *)src);
-
- musb_writew(epio, MUSB_TXCOUNT, len);
-
- dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
- hw_ep->epnum, fifo, len, src, epio);
-
- dump_fifo_data(src, len);
-
- if (!ANOMALY_05000380 && epnum != 0) {
- u16 dma_reg;
-
- flush_dcache_range((unsigned long)src,
- (unsigned long)(src + len));
-
- /* Setup DMA address register */
- dma_reg = (u32)src;
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
- SSYNC();
-
- dma_reg = (u32)src >> 16;
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
- SSYNC();
-
- /* Setup DMA count register */
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
- SSYNC();
-
- /* Enable the DMA */
- dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
- SSYNC();
-
- /* Wait for complete */
- while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
- cpu_relax();
-
- /* acknowledge dma interrupt */
- bfin_write_USB_DMA_INTERRUPT(1 << epnum);
- SSYNC();
-
- /* Reset DMA */
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
- SSYNC();
- } else {
- SSYNC();
-
- if (unlikely((unsigned long)src & 0x01))
- outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
- else
- outsw((unsigned long)fifo, src, (len + 1) >> 1);
- }
-}
-/*
- * Unload an endpoint's FIFO
- */
-static void bfin_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
-{
- struct musb *musb = hw_ep->musb;
- void __iomem *fifo = hw_ep->fifo;
- u8 epnum = hw_ep->epnum;
-
- if (ANOMALY_05000467 && epnum != 0) {
- u16 dma_reg;
-
- invalidate_dcache_range((unsigned long)dst,
- (unsigned long)(dst + len));
-
- /* Setup DMA address register */
- dma_reg = (u32)dst;
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
- SSYNC();
-
- dma_reg = (u32)dst >> 16;
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
- SSYNC();
-
- /* Setup DMA count register */
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
- SSYNC();
-
- /* Enable the DMA */
- dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
- SSYNC();
-
- /* Wait for complete */
- while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
- cpu_relax();
-
- /* acknowledge dma interrupt */
- bfin_write_USB_DMA_INTERRUPT(1 << epnum);
- SSYNC();
-
- /* Reset DMA */
- bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
- SSYNC();
- } else {
- SSYNC();
- /* Read the last byte of packet with odd size from address fifo + 4
- * to trigger 1 byte access to EP0 FIFO.
- */
- if (len == 1)
- *dst = (u8)inw((unsigned long)fifo + 4);
- else {
- if (unlikely((unsigned long)dst & 0x01))
- insw_8((unsigned long)fifo, dst, len >> 1);
- else
- insw((unsigned long)fifo, dst, len >> 1);
-
- if (len & 0x01)
- *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
- }
- }
- dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
- 'R', hw_ep->epnum, fifo, len, dst);
-
- dump_fifo_data(dst, len);
-}
-
-static irqreturn_t blackfin_interrupt(int irq, void *__hci)
-{
- unsigned long flags;
- irqreturn_t retval = IRQ_NONE;
- struct musb *musb = __hci;
-
- spin_lock_irqsave(&musb->lock, flags);
-
- musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
- musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
- musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
-
- if (musb->int_usb || musb->int_tx || musb->int_rx) {
- musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
- musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
- musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
- retval = musb_interrupt(musb);
- }
-
- /* Start sampling ID pin, when plug is removed from MUSB */
- if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
- || musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) ||
- (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
- mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
- musb->a_wait_bcon = TIMER_DELAY;
- }
-
- spin_unlock_irqrestore(&musb->lock, flags);
-
- return retval;
-}
-
-static void musb_conn_timer_handler(struct timer_list *t)
-{
- struct musb *musb = from_timer(musb, t, dev_timer);
- unsigned long flags;
- u16 val;
- static u8 toggle;
-
- spin_lock_irqsave(&musb->lock, flags);
- switch (musb->xceiv->otg->state) {
- case OTG_STATE_A_IDLE:
- case OTG_STATE_A_WAIT_BCON:
- /* Start a new session */
- val = musb_readw(musb->mregs, MUSB_DEVCTL);
- val &= ~MUSB_DEVCTL_SESSION;
- musb_writew(musb->mregs, MUSB_DEVCTL, val);
- val |= MUSB_DEVCTL_SESSION;
- musb_writew(musb->mregs, MUSB_DEVCTL, val);
- /* Check if musb is host or peripheral. */
- val = musb_readw(musb->mregs, MUSB_DEVCTL);
-
- if (!(val & MUSB_DEVCTL_BDEVICE)) {
- gpio_set_value(musb->config->gpio_vrsel, 1);
- musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
- } else {
- gpio_set_value(musb->config->gpio_vrsel, 0);
- /* Ignore VBUSERROR and SUSPEND IRQ */
- val = musb_readb(musb->mregs, MUSB_INTRUSBE);
- val &= ~MUSB_INTR_VBUSERROR;
- musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
-
- val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
- musb_writeb(musb->mregs, MUSB_INTRUSB, val);
- musb->xceiv->otg->state = OTG_STATE_B_IDLE;
- }
- mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
- break;
- case OTG_STATE_B_IDLE:
- /*
- * Start a new session. It seems that MUSB needs taking
- * some time to recognize the type of the plug inserted?
- */
- val = musb_readw(musb->mregs, MUSB_DEVCTL);
- val |= MUSB_DEVCTL_SESSION;
- musb_writew(musb->mregs, MUSB_DEVCTL, val);
- val = musb_readw(musb->mregs, MUSB_DEVCTL);
-
- if (!(val & MUSB_DEVCTL_BDEVICE)) {
- gpio_set_value(musb->config->gpio_vrsel, 1);
- musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
- } else {
- gpio_set_value(musb->config->gpio_vrsel, 0);
-
- /* Ignore VBUSERROR and SUSPEND IRQ */
- val = musb_readb(musb->mregs, MUSB_INTRUSBE);
- val &= ~MUSB_INTR_VBUSERROR;
- musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
-
- val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
- musb_writeb(musb->mregs, MUSB_INTRUSB, val);
-
- /* Toggle the Soft Conn bit, so that we can response to
- * the inserting of either A-plug or B-plug.
- */
- if (toggle) {
- val = musb_readb(musb->mregs, MUSB_POWER);
- val &= ~MUSB_POWER_SOFTCONN;
- musb_writeb(musb->mregs, MUSB_POWER, val);
- toggle = 0;
- } else {
- val = musb_readb(musb->mregs, MUSB_POWER);
- val |= MUSB_POWER_SOFTCONN;
- musb_writeb(musb->mregs, MUSB_POWER, val);
- toggle = 1;
- }
- /* The delay time is set to 1/4 second by default,
- * shortening it, if accelerating A-plug detection
- * is needed in OTG mode.
- */
- mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY / 4);
- }
- break;
- default:
- dev_dbg(musb->controller, "%s state not handled\n",
- usb_otg_state_string(musb->xceiv->otg->state));
- break;
- }
- spin_unlock_irqrestore(&musb->lock, flags);
-
- dev_dbg(musb->controller, "state is %s\n",
- usb_otg_state_string(musb->xceiv->otg->state));
-}
-
-static void bfin_musb_enable(struct musb *musb)
-{
- /* REVISIT is this really correct ? */
-}
-
-static void bfin_musb_disable(struct musb *musb)
-{
-}
-
-static void bfin_musb_set_vbus(struct musb *musb, int is_on)
-{
- int value = musb->config->gpio_vrsel_active;
- if (!is_on)
- value = !value;
- gpio_set_value(musb->config->gpio_vrsel, value);
-
- dev_dbg(musb->controller, "VBUS %s, devctl %02x "
- /* otg %3x conf %08x prcm %08x */ "\n",
- usb_otg_state_string(musb->xceiv->otg->state),
- musb_readb(musb->mregs, MUSB_DEVCTL));
-}
-
-static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
-{
- return 0;
-}
-
-static int bfin_musb_vbus_status(struct musb *musb)
-{
- return 0;
-}
-
-static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
-{
- return -EIO;
-}
-
-static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
- u16 packet_sz, u8 *mode,
- dma_addr_t *dma_addr, u32 *len)
-{
- struct musb_dma_channel *musb_channel = channel->private_data;
-
- /*
- * Anomaly 05000450 might cause data corruption when using DMA
- * MODE 1 transmits with short packet. So to work around this,
- * we truncate all MODE 1 transfers down to a multiple of the
- * max packet size, and then do the last short packet transfer
- * (if there is any) using MODE 0.
- */
- if (ANOMALY_05000450) {
- if (musb_channel->transmit && *mode == 1)
- *len = *len - (*len % packet_sz);
- }
-
- return 0;
-}
-
-static void bfin_musb_reg_init(struct musb *musb)
-{
- if (ANOMALY_05000346) {
- bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
- SSYNC();
- }
-
- if (ANOMALY_05000347) {
- bfin_write_USB_APHY_CNTRL(0x0);
- SSYNC();
- }
-
- /* Configure PLL oscillator register */
- bfin_write_USB_PLLOSC_CTRL(0x3080 |
- ((480/musb->config->clkin) << 1));
- SSYNC();
-
- bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
- SSYNC();
-
- bfin_write_USB_EP_NI0_RXMAXP(64);
- SSYNC();
-
- bfin_write_USB_EP_NI0_TXMAXP(64);
- SSYNC();
-
- /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
- bfin_write_USB_GLOBINTR(0x7);
- SSYNC();
-
- bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
- EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
- EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
- EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
- EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
- SSYNC();
-}
-
-static int bfin_musb_init(struct musb *musb)
-{
-
- /*
- * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
- * and OTG HOST modes, while rev 1.1 and greater require PE7 to
- * be low for DEVICE mode and high for HOST mode. We set it high
- * here because we are in host mode
- */
-
- if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
- printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
- musb->config->gpio_vrsel);
- return -ENODEV;
- }
- gpio_direction_output(musb->config->gpio_vrsel, 0);
-
- musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
- if (IS_ERR_OR_NULL(musb->xceiv)) {
- gpio_free(musb->config->gpio_vrsel);
- return -EPROBE_DEFER;
- }
-
- bfin_musb_reg_init(musb);
-
- timer_setup(&musb->dev_timer, musb_conn_timer_handler, 0);
-
- musb->xceiv->set_power = bfin_musb_set_power;
-
- musb->isr = blackfin_interrupt;
- musb->double_buffer_not_ok = true;
-
- return 0;
-}
-
-static int bfin_musb_exit(struct musb *musb)
-{
- gpio_free(musb->config->gpio_vrsel);
- usb_put_phy(musb->xceiv);
-
- return 0;
-}
-
-static const struct musb_platform_ops bfin_ops = {
- .quirks = MUSB_DMA_INVENTRA,
- .init = bfin_musb_init,
- .exit = bfin_musb_exit,
-
- .fifo_offset = bfin_fifo_offset,
- .readb = bfin_readb,
- .writeb = bfin_writeb,
- .readw = bfin_readw,
- .writew = bfin_writew,
- .readl = bfin_readl,
- .writel = bfin_writel,
- .fifo_mode = 2,
- .read_fifo = bfin_read_fifo,
- .write_fifo = bfin_write_fifo,
-#ifdef CONFIG_USB_INVENTRA_DMA
- .dma_init = musbhs_dma_controller_create,
- .dma_exit = musbhs_dma_controller_destroy,
-#endif
- .enable = bfin_musb_enable,
- .disable = bfin_musb_disable,
-
- .set_mode = bfin_musb_set_mode,
-
- .vbus_status = bfin_musb_vbus_status,
- .set_vbus = bfin_musb_set_vbus,
-
- .adjust_channel_params = bfin_musb_adjust_channel_params,
-};
-
-static u64 bfin_dmamask = DMA_BIT_MASK(32);
-
-static int bfin_probe(struct platform_device *pdev)
-{
- struct resource musb_resources[2];
- struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
- struct platform_device *musb;
- struct bfin_glue *glue;
-
- int ret = -ENOMEM;
-
- glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
- if (!glue)
- goto err0;
-
- musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
- if (!musb)
- goto err0;
-
- musb->dev.parent = &pdev->dev;
- musb->dev.dma_mask = &bfin_dmamask;
- musb->dev.coherent_dma_mask = bfin_dmamask;
-
- glue->dev = &pdev->dev;
- glue->musb = musb;
-
- pdata->platform_ops = &bfin_ops;
-
- glue->phy = usb_phy_generic_register();
- if (IS_ERR(glue->phy))
- goto err1;
- platform_set_drvdata(pdev, glue);
-
- memset(musb_resources, 0x00, sizeof(*musb_resources) *
- ARRAY_SIZE(musb_resources));
-
- musb_resources[0].name = pdev->resource[0].name;
- musb_resources[0].start = pdev->resource[0].start;
- musb_resources[0].end = pdev->resource[0].end;
- musb_resources[0].flags = pdev->resource[0].flags;
-
- musb_resources[1].name = pdev->resource[1].name;
- musb_resources[1].start = pdev->resource[1].start;
- musb_resources[1].end = pdev->resource[1].end;
- musb_resources[1].flags = pdev->resource[1].flags;
-
- ret = platform_device_add_resources(musb, musb_resources,
- ARRAY_SIZE(musb_resources));
- if (ret) {
- dev_err(&pdev->dev, "failed to add resources\n");
- goto err2;
- }
-
- ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
- if (ret) {
- dev_err(&pdev->dev, "failed to add platform_data\n");
- goto err2;
- }
-
- ret = platform_device_add(musb);
- if (ret) {
- dev_err(&pdev->dev, "failed to register musb device\n");
- goto err2;
- }
-
- return 0;
-
-err2:
- usb_phy_generic_unregister(glue->phy);
-
-err1:
- platform_device_put(musb);
-
-err0:
- return ret;
-}
-
-static int bfin_remove(struct platform_device *pdev)
-{
- struct bfin_glue *glue = platform_get_drvdata(pdev);
-
- platform_device_unregister(glue->musb);
- usb_phy_generic_unregister(glue->phy);
-
- return 0;
-}
-
-static int __maybe_unused bfin_suspend(struct device *dev)
-{
- struct bfin_glue *glue = dev_get_drvdata(dev);
- struct musb *musb = glue_to_musb(glue);
-
- if (is_host_active(musb))
- /*
- * During hibernate gpio_vrsel will change from high to low
- * low which will generate wakeup event resume the system
- * immediately. Set it to 0 before hibernate to avoid this
- * wakeup event.
- */
- gpio_set_value(musb->config->gpio_vrsel, 0);
-
- return 0;
-}
-
-static int __maybe_unused bfin_resume(struct device *dev)
-{
- struct bfin_glue *glue = dev_get_drvdata(dev);
- struct musb *musb = glue_to_musb(glue);
-
- bfin_musb_reg_init(musb);
-
- return 0;
-}
-
-static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
-
-static struct platform_driver bfin_driver = {
- .probe = bfin_probe,
- .remove = bfin_remove,
- .driver = {
- .name = "musb-blackfin",
- .pm = &bfin_pm_ops,
- },
-};
-
-MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
-MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
-MODULE_LICENSE("GPL v2");
-module_platform_driver(bfin_driver);
diff --git a/drivers/usb/musb/blackfin.h b/drivers/usb/musb/blackfin.h
deleted file mode 100644
index 5b14991..0000000
--- a/drivers/usb/musb/blackfin.h
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2007 by Analog Devices, Inc.
- */
-
-#ifndef __MUSB_BLACKFIN_H__
-#define __MUSB_BLACKFIN_H__
-
-/*
- * Blackfin specific definitions
- */
-
-/* Anomalies notes:
- *
- * 05000450 - USB DMA Mode 1 Short Packet Data Corruption:
- * MUSB driver is designed to transfer buffer of N * maxpacket size
- * in DMA mode 1 and leave the rest of the data to the next
- * transfer in DMA mode 0, so we never transmit a short packet in
- * DMA mode 1.
- *
- * 05000463 - This anomaly doesn't affect this driver since it
- * never uses L1 or L2 memory as data destination.
- *
- * 05000464 - This anomaly doesn't affect this driver since it
- * never uses L1 or L2 memory as data source.
- *
- * 05000465 - The anomaly can be seen when SCLK is over 100 MHz, and there is
- * no way to workaround for bulk endpoints. Since the wMaxPackSize
- * of bulk is less than or equal to 512, while the fifo size of
- * endpoint 5, 6, 7 is 1024, the double buffer mode is enabled
- * automatically when these endpoints are used for bulk OUT.
- *
- * 05000466 - This anomaly doesn't affect this driver since it never mixes
- * concurrent DMA and core accesses to the TX endpoint FIFOs.
- *
- * 05000467 - The workaround for this anomaly will introduce another
- * anomaly - 05000465.
- */
-
-/* The Mentor USB DMA engine on BF52x (silicon v0.0 and v0.1) seems to be
- * unstable in host mode. This may be caused by Anomaly 05000380. After
- * digging out the root cause, we will change this number accordingly.
- * So, need to either use silicon v0.2+ or disable DMA mode in MUSB.
- */
-#if ANOMALY_05000380 && defined(CONFIG_BF52x) && \
- !defined(CONFIG_MUSB_PIO_ONLY)
-# error "Please use PIO mode in MUSB driver on bf52x chip v0.0 and v0.1"
-#endif
-
-#undef DUMP_FIFO_DATA
-#ifdef DUMP_FIFO_DATA
-static void dump_fifo_data(u8 *buf, u16 len)
-{
- u8 *tmp = buf;
- int i;
-
- for (i = 0; i < len; i++) {
- if (!(i % 16) && i)
- pr_debug("\n");
- pr_debug("%02x ", *tmp++);
- }
- pr_debug("\n");
-}
-#else
-#define dump_fifo_data(buf, len) do {} while (0)
-#endif
-
-
-#define USB_DMA_BASE USB_DMA_INTERRUPT
-#define USB_DMAx_CTRL 0x04
-#define USB_DMAx_ADDR_LOW 0x08
-#define USB_DMAx_ADDR_HIGH 0x0C
-#define USB_DMAx_COUNT_LOW 0x10
-#define USB_DMAx_COUNT_HIGH 0x14
-
-#define USB_DMA_REG(ep, reg) (USB_DMA_BASE + 0x20 * ep + reg)
-
-/* Almost 1 second */
-#define TIMER_DELAY (1 * HZ)
-
-#endif /* __MUSB_BLACKFIN_H__ */
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index eef4ad5..1348658 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -126,7 +126,6 @@ EXPORT_SYMBOL_GPL(musb_get_mode);
/*-------------------------------------------------------------------------*/
-#ifndef CONFIG_BLACKFIN
static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
{
void __iomem *addr = phy->io_priv;
@@ -208,10 +207,6 @@ static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
return ret;
}
-#else
-#define musb_ulpi_read NULL
-#define musb_ulpi_write NULL
-#endif
static struct usb_phy_io_ops musb_ulpi_access = {
.read = musb_ulpi_read,
@@ -2171,7 +2166,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
* - initializes musb->xceiv, usually by otg_get_phy()
* - stops powering VBUS
*
- * There are various transceiver configurations. Blackfin,
+ * There are various transceiver configurations.
* DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
* external/discrete ones in various flavors (twl4030 family,
* isp1504, non-OTG, etc) mostly hooking up through ULPI.
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 385841e..d91bb28 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -414,19 +414,6 @@ struct musb {
struct usb_gadget_driver *gadget_driver; /* its driver */
struct usb_hcd *hcd; /* the usb hcd */
- /*
- * FIXME: Remove this flag.
- *
- * This is only added to allow Blackfin to work
- * with current driver. For some unknown reason
- * Blackfin doesn't work with double buffering
- * and that's enabled by default.
- *
- * We added this flag to forcefully disable double
- * buffering until we get it working.
- */
- unsigned double_buffer_not_ok:1;
-
const struct musb_hdrc_config *config;
int xceiv_old_state;
@@ -467,34 +454,6 @@ static inline char *musb_ep_xfertype_string(u8 type)
return s;
}
-#ifdef CONFIG_BLACKFIN
-static inline int musb_read_fifosize(struct musb *musb,
- struct musb_hw_ep *hw_ep, u8 epnum)
-{
- musb->nr_endpoints++;
- musb->epmask |= (1 << epnum);
-
- if (epnum < 5) {
- hw_ep->max_packet_sz_tx = 128;
- hw_ep->max_packet_sz_rx = 128;
- } else {
- hw_ep->max_packet_sz_tx = 1024;
- hw_ep->max_packet_sz_rx = 1024;
- }
- hw_ep->is_shared_fifo = false;
-
- return 0;
-}
-
-static inline void musb_configure_ep0(struct musb *musb)
-{
- musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
- musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
- musb->endpoints[0].is_shared_fifo = true;
-}
-
-#else
-
static inline int musb_read_fifosize(struct musb *musb,
struct musb_hw_ep *hw_ep, u8 epnum)
{
@@ -531,7 +490,6 @@ static inline void musb_configure_ep0(struct musb *musb)
musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
musb->endpoints[0].is_shared_fifo = true;
}
-#endif /* CONFIG_BLACKFIN */
/***************************** Glue it together *****************************/
diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c
index 7cf5a1b..7dac456 100644
--- a/drivers/usb/musb/musb_debugfs.c
+++ b/drivers/usb/musb/musb_debugfs.c
@@ -70,7 +70,6 @@ static const struct musb_register_map musb_regmap[] = {
{ "DMA_CNTLch7", 0x274, 16 },
{ "DMA_ADDRch7", 0x278, 32 },
{ "DMA_COUNTch7", 0x27C, 32 },
-#ifndef CONFIG_BLACKFIN
{ "ConfigData", MUSB_CONFIGDATA,8 },
{ "BabbleCtl", MUSB_BABBLE_CTL,8 },
{ "TxFIFOsz", MUSB_TXFIFOSZ, 8 },
@@ -79,7 +78,6 @@ static const struct musb_register_map musb_regmap[] = {
{ "RxFIFOadd", MUSB_RXFIFOADD, 16 },
{ "EPInfo", MUSB_EPINFO, 8 },
{ "RAMInfo", MUSB_RAMINFO, 8 },
-#endif
{ } /* Terminating Entry */
};
diff --git a/drivers/usb/musb/musb_dma.h b/drivers/usb/musb/musb_dma.h
index a4241f4..0fc8cd0 100644
--- a/drivers/usb/musb/musb_dma.h
+++ b/drivers/usb/musb/musb_dma.h
@@ -80,17 +80,6 @@ struct musb_hw_ep;
#define is_cppi_enabled(musb) 0
#endif
-/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
- * Only allow DMA mode 1 to be used when the USB will actually generate the
- * interrupts we expect.
- */
-#ifdef CONFIG_BLACKFIN
-# undef USE_MODE1
-# if !ANOMALY_05000456
-# define USE_MODE1
-# endif
-#endif
-
/*
* DMA channel status ... updated by the dma controller driver whenever that
* status changes, and protected by the overall controller spinlock.
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index 293e5b8..1e40a81 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -1680,39 +1680,7 @@ static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
return 0;
}
-#ifdef CONFIG_BLACKFIN
-static struct usb_ep *musb_match_ep(struct usb_gadget *g,
- struct usb_endpoint_descriptor *desc,
- struct usb_ss_ep_comp_descriptor *ep_comp)
-{
- struct usb_ep *ep = NULL;
-
- switch (usb_endpoint_type(desc)) {
- case USB_ENDPOINT_XFER_ISOC:
- case USB_ENDPOINT_XFER_BULK:
- if (usb_endpoint_dir_in(desc))
- ep = gadget_find_ep_by_name(g, "ep5in");
- else
- ep = gadget_find_ep_by_name(g, "ep6out");
- break;
- case USB_ENDPOINT_XFER_INT:
- if (usb_endpoint_dir_in(desc))
- ep = gadget_find_ep_by_name(g, "ep1in");
- else
- ep = gadget_find_ep_by_name(g, "ep2out");
- break;
- default:
- break;
- }
-
- if (ep && usb_gadget_ep_match_desc(g, ep, desc, ep_comp))
- return ep;
-
- return NULL;
-}
-#else
#define musb_match_ep NULL
-#endif
static int musb_gadget_start(struct usb_gadget *g,
struct usb_gadget_driver *driver);
diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h
index a4beba1..8846662 100644
--- a/drivers/usb/musb/musb_regs.h
+++ b/drivers/usb/musb/musb_regs.h
@@ -195,8 +195,6 @@
#define MUSB_HUBADDR_MULTI_TT 0x80
-#ifndef CONFIG_BLACKFIN
-
/*
* Common USB registers
*/
@@ -416,184 +414,4 @@ static inline u8 musb_read_txhubport(struct musb *musb, u8 epnum)
musb->io.busctl_offset(epnum, MUSB_TXHUBPORT));
}
-#else /* CONFIG_BLACKFIN */
-
-#define USB_BASE USB_FADDR
-#define USB_OFFSET(reg) (reg - USB_BASE)
-
-/*
- * Common USB registers
- */
-#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
-#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
-#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
-#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
-#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
-#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
-#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
-#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
-#define MUSB_FRAME USB_OFFSET(USB_FRAME)
-#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
-#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
-
-/*
- * Additional Control Registers
- */
-
-#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
-
-#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
-#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
-#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
-#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
-#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
-
-/* Offsets to endpoint registers */
-#define MUSB_TXMAXP 0x00
-#define MUSB_TXCSR 0x04
-#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
-#define MUSB_RXMAXP 0x08
-#define MUSB_RXCSR 0x0C
-#define MUSB_RXCOUNT 0x10
-#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
-#define MUSB_TXTYPE 0x14
-#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
-#define MUSB_TXINTERVAL 0x18
-#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
-#define MUSB_RXTYPE 0x1C
-#define MUSB_RXINTERVAL 0x20
-#define MUSB_TXCOUNT 0x28
-
-/* Offsets to endpoint registers in indexed model (using INDEX register) */
-#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
- (0x40 + (_offset))
-
-/* Offsets to endpoint registers in flat models */
-#define MUSB_FLAT_OFFSET(_epnum, _offset) \
- (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
-
-/* Not implemented - HW has separate Tx/Rx FIFO */
-#define MUSB_TXCSR_MODE 0x0000
-
-static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
-{
-}
-
-static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
-{
-}
-
-static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
-{
-}
-
-static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
-{
-}
-
-static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
-{
-}
-
-static inline u8 musb_read_txfifosz(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u16 musb_read_txfifoadd(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u8 musb_read_rxfifosz(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u8 musb_read_configdata(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u16 musb_read_hwvers(void __iomem *mbase)
-{
- /*
- * This register is invisible on Blackfin, actually the MUSB
- * RTL version of Blackfin is 1.9, so just hardcode its value.
- */
- return MUSB_HWVERS_1900;
-}
-
-static inline void musb_write_rxfunaddr(void __iomem *mbase, u8 epnum,
- u8 qh_addr_req)
-{
-}
-
-static inline void musb_write_rxhubaddr(void __iomem *mbase, u8 epnum,
- u8 qh_h_addr_reg)
-{
-}
-
-static inline void musb_write_rxhubport(void __iomem *mbase, u8 epnum,
- u8 qh_h_port_reg)
-{
-}
-
-static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
- u8 qh_addr_reg)
-{
-}
-
-static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
- u8 qh_addr_reg)
-{
-}
-
-static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
- u8 qh_h_port_reg)
-{
-}
-
-static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-#endif /* CONFIG_BLACKFIN */
-
#endif /* __MUSB_REGS_H__ */
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index 21fb9e6..4389fc3 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -235,11 +235,6 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
-#ifdef CONFIG_BLACKFIN
- /* Clear DMA interrupt flags */
- musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
-#endif
-
if (!int_hsdma) {
musb_dbg(musb, "spurious DMA irq");
diff --git a/drivers/usb/musb/musbhsdma.h b/drivers/usb/musb/musbhsdma.h
index 44f7983..51bc12f 100644
--- a/drivers/usb/musb/musbhsdma.h
+++ b/drivers/usb/musb/musbhsdma.h
@@ -6,8 +6,6 @@
* Copyright (C) 2005-2007 by Texas Instruments
*/
-#ifndef CONFIG_BLACKFIN
-
#define MUSB_HSDMA_BASE 0x200
#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
#define MUSB_HSDMA_CONTROL 0x4
@@ -34,68 +32,6 @@
musb_writel(mbase, \
MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
len)
-#else
-
-#define MUSB_HSDMA_BASE 0x400
-#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
-#define MUSB_HSDMA_CONTROL 0x04
-#define MUSB_HSDMA_ADDR_LOW 0x08
-#define MUSB_HSDMA_ADDR_HIGH 0x0C
-#define MUSB_HSDMA_COUNT_LOW 0x10
-#define MUSB_HSDMA_COUNT_HIGH 0x14
-
-#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
- (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
-
-static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
-{
- u32 addr = musb_readw(mbase,
- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
-
- addr = addr << 16;
-
- addr |= musb_readw(mbase,
- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
-
- return addr;
-}
-
-static inline void musb_write_hsdma_addr(void __iomem *mbase,
- u8 bchannel, dma_addr_t dma_addr)
-{
- musb_writew(mbase,
- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
- dma_addr);
- musb_writew(mbase,
- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
- (dma_addr >> 16));
-}
-
-static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
-{
- u32 count = musb_readw(mbase,
- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));
-
- count = count << 16;
-
- count |= musb_readw(mbase,
- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW));
-
- return count;
-}
-
-static inline void musb_write_hsdma_count(void __iomem *mbase,
- u8 bchannel, u32 len)
-{
- musb_writew(mbase,
- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),len);
- musb_writew(mbase,
- MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
- (len >> 16));
-}
-
-#endif /* CONFIG_BLACKFIN */
-
/* control register (16-bit): */
#define MUSB_HSDMA_ENABLE_SHIFT 0
#define MUSB_HSDMA_TRANSMIT_SHIFT 1
diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h
index 5d19e67..9eb908a 100644
--- a/include/linux/usb/musb.h
+++ b/include/linux/usb/musb.h
@@ -89,13 +89,6 @@ struct musb_hdrc_config {
u8 ram_bits; /* ram address size */
struct musb_hdrc_eps_bits *eps_bits __deprecated;
-#ifdef CONFIG_BLACKFIN
- /* A GPIO controlling VRSEL in Blackfin */
- unsigned int gpio_vrsel;
- unsigned int gpio_vrsel_active;
- /* musb CLKIN in Blackfin in MHZ */
- unsigned char clkin;
-#endif
u32 maximum_speed;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 18/28] crypto: Remove Blackfin crypto support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (15 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 17/28] usb: Remove Blackfin USB support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 19/28] ata: Remove Blackfin PATA support Aaron Wu
` (9 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin crypto support
---
crypto/testmgr.c | 6 -
crypto/testmgr.h | 88 ------
drivers/crypto/Kconfig | 7 -
drivers/crypto/Makefile | 1 -
drivers/crypto/bfin_crc.c | 743 ----------------------------------------------
drivers/crypto/bfin_crc.h | 124 --------
6 files changed, 969 deletions(-)
delete mode 100644 drivers/crypto/bfin_crc.c
delete mode 100644 drivers/crypto/bfin_crc.h
diff --git a/crypto/testmgr.c b/crypto/testmgr.c
index d5e23a1..8dacd69 100644
--- a/crypto/testmgr.c
+++ b/crypto/testmgr.c
@@ -3070,12 +3070,6 @@ static const struct alg_test_desc alg_test_descs[] = {
.hash = __VECS(ghash_tv_template)
}
}, {
- .alg = "hmac(crc32)",
- .test = alg_test_hash,
- .suite = {
- .hash = __VECS(bfin_crc_tv_template)
- }
- }, {
.alg = "hmac(md5)",
.test = alg_test_hash,
.suite = {
diff --git a/crypto/testmgr.h b/crypto/testmgr.h
index 6044f69..021e953 100644
--- a/crypto/testmgr.h
+++ b/crypto/testmgr.h
@@ -35045,94 +35045,6 @@ static const struct hash_testvec crc32c_tv_template[] = {
}
};
-/*
- * Blakcifn CRC test vectors
- */
-static const struct hash_testvec bfin_crc_tv_template[] = {
- {
- .psize = 0,
- .digest = "\x00\x00\x00\x00",
- },
- {
- .key = "\x87\xa9\xcb\xed",
- .ksize = 4,
- .psize = 0,
- .digest = "\x87\xa9\xcb\xed",
- },
- {
- .key = "\xff\xff\xff\xff",
- .ksize = 4,
- .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08"
- "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
- "\x11\x12\x13\x14\x15\x16\x17\x18"
- "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
- "\x21\x22\x23\x24\x25\x26\x27\x28",
- .psize = 40,
- .digest = "\x84\x0c\x8d\xa2",
- },
- {
- .key = "\xff\xff\xff\xff",
- .ksize = 4,
- .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08"
- "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
- "\x11\x12\x13\x14\x15\x16\x17\x18"
- "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
- "\x21\x22\x23\x24\x25\x26",
- .psize = 38,
- .digest = "\x8c\x58\xec\xb7",
- },
- {
- .key = "\xff\xff\xff\xff",
- .ksize = 4,
- .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08"
- "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
- "\x11\x12\x13\x14\x15\x16\x17\x18"
- "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
- "\x21\x22\x23\x24\x25\x26\x27",
- .psize = 39,
- .digest = "\xdc\x50\x28\x7b",
- },
- {
- .key = "\xff\xff\xff\xff",
- .ksize = 4,
- .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08"
- "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
- "\x11\x12\x13\x14\x15\x16\x17\x18"
- "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
- "\x21\x22\x23\x24\x25\x26\x27\x28"
- "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30"
- "\x31\x32\x33\x34\x35\x36\x37\x38"
- "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40"
- "\x41\x42\x43\x44\x45\x46\x47\x48"
- "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50"
- "\x51\x52\x53\x54\x55\x56\x57\x58"
- "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60"
- "\x61\x62\x63\x64\x65\x66\x67\x68"
- "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70"
- "\x71\x72\x73\x74\x75\x76\x77\x78"
- "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80"
- "\x81\x82\x83\x84\x85\x86\x87\x88"
- "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90"
- "\x91\x92\x93\x94\x95\x96\x97\x98"
- "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0"
- "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8"
- "\xa9\xaa\xab\xac\xad\xae\xaf\xb0"
- "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8"
- "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0"
- "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8"
- "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0"
- "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8"
- "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0"
- "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8"
- "\xe9\xea\xeb\xec\xed\xee\xef\xf0",
- .psize = 240,
- .digest = "\x10\x19\x4a\x5c",
- .np = 2,
- .tap = { 31, 209 }
- },
-
-};
-
static const struct comp_testvec lz4_comp_tv_template[] = {
{
.inlen = 255,
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 4b741b8..c17368c 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -464,13 +464,6 @@ if CRYPTO_DEV_UX500
source "drivers/crypto/ux500/Kconfig"
endif # if CRYPTO_DEV_UX500
-config CRYPTO_DEV_BFIN_CRC
- tristate "Support for Blackfin CRC hardware"
- depends on BF60x
- help
- Newer Blackfin processors have CRC hardware. Select this if you
- want to use the Blackfin CRC module.
-
config CRYPTO_DEV_ATMEL_AUTHENC
tristate "Support for Atmel IPSEC/SSL hw accelerator"
depends on HAS_DMA
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 2513d13..c08622b 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -3,7 +3,6 @@ obj-$(CONFIG_CRYPTO_DEV_ATMEL_AES) += atmel-aes.o
obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA) += atmel-sha.o
obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o
obj-$(CONFIG_CRYPTO_DEV_ATMEL_ECC) += atmel-ecc.o
-obj-$(CONFIG_CRYPTO_DEV_BFIN_CRC) += bfin_crc.o
obj-$(CONFIG_CRYPTO_DEV_CAVIUM_ZIP) += cavium/
obj-$(CONFIG_CRYPTO_DEV_CCP) += ccp/
obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/
diff --git a/drivers/crypto/bfin_crc.c b/drivers/crypto/bfin_crc.c
deleted file mode 100644
index bfbf8bf..0000000
--- a/drivers/crypto/bfin_crc.c
+++ /dev/null
@@ -1,743 +0,0 @@
-/*
- * Cryptographic API.
- *
- * Support Blackfin CRC HW acceleration.
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/scatterlist.h>
-#include <linux/dma-mapping.h>
-#include <linux/delay.h>
-#include <linux/crypto.h>
-#include <linux/cryptohash.h>
-#include <crypto/scatterwalk.h>
-#include <crypto/algapi.h>
-#include <crypto/hash.h>
-#include <crypto/internal/hash.h>
-#include <asm/unaligned.h>
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-#include <asm/io.h>
-
-#include "bfin_crc.h"
-
-#define CRC_CCRYPTO_QUEUE_LENGTH 5
-
-#define DRIVER_NAME "bfin-hmac-crc"
-#define CHKSUM_DIGEST_SIZE 4
-#define CHKSUM_BLOCK_SIZE 1
-
-#define CRC_MAX_DMA_DESC 100
-
-#define CRC_CRYPTO_STATE_UPDATE 1
-#define CRC_CRYPTO_STATE_FINALUPDATE 2
-#define CRC_CRYPTO_STATE_FINISH 3
-
-struct bfin_crypto_crc {
- struct list_head list;
- struct device *dev;
- spinlock_t lock;
-
- int irq;
- int dma_ch;
- u32 poly;
- struct crc_register *regs;
-
- struct ahash_request *req; /* current request in operation */
- struct dma_desc_array *sg_cpu; /* virt addr of sg dma descriptors */
- dma_addr_t sg_dma; /* phy addr of sg dma descriptors */
- u8 *sg_mid_buf;
- dma_addr_t sg_mid_dma; /* phy addr of sg mid buffer */
-
- struct tasklet_struct done_task;
- struct crypto_queue queue; /* waiting requests */
-
- u8 busy:1; /* crc device in operation flag */
-};
-
-static struct bfin_crypto_crc_list {
- struct list_head dev_list;
- spinlock_t lock;
-} crc_list;
-
-struct bfin_crypto_crc_reqctx {
- struct bfin_crypto_crc *crc;
-
- unsigned int total; /* total request bytes */
- size_t sg_buflen; /* bytes for this update */
- unsigned int sg_nents;
- struct scatterlist *sg; /* sg list head for this update*/
- struct scatterlist bufsl[2]; /* chained sg list */
-
- size_t bufnext_len;
- size_t buflast_len;
- u8 bufnext[CHKSUM_DIGEST_SIZE]; /* extra bytes for next udpate */
- u8 buflast[CHKSUM_DIGEST_SIZE]; /* extra bytes from last udpate */
-
- u8 flag;
-};
-
-struct bfin_crypto_crc_ctx {
- struct bfin_crypto_crc *crc;
- u32 key;
-};
-
-/*
- * get element in scatter list by given index
- */
-static struct scatterlist *sg_get(struct scatterlist *sg_list, unsigned int nents,
- unsigned int index)
-{
- struct scatterlist *sg = NULL;
- int i;
-
- for_each_sg(sg_list, sg, nents, i)
- if (i == index)
- break;
-
- return sg;
-}
-
-static int bfin_crypto_crc_init_hw(struct bfin_crypto_crc *crc, u32 key)
-{
- writel(0, &crc->regs->datacntrld);
- writel(MODE_CALC_CRC << OPMODE_OFFSET, &crc->regs->control);
- writel(key, &crc->regs->curresult);
-
- /* setup CRC interrupts */
- writel(CMPERRI | DCNTEXPI, &crc->regs->status);
- writel(CMPERRI | DCNTEXPI, &crc->regs->intrenset);
-
- return 0;
-}
-
-static int bfin_crypto_crc_init(struct ahash_request *req)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
- struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
- struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
- struct bfin_crypto_crc *crc;
-
- dev_dbg(ctx->crc->dev, "crc_init\n");
- spin_lock_bh(&crc_list.lock);
- list_for_each_entry(crc, &crc_list.dev_list, list) {
- crc_ctx->crc = crc;
- break;
- }
- spin_unlock_bh(&crc_list.lock);
-
- if (sg_nents(req->src) > CRC_MAX_DMA_DESC) {
- dev_dbg(ctx->crc->dev, "init: requested sg list is too big > %d\n",
- CRC_MAX_DMA_DESC);
- return -EINVAL;
- }
-
- ctx->crc = crc;
- ctx->bufnext_len = 0;
- ctx->buflast_len = 0;
- ctx->sg_buflen = 0;
- ctx->total = 0;
- ctx->flag = 0;
-
- /* init crc results */
- put_unaligned_le32(crc_ctx->key, req->result);
-
- dev_dbg(ctx->crc->dev, "init: digest size: %d\n",
- crypto_ahash_digestsize(tfm));
-
- return bfin_crypto_crc_init_hw(crc, crc_ctx->key);
-}
-
-static void bfin_crypto_crc_config_dma(struct bfin_crypto_crc *crc)
-{
- struct scatterlist *sg;
- struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(crc->req);
- int i = 0, j = 0;
- unsigned long dma_config;
- unsigned int dma_count;
- unsigned int dma_addr;
- unsigned int mid_dma_count = 0;
- int dma_mod;
-
- dma_map_sg(crc->dev, ctx->sg, ctx->sg_nents, DMA_TO_DEVICE);
-
- for_each_sg(ctx->sg, sg, ctx->sg_nents, j) {
- dma_addr = sg_dma_address(sg);
- /* deduce extra bytes in last sg */
- if (sg_is_last(sg))
- dma_count = sg_dma_len(sg) - ctx->bufnext_len;
- else
- dma_count = sg_dma_len(sg);
-
- if (mid_dma_count) {
- /* Append last middle dma buffer to 4 bytes with first
- bytes in current sg buffer. Move addr of current
- sg and deduce the length of current sg.
- */
- memcpy(crc->sg_mid_buf +(i << 2) + mid_dma_count,
- sg_virt(sg),
- CHKSUM_DIGEST_SIZE - mid_dma_count);
- dma_addr += CHKSUM_DIGEST_SIZE - mid_dma_count;
- dma_count -= CHKSUM_DIGEST_SIZE - mid_dma_count;
-
- dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 |
- DMAEN | PSIZE_32 | WDSIZE_32;
-
- /* setup new dma descriptor for next middle dma */
- crc->sg_cpu[i].start_addr = crc->sg_mid_dma + (i << 2);
- crc->sg_cpu[i].cfg = dma_config;
- crc->sg_cpu[i].x_count = 1;
- crc->sg_cpu[i].x_modify = CHKSUM_DIGEST_SIZE;
- dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
- "cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
- i, crc->sg_cpu[i].start_addr,
- crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
- crc->sg_cpu[i].x_modify);
- i++;
- }
-
- dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | DMAEN | PSIZE_32;
- /* chop current sg dma len to multiple of 32 bits */
- mid_dma_count = dma_count % 4;
- dma_count &= ~0x3;
-
- if (dma_addr % 4 == 0) {
- dma_config |= WDSIZE_32;
- dma_count >>= 2;
- dma_mod = 4;
- } else if (dma_addr % 2 == 0) {
- dma_config |= WDSIZE_16;
- dma_count >>= 1;
- dma_mod = 2;
- } else {
- dma_config |= WDSIZE_8;
- dma_mod = 1;
- }
-
- crc->sg_cpu[i].start_addr = dma_addr;
- crc->sg_cpu[i].cfg = dma_config;
- crc->sg_cpu[i].x_count = dma_count;
- crc->sg_cpu[i].x_modify = dma_mod;
- dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
- "cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
- i, crc->sg_cpu[i].start_addr,
- crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
- crc->sg_cpu[i].x_modify);
- i++;
-
- if (mid_dma_count) {
- /* copy extra bytes to next middle dma buffer */
- memcpy(crc->sg_mid_buf + (i << 2),
- (u8*)sg_virt(sg) + (dma_count << 2),
- mid_dma_count);
- }
- }
-
- dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | DMAEN | PSIZE_32 | WDSIZE_32;
- /* For final update req, append the buffer for next update as well*/
- if (ctx->bufnext_len && (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE ||
- ctx->flag == CRC_CRYPTO_STATE_FINISH)) {
- crc->sg_cpu[i].start_addr = dma_map_single(crc->dev, ctx->bufnext,
- CHKSUM_DIGEST_SIZE, DMA_TO_DEVICE);
- crc->sg_cpu[i].cfg = dma_config;
- crc->sg_cpu[i].x_count = 1;
- crc->sg_cpu[i].x_modify = CHKSUM_DIGEST_SIZE;
- dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
- "cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
- i, crc->sg_cpu[i].start_addr,
- crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
- crc->sg_cpu[i].x_modify);
- i++;
- }
-
- if (i == 0)
- return;
-
- /* Set the last descriptor to stop mode */
- crc->sg_cpu[i - 1].cfg &= ~(DMAFLOW | NDSIZE);
- crc->sg_cpu[i - 1].cfg |= DI_EN;
- set_dma_curr_desc_addr(crc->dma_ch, (unsigned long *)crc->sg_dma);
- set_dma_x_count(crc->dma_ch, 0);
- set_dma_x_modify(crc->dma_ch, 0);
- set_dma_config(crc->dma_ch, dma_config);
-}
-
-static int bfin_crypto_crc_handle_queue(struct bfin_crypto_crc *crc,
- struct ahash_request *req)
-{
- struct crypto_async_request *async_req, *backlog;
- struct bfin_crypto_crc_reqctx *ctx;
- struct scatterlist *sg;
- int ret = 0;
- int nsg, i, j;
- unsigned int nextlen;
- unsigned long flags;
- u32 reg;
-
- spin_lock_irqsave(&crc->lock, flags);
- if (req)
- ret = ahash_enqueue_request(&crc->queue, req);
- if (crc->busy) {
- spin_unlock_irqrestore(&crc->lock, flags);
- return ret;
- }
- backlog = crypto_get_backlog(&crc->queue);
- async_req = crypto_dequeue_request(&crc->queue);
- if (async_req)
- crc->busy = 1;
- spin_unlock_irqrestore(&crc->lock, flags);
-
- if (!async_req)
- return ret;
-
- if (backlog)
- backlog->complete(backlog, -EINPROGRESS);
-
- req = ahash_request_cast(async_req);
- crc->req = req;
- ctx = ahash_request_ctx(req);
- ctx->sg = NULL;
- ctx->sg_buflen = 0;
- ctx->sg_nents = 0;
-
- dev_dbg(crc->dev, "handling new req, flag=%u, nbytes: %d\n",
- ctx->flag, req->nbytes);
-
- if (ctx->flag == CRC_CRYPTO_STATE_FINISH) {
- if (ctx->bufnext_len == 0) {
- crc->busy = 0;
- return 0;
- }
-
- /* Pack last crc update buffer to 32bit */
- memset(ctx->bufnext + ctx->bufnext_len, 0,
- CHKSUM_DIGEST_SIZE - ctx->bufnext_len);
- } else {
- /* Pack small data which is less than 32bit to buffer for next update. */
- if (ctx->bufnext_len + req->nbytes < CHKSUM_DIGEST_SIZE) {
- memcpy(ctx->bufnext + ctx->bufnext_len,
- sg_virt(req->src), req->nbytes);
- ctx->bufnext_len += req->nbytes;
- if (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE &&
- ctx->bufnext_len) {
- goto finish_update;
- } else {
- crc->busy = 0;
- return 0;
- }
- }
-
- if (ctx->bufnext_len) {
- /* Chain in extra bytes of last update */
- ctx->buflast_len = ctx->bufnext_len;
- memcpy(ctx->buflast, ctx->bufnext, ctx->buflast_len);
-
- nsg = ctx->sg_buflen ? 2 : 1;
- sg_init_table(ctx->bufsl, nsg);
- sg_set_buf(ctx->bufsl, ctx->buflast, ctx->buflast_len);
- if (nsg > 1)
- sg_chain(ctx->bufsl, nsg, req->src);
- ctx->sg = ctx->bufsl;
- } else
- ctx->sg = req->src;
-
- /* Chop crc buffer size to multiple of 32 bit */
- nsg = sg_nents(ctx->sg);
- ctx->sg_nents = nsg;
- ctx->sg_buflen = ctx->buflast_len + req->nbytes;
- ctx->bufnext_len = ctx->sg_buflen % 4;
- ctx->sg_buflen &= ~0x3;
-
- if (ctx->bufnext_len) {
- /* copy extra bytes to buffer for next update */
- memset(ctx->bufnext, 0, CHKSUM_DIGEST_SIZE);
- nextlen = ctx->bufnext_len;
- for (i = nsg - 1; i >= 0; i--) {
- sg = sg_get(ctx->sg, nsg, i);
- j = min(nextlen, sg_dma_len(sg));
- memcpy(ctx->bufnext + nextlen - j,
- sg_virt(sg) + sg_dma_len(sg) - j, j);
- if (j == sg_dma_len(sg))
- ctx->sg_nents--;
- nextlen -= j;
- if (nextlen == 0)
- break;
- }
- }
- }
-
-finish_update:
- if (ctx->bufnext_len && (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE ||
- ctx->flag == CRC_CRYPTO_STATE_FINISH))
- ctx->sg_buflen += CHKSUM_DIGEST_SIZE;
-
- /* set CRC data count before start DMA */
- writel(ctx->sg_buflen >> 2, &crc->regs->datacnt);
-
- /* setup and enable CRC DMA */
- bfin_crypto_crc_config_dma(crc);
-
- /* finally kick off CRC operation */
- reg = readl(&crc->regs->control);
- writel(reg | BLKEN, &crc->regs->control);
-
- return -EINPROGRESS;
-}
-
-static int bfin_crypto_crc_update(struct ahash_request *req)
-{
- struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
-
- if (!req->nbytes)
- return 0;
-
- dev_dbg(ctx->crc->dev, "crc_update\n");
- ctx->total += req->nbytes;
- ctx->flag = CRC_CRYPTO_STATE_UPDATE;
-
- return bfin_crypto_crc_handle_queue(ctx->crc, req);
-}
-
-static int bfin_crypto_crc_final(struct ahash_request *req)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
- struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
- struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
-
- dev_dbg(ctx->crc->dev, "crc_final\n");
- ctx->flag = CRC_CRYPTO_STATE_FINISH;
- crc_ctx->key = 0;
-
- return bfin_crypto_crc_handle_queue(ctx->crc, req);
-}
-
-static int bfin_crypto_crc_finup(struct ahash_request *req)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
- struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
- struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
-
- dev_dbg(ctx->crc->dev, "crc_finishupdate\n");
- ctx->total += req->nbytes;
- ctx->flag = CRC_CRYPTO_STATE_FINALUPDATE;
- crc_ctx->key = 0;
-
- return bfin_crypto_crc_handle_queue(ctx->crc, req);
-}
-
-static int bfin_crypto_crc_digest(struct ahash_request *req)
-{
- int ret;
-
- ret = bfin_crypto_crc_init(req);
- if (ret)
- return ret;
-
- return bfin_crypto_crc_finup(req);
-}
-
-static int bfin_crypto_crc_setkey(struct crypto_ahash *tfm, const u8 *key,
- unsigned int keylen)
-{
- struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
-
- dev_dbg(crc_ctx->crc->dev, "crc_setkey\n");
- if (keylen != CHKSUM_DIGEST_SIZE) {
- crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
- return -EINVAL;
- }
-
- crc_ctx->key = get_unaligned_le32(key);
-
- return 0;
-}
-
-static int bfin_crypto_crc_cra_init(struct crypto_tfm *tfm)
-{
- struct bfin_crypto_crc_ctx *crc_ctx = crypto_tfm_ctx(tfm);
-
- crc_ctx->key = 0;
- crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
- sizeof(struct bfin_crypto_crc_reqctx));
-
- return 0;
-}
-
-static void bfin_crypto_crc_cra_exit(struct crypto_tfm *tfm)
-{
-}
-
-static struct ahash_alg algs = {
- .init = bfin_crypto_crc_init,
- .update = bfin_crypto_crc_update,
- .final = bfin_crypto_crc_final,
- .finup = bfin_crypto_crc_finup,
- .digest = bfin_crypto_crc_digest,
- .setkey = bfin_crypto_crc_setkey,
- .halg.digestsize = CHKSUM_DIGEST_SIZE,
- .halg.base = {
- .cra_name = "hmac(crc32)",
- .cra_driver_name = DRIVER_NAME,
- .cra_priority = 100,
- .cra_flags = CRYPTO_ALG_TYPE_AHASH |
- CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_OPTIONAL_KEY,
- .cra_blocksize = CHKSUM_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct bfin_crypto_crc_ctx),
- .cra_alignmask = 3,
- .cra_module = THIS_MODULE,
- .cra_init = bfin_crypto_crc_cra_init,
- .cra_exit = bfin_crypto_crc_cra_exit,
- }
-};
-
-static void bfin_crypto_crc_done_task(unsigned long data)
-{
- struct bfin_crypto_crc *crc = (struct bfin_crypto_crc *)data;
-
- bfin_crypto_crc_handle_queue(crc, NULL);
-}
-
-static irqreturn_t bfin_crypto_crc_handler(int irq, void *dev_id)
-{
- struct bfin_crypto_crc *crc = dev_id;
- u32 reg;
-
- if (readl(&crc->regs->status) & DCNTEXP) {
- writel(DCNTEXP, &crc->regs->status);
-
- /* prepare results */
- put_unaligned_le32(readl(&crc->regs->result),
- crc->req->result);
-
- reg = readl(&crc->regs->control);
- writel(reg & ~BLKEN, &crc->regs->control);
- crc->busy = 0;
-
- if (crc->req->base.complete)
- crc->req->base.complete(&crc->req->base, 0);
-
- tasklet_schedule(&crc->done_task);
-
- return IRQ_HANDLED;
- } else
- return IRQ_NONE;
-}
-
-#ifdef CONFIG_PM
-/**
- * bfin_crypto_crc_suspend - suspend crc device
- * @pdev: device being suspended
- * @state: requested suspend state
- */
-static int bfin_crypto_crc_suspend(struct platform_device *pdev, pm_message_t state)
-{
- struct bfin_crypto_crc *crc = platform_get_drvdata(pdev);
- int i = 100000;
-
- while ((readl(&crc->regs->control) & BLKEN) && --i)
- cpu_relax();
-
- if (i == 0)
- return -EBUSY;
-
- return 0;
-}
-#else
-# define bfin_crypto_crc_suspend NULL
-#endif
-
-#define bfin_crypto_crc_resume NULL
-
-/**
- * bfin_crypto_crc_probe - Initialize module
- *
- */
-static int bfin_crypto_crc_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct resource *res;
- struct bfin_crypto_crc *crc;
- unsigned int timeout = 100000;
- int ret;
-
- crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
- if (!crc) {
- dev_err(&pdev->dev, "fail to malloc bfin_crypto_crc\n");
- return -ENOMEM;
- }
-
- crc->dev = dev;
-
- INIT_LIST_HEAD(&crc->list);
- spin_lock_init(&crc->lock);
- tasklet_init(&crc->done_task, bfin_crypto_crc_done_task, (unsigned long)crc);
- crypto_init_queue(&crc->queue, CRC_CCRYPTO_QUEUE_LENGTH);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- crc->regs = devm_ioremap_resource(dev, res);
- if (IS_ERR((void *)crc->regs)) {
- dev_err(&pdev->dev, "Cannot map CRC IO\n");
- return PTR_ERR((void *)crc->regs);
- }
-
- crc->irq = platform_get_irq(pdev, 0);
- if (crc->irq < 0) {
- dev_err(&pdev->dev, "No CRC DCNTEXP IRQ specified\n");
- return -ENOENT;
- }
-
- ret = devm_request_irq(dev, crc->irq, bfin_crypto_crc_handler,
- IRQF_SHARED, dev_name(dev), crc);
- if (ret) {
- dev_err(&pdev->dev, "Unable to request blackfin crc irq\n");
- return ret;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (res == NULL) {
- dev_err(&pdev->dev, "No CRC DMA channel specified\n");
- return -ENOENT;
- }
- crc->dma_ch = res->start;
-
- ret = request_dma(crc->dma_ch, dev_name(dev));
- if (ret) {
- dev_err(&pdev->dev, "Unable to attach Blackfin CRC DMA channel\n");
- return ret;
- }
-
- crc->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &crc->sg_dma, GFP_KERNEL);
- if (crc->sg_cpu == NULL) {
- ret = -ENOMEM;
- goto out_error_dma;
- }
- /*
- * need at most CRC_MAX_DMA_DESC sg + CRC_MAX_DMA_DESC middle +
- * 1 last + 1 next dma descriptors
- */
- crc->sg_mid_buf = (u8 *)(crc->sg_cpu + ((CRC_MAX_DMA_DESC + 1) << 1));
- crc->sg_mid_dma = crc->sg_dma + sizeof(struct dma_desc_array)
- * ((CRC_MAX_DMA_DESC + 1) << 1);
-
- writel(0, &crc->regs->control);
- crc->poly = (u32)pdev->dev.platform_data;
- writel(crc->poly, &crc->regs->poly);
-
- while (!(readl(&crc->regs->status) & LUTDONE) && (--timeout) > 0)
- cpu_relax();
-
- if (timeout == 0)
- dev_info(&pdev->dev, "init crc poly timeout\n");
-
- platform_set_drvdata(pdev, crc);
-
- spin_lock(&crc_list.lock);
- list_add(&crc->list, &crc_list.dev_list);
- spin_unlock(&crc_list.lock);
-
- if (list_is_singular(&crc_list.dev_list)) {
- ret = crypto_register_ahash(&algs);
- if (ret) {
- dev_err(&pdev->dev,
- "Can't register crypto ahash device\n");
- goto out_error_dma;
- }
- }
-
- dev_info(&pdev->dev, "initialized\n");
-
- return 0;
-
-out_error_dma:
- if (crc->sg_cpu)
- dma_free_coherent(&pdev->dev, PAGE_SIZE, crc->sg_cpu, crc->sg_dma);
- free_dma(crc->dma_ch);
-
- return ret;
-}
-
-/**
- * bfin_crypto_crc_remove - Initialize module
- *
- */
-static int bfin_crypto_crc_remove(struct platform_device *pdev)
-{
- struct bfin_crypto_crc *crc = platform_get_drvdata(pdev);
-
- if (!crc)
- return -ENODEV;
-
- spin_lock(&crc_list.lock);
- list_del(&crc->list);
- spin_unlock(&crc_list.lock);
-
- crypto_unregister_ahash(&algs);
- tasklet_kill(&crc->done_task);
- free_dma(crc->dma_ch);
-
- return 0;
-}
-
-static struct platform_driver bfin_crypto_crc_driver = {
- .probe = bfin_crypto_crc_probe,
- .remove = bfin_crypto_crc_remove,
- .suspend = bfin_crypto_crc_suspend,
- .resume = bfin_crypto_crc_resume,
- .driver = {
- .name = DRIVER_NAME,
- },
-};
-
-/**
- * bfin_crypto_crc_mod_init - Initialize module
- *
- * Checks the module params and registers the platform driver.
- * Real work is in the platform probe function.
- */
-static int __init bfin_crypto_crc_mod_init(void)
-{
- int ret;
-
- pr_info("Blackfin hardware CRC crypto driver\n");
-
- INIT_LIST_HEAD(&crc_list.dev_list);
- spin_lock_init(&crc_list.lock);
-
- ret = platform_driver_register(&bfin_crypto_crc_driver);
- if (ret) {
- pr_err("unable to register driver\n");
- return ret;
- }
-
- return 0;
-}
-
-/**
- * bfin_crypto_crc_mod_exit - Deinitialize module
- */
-static void __exit bfin_crypto_crc_mod_exit(void)
-{
- platform_driver_unregister(&bfin_crypto_crc_driver);
-}
-
-module_init(bfin_crypto_crc_mod_init);
-module_exit(bfin_crypto_crc_mod_exit);
-
-MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
-MODULE_DESCRIPTION("Blackfin CRC hardware crypto driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/crypto/bfin_crc.h b/drivers/crypto/bfin_crc.h
deleted file mode 100644
index 786ef74..0000000
--- a/drivers/crypto/bfin_crc.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * bfin_crc.h - interface to Blackfin CRC controllers
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_CRC_H__
-#define __BFIN_CRC_H__
-
-/* Function driver which use hardware crc must initialize the structure */
-struct crc_info {
- /* Input data address */
- unsigned char *in_addr;
- /* Output data address */
- unsigned char *out_addr;
- /* Input or output bytes */
- unsigned long datasize;
- union {
- /* CRC to compare with that of input buffer */
- unsigned long crc_compare;
- /* Value to compare with input data */
- unsigned long val_verify;
- /* Value to fill */
- unsigned long val_fill;
- };
- /* Value to program the 32b CRC Polynomial */
- unsigned long crc_poly;
- union {
- /* CRC calculated from the input data */
- unsigned long crc_result;
- /* First failed position to verify input data */
- unsigned long pos_verify;
- };
- /* CRC mirror flags */
- unsigned int bitmirr:1;
- unsigned int bytmirr:1;
- unsigned int w16swp:1;
- unsigned int fdsel:1;
- unsigned int rsltmirr:1;
- unsigned int polymirr:1;
- unsigned int cmpmirr:1;
-};
-
-/* Userspace interface */
-#define CRC_IOC_MAGIC 'C'
-#define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int)
-#define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int)
-#define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int)
-#define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int)
-
-
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-#include <linux/spinlock.h>
-
-struct crc_register {
- u32 control;
- u32 datacnt;
- u32 datacntrld;
- u32 __pad_1[2];
- u32 compare;
- u32 fillval;
- u32 datafifo;
- u32 intren;
- u32 intrenset;
- u32 intrenclr;
- u32 poly;
- u32 __pad_2[4];
- u32 status;
- u32 datacntcap;
- u32 __pad_3;
- u32 result;
- u32 curresult;
- u32 __pad_4[3];
- u32 revid;
-};
-
-/* CRC_STATUS Masks */
-#define CMPERR 0x00000002 /* Compare error */
-#define DCNTEXP 0x00000010 /* datacnt register expired */
-#define IBR 0x00010000 /* Input buffer ready */
-#define OBR 0x00020000 /* Output buffer ready */
-#define IRR 0x00040000 /* Immediate result readt */
-#define LUTDONE 0x00080000 /* Look-up table generation done */
-#define FSTAT 0x00700000 /* FIFO status */
-#define MAX_FIFO 4 /* Max fifo size */
-
-/* CRC_CONTROL Masks */
-#define BLKEN 0x00000001 /* Block enable */
-#define OPMODE 0x000000F0 /* Operation mode */
-#define OPMODE_OFFSET 4 /* Operation mode mask offset*/
-#define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */
-#define MODE_DATA_FILL 2 /* MTM data fill */
-#define MODE_CALC_CRC 3 /* MSM CRC compute and compare */
-#define MODE_DATA_VERIFY 4 /* MSM data verify */
-#define AUTOCLRZ 0x00000100 /* Auto clear to zero */
-#define AUTOCLRF 0x00000200 /* Auto clear to one */
-#define OBRSTALL 0x00001000 /* Stall on output buffer ready */
-#define IRRSTALL 0x00002000 /* Stall on immediate result ready */
-#define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */
-#define BITMIRR_OFFSET 16 /* Mirror bits offset */
-#define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */
-#define BYTMIRR_OFFSET 17 /* Mirror bytes offset */
-#define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */
-#define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */
-#define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */
-#define FDSEL_OFFSET 19 /* Mirror FIFO offset */
-#define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */
-#define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */
-#define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */
-#define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */
-#define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */
-#define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */
-
-/* CRC_INTREN Masks */
-#define CMPERRI 0x02 /* CRC_ERROR_INTR */
-#define DCNTEXPI 0x10 /* CRC_STATUS_INTR */
-
-#endif
-
-#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 19/28] ata: Remove Blackfin PATA support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (16 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 18/28] crypto: Remove Blackfin crypto support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 20/28] pwm: Remove Blackfin PWM support Aaron Wu
` (8 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin PATA support
---
drivers/ata/Kconfig | 9 -
drivers/ata/Makefile | 1 -
drivers/ata/pata_bf54x.c | 1703 ----------------------------------------------
3 files changed, 1713 deletions(-)
delete mode 100644 drivers/ata/pata_bf54x.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index a7120d6..4582fa2 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -549,15 +549,6 @@ config PATA_ATP867X
If unsure, say N.
-config PATA_BF54X
- tristate "Blackfin 54x ATAPI support"
- depends on BF542 || BF548 || BF549
- help
- This option enables support for the built-in ATAPI controller on
- Blackfin 54x family chips.
-
- If unsure, say N.
-
config PATA_BK3710
tristate "Palmchip BK3710 PATA support"
depends on ARCH_DAVINCI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index f1f5a3f..6dae8c9 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -53,7 +53,6 @@ obj-$(CONFIG_PATA_AMD) += pata_amd.o
obj-$(CONFIG_PATA_ARTOP) += pata_artop.o
obj-$(CONFIG_PATA_ATIIXP) += pata_atiixp.o
obj-$(CONFIG_PATA_ATP867X) += pata_atp867x.o
-obj-$(CONFIG_PATA_BF54X) += pata_bf54x.o
obj-$(CONFIG_PATA_BK3710) += pata_bk3710.o
obj-$(CONFIG_PATA_CMD64X) += pata_cmd64x.o
obj-$(CONFIG_PATA_CS5520) += pata_cs5520.o
diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c
deleted file mode 100644
index 0e55a8d..0000000
--- a/drivers/ata/pata_bf54x.c
+++ /dev/null
@@ -1,1703 +0,0 @@
-/*
- * File: drivers/ata/pata_bf54x.c
- * Author: Sonic Zhang <sonic.zhang@analog.com>
- *
- * Created:
- * Description: PATA Driver for blackfin 54x
- *
- * Modified:
- * Copyright 2007 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/blkdev.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <scsi/scsi_host.h>
-#include <linux/libata.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define DRV_NAME "pata-bf54x"
-#define DRV_VERSION "0.9"
-
-#define ATA_REG_CTRL 0x0E
-#define ATA_REG_ALTSTATUS ATA_REG_CTRL
-
-/* These are the offset of the controller's registers */
-#define ATAPI_OFFSET_CONTROL 0x00
-#define ATAPI_OFFSET_STATUS 0x04
-#define ATAPI_OFFSET_DEV_ADDR 0x08
-#define ATAPI_OFFSET_DEV_TXBUF 0x0c
-#define ATAPI_OFFSET_DEV_RXBUF 0x10
-#define ATAPI_OFFSET_INT_MASK 0x14
-#define ATAPI_OFFSET_INT_STATUS 0x18
-#define ATAPI_OFFSET_XFER_LEN 0x1c
-#define ATAPI_OFFSET_LINE_STATUS 0x20
-#define ATAPI_OFFSET_SM_STATE 0x24
-#define ATAPI_OFFSET_TERMINATE 0x28
-#define ATAPI_OFFSET_PIO_TFRCNT 0x2c
-#define ATAPI_OFFSET_DMA_TFRCNT 0x30
-#define ATAPI_OFFSET_UMAIN_TFRCNT 0x34
-#define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38
-#define ATAPI_OFFSET_REG_TIM_0 0x40
-#define ATAPI_OFFSET_PIO_TIM_0 0x44
-#define ATAPI_OFFSET_PIO_TIM_1 0x48
-#define ATAPI_OFFSET_MULTI_TIM_0 0x50
-#define ATAPI_OFFSET_MULTI_TIM_1 0x54
-#define ATAPI_OFFSET_MULTI_TIM_2 0x58
-#define ATAPI_OFFSET_ULTRA_TIM_0 0x60
-#define ATAPI_OFFSET_ULTRA_TIM_1 0x64
-#define ATAPI_OFFSET_ULTRA_TIM_2 0x68
-#define ATAPI_OFFSET_ULTRA_TIM_3 0x6c
-
-
-#define ATAPI_GET_CONTROL(base)\
- bfin_read16(base + ATAPI_OFFSET_CONTROL)
-#define ATAPI_SET_CONTROL(base, val)\
- bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
-#define ATAPI_GET_STATUS(base)\
- bfin_read16(base + ATAPI_OFFSET_STATUS)
-#define ATAPI_GET_DEV_ADDR(base)\
- bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
-#define ATAPI_SET_DEV_ADDR(base, val)\
- bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
-#define ATAPI_GET_DEV_TXBUF(base)\
- bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
-#define ATAPI_SET_DEV_TXBUF(base, val)\
- bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
-#define ATAPI_GET_DEV_RXBUF(base)\
- bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
-#define ATAPI_SET_DEV_RXBUF(base, val)\
- bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
-#define ATAPI_GET_INT_MASK(base)\
- bfin_read16(base + ATAPI_OFFSET_INT_MASK)
-#define ATAPI_SET_INT_MASK(base, val)\
- bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
-#define ATAPI_GET_INT_STATUS(base)\
- bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
-#define ATAPI_SET_INT_STATUS(base, val)\
- bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
-#define ATAPI_GET_XFER_LEN(base)\
- bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
-#define ATAPI_SET_XFER_LEN(base, val)\
- bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
-#define ATAPI_GET_LINE_STATUS(base)\
- bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
-#define ATAPI_GET_SM_STATE(base)\
- bfin_read16(base + ATAPI_OFFSET_SM_STATE)
-#define ATAPI_GET_TERMINATE(base)\
- bfin_read16(base + ATAPI_OFFSET_TERMINATE)
-#define ATAPI_SET_TERMINATE(base, val)\
- bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
-#define ATAPI_GET_PIO_TFRCNT(base)\
- bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
-#define ATAPI_GET_DMA_TFRCNT(base)\
- bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
-#define ATAPI_GET_UMAIN_TFRCNT(base)\
- bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
-#define ATAPI_GET_UDMAOUT_TFRCNT(base)\
- bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
-#define ATAPI_GET_REG_TIM_0(base)\
- bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
-#define ATAPI_SET_REG_TIM_0(base, val)\
- bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
-#define ATAPI_GET_PIO_TIM_0(base)\
- bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
-#define ATAPI_SET_PIO_TIM_0(base, val)\
- bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
-#define ATAPI_GET_PIO_TIM_1(base)\
- bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
-#define ATAPI_SET_PIO_TIM_1(base, val)\
- bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
-#define ATAPI_GET_MULTI_TIM_0(base)\
- bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
-#define ATAPI_SET_MULTI_TIM_0(base, val)\
- bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
-#define ATAPI_GET_MULTI_TIM_1(base)\
- bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
-#define ATAPI_SET_MULTI_TIM_1(base, val)\
- bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
-#define ATAPI_GET_MULTI_TIM_2(base)\
- bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
-#define ATAPI_SET_MULTI_TIM_2(base, val)\
- bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
-#define ATAPI_GET_ULTRA_TIM_0(base)\
- bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
-#define ATAPI_SET_ULTRA_TIM_0(base, val)\
- bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
-#define ATAPI_GET_ULTRA_TIM_1(base)\
- bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
-#define ATAPI_SET_ULTRA_TIM_1(base, val)\
- bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
-#define ATAPI_GET_ULTRA_TIM_2(base)\
- bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
-#define ATAPI_SET_ULTRA_TIM_2(base, val)\
- bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
-#define ATAPI_GET_ULTRA_TIM_3(base)\
- bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
-#define ATAPI_SET_ULTRA_TIM_3(base, val)\
- bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
-
-/**
- * PIO Mode - Frequency compatibility
- */
-/* mode: 0 1 2 3 4 */
-static const u32 pio_fsclk[] =
-{ 33333333, 33333333, 33333333, 33333333, 33333333 };
-
-/**
- * MDMA Mode - Frequency compatibility
- */
-/* mode: 0 1 2 */
-static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 };
-
-/**
- * UDMA Mode - Frequency compatibility
- *
- * UDMA5 - 100 MB/s - SCLK = 133 MHz
- * UDMA4 - 66 MB/s - SCLK >= 80 MHz
- * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz
- * UDMA2 - 33 MB/s - SCLK >= 40 MHz
- */
-/* mode: 0 1 2 3 4 5 */
-static const u32 udma_fsclk[] =
-{ 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 };
-
-/**
- * Register transfer timing table
- */
-/* mode: 0 1 2 3 4 */
-/* Cycle Time */
-static const u32 reg_t0min[] = { 600, 383, 330, 180, 120 };
-/* DIOR/DIOW to end cycle */
-static const u32 reg_t2min[] = { 290, 290, 290, 70, 25 };
-/* DIOR/DIOW asserted pulse width */
-static const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 };
-
-/**
- * PIO timing table
- */
-/* mode: 0 1 2 3 4 */
-/* Cycle Time */
-static const u32 pio_t0min[] = { 600, 383, 240, 180, 120 };
-/* Address valid to DIOR/DIORW */
-static const u32 pio_t1min[] = { 70, 50, 30, 30, 25 };
-/* DIOR/DIOW to end cycle */
-static const u32 pio_t2min[] = { 165, 125, 100, 80, 70 };
-/* DIOR/DIOW asserted pulse width */
-static const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 };
-/* DIOW data hold */
-static const u32 pio_t4min[] = { 30, 20, 15, 10, 10 };
-
-/* ******************************************************************
- * Multiword DMA timing table
- * ******************************************************************
- */
-/* mode: 0 1 2 */
-/* Cycle Time */
-static const u32 mdma_t0min[] = { 480, 150, 120 };
-/* DIOR/DIOW asserted pulse width */
-static const u32 mdma_tdmin[] = { 215, 80, 70 };
-/* DMACK to read data released */
-static const u32 mdma_thmin[] = { 20, 15, 10 };
-/* DIOR/DIOW to DMACK hold */
-static const u32 mdma_tjmin[] = { 20, 5, 5 };
-/* DIOR negated pulse width */
-static const u32 mdma_tkrmin[] = { 50, 50, 25 };
-/* DIOR negated pulse width */
-static const u32 mdma_tkwmin[] = { 215, 50, 25 };
-/* CS[1:0] valid to DIOR/DIOW */
-static const u32 mdma_tmmin[] = { 50, 30, 25 };
-/* DMACK to read data released */
-static const u32 mdma_tzmax[] = { 20, 25, 25 };
-
-/**
- * Ultra DMA timing table
- */
-/* mode: 0 1 2 3 4 5 */
-static const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 };
-static const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 };
-static const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 };
-static const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 };
-static const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 };
-
-
-static const u32 udma_tmlimin = 20;
-static const u32 udma_tzahmin = 20;
-static const u32 udma_tenvmin = 20;
-static const u32 udma_tackmin = 20;
-static const u32 udma_tssmin = 50;
-
-#define BFIN_MAX_SG_SEGMENTS 4
-
-/**
- *
- * Function: num_clocks_min
- *
- * Description:
- * calculate number of SCLK cycles to meet minimum timing
- */
-static unsigned short num_clocks_min(unsigned long tmin,
- unsigned long fsclk)
-{
- unsigned long tmp ;
- unsigned short result;
-
- tmp = tmin * (fsclk/1000/1000) / 1000;
- result = (unsigned short)tmp;
- if ((tmp*1000*1000) < (tmin*(fsclk/1000))) {
- result++;
- }
-
- return result;
-}
-
-/**
- * bfin_set_piomode - Initialize host controller PATA PIO timings
- * @ap: Port whose timings we are configuring
- * @adev: um
- *
- * Set PIO mode for device.
- *
- * LOCKING:
- * None (inherited from caller).
- */
-
-static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev)
-{
- int mode = adev->pio_mode - XFER_PIO_0;
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- unsigned int fsclk = get_sclk();
- unsigned short teoc_reg, t2_reg, teoc_pio;
- unsigned short t4_reg, t2_pio, t1_reg;
- unsigned short n0, n6, t6min = 5;
-
- /* the most restrictive timing value is t6 and tc, the DIOW - data hold
- * If one SCLK pulse is longer than this minimum value then register
- * transfers cannot be supported at this frequency.
- */
- n6 = num_clocks_min(t6min, fsclk);
- if (mode >= 0 && mode <= 4 && n6 >= 1) {
- dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
- /* calculate the timing values for register transfers. */
- while (mode > 0 && pio_fsclk[mode] > fsclk)
- mode--;
-
- /* DIOR/DIOW to end cycle time */
- t2_reg = num_clocks_min(reg_t2min[mode], fsclk);
- /* DIOR/DIOW asserted pulse width */
- teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk);
- /* Cycle Time */
- n0 = num_clocks_min(reg_t0min[mode], fsclk);
-
- /* increase t2 until we meed the minimum cycle length */
- if (t2_reg + teoc_reg < n0)
- t2_reg = n0 - teoc_reg;
-
- /* calculate the timing values for pio transfers. */
-
- /* DIOR/DIOW to end cycle time */
- t2_pio = num_clocks_min(pio_t2min[mode], fsclk);
- /* DIOR/DIOW asserted pulse width */
- teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk);
- /* Cycle Time */
- n0 = num_clocks_min(pio_t0min[mode], fsclk);
-
- /* increase t2 until we meed the minimum cycle length */
- if (t2_pio + teoc_pio < n0)
- t2_pio = n0 - teoc_pio;
-
- /* Address valid to DIOR/DIORW */
- t1_reg = num_clocks_min(pio_t1min[mode], fsclk);
-
- /* DIOW data hold */
- t4_reg = num_clocks_min(pio_t4min[mode], fsclk);
-
- ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
- ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
- ATAPI_SET_PIO_TIM_1(base, teoc_pio);
- if (mode > 2) {
- ATAPI_SET_CONTROL(base,
- ATAPI_GET_CONTROL(base) | IORDY_EN);
- } else {
- ATAPI_SET_CONTROL(base,
- ATAPI_GET_CONTROL(base) & ~IORDY_EN);
- }
-
- /* Disable host ATAPI PIO interrupts */
- ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
- & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK));
- SSYNC();
- }
-}
-
-/**
- * bfin_set_dmamode - Initialize host controller PATA DMA timings
- * @ap: Port whose timings we are configuring
- * @adev: um
- *
- * Set UDMA mode for device.
- *
- * LOCKING:
- * None (inherited from caller).
- */
-
-static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
-{
- int mode;
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- unsigned long fsclk = get_sclk();
- unsigned short tenv, tack, tcyc_tdvs, tdvs, tmli, tss, trp, tzah;
- unsigned short tm, td, tkr, tkw, teoc, th;
- unsigned short n0, nf, tfmin = 5;
- unsigned short nmin, tcyc;
-
- mode = adev->dma_mode - XFER_UDMA_0;
- if (mode >= 0 && mode <= 5) {
- dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode);
- /* the most restrictive timing value is t6 and tc,
- * the DIOW - data hold. If one SCLK pulse is longer
- * than this minimum value then register
- * transfers cannot be supported at this frequency.
- */
- while (mode > 0 && udma_fsclk[mode] > fsclk)
- mode--;
-
- nmin = num_clocks_min(udma_tmin[mode], fsclk);
- if (nmin >= 1) {
- /* calculate the timing values for Ultra DMA. */
- tdvs = num_clocks_min(udma_tdvsmin[mode], fsclk);
- tcyc = num_clocks_min(udma_tcycmin[mode], fsclk);
- tcyc_tdvs = 2;
-
- /* increase tcyc - tdvs (tcyc_tdvs) until we meed
- * the minimum cycle length
- */
- if (tdvs + tcyc_tdvs < tcyc)
- tcyc_tdvs = tcyc - tdvs;
-
- /* Mow assign the values required for the timing
- * registers
- */
- if (tcyc_tdvs < 2)
- tcyc_tdvs = 2;
-
- if (tdvs < 2)
- tdvs = 2;
-
- tack = num_clocks_min(udma_tackmin, fsclk);
- tss = num_clocks_min(udma_tssmin, fsclk);
- tmli = num_clocks_min(udma_tmlimin, fsclk);
- tzah = num_clocks_min(udma_tzahmin, fsclk);
- trp = num_clocks_min(udma_trpmin[mode], fsclk);
- tenv = num_clocks_min(udma_tenvmin, fsclk);
- if (tenv <= udma_tenvmax[mode]) {
- ATAPI_SET_ULTRA_TIM_0(base, (tenv<<8 | tack));
- ATAPI_SET_ULTRA_TIM_1(base,
- (tcyc_tdvs<<8 | tdvs));
- ATAPI_SET_ULTRA_TIM_2(base, (tmli<<8 | tss));
- ATAPI_SET_ULTRA_TIM_3(base, (trp<<8 | tzah));
- }
- }
- }
-
- mode = adev->dma_mode - XFER_MW_DMA_0;
- if (mode >= 0 && mode <= 2) {
- dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode);
- /* the most restrictive timing value is tf, the DMACK to
- * read data released. If one SCLK pulse is longer than
- * this maximum value then the MDMA mode
- * cannot be supported at this frequency.
- */
- while (mode > 0 && mdma_fsclk[mode] > fsclk)
- mode--;
-
- nf = num_clocks_min(tfmin, fsclk);
- if (nf >= 1) {
- /* calculate the timing values for Multi-word DMA. */
-
- /* DIOR/DIOW asserted pulse width */
- td = num_clocks_min(mdma_tdmin[mode], fsclk);
-
- /* DIOR negated pulse width */
- tkw = num_clocks_min(mdma_tkwmin[mode], fsclk);
-
- /* Cycle Time */
- n0 = num_clocks_min(mdma_t0min[mode], fsclk);
-
- /* increase tk until we meed the minimum cycle length */
- if (tkw + td < n0)
- tkw = n0 - td;
-
- /* DIOR negated pulse width - read */
- tkr = num_clocks_min(mdma_tkrmin[mode], fsclk);
- /* CS{1:0] valid to DIOR/DIOW */
- tm = num_clocks_min(mdma_tmmin[mode], fsclk);
- /* DIOR/DIOW to DMACK hold */
- teoc = num_clocks_min(mdma_tjmin[mode], fsclk);
- /* DIOW Data hold */
- th = num_clocks_min(mdma_thmin[mode], fsclk);
-
- ATAPI_SET_MULTI_TIM_0(base, (tm<<8 | td));
- ATAPI_SET_MULTI_TIM_1(base, (tkr<<8 | tkw));
- ATAPI_SET_MULTI_TIM_2(base, (teoc<<8 | th));
- SSYNC();
- }
- }
- return;
-}
-
-/**
- *
- * Function: wait_complete
- *
- * Description: Waits the interrupt from device
- *
- */
-static inline void wait_complete(void __iomem *base, unsigned short mask)
-{
- unsigned short status;
- unsigned int i = 0;
-
-#define PATA_BF54X_WAIT_TIMEOUT 10000
-
- for (i = 0; i < PATA_BF54X_WAIT_TIMEOUT; i++) {
- status = ATAPI_GET_INT_STATUS(base) & mask;
- if (status)
- break;
- }
-
- ATAPI_SET_INT_STATUS(base, mask);
-}
-
-/**
- *
- * Function: write_atapi_register
- *
- * Description: Writes to ATA Device Resgister
- *
- */
-
-static void write_atapi_register(void __iomem *base,
- unsigned long ata_reg, unsigned short value)
-{
- /* Program the ATA_DEV_TXBUF register with write data (to be
- * written into the device).
- */
- ATAPI_SET_DEV_TXBUF(base, value);
-
- /* Program the ATA_DEV_ADDR register with address of the
- * device register (0x01 to 0x0F).
- */
- ATAPI_SET_DEV_ADDR(base, ata_reg);
-
- /* Program the ATA_CTRL register with dir set to write (1)
- */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
-
- /* ensure PIO DMA is not set */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
-
- /* and start the transfer */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
-
- /* Wait for the interrupt to indicate the end of the transfer.
- * (We need to wait on and clear rhe ATA_DEV_INT interrupt status)
- */
- wait_complete(base, PIO_DONE_INT);
-}
-
-/**
- *
- * Function: read_atapi_register
- *
- *Description: Reads from ATA Device Resgister
- *
- */
-
-static unsigned short read_atapi_register(void __iomem *base,
- unsigned long ata_reg)
-{
- /* Program the ATA_DEV_ADDR register with address of the
- * device register (0x01 to 0x0F).
- */
- ATAPI_SET_DEV_ADDR(base, ata_reg);
-
- /* Program the ATA_CTRL register with dir set to read (0) and
- */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
-
- /* ensure PIO DMA is not set */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
-
- /* and start the transfer */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
-
- /* Wait for the interrupt to indicate the end of the transfer.
- * (PIO_DONE interrupt is set and it doesn't seem to matter
- * that we don't clear it)
- */
- wait_complete(base, PIO_DONE_INT);
-
- /* Read the ATA_DEV_RXBUF register with write data (to be
- * written into the device).
- */
- return ATAPI_GET_DEV_RXBUF(base);
-}
-
-/**
- *
- * Function: write_atapi_register_data
- *
- * Description: Writes to ATA Device Resgister
- *
- */
-
-static void write_atapi_data(void __iomem *base,
- int len, unsigned short *buf)
-{
- int i;
-
- /* Set transfer length to 1 */
- ATAPI_SET_XFER_LEN(base, 1);
-
- /* Program the ATA_DEV_ADDR register with address of the
- * ATA_REG_DATA
- */
- ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
-
- /* Program the ATA_CTRL register with dir set to write (1)
- */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
-
- /* ensure PIO DMA is not set */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
-
- for (i = 0; i < len; i++) {
- /* Program the ATA_DEV_TXBUF register with write data (to be
- * written into the device).
- */
- ATAPI_SET_DEV_TXBUF(base, buf[i]);
-
- /* and start the transfer */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
-
- /* Wait for the interrupt to indicate the end of the transfer.
- * (We need to wait on and clear rhe ATA_DEV_INT
- * interrupt status)
- */
- wait_complete(base, PIO_DONE_INT);
- }
-}
-
-/**
- *
- * Function: read_atapi_register_data
- *
- * Description: Reads from ATA Device Resgister
- *
- */
-
-static void read_atapi_data(void __iomem *base,
- int len, unsigned short *buf)
-{
- int i;
-
- /* Set transfer length to 1 */
- ATAPI_SET_XFER_LEN(base, 1);
-
- /* Program the ATA_DEV_ADDR register with address of the
- * ATA_REG_DATA
- */
- ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
-
- /* Program the ATA_CTRL register with dir set to read (0) and
- */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
-
- /* ensure PIO DMA is not set */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
-
- for (i = 0; i < len; i++) {
- /* and start the transfer */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
-
- /* Wait for the interrupt to indicate the end of the transfer.
- * (PIO_DONE interrupt is set and it doesn't seem to matter
- * that we don't clear it)
- */
- wait_complete(base, PIO_DONE_INT);
-
- /* Read the ATA_DEV_RXBUF register with write data (to be
- * written into the device).
- */
- buf[i] = ATAPI_GET_DEV_RXBUF(base);
- }
-}
-
-/**
- * bfin_tf_load - send taskfile registers to host controller
- * @ap: Port to which output is sent
- * @tf: ATA taskfile register set
- *
- * Note: Original code is ata_sff_tf_load().
- */
-
-static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
-
- if (tf->ctl != ap->last_ctl) {
- write_atapi_register(base, ATA_REG_CTRL, tf->ctl);
- ap->last_ctl = tf->ctl;
- ata_wait_idle(ap);
- }
-
- if (is_addr) {
- if (tf->flags & ATA_TFLAG_LBA48) {
- write_atapi_register(base, ATA_REG_FEATURE,
- tf->hob_feature);
- write_atapi_register(base, ATA_REG_NSECT,
- tf->hob_nsect);
- write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal);
- write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam);
- write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah);
- dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X "
- "0x%X 0x%X\n",
- tf->hob_feature,
- tf->hob_nsect,
- tf->hob_lbal,
- tf->hob_lbam,
- tf->hob_lbah);
- }
-
- write_atapi_register(base, ATA_REG_FEATURE, tf->feature);
- write_atapi_register(base, ATA_REG_NSECT, tf->nsect);
- write_atapi_register(base, ATA_REG_LBAL, tf->lbal);
- write_atapi_register(base, ATA_REG_LBAM, tf->lbam);
- write_atapi_register(base, ATA_REG_LBAH, tf->lbah);
- dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
- tf->feature,
- tf->nsect,
- tf->lbal,
- tf->lbam,
- tf->lbah);
- }
-
- if (tf->flags & ATA_TFLAG_DEVICE) {
- write_atapi_register(base, ATA_REG_DEVICE, tf->device);
- dev_dbg(ap->dev, "device 0x%X\n", tf->device);
- }
-
- ata_wait_idle(ap);
-}
-
-/**
- * bfin_check_status - Read device status reg & clear interrupt
- * @ap: port where the device is
- *
- * Note: Original code is ata_check_status().
- */
-
-static u8 bfin_check_status(struct ata_port *ap)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- return read_atapi_register(base, ATA_REG_STATUS);
-}
-
-/**
- * bfin_tf_read - input device's ATA taskfile shadow registers
- * @ap: Port from which input is read
- * @tf: ATA taskfile register set for storing input
- *
- * Note: Original code is ata_sff_tf_read().
- */
-
-static void bfin_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-
- tf->command = bfin_check_status(ap);
- tf->feature = read_atapi_register(base, ATA_REG_ERR);
- tf->nsect = read_atapi_register(base, ATA_REG_NSECT);
- tf->lbal = read_atapi_register(base, ATA_REG_LBAL);
- tf->lbam = read_atapi_register(base, ATA_REG_LBAM);
- tf->lbah = read_atapi_register(base, ATA_REG_LBAH);
- tf->device = read_atapi_register(base, ATA_REG_DEVICE);
-
- if (tf->flags & ATA_TFLAG_LBA48) {
- write_atapi_register(base, ATA_REG_CTRL, tf->ctl | ATA_HOB);
- tf->hob_feature = read_atapi_register(base, ATA_REG_ERR);
- tf->hob_nsect = read_atapi_register(base, ATA_REG_NSECT);
- tf->hob_lbal = read_atapi_register(base, ATA_REG_LBAL);
- tf->hob_lbam = read_atapi_register(base, ATA_REG_LBAM);
- tf->hob_lbah = read_atapi_register(base, ATA_REG_LBAH);
- }
-}
-
-/**
- * bfin_exec_command - issue ATA command to host controller
- * @ap: port to which command is being issued
- * @tf: ATA taskfile register set
- *
- * Note: Original code is ata_sff_exec_command().
- */
-
-static void bfin_exec_command(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- dev_dbg(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command);
-
- write_atapi_register(base, ATA_REG_CMD, tf->command);
- ata_sff_pause(ap);
-}
-
-/**
- * bfin_check_altstatus - Read device alternate status reg
- * @ap: port where the device is
- */
-
-static u8 bfin_check_altstatus(struct ata_port *ap)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- return read_atapi_register(base, ATA_REG_ALTSTATUS);
-}
-
-/**
- * bfin_dev_select - Select device 0/1 on ATA bus
- * @ap: ATA channel to manipulate
- * @device: ATA device (numbered from zero) to select
- *
- * Note: Original code is ata_sff_dev_select().
- */
-
-static void bfin_dev_select(struct ata_port *ap, unsigned int device)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- u8 tmp;
-
- if (device == 0)
- tmp = ATA_DEVICE_OBS;
- else
- tmp = ATA_DEVICE_OBS | ATA_DEV1;
-
- write_atapi_register(base, ATA_REG_DEVICE, tmp);
- ata_sff_pause(ap);
-}
-
-/**
- * bfin_set_devctl - Write device control reg
- * @ap: port where the device is
- * @ctl: value to write
- */
-
-static void bfin_set_devctl(struct ata_port *ap, u8 ctl)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- write_atapi_register(base, ATA_REG_CTRL, ctl);
-}
-
-/**
- * bfin_bmdma_setup - Set up IDE DMA transaction
- * @qc: Info associated with this ATA transaction.
- *
- * Note: Original code is ata_bmdma_setup().
- */
-
-static void bfin_bmdma_setup(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- struct dma_desc_array *dma_desc_cpu = (struct dma_desc_array *)ap->bmdma_prd;
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- unsigned short config = DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_16 | DMAEN;
- struct scatterlist *sg;
- unsigned int si;
- unsigned int channel;
- unsigned int dir;
- unsigned int size = 0;
-
- dev_dbg(qc->ap->dev, "in atapi dma setup\n");
- /* Program the ATA_CTRL register with dir */
- if (qc->tf.flags & ATA_TFLAG_WRITE) {
- channel = CH_ATAPI_TX;
- dir = DMA_TO_DEVICE;
- } else {
- channel = CH_ATAPI_RX;
- dir = DMA_FROM_DEVICE;
- config |= WNR;
- }
-
- dma_map_sg(ap->dev, qc->sg, qc->n_elem, dir);
-
- /* fill the ATAPI DMA controller */
- for_each_sg(qc->sg, sg, qc->n_elem, si) {
- dma_desc_cpu[si].start_addr = sg_dma_address(sg);
- dma_desc_cpu[si].cfg = config;
- dma_desc_cpu[si].x_count = sg_dma_len(sg) >> 1;
- dma_desc_cpu[si].x_modify = 2;
- size += sg_dma_len(sg);
- }
-
- /* Set the last descriptor to stop mode */
- dma_desc_cpu[qc->n_elem - 1].cfg &= ~(DMAFLOW | NDSIZE);
-
- flush_dcache_range((unsigned int)dma_desc_cpu,
- (unsigned int)dma_desc_cpu +
- qc->n_elem * sizeof(struct dma_desc_array));
-
- /* Enable ATA DMA operation*/
- set_dma_curr_desc_addr(channel, (unsigned long *)ap->bmdma_prd_dma);
- set_dma_x_count(channel, 0);
- set_dma_x_modify(channel, 0);
- set_dma_config(channel, config);
-
- SSYNC();
-
- /* Send ATA DMA command */
- bfin_exec_command(ap, &qc->tf);
-
- if (qc->tf.flags & ATA_TFLAG_WRITE) {
- /* set ATA DMA write direction */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
- | XFER_DIR));
- } else {
- /* set ATA DMA read direction */
- ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
- & ~XFER_DIR));
- }
-
- /* Reset all transfer count */
- ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST);
-
- /* Set ATAPI state machine contorl in terminate sequence */
- ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM);
-
- /* Set transfer length to the total size of sg buffers */
- ATAPI_SET_XFER_LEN(base, size >> 1);
-}
-
-/**
- * bfin_bmdma_start - Start an IDE DMA transaction
- * @qc: Info associated with this ATA transaction.
- *
- * Note: Original code is ata_bmdma_start().
- */
-
-static void bfin_bmdma_start(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-
- dev_dbg(qc->ap->dev, "in atapi dma start\n");
-
- if (!(ap->udma_mask || ap->mwdma_mask))
- return;
-
- /* start ATAPI transfer*/
- if (ap->udma_mask)
- ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
- | ULTRA_START);
- else
- ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
- | MULTI_START);
-}
-
-/**
- * bfin_bmdma_stop - Stop IDE DMA transfer
- * @qc: Command we are ending DMA for
- */
-
-static void bfin_bmdma_stop(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- unsigned int dir;
-
- dev_dbg(qc->ap->dev, "in atapi dma stop\n");
-
- if (!(ap->udma_mask || ap->mwdma_mask))
- return;
-
- /* stop ATAPI DMA controller*/
- if (qc->tf.flags & ATA_TFLAG_WRITE) {
- dir = DMA_TO_DEVICE;
- disable_dma(CH_ATAPI_TX);
- } else {
- dir = DMA_FROM_DEVICE;
- disable_dma(CH_ATAPI_RX);
- }
-
- dma_unmap_sg(ap->dev, qc->sg, qc->n_elem, dir);
-}
-
-/**
- * bfin_devchk - PATA device presence detection
- * @ap: ATA channel to examine
- * @device: Device to examine (starting at zero)
- *
- * Note: Original code is ata_devchk().
- */
-
-static unsigned int bfin_devchk(struct ata_port *ap,
- unsigned int device)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- u8 nsect, lbal;
-
- bfin_dev_select(ap, device);
-
- write_atapi_register(base, ATA_REG_NSECT, 0x55);
- write_atapi_register(base, ATA_REG_LBAL, 0xaa);
-
- write_atapi_register(base, ATA_REG_NSECT, 0xaa);
- write_atapi_register(base, ATA_REG_LBAL, 0x55);
-
- write_atapi_register(base, ATA_REG_NSECT, 0x55);
- write_atapi_register(base, ATA_REG_LBAL, 0xaa);
-
- nsect = read_atapi_register(base, ATA_REG_NSECT);
- lbal = read_atapi_register(base, ATA_REG_LBAL);
-
- if ((nsect == 0x55) && (lbal == 0xaa))
- return 1; /* we found a device */
-
- return 0; /* nothing found */
-}
-
-/**
- * bfin_bus_post_reset - PATA device post reset
- *
- * Note: Original code is ata_bus_post_reset().
- */
-
-static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- unsigned int dev0 = devmask & (1 << 0);
- unsigned int dev1 = devmask & (1 << 1);
- unsigned long deadline;
-
- /* if device 0 was found in ata_devchk, wait for its
- * BSY bit to clear
- */
- if (dev0)
- ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
-
- /* if device 1 was found in ata_devchk, wait for
- * register access, then wait for BSY to clear
- */
- deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT);
- while (dev1) {
- u8 nsect, lbal;
-
- bfin_dev_select(ap, 1);
- nsect = read_atapi_register(base, ATA_REG_NSECT);
- lbal = read_atapi_register(base, ATA_REG_LBAL);
- if ((nsect == 1) && (lbal == 1))
- break;
- if (time_after(jiffies, deadline)) {
- dev1 = 0;
- break;
- }
- ata_msleep(ap, 50); /* give drive a breather */
- }
- if (dev1)
- ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
-
- /* is all this really necessary? */
- bfin_dev_select(ap, 0);
- if (dev1)
- bfin_dev_select(ap, 1);
- if (dev0)
- bfin_dev_select(ap, 0);
-}
-
-/**
- * bfin_bus_softreset - PATA device software reset
- *
- * Note: Original code is ata_bus_softreset().
- */
-
-static unsigned int bfin_bus_softreset(struct ata_port *ap,
- unsigned int devmask)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-
- /* software reset. causes dev0 to be selected */
- write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
- udelay(20);
- write_atapi_register(base, ATA_REG_CTRL, ap->ctl | ATA_SRST);
- udelay(20);
- write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
-
- /* spec mandates ">= 2ms" before checking status.
- * We wait 150ms, because that was the magic delay used for
- * ATAPI devices in Hale Landis's ATADRVR, for the period of time
- * between when the ATA command register is written, and then
- * status is checked. Because waiting for "a while" before
- * checking status is fine, post SRST, we perform this magic
- * delay here as well.
- *
- * Old drivers/ide uses the 2mS rule and then waits for ready
- */
- ata_msleep(ap, 150);
-
- /* Before we perform post reset processing we want to see if
- * the bus shows 0xFF because the odd clown forgets the D7
- * pulldown resistor.
- */
- if (bfin_check_status(ap) == 0xFF)
- return 0;
-
- bfin_bus_post_reset(ap, devmask);
-
- return 0;
-}
-
-/**
- * bfin_softreset - reset host port via ATA SRST
- * @ap: port to reset
- * @classes: resulting classes of attached devices
- *
- * Note: Original code is ata_sff_softreset().
- */
-
-static int bfin_softreset(struct ata_link *link, unsigned int *classes,
- unsigned long deadline)
-{
- struct ata_port *ap = link->ap;
- unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
- unsigned int devmask = 0, err_mask;
- u8 err;
-
- /* determine if device 0/1 are present */
- if (bfin_devchk(ap, 0))
- devmask |= (1 << 0);
- if (slave_possible && bfin_devchk(ap, 1))
- devmask |= (1 << 1);
-
- /* select device 0 again */
- bfin_dev_select(ap, 0);
-
- /* issue bus reset */
- err_mask = bfin_bus_softreset(ap, devmask);
- if (err_mask) {
- ata_port_err(ap, "SRST failed (err_mask=0x%x)\n",
- err_mask);
- return -EIO;
- }
-
- /* determine by signature whether we have ATA or ATAPI devices */
- classes[0] = ata_sff_dev_classify(&ap->link.device[0],
- devmask & (1 << 0), &err);
- if (slave_possible && err != 0x81)
- classes[1] = ata_sff_dev_classify(&ap->link.device[1],
- devmask & (1 << 1), &err);
-
- return 0;
-}
-
-/**
- * bfin_bmdma_status - Read IDE DMA status
- * @ap: Port associated with this ATA transaction.
- */
-
-static unsigned char bfin_bmdma_status(struct ata_port *ap)
-{
- unsigned char host_stat = 0;
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-
- if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON | ULTRA_XFER_ON))
- host_stat |= ATA_DMA_ACTIVE;
- if (ATAPI_GET_INT_STATUS(base) & ATAPI_DEV_INT)
- host_stat |= ATA_DMA_INTR;
-
- dev_dbg(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat);
-
- return host_stat;
-}
-
-/**
- * bfin_data_xfer - Transfer data by PIO
- * @qc: queued command
- * @buf: data buffer
- * @buflen: buffer length
- * @write_data: read/write
- *
- * Note: Original code is ata_sff_data_xfer().
- */
-
-static unsigned int bfin_data_xfer(struct ata_queued_cmd *qc,
- unsigned char *buf,
- unsigned int buflen, int rw)
-{
- struct ata_port *ap = qc->dev->link->ap;
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- unsigned int words = buflen >> 1;
- unsigned short *buf16 = (u16 *)buf;
-
- /* Transfer multiple of 2 bytes */
- if (rw == READ)
- read_atapi_data(base, words, buf16);
- else
- write_atapi_data(base, words, buf16);
-
- /* Transfer trailing 1 byte, if any. */
- if (unlikely(buflen & 0x01)) {
- unsigned short align_buf[1] = { 0 };
- unsigned char *trailing_buf = buf + buflen - 1;
-
- if (rw == READ) {
- read_atapi_data(base, 1, align_buf);
- memcpy(trailing_buf, align_buf, 1);
- } else {
- memcpy(align_buf, trailing_buf, 1);
- write_atapi_data(base, 1, align_buf);
- }
- words++;
- }
-
- return words << 1;
-}
-
-/**
- * bfin_irq_clear - Clear ATAPI interrupt.
- * @ap: Port associated with this ATA transaction.
- *
- * Note: Original code is ata_bmdma_irq_clear().
- */
-
-static void bfin_irq_clear(struct ata_port *ap)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-
- dev_dbg(ap->dev, "in atapi irq clear\n");
- ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
- | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
- | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
-}
-
-/**
- * bfin_thaw - Thaw DMA controller port
- * @ap: port to thaw
- *
- * Note: Original code is ata_sff_thaw().
- */
-
-void bfin_thaw(struct ata_port *ap)
-{
- dev_dbg(ap->dev, "in atapi dma thaw\n");
- bfin_check_status(ap);
- ata_sff_irq_on(ap);
-}
-
-/**
- * bfin_postreset - standard postreset callback
- * @ap: the target ata_port
- * @classes: classes of attached devices
- *
- * Note: Original code is ata_sff_postreset().
- */
-
-static void bfin_postreset(struct ata_link *link, unsigned int *classes)
-{
- struct ata_port *ap = link->ap;
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
-
- /* re-enable interrupts */
- ata_sff_irq_on(ap);
-
- /* is double-select really necessary? */
- if (classes[0] != ATA_DEV_NONE)
- bfin_dev_select(ap, 1);
- if (classes[1] != ATA_DEV_NONE)
- bfin_dev_select(ap, 0);
-
- /* bail out if no device is present */
- if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
- return;
- }
-
- /* set up device control */
- write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
-}
-
-static void bfin_port_stop(struct ata_port *ap)
-{
- dev_dbg(ap->dev, "in atapi port stop\n");
- if (ap->udma_mask != 0 || ap->mwdma_mask != 0) {
- dma_free_coherent(ap->dev,
- BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array),
- ap->bmdma_prd,
- ap->bmdma_prd_dma);
-
- free_dma(CH_ATAPI_RX);
- free_dma(CH_ATAPI_TX);
- }
-}
-
-static int bfin_port_start(struct ata_port *ap)
-{
- dev_dbg(ap->dev, "in atapi port start\n");
- if (!(ap->udma_mask || ap->mwdma_mask))
- return 0;
-
- ap->bmdma_prd = dma_alloc_coherent(ap->dev,
- BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array),
- &ap->bmdma_prd_dma,
- GFP_KERNEL);
-
- if (ap->bmdma_prd == NULL) {
- dev_info(ap->dev, "Unable to allocate DMA descriptor array.\n");
- goto out;
- }
-
- if (request_dma(CH_ATAPI_RX, "BFIN ATAPI RX DMA") >= 0) {
- if (request_dma(CH_ATAPI_TX,
- "BFIN ATAPI TX DMA") >= 0)
- return 0;
-
- free_dma(CH_ATAPI_RX);
- dma_free_coherent(ap->dev,
- BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array),
- ap->bmdma_prd,
- ap->bmdma_prd_dma);
- }
-
-out:
- ap->udma_mask = 0;
- ap->mwdma_mask = 0;
- dev_err(ap->dev, "Unable to request ATAPI DMA!"
- " Continue in PIO mode.\n");
-
- return 0;
-}
-
-static unsigned int bfin_ata_host_intr(struct ata_port *ap,
- struct ata_queued_cmd *qc)
-{
- struct ata_eh_info *ehi = &ap->link.eh_info;
- u8 status, host_stat = 0;
-
- VPRINTK("ata%u: protocol %d task_state %d\n",
- ap->print_id, qc->tf.protocol, ap->hsm_task_state);
-
- /* Check whether we are expecting interrupt in this state */
- switch (ap->hsm_task_state) {
- case HSM_ST_FIRST:
- /* Some pre-ATAPI-4 devices assert INTRQ
- * at this state when ready to receive CDB.
- */
-
- /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
- * The flag was turned on only for atapi devices.
- * No need to check is_atapi_taskfile(&qc->tf) again.
- */
- if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
- goto idle_irq;
- break;
- case HSM_ST_LAST:
- if (qc->tf.protocol == ATA_PROT_DMA ||
- qc->tf.protocol == ATAPI_PROT_DMA) {
- /* check status of DMA engine */
- host_stat = ap->ops->bmdma_status(ap);
- VPRINTK("ata%u: host_stat 0x%X\n",
- ap->print_id, host_stat);
-
- /* if it's not our irq... */
- if (!(host_stat & ATA_DMA_INTR))
- goto idle_irq;
-
- /* before we do anything else, clear DMA-Start bit */
- ap->ops->bmdma_stop(qc);
-
- if (unlikely(host_stat & ATA_DMA_ERR)) {
- /* error when transferring data to/from memory */
- qc->err_mask |= AC_ERR_HOST_BUS;
- ap->hsm_task_state = HSM_ST_ERR;
- }
- }
- break;
- case HSM_ST:
- break;
- default:
- goto idle_irq;
- }
-
- /* check altstatus */
- status = ap->ops->sff_check_altstatus(ap);
- if (status & ATA_BUSY)
- goto busy_ata;
-
- /* check main status, clearing INTRQ */
- status = ap->ops->sff_check_status(ap);
- if (unlikely(status & ATA_BUSY))
- goto busy_ata;
-
- /* ack bmdma irq events */
- ap->ops->sff_irq_clear(ap);
-
- ata_sff_hsm_move(ap, qc, status, 0);
-
- if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
- qc->tf.protocol == ATAPI_PROT_DMA))
- ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
-
-busy_ata:
- return 1; /* irq handled */
-
-idle_irq:
- ap->stats.idle_irq++;
-
-#ifdef ATA_IRQ_TRAP
- if ((ap->stats.idle_irq % 1000) == 0) {
- ap->ops->irq_ack(ap, 0); /* debug trap */
- ata_port_warn(ap, "irq trap\n");
- return 1;
- }
-#endif
- return 0; /* irq not handled */
-}
-
-static irqreturn_t bfin_ata_interrupt(int irq, void *dev_instance)
-{
- struct ata_host *host = dev_instance;
- unsigned int i;
- unsigned int handled = 0;
- unsigned long flags;
-
- /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
- spin_lock_irqsave(&host->lock, flags);
-
- for (i = 0; i < host->n_ports; i++) {
- struct ata_port *ap = host->ports[i];
- struct ata_queued_cmd *qc;
-
- qc = ata_qc_from_tag(ap, ap->link.active_tag);
- if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
- handled |= bfin_ata_host_intr(ap, qc);
- }
-
- spin_unlock_irqrestore(&host->lock, flags);
-
- return IRQ_RETVAL(handled);
-}
-
-
-static struct scsi_host_template bfin_sht = {
- ATA_BASE_SHT(DRV_NAME),
- .sg_tablesize = BFIN_MAX_SG_SEGMENTS,
- .dma_boundary = ATA_DMA_BOUNDARY,
-};
-
-static struct ata_port_operations bfin_pata_ops = {
- .inherits = &ata_bmdma_port_ops,
-
- .set_piomode = bfin_set_piomode,
- .set_dmamode = bfin_set_dmamode,
-
- .sff_tf_load = bfin_tf_load,
- .sff_tf_read = bfin_tf_read,
- .sff_exec_command = bfin_exec_command,
- .sff_check_status = bfin_check_status,
- .sff_check_altstatus = bfin_check_altstatus,
- .sff_dev_select = bfin_dev_select,
- .sff_set_devctl = bfin_set_devctl,
-
- .bmdma_setup = bfin_bmdma_setup,
- .bmdma_start = bfin_bmdma_start,
- .bmdma_stop = bfin_bmdma_stop,
- .bmdma_status = bfin_bmdma_status,
- .sff_data_xfer = bfin_data_xfer,
-
- .qc_prep = ata_noop_qc_prep,
-
- .thaw = bfin_thaw,
- .softreset = bfin_softreset,
- .postreset = bfin_postreset,
-
- .sff_irq_clear = bfin_irq_clear,
-
- .port_start = bfin_port_start,
- .port_stop = bfin_port_stop,
-};
-
-static struct ata_port_info bfin_port_info[] = {
- {
- .flags = ATA_FLAG_SLAVE_POSS,
- .pio_mask = ATA_PIO4,
- .mwdma_mask = 0,
- .udma_mask = 0,
- .port_ops = &bfin_pata_ops,
- },
-};
-
-/**
- * bfin_reset_controller - initialize BF54x ATAPI controller.
- */
-
-static int bfin_reset_controller(struct ata_host *host)
-{
- void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr;
- int count;
- unsigned short status;
-
- /* Disable all ATAPI interrupts */
- ATAPI_SET_INT_MASK(base, 0);
- SSYNC();
-
- /* Assert the RESET signal 25us*/
- ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
- udelay(30);
-
- /* Negate the RESET signal for 2ms*/
- ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
- msleep(2);
-
- /* Wait on Busy flag to clear */
- count = 10000000;
- do {
- status = read_atapi_register(base, ATA_REG_STATUS);
- } while (--count && (status & ATA_BUSY));
-
- /* Enable only ATAPI Device interrupt */
- ATAPI_SET_INT_MASK(base, 1);
- SSYNC();
-
- return (!count);
-}
-
-/**
- * atapi_io_port - define atapi peripheral port pins.
- */
-static unsigned short atapi_io_port[] = {
- P_ATAPI_RESET,
- P_ATAPI_DIOR,
- P_ATAPI_DIOW,
- P_ATAPI_CS0,
- P_ATAPI_CS1,
- P_ATAPI_DMACK,
- P_ATAPI_DMARQ,
- P_ATAPI_INTRQ,
- P_ATAPI_IORDY,
- P_ATAPI_D0A,
- P_ATAPI_D1A,
- P_ATAPI_D2A,
- P_ATAPI_D3A,
- P_ATAPI_D4A,
- P_ATAPI_D5A,
- P_ATAPI_D6A,
- P_ATAPI_D7A,
- P_ATAPI_D8A,
- P_ATAPI_D9A,
- P_ATAPI_D10A,
- P_ATAPI_D11A,
- P_ATAPI_D12A,
- P_ATAPI_D13A,
- P_ATAPI_D14A,
- P_ATAPI_D15A,
- P_ATAPI_A0A,
- P_ATAPI_A1A,
- P_ATAPI_A2A,
- 0
-};
-
-/**
- * bfin_atapi_probe - attach a bfin atapi interface
- * @pdev: platform device
- *
- * Register a bfin atapi interface.
- *
- *
- * Platform devices are expected to contain 2 resources per port:
- *
- * - I/O Base (IORESOURCE_IO)
- * - IRQ (IORESOURCE_IRQ)
- *
- */
-static int bfin_atapi_probe(struct platform_device *pdev)
-{
- int board_idx = 0;
- struct resource *res;
- struct ata_host *host;
- unsigned int fsclk = get_sclk();
- int udma_mode = 5;
- const struct ata_port_info *ppi[] =
- { &bfin_port_info[board_idx], NULL };
-
- /*
- * Simple resource validation ..
- */
- if (unlikely(pdev->num_resources != 2)) {
- dev_err(&pdev->dev, "invalid number of resources\n");
- return -EINVAL;
- }
-
- /*
- * Get the register base first
- */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL)
- return -EINVAL;
-
- while (bfin_port_info[board_idx].udma_mask > 0 &&
- udma_fsclk[udma_mode] > fsclk) {
- udma_mode--;
- bfin_port_info[board_idx].udma_mask >>= 1;
- }
-
- /*
- * Now that that's out of the way, wire up the port..
- */
- host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
- if (!host)
- return -ENOMEM;
-
- host->ports[0]->ioaddr.ctl_addr = (void *)res->start;
-
- if (peripheral_request_list(atapi_io_port, "atapi-io-port")) {
- dev_err(&pdev->dev, "Requesting Peripherals failed\n");
- return -EFAULT;
- }
-
- if (bfin_reset_controller(host)) {
- peripheral_free_list(atapi_io_port);
- dev_err(&pdev->dev, "Fail to reset ATAPI device\n");
- return -EFAULT;
- }
-
- if (ata_host_activate(host, platform_get_irq(pdev, 0),
- bfin_ata_interrupt, IRQF_SHARED, &bfin_sht) != 0) {
- peripheral_free_list(atapi_io_port);
- dev_err(&pdev->dev, "Fail to attach ATAPI device\n");
- return -ENODEV;
- }
-
- return 0;
-}
-
-/**
- * bfin_atapi_remove - unplug a bfin atapi interface
- * @pdev: platform device
- *
- * A bfin atapi device has been unplugged. Perform the needed
- * cleanup. Also called on module unload for any active devices.
- */
-static int bfin_atapi_remove(struct platform_device *pdev)
-{
- struct ata_host *host = platform_get_drvdata(pdev);
-
- ata_host_detach(host);
-
- peripheral_free_list(atapi_io_port);
-
- return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int bfin_atapi_suspend(struct platform_device *pdev, pm_message_t state)
-{
- struct ata_host *host = platform_get_drvdata(pdev);
- if (host)
- return ata_host_suspend(host, state);
- else
- return 0;
-}
-
-static int bfin_atapi_resume(struct platform_device *pdev)
-{
- struct ata_host *host = platform_get_drvdata(pdev);
- int ret;
-
- if (host) {
- ret = bfin_reset_controller(host);
- if (ret) {
- printk(KERN_ERR DRV_NAME ": Error during HW init\n");
- return ret;
- }
- ata_host_resume(host);
- }
-
- return 0;
-}
-#else
-#define bfin_atapi_suspend NULL
-#define bfin_atapi_resume NULL
-#endif
-
-static struct platform_driver bfin_atapi_driver = {
- .probe = bfin_atapi_probe,
- .remove = bfin_atapi_remove,
- .suspend = bfin_atapi_suspend,
- .resume = bfin_atapi_resume,
- .driver = {
- .name = DRV_NAME,
- },
-};
-
-#define ATAPI_MODE_SIZE 10
-static char bfin_atapi_mode[ATAPI_MODE_SIZE];
-
-static int __init bfin_atapi_init(void)
-{
- pr_info("register bfin atapi driver\n");
-
- switch(bfin_atapi_mode[0]) {
- case 'p':
- case 'P':
- break;
- case 'm':
- case 'M':
- bfin_port_info[0].mwdma_mask = ATA_MWDMA2;
- break;
- default:
- bfin_port_info[0].udma_mask = ATA_UDMA5;
- };
-
- return platform_driver_register(&bfin_atapi_driver);
-}
-
-static void __exit bfin_atapi_exit(void)
-{
- platform_driver_unregister(&bfin_atapi_driver);
-}
-
-module_init(bfin_atapi_init);
-module_exit(bfin_atapi_exit);
-/*
- * ATAPI mode:
- * pio/PIO
- * udma/UDMA (default)
- * mwdma/MWDMA
- */
-module_param_string(bfin_atapi_mode, bfin_atapi_mode, ATAPI_MODE_SIZE, 0);
-
-MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
-MODULE_DESCRIPTION("PATA driver for blackfin 54x ATAPI controller");
-MODULE_LICENSE("GPL");
-MODULE_VERSION(DRV_VERSION);
-MODULE_ALIAS("platform:" DRV_NAME);
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 20/28] pwm: Remove Blackfin PWM support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (17 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 19/28] ata: Remove Blackfin PATA support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 21/28] pcmcia: Remove Blackfin PCMCIA support Aaron Wu
` (7 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin PWM support
---
drivers/pwm/Kconfig | 9 ---
drivers/pwm/Makefile | 1 -
drivers/pwm/pwm-bfin.c | 157 -------------------------------------------------
3 files changed, 167 deletions(-)
delete mode 100644 drivers/pwm/pwm-bfin.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 763ee50..5d9868d 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -113,15 +113,6 @@ config PWM_BERLIN
To compile this driver as a module, choose M here: the module
will be called pwm-berlin.
-config PWM_BFIN
- tristate "Blackfin PWM support"
- depends on BFIN_GPTIMERS
- help
- Generic PWM framework driver for Blackfin.
-
- To compile this driver as a module, choose M here: the module
- will be called pwm-bfin.
-
config PWM_BRCMSTB
tristate "Broadcom STB PWM support"
depends on ARCH_BRCMSTB || BMIPS_GENERIC
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 0258a74..9c676a0 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -9,7 +9,6 @@ obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o
obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o
obj-$(CONFIG_PWM_BERLIN) += pwm-berlin.o
-obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
obj-$(CONFIG_PWM_BRCMSTB) += pwm-brcmstb.o
obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o
obj-$(CONFIG_PWM_CRC) += pwm-crc.o
diff --git a/drivers/pwm/pwm-bfin.c b/drivers/pwm/pwm-bfin.c
deleted file mode 100644
index a9a8813..0000000
--- a/drivers/pwm/pwm-bfin.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Blackfin Pulse Width Modulation (PWM) core
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/pwm.h>
-#include <linux/slab.h>
-
-#include <asm/gptimers.h>
-#include <asm/portmux.h>
-
-struct bfin_pwm_chip {
- struct pwm_chip chip;
-};
-
-struct bfin_pwm {
- unsigned short pin;
-};
-
-static const unsigned short pwm_to_gptimer_per[] = {
- P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR4, P_TMR5,
- P_TMR6, P_TMR7, P_TMR8, P_TMR9, P_TMR10, P_TMR11,
-};
-
-static int bfin_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
-{
- struct bfin_pwm *priv;
- int ret;
-
- if (pwm->hwpwm >= ARRAY_SIZE(pwm_to_gptimer_per))
- return -EINVAL;
-
- priv = kzalloc(sizeof(*priv), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
-
- priv->pin = pwm_to_gptimer_per[pwm->hwpwm];
-
- ret = peripheral_request(priv->pin, NULL);
- if (ret) {
- kfree(priv);
- return ret;
- }
-
- pwm_set_chip_data(pwm, priv);
-
- return 0;
-}
-
-static void bfin_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
-{
- struct bfin_pwm *priv = pwm_get_chip_data(pwm);
-
- if (priv) {
- peripheral_free(priv->pin);
- kfree(priv);
- }
-}
-
-static int bfin_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
- int duty_ns, int period_ns)
-{
- struct bfin_pwm *priv = pwm_get_chip_data(pwm);
- unsigned long period, duty;
- unsigned long long val;
-
- val = (unsigned long long)get_sclk() * period_ns;
- do_div(val, NSEC_PER_SEC);
- period = val;
-
- val = (unsigned long long)period * duty_ns;
- do_div(val, period_ns);
- duty = period - val;
-
- if (duty >= period)
- duty = period - 1;
-
- set_gptimer_config(priv->pin, TIMER_MODE_PWM | TIMER_PERIOD_CNT);
- set_gptimer_pwidth(priv->pin, duty);
- set_gptimer_period(priv->pin, period);
-
- return 0;
-}
-
-static int bfin_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
- struct bfin_pwm *priv = pwm_get_chip_data(pwm);
-
- enable_gptimer(priv->pin);
-
- return 0;
-}
-
-static void bfin_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
- struct bfin_pwm *priv = pwm_get_chip_data(pwm);
-
- disable_gptimer(priv->pin);
-}
-
-static const struct pwm_ops bfin_pwm_ops = {
- .request = bfin_pwm_request,
- .free = bfin_pwm_free,
- .config = bfin_pwm_config,
- .enable = bfin_pwm_enable,
- .disable = bfin_pwm_disable,
- .owner = THIS_MODULE,
-};
-
-static int bfin_pwm_probe(struct platform_device *pdev)
-{
- struct bfin_pwm_chip *pwm;
- int ret;
-
- pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
- if (!pwm)
- return -ENOMEM;
-
- platform_set_drvdata(pdev, pwm);
-
- pwm->chip.dev = &pdev->dev;
- pwm->chip.ops = &bfin_pwm_ops;
- pwm->chip.base = -1;
- pwm->chip.npwm = 12;
-
- ret = pwmchip_add(&pwm->chip);
- if (ret < 0) {
- dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-static int bfin_pwm_remove(struct platform_device *pdev)
-{
- struct bfin_pwm_chip *pwm = platform_get_drvdata(pdev);
-
- return pwmchip_remove(&pwm->chip);
-}
-
-static struct platform_driver bfin_pwm_driver = {
- .driver = {
- .name = "bfin-pwm",
- },
- .probe = bfin_pwm_probe,
- .remove = bfin_pwm_remove,
-};
-
-module_platform_driver(bfin_pwm_driver);
-
-MODULE_LICENSE("GPL");
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 21/28] pcmcia: Remove Blackfin PCMCIA support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (18 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 20/28] pwm: Remove Blackfin PWM support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 22/28] can: Remove Blackfin CAN bus support Aaron Wu
` (6 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin PCMCIA support
---
drivers/pcmcia/Kconfig | 7 -
drivers/pcmcia/Makefile | 1 -
drivers/pcmcia/bfin_cf_pcmcia.c | 316 ----------------------------------------
3 files changed, 324 deletions(-)
delete mode 100644 drivers/pcmcia/bfin_cf_pcmcia.c
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index d3c378b..9f63c66 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -266,13 +266,6 @@ config OMAP_CF
Say Y here to support the CompactFlash controller on OMAP.
Note that this doesn't support "True IDE" mode.
-config BFIN_CFPCMCIA
- tristate "Blackfin CompactFlash PCMCIA Driver"
- depends on PCMCIA && BLACKFIN
- help
- Say Y here to support the CompactFlash PCMCIA driver for Blackfin.
-
-
config AT91_CF
tristate "AT91 CompactFlash Controller"
depends on PCI
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index e7dae16..55a2268 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -34,7 +34,6 @@ obj-$(CONFIG_PCMCIA_BCM63XX) += bcm63xx_pcmcia.o
obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o
obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o
obj-$(CONFIG_OMAP_CF) += omap_cf.o
-obj-$(CONFIG_BFIN_CFPCMCIA) += bfin_cf_pcmcia.o
obj-$(CONFIG_AT91_CF) += at91_cf.o
obj-$(CONFIG_ELECTRA_CF) += electra_cf.o
obj-$(CONFIG_PCMCIA_ALCHEMY_DEVBOARD) += db1xxx_ss.o
diff --git a/drivers/pcmcia/bfin_cf_pcmcia.c b/drivers/pcmcia/bfin_cf_pcmcia.c
deleted file mode 100644
index 00a296d..0000000
--- a/drivers/pcmcia/bfin_cf_pcmcia.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * file: drivers/pcmcia/bfin_cf.c
- *
- * based on: drivers/pcmcia/omap_cf.c
- * omap_cf.c -- OMAP 16xx CompactFlash controller driver
- *
- * Copyright (c) 2005 David Brownell
- * Copyright (c) 2006-2008 Michael Hennerich Analog Devices Inc.
- *
- * bugs: enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose. see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/platform_device.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <pcmcia/ss.h>
-#include <pcmcia/cisreg.h>
-
-#define SZ_1K 0x00000400
-#define SZ_8K 0x00002000
-#define SZ_2K (2 * SZ_1K)
-
-#define POLL_INTERVAL (2 * HZ)
-
-#define CF_ATASEL_ENA 0x20311802 /* Inverts RESET */
-#define CF_ATASEL_DIS 0x20311800
-
-#define bfin_cf_present(pfx) (gpio_get_value(pfx))
-
-/*--------------------------------------------------------------------------*/
-
-static const char driver_name[] = "bfin_cf_pcmcia";
-
-struct bfin_cf_socket {
- struct pcmcia_socket socket;
-
- struct timer_list timer;
- unsigned present:1;
- unsigned active:1;
-
- struct platform_device *pdev;
- unsigned long phys_cf_io;
- unsigned long phys_cf_attr;
- u_int irq;
- u_short cd_pfx;
-};
-
-/*--------------------------------------------------------------------------*/
-static int bfin_cf_reset(void)
-{
- outw(0, CF_ATASEL_ENA);
- mdelay(200);
- outw(0, CF_ATASEL_DIS);
-
- return 0;
-}
-
-static int bfin_cf_ss_init(struct pcmcia_socket *s)
-{
- return 0;
-}
-
-/* the timer is primarily to kick this socket's pccardd */
-static void bfin_cf_timer(struct timer_list *t)
-{
- struct bfin_cf_socket *cf = from_timer(cf, t, timer);
- unsigned short present = bfin_cf_present(cf->cd_pfx);
-
- if (present != cf->present) {
- cf->present = present;
- dev_dbg(&cf->pdev->dev, ": card %s\n",
- present ? "present" : "gone");
- pcmcia_parse_events(&cf->socket, SS_DETECT);
- }
-
- if (cf->active)
- mod_timer(&cf->timer, jiffies + POLL_INTERVAL);
-}
-
-static int bfin_cf_get_status(struct pcmcia_socket *s, u_int *sp)
-{
- struct bfin_cf_socket *cf;
-
- if (!sp)
- return -EINVAL;
-
- cf = container_of(s, struct bfin_cf_socket, socket);
-
- if (bfin_cf_present(cf->cd_pfx)) {
- *sp = SS_READY | SS_DETECT | SS_POWERON | SS_3VCARD;
- s->pcmcia_irq = 0;
- s->pci_irq = cf->irq;
-
- } else
- *sp = 0;
- return 0;
-}
-
-static int
-bfin_cf_set_socket(struct pcmcia_socket *sock, struct socket_state_t *s)
-{
-
- struct bfin_cf_socket *cf;
- cf = container_of(sock, struct bfin_cf_socket, socket);
-
- switch (s->Vcc) {
- case 0:
- case 33:
- break;
- case 50:
- break;
- default:
- return -EINVAL;
- }
-
- if (s->flags & SS_RESET) {
- disable_irq(cf->irq);
- bfin_cf_reset();
- enable_irq(cf->irq);
- }
-
- dev_dbg(&cf->pdev->dev, ": Vcc %d, io_irq %d, flags %04x csc %04x\n",
- s->Vcc, s->io_irq, s->flags, s->csc_mask);
-
- return 0;
-}
-
-static int bfin_cf_ss_suspend(struct pcmcia_socket *s)
-{
- return bfin_cf_set_socket(s, &dead_socket);
-}
-
-/* regions are 2K each: mem, attrib, io (and reserved-for-ide) */
-
-static int bfin_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
-{
- struct bfin_cf_socket *cf;
-
- cf = container_of(s, struct bfin_cf_socket, socket);
- io->flags &= MAP_ACTIVE | MAP_ATTRIB | MAP_16BIT;
- io->start = cf->phys_cf_io;
- io->stop = io->start + SZ_2K - 1;
- return 0;
-}
-
-static int
-bfin_cf_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *map)
-{
- struct bfin_cf_socket *cf;
-
- if (map->card_start)
- return -EINVAL;
- cf = container_of(s, struct bfin_cf_socket, socket);
- map->static_start = cf->phys_cf_io;
- map->flags &= MAP_ACTIVE | MAP_ATTRIB | MAP_16BIT;
- if (map->flags & MAP_ATTRIB)
- map->static_start = cf->phys_cf_attr;
-
- return 0;
-}
-
-static struct pccard_operations bfin_cf_ops = {
- .init = bfin_cf_ss_init,
- .suspend = bfin_cf_ss_suspend,
- .get_status = bfin_cf_get_status,
- .set_socket = bfin_cf_set_socket,
- .set_io_map = bfin_cf_set_io_map,
- .set_mem_map = bfin_cf_set_mem_map,
-};
-
-/*--------------------------------------------------------------------------*/
-
-static int bfin_cf_probe(struct platform_device *pdev)
-{
- struct bfin_cf_socket *cf;
- struct resource *io_mem, *attr_mem;
- int irq;
- unsigned short cd_pfx;
- int status = 0;
-
- dev_info(&pdev->dev, "Blackfin CompactFlash/PCMCIA Socket Driver\n");
-
- irq = platform_get_irq(pdev, 0);
- if (irq <= 0)
- return -EINVAL;
-
- cd_pfx = platform_get_irq(pdev, 1); /*Card Detect GPIO PIN */
-
- if (gpio_request(cd_pfx, "pcmcia: CD")) {
- dev_err(&pdev->dev,
- "Failed ro request Card Detect GPIO_%d\n",
- cd_pfx);
- return -EBUSY;
- }
- gpio_direction_input(cd_pfx);
-
- cf = kzalloc(sizeof *cf, GFP_KERNEL);
- if (!cf) {
- gpio_free(cd_pfx);
- return -ENOMEM;
- }
-
- cf->cd_pfx = cd_pfx;
-
- timer_setup(&cf->timer, bfin_cf_timer, 0);
-
- cf->pdev = pdev;
- platform_set_drvdata(pdev, cf);
-
- cf->irq = irq;
- cf->socket.pci_irq = irq;
-
- irq_set_irq_type(irq, IRQF_TRIGGER_LOW);
-
- io_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- attr_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-
- if (!io_mem || !attr_mem)
- goto fail0;
-
- cf->phys_cf_io = io_mem->start;
- cf->phys_cf_attr = attr_mem->start;
-
- /* pcmcia layer only remaps "real" memory */
- cf->socket.io_offset = (unsigned long)
- ioremap(cf->phys_cf_io, SZ_2K);
-
- if (!cf->socket.io_offset)
- goto fail0;
-
- dev_err(&pdev->dev, ": on irq %d\n", irq);
-
- dev_dbg(&pdev->dev, ": %s\n",
- bfin_cf_present(cf->cd_pfx) ? "present" : "(not present)");
-
- cf->socket.owner = THIS_MODULE;
- cf->socket.dev.parent = &pdev->dev;
- cf->socket.ops = &bfin_cf_ops;
- cf->socket.resource_ops = &pccard_static_ops;
- cf->socket.features = SS_CAP_PCCARD | SS_CAP_STATIC_MAP
- | SS_CAP_MEM_ALIGN;
- cf->socket.map_size = SZ_2K;
-
- status = pcmcia_register_socket(&cf->socket);
- if (status < 0)
- goto fail2;
-
- cf->active = 1;
- mod_timer(&cf->timer, jiffies + POLL_INTERVAL);
- return 0;
-
-fail2:
- iounmap((void __iomem *)cf->socket.io_offset);
- release_mem_region(cf->phys_cf_io, SZ_8K);
-
-fail0:
- gpio_free(cf->cd_pfx);
- kfree(cf);
- platform_set_drvdata(pdev, NULL);
-
- return status;
-}
-
-static int bfin_cf_remove(struct platform_device *pdev)
-{
- struct bfin_cf_socket *cf = platform_get_drvdata(pdev);
-
- gpio_free(cf->cd_pfx);
- cf->active = 0;
- pcmcia_unregister_socket(&cf->socket);
- del_timer_sync(&cf->timer);
- iounmap((void __iomem *)cf->socket.io_offset);
- release_mem_region(cf->phys_cf_io, SZ_8K);
- platform_set_drvdata(pdev, NULL);
- kfree(cf);
- return 0;
-}
-
-static struct platform_driver bfin_cf_driver = {
- .driver = {
- .name = driver_name,
- },
- .probe = bfin_cf_probe,
- .remove = bfin_cf_remove,
-};
-
-module_platform_driver(bfin_cf_driver);
-
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("BFIN CF/PCMCIA Driver");
-MODULE_LICENSE("GPL");
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 22/28] can: Remove Blackfin CAN bus support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (19 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 21/28] pcmcia: Remove Blackfin PCMCIA support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 23/28] char: Remove Blackfin OTP support Aaron Wu
` (5 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin CAN bus support
---
drivers/net/can/Kconfig | 9 -
drivers/net/can/Makefile | 1 -
drivers/net/can/bfin_can.c | 784 ---------------------------------------------
3 files changed, 794 deletions(-)
delete mode 100644 drivers/net/can/bfin_can.c
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index ac4ff39..2cb7598 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -88,15 +88,6 @@ config CAN_AT91
This is a driver for the SoC CAN controller in Atmel's AT91SAM9263
and AT91SAM9X5 processors.
-config CAN_BFIN
- depends on BF534 || BF536 || BF537 || BF538 || BF539 || BF54x
- tristate "Analog Devices Blackfin on-chip CAN"
- ---help---
- Driver for the Analog Devices Blackfin on-chip CAN controllers
-
- To compile this driver as a module, choose M here: the
- module will be called bfin_can.
-
config CAN_FLEXCAN
tristate "Support for Freescale FLEXCAN based chips"
depends on ARM || PPC
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 02b8ed7..44922bf 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -19,7 +19,6 @@ obj-y += usb/
obj-y += softing/
obj-$(CONFIG_CAN_AT91) += at91_can.o
-obj-$(CONFIG_CAN_BFIN) += bfin_can.o
obj-$(CONFIG_CAN_CC770) += cc770/
obj-$(CONFIG_CAN_C_CAN) += c_can/
obj-$(CONFIG_CAN_FLEXCAN) += flexcan.o
diff --git a/drivers/net/can/bfin_can.c b/drivers/net/can/bfin_can.c
deleted file mode 100644
index 1deb8ff9..0000000
--- a/drivers/net/can/bfin_can.c
+++ /dev/null
@@ -1,784 +0,0 @@
-/*
- * Blackfin On-Chip CAN Driver
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <linux/netdevice.h>
-#include <linux/skbuff.h>
-#include <linux/platform_device.h>
-
-#include <linux/can/dev.h>
-#include <linux/can/error.h>
-
-#include <asm/portmux.h>
-
-#define DRV_NAME "bfin_can"
-#define BFIN_CAN_TIMEOUT 100
-#define TX_ECHO_SKB_MAX 1
-
-/* transmit and receive channels */
-#define TRANSMIT_CHL 24
-#define RECEIVE_STD_CHL 0
-#define RECEIVE_EXT_CHL 4
-#define RECEIVE_RTR_CHL 8
-#define RECEIVE_EXT_RTR_CHL 12
-#define MAX_CHL_NUMBER 32
-
-/* All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/* bfin can registers layout */
-struct bfin_can_mask_regs {
- __BFP(aml);
- __BFP(amh);
-};
-
-struct bfin_can_channel_regs {
- /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
- u16 data[8];
- __BFP(dlc);
- __BFP(tsv);
- __BFP(id0);
- __BFP(id1);
-};
-
-struct bfin_can_regs {
- /* global control and status registers */
- __BFP(mc1); /* offset 0x00 */
- __BFP(md1); /* offset 0x04 */
- __BFP(trs1); /* offset 0x08 */
- __BFP(trr1); /* offset 0x0c */
- __BFP(ta1); /* offset 0x10 */
- __BFP(aa1); /* offset 0x14 */
- __BFP(rmp1); /* offset 0x18 */
- __BFP(rml1); /* offset 0x1c */
- __BFP(mbtif1); /* offset 0x20 */
- __BFP(mbrif1); /* offset 0x24 */
- __BFP(mbim1); /* offset 0x28 */
- __BFP(rfh1); /* offset 0x2c */
- __BFP(opss1); /* offset 0x30 */
- u32 __pad1[3];
- __BFP(mc2); /* offset 0x40 */
- __BFP(md2); /* offset 0x44 */
- __BFP(trs2); /* offset 0x48 */
- __BFP(trr2); /* offset 0x4c */
- __BFP(ta2); /* offset 0x50 */
- __BFP(aa2); /* offset 0x54 */
- __BFP(rmp2); /* offset 0x58 */
- __BFP(rml2); /* offset 0x5c */
- __BFP(mbtif2); /* offset 0x60 */
- __BFP(mbrif2); /* offset 0x64 */
- __BFP(mbim2); /* offset 0x68 */
- __BFP(rfh2); /* offset 0x6c */
- __BFP(opss2); /* offset 0x70 */
- u32 __pad2[3];
- __BFP(clock); /* offset 0x80 */
- __BFP(timing); /* offset 0x84 */
- __BFP(debug); /* offset 0x88 */
- __BFP(status); /* offset 0x8c */
- __BFP(cec); /* offset 0x90 */
- __BFP(gis); /* offset 0x94 */
- __BFP(gim); /* offset 0x98 */
- __BFP(gif); /* offset 0x9c */
- __BFP(control); /* offset 0xa0 */
- __BFP(intr); /* offset 0xa4 */
- __BFP(version); /* offset 0xa8 */
- __BFP(mbtd); /* offset 0xac */
- __BFP(ewr); /* offset 0xb0 */
- __BFP(esr); /* offset 0xb4 */
- u32 __pad3[2];
- __BFP(ucreg); /* offset 0xc0 */
- __BFP(uccnt); /* offset 0xc4 */
- __BFP(ucrc); /* offset 0xc8 */
- __BFP(uccnf); /* offset 0xcc */
- u32 __pad4[1];
- __BFP(version2); /* offset 0xd4 */
- u32 __pad5[10];
-
- /* channel(mailbox) mask and message registers */
- struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */
- struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
-};
-
-#undef __BFP
-
-#define SRS 0x0001 /* Software Reset */
-#define SER 0x0008 /* Stuff Error */
-#define BOIM 0x0008 /* Enable Bus Off Interrupt */
-#define CCR 0x0080 /* CAN Configuration Mode Request */
-#define CCA 0x0080 /* Configuration Mode Acknowledge */
-#define SAM 0x0080 /* Sampling */
-#define AME 0x8000 /* Acceptance Mask Enable */
-#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
-#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
-#define RTR 0x4000 /* Remote Frame Transmission Request */
-#define BOIS 0x0008 /* Bus Off IRQ Status */
-#define IDE 0x2000 /* Identifier Extension */
-#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
-#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
-#define EWTIS 0x0001 /* TX Error Count IRQ Status */
-#define EWRIS 0x0002 /* RX Error Count IRQ Status */
-#define BEF 0x0040 /* Bit Error Flag */
-#define FER 0x0080 /* Form Error Flag */
-#define SMR 0x0020 /* Sleep Mode Request */
-#define SMACK 0x0008 /* Sleep Mode Acknowledge */
-
-/*
- * bfin can private data
- */
-struct bfin_can_priv {
- struct can_priv can; /* must be the first member */
- struct net_device *dev;
- void __iomem *membase;
- int rx_irq;
- int tx_irq;
- int err_irq;
- unsigned short *pin_list;
-};
-
-/*
- * bfin can timing parameters
- */
-static const struct can_bittiming_const bfin_can_bittiming_const = {
- .name = DRV_NAME,
- .tseg1_min = 1,
- .tseg1_max = 16,
- .tseg2_min = 1,
- .tseg2_max = 8,
- .sjw_max = 4,
- /*
- * Although the BRP field can be set to any value, it is recommended
- * that the value be greater than or equal to 4, as restrictions
- * apply to the bit timing configuration when BRP is less than 4.
- */
- .brp_min = 4,
- .brp_max = 1024,
- .brp_inc = 1,
-};
-
-static int bfin_can_set_bittiming(struct net_device *dev)
-{
- struct bfin_can_priv *priv = netdev_priv(dev);
- struct bfin_can_regs __iomem *reg = priv->membase;
- struct can_bittiming *bt = &priv->can.bittiming;
- u16 clk, timing;
-
- clk = bt->brp - 1;
- timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) |
- ((bt->phase_seg2 - 1) << 4);
-
- /*
- * If the SAM bit is set, the input signal is oversampled three times
- *@the SCLK rate.
- */
- if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
- timing |= SAM;
-
- writew(clk, ®->clock);
- writew(timing, ®->timing);
-
- netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing);
-
- return 0;
-}
-
-static void bfin_can_set_reset_mode(struct net_device *dev)
-{
- struct bfin_can_priv *priv = netdev_priv(dev);
- struct bfin_can_regs __iomem *reg = priv->membase;
- int timeout = BFIN_CAN_TIMEOUT;
- int i;
-
- /* disable interrupts */
- writew(0, ®->mbim1);
- writew(0, ®->mbim2);
- writew(0, ®->gim);
-
- /* reset can and enter configuration mode */
- writew(SRS | CCR, ®->control);
- writew(CCR, ®->control);
- while (!(readw(®->control) & CCA)) {
- udelay(10);
- if (--timeout == 0) {
- netdev_err(dev, "fail to enter configuration mode\n");
- BUG();
- }
- }
-
- /*
- * All mailbox configurations are marked as inactive
- * by writing to CAN Mailbox Configuration Registers 1 and 2
- * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled
- */
- writew(0, ®->mc1);
- writew(0, ®->mc2);
-
- /* Set Mailbox Direction */
- writew(0xFFFF, ®->md1); /* mailbox 1-16 are RX */
- writew(0, ®->md2); /* mailbox 17-32 are TX */
-
- /* RECEIVE_STD_CHL */
- for (i = 0; i < 2; i++) {
- writew(0, ®->chl[RECEIVE_STD_CHL + i].id0);
- writew(AME, ®->chl[RECEIVE_STD_CHL + i].id1);
- writew(0, ®->chl[RECEIVE_STD_CHL + i].dlc);
- writew(0x1FFF, ®->msk[RECEIVE_STD_CHL + i].amh);
- writew(0xFFFF, ®->msk[RECEIVE_STD_CHL + i].aml);
- }
-
- /* RECEIVE_EXT_CHL */
- for (i = 0; i < 2; i++) {
- writew(0, ®->chl[RECEIVE_EXT_CHL + i].id0);
- writew(AME | IDE, ®->chl[RECEIVE_EXT_CHL + i].id1);
- writew(0, ®->chl[RECEIVE_EXT_CHL + i].dlc);
- writew(0x1FFF, ®->msk[RECEIVE_EXT_CHL + i].amh);
- writew(0xFFFF, ®->msk[RECEIVE_EXT_CHL + i].aml);
- }
-
- writew(BIT(TRANSMIT_CHL - 16), ®->mc2);
- writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), ®->mc1);
-
- priv->can.state = CAN_STATE_STOPPED;
-}
-
-static void bfin_can_set_normal_mode(struct net_device *dev)
-{
- struct bfin_can_priv *priv = netdev_priv(dev);
- struct bfin_can_regs __iomem *reg = priv->membase;
- int timeout = BFIN_CAN_TIMEOUT;
-
- /*
- * leave configuration mode
- */
- writew(readw(®->control) & ~CCR, ®->control);
-
- while (readw(®->status) & CCA) {
- udelay(10);
- if (--timeout == 0) {
- netdev_err(dev, "fail to leave configuration mode\n");
- BUG();
- }
- }
-
- /*
- * clear _All_ tx and rx interrupts
- */
- writew(0xFFFF, ®->mbtif1);
- writew(0xFFFF, ®->mbtif2);
- writew(0xFFFF, ®->mbrif1);
- writew(0xFFFF, ®->mbrif2);
-
- /*
- * clear global interrupt status register
- */
- writew(0x7FF, ®->gis); /* overwrites with '1' */
-
- /*
- * Initialize Interrupts
- * - set bits in the mailbox interrupt mask register
- * - global interrupt mask
- */
- writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), ®->mbim1);
- writew(BIT(TRANSMIT_CHL - 16), ®->mbim2);
-
- writew(EPIM | BOIM | RMLIM, ®->gim);
-}
-
-static void bfin_can_start(struct net_device *dev)
-{
- struct bfin_can_priv *priv = netdev_priv(dev);
-
- /* enter reset mode */
- if (priv->can.state != CAN_STATE_STOPPED)
- bfin_can_set_reset_mode(dev);
-
- /* leave reset mode */
- bfin_can_set_normal_mode(dev);
-}
-
-static int bfin_can_set_mode(struct net_device *dev, enum can_mode mode)
-{
- switch (mode) {
- case CAN_MODE_START:
- bfin_can_start(dev);
- if (netif_queue_stopped(dev))
- netif_wake_queue(dev);
- break;
-
- default:
- return -EOPNOTSUPP;
- }
-
- return 0;
-}
-
-static int bfin_can_get_berr_counter(const struct net_device *dev,
- struct can_berr_counter *bec)
-{
- struct bfin_can_priv *priv = netdev_priv(dev);
- struct bfin_can_regs __iomem *reg = priv->membase;
-
- u16 cec = readw(®->cec);
-
- bec->txerr = cec >> 8;
- bec->rxerr = cec;
-
- return 0;
-}
-
-static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev)
-{
- struct bfin_can_priv *priv = netdev_priv(dev);
- struct bfin_can_regs __iomem *reg = priv->membase;
- struct can_frame *cf = (struct can_frame *)skb->data;
- u8 dlc = cf->can_dlc;
- canid_t id = cf->can_id;
- u8 *data = cf->data;
- u16 val;
- int i;
-
- if (can_dropped_invalid_skb(dev, skb))
- return NETDEV_TX_OK;
-
- netif_stop_queue(dev);
-
- /* fill id */
- if (id & CAN_EFF_FLAG) {
- writew(id, ®->chl[TRANSMIT_CHL].id0);
- val = ((id & 0x1FFF0000) >> 16) | IDE;
- } else
- val = (id << 2);
- if (id & CAN_RTR_FLAG)
- val |= RTR;
- writew(val | AME, ®->chl[TRANSMIT_CHL].id1);
-
- /* fill payload */
- for (i = 0; i < 8; i += 2) {
- val = ((7 - i) < dlc ? (data[7 - i]) : 0) +
- ((6 - i) < dlc ? (data[6 - i] << 8) : 0);
- writew(val, ®->chl[TRANSMIT_CHL].data[i]);
- }
-
- /* fill data length code */
- writew(dlc, ®->chl[TRANSMIT_CHL].dlc);
-
- can_put_echo_skb(skb, dev, 0);
-
- /* set transmit request */
- writew(BIT(TRANSMIT_CHL - 16), ®->trs2);
-
- return 0;
-}
-
-static void bfin_can_rx(struct net_device *dev, u16 isrc)
-{
- struct bfin_can_priv *priv = netdev_priv(dev);
- struct net_device_stats *stats = &dev->stats;
- struct bfin_can_regs __iomem *reg = priv->membase;
- struct can_frame *cf;
- struct sk_buff *skb;
- int obj;
- int i;
- u16 val;
-
- skb = alloc_can_skb(dev, &cf);
- if (skb == NULL)
- return;
-
- /* get id */
- if (isrc & BIT(RECEIVE_EXT_CHL)) {
- /* extended frame format (EFF) */
- cf->can_id = ((readw(®->chl[RECEIVE_EXT_CHL].id1)
- & 0x1FFF) << 16)
- + readw(®->chl[RECEIVE_EXT_CHL].id0);
- cf->can_id |= CAN_EFF_FLAG;
- obj = RECEIVE_EXT_CHL;
- } else {
- /* standard frame format (SFF) */
- cf->can_id = (readw(®->chl[RECEIVE_STD_CHL].id1)
- & 0x1ffc) >> 2;
- obj = RECEIVE_STD_CHL;
- }
- if (readw(®->chl[obj].id1) & RTR)
- cf->can_id |= CAN_RTR_FLAG;
-
- /* get data length code */
- cf->can_dlc = get_can_dlc(readw(®->chl[obj].dlc) & 0xF);
-
- /* get payload */
- for (i = 0; i < 8; i += 2) {
- val = readw(®->chl[obj].data[i]);
- cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0;
- cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0;
- }
-
- stats->rx_packets++;
- stats->rx_bytes += cf->can_dlc;
- netif_rx(skb);
-}
-
-static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status)
-{
- struct bfin_can_priv *priv = netdev_priv(dev);
- struct bfin_can_regs __iomem *reg = priv->membase;
- struct net_device_stats *stats = &dev->stats;
- struct can_frame *cf;
- struct sk_buff *skb;
- enum can_state state = priv->can.state;
-
- skb = alloc_can_err_skb(dev, &cf);
- if (skb == NULL)
- return -ENOMEM;
-
- if (isrc & RMLIS) {
- /* data overrun interrupt */
- netdev_dbg(dev, "data overrun interrupt\n");
- cf->can_id |= CAN_ERR_CRTL;
- cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
- stats->rx_over_errors++;
- stats->rx_errors++;
- }
-
- if (isrc & BOIS) {
- netdev_dbg(dev, "bus-off mode interrupt\n");
- state = CAN_STATE_BUS_OFF;
- cf->can_id |= CAN_ERR_BUSOFF;
- priv->can.can_stats.bus_off++;
- can_bus_off(dev);
- }
-
- if (isrc & EPIS) {
- /* error passive interrupt */
- netdev_dbg(dev, "error passive interrupt\n");
- state = CAN_STATE_ERROR_PASSIVE;
- }
-
- if ((isrc & EWTIS) || (isrc & EWRIS)) {
- netdev_dbg(dev, "Error Warning Transmit/Receive Interrupt\n");
- state = CAN_STATE_ERROR_WARNING;
- }
-
- if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
- state == CAN_STATE_ERROR_PASSIVE)) {
- u16 cec = readw(®->cec);
- u8 rxerr = cec;
- u8 txerr = cec >> 8;
-
- cf->can_id |= CAN_ERR_CRTL;
- if (state == CAN_STATE_ERROR_WARNING) {
- priv->can.can_stats.error_warning++;
- cf->data[1] = (txerr > rxerr) ?
- CAN_ERR_CRTL_TX_WARNING :
- CAN_ERR_CRTL_RX_WARNING;
- } else {
- priv->can.can_stats.error_passive++;
- cf->data[1] = (txerr > rxerr) ?
- CAN_ERR_CRTL_TX_PASSIVE :
- CAN_ERR_CRTL_RX_PASSIVE;
- }
- }
-
- if (status) {
- priv->can.can_stats.bus_error++;
-
- cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
-
- if (status & BEF)
- cf->data[2] |= CAN_ERR_PROT_BIT;
- else if (status & FER)
- cf->data[2] |= CAN_ERR_PROT_FORM;
- else if (status & SER)
- cf->data[2] |= CAN_ERR_PROT_STUFF;
- }
-
- priv->can.state = state;
-
- stats->rx_packets++;
- stats->rx_bytes += cf->can_dlc;
- netif_rx(skb);
-
- return 0;
-}
-
-static irqreturn_t bfin_can_interrupt(int irq, void *dev_id)
-{
- struct net_device *dev = dev_id;
- struct bfin_can_priv *priv = netdev_priv(dev);
- struct bfin_can_regs __iomem *reg = priv->membase;
- struct net_device_stats *stats = &dev->stats;
- u16 status, isrc;
-
- if ((irq == priv->tx_irq) && readw(®->mbtif2)) {
- /* transmission complete interrupt */
- writew(0xFFFF, ®->mbtif2);
- stats->tx_packets++;
- stats->tx_bytes += readw(®->chl[TRANSMIT_CHL].dlc);
- can_get_echo_skb(dev, 0);
- netif_wake_queue(dev);
- } else if ((irq == priv->rx_irq) && readw(®->mbrif1)) {
- /* receive interrupt */
- isrc = readw(®->mbrif1);
- writew(0xFFFF, ®->mbrif1);
- bfin_can_rx(dev, isrc);
- } else if ((irq == priv->err_irq) && readw(®->gis)) {
- /* error interrupt */
- isrc = readw(®->gis);
- status = readw(®->esr);
- writew(0x7FF, ®->gis);
- bfin_can_err(dev, isrc, status);
- } else {
- return IRQ_NONE;
- }
-
- return IRQ_HANDLED;
-}
-
-static int bfin_can_open(struct net_device *dev)
-{
- struct bfin_can_priv *priv = netdev_priv(dev);
- int err;
-
- /* set chip into reset mode */
- bfin_can_set_reset_mode(dev);
-
- /* common open */
- err = open_candev(dev);
- if (err)
- goto exit_open;
-
- /* register interrupt handler */
- err = request_irq(priv->rx_irq, &bfin_can_interrupt, 0,
- "bfin-can-rx", dev);
- if (err)
- goto exit_rx_irq;
- err = request_irq(priv->tx_irq, &bfin_can_interrupt, 0,
- "bfin-can-tx", dev);
- if (err)
- goto exit_tx_irq;
- err = request_irq(priv->err_irq, &bfin_can_interrupt, 0,
- "bfin-can-err", dev);
- if (err)
- goto exit_err_irq;
-
- bfin_can_start(dev);
-
- netif_start_queue(dev);
-
- return 0;
-
-exit_err_irq:
- free_irq(priv->tx_irq, dev);
-exit_tx_irq:
- free_irq(priv->rx_irq, dev);
-exit_rx_irq:
- close_candev(dev);
-exit_open:
- return err;
-}
-
-static int bfin_can_close(struct net_device *dev)
-{
- struct bfin_can_priv *priv = netdev_priv(dev);
-
- netif_stop_queue(dev);
- bfin_can_set_reset_mode(dev);
-
- close_candev(dev);
-
- free_irq(priv->rx_irq, dev);
- free_irq(priv->tx_irq, dev);
- free_irq(priv->err_irq, dev);
-
- return 0;
-}
-
-static struct net_device *alloc_bfin_candev(void)
-{
- struct net_device *dev;
- struct bfin_can_priv *priv;
-
- dev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX);
- if (!dev)
- return NULL;
-
- priv = netdev_priv(dev);
-
- priv->dev = dev;
- priv->can.bittiming_const = &bfin_can_bittiming_const;
- priv->can.do_set_bittiming = bfin_can_set_bittiming;
- priv->can.do_set_mode = bfin_can_set_mode;
- priv->can.do_get_berr_counter = bfin_can_get_berr_counter;
- priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
-
- return dev;
-}
-
-static const struct net_device_ops bfin_can_netdev_ops = {
- .ndo_open = bfin_can_open,
- .ndo_stop = bfin_can_close,
- .ndo_start_xmit = bfin_can_start_xmit,
- .ndo_change_mtu = can_change_mtu,
-};
-
-static int bfin_can_probe(struct platform_device *pdev)
-{
- int err;
- struct net_device *dev;
- struct bfin_can_priv *priv;
- struct resource *res_mem, *rx_irq, *tx_irq, *err_irq;
- unsigned short *pdata;
-
- pdata = dev_get_platdata(&pdev->dev);
- if (!pdata) {
- dev_err(&pdev->dev, "No platform data provided!\n");
- err = -EINVAL;
- goto exit;
- }
-
- res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- rx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- tx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
- err_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
- if (!res_mem || !rx_irq || !tx_irq || !err_irq) {
- err = -EINVAL;
- goto exit;
- }
-
- /* request peripheral pins */
- err = peripheral_request_list(pdata, dev_name(&pdev->dev));
- if (err)
- goto exit;
-
- dev = alloc_bfin_candev();
- if (!dev) {
- err = -ENOMEM;
- goto exit_peri_pin_free;
- }
-
- priv = netdev_priv(dev);
-
- priv->membase = devm_ioremap_resource(&pdev->dev, res_mem);
- if (IS_ERR(priv->membase)) {
- err = PTR_ERR(priv->membase);
- goto exit_peri_pin_free;
- }
-
- priv->rx_irq = rx_irq->start;
- priv->tx_irq = tx_irq->start;
- priv->err_irq = err_irq->start;
- priv->pin_list = pdata;
- priv->can.clock.freq = get_sclk();
-
- platform_set_drvdata(pdev, dev);
- SET_NETDEV_DEV(dev, &pdev->dev);
-
- dev->flags |= IFF_ECHO; /* we support local echo */
- dev->netdev_ops = &bfin_can_netdev_ops;
-
- bfin_can_set_reset_mode(dev);
-
- err = register_candev(dev);
- if (err) {
- dev_err(&pdev->dev, "registering failed (err=%d)\n", err);
- goto exit_candev_free;
- }
-
- dev_info(&pdev->dev,
- "%s device registered"
- "(®_base=%p, rx_irq=%d, tx_irq=%d, err_irq=%d, sclk=%d)\n",
- DRV_NAME, priv->membase, priv->rx_irq,
- priv->tx_irq, priv->err_irq, priv->can.clock.freq);
- return 0;
-
-exit_candev_free:
- free_candev(dev);
-exit_peri_pin_free:
- peripheral_free_list(pdata);
-exit:
- return err;
-}
-
-static int bfin_can_remove(struct platform_device *pdev)
-{
- struct net_device *dev = platform_get_drvdata(pdev);
- struct bfin_can_priv *priv = netdev_priv(dev);
-
- bfin_can_set_reset_mode(dev);
-
- unregister_candev(dev);
-
- peripheral_free_list(priv->pin_list);
-
- free_candev(dev);
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg)
-{
- struct net_device *dev = platform_get_drvdata(pdev);
- struct bfin_can_priv *priv = netdev_priv(dev);
- struct bfin_can_regs __iomem *reg = priv->membase;
- int timeout = BFIN_CAN_TIMEOUT;
-
- if (netif_running(dev)) {
- /* enter sleep mode */
- writew(readw(®->control) | SMR, ®->control);
- while (!(readw(®->intr) & SMACK)) {
- udelay(10);
- if (--timeout == 0) {
- netdev_err(dev, "fail to enter sleep mode\n");
- BUG();
- }
- }
- }
-
- return 0;
-}
-
-static int bfin_can_resume(struct platform_device *pdev)
-{
- struct net_device *dev = platform_get_drvdata(pdev);
- struct bfin_can_priv *priv = netdev_priv(dev);
- struct bfin_can_regs __iomem *reg = priv->membase;
-
- if (netif_running(dev)) {
- /* leave sleep mode */
- writew(0, ®->intr);
- }
-
- return 0;
-}
-#else
-#define bfin_can_suspend NULL
-#define bfin_can_resume NULL
-#endif /* CONFIG_PM */
-
-static struct platform_driver bfin_can_driver = {
- .probe = bfin_can_probe,
- .remove = bfin_can_remove,
- .suspend = bfin_can_suspend,
- .resume = bfin_can_resume,
- .driver = {
- .name = DRV_NAME,
- },
-};
-
-module_platform_driver(bfin_can_driver);
-
-MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Blackfin on-chip CAN netdevice driver");
-MODULE_ALIAS("platform:" DRV_NAME);
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 23/28] char: Remove Blackfin OTP support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (20 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 22/28] can: Remove Blackfin CAN bus support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 24/28] pinctrl: Remove Blackfin pinctrl support Aaron Wu
` (4 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin OTP support
---
drivers/char/Kconfig | 28 ------
drivers/char/Makefile | 1 -
drivers/char/bfin-otp.c | 237 ------------------------------------------------
3 files changed, 266 deletions(-)
delete mode 100644 drivers/char/bfin-otp.c
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index c28dca0..8f64ce8 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -66,34 +66,6 @@ config TTY_PRINTK
If unsure, say N.
-config BFIN_OTP
- tristate "Blackfin On-Chip OTP Memory Support"
- depends on BLACKFIN && (BF51x || BF52x || BF54x)
- default y
- help
- If you say Y here, you will get support for a character device
- interface into the One Time Programmable memory pages that are
- stored on the Blackfin processor. This will not get you access
- to the secure memory pages however. You will need to write your
- own secure code and reader for that.
-
- To compile this driver as a module, choose M here: the module
- will be called bfin-otp.
-
- If unsure, it is safe to say Y.
-
-config BFIN_OTP_WRITE_ENABLE
- bool "Enable writing support of OTP pages"
- depends on BFIN_OTP
- default n
- help
- If you say Y here, you will enable support for writing of the
- OTP pages. This is dangerous by nature as you can only program
- the pages once, so only enable this option when you actually
- need it so as to not inadvertently clobber data.
-
- If unsure, say N.
-
config PRINTER
tristate "Parallel printer support"
depends on PARPORT
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 7dc3abe..f28d07b 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_MSPEC) += mspec.o
obj-$(CONFIG_UV_MMTIMER) += uv_mmtimer.o
obj-$(CONFIG_IBM_BSR) += bsr.o
obj-$(CONFIG_SGI_MBCS) += mbcs.o
-obj-$(CONFIG_BFIN_OTP) += bfin-otp.o
obj-$(CONFIG_PRINTER) += lp.o
diff --git a/drivers/char/bfin-otp.c b/drivers/char/bfin-otp.c
deleted file mode 100644
index 0584025..0000000
--- a/drivers/char/bfin-otp.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * Blackfin On-Chip OTP Memory Interface
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/miscdevice.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/types.h>
-#include <mtd/mtd-abi.h>
-
-#include <asm/blackfin.h>
-#include <asm/bfrom.h>
-#include <linux/uaccess.h>
-
-#define stamp(fmt, args...) pr_debug("%s:%i: " fmt "\n", __func__, __LINE__, ## args)
-#define stampit() stamp("here i am")
-#define pr_init(fmt, args...) ({ static const __initconst char __fmt[] = fmt; printk(__fmt, ## args); })
-
-#define DRIVER_NAME "bfin-otp"
-#define PFX DRIVER_NAME ": "
-
-static DEFINE_MUTEX(bfin_otp_lock);
-
-/**
- * bfin_otp_read - Read OTP pages
- *
- * All reads must be in half page chunks (half page == 64 bits).
- */
-static ssize_t bfin_otp_read(struct file *file, char __user *buff, size_t count, loff_t *pos)
-{
- ssize_t bytes_done;
- u32 page, flags, ret;
- u64 content;
-
- stampit();
-
- if (count % sizeof(u64))
- return -EMSGSIZE;
-
- if (mutex_lock_interruptible(&bfin_otp_lock))
- return -ERESTARTSYS;
-
- bytes_done = 0;
- page = *pos / (sizeof(u64) * 2);
- while (bytes_done < count) {
- flags = (*pos % (sizeof(u64) * 2) ? OTP_UPPER_HALF : OTP_LOWER_HALF);
- stamp("processing page %i (0x%x:%s)", page, flags,
- (flags & OTP_UPPER_HALF ? "upper" : "lower"));
- ret = bfrom_OtpRead(page, flags, &content);
- if (ret & OTP_MASTER_ERROR) {
- stamp("error from otp: 0x%x", ret);
- bytes_done = -EIO;
- break;
- }
- if (copy_to_user(buff + bytes_done, &content, sizeof(content))) {
- bytes_done = -EFAULT;
- break;
- }
- if (flags & OTP_UPPER_HALF)
- ++page;
- bytes_done += sizeof(content);
- *pos += sizeof(content);
- }
-
- mutex_unlock(&bfin_otp_lock);
-
- return bytes_done;
-}
-
-#ifdef CONFIG_BFIN_OTP_WRITE_ENABLE
-static bool allow_writes;
-
-/**
- * bfin_otp_init_timing - setup OTP timing parameters
- *
- * Required before doing any write operation. Algorithms from HRM.
- */
-static u32 bfin_otp_init_timing(void)
-{
- u32 tp1, tp2, tp3, timing;
-
- tp1 = get_sclk() / 1000000;
- tp2 = (2 * get_sclk() / 10000000) << 8;
- tp3 = (0x1401) << 15;
- timing = tp1 | tp2 | tp3;
- if (bfrom_OtpCommand(OTP_INIT, timing))
- return 0;
-
- return timing;
-}
-
-/**
- * bfin_otp_deinit_timing - set timings to only allow reads
- *
- * Should be called after all writes are done.
- */
-static void bfin_otp_deinit_timing(u32 timing)
-{
- /* mask bits [31:15] so that any attempts to write fail */
- bfrom_OtpCommand(OTP_CLOSE, 0);
- bfrom_OtpCommand(OTP_INIT, timing & ~(-1 << 15));
- bfrom_OtpCommand(OTP_CLOSE, 0);
-}
-
-/**
- * bfin_otp_write - write OTP pages
- *
- * All writes must be in half page chunks (half page == 64 bits).
- */
-static ssize_t bfin_otp_write(struct file *filp, const char __user *buff, size_t count, loff_t *pos)
-{
- ssize_t bytes_done;
- u32 timing, page, base_flags, flags, ret;
- u64 content;
-
- if (!allow_writes)
- return -EACCES;
-
- if (count % sizeof(u64))
- return -EMSGSIZE;
-
- if (mutex_lock_interruptible(&bfin_otp_lock))
- return -ERESTARTSYS;
-
- stampit();
-
- timing = bfin_otp_init_timing();
- if (timing == 0) {
- mutex_unlock(&bfin_otp_lock);
- return -EIO;
- }
-
- base_flags = OTP_CHECK_FOR_PREV_WRITE;
-
- bytes_done = 0;
- page = *pos / (sizeof(u64) * 2);
- while (bytes_done < count) {
- flags = base_flags | (*pos % (sizeof(u64) * 2) ? OTP_UPPER_HALF : OTP_LOWER_HALF);
- stamp("processing page %i (0x%x:%s) from %p", page, flags,
- (flags & OTP_UPPER_HALF ? "upper" : "lower"), buff + bytes_done);
- if (copy_from_user(&content, buff + bytes_done, sizeof(content))) {
- bytes_done = -EFAULT;
- break;
- }
- ret = bfrom_OtpWrite(page, flags, &content);
- if (ret & OTP_MASTER_ERROR) {
- stamp("error from otp: 0x%x", ret);
- bytes_done = -EIO;
- break;
- }
- if (flags & OTP_UPPER_HALF)
- ++page;
- bytes_done += sizeof(content);
- *pos += sizeof(content);
- }
-
- bfin_otp_deinit_timing(timing);
-
- mutex_unlock(&bfin_otp_lock);
-
- return bytes_done;
-}
-
-static long bfin_otp_ioctl(struct file *filp, unsigned cmd, unsigned long arg)
-{
- stampit();
-
- switch (cmd) {
- case OTPLOCK: {
- u32 timing;
- int ret = -EIO;
-
- if (!allow_writes)
- return -EACCES;
-
- if (mutex_lock_interruptible(&bfin_otp_lock))
- return -ERESTARTSYS;
-
- timing = bfin_otp_init_timing();
- if (timing) {
- u32 otp_result = bfrom_OtpWrite(arg, OTP_LOCK, NULL);
- stamp("locking page %lu resulted in 0x%x", arg, otp_result);
- if (!(otp_result & OTP_MASTER_ERROR))
- ret = 0;
-
- bfin_otp_deinit_timing(timing);
- }
-
- mutex_unlock(&bfin_otp_lock);
-
- return ret;
- }
-
- case MEMLOCK:
- allow_writes = false;
- return 0;
-
- case MEMUNLOCK:
- allow_writes = true;
- return 0;
- }
-
- return -EINVAL;
-}
-#else
-# define bfin_otp_write NULL
-# define bfin_otp_ioctl NULL
-#endif
-
-static const struct file_operations bfin_otp_fops = {
- .owner = THIS_MODULE,
- .unlocked_ioctl = bfin_otp_ioctl,
- .read = bfin_otp_read,
- .write = bfin_otp_write,
- .llseek = default_llseek,
-};
-
-static struct miscdevice bfin_otp_misc_device = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = DRIVER_NAME,
- .fops = &bfin_otp_fops,
-};
-module_misc_device(bfin_otp_misc_device);
-
-MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
-MODULE_DESCRIPTION("Blackfin OTP Memory Interface");
-MODULE_LICENSE("GPL");
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 24/28] pinctrl: Remove Blackfin pinctrl support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (21 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 23/28] char: Remove Blackfin OTP support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 25/28] staging: Remove Blackfin iio trigger timer support Aaron Wu
` (3 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin pinctrl support
---
drivers/pinctrl/Kconfig | 19 -
drivers/pinctrl/Makefile | 3 -
drivers/pinctrl/pinctrl-adi2-bf54x.c | 588 ------------------
drivers/pinctrl/pinctrl-adi2-bf60x.c | 517 ----------------
drivers/pinctrl/pinctrl-adi2.c | 1114 ----------------------------------
drivers/pinctrl/pinctrl-adi2.h | 75 ---
6 files changed, 2316 deletions(-)
delete mode 100644 drivers/pinctrl/pinctrl-adi2-bf54x.c
delete mode 100644 drivers/pinctrl/pinctrl-adi2-bf60x.c
delete mode 100644 drivers/pinctrl/pinctrl-adi2.c
delete mode 100644 drivers/pinctrl/pinctrl-adi2.h
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 0f254b3..0080735 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -30,17 +30,6 @@ config DEBUG_PINCTRL
help
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
-config PINCTRL_ADI2
- bool "ADI pin controller driver"
- depends on (BF54x || BF60x)
- depends on !GPIO_ADI
- select PINMUX
- select IRQ_DOMAIN
- help
- This is the pin controller and gpio driver for ADI BF54x, BF60x and
- future processors. This option is selected automatically when specific
- machine and arch are selected to build.
-
config PINCTRL_ARTPEC6
bool "Axis ARTPEC-6 pin controller driver"
depends on MACH_ARTPEC6
@@ -77,14 +66,6 @@ config PINCTRL_AXP209
selected.
Say yes to enable pinctrl and GPIO support for the AXP209 PMIC
-config PINCTRL_BF54x
- def_bool y if BF54x
- select PINCTRL_ADI2
-
-config PINCTRL_BF60x
- def_bool y if BF60x
- select PINCTRL_ADI2
-
config PINCTRL_AT91
bool "AT91 pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d369263..92a40bd 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -8,12 +8,9 @@ obj-$(CONFIG_PINMUX) += pinmux.o
obj-$(CONFIG_PINCONF) += pinconf.o
obj-$(CONFIG_OF) += devicetree.o
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
-obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o
obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o
obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o
-obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
-obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
diff --git a/drivers/pinctrl/pinctrl-adi2-bf54x.c b/drivers/pinctrl/pinctrl-adi2-bf54x.c
deleted file mode 100644
index 008a29e..0000000
--- a/drivers/pinctrl/pinctrl-adi2-bf54x.c
+++ /dev/null
@@ -1,588 +0,0 @@
-/*
- * Pinctrl Driver for ADI GPIO2 controller
- *
- * Copyright 2007-2013 Analog Devices Inc.
- *
- * Licensed under the GPLv2 or later
- */
-
-#include <asm/portmux.h>
-#include "pinctrl-adi2.h"
-
-static const struct pinctrl_pin_desc adi_pads[] = {
- PINCTRL_PIN(0, "PA0"),
- PINCTRL_PIN(1, "PA1"),
- PINCTRL_PIN(2, "PA2"),
- PINCTRL_PIN(3, "PG3"),
- PINCTRL_PIN(4, "PA4"),
- PINCTRL_PIN(5, "PA5"),
- PINCTRL_PIN(6, "PA6"),
- PINCTRL_PIN(7, "PA7"),
- PINCTRL_PIN(8, "PA8"),
- PINCTRL_PIN(9, "PA9"),
- PINCTRL_PIN(10, "PA10"),
- PINCTRL_PIN(11, "PA11"),
- PINCTRL_PIN(12, "PA12"),
- PINCTRL_PIN(13, "PA13"),
- PINCTRL_PIN(14, "PA14"),
- PINCTRL_PIN(15, "PA15"),
- PINCTRL_PIN(16, "PB0"),
- PINCTRL_PIN(17, "PB1"),
- PINCTRL_PIN(18, "PB2"),
- PINCTRL_PIN(19, "PB3"),
- PINCTRL_PIN(20, "PB4"),
- PINCTRL_PIN(21, "PB5"),
- PINCTRL_PIN(22, "PB6"),
- PINCTRL_PIN(23, "PB7"),
- PINCTRL_PIN(24, "PB8"),
- PINCTRL_PIN(25, "PB9"),
- PINCTRL_PIN(26, "PB10"),
- PINCTRL_PIN(27, "PB11"),
- PINCTRL_PIN(28, "PB12"),
- PINCTRL_PIN(29, "PB13"),
- PINCTRL_PIN(30, "PB14"),
- PINCTRL_PIN(32, "PC0"),
- PINCTRL_PIN(33, "PC1"),
- PINCTRL_PIN(34, "PC2"),
- PINCTRL_PIN(35, "PC3"),
- PINCTRL_PIN(36, "PC4"),
- PINCTRL_PIN(37, "PC5"),
- PINCTRL_PIN(38, "PC6"),
- PINCTRL_PIN(39, "PC7"),
- PINCTRL_PIN(40, "PC8"),
- PINCTRL_PIN(41, "PC9"),
- PINCTRL_PIN(42, "PC10"),
- PINCTRL_PIN(43, "PC11"),
- PINCTRL_PIN(44, "PC12"),
- PINCTRL_PIN(45, "PC13"),
- PINCTRL_PIN(48, "PD0"),
- PINCTRL_PIN(49, "PD1"),
- PINCTRL_PIN(50, "PD2"),
- PINCTRL_PIN(51, "PD3"),
- PINCTRL_PIN(52, "PD4"),
- PINCTRL_PIN(53, "PD5"),
- PINCTRL_PIN(54, "PD6"),
- PINCTRL_PIN(55, "PD7"),
- PINCTRL_PIN(56, "PD8"),
- PINCTRL_PIN(57, "PD9"),
- PINCTRL_PIN(58, "PD10"),
- PINCTRL_PIN(59, "PD11"),
- PINCTRL_PIN(60, "PD12"),
- PINCTRL_PIN(61, "PD13"),
- PINCTRL_PIN(62, "PD14"),
- PINCTRL_PIN(63, "PD15"),
- PINCTRL_PIN(64, "PE0"),
- PINCTRL_PIN(65, "PE1"),
- PINCTRL_PIN(66, "PE2"),
- PINCTRL_PIN(67, "PE3"),
- PINCTRL_PIN(68, "PE4"),
- PINCTRL_PIN(69, "PE5"),
- PINCTRL_PIN(70, "PE6"),
- PINCTRL_PIN(71, "PE7"),
- PINCTRL_PIN(72, "PE8"),
- PINCTRL_PIN(73, "PE9"),
- PINCTRL_PIN(74, "PE10"),
- PINCTRL_PIN(75, "PE11"),
- PINCTRL_PIN(76, "PE12"),
- PINCTRL_PIN(77, "PE13"),
- PINCTRL_PIN(78, "PE14"),
- PINCTRL_PIN(79, "PE15"),
- PINCTRL_PIN(80, "PF0"),
- PINCTRL_PIN(81, "PF1"),
- PINCTRL_PIN(82, "PF2"),
- PINCTRL_PIN(83, "PF3"),
- PINCTRL_PIN(84, "PF4"),
- PINCTRL_PIN(85, "PF5"),
- PINCTRL_PIN(86, "PF6"),
- PINCTRL_PIN(87, "PF7"),
- PINCTRL_PIN(88, "PF8"),
- PINCTRL_PIN(89, "PF9"),
- PINCTRL_PIN(90, "PF10"),
- PINCTRL_PIN(91, "PF11"),
- PINCTRL_PIN(92, "PF12"),
- PINCTRL_PIN(93, "PF13"),
- PINCTRL_PIN(94, "PF14"),
- PINCTRL_PIN(95, "PF15"),
- PINCTRL_PIN(96, "PG0"),
- PINCTRL_PIN(97, "PG1"),
- PINCTRL_PIN(98, "PG2"),
- PINCTRL_PIN(99, "PG3"),
- PINCTRL_PIN(100, "PG4"),
- PINCTRL_PIN(101, "PG5"),
- PINCTRL_PIN(102, "PG6"),
- PINCTRL_PIN(103, "PG7"),
- PINCTRL_PIN(104, "PG8"),
- PINCTRL_PIN(105, "PG9"),
- PINCTRL_PIN(106, "PG10"),
- PINCTRL_PIN(107, "PG11"),
- PINCTRL_PIN(108, "PG12"),
- PINCTRL_PIN(109, "PG13"),
- PINCTRL_PIN(110, "PG14"),
- PINCTRL_PIN(111, "PG15"),
- PINCTRL_PIN(112, "PH0"),
- PINCTRL_PIN(113, "PH1"),
- PINCTRL_PIN(114, "PH2"),
- PINCTRL_PIN(115, "PH3"),
- PINCTRL_PIN(116, "PH4"),
- PINCTRL_PIN(117, "PH5"),
- PINCTRL_PIN(118, "PH6"),
- PINCTRL_PIN(119, "PH7"),
- PINCTRL_PIN(120, "PH8"),
- PINCTRL_PIN(121, "PH9"),
- PINCTRL_PIN(122, "PH10"),
- PINCTRL_PIN(123, "PH11"),
- PINCTRL_PIN(124, "PH12"),
- PINCTRL_PIN(125, "PH13"),
- PINCTRL_PIN(128, "PI0"),
- PINCTRL_PIN(129, "PI1"),
- PINCTRL_PIN(130, "PI2"),
- PINCTRL_PIN(131, "PI3"),
- PINCTRL_PIN(132, "PI4"),
- PINCTRL_PIN(133, "PI5"),
- PINCTRL_PIN(134, "PI6"),
- PINCTRL_PIN(135, "PI7"),
- PINCTRL_PIN(136, "PI8"),
- PINCTRL_PIN(137, "PI9"),
- PINCTRL_PIN(138, "PI10"),
- PINCTRL_PIN(139, "PI11"),
- PINCTRL_PIN(140, "PI12"),
- PINCTRL_PIN(141, "PI13"),
- PINCTRL_PIN(142, "PI14"),
- PINCTRL_PIN(143, "PI15"),
- PINCTRL_PIN(144, "PJ0"),
- PINCTRL_PIN(145, "PJ1"),
- PINCTRL_PIN(146, "PJ2"),
- PINCTRL_PIN(147, "PJ3"),
- PINCTRL_PIN(148, "PJ4"),
- PINCTRL_PIN(149, "PJ5"),
- PINCTRL_PIN(150, "PJ6"),
- PINCTRL_PIN(151, "PJ7"),
- PINCTRL_PIN(152, "PJ8"),
- PINCTRL_PIN(153, "PJ9"),
- PINCTRL_PIN(154, "PJ10"),
- PINCTRL_PIN(155, "PJ11"),
- PINCTRL_PIN(156, "PJ12"),
- PINCTRL_PIN(157, "PJ13"),
-};
-
-static const unsigned uart0_pins[] = {
- GPIO_PE7, GPIO_PE8,
-};
-
-static const unsigned uart1_pins[] = {
- GPIO_PH0, GPIO_PH1,
-};
-
-static const unsigned uart1_ctsrts_pins[] = {
- GPIO_PE9, GPIO_PE10,
-};
-
-static const unsigned uart2_pins[] = {
- GPIO_PB4, GPIO_PB5,
-};
-
-static const unsigned uart3_pins[] = {
- GPIO_PB6, GPIO_PB7,
-};
-
-static const unsigned uart3_ctsrts_pins[] = {
- GPIO_PB2, GPIO_PB3,
-};
-
-static const unsigned rsi0_pins[] = {
- GPIO_PC8, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12, GPIO_PC13,
-};
-
-static const unsigned spi0_pins[] = {
- GPIO_PE0, GPIO_PE1, GPIO_PE2,
-};
-
-static const unsigned spi1_pins[] = {
- GPIO_PG8, GPIO_PG9, GPIO_PG10,
-};
-
-static const unsigned twi0_pins[] = {
- GPIO_PE14, GPIO_PE15,
-};
-
-static const unsigned twi1_pins[] = {
- GPIO_PB0, GPIO_PB1,
-};
-
-static const unsigned rotary_pins[] = {
- GPIO_PH4, GPIO_PH3, GPIO_PH5,
-};
-
-static const unsigned can0_pins[] = {
- GPIO_PG13, GPIO_PG12,
-};
-
-static const unsigned can1_pins[] = {
- GPIO_PG14, GPIO_PG15,
-};
-
-static const unsigned smc0_pins[] = {
- GPIO_PH8, GPIO_PH9, GPIO_PH10, GPIO_PH11, GPIO_PH12, GPIO_PH13,
- GPIO_PI0, GPIO_PI1, GPIO_PI2, GPIO_PI3, GPIO_PI4, GPIO_PI5, GPIO_PI6,
- GPIO_PI7, GPIO_PI8, GPIO_PI9, GPIO_PI10, GPIO_PI11,
- GPIO_PI12, GPIO_PI13, GPIO_PI14, GPIO_PI15,
-};
-
-static const unsigned sport0_pins[] = {
- GPIO_PC0, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC6, GPIO_PC7,
-};
-
-static const unsigned sport1_pins[] = {
- GPIO_PD0, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD6, GPIO_PD7,
-};
-
-static const unsigned sport2_pins[] = {
- GPIO_PA0, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA6, GPIO_PA7,
-};
-
-static const unsigned sport3_pins[] = {
- GPIO_PA8, GPIO_PA10, GPIO_PA11, GPIO_PA12, GPIO_PA14, GPIO_PA15,
-};
-
-static const unsigned ppi0_8b_pins[] = {
- GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
- GPIO_PF7, GPIO_PF13, GPIO_PG0, GPIO_PG1, GPIO_PG2,
-};
-
-static const unsigned ppi0_16b_pins[] = {
- GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
- GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
- GPIO_PF13, GPIO_PF14, GPIO_PF15,
- GPIO_PG0, GPIO_PG1, GPIO_PG2,
-};
-
-static const unsigned ppi0_24b_pins[] = {
- GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
- GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
- GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PD0, GPIO_PD1, GPIO_PD2,
- GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PG3, GPIO_PG4,
- GPIO_PG0, GPIO_PG1, GPIO_PG2,
-};
-
-static const unsigned ppi1_8b_pins[] = {
- GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6,
- GPIO_PD7, GPIO_PE11, GPIO_PE12, GPIO_PE13,
-};
-
-static const unsigned ppi1_16b_pins[] = {
- GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6,
- GPIO_PD7, GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12,
- GPIO_PD13, GPIO_PD14, GPIO_PD15,
- GPIO_PE11, GPIO_PE12, GPIO_PE13,
-};
-
-static const unsigned ppi2_8b_pins[] = {
- GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12,
- GPIO_PD13, GPIO_PD14, GPIO_PD15,
- GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3,
-};
-
-static const unsigned atapi_pins[] = {
- GPIO_PH2, GPIO_PJ3, GPIO_PJ4, GPIO_PJ5, GPIO_PJ6,
- GPIO_PJ7, GPIO_PJ8, GPIO_PJ9, GPIO_PJ10,
-};
-
-static const unsigned atapi_alter_pins[] = {
- GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
- GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
- GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PG2, GPIO_PG3, GPIO_PG4,
-};
-
-static const unsigned nfc0_pins[] = {
- GPIO_PJ1, GPIO_PJ2,
-};
-
-static const unsigned keys_4x4_pins[] = {
- GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11,
- GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15,
-};
-
-static const unsigned keys_8x8_pins[] = {
- GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11,
- GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15,
- GPIO_PE0, GPIO_PE1, GPIO_PE2, GPIO_PE3,
- GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7,
-};
-
-static const unsigned short uart0_mux[] = {
- P_UART0_TX, P_UART0_RX,
- 0
-};
-
-static const unsigned short uart1_mux[] = {
- P_UART1_TX, P_UART1_RX,
- 0
-};
-
-static const unsigned short uart1_ctsrts_mux[] = {
- P_UART1_RTS, P_UART1_CTS,
- 0
-};
-
-static const unsigned short uart2_mux[] = {
- P_UART2_TX, P_UART2_RX,
- 0
-};
-
-static const unsigned short uart3_mux[] = {
- P_UART3_TX, P_UART3_RX,
- 0
-};
-
-static const unsigned short uart3_ctsrts_mux[] = {
- P_UART3_RTS, P_UART3_CTS,
- 0
-};
-
-static const unsigned short rsi0_mux[] = {
- P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD,
- 0
-};
-
-static const unsigned short spi0_mux[] = {
- P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0
-};
-
-static const unsigned short spi1_mux[] = {
- P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0
-};
-
-static const unsigned short twi0_mux[] = {
- P_TWI0_SCL, P_TWI0_SDA, 0
-};
-
-static const unsigned short twi1_mux[] = {
- P_TWI1_SCL, P_TWI1_SDA, 0
-};
-
-static const unsigned short rotary_mux[] = {
- P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0
-};
-
-static const unsigned short sport0_mux[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static const unsigned short sport1_mux[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static const unsigned short sport2_mux[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, 0
-};
-
-static const unsigned short sport3_mux[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, 0
-};
-
-static const unsigned short can0_mux[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static const unsigned short can1_mux[] = {
- P_CAN1_RX, P_CAN1_TX, 0
-};
-
-static const unsigned short smc0_mux[] = {
- P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
- P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
- P_A22, P_A23, P_A24, P_A25, P_NOR_CLK, 0,
-};
-
-static const unsigned short ppi0_8b_mux[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const unsigned short ppi0_16b_mux[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const unsigned short ppi0_24b_mux[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
- P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
- P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const unsigned short ppi1_8b_mux[] = {
- P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
- P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
- P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
- 0,
-};
-
-static const unsigned short ppi1_16b_mux[] = {
- P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
- P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
- P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11,
- P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15,
- P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
- 0,
-};
-
-static const unsigned short ppi2_8b_mux[] = {
- P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
- P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
- P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
- 0,
-};
-
-static const unsigned short atapi_mux[] = {
- P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0, P_ATAPI_CS1,
- P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ, P_ATAPI_IORDY,
-};
-
-static const unsigned short atapi_alter_mux[] = {
- P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A, P_ATAPI_D3A, P_ATAPI_D4A,
- P_ATAPI_D5A, P_ATAPI_D6A, P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A,
- P_ATAPI_D10A, P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
- P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A,
- 0
-};
-
-static const unsigned short nfc0_mux[] = {
- P_NAND_CE, P_NAND_RB,
- 0
-};
-
-static const unsigned short keys_4x4_mux[] = {
- P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0,
- P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0,
- 0
-};
-
-static const unsigned short keys_8x8_mux[] = {
- P_KEY_ROW7, P_KEY_ROW6, P_KEY_ROW5, P_KEY_ROW4,
- P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0,
- P_KEY_COL7, P_KEY_COL6, P_KEY_COL5, P_KEY_COL4,
- P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0,
- 0
-};
-
-static const struct adi_pin_group adi_pin_groups[] = {
- ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux),
- ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux),
- ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux),
- ADI_PIN_GROUP("uart2grp", uart2_pins, uart2_mux),
- ADI_PIN_GROUP("uart3grp", uart3_pins, uart3_mux),
- ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins, uart3_ctsrts_mux),
- ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux),
- ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux),
- ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux),
- ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux),
- ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux),
- ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux),
- ADI_PIN_GROUP("can0grp", can0_pins, can0_mux),
- ADI_PIN_GROUP("can1grp", can1_pins, can1_mux),
- ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux),
- ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux),
- ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux),
- ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux),
- ADI_PIN_GROUP("sport3grp", sport3_pins, sport3_mux),
- ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux),
- ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux),
- ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux),
- ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux),
- ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux),
- ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux),
- ADI_PIN_GROUP("atapigrp", atapi_pins, atapi_mux),
- ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins, atapi_alter_mux),
- ADI_PIN_GROUP("nfc0grp", nfc0_pins, nfc0_mux),
- ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins, keys_4x4_mux),
- ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins, keys_8x8_mux),
-};
-
-static const char * const uart0grp[] = { "uart0grp" };
-static const char * const uart1grp[] = { "uart1grp" };
-static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" };
-static const char * const uart2grp[] = { "uart2grp" };
-static const char * const uart3grp[] = { "uart3grp" };
-static const char * const uart3ctsrtsgrp[] = { "uart3ctsrtsgrp" };
-static const char * const rsi0grp[] = { "rsi0grp" };
-static const char * const spi0grp[] = { "spi0grp" };
-static const char * const spi1grp[] = { "spi1grp" };
-static const char * const twi0grp[] = { "twi0grp" };
-static const char * const twi1grp[] = { "twi1grp" };
-static const char * const rotarygrp[] = { "rotarygrp" };
-static const char * const can0grp[] = { "can0grp" };
-static const char * const can1grp[] = { "can1grp" };
-static const char * const smc0grp[] = { "smc0grp" };
-static const char * const sport0grp[] = { "sport0grp" };
-static const char * const sport1grp[] = { "sport1grp" };
-static const char * const sport2grp[] = { "sport2grp" };
-static const char * const sport3grp[] = { "sport3grp" };
-static const char * const ppi0grp[] = { "ppi0_8bgrp",
- "ppi0_16bgrp",
- "ppi0_24bgrp" };
-static const char * const ppi1grp[] = { "ppi1_8bgrp",
- "ppi1_16bgrp" };
-static const char * const ppi2grp[] = { "ppi2_8bgrp" };
-static const char * const atapigrp[] = { "atapigrp" };
-static const char * const atapialtergrp[] = { "atapialtergrp" };
-static const char * const nfc0grp[] = { "nfc0grp" };
-static const char * const keysgrp[] = { "keys_4x4grp",
- "keys_8x8grp" };
-
-static const struct adi_pmx_func adi_pmx_functions[] = {
- ADI_PMX_FUNCTION("uart0", uart0grp),
- ADI_PMX_FUNCTION("uart1", uart1grp),
- ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp),
- ADI_PMX_FUNCTION("uart2", uart2grp),
- ADI_PMX_FUNCTION("uart3", uart3grp),
- ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp),
- ADI_PMX_FUNCTION("rsi0", rsi0grp),
- ADI_PMX_FUNCTION("spi0", spi0grp),
- ADI_PMX_FUNCTION("spi1", spi1grp),
- ADI_PMX_FUNCTION("twi0", twi0grp),
- ADI_PMX_FUNCTION("twi1", twi1grp),
- ADI_PMX_FUNCTION("rotary", rotarygrp),
- ADI_PMX_FUNCTION("can0", can0grp),
- ADI_PMX_FUNCTION("can1", can1grp),
- ADI_PMX_FUNCTION("smc0", smc0grp),
- ADI_PMX_FUNCTION("sport0", sport0grp),
- ADI_PMX_FUNCTION("sport1", sport1grp),
- ADI_PMX_FUNCTION("sport2", sport2grp),
- ADI_PMX_FUNCTION("sport3", sport3grp),
- ADI_PMX_FUNCTION("ppi0", ppi0grp),
- ADI_PMX_FUNCTION("ppi1", ppi1grp),
- ADI_PMX_FUNCTION("ppi2", ppi2grp),
- ADI_PMX_FUNCTION("atapi", atapigrp),
- ADI_PMX_FUNCTION("atapi_alter", atapialtergrp),
- ADI_PMX_FUNCTION("nfc0", nfc0grp),
- ADI_PMX_FUNCTION("keys", keysgrp),
-};
-
-static const struct adi_pinctrl_soc_data adi_bf54x_soc = {
- .functions = adi_pmx_functions,
- .nfunctions = ARRAY_SIZE(adi_pmx_functions),
- .groups = adi_pin_groups,
- .ngroups = ARRAY_SIZE(adi_pin_groups),
- .pins = adi_pads,
- .npins = ARRAY_SIZE(adi_pads),
-};
-
-void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc)
-{
- *soc = &adi_bf54x_soc;
-}
diff --git a/drivers/pinctrl/pinctrl-adi2-bf60x.c b/drivers/pinctrl/pinctrl-adi2-bf60x.c
deleted file mode 100644
index fcfa008..0000000
--- a/drivers/pinctrl/pinctrl-adi2-bf60x.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/*
- * Pinctrl Driver for ADI GPIO2 controller
- *
- * Copyright 2007-2013 Analog Devices Inc.
- *
- * Licensed under the GPLv2 or later
- */
-
-#include <asm/portmux.h>
-#include "pinctrl-adi2.h"
-
-static const struct pinctrl_pin_desc adi_pads[] = {
- PINCTRL_PIN(0, "PA0"),
- PINCTRL_PIN(1, "PA1"),
- PINCTRL_PIN(2, "PA2"),
- PINCTRL_PIN(3, "PG3"),
- PINCTRL_PIN(4, "PA4"),
- PINCTRL_PIN(5, "PA5"),
- PINCTRL_PIN(6, "PA6"),
- PINCTRL_PIN(7, "PA7"),
- PINCTRL_PIN(8, "PA8"),
- PINCTRL_PIN(9, "PA9"),
- PINCTRL_PIN(10, "PA10"),
- PINCTRL_PIN(11, "PA11"),
- PINCTRL_PIN(12, "PA12"),
- PINCTRL_PIN(13, "PA13"),
- PINCTRL_PIN(14, "PA14"),
- PINCTRL_PIN(15, "PA15"),
- PINCTRL_PIN(16, "PB0"),
- PINCTRL_PIN(17, "PB1"),
- PINCTRL_PIN(18, "PB2"),
- PINCTRL_PIN(19, "PB3"),
- PINCTRL_PIN(20, "PB4"),
- PINCTRL_PIN(21, "PB5"),
- PINCTRL_PIN(22, "PB6"),
- PINCTRL_PIN(23, "PB7"),
- PINCTRL_PIN(24, "PB8"),
- PINCTRL_PIN(25, "PB9"),
- PINCTRL_PIN(26, "PB10"),
- PINCTRL_PIN(27, "PB11"),
- PINCTRL_PIN(28, "PB12"),
- PINCTRL_PIN(29, "PB13"),
- PINCTRL_PIN(30, "PB14"),
- PINCTRL_PIN(31, "PB15"),
- PINCTRL_PIN(32, "PC0"),
- PINCTRL_PIN(33, "PC1"),
- PINCTRL_PIN(34, "PC2"),
- PINCTRL_PIN(35, "PC3"),
- PINCTRL_PIN(36, "PC4"),
- PINCTRL_PIN(37, "PC5"),
- PINCTRL_PIN(38, "PC6"),
- PINCTRL_PIN(39, "PC7"),
- PINCTRL_PIN(40, "PC8"),
- PINCTRL_PIN(41, "PC9"),
- PINCTRL_PIN(42, "PC10"),
- PINCTRL_PIN(43, "PC11"),
- PINCTRL_PIN(44, "PC12"),
- PINCTRL_PIN(45, "PC13"),
- PINCTRL_PIN(46, "PC14"),
- PINCTRL_PIN(47, "PC15"),
- PINCTRL_PIN(48, "PD0"),
- PINCTRL_PIN(49, "PD1"),
- PINCTRL_PIN(50, "PD2"),
- PINCTRL_PIN(51, "PD3"),
- PINCTRL_PIN(52, "PD4"),
- PINCTRL_PIN(53, "PD5"),
- PINCTRL_PIN(54, "PD6"),
- PINCTRL_PIN(55, "PD7"),
- PINCTRL_PIN(56, "PD8"),
- PINCTRL_PIN(57, "PD9"),
- PINCTRL_PIN(58, "PD10"),
- PINCTRL_PIN(59, "PD11"),
- PINCTRL_PIN(60, "PD12"),
- PINCTRL_PIN(61, "PD13"),
- PINCTRL_PIN(62, "PD14"),
- PINCTRL_PIN(63, "PD15"),
- PINCTRL_PIN(64, "PE0"),
- PINCTRL_PIN(65, "PE1"),
- PINCTRL_PIN(66, "PE2"),
- PINCTRL_PIN(67, "PE3"),
- PINCTRL_PIN(68, "PE4"),
- PINCTRL_PIN(69, "PE5"),
- PINCTRL_PIN(70, "PE6"),
- PINCTRL_PIN(71, "PE7"),
- PINCTRL_PIN(72, "PE8"),
- PINCTRL_PIN(73, "PE9"),
- PINCTRL_PIN(74, "PE10"),
- PINCTRL_PIN(75, "PE11"),
- PINCTRL_PIN(76, "PE12"),
- PINCTRL_PIN(77, "PE13"),
- PINCTRL_PIN(78, "PE14"),
- PINCTRL_PIN(79, "PE15"),
- PINCTRL_PIN(80, "PF0"),
- PINCTRL_PIN(81, "PF1"),
- PINCTRL_PIN(82, "PF2"),
- PINCTRL_PIN(83, "PF3"),
- PINCTRL_PIN(84, "PF4"),
- PINCTRL_PIN(85, "PF5"),
- PINCTRL_PIN(86, "PF6"),
- PINCTRL_PIN(87, "PF7"),
- PINCTRL_PIN(88, "PF8"),
- PINCTRL_PIN(89, "PF9"),
- PINCTRL_PIN(90, "PF10"),
- PINCTRL_PIN(91, "PF11"),
- PINCTRL_PIN(92, "PF12"),
- PINCTRL_PIN(93, "PF13"),
- PINCTRL_PIN(94, "PF14"),
- PINCTRL_PIN(95, "PF15"),
- PINCTRL_PIN(96, "PG0"),
- PINCTRL_PIN(97, "PG1"),
- PINCTRL_PIN(98, "PG2"),
- PINCTRL_PIN(99, "PG3"),
- PINCTRL_PIN(100, "PG4"),
- PINCTRL_PIN(101, "PG5"),
- PINCTRL_PIN(102, "PG6"),
- PINCTRL_PIN(103, "PG7"),
- PINCTRL_PIN(104, "PG8"),
- PINCTRL_PIN(105, "PG9"),
- PINCTRL_PIN(106, "PG10"),
- PINCTRL_PIN(107, "PG11"),
- PINCTRL_PIN(108, "PG12"),
- PINCTRL_PIN(109, "PG13"),
- PINCTRL_PIN(110, "PG14"),
- PINCTRL_PIN(111, "PG15"),
-};
-
-static const unsigned uart0_pins[] = {
- GPIO_PD7, GPIO_PD8,
-};
-
-static const unsigned uart0_ctsrts_pins[] = {
- GPIO_PD9, GPIO_PD10,
-};
-
-static const unsigned uart1_pins[] = {
- GPIO_PG15, GPIO_PG14,
-};
-
-static const unsigned uart1_ctsrts_pins[] = {
- GPIO_PG10, GPIO_PG13,
-};
-
-static const unsigned rsi0_pins[] = {
- GPIO_PG3, GPIO_PG2, GPIO_PG0, GPIO_PE15, GPIO_PG5, GPIO_PG6,
-};
-
-static const unsigned eth0_pins[] = {
- GPIO_PC6, GPIO_PC7, GPIO_PC2, GPIO_PC0, GPIO_PC3, GPIO_PC1,
- GPIO_PB13, GPIO_PD6, GPIO_PC5, GPIO_PC4, GPIO_PB14, GPIO_PB15,
-};
-
-static const unsigned eth1_pins[] = {
- GPIO_PE10, GPIO_PE11, GPIO_PG3, GPIO_PG0, GPIO_PG2, GPIO_PE15,
- GPIO_PG5, GPIO_PE12, GPIO_PE13, GPIO_PE14, GPIO_PG6, GPIO_PC9,
-};
-
-static const unsigned spi0_pins[] = {
- GPIO_PD4, GPIO_PD2, GPIO_PD3,
-};
-
-static const unsigned spi1_pins[] = {
- GPIO_PD5, GPIO_PD14, GPIO_PD13,
-};
-
-static const unsigned twi0_pins[] = {
-};
-
-static const unsigned twi1_pins[] = {
-};
-
-static const unsigned rotary_pins[] = {
- GPIO_PG7, GPIO_PG11, GPIO_PG12,
-};
-
-static const unsigned can0_pins[] = {
- GPIO_PG1, GPIO_PG4,
-};
-
-static const unsigned smc0_pins[] = {
- GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
- GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PB2, GPIO_PA10, GPIO_PA11,
- GPIO_PB3, GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB6,
- GPIO_PB7, GPIO_PB8, GPIO_PB10, GPIO_PB11, GPIO_PB0,
-};
-
-static const unsigned sport0_pins[] = {
- GPIO_PB5, GPIO_PB4, GPIO_PB9, GPIO_PB8, GPIO_PB7, GPIO_PB11,
-};
-
-static const unsigned sport1_pins[] = {
- GPIO_PE2, GPIO_PE5, GPIO_PD15, GPIO_PE4, GPIO_PE3, GPIO_PE1,
-};
-
-static const unsigned sport2_pins[] = {
- GPIO_PG4, GPIO_PG1, GPIO_PG9, GPIO_PG10, GPIO_PG7, GPIO_PB12,
-};
-
-static const unsigned ppi0_8b_pins[] = {
- GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
- GPIO_PF7, GPIO_PF13, GPIO_PF14, GPIO_PF15,
- GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9,
-};
-
-static const unsigned ppi0_16b_pins[] = {
- GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
- GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
- GPIO_PF13, GPIO_PF14, GPIO_PF15,
- GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9,
-};
-
-static const unsigned ppi0_24b_pins[] = {
- GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
- GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
- GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PE0, GPIO_PE1, GPIO_PE2,
- GPIO_PE3, GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, GPIO_PE8,
- GPIO_PE9, GPIO_PD12, GPIO_PD15,
-};
-
-static const unsigned ppi1_8b_pins[] = {
- GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6,
- GPIO_PC7, GPIO_PC8, GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6,
-};
-
-static const unsigned ppi1_16b_pins[] = {
- GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6,
- GPIO_PC7, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12,
- GPIO_PC13, GPIO_PC14, GPIO_PC15,
- GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6,
-};
-
-static const unsigned ppi2_8b_pins[] = {
- GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
- GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3,
-};
-
-static const unsigned ppi2_16b_pins[] = {
- GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
- GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11, GPIO_PA12,
- GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB0, GPIO_PB1, GPIO_PB2,
-};
-
-static const unsigned lp0_pins[] = {
- GPIO_PB0, GPIO_PB1, GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3,
- GPIO_PA4, GPIO_PA5, GPIO_PA6, GPIO_PA7,
-};
-
-static const unsigned lp1_pins[] = {
- GPIO_PB3, GPIO_PB2, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11,
- GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15,
-};
-
-static const unsigned lp2_pins[] = {
- GPIO_PE6, GPIO_PE7, GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3,
- GPIO_PF4, GPIO_PF5, GPIO_PF6, GPIO_PF7,
-};
-
-static const unsigned lp3_pins[] = {
- GPIO_PE9, GPIO_PE8, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
- GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15,
-};
-
-static const unsigned short uart0_mux[] = {
- P_UART0_TX, P_UART0_RX,
- 0
-};
-
-static const unsigned short uart0_ctsrts_mux[] = {
- P_UART0_RTS, P_UART0_CTS,
- 0
-};
-
-static const unsigned short uart1_mux[] = {
- P_UART1_TX, P_UART1_RX,
- 0
-};
-
-static const unsigned short uart1_ctsrts_mux[] = {
- P_UART1_RTS, P_UART1_CTS,
- 0
-};
-
-static const unsigned short rsi0_mux[] = {
- P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3,
- P_RSI_CMD, P_RSI_CLK, 0
-};
-
-static const unsigned short eth0_mux[] = P_RMII0;
-static const unsigned short eth1_mux[] = P_RMII1;
-
-static const unsigned short spi0_mux[] = {
- P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0
-};
-
-static const unsigned short spi1_mux[] = {
- P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0
-};
-
-static const unsigned short twi0_mux[] = {
- P_TWI0_SCL, P_TWI0_SDA, 0
-};
-
-static const unsigned short twi1_mux[] = {
- P_TWI1_SCL, P_TWI1_SDA, 0
-};
-
-static const unsigned short rotary_mux[] = {
- P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0
-};
-
-static const unsigned short sport0_mux[] = {
- P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
- P_SPORT0_BFS, P_SPORT0_BD0, 0,
-};
-
-static const unsigned short sport1_mux[] = {
- P_SPORT1_ACLK, P_SPORT1_AFS, P_SPORT1_AD0, P_SPORT1_BCLK,
- P_SPORT1_BFS, P_SPORT1_BD0, 0,
-};
-
-static const unsigned short sport2_mux[] = {
- P_SPORT2_ACLK, P_SPORT2_AFS, P_SPORT2_AD0, P_SPORT2_BCLK,
- P_SPORT2_BFS, P_SPORT2_BD0, 0,
-};
-
-static const unsigned short can0_mux[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static const unsigned short smc0_mux[] = {
- P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
- P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
- P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
-};
-
-static const unsigned short ppi0_8b_mux[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const unsigned short ppi0_16b_mux[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const unsigned short ppi0_24b_mux[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
- P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
- P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const unsigned short ppi1_8b_mux[] = {
- P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
- P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
- P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
- 0,
-};
-
-static const unsigned short ppi1_16b_mux[] = {
- P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
- P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
- P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11,
- P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15,
- P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
- 0,
-};
-
-static const unsigned short ppi2_8b_mux[] = {
- P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
- P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
- P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
- 0,
-};
-
-static const unsigned short ppi2_16b_mux[] = {
- P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
- P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
- P_PPI2_D8, P_PPI2_D9, P_PPI2_D10, P_PPI2_D11,
- P_PPI2_D12, P_PPI2_D13, P_PPI2_D14, P_PPI2_D15,
- P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
- 0,
-};
-
-static const unsigned short lp0_mux[] = {
- P_LP0_CLK, P_LP0_ACK, P_LP0_D0, P_LP0_D1, P_LP0_D2,
- P_LP0_D3, P_LP0_D4, P_LP0_D5, P_LP0_D6, P_LP0_D7,
- 0
-};
-
-static const unsigned short lp1_mux[] = {
- P_LP1_CLK, P_LP1_ACK, P_LP1_D0, P_LP1_D1, P_LP1_D2,
- P_LP1_D3, P_LP1_D4, P_LP1_D5, P_LP1_D6, P_LP1_D7,
- 0
-};
-
-static const unsigned short lp2_mux[] = {
- P_LP2_CLK, P_LP2_ACK, P_LP2_D0, P_LP2_D1, P_LP2_D2,
- P_LP2_D3, P_LP2_D4, P_LP2_D5, P_LP2_D6, P_LP2_D7,
- 0
-};
-
-static const unsigned short lp3_mux[] = {
- P_LP3_CLK, P_LP3_ACK, P_LP3_D0, P_LP3_D1, P_LP3_D2,
- P_LP3_D3, P_LP3_D4, P_LP3_D5, P_LP3_D6, P_LP3_D7,
- 0
-};
-
-static const struct adi_pin_group adi_pin_groups[] = {
- ADI_PIN_GROUP("uart0grp", uart0_pins, uart0_mux),
- ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins, uart0_ctsrts_mux),
- ADI_PIN_GROUP("uart1grp", uart1_pins, uart1_mux),
- ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins, uart1_ctsrts_mux),
- ADI_PIN_GROUP("rsi0grp", rsi0_pins, rsi0_mux),
- ADI_PIN_GROUP("eth0grp", eth0_pins, eth0_mux),
- ADI_PIN_GROUP("eth1grp", eth1_pins, eth1_mux),
- ADI_PIN_GROUP("spi0grp", spi0_pins, spi0_mux),
- ADI_PIN_GROUP("spi1grp", spi1_pins, spi1_mux),
- ADI_PIN_GROUP("twi0grp", twi0_pins, twi0_mux),
- ADI_PIN_GROUP("twi1grp", twi1_pins, twi1_mux),
- ADI_PIN_GROUP("rotarygrp", rotary_pins, rotary_mux),
- ADI_PIN_GROUP("can0grp", can0_pins, can0_mux),
- ADI_PIN_GROUP("smc0grp", smc0_pins, smc0_mux),
- ADI_PIN_GROUP("sport0grp", sport0_pins, sport0_mux),
- ADI_PIN_GROUP("sport1grp", sport1_pins, sport1_mux),
- ADI_PIN_GROUP("sport2grp", sport2_pins, sport2_mux),
- ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins, ppi0_8b_mux),
- ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins, ppi0_16b_mux),
- ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins, ppi0_24b_mux),
- ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins, ppi1_8b_mux),
- ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins, ppi1_16b_mux),
- ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins, ppi2_8b_mux),
- ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins, ppi2_16b_mux),
- ADI_PIN_GROUP("lp0grp", lp0_pins, lp0_mux),
- ADI_PIN_GROUP("lp1grp", lp1_pins, lp1_mux),
- ADI_PIN_GROUP("lp2grp", lp2_pins, lp2_mux),
- ADI_PIN_GROUP("lp3grp", lp3_pins, lp3_mux),
-};
-
-static const char * const uart0grp[] = { "uart0grp" };
-static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" };
-static const char * const uart1grp[] = { "uart1grp" };
-static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" };
-static const char * const rsi0grp[] = { "rsi0grp" };
-static const char * const eth0grp[] = { "eth0grp" };
-static const char * const eth1grp[] = { "eth1grp" };
-static const char * const spi0grp[] = { "spi0grp" };
-static const char * const spi1grp[] = { "spi1grp" };
-static const char * const twi0grp[] = { "twi0grp" };
-static const char * const twi1grp[] = { "twi1grp" };
-static const char * const rotarygrp[] = { "rotarygrp" };
-static const char * const can0grp[] = { "can0grp" };
-static const char * const smc0grp[] = { "smc0grp" };
-static const char * const sport0grp[] = { "sport0grp" };
-static const char * const sport1grp[] = { "sport1grp" };
-static const char * const sport2grp[] = { "sport2grp" };
-static const char * const ppi0grp[] = { "ppi0_8bgrp",
- "ppi0_16bgrp",
- "ppi0_24bgrp" };
-static const char * const ppi1grp[] = { "ppi1_8bgrp",
- "ppi1_16bgrp" };
-static const char * const ppi2grp[] = { "ppi2_8bgrp",
- "ppi2_16bgrp" };
-static const char * const lp0grp[] = { "lp0grp" };
-static const char * const lp1grp[] = { "lp1grp" };
-static const char * const lp2grp[] = { "lp2grp" };
-static const char * const lp3grp[] = { "lp3grp" };
-
-static const struct adi_pmx_func adi_pmx_functions[] = {
- ADI_PMX_FUNCTION("uart0", uart0grp),
- ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp),
- ADI_PMX_FUNCTION("uart1", uart1grp),
- ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp),
- ADI_PMX_FUNCTION("rsi0", rsi0grp),
- ADI_PMX_FUNCTION("eth0", eth0grp),
- ADI_PMX_FUNCTION("eth1", eth1grp),
- ADI_PMX_FUNCTION("spi0", spi0grp),
- ADI_PMX_FUNCTION("spi1", spi1grp),
- ADI_PMX_FUNCTION("twi0", twi0grp),
- ADI_PMX_FUNCTION("twi1", twi1grp),
- ADI_PMX_FUNCTION("rotary", rotarygrp),
- ADI_PMX_FUNCTION("can0", can0grp),
- ADI_PMX_FUNCTION("smc0", smc0grp),
- ADI_PMX_FUNCTION("sport0", sport0grp),
- ADI_PMX_FUNCTION("sport1", sport1grp),
- ADI_PMX_FUNCTION("sport2", sport2grp),
- ADI_PMX_FUNCTION("ppi0", ppi0grp),
- ADI_PMX_FUNCTION("ppi1", ppi1grp),
- ADI_PMX_FUNCTION("ppi2", ppi2grp),
- ADI_PMX_FUNCTION("lp0", lp0grp),
- ADI_PMX_FUNCTION("lp1", lp1grp),
- ADI_PMX_FUNCTION("lp2", lp2grp),
- ADI_PMX_FUNCTION("lp3", lp3grp),
-};
-
-static const struct adi_pinctrl_soc_data adi_bf60x_soc = {
- .functions = adi_pmx_functions,
- .nfunctions = ARRAY_SIZE(adi_pmx_functions),
- .groups = adi_pin_groups,
- .ngroups = ARRAY_SIZE(adi_pin_groups),
- .pins = adi_pads,
- .npins = ARRAY_SIZE(adi_pads),
-};
-
-void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc)
-{
- *soc = &adi_bf60x_soc;
-}
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c
deleted file mode 100644
index 094a451..0000000
--- a/drivers/pinctrl/pinctrl-adi2.c
+++ /dev/null
@@ -1,1114 +0,0 @@
-/*
- * Pinctrl Driver for ADI GPIO2 controller
- *
- * Copyright 2007-2013 Analog Devices Inc.
- *
- * Licensed under the GPLv2 or later
- */
-
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#include <linux/platform_data/pinctrl-adi2.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/syscore_ops.h>
-#include <linux/gpio.h>
-#include <asm/portmux.h>
-#include "pinctrl-adi2.h"
-#include "core.h"
-
-/*
-According to the BF54x HRM, pint means "pin interrupt".
-http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf
-
-ADSP-BF54x processor Blackfin processors have four SIC interrupt chan-
-nels dedicated to pin interrupt purposes. These channels are managed by
-four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx
-block can sense to up to 32 pins. While PINT0 and PINT1 can sense the
-pins of port A and port B, PINT2 and PINT3 manage all the pins from port
-C to port J as shown in Figure 9-2.
-
-n BF54x HRM:
-The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and
-upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi-
-plexers shown in Figure 9-3. Lower half units of eight pins can be
-forwarded to either byte 0 or byte 2 of either associated PINTx block.
-Upper half units can be forwarded to either byte 1 or byte 3 of the pin
-interrupt blocks, without further restrictions.
-
-All MMR registers in the pin interrupt module are 32 bits wide. To simply the
-mapping logic, this driver only maps a 16-bit gpio port to the upper or lower
-16 bits of a PINTx block. You can find the Figure 9-3 on page 583.
-
-Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map
-to one PINT device. Two in "struct gpio_pint" are used to ease the PINT
-interrupt handler.
-
-The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ
-domain pointer in domain[0]. The IRQ domain pointer of the other bank is set
-to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out
-the current domain pointer according to whether the interrupt request mask
-is in lower 16 bits (domain[0]) or upper 16bits (domain[1]).
-
-A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO
-port devices can be mapped to the same PINT device.
-
-*/
-
-static LIST_HEAD(adi_pint_list);
-static LIST_HEAD(adi_gpio_port_list);
-
-#define DRIVER_NAME "pinctrl-adi2"
-
-#define PINT_HI_OFFSET 16
-
-/**
- * struct gpio_port_saved - GPIO port registers that should be saved between
- * power suspend and resume operations.
- *
- * @fer: PORTx_FER register
- * @data: PORTx_DATA register
- * @dir: PORTx_DIR register
- * @inen: PORTx_INEN register
- * @mux: PORTx_MUX register
- */
-struct gpio_port_saved {
- u16 fer;
- u16 data;
- u16 dir;
- u16 inen;
- u32 mux;
-};
-
-/*
- * struct gpio_pint_saved - PINT registers saved in PM operations
- *
- * @assign: ASSIGN register
- * @edge_set: EDGE_SET register
- * @invert_set: INVERT_SET register
- */
-struct gpio_pint_saved {
- u32 assign;
- u32 edge_set;
- u32 invert_set;
-};
-
-/**
- * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
- * banks can be mapped into one Pin interrupt controller.
- *
- * @node: All gpio_pint instances are added to a global list.
- * @base: PINT device register base address
- * @irq: IRQ of the PINT device, it is the parent IRQ of all
- * GPIO IRQs mapping to this device.
- * @domain: [0] irq domain of the gpio port, whose hardware interrupts are
- * mapping to the low 16-bit of the pint registers.
- * [1] irq domain of the gpio port, whose hardware interrupts are
- * mapping to the high 16-bit of the pint registers.
- * @regs: address pointer to the PINT device
- * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
- * @lock: This lock make sure the irq_chip operations to one PINT device
- * for different GPIO interrrupts are atomic.
- * @pint_map_port: Set up the mapping between one PINT device and
- * multiple GPIO banks.
- */
-struct gpio_pint {
- struct list_head node;
- void __iomem *base;
- int irq;
- struct irq_domain *domain[2];
- struct gpio_pint_regs *regs;
- struct gpio_pint_saved saved_data;
- int map_count;
- spinlock_t lock;
-
- int (*pint_map_port)(struct gpio_pint *pint, bool assign,
- u8 map, struct irq_domain *domain);
-};
-
-/**
- * ADI pin controller
- *
- * @dev: a pointer back to containing device
- * @pctl: the pinctrl device
- * @soc: SoC data for this specific chip
- */
-struct adi_pinctrl {
- struct device *dev;
- struct pinctrl_dev *pctl;
- const struct adi_pinctrl_soc_data *soc;
-};
-
-/**
- * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped
- * into one pin interrupt controller.
- *
- * @node: All gpio_port instances are added to a list.
- * @base: GPIO bank device register base address
- * @irq_base: base IRQ of the GPIO bank device
- * @width: PIN number of the GPIO bank device
- * @regs: address pointer to the GPIO bank device
- * @saved_data: registers that should be saved between PM operations.
- * @dev: device structure of this GPIO bank
- * @pint: GPIO PINT device that this GPIO bank mapped to
- * @pint_map: GIOP bank mapping code in PINT device
- * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A
- * GPIO bank can be mapped into either low 16 bits[0] or high 16
- * bits[1] of each PINT register.
- * @lock: This lock make sure the irq_chip operations to one PINT device
- * for different GPIO interrrupts are atomic.
- * @chip: abstract a GPIO controller
- * @domain: The irq domain owned by the GPIO port.
- * @rsvmap: Reservation map array for each pin in the GPIO bank
- */
-struct gpio_port {
- struct list_head node;
- void __iomem *base;
- int irq_base;
- unsigned int width;
- struct gpio_port_t *regs;
- struct gpio_port_saved saved_data;
- struct device *dev;
-
- struct gpio_pint *pint;
- u8 pint_map;
- bool pint_assign;
-
- spinlock_t lock;
- struct gpio_chip chip;
- struct irq_domain *domain;
-};
-
-static inline u8 pin_to_offset(struct pinctrl_gpio_range *range, unsigned pin)
-{
- return pin - range->pin_base;
-}
-
-static inline u32 hwirq_to_pintbit(struct gpio_port *port, int hwirq)
-{
- return port->pint_assign ? BIT(hwirq) << PINT_HI_OFFSET : BIT(hwirq);
-}
-
-static struct gpio_pint *find_gpio_pint(unsigned id)
-{
- struct gpio_pint *pint;
- int i = 0;
-
- list_for_each_entry(pint, &adi_pint_list, node) {
- if (id == i)
- return pint;
- i++;
- }
-
- return NULL;
-}
-
-static inline void port_setup(struct gpio_port *port, unsigned offset,
- bool use_for_gpio)
-{
- struct gpio_port_t *regs = port->regs;
-
- if (use_for_gpio)
- writew(readw(®s->port_fer) & ~BIT(offset),
- ®s->port_fer);
- else
- writew(readw(®s->port_fer) | BIT(offset), ®s->port_fer);
-}
-
-static inline void portmux_setup(struct gpio_port *port, unsigned offset,
- unsigned short function)
-{
- struct gpio_port_t *regs = port->regs;
- u32 pmux;
-
- pmux = readl(®s->port_mux);
-
- /* The function field of each pin has 2 consecutive bits in
- * the mux register.
- */
- pmux &= ~(0x3 << (2 * offset));
- pmux |= (function & 0x3) << (2 * offset);
-
- writel(pmux, ®s->port_mux);
-}
-
-static inline u16 get_portmux(struct gpio_port *port, unsigned offset)
-{
- struct gpio_port_t *regs = port->regs;
- u32 pmux = readl(®s->port_mux);
-
- /* The function field of each pin has 2 consecutive bits in
- * the mux register.
- */
- return pmux >> (2 * offset) & 0x3;
-}
-
-static void adi_gpio_ack_irq(struct irq_data *d)
-{
- unsigned long flags;
- struct gpio_port *port = irq_data_get_irq_chip_data(d);
- struct gpio_pint_regs *regs = port->pint->regs;
- unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
-
- spin_lock_irqsave(&port->lock, flags);
- spin_lock(&port->pint->lock);
-
- if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
- if (readl(®s->invert_set) & pintbit)
- writel(pintbit, ®s->invert_clear);
- else
- writel(pintbit, ®s->invert_set);
- }
-
- writel(pintbit, ®s->request);
-
- spin_unlock(&port->pint->lock);
- spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static void adi_gpio_mask_ack_irq(struct irq_data *d)
-{
- unsigned long flags;
- struct gpio_port *port = irq_data_get_irq_chip_data(d);
- struct gpio_pint_regs *regs = port->pint->regs;
- unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
-
- spin_lock_irqsave(&port->lock, flags);
- spin_lock(&port->pint->lock);
-
- if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
- if (readl(®s->invert_set) & pintbit)
- writel(pintbit, ®s->invert_clear);
- else
- writel(pintbit, ®s->invert_set);
- }
-
- writel(pintbit, ®s->request);
- writel(pintbit, ®s->mask_clear);
-
- spin_unlock(&port->pint->lock);
- spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static void adi_gpio_mask_irq(struct irq_data *d)
-{
- unsigned long flags;
- struct gpio_port *port = irq_data_get_irq_chip_data(d);
- struct gpio_pint_regs *regs = port->pint->regs;
-
- spin_lock_irqsave(&port->lock, flags);
- spin_lock(&port->pint->lock);
-
- writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear);
-
- spin_unlock(&port->pint->lock);
- spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static void adi_gpio_unmask_irq(struct irq_data *d)
-{
- unsigned long flags;
- struct gpio_port *port = irq_data_get_irq_chip_data(d);
- struct gpio_pint_regs *regs = port->pint->regs;
-
- spin_lock_irqsave(&port->lock, flags);
- spin_lock(&port->pint->lock);
-
- writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set);
-
- spin_unlock(&port->pint->lock);
- spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static unsigned int adi_gpio_irq_startup(struct irq_data *d)
-{
- unsigned long flags;
- struct gpio_port *port = irq_data_get_irq_chip_data(d);
- struct gpio_pint_regs *regs;
-
- if (!port) {
- pr_err("GPIO IRQ %d :Not exist\n", d->irq);
- /* FIXME: negative return code will be ignored */
- return -ENODEV;
- }
-
- regs = port->pint->regs;
-
- spin_lock_irqsave(&port->lock, flags);
- spin_lock(&port->pint->lock);
-
- port_setup(port, d->hwirq, true);
- writew(BIT(d->hwirq), &port->regs->dir_clear);
- writew(readw(&port->regs->inen) | BIT(d->hwirq), &port->regs->inen);
-
- writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set);
-
- spin_unlock(&port->pint->lock);
- spin_unlock_irqrestore(&port->lock, flags);
-
- return 0;
-}
-
-static void adi_gpio_irq_shutdown(struct irq_data *d)
-{
- unsigned long flags;
- struct gpio_port *port = irq_data_get_irq_chip_data(d);
- struct gpio_pint_regs *regs = port->pint->regs;
-
- spin_lock_irqsave(&port->lock, flags);
- spin_lock(&port->pint->lock);
-
- writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear);
-
- spin_unlock(&port->pint->lock);
- spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static int adi_gpio_irq_type(struct irq_data *d, unsigned int type)
-{
- unsigned long flags;
- struct gpio_port *port = irq_data_get_irq_chip_data(d);
- struct gpio_pint_regs *pint_regs;
- unsigned pintmask;
- unsigned int irq = d->irq;
- int ret = 0;
- char buf[16];
-
- if (!port) {
- pr_err("GPIO IRQ %d :Not exist\n", d->irq);
- return -ENODEV;
- }
-
- pint_regs = port->pint->regs;
-
- pintmask = hwirq_to_pintbit(port, d->hwirq);
-
- spin_lock_irqsave(&port->lock, flags);
- spin_lock(&port->pint->lock);
-
- /* In case of interrupt autodetect, set irq type to edge sensitive. */
- if (type == IRQ_TYPE_PROBE)
- type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
- IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
- snprintf(buf, 16, "gpio-irq%u", irq);
- port_setup(port, d->hwirq, true);
- } else
- goto out;
-
- /* The GPIO interrupt is triggered only when its input value
- * transfer from 0 to 1. So, invert the input value if the
- * irq type is low or falling
- */
- if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
- writel(pintmask, &pint_regs->invert_set);
- else
- writel(pintmask, &pint_regs->invert_clear);
-
- /* In edge sensitive case, if the input value of the requested irq
- * is already 1, invert it.
- */
- if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
- if (gpio_get_value(port->chip.base + d->hwirq))
- writel(pintmask, &pint_regs->invert_set);
- else
- writel(pintmask, &pint_regs->invert_clear);
- }
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
- writel(pintmask, &pint_regs->edge_set);
- irq_set_handler_locked(d, handle_edge_irq);
- } else {
- writel(pintmask, &pint_regs->edge_clear);
- irq_set_handler_locked(d, handle_level_irq);
- }
-
-out:
- spin_unlock(&port->pint->lock);
- spin_unlock_irqrestore(&port->lock, flags);
-
- return ret;
-}
-
-#ifdef CONFIG_PM
-static int adi_gpio_set_wake(struct irq_data *d, unsigned int state)
-{
- struct gpio_port *port = irq_data_get_irq_chip_data(d);
-
- if (!port || !port->pint || port->pint->irq != d->irq)
- return -EINVAL;
-
-#ifndef SEC_GCTL
- adi_internal_set_wake(port->pint->irq, state);
-#endif
-
- return 0;
-}
-
-static int adi_pint_suspend(void)
-{
- struct gpio_pint *pint;
-
- list_for_each_entry(pint, &adi_pint_list, node) {
- writel(0xffffffff, &pint->regs->mask_clear);
- pint->saved_data.assign = readl(&pint->regs->assign);
- pint->saved_data.edge_set = readl(&pint->regs->edge_set);
- pint->saved_data.invert_set = readl(&pint->regs->invert_set);
- }
-
- return 0;
-}
-
-static void adi_pint_resume(void)
-{
- struct gpio_pint *pint;
-
- list_for_each_entry(pint, &adi_pint_list, node) {
- writel(pint->saved_data.assign, &pint->regs->assign);
- writel(pint->saved_data.edge_set, &pint->regs->edge_set);
- writel(pint->saved_data.invert_set, &pint->regs->invert_set);
- }
-}
-
-static int adi_gpio_suspend(void)
-{
- struct gpio_port *port;
-
- list_for_each_entry(port, &adi_gpio_port_list, node) {
- port->saved_data.fer = readw(&port->regs->port_fer);
- port->saved_data.mux = readl(&port->regs->port_mux);
- port->saved_data.data = readw(&port->regs->data);
- port->saved_data.inen = readw(&port->regs->inen);
- port->saved_data.dir = readw(&port->regs->dir_set);
- }
-
- return adi_pint_suspend();
-}
-
-static void adi_gpio_resume(void)
-{
- struct gpio_port *port;
-
- adi_pint_resume();
-
- list_for_each_entry(port, &adi_gpio_port_list, node) {
- writel(port->saved_data.mux, &port->regs->port_mux);
- writew(port->saved_data.fer, &port->regs->port_fer);
- writew(port->saved_data.inen, &port->regs->inen);
- writew(port->saved_data.data & port->saved_data.dir,
- &port->regs->data_set);
- writew(port->saved_data.dir, &port->regs->dir_set);
- }
-
-}
-
-static struct syscore_ops gpio_pm_syscore_ops = {
- .suspend = adi_gpio_suspend,
- .resume = adi_gpio_resume,
-};
-#else /* CONFIG_PM */
-#define adi_gpio_set_wake NULL
-#endif /* CONFIG_PM */
-
-#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
-static inline void preflow_handler(struct irq_desc *desc)
-{
- if (desc->preflow_handler)
- desc->preflow_handler(&desc->irq_data);
-}
-#else
-static inline void preflow_handler(struct irq_desc *desc) { }
-#endif
-
-static void adi_gpio_handle_pint_irq(struct irq_desc *desc)
-{
- u32 request;
- u32 level_mask, hwirq;
- bool umask = false;
- struct gpio_pint *pint = irq_desc_get_handler_data(desc);
- struct irq_chip *chip = irq_desc_get_chip(desc);
- struct gpio_pint_regs *regs = pint->regs;
- struct irq_domain *domain;
-
- preflow_handler(desc);
- chained_irq_enter(chip, desc);
-
- request = readl(®s->request);
- level_mask = readl(®s->edge_set) & request;
-
- hwirq = 0;
- domain = pint->domain[0];
- while (request) {
- /* domain pointer need to be changed only once at IRQ 16 when
- * we go through IRQ requests from bit 0 to bit 31.
- */
- if (hwirq == PINT_HI_OFFSET)
- domain = pint->domain[1];
-
- if (request & 1) {
- if (level_mask & BIT(hwirq)) {
- umask = true;
- chained_irq_exit(chip, desc);
- }
- generic_handle_irq(irq_find_mapping(domain,
- hwirq % PINT_HI_OFFSET));
- }
-
- hwirq++;
- request >>= 1;
- }
-
- if (!umask)
- chained_irq_exit(chip, desc);
-}
-
-static struct irq_chip adi_gpio_irqchip = {
- .name = "GPIO",
- .irq_ack = adi_gpio_ack_irq,
- .irq_mask = adi_gpio_mask_irq,
- .irq_mask_ack = adi_gpio_mask_ack_irq,
- .irq_unmask = adi_gpio_unmask_irq,
- .irq_disable = adi_gpio_mask_irq,
- .irq_enable = adi_gpio_unmask_irq,
- .irq_set_type = adi_gpio_irq_type,
- .irq_startup = adi_gpio_irq_startup,
- .irq_shutdown = adi_gpio_irq_shutdown,
- .irq_set_wake = adi_gpio_set_wake,
-};
-
-static int adi_get_groups_count(struct pinctrl_dev *pctldev)
-{
- struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
-
- return pinctrl->soc->ngroups;
-}
-
-static const char *adi_get_group_name(struct pinctrl_dev *pctldev,
- unsigned selector)
-{
- struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
-
- return pinctrl->soc->groups[selector].name;
-}
-
-static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
- const unsigned **pins,
- unsigned *num_pins)
-{
- struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
-
- *pins = pinctrl->soc->groups[selector].pins;
- *num_pins = pinctrl->soc->groups[selector].num;
- return 0;
-}
-
-static const struct pinctrl_ops adi_pctrl_ops = {
- .get_groups_count = adi_get_groups_count,
- .get_group_name = adi_get_group_name,
- .get_group_pins = adi_get_group_pins,
-};
-
-static int adi_pinmux_set(struct pinctrl_dev *pctldev, unsigned func_id,
- unsigned group_id)
-{
- struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
- struct gpio_port *port;
- struct pinctrl_gpio_range *range;
- unsigned long flags;
- unsigned short *mux, pin;
-
- mux = (unsigned short *)pinctrl->soc->groups[group_id].mux;
-
- while (*mux) {
- pin = P_IDENT(*mux);
-
- range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
- if (range == NULL) /* should not happen */
- return -ENODEV;
-
- port = gpiochip_get_data(range->gc);
-
- spin_lock_irqsave(&port->lock, flags);
-
- portmux_setup(port, pin_to_offset(range, pin),
- P_FUNCT2MUX(*mux));
- port_setup(port, pin_to_offset(range, pin), false);
- mux++;
-
- spin_unlock_irqrestore(&port->lock, flags);
- }
-
- return 0;
-}
-
-static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
-
- return pinctrl->soc->nfunctions;
-}
-
-static const char *adi_pinmux_get_func_name(struct pinctrl_dev *pctldev,
- unsigned selector)
-{
- struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
-
- return pinctrl->soc->functions[selector].name;
-}
-
-static int adi_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
- const char * const **groups,
- unsigned * const num_groups)
-{
- struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
-
- *groups = pinctrl->soc->functions[selector].groups;
- *num_groups = pinctrl->soc->functions[selector].num_groups;
- return 0;
-}
-
-static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range, unsigned pin)
-{
- struct gpio_port *port;
- unsigned long flags;
- u8 offset;
-
- port = gpiochip_get_data(range->gc);
- offset = pin_to_offset(range, pin);
-
- spin_lock_irqsave(&port->lock, flags);
-
- port_setup(port, offset, true);
-
- spin_unlock_irqrestore(&port->lock, flags);
-
- return 0;
-}
-
-static const struct pinmux_ops adi_pinmux_ops = {
- .set_mux = adi_pinmux_set,
- .get_functions_count = adi_pinmux_get_funcs_count,
- .get_function_name = adi_pinmux_get_func_name,
- .get_function_groups = adi_pinmux_get_groups,
- .gpio_request_enable = adi_pinmux_request_gpio,
- .strict = true,
-};
-
-
-static struct pinctrl_desc adi_pinmux_desc = {
- .name = DRIVER_NAME,
- .pctlops = &adi_pctrl_ops,
- .pmxops = &adi_pinmux_ops,
- .owner = THIS_MODULE,
-};
-
-static int adi_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
- struct gpio_port *port;
- unsigned long flags;
-
- port = gpiochip_get_data(chip);
-
- spin_lock_irqsave(&port->lock, flags);
-
- writew(BIT(offset), &port->regs->dir_clear);
- writew(readw(&port->regs->inen) | BIT(offset), &port->regs->inen);
-
- spin_unlock_irqrestore(&port->lock, flags);
-
- return 0;
-}
-
-static void adi_gpio_set_value(struct gpio_chip *chip, unsigned offset,
- int value)
-{
- struct gpio_port *port = gpiochip_get_data(chip);
- struct gpio_port_t *regs = port->regs;
- unsigned long flags;
-
- spin_lock_irqsave(&port->lock, flags);
-
- if (value)
- writew(BIT(offset), ®s->data_set);
- else
- writew(BIT(offset), ®s->data_clear);
-
- spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static int adi_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
- int value)
-{
- struct gpio_port *port = gpiochip_get_data(chip);
- struct gpio_port_t *regs = port->regs;
- unsigned long flags;
-
- spin_lock_irqsave(&port->lock, flags);
-
- writew(readw(®s->inen) & ~BIT(offset), ®s->inen);
- if (value)
- writew(BIT(offset), ®s->data_set);
- else
- writew(BIT(offset), ®s->data_clear);
- writew(BIT(offset), ®s->dir_set);
-
- spin_unlock_irqrestore(&port->lock, flags);
-
- return 0;
-}
-
-static int adi_gpio_get_value(struct gpio_chip *chip, unsigned offset)
-{
- struct gpio_port *port = gpiochip_get_data(chip);
- struct gpio_port_t *regs = port->regs;
- unsigned long flags;
- int ret;
-
- spin_lock_irqsave(&port->lock, flags);
-
- ret = !!(readw(®s->data) & BIT(offset));
-
- spin_unlock_irqrestore(&port->lock, flags);
-
- return ret;
-}
-
-static int adi_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
- struct gpio_port *port = gpiochip_get_data(chip);
-
- if (port->irq_base >= 0)
- return irq_find_mapping(port->domain, offset);
- else
- return irq_create_mapping(port->domain, offset);
-}
-
-static int adi_pint_map_port(struct gpio_pint *pint, bool assign, u8 map,
- struct irq_domain *domain)
-{
- struct gpio_pint_regs *regs = pint->regs;
- u32 map_mask;
-
- if (pint->map_count > 1)
- return -EINVAL;
-
- pint->map_count++;
-
- /* The map_mask of each gpio port is a 16-bit duplicate
- * of the 8-bit map. It can be set to either high 16 bits or low
- * 16 bits of the pint assignment register.
- */
- map_mask = (map << 8) | map;
- if (assign) {
- map_mask <<= PINT_HI_OFFSET;
- writel((readl(®s->assign) & 0xFFFF) | map_mask,
- ®s->assign);
- } else
- writel((readl(®s->assign) & 0xFFFF0000) | map_mask,
- ®s->assign);
-
- pint->domain[assign] = domain;
-
- return 0;
-}
-
-static int adi_gpio_pint_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct resource *res;
- struct gpio_pint *pint = devm_kzalloc(dev, sizeof(*pint), GFP_KERNEL);
-
- if (!pint)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- pint->base = devm_ioremap_resource(dev, res);
- if (IS_ERR(pint->base))
- return PTR_ERR(pint->base);
-
- pint->regs = (struct gpio_pint_regs *)pint->base;
-
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res) {
- dev_err(dev, "Invalid IRQ resource\n");
- return -ENODEV;
- }
-
- spin_lock_init(&pint->lock);
-
- pint->irq = res->start;
- pint->pint_map_port = adi_pint_map_port;
- platform_set_drvdata(pdev, pint);
-
- irq_set_chained_handler_and_data(pint->irq, adi_gpio_handle_pint_irq,
- pint);
-
- list_add_tail(&pint->node, &adi_pint_list);
-
- return 0;
-}
-
-static int adi_gpio_pint_remove(struct platform_device *pdev)
-{
- struct gpio_pint *pint = platform_get_drvdata(pdev);
-
- list_del(&pint->node);
- irq_set_handler(pint->irq, handle_simple_irq);
-
- return 0;
-}
-
-static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hwirq)
-{
- struct gpio_port *port = d->host_data;
-
- if (!port)
- return -EINVAL;
-
- irq_set_chip_data(irq, port);
- irq_set_chip_and_handler(irq, &adi_gpio_irqchip,
- handle_level_irq);
-
- return 0;
-}
-
-static const struct irq_domain_ops adi_gpio_irq_domain_ops = {
- .map = adi_gpio_irq_map,
- .xlate = irq_domain_xlate_onecell,
-};
-
-static int adi_gpio_init_int(struct gpio_port *port)
-{
- struct device_node *node = port->dev->of_node;
- struct gpio_pint *pint = port->pint;
- int ret;
-
- port->domain = irq_domain_add_linear(node, port->width,
- &adi_gpio_irq_domain_ops, port);
- if (!port->domain) {
- dev_err(port->dev, "Failed to create irqdomain\n");
- return -ENOSYS;
- }
-
- /* According to BF54x and BF60x HRM, pin interrupt devices are not
- * part of the GPIO port device. in GPIO interrupt mode, the GPIO
- * pins of multiple port devices can be routed into one pin interrupt
- * device. The mapping can be configured by setting pint assignment
- * register with the mapping value of different GPIO port. This is
- * done via function pint_map_port().
- */
- ret = pint->pint_map_port(port->pint, port->pint_assign,
- port->pint_map, port->domain);
- if (ret)
- return ret;
-
- if (port->irq_base >= 0) {
- ret = irq_create_strict_mappings(port->domain, port->irq_base,
- 0, port->width);
- if (ret) {
- dev_err(port->dev, "Couldn't associate to domain\n");
- return ret;
- }
- }
-
- return 0;
-}
-
-#define DEVNAME_SIZE 16
-
-static int adi_gpio_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- const struct adi_pinctrl_gpio_platform_data *pdata;
- struct resource *res;
- struct gpio_port *port;
- char pinctrl_devname[DEVNAME_SIZE];
- static int gpio;
- int ret = 0;
-
- pdata = dev->platform_data;
- if (!pdata)
- return -EINVAL;
-
- port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
- if (!port)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- port->base = devm_ioremap_resource(dev, res);
- if (IS_ERR(port->base))
- return PTR_ERR(port->base);
-
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res)
- port->irq_base = -1;
- else
- port->irq_base = res->start;
-
- port->width = pdata->port_width;
- port->dev = dev;
- port->regs = (struct gpio_port_t *)port->base;
- port->pint_assign = pdata->pint_assign;
- port->pint_map = pdata->pint_map;
-
- port->pint = find_gpio_pint(pdata->pint_id);
- if (port->pint) {
- ret = adi_gpio_init_int(port);
- if (ret)
- return ret;
- }
-
- spin_lock_init(&port->lock);
-
- platform_set_drvdata(pdev, port);
-
- port->chip.label = "adi-gpio";
- port->chip.direction_input = adi_gpio_direction_input;
- port->chip.get = adi_gpio_get_value;
- port->chip.direction_output = adi_gpio_direction_output;
- port->chip.set = adi_gpio_set_value;
- port->chip.request = gpiochip_generic_request,
- port->chip.free = gpiochip_generic_free,
- port->chip.to_irq = adi_gpio_to_irq;
- if (pdata->port_gpio_base > 0)
- port->chip.base = pdata->port_gpio_base;
- else
- port->chip.base = gpio;
- port->chip.ngpio = port->width;
- gpio = port->chip.base + port->width;
-
- ret = gpiochip_add_data(&port->chip, port);
- if (ret) {
- dev_err(&pdev->dev, "Fail to add GPIO chip.\n");
- goto out_remove_domain;
- }
-
- /* Add gpio pin range */
- snprintf(pinctrl_devname, DEVNAME_SIZE, "pinctrl-adi2.%d",
- pdata->pinctrl_id);
- pinctrl_devname[DEVNAME_SIZE - 1] = 0;
- ret = gpiochip_add_pin_range(&port->chip, pinctrl_devname,
- 0, pdata->port_pin_base, port->width);
- if (ret) {
- dev_err(&pdev->dev, "Fail to add pin range to %s.\n",
- pinctrl_devname);
- goto out_remove_gpiochip;
- }
-
- list_add_tail(&port->node, &adi_gpio_port_list);
-
- return 0;
-
-out_remove_gpiochip:
- gpiochip_remove(&port->chip);
-out_remove_domain:
- if (port->pint)
- irq_domain_remove(port->domain);
-
- return ret;
-}
-
-static int adi_gpio_remove(struct platform_device *pdev)
-{
- struct gpio_port *port = platform_get_drvdata(pdev);
- u8 offset;
-
- list_del(&port->node);
- gpiochip_remove(&port->chip);
- if (port->pint) {
- for (offset = 0; offset < port->width; offset++)
- irq_dispose_mapping(irq_find_mapping(port->domain,
- offset));
- irq_domain_remove(port->domain);
- }
-
- return 0;
-}
-
-static int adi_pinctrl_probe(struct platform_device *pdev)
-{
- struct adi_pinctrl *pinctrl;
-
- pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
- if (!pinctrl)
- return -ENOMEM;
-
- pinctrl->dev = &pdev->dev;
-
- adi_pinctrl_soc_init(&pinctrl->soc);
-
- adi_pinmux_desc.pins = pinctrl->soc->pins;
- adi_pinmux_desc.npins = pinctrl->soc->npins;
-
- /* Now register the pin controller and all pins it handles */
- pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &adi_pinmux_desc,
- pinctrl);
- if (IS_ERR(pinctrl->pctl)) {
- dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n");
- return PTR_ERR(pinctrl->pctl);
- }
-
- platform_set_drvdata(pdev, pinctrl);
-
- return 0;
-}
-
-static struct platform_driver adi_pinctrl_driver = {
- .probe = adi_pinctrl_probe,
- .driver = {
- .name = DRIVER_NAME,
- },
-};
-
-static struct platform_driver adi_gpio_pint_driver = {
- .probe = adi_gpio_pint_probe,
- .remove = adi_gpio_pint_remove,
- .driver = {
- .name = "adi-gpio-pint",
- },
-};
-
-static struct platform_driver adi_gpio_driver = {
- .probe = adi_gpio_probe,
- .remove = adi_gpio_remove,
- .driver = {
- .name = "adi-gpio",
- },
-};
-
-static struct platform_driver * const drivers[] = {
- &adi_pinctrl_driver,
- &adi_gpio_pint_driver,
- &adi_gpio_driver,
-};
-
-static int __init adi_pinctrl_setup(void)
-{
- int ret;
-
- ret = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
- if (ret)
- return ret;
-
-#ifdef CONFIG_PM
- register_syscore_ops(&gpio_pm_syscore_ops);
-#endif
- return 0;
-}
-arch_initcall(adi_pinctrl_setup);
-
-MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
-MODULE_DESCRIPTION("ADI gpio2 pin control driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-adi2.h b/drivers/pinctrl/pinctrl-adi2.h
deleted file mode 100644
index 3ca2973..0000000
--- a/drivers/pinctrl/pinctrl-adi2.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Pinctrl Driver for ADI GPIO2 controller
- *
- * Copyright 2007-2013 Analog Devices Inc.
- *
- * Licensed under the GPLv2 or later
- */
-
-#ifndef PINCTRL_PINCTRL_ADI2_H
-#define PINCTRL_PINCTRL_ADI2_H
-
-#include <linux/pinctrl/pinctrl.h>
-
- /**
- * struct adi_pin_group - describes a pin group
- * @name: the name of this pin group
- * @pins: an array of pins
- * @num: the number of pins in this array
- */
-struct adi_pin_group {
- const char *name;
- const unsigned *pins;
- const unsigned num;
- const unsigned short *mux;
-};
-
-#define ADI_PIN_GROUP(n, p, m) \
- { \
- .name = n, \
- .pins = p, \
- .num = ARRAY_SIZE(p), \
- .mux = m, \
- }
-
- /**
- * struct adi_pmx_func - describes function mux setting of pin groups
- * @name: the name of this function mux setting
- * @groups: an array of pin groups
- * @num_groups: the number of pin groups in this array
- * @mux: the function mux setting array, end by zero
- */
-struct adi_pmx_func {
- const char *name;
- const char * const *groups;
- const unsigned num_groups;
-};
-
-#define ADI_PMX_FUNCTION(n, g) \
- { \
- .name = n, \
- .groups = g, \
- .num_groups = ARRAY_SIZE(g), \
- }
-
-/**
- * struct adi_pinctrl_soc_data - ADI pin controller per-SoC configuration
- * @functions: The functions supported on this SoC.
- * @nfunction: The number of entries in @functions.
- * @groups: An array describing all pin groups the pin SoC supports.
- * @ngroups: The number of entries in @groups.
- * @pins: An array describing all pins the pin controller affects.
- * @npins: The number of entries in @pins.
- */
-struct adi_pinctrl_soc_data {
- const struct adi_pmx_func *functions;
- int nfunctions;
- const struct adi_pin_group *groups;
- int ngroups;
- const struct pinctrl_pin_desc *pins;
- int npins;
-};
-
-void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc);
-
-#endif /* PINCTRL_PINCTRL_ADI2_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 25/28] staging: Remove Blackfin iio trigger timer support
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (22 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 24/28] pinctrl: Remove Blackfin pinctrl support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 26/28] samples: Remove Blackfin gptimers sample code Aaron Wu
` (2 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin iio trigger timer support
---
drivers/staging/iio/Kconfig | 1 -
drivers/staging/iio/Makefile | 1 -
drivers/staging/iio/trigger/Kconfig | 19 --
drivers/staging/iio/trigger/Makefile | 5 -
drivers/staging/iio/trigger/iio-trig-bfin-timer.c | 292 ----------------------
drivers/staging/iio/trigger/iio-trig-bfin-timer.h | 25 --
6 files changed, 343 deletions(-)
delete mode 100644 drivers/staging/iio/trigger/Kconfig
delete mode 100644 drivers/staging/iio/trigger/Makefile
delete mode 100644 drivers/staging/iio/trigger/iio-trig-bfin-timer.c
delete mode 100644 drivers/staging/iio/trigger/iio-trig-bfin-timer.h
diff --git a/drivers/staging/iio/Kconfig b/drivers/staging/iio/Kconfig
index 8abc1ab..bd94459 100644
--- a/drivers/staging/iio/Kconfig
+++ b/drivers/staging/iio/Kconfig
@@ -14,6 +14,5 @@ source "drivers/staging/iio/impedance-analyzer/Kconfig"
source "drivers/staging/iio/light/Kconfig"
source "drivers/staging/iio/meter/Kconfig"
source "drivers/staging/iio/resolver/Kconfig"
-source "drivers/staging/iio/trigger/Kconfig"
endmenu
diff --git a/drivers/staging/iio/Makefile b/drivers/staging/iio/Makefile
index 455bffc..e99a375 100644
--- a/drivers/staging/iio/Makefile
+++ b/drivers/staging/iio/Makefile
@@ -13,4 +13,3 @@ obj-y += impedance-analyzer/
obj-y += light/
obj-y += meter/
obj-y += resolver/
-obj-y += trigger/
diff --git a/drivers/staging/iio/trigger/Kconfig b/drivers/staging/iio/trigger/Kconfig
deleted file mode 100644
index 0b01d24..0000000
--- a/drivers/staging/iio/trigger/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
- #
-# Industrial I/O standalone triggers
-#
-comment "Triggers - standalone"
-
-if IIO_TRIGGER
-
-config IIO_BFIN_TMR_TRIGGER
- tristate "Blackfin TIMER trigger"
- depends on BLACKFIN
- select BFIN_GPTIMERS
- help
- Provides support for using a Blackfin timer as IIO triggers.
- If unsure, say N (but it's safe to say "Y").
-
- To compile this driver as a module, choose M here: the
- module will be called iio-trig-bfin-timer.
-
-endif # IIO_TRIGGER
diff --git a/drivers/staging/iio/trigger/Makefile b/drivers/staging/iio/trigger/Makefile
deleted file mode 100644
index 1300a21..0000000
--- a/drivers/staging/iio/trigger/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for triggers not associated with iio-devices
-#
-
-obj-$(CONFIG_IIO_BFIN_TMR_TRIGGER) += iio-trig-bfin-timer.o
diff --git a/drivers/staging/iio/trigger/iio-trig-bfin-timer.c b/drivers/staging/iio/trigger/iio-trig-bfin-timer.c
deleted file mode 100644
index 71f11d7..0000000
--- a/drivers/staging/iio/trigger/iio-trig-bfin-timer.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-
-#include <asm/gptimers.h>
-#include <asm/portmux.h>
-
-#include <linux/iio/iio.h>
-#include <linux/iio/trigger.h>
-
-#include "iio-trig-bfin-timer.h"
-
-struct bfin_timer {
- unsigned short id, bit;
- unsigned long irqbit;
- int irq;
- int pin;
-};
-
-/*
- * this covers all hardware timer configurations on
- * all Blackfin derivatives out there today
- */
-
-static struct bfin_timer iio_bfin_timer_code[MAX_BLACKFIN_GPTIMERS] = {
- {TIMER0_id, TIMER0bit, TIMER_STATUS_TIMIL0, IRQ_TIMER0, P_TMR0},
- {TIMER1_id, TIMER1bit, TIMER_STATUS_TIMIL1, IRQ_TIMER1, P_TMR1},
- {TIMER2_id, TIMER2bit, TIMER_STATUS_TIMIL2, IRQ_TIMER2, P_TMR2},
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- {TIMER3_id, TIMER3bit, TIMER_STATUS_TIMIL3, IRQ_TIMER3, P_TMR3},
- {TIMER4_id, TIMER4bit, TIMER_STATUS_TIMIL4, IRQ_TIMER4, P_TMR4},
- {TIMER5_id, TIMER5bit, TIMER_STATUS_TIMIL5, IRQ_TIMER5, P_TMR5},
- {TIMER6_id, TIMER6bit, TIMER_STATUS_TIMIL6, IRQ_TIMER6, P_TMR6},
- {TIMER7_id, TIMER7bit, TIMER_STATUS_TIMIL7, IRQ_TIMER7, P_TMR7},
-#endif
-#if (MAX_BLACKFIN_GPTIMERS > 8)
- {TIMER8_id, TIMER8bit, TIMER_STATUS_TIMIL8, IRQ_TIMER8, P_TMR8},
- {TIMER9_id, TIMER9bit, TIMER_STATUS_TIMIL9, IRQ_TIMER9, P_TMR9},
- {TIMER10_id, TIMER10bit, TIMER_STATUS_TIMIL10, IRQ_TIMER10, P_TMR10},
-#if (MAX_BLACKFIN_GPTIMERS > 11)
- {TIMER11_id, TIMER11bit, TIMER_STATUS_TIMIL11, IRQ_TIMER11, P_TMR11},
-#endif
-#endif
-};
-
-struct bfin_tmr_state {
- struct iio_trigger *trig;
- struct bfin_timer *t;
- unsigned int timer_num;
- bool output_enable;
- unsigned int duty;
- int irq;
-};
-
-static int iio_bfin_tmr_set_state(struct iio_trigger *trig, bool state)
-{
- struct bfin_tmr_state *st = iio_trigger_get_drvdata(trig);
-
- if (get_gptimer_period(st->t->id) == 0)
- return -EINVAL;
-
- if (state)
- enable_gptimers(st->t->bit);
- else
- disable_gptimers(st->t->bit);
-
- return 0;
-}
-
-static ssize_t frequency_store(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- struct iio_trigger *trig = to_iio_trigger(dev);
- struct bfin_tmr_state *st = iio_trigger_get_drvdata(trig);
- unsigned int val;
- bool enabled;
- int ret;
-
- ret = kstrtouint(buf, 10, &val);
- if (ret)
- return ret;
-
- if (val > 100000)
- return -EINVAL;
-
- enabled = get_enabled_gptimers() & st->t->bit;
-
- if (enabled)
- disable_gptimers(st->t->bit);
-
- if (!val)
- return count;
-
- val = get_sclk() / val;
- if (val <= 4 || val <= st->duty)
- return -EINVAL;
-
- set_gptimer_period(st->t->id, val);
- set_gptimer_pwidth(st->t->id, val - st->duty);
-
- if (enabled)
- enable_gptimers(st->t->bit);
-
- return count;
-}
-
-static ssize_t frequency_show(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_trigger *trig = to_iio_trigger(dev);
- struct bfin_tmr_state *st = iio_trigger_get_drvdata(trig);
- unsigned int period = get_gptimer_period(st->t->id);
- unsigned long val;
-
- if (!period)
- val = 0;
- else
- val = get_sclk() / get_gptimer_period(st->t->id);
-
- return sprintf(buf, "%lu\n", val);
-}
-
-static DEVICE_ATTR_RW(frequency);
-
-static struct attribute *iio_bfin_tmr_trigger_attrs[] = {
- &dev_attr_frequency.attr,
- NULL,
-};
-
-static const struct attribute_group iio_bfin_tmr_trigger_attr_group = {
- .attrs = iio_bfin_tmr_trigger_attrs,
-};
-
-static const struct attribute_group *iio_bfin_tmr_trigger_attr_groups[] = {
- &iio_bfin_tmr_trigger_attr_group,
- NULL
-};
-
-static irqreturn_t iio_bfin_tmr_trigger_isr(int irq, void *devid)
-{
- struct bfin_tmr_state *st = devid;
-
- clear_gptimer_intr(st->t->id);
- iio_trigger_poll(st->trig);
-
- return IRQ_HANDLED;
-}
-
-static int iio_bfin_tmr_get_number(int irq)
-{
- int i;
-
- for (i = 0; i < MAX_BLACKFIN_GPTIMERS; i++)
- if (iio_bfin_timer_code[i].irq == irq)
- return i;
-
- return -ENODEV;
-}
-
-static const struct iio_trigger_ops iio_bfin_tmr_trigger_ops = {
- .set_trigger_state = iio_bfin_tmr_set_state,
-};
-
-static int iio_bfin_tmr_trigger_probe(struct platform_device *pdev)
-{
- struct iio_bfin_timer_trigger_pdata *pdata;
- struct bfin_tmr_state *st;
- unsigned int config;
- int ret;
-
- st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL);
- if (!st)
- return -ENOMEM;
-
- st->irq = platform_get_irq(pdev, 0);
- if (st->irq < 0) {
- dev_err(&pdev->dev, "No IRQs specified");
- return st->irq;
- }
-
- ret = iio_bfin_tmr_get_number(st->irq);
- if (ret < 0)
- return ret;
-
- st->timer_num = ret;
- st->t = &iio_bfin_timer_code[st->timer_num];
-
- st->trig = iio_trigger_alloc("bfintmr%d", st->timer_num);
- if (!st->trig)
- return -ENOMEM;
-
- st->trig->ops = &iio_bfin_tmr_trigger_ops;
- st->trig->dev.groups = iio_bfin_tmr_trigger_attr_groups;
- iio_trigger_set_drvdata(st->trig, st);
- ret = iio_trigger_register(st->trig);
- if (ret)
- goto out;
-
- ret = request_irq(st->irq, iio_bfin_tmr_trigger_isr,
- 0, st->trig->name, st);
- if (ret) {
- dev_err(&pdev->dev,
- "request IRQ-%d failed", st->irq);
- goto out1;
- }
-
- config = PWM_OUT | PERIOD_CNT | IRQ_ENA;
-
- pdata = dev_get_platdata(&pdev->dev);
- if (pdata && pdata->output_enable) {
- unsigned long long val;
-
- st->output_enable = true;
-
- ret = peripheral_request(st->t->pin, st->trig->name);
- if (ret)
- goto out_free_irq;
-
- val = (unsigned long long)get_sclk() * pdata->duty_ns;
- do_div(val, NSEC_PER_SEC);
- st->duty = val;
-
- /**
- * The interrupt will be generated at the end of the period,
- * since we want the interrupt to be generated at end of the
- * pulse we invert both polarity and duty cycle, so that the
- * pulse will be generated directly before the interrupt.
- */
- if (pdata->active_low)
- config |= PULSE_HI;
- } else {
- st->duty = 1;
- config |= OUT_DIS;
- }
-
- set_gptimer_config(st->t->id, config);
-
- dev_info(&pdev->dev, "iio trigger Blackfin TMR%d, IRQ-%d",
- st->timer_num, st->irq);
- platform_set_drvdata(pdev, st);
-
- return 0;
-out_free_irq:
- free_irq(st->irq, st);
-out1:
- iio_trigger_unregister(st->trig);
-out:
- iio_trigger_free(st->trig);
- return ret;
-}
-
-static int iio_bfin_tmr_trigger_remove(struct platform_device *pdev)
-{
- struct bfin_tmr_state *st = platform_get_drvdata(pdev);
-
- disable_gptimers(st->t->bit);
- if (st->output_enable)
- peripheral_free(st->t->pin);
- free_irq(st->irq, st);
- iio_trigger_unregister(st->trig);
- iio_trigger_free(st->trig);
-
- return 0;
-}
-
-static struct platform_driver iio_bfin_tmr_trigger_driver = {
- .driver = {
- .name = "iio_bfin_tmr_trigger",
- },
- .probe = iio_bfin_tmr_trigger_probe,
- .remove = iio_bfin_tmr_trigger_remove,
-};
-
-module_platform_driver(iio_bfin_tmr_trigger_driver);
-
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("Blackfin system timer based trigger for the iio subsystem");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:iio-trig-bfin-timer");
diff --git a/drivers/staging/iio/trigger/iio-trig-bfin-timer.h b/drivers/staging/iio/trigger/iio-trig-bfin-timer.h
deleted file mode 100644
index fb05a2a..0000000
--- a/drivers/staging/iio/trigger/iio-trig-bfin-timer.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __IIO_BFIN_TIMER_TRIGGER_H__
-#define __IIO_BFIN_TIMER_TRIGGER_H__
-
-/**
- * struct iio_bfin_timer_trigger_pdata - timer trigger platform data
- * @output_enable: Enable external trigger pulse generation.
- * @active_low: Whether the trigger pulse is active low.
- * @duty_ns: Length of the trigger pulse in nanoseconds.
- *
- * This struct is used to configure the output pulse generation of the blackfin
- * timer trigger. If output_enable is set to true an external trigger signal
- * will generated on the pin corresponding to the timer. This is useful for
- * converters which needs an external signal to start conversion. active_low and
- * duty_ns are used to configure the type of the trigger pulse. If output_enable
- * is set to false no external trigger pulse will be generated and active_low
- * and duty_ns are ignored.
- **/
-struct iio_bfin_timer_trigger_pdata {
- bool output_enable;
- bool active_low;
- unsigned int duty_ns;
-};
-
-#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 26/28] samples: Remove Blackfin gptimers sample code
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (23 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 25/28] staging: Remove Blackfin iio trigger timer support Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 27/28] documentation: Remove Blackfin documentation Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 28/28] MAINTAINERS: Remove Blackfin from MAINTAINERS list Aaron Wu
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin gptimers sample code
---
samples/Kconfig | 6 ---
samples/Makefile | 2 +-
samples/blackfin/Makefile | 1 -
samples/blackfin/gptimers-example.c | 91 -------------------------------------
4 files changed, 1 insertion(+), 99 deletions(-)
delete mode 100644 samples/blackfin/Makefile
delete mode 100644 samples/blackfin/gptimers-example.c
diff --git a/samples/Kconfig b/samples/Kconfig
index c332a3b..f524f55 100644
--- a/samples/Kconfig
+++ b/samples/Kconfig
@@ -98,12 +98,6 @@ config SAMPLE_SECCOMP
Build samples of seccomp filters using various methods of
BPF filter construction.
-config SAMPLE_BLACKFIN_GPTIMERS
- tristate "Build blackfin gptimers sample code -- loadable modules only"
- depends on BLACKFIN && BFIN_GPTIMERS && m
- help
- Build samples of blackfin gptimers sample module.
-
config SAMPLE_VFIO_MDEV_MTTY
tristate "Build VFIO mtty example mediated device sample code -- loadable modules only"
depends on VFIO_MDEV_DEVICE && m
diff --git a/samples/Makefile b/samples/Makefile
index db54e76..70cf375 100644
--- a/samples/Makefile
+++ b/samples/Makefile
@@ -2,5 +2,5 @@
obj-$(CONFIG_SAMPLES) += kobject/ kprobes/ trace_events/ livepatch/ \
hw_breakpoint/ kfifo/ kdb/ hidraw/ rpmsg/ seccomp/ \
- configfs/ connector/ v4l/ trace_printk/ blackfin/ \
+ configfs/ connector/ v4l/ trace_printk/ \
vfio-mdev/ statx/
diff --git a/samples/blackfin/Makefile b/samples/blackfin/Makefile
deleted file mode 100644
index 89b86cf..0000000
--- a/samples/blackfin/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-$(CONFIG_SAMPLE_BLACKFIN_GPTIMERS) += gptimers-example.o
diff --git a/samples/blackfin/gptimers-example.c b/samples/blackfin/gptimers-example.c
deleted file mode 100644
index 283eba9..0000000
--- a/samples/blackfin/gptimers-example.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Simple gptimers example
- * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:gptimers
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/interrupt.h>
-#include <linux/module.h>
-
-#include <asm/gptimers.h>
-#include <asm/portmux.h>
-
-/* ... random driver includes ... */
-
-#define DRIVER_NAME "gptimer_example"
-
-#ifdef IRQ_TIMER5
-#define SAMPLE_IRQ_TIMER IRQ_TIMER5
-#else
-#define SAMPLE_IRQ_TIMER IRQ_TIMER2
-#endif
-
-struct gptimer_data {
- uint32_t period, width;
-};
-static struct gptimer_data data;
-
-/* ... random driver state ... */
-
-static irqreturn_t gptimer_example_irq(int irq, void *dev_id)
-{
- struct gptimer_data *data = dev_id;
-
- /* make sure it was our timer which caused the interrupt */
- if (!get_gptimer_intr(TIMER5_id))
- return IRQ_NONE;
-
- /* read the width/period values that were captured for the waveform */
- data->width = get_gptimer_pwidth(TIMER5_id);
- data->period = get_gptimer_period(TIMER5_id);
-
- /* acknowledge the interrupt */
- clear_gptimer_intr(TIMER5_id);
-
- /* tell the upper layers we took care of things */
- return IRQ_HANDLED;
-}
-
-/* ... random driver code ... */
-
-static int __init gptimer_example_init(void)
-{
- int ret;
-
- /* grab the peripheral pins */
- ret = peripheral_request(P_TMR5, DRIVER_NAME);
- if (ret) {
- printk(KERN_NOTICE DRIVER_NAME ": peripheral request failed\n");
- return ret;
- }
-
- /* grab the IRQ for the timer */
- ret = request_irq(SAMPLE_IRQ_TIMER, gptimer_example_irq,
- IRQF_SHARED, DRIVER_NAME, &data);
- if (ret) {
- printk(KERN_NOTICE DRIVER_NAME ": IRQ request failed\n");
- peripheral_free(P_TMR5);
- return ret;
- }
-
- /* setup the timer and enable it */
- set_gptimer_config(TIMER5_id,
- WDTH_CAP | PULSE_HI | PERIOD_CNT | IRQ_ENA);
- enable_gptimers(TIMER5bit);
-
- return 0;
-}
-module_init(gptimer_example_init);
-
-static void __exit gptimer_example_exit(void)
-{
- disable_gptimers(TIMER5bit);
- free_irq(SAMPLE_IRQ_TIMER, &data);
- peripheral_free(P_TMR5);
-}
-module_exit(gptimer_example_exit);
-
-MODULE_LICENSE("BSD");
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 27/28] documentation: Remove Blackfin documentation
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (24 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 26/28] samples: Remove Blackfin gptimers sample code Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 28/28] MAINTAINERS: Remove Blackfin from MAINTAINERS list Aaron Wu
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin documentation
---
Documentation/00-INDEX | 2 -
Documentation/admin-guide/kernel-parameters.rst | 1 -
Documentation/admin-guide/kernel-parameters.txt | 2 +-
Documentation/blackfin/00-INDEX | 6 --
Documentation/blackfin/bfin-gpio-notes.txt | 71 ----------------------
Documentation/blackfin/bfin-spi-notes.txt | 16 -----
.../driver-api/usb/writing_musb_glue_layer.rst | 3 -
.../features/core/BPF-JIT/arch-support.txt | 1 -
.../core/generic-idle-thread/arch-support.txt | 1 -
.../features/core/jump-labels/arch-support.txt | 1 -
.../features/core/tracehook/arch-support.txt | 1 -
.../features/debug/KASAN/arch-support.txt | 1 -
.../debug/gcov-profile-all/arch-support.txt | 1 -
Documentation/features/debug/kgdb/arch-support.txt | 1 -
.../debug/kprobes-on-ftrace/arch-support.txt | 1 -
.../features/debug/kprobes/arch-support.txt | 1 -
.../features/debug/kretprobes/arch-support.txt | 1 -
.../features/debug/optprobes/arch-support.txt | 1 -
.../features/debug/stackprotector/arch-support.txt | 1 -
.../features/debug/uprobes/arch-support.txt | 1 -
.../debug/user-ret-profiler/arch-support.txt | 1 -
.../features/io/dma-api-debug/arch-support.txt | 1 -
.../features/io/dma-contiguous/arch-support.txt | 1 -
.../features/io/sg-chain/arch-support.txt | 1 -
.../features/lib/strncasecmp/arch-support.txt | 1 -
.../locking/cmpxchg-local/arch-support.txt | 1 -
.../features/locking/lockdep/arch-support.txt | 1 -
.../locking/queued-rwlocks/arch-support.txt | 1 -
.../locking/queued-spinlocks/arch-support.txt | 1 -
.../locking/rwsem-optimized/arch-support.txt | 1 -
.../features/perf/kprobes-event/arch-support.txt | 1 -
.../features/perf/perf-regs/arch-support.txt | 1 -
.../features/perf/perf-stackdump/arch-support.txt | 1 -
.../sched/membarrier-sync-core/arch-support.txt | 1 -
.../features/sched/numa-balancing/arch-support.txt | 1 -
.../seccomp/seccomp-filter/arch-support.txt | 1 -
.../time/arch-tick-broadcast/arch-support.txt | 1 -
.../features/time/clockevents/arch-support.txt | 1 -
.../time/context-tracking/arch-support.txt | 1 -
.../features/time/irq-time-acct/arch-support.txt | 1 -
.../time/modern-timekeeping/arch-support.txt | 1 -
.../features/time/virt-cpuacct/arch-support.txt | 1 -
.../features/vm/ELF-ASLR/arch-support.txt | 1 -
.../features/vm/PG_uncached/arch-support.txt | 1 -
Documentation/features/vm/THP/arch-support.txt | 1 -
Documentation/features/vm/TLB/arch-support.txt | 1 -
.../features/vm/huge-vmap/arch-support.txt | 1 -
.../features/vm/ioremap_prot/arch-support.txt | 1 -
.../features/vm/numa-memblock/arch-support.txt | 1 -
.../features/vm/pte_special/arch-support.txt | 1 -
50 files changed, 1 insertion(+), 143 deletions(-)
delete mode 100644 Documentation/blackfin/00-INDEX
delete mode 100644 Documentation/blackfin/bfin-gpio-notes.txt
delete mode 100644 Documentation/blackfin/bfin-spi-notes.txt
diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX
index 7f3a072..2956d7f 100644
--- a/Documentation/00-INDEX
+++ b/Documentation/00-INDEX
@@ -66,8 +66,6 @@ backlight/
- directory with info on controlling backlights in flat panel displays
bcache.txt
- Block-layer cache on fast SSDs to improve slow (raid) I/O performance.
-blackfin/
- - directory with documentation for the Blackfin arch.
block/
- info on the Block I/O (BIO) layer.
blockdev/
diff --git a/Documentation/admin-guide/kernel-parameters.rst b/Documentation/admin-guide/kernel-parameters.rst
index 7242cbd..b8d0bc0 100644
--- a/Documentation/admin-guide/kernel-parameters.rst
+++ b/Documentation/admin-guide/kernel-parameters.rst
@@ -89,7 +89,6 @@ parameter is applicable::
APM Advanced Power Management support is enabled.
ARM ARM architecture is enabled.
AX25 Appropriate AX.25 support is enabled.
- BLACKFIN Blackfin architecture is enabled.
CLK Common clock infrastructure is enabled.
CMA Contiguous Memory Area support is enabled.
DRM Direct Rendering Management support is enabled.
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 1d1d53f..0d9b5b7 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -1025,7 +1025,7 @@
address. The serial port must already be setup
and configured. Options are not yet supported.
- earlyprintk= [X86,SH,BLACKFIN,ARM,M68k,S390]
+ earlyprintk= [X86,SH,ARM,M68k,S390]
earlyprintk=vga
earlyprintk=efi
earlyprintk=sclp
diff --git a/Documentation/blackfin/00-INDEX b/Documentation/blackfin/00-INDEX
deleted file mode 100644
index 265a1ef..0000000
--- a/Documentation/blackfin/00-INDEX
+++ /dev/null
@@ -1,6 +0,0 @@
-00-INDEX
- - This file
-bfin-gpio-notes.txt
- - Notes in developing/using bfin-gpio driver.
-bfin-spi-notes.txt
- - Notes for using bfin spi bus driver.
diff --git a/Documentation/blackfin/bfin-gpio-notes.txt b/Documentation/blackfin/bfin-gpio-notes.txt
deleted file mode 100644
index d245f39..0000000
--- a/Documentation/blackfin/bfin-gpio-notes.txt
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * File: Documentation/blackfin/bfin-gpio-notes.txt
- * Based on:
- * Author:
- *
- * Created: $Id: bfin-gpio-note.txt 2008-11-24 16:42 grafyang $
- * Description: This file contains the notes in developing/using bfin-gpio.
- *
- *
- * Rev:
- *
- * Modified:
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- */
-
-
-1. Blackfin GPIO introduction
-
- There are many GPIO pins on Blackfin. Most of these pins are muxed to
- multi-functions. They can be configured as peripheral, or just as GPIO,
- configured to input with interrupt enabled, or output.
-
- For detailed information, please see "arch/blackfin/kernel/bfin_gpio.c",
- or the relevant HRM.
-
-
-2. Avoiding resource conflict
-
- Followed function groups are used to avoiding resource conflict,
- - Use the pin as peripheral,
- int peripheral_request(unsigned short per, const char *label);
- int peripheral_request_list(const unsigned short per[], const char *label);
- void peripheral_free(unsigned short per);
- void peripheral_free_list(const unsigned short per[]);
- - Use the pin as GPIO,
- int bfin_gpio_request(unsigned gpio, const char *label);
- void bfin_gpio_free(unsigned gpio);
- - Use the pin as GPIO interrupt,
- int bfin_gpio_irq_request(unsigned gpio, const char *label);
- void bfin_gpio_irq_free(unsigned gpio);
-
- The request functions will record the function state for a certain pin,
- the free functions will clear its function state.
- Once a pin is requested, it can't be requested again before it is freed by
- previous caller, otherwise kernel will dump stacks, and the request
- function fail.
- These functions are wrapped by other functions, most of the users need not
- care.
-
-
-3. But there are some exceptions
- - Kernel permit the identical GPIO be requested both as GPIO and GPIO
- interrupt.
- Some drivers, like gpio-keys, need this behavior. Kernel only print out
- warning messages like,
- bfin-gpio: GPIO 24 is already reserved by gpio-keys: BTN0, and you are
-configuring it as IRQ!
-
- Note: Consider the case that, if there are two drivers need the
- identical GPIO, one of them use it as GPIO, the other use it as
- GPIO interrupt. This will really cause resource conflict. So if
- there is any abnormal driver behavior, please check the bfin-gpio
- warning messages.
-
- - Kernel permit the identical GPIO be requested from the same driver twice.
-
-
-
diff --git a/Documentation/blackfin/bfin-spi-notes.txt b/Documentation/blackfin/bfin-spi-notes.txt
deleted file mode 100644
index eae6eaf..0000000
--- a/Documentation/blackfin/bfin-spi-notes.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-SPI Chip Select behavior:
-
-With the Blackfin on-chip SPI peripheral, there is some logic tied to the CPHA
-bit whether the Slave Select Line is controlled by hardware (CPHA=0) or
-controlled by software (CPHA=1). However, the Linux SPI bus driver assumes that
-the Slave Select is always under software control and being asserted during
-the entire SPI transfer. - And not just bits_per_word duration.
-
-In most cases you can utilize SPI MODE_3 instead of MODE_0 to work-around this
-behavior. If your SPI slave device in question requires SPI MODE_0 or MODE_2
-timing, you can utilize the GPIO controlled SPI Slave Select option instead.
-In this case, you should use GPIO based CS for all of your slaves and not just
-the ones using mode 0 or 2 in order to guarantee correct CS toggling behavior.
-
-You can even use the same pin whose peripheral role is a SSEL,
-but use it as a GPIO instead.
diff --git a/Documentation/driver-api/usb/writing_musb_glue_layer.rst b/Documentation/driver-api/usb/writing_musb_glue_layer.rst
index e90e8fa..5bf7152 100644
--- a/Documentation/driver-api/usb/writing_musb_glue_layer.rst
+++ b/Documentation/driver-api/usb/writing_musb_glue_layer.rst
@@ -718,6 +718,3 @@ http://www.maximintegrated.com/app-notes/index.mvp/id/1822
Texas Instruments USB Configuration Wiki Page:
http://processors.wiki.ti.com/index.php/Usbgeneralpage
-
-Analog Devices Blackfin MUSB Configuration:
-http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:musb
diff --git a/Documentation/features/core/BPF-JIT/arch-support.txt b/Documentation/features/core/BPF-JIT/arch-support.txt
index 5575d2d..740879c 100644
--- a/Documentation/features/core/BPF-JIT/arch-support.txt
+++ b/Documentation/features/core/BPF-JIT/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/core/generic-idle-thread/arch-support.txt b/Documentation/features/core/generic-idle-thread/arch-support.txt
index abb5f27..eff8cc3 100644
--- a/Documentation/features/core/generic-idle-thread/arch-support.txt
+++ b/Documentation/features/core/generic-idle-thread/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | ok |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/core/jump-labels/arch-support.txt b/Documentation/features/core/jump-labels/arch-support.txt
index dbdaffc..7f90c27 100644
--- a/Documentation/features/core/jump-labels/arch-support.txt
+++ b/Documentation/features/core/jump-labels/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/core/tracehook/arch-support.txt b/Documentation/features/core/tracehook/arch-support.txt
index dfb638c..9239b54 100644
--- a/Documentation/features/core/tracehook/arch-support.txt
+++ b/Documentation/features/core/tracehook/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | ok |
| c6x: | ok |
| cris: | TODO |
| frv: | ok |
diff --git a/Documentation/features/debug/KASAN/arch-support.txt b/Documentation/features/debug/KASAN/arch-support.txt
index 3406fae..38f2b5f 100644
--- a/Documentation/features/debug/KASAN/arch-support.txt
+++ b/Documentation/features/debug/KASAN/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt
index 830dbe8..d5f6330 100644
--- a/Documentation/features/debug/gcov-profile-all/arch-support.txt
+++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/debug/kgdb/arch-support.txt b/Documentation/features/debug/kgdb/arch-support.txt
index 0217bf6..1100345 100644
--- a/Documentation/features/debug/kgdb/arch-support.txt
+++ b/Documentation/features/debug/kgdb/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | ok |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt
index 1e84be3c..250248d 100644
--- a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt
+++ b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/debug/kprobes/arch-support.txt b/Documentation/features/debug/kprobes/arch-support.txt
index 529f66e..a23d2f3 100644
--- a/Documentation/features/debug/kprobes/arch-support.txt
+++ b/Documentation/features/debug/kprobes/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | ok |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/debug/kretprobes/arch-support.txt b/Documentation/features/debug/kretprobes/arch-support.txt
index 4335324..145f65b 100644
--- a/Documentation/features/debug/kretprobes/arch-support.txt
+++ b/Documentation/features/debug/kretprobes/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | ok |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/debug/optprobes/arch-support.txt b/Documentation/features/debug/optprobes/arch-support.txt
index f559f1b..6a4bb93 100644
--- a/Documentation/features/debug/optprobes/arch-support.txt
+++ b/Documentation/features/debug/optprobes/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/debug/stackprotector/arch-support.txt b/Documentation/features/debug/stackprotector/arch-support.txt
index 59a4c9f..38f2ed4 100644
--- a/Documentation/features/debug/stackprotector/arch-support.txt
+++ b/Documentation/features/debug/stackprotector/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/debug/uprobes/arch-support.txt b/Documentation/features/debug/uprobes/arch-support.txt
index 53ed42b..6f617f7 100644
--- a/Documentation/features/debug/uprobes/arch-support.txt
+++ b/Documentation/features/debug/uprobes/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/debug/user-ret-profiler/arch-support.txt b/Documentation/features/debug/user-ret-profiler/arch-support.txt
index 1494439..6b772ed0 100644
--- a/Documentation/features/debug/user-ret-profiler/arch-support.txt
+++ b/Documentation/features/debug/user-ret-profiler/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/io/dma-api-debug/arch-support.txt b/Documentation/features/io/dma-api-debug/arch-support.txt
index 6be9206..1c07e83b 100644
--- a/Documentation/features/io/dma-api-debug/arch-support.txt
+++ b/Documentation/features/io/dma-api-debug/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | ok |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/io/dma-contiguous/arch-support.txt b/Documentation/features/io/dma-contiguous/arch-support.txt
index 0eb08e1..2d86648 100644
--- a/Documentation/features/io/dma-contiguous/arch-support.txt
+++ b/Documentation/features/io/dma-contiguous/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/io/sg-chain/arch-support.txt b/Documentation/features/io/sg-chain/arch-support.txt
index 514ad34..62bc1e0 100644
--- a/Documentation/features/io/sg-chain/arch-support.txt
+++ b/Documentation/features/io/sg-chain/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/lib/strncasecmp/arch-support.txt b/Documentation/features/lib/strncasecmp/arch-support.txt
index 532c6f0..d71b852 100644
--- a/Documentation/features/lib/strncasecmp/arch-support.txt
+++ b/Documentation/features/lib/strncasecmp/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/locking/cmpxchg-local/arch-support.txt b/Documentation/features/locking/cmpxchg-local/arch-support.txt
index f3eec26..4e9f51b 100644
--- a/Documentation/features/locking/cmpxchg-local/arch-support.txt
+++ b/Documentation/features/locking/cmpxchg-local/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/locking/lockdep/arch-support.txt b/Documentation/features/locking/lockdep/arch-support.txt
index 9756abc..4632644 100644
--- a/Documentation/features/locking/lockdep/arch-support.txt
+++ b/Documentation/features/locking/lockdep/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | ok |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/locking/queued-rwlocks/arch-support.txt b/Documentation/features/locking/queued-rwlocks/arch-support.txt
index 62f4ee5..1cf417e 100644
--- a/Documentation/features/locking/queued-rwlocks/arch-support.txt
+++ b/Documentation/features/locking/queued-rwlocks/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/locking/queued-spinlocks/arch-support.txt b/Documentation/features/locking/queued-spinlocks/arch-support.txt
index 321b32f..aea2efa 100644
--- a/Documentation/features/locking/queued-spinlocks/arch-support.txt
+++ b/Documentation/features/locking/queued-spinlocks/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/locking/rwsem-optimized/arch-support.txt b/Documentation/features/locking/rwsem-optimized/arch-support.txt
index 79bfa4d..7414867 100644
--- a/Documentation/features/locking/rwsem-optimized/arch-support.txt
+++ b/Documentation/features/locking/rwsem-optimized/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/perf/kprobes-event/arch-support.txt b/Documentation/features/perf/kprobes-event/arch-support.txt
index 00f1606..f0f6cec 100644
--- a/Documentation/features/perf/kprobes-event/arch-support.txt
+++ b/Documentation/features/perf/kprobes-event/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/perf/perf-regs/arch-support.txt b/Documentation/features/perf/perf-regs/arch-support.txt
index 7d516ea..6b305e6 100644
--- a/Documentation/features/perf/perf-regs/arch-support.txt
+++ b/Documentation/features/perf/perf-regs/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/perf/perf-stackdump/arch-support.txt b/Documentation/features/perf/perf-stackdump/arch-support.txt
index f974b8d..cafa704 100644
--- a/Documentation/features/perf/perf-stackdump/arch-support.txt
+++ b/Documentation/features/perf/perf-stackdump/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/sched/membarrier-sync-core/arch-support.txt b/Documentation/features/sched/membarrier-sync-core/arch-support.txt
index 2c815a7..ccbfb24 100644
--- a/Documentation/features/sched/membarrier-sync-core/arch-support.txt
+++ b/Documentation/features/sched/membarrier-sync-core/arch-support.txt
@@ -33,7 +33,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/sched/numa-balancing/arch-support.txt b/Documentation/features/sched/numa-balancing/arch-support.txt
index 1d3c0f6..54fa603 100644
--- a/Documentation/features/sched/numa-balancing/arch-support.txt
+++ b/Documentation/features/sched/numa-balancing/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | .. |
| arm: | .. |
| arm64: | .. |
- | blackfin: | .. |
| c6x: | .. |
| cris: | .. |
| frv: | .. |
diff --git a/Documentation/features/seccomp/seccomp-filter/arch-support.txt b/Documentation/features/seccomp/seccomp-filter/arch-support.txt
index a32d5b2..dc0a901 100644
--- a/Documentation/features/seccomp/seccomp-filter/arch-support.txt
+++ b/Documentation/features/seccomp/seccomp-filter/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/time/arch-tick-broadcast/arch-support.txt b/Documentation/features/time/arch-tick-broadcast/arch-support.txt
index caee8f6..ca3aa5c 100644
--- a/Documentation/features/time/arch-tick-broadcast/arch-support.txt
+++ b/Documentation/features/time/arch-tick-broadcast/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/time/clockevents/arch-support.txt b/Documentation/features/time/clockevents/arch-support.txt
index 1cd87f6..8535d3c 100644
--- a/Documentation/features/time/clockevents/arch-support.txt
+++ b/Documentation/features/time/clockevents/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | ok |
| c6x: | ok |
| cris: | ok |
| frv: | TODO |
diff --git a/Documentation/features/time/context-tracking/arch-support.txt b/Documentation/features/time/context-tracking/arch-support.txt
index e6d7c7b..cffcf08 100644
--- a/Documentation/features/time/context-tracking/arch-support.txt
+++ b/Documentation/features/time/context-tracking/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/time/irq-time-acct/arch-support.txt b/Documentation/features/time/irq-time-acct/arch-support.txt
index 15c6071..9b1ab68 100644
--- a/Documentation/features/time/irq-time-acct/arch-support.txt
+++ b/Documentation/features/time/irq-time-acct/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/time/modern-timekeeping/arch-support.txt b/Documentation/features/time/modern-timekeeping/arch-support.txt
index baee761..fe4df2f 100644
--- a/Documentation/features/time/modern-timekeeping/arch-support.txt
+++ b/Documentation/features/time/modern-timekeeping/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | TODO |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | ok |
| cris: | TODO |
| frv: | ok |
diff --git a/Documentation/features/time/virt-cpuacct/arch-support.txt b/Documentation/features/time/virt-cpuacct/arch-support.txt
index 9129530..304b941 100644
--- a/Documentation/features/time/virt-cpuacct/arch-support.txt
+++ b/Documentation/features/time/virt-cpuacct/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/vm/ELF-ASLR/arch-support.txt b/Documentation/features/vm/ELF-ASLR/arch-support.txt
index f6829af..3efb2ae 100644
--- a/Documentation/features/vm/ELF-ASLR/arch-support.txt
+++ b/Documentation/features/vm/ELF-ASLR/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/vm/PG_uncached/arch-support.txt b/Documentation/features/vm/PG_uncached/arch-support.txt
index 1a09ea9..aadc97f 100644
--- a/Documentation/features/vm/PG_uncached/arch-support.txt
+++ b/Documentation/features/vm/PG_uncached/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/vm/THP/arch-support.txt b/Documentation/features/vm/THP/arch-support.txt
index d170e62..76cfb97 100644
--- a/Documentation/features/vm/THP/arch-support.txt
+++ b/Documentation/features/vm/THP/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | .. |
| c6x: | .. |
| cris: | .. |
| frv: | .. |
diff --git a/Documentation/features/vm/TLB/arch-support.txt b/Documentation/features/vm/TLB/arch-support.txt
index abfab40..3a6546a 100644
--- a/Documentation/features/vm/TLB/arch-support.txt
+++ b/Documentation/features/vm/TLB/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | .. |
| cris: | .. |
| frv: | .. |
diff --git a/Documentation/features/vm/huge-vmap/arch-support.txt b/Documentation/features/vm/huge-vmap/arch-support.txt
index f81f09b..fe1e3b2 100644
--- a/Documentation/features/vm/huge-vmap/arch-support.txt
+++ b/Documentation/features/vm/huge-vmap/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | TODO |
| arm: | TODO |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt
index 0cc3e11..d42dbe0 100644
--- a/Documentation/features/vm/ioremap_prot/arch-support.txt
+++ b/Documentation/features/vm/ioremap_prot/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | TODO |
| arm64: | TODO |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
diff --git a/Documentation/features/vm/numa-memblock/arch-support.txt b/Documentation/features/vm/numa-memblock/arch-support.txt
index 9a3fdac..bb9cd30 100644
--- a/Documentation/features/vm/numa-memblock/arch-support.txt
+++ b/Documentation/features/vm/numa-memblock/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | .. |
| arm: | .. |
| arm64: | .. |
- | blackfin: | .. |
| c6x: | .. |
| cris: | .. |
| frv: | .. |
diff --git a/Documentation/features/vm/pte_special/arch-support.txt b/Documentation/features/vm/pte_special/arch-support.txt
index dfaa39e..f7b7626 100644
--- a/Documentation/features/vm/pte_special/arch-support.txt
+++ b/Documentation/features/vm/pte_special/arch-support.txt
@@ -10,7 +10,6 @@
| arc: | ok |
| arm: | ok |
| arm64: | ok |
- | blackfin: | TODO |
| c6x: | TODO |
| cris: | TODO |
| frv: | TODO |
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 28/28] MAINTAINERS: Remove Blackfin from MAINTAINERS list
2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
` (25 preceding siblings ...)
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 27/28] documentation: Remove Blackfin documentation Aaron Wu
@ 2018-03-15 10:50 ` Aaron Wu
26 siblings, 0 replies; 29+ messages in thread
From: Aaron Wu @ 2018-03-15 10:50 UTC (permalink / raw)
To: openrisc
Signed-off-by: Aaron Wu <aaron.wu@analog.com>
Remove Blackfin from MAINTAINERS list
---
MAINTAINERS | 52 ----------------------------------------------------
1 file changed, 52 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4623caf..f5a0857 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -841,13 +841,6 @@ F: sound/soc/codecs/ad7*
F: sound/soc/codecs/ssm*
F: sound/soc/codecs/sigmadsp.*
-ANALOG DEVICES INC ASOC DRIVERS
-L: adi-buildroot-devel at lists.sourceforge.net (moderated for non-subscribers)
-L: alsa-devel at alsa-project.org (moderated for non-subscribers)
-W: http://blackfin.uclinux.org/
-S: Supported
-F: sound/soc/blackfin/*
-
ANALOG DEVICES INC DMA DRIVERS
M: Lars-Peter Clausen <lars@metafoo.de>
W: http://ez.analog.com/community/linux-device-drivers
@@ -2629,51 +2622,6 @@ F: Documentation/filesystems/bfs.txt
F: fs/bfs/
F: include/uapi/linux/bfs_fs.h
-BLACKFIN ARCHITECTURE
-L: adi-buildroot-devel at lists.sourceforge.net (moderated for non-subscribers)
-T: git git://git.code.sf.net/p/adi-linux/code
-W: http://blackfin.uclinux.org
-S: Orphan
-F: arch/blackfin/
-
-BLACKFIN EMAC DRIVER
-L: adi-buildroot-devel at lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/net/ethernet/adi/
-
-BLACKFIN MEDIA DRIVER
-L: adi-buildroot-devel at lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org/
-S: Orphan
-F: drivers/media/platform/blackfin/
-F: drivers/media/i2c/adv7183*
-F: drivers/media/i2c/vs6624*
-
-BLACKFIN RTC DRIVER
-L: adi-buildroot-devel at lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/rtc/rtc-bfin.c
-
-BLACKFIN SDH DRIVER
-L: adi-buildroot-devel at lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/mmc/host/bfin_sdh.c
-
-BLACKFIN SERIAL DRIVER
-L: adi-buildroot-devel at lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/tty/serial/bfin_uart.c
-
-BLACKFIN WATCHDOG DRIVER
-L: adi-buildroot-devel at lists.sourceforge.net (moderated for non-subscribers)
-W: http://blackfin.uclinux.org
-S: Orphan
-F: drivers/watchdog/bfin_wdt.c
-
BLINKM RGB LED DRIVER
M: Jan-Simon Moeller <jansimon.moeller@gmx.de>
S: Maintained
--
2.7.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [OpenRISC] [Blackfin removal] [PATCH 07/28] watchdog: Remove Blackfin watchdog support
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 07/28] watchdog: Remove Blackfin watchdog support Aaron Wu
@ 2018-03-15 14:43 ` Guenter Roeck
0 siblings, 0 replies; 29+ messages in thread
From: Guenter Roeck @ 2018-03-15 14:43 UTC (permalink / raw)
To: openrisc
On Thu, Mar 15, 2018 at 06:50:07PM +0800, Aaron Wu wrote:
> Signed-off-by: Aaron Wu <aaron.wu@analog.com>
>
> Remove Blackfin watchdog support
Signed-off statement comes last.
Anyway, wasn't this already submitted by Arnd ?
Guenter
> ---
> drivers/watchdog/Kconfig | 13 --
> drivers/watchdog/Makefile | 3 -
> drivers/watchdog/bfin_wdt.c | 476 --------------------------------------------
> 3 files changed, 492 deletions(-)
> delete mode 100644 drivers/watchdog/bfin_wdt.c
>
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 37460cd..6174e99 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -815,19 +815,6 @@ config SPRD_WATCHDOG
> Say Y here to include watchdog timer supported
> by Spreadtrum system.
>
> -# BLACKFIN Architecture
> -
> -config BFIN_WDT
> - tristate "Blackfin On-Chip Watchdog Timer"
> - depends on BLACKFIN
> - ---help---
> - If you say yes here you will get support for the Blackfin On-Chip
> - Watchdog Timer. If you have one of these processors and wish to
> - have watchdog support enabled, say Y, otherwise say N.
> -
> - To compile this driver as a module, choose M here: the
> - module will be called bfin_wdt.
> -
> # CRIS Architecture
>
> # FRV Architecture
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index 0474d38..1971f86 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -91,9 +91,6 @@ obj-$(CONFIG_UNIPHIER_WATCHDOG) += uniphier_wdt.o
> obj-$(CONFIG_RTD119X_WATCHDOG) += rtd119x_wdt.o
> obj-$(CONFIG_SPRD_WATCHDOG) += sprd_wdt.o
>
> -# BLACKFIN Architecture
> -obj-$(CONFIG_BFIN_WDT) += bfin_wdt.o
> -
> # CRIS Architecture
>
> # FRV Architecture
> diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c
> deleted file mode 100644
> index aa4d2e8..0000000
> --- a/drivers/watchdog/bfin_wdt.c
> +++ /dev/null
> @@ -1,476 +0,0 @@
> -/*
> - * Blackfin On-Chip Watchdog Driver
> - *
> - * Originally based on softdog.c
> - * Copyright 2006-2010 Analog Devices Inc.
> - * Copyright 2006-2007 Michele d'Amico
> - * Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
> - *
> - * Enter bugs at http://blackfin.uclinux.org/
> - *
> - * Licensed under the GPL-2 or later.
> - */
> -
> -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> -
> -#include <linux/platform_device.h>
> -#include <linux/module.h>
> -#include <linux/moduleparam.h>
> -#include <linux/types.h>
> -#include <linux/timer.h>
> -#include <linux/miscdevice.h>
> -#include <linux/watchdog.h>
> -#include <linux/fs.h>
> -#include <linux/init.h>
> -#include <linux/interrupt.h>
> -#include <linux/uaccess.h>
> -#include <asm/blackfin.h>
> -#include <asm/bfin_watchdog.h>
> -
> -#define stamp(fmt, args...) \
> - pr_debug("%s:%i: " fmt "\n", __func__, __LINE__, ## args)
> -#define stampit() stamp("here i am")
> -
> -#define WATCHDOG_NAME "bfin-wdt"
> -
> -/* The BF561 has two watchdogs (one per core), but since Linux
> - * only runs on core A, we'll just work with that one.
> - */
> -#ifdef BF561_FAMILY
> -# define bfin_read_WDOG_CTL() bfin_read_WDOGA_CTL()
> -# define bfin_read_WDOG_CNT() bfin_read_WDOGA_CNT()
> -# define bfin_read_WDOG_STAT() bfin_read_WDOGA_STAT()
> -# define bfin_write_WDOG_CTL(x) bfin_write_WDOGA_CTL(x)
> -# define bfin_write_WDOG_CNT(x) bfin_write_WDOGA_CNT(x)
> -# define bfin_write_WDOG_STAT(x) bfin_write_WDOGA_STAT(x)
> -#endif
> -
> -/* some defaults */
> -#define WATCHDOG_TIMEOUT 20
> -
> -static unsigned int timeout = WATCHDOG_TIMEOUT;
> -static bool nowayout = WATCHDOG_NOWAYOUT;
> -static const struct watchdog_info bfin_wdt_info;
> -static unsigned long open_check;
> -static char expect_close;
> -static DEFINE_SPINLOCK(bfin_wdt_spinlock);
> -
> -/**
> - * bfin_wdt_keepalive - Keep the Userspace Watchdog Alive
> - *
> - * The Userspace watchdog got a KeepAlive: schedule the next timeout.
> - */
> -static int bfin_wdt_keepalive(void)
> -{
> - stampit();
> - bfin_write_WDOG_STAT(0);
> - return 0;
> -}
> -
> -/**
> - * bfin_wdt_stop - Stop the Watchdog
> - *
> - * Stops the on-chip watchdog.
> - */
> -static int bfin_wdt_stop(void)
> -{
> - stampit();
> - bfin_write_WDOG_CTL(WDEN_DISABLE);
> - return 0;
> -}
> -
> -/**
> - * bfin_wdt_start - Start the Watchdog
> - *
> - * Starts the on-chip watchdog. Automatically loads WDOG_CNT
> - * into WDOG_STAT for us.
> - */
> -static int bfin_wdt_start(void)
> -{
> - stampit();
> - bfin_write_WDOG_CTL(WDEN_ENABLE | ICTL_RESET);
> - return 0;
> -}
> -
> -/**
> - * bfin_wdt_running - Check Watchdog status
> - *
> - * See if the watchdog is running.
> - */
> -static int bfin_wdt_running(void)
> -{
> - stampit();
> - return ((bfin_read_WDOG_CTL() & WDEN_MASK) != WDEN_DISABLE);
> -}
> -
> -/**
> - * bfin_wdt_set_timeout - Set the Userspace Watchdog timeout
> - * @t: new timeout value (in seconds)
> - *
> - * Translate the specified timeout in seconds into System Clock
> - * terms which is what the on-chip Watchdog requires.
> - */
> -static int bfin_wdt_set_timeout(unsigned long t)
> -{
> - u32 cnt, max_t, sclk;
> - unsigned long flags;
> -
> - sclk = get_sclk();
> - max_t = -1 / sclk;
> - cnt = t * sclk;
> - stamp("maxtimeout=%us newtimeout=%lus (cnt=%#x)", max_t, t, cnt);
> -
> - if (t > max_t) {
> - pr_warn("timeout value is too large\n");
> - return -EINVAL;
> - }
> -
> - spin_lock_irqsave(&bfin_wdt_spinlock, flags);
> - {
> - int run = bfin_wdt_running();
> - bfin_wdt_stop();
> - bfin_write_WDOG_CNT(cnt);
> - if (run)
> - bfin_wdt_start();
> - }
> - spin_unlock_irqrestore(&bfin_wdt_spinlock, flags);
> -
> - timeout = t;
> -
> - return 0;
> -}
> -
> -/**
> - * bfin_wdt_open - Open the Device
> - * @inode: inode of device
> - * @file: file handle of device
> - *
> - * Watchdog device is opened and started.
> - */
> -static int bfin_wdt_open(struct inode *inode, struct file *file)
> -{
> - stampit();
> -
> - if (test_and_set_bit(0, &open_check))
> - return -EBUSY;
> -
> - if (nowayout)
> - __module_get(THIS_MODULE);
> -
> - bfin_wdt_keepalive();
> - bfin_wdt_start();
> -
> - return nonseekable_open(inode, file);
> -}
> -
> -/**
> - * bfin_wdt_close - Close the Device
> - * @inode: inode of device
> - * @file: file handle of device
> - *
> - * Watchdog device is closed and stopped.
> - */
> -static int bfin_wdt_release(struct inode *inode, struct file *file)
> -{
> - stampit();
> -
> - if (expect_close == 42)
> - bfin_wdt_stop();
> - else {
> - pr_crit("Unexpected close, not stopping watchdog!\n");
> - bfin_wdt_keepalive();
> - }
> - expect_close = 0;
> - clear_bit(0, &open_check);
> - return 0;
> -}
> -
> -/**
> - * bfin_wdt_write - Write to Device
> - * @file: file handle of device
> - * @buf: buffer to write
> - * @count: length of buffer
> - * @ppos: offset
> - *
> - * Pings the watchdog on write.
> - */
> -static ssize_t bfin_wdt_write(struct file *file, const char __user *data,
> - size_t len, loff_t *ppos)
> -{
> - stampit();
> -
> - if (len) {
> - if (!nowayout) {
> - size_t i;
> -
> - /* In case it was set long ago */
> - expect_close = 0;
> -
> - for (i = 0; i != len; i++) {
> - char c;
> - if (get_user(c, data + i))
> - return -EFAULT;
> - if (c == 'V')
> - expect_close = 42;
> - }
> - }
> - bfin_wdt_keepalive();
> - }
> -
> - return len;
> -}
> -
> -/**
> - * bfin_wdt_ioctl - Query Device
> - * @file: file handle of device
> - * @cmd: watchdog command
> - * @arg: argument
> - *
> - * Query basic information from the device or ping it, as outlined by the
> - * watchdog API.
> - */
> -static long bfin_wdt_ioctl(struct file *file,
> - unsigned int cmd, unsigned long arg)
> -{
> - void __user *argp = (void __user *)arg;
> - int __user *p = argp;
> -
> - stampit();
> -
> - switch (cmd) {
> - case WDIOC_GETSUPPORT:
> - if (copy_to_user(argp, &bfin_wdt_info, sizeof(bfin_wdt_info)))
> - return -EFAULT;
> - else
> - return 0;
> - case WDIOC_GETSTATUS:
> - case WDIOC_GETBOOTSTATUS:
> - return put_user(!!(_bfin_swrst & SWRST_RESET_WDOG), p);
> - case WDIOC_SETOPTIONS: {
> - unsigned long flags;
> - int options, ret = -EINVAL;
> -
> - if (get_user(options, p))
> - return -EFAULT;
> -
> - spin_lock_irqsave(&bfin_wdt_spinlock, flags);
> - if (options & WDIOS_DISABLECARD) {
> - bfin_wdt_stop();
> - ret = 0;
> - }
> - if (options & WDIOS_ENABLECARD) {
> - bfin_wdt_start();
> - ret = 0;
> - }
> - spin_unlock_irqrestore(&bfin_wdt_spinlock, flags);
> - return ret;
> - }
> - case WDIOC_KEEPALIVE:
> - bfin_wdt_keepalive();
> - return 0;
> - case WDIOC_SETTIMEOUT: {
> - int new_timeout;
> -
> - if (get_user(new_timeout, p))
> - return -EFAULT;
> - if (bfin_wdt_set_timeout(new_timeout))
> - return -EINVAL;
> - }
> - /* Fall */
> - case WDIOC_GETTIMEOUT:
> - return put_user(timeout, p);
> - default:
> - return -ENOTTY;
> - }
> -}
> -
> -#ifdef CONFIG_PM
> -static int state_before_suspend;
> -
> -/**
> - * bfin_wdt_suspend - suspend the watchdog
> - * @pdev: device being suspended
> - * @state: requested suspend state
> - *
> - * Remember if the watchdog was running and stop it.
> - * TODO: is this even right? Doesn't seem to be any
> - * standard in the watchdog world ...
> - */
> -static int bfin_wdt_suspend(struct platform_device *pdev, pm_message_t state)
> -{
> - stampit();
> -
> - state_before_suspend = bfin_wdt_running();
> - bfin_wdt_stop();
> -
> - return 0;
> -}
> -
> -/**
> - * bfin_wdt_resume - resume the watchdog
> - * @pdev: device being resumed
> - *
> - * If the watchdog was running, turn it back on.
> - */
> -static int bfin_wdt_resume(struct platform_device *pdev)
> -{
> - stampit();
> -
> - if (state_before_suspend) {
> - bfin_wdt_set_timeout(timeout);
> - bfin_wdt_start();
> - }
> -
> - return 0;
> -}
> -#else
> -# define bfin_wdt_suspend NULL
> -# define bfin_wdt_resume NULL
> -#endif
> -
> -static const struct file_operations bfin_wdt_fops = {
> - .owner = THIS_MODULE,
> - .llseek = no_llseek,
> - .write = bfin_wdt_write,
> - .unlocked_ioctl = bfin_wdt_ioctl,
> - .open = bfin_wdt_open,
> - .release = bfin_wdt_release,
> -};
> -
> -static struct miscdevice bfin_wdt_miscdev = {
> - .minor = WATCHDOG_MINOR,
> - .name = "watchdog",
> - .fops = &bfin_wdt_fops,
> -};
> -
> -static const struct watchdog_info bfin_wdt_info = {
> - .identity = "Blackfin Watchdog",
> - .options = WDIOF_SETTIMEOUT |
> - WDIOF_KEEPALIVEPING |
> - WDIOF_MAGICCLOSE,
> -};
> -
> -/**
> - * bfin_wdt_probe - Initialize module
> - *
> - * Registers the misc device. Actual device
> - * initialization is handled by bfin_wdt_open().
> - */
> -static int bfin_wdt_probe(struct platform_device *pdev)
> -{
> - int ret;
> -
> - ret = misc_register(&bfin_wdt_miscdev);
> - if (ret) {
> - pr_err("cannot register miscdev on minor=%d (err=%d)\n",
> - WATCHDOG_MINOR, ret);
> - return ret;
> - }
> -
> - pr_info("initialized: timeout=%d sec (nowayout=%d)\n",
> - timeout, nowayout);
> -
> - return 0;
> -}
> -
> -/**
> - * bfin_wdt_remove - Initialize module
> - *
> - * Unregisters the misc device. Actual device
> - * deinitialization is handled by bfin_wdt_close().
> - */
> -static int bfin_wdt_remove(struct platform_device *pdev)
> -{
> - misc_deregister(&bfin_wdt_miscdev);
> - return 0;
> -}
> -
> -/**
> - * bfin_wdt_shutdown - Soft Shutdown Handler
> - *
> - * Handles the soft shutdown event.
> - */
> -static void bfin_wdt_shutdown(struct platform_device *pdev)
> -{
> - stampit();
> -
> - bfin_wdt_stop();
> -}
> -
> -static struct platform_device *bfin_wdt_device;
> -
> -static struct platform_driver bfin_wdt_driver = {
> - .probe = bfin_wdt_probe,
> - .remove = bfin_wdt_remove,
> - .shutdown = bfin_wdt_shutdown,
> - .suspend = bfin_wdt_suspend,
> - .resume = bfin_wdt_resume,
> - .driver = {
> - .name = WATCHDOG_NAME,
> - },
> -};
> -
> -/**
> - * bfin_wdt_init - Initialize module
> - *
> - * Checks the module params and registers the platform device & driver.
> - * Real work is in the platform probe function.
> - */
> -static int __init bfin_wdt_init(void)
> -{
> - int ret;
> -
> - stampit();
> -
> - /* Check that the timeout value is within range */
> - if (bfin_wdt_set_timeout(timeout))
> - return -EINVAL;
> -
> - /* Since this is an on-chip device and needs no board-specific
> - * resources, we'll handle all the platform device stuff here.
> - */
> - ret = platform_driver_register(&bfin_wdt_driver);
> - if (ret) {
> - pr_err("unable to register driver\n");
> - return ret;
> - }
> -
> - bfin_wdt_device = platform_device_register_simple(WATCHDOG_NAME,
> - -1, NULL, 0);
> - if (IS_ERR(bfin_wdt_device)) {
> - pr_err("unable to register device\n");
> - platform_driver_unregister(&bfin_wdt_driver);
> - return PTR_ERR(bfin_wdt_device);
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * bfin_wdt_exit - Deinitialize module
> - *
> - * Back out the platform device & driver steps. Real work is in the
> - * platform remove function.
> - */
> -static void __exit bfin_wdt_exit(void)
> -{
> - platform_device_unregister(bfin_wdt_device);
> - platform_driver_unregister(&bfin_wdt_driver);
> -}
> -
> -module_init(bfin_wdt_init);
> -module_exit(bfin_wdt_exit);
> -
> -MODULE_AUTHOR("Michele d'Amico, Mike Frysinger <vapier@gentoo.org>");
> -MODULE_DESCRIPTION("Blackfin Watchdog Device Driver");
> -MODULE_LICENSE("GPL");
> -
> -module_param(timeout, uint, 0);
> -MODULE_PARM_DESC(timeout,
> - "Watchdog timeout in seconds. (1<=timeout<=((2^32)/SCLK), default="
> - __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
> -
> -module_param(nowayout, bool, 0);
> -MODULE_PARM_DESC(nowayout,
> - "Watchdog cannot be stopped once started (default="
> - __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2018-03-15 14:43 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz follow: Atom feed
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2018-03-15 10:50 [OpenRISC] [Blackfin removal] [PATCH 01/28] Blackfin arch: Remove Blackfin CPU arch general support Aaron Wu
2018-03-15 10:50 ` [OpenRISC] [Blackfin removal] [PATCH 02/28] net: Remove Blackfin Ethernet support Aaron Wu
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