* [PATCH 1/2] platform: Remove platform/thead
@ 2021-04-24 2:01 guoren
2021-04-24 2:01 ` [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors guoren
2021-04-25 4:48 ` [PATCH 1/2] platform: Remove platform/thead Anup Patel
0 siblings, 2 replies; 7+ messages in thread
From: guoren @ 2021-04-24 2:01 UTC (permalink / raw)
To: opensbi
From: Guo Ren <guoren@linux.alibaba.com>
We could use platform/generic instead, and won't use it again.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Anup Patel <anup.patel@wdc.com>
---
docs/platform/platform.md | 3 -
docs/platform/thead-c910.md | 34 ---------
platform/thead/c910/config.mk | 14 ----
platform/thead/c910/objects.mk | 5 --
platform/thead/c910/platform.c | 156 ---------------------------------------
platform/thead/c910/platform.h | 46 ------------
scripts/create-binary-archive.sh | 1 -
7 files changed, 259 deletions(-)
delete mode 100644 docs/platform/thead-c910.md
delete mode 100644 platform/thead/c910/config.mk
delete mode 100644 platform/thead/c910/objects.mk
delete mode 100644 platform/thead/c910/platform.c
delete mode 100644 platform/thead/c910/platform.h
diff --git a/docs/platform/platform.md b/docs/platform/platform.md
index 7f47068..b0cff37 100644
--- a/docs/platform/platform.md
+++ b/docs/platform/platform.md
@@ -28,9 +28,6 @@ OpenSBI currently supports the following virtual and hardware platforms:
* **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350). More
details on this platform can be found in the file *[andes-ae350.md]*.
-* **T-HEAD C910**: Platform support for the T-HEAD C910 Processor. More
- details on this platform can be found in the file *[thead-c910.md]*.
-
* **Spike**: Platform support for the Spike emulator. More
details on this platform can be found in the file *[spike.md]*.
diff --git a/docs/platform/thead-c910.md b/docs/platform/thead-c910.md
deleted file mode 100644
index 786b47d..0000000
--- a/docs/platform/thead-c910.md
+++ /dev/null
@@ -1,34 +0,0 @@
-T-HEAD C910 Processor
-=====================
-C910 is a 12-stage, 3 issues, 8 executions, out-of-order 64-bit RISC-V CPU which
-supports 16 cores, runs with 2.5GHz, and is capable of running Linux.
-
-To build platform specific library and firmwares, provide the
-*PLATFORM=thead/c910* parameter to the top level make command.
-
-Platform Options
-----------------
-
-The *T-HEAD C910* platform does not have any platform-specific options.
-
-Building T-HEAD C910 Platform
------------------------------
-
-```
-make PLATFORM=thead/c910
-```
-
-Booting T-HEAD C910 Platform
-----------------------------
-
-**No Payload**
-
-As there's no payload, you may download vmlinux or u-boot to FW_JUMP_ADDR which
-specified in config.mk or compile commands with GDB. And the execution flow will
-turn to vmlinux or u-boot when opensbi ends.
-
-**Linux Kernel Payload**
-
-You can also choose to use Linux kernel as payload by enabling FW_PAYLOAD=y
-along with specifying FW_PAYLOAD_OFFSET. The kernel image will be embedded in
-the OPENSBI firmware binary, T-head will directly boot into Linux after OpenSBI.
diff --git a/platform/thead/c910/config.mk b/platform/thead/c910/config.mk
deleted file mode 100644
index bd5eab7..0000000
--- a/platform/thead/c910/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# SPDX-License-Identifier: BSD-2-Clause
-#
-
-# Compiler flags
-platform-cppflags-y =
-platform-cflags-y =
-platform-asflags-y =
-platform-ldflags-y =
-
-# Blobs to build
-FW_TEXT_START?=0x0
-FW_JUMP=y
-FW_JUMP_ADDR?=0x00200000
diff --git a/platform/thead/c910/objects.mk b/platform/thead/c910/objects.mk
deleted file mode 100644
index d025a36..0000000
--- a/platform/thead/c910/objects.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier: BSD-2-Clause
-#
-
-platform-objs-y += platform.o
diff --git a/platform/thead/c910/platform.c b/platform/thead/c910/platform.c
deleted file mode 100644
index dfa484a..0000000
--- a/platform/thead/c910/platform.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- */
-
-#include <sbi/riscv_encoding.h>
-#include <sbi/riscv_io.h>
-#include <sbi/sbi_console.h>
-#include <sbi/sbi_const.h>
-#include <sbi/sbi_hart.h>
-#include <sbi/sbi_platform.h>
-#include <sbi_utils/irqchip/plic.h>
-#include <sbi_utils/serial/uart8250.h>
-#include <sbi_utils/sys/clint.h>
-#include "platform.h"
-
-static struct c910_regs_struct c910_regs;
-
-static struct clint_data clint = {
- .addr = 0, /* Updated at cold boot time */
- .first_hartid = 0,
- .hart_count = C910_HART_COUNT,
- .has_64bit_mmio = FALSE,
-};
-
-static int c910_early_init(bool cold_boot)
-{
- if (cold_boot) {
- /* Load from boot core */
- c910_regs.pmpaddr0 = csr_read(CSR_PMPADDR0);
- c910_regs.pmpaddr1 = csr_read(CSR_PMPADDR1);
- c910_regs.pmpaddr2 = csr_read(CSR_PMPADDR2);
- c910_regs.pmpaddr3 = csr_read(CSR_PMPADDR3);
- c910_regs.pmpaddr4 = csr_read(CSR_PMPADDR4);
- c910_regs.pmpaddr5 = csr_read(CSR_PMPADDR5);
- c910_regs.pmpaddr6 = csr_read(CSR_PMPADDR6);
- c910_regs.pmpaddr7 = csr_read(CSR_PMPADDR7);
- c910_regs.pmpcfg0 = csr_read(CSR_PMPCFG0);
-
- c910_regs.mcor = csr_read(CSR_MCOR);
- c910_regs.mhcr = csr_read(CSR_MHCR);
- c910_regs.mccr2 = csr_read(CSR_MCCR2);
- c910_regs.mhint = csr_read(CSR_MHINT);
- c910_regs.mxstatus = csr_read(CSR_MXSTATUS);
-
- c910_regs.plic_base_addr = csr_read(CSR_PLIC_BASE);
- c910_regs.clint_base_addr =
- c910_regs.plic_base_addr + C910_PLIC_CLINT_OFFSET;
- } else {
- /* Store to other core */
- csr_write(CSR_PMPADDR0, c910_regs.pmpaddr0);
- csr_write(CSR_PMPADDR1, c910_regs.pmpaddr1);
- csr_write(CSR_PMPADDR2, c910_regs.pmpaddr2);
- csr_write(CSR_PMPADDR3, c910_regs.pmpaddr3);
- csr_write(CSR_PMPADDR4, c910_regs.pmpaddr4);
- csr_write(CSR_PMPADDR5, c910_regs.pmpaddr5);
- csr_write(CSR_PMPADDR6, c910_regs.pmpaddr6);
- csr_write(CSR_PMPADDR7, c910_regs.pmpaddr7);
- csr_write(CSR_PMPCFG0, c910_regs.pmpcfg0);
-
- csr_write(CSR_MCOR, c910_regs.mcor);
- csr_write(CSR_MHCR, c910_regs.mhcr);
- csr_write(CSR_MHINT, c910_regs.mhint);
- csr_write(CSR_MXSTATUS, c910_regs.mxstatus);
- }
-
- return 0;
-}
-
-static int c910_final_init(bool cold_boot)
-{
- return 0;
-}
-
-static int c910_irqchip_init(bool cold_boot)
-{
- /* Delegate plic enable into S-mode */
- writel(C910_PLIC_DELEG_ENABLE,
- (void *)c910_regs.plic_base_addr + C910_PLIC_DELEG_OFFSET);
-
- return 0;
-}
-
-static int c910_ipi_init(bool cold_boot)
-{
- int rc;
-
- if (cold_boot) {
- clint.addr = c910_regs.clint_base_addr;
- rc = clint_cold_ipi_init(&clint);
- if (rc)
- return rc;
- }
-
- return clint_warm_ipi_init();
-}
-
-static int c910_timer_init(bool cold_boot)
-{
- int ret;
-
- if (cold_boot) {
- clint.addr = c910_regs.clint_base_addr;
- ret = clint_cold_timer_init(&clint, NULL);
- if (ret)
- return ret;
- }
-
- return clint_warm_timer_init();
-}
-
-static int c910_system_reset_check(u32 type, u32 reason)
-{
- return 1;
-}
-
-static void c910_system_reset(u32 type, u32 reason)
-{
- asm volatile ("ebreak");
-}
-
-int c910_hart_start(u32 hartid, ulong saddr)
-{
- csr_write(CSR_MRVBR, saddr);
- csr_write(CSR_MRMR, csr_read(CSR_MRMR) | (1 << hartid));
-
- return 0;
-}
-
-const struct sbi_platform_operations platform_ops = {
- .early_init = c910_early_init,
- .final_init = c910_final_init,
-
- .irqchip_init = c910_irqchip_init,
-
- .ipi_init = c910_ipi_init,
- .ipi_send = clint_ipi_send,
- .ipi_clear = clint_ipi_clear,
-
- .timer_init = c910_timer_init,
- .timer_event_start = clint_timer_event_start,
-
- .system_reset_check = c910_system_reset_check,
- .system_reset = c910_system_reset,
-
- .hart_start = c910_hart_start,
-};
-
-const struct sbi_platform platform = {
- .opensbi_version = OPENSBI_VERSION,
- .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
- .name = "T-HEAD Xuantie c910",
- .features = SBI_THEAD_FEATURES,
- .hart_count = C910_HART_COUNT,
- .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
- .platform_ops_addr = (unsigned long)&platform_ops
-};
diff --git a/platform/thead/c910/platform.h b/platform/thead/c910/platform.h
deleted file mode 100644
index 354404e..0000000
--- a/platform/thead/c910/platform.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- */
-
-#ifndef _C910_PLATFORM_H_
-#define _C910_PLATFORM_H_
-
-#define C910_HART_COUNT 16
-
-#define SBI_THEAD_FEATURES \
- (SBI_PLATFORM_HAS_MFAULTS_DELEGATION | \
- SBI_PLATFORM_HAS_HART_SECONDARY_BOOT)
-
-#define CSR_MCOR 0x7c2
-#define CSR_MHCR 0x7c1
-#define CSR_MCCR2 0x7c3
-#define CSR_MHINT 0x7c5
-#define CSR_MXSTATUS 0x7c0
-#define CSR_PLIC_BASE 0xfc1
-#define CSR_MRMR 0x7c6
-#define CSR_MRVBR 0x7c7
-
-#define C910_PLIC_CLINT_OFFSET 0x04000000 /* 64M */
-#define C910_PLIC_DELEG_OFFSET 0x001ffffc
-#define C910_PLIC_DELEG_ENABLE 0x1
-
-struct c910_regs_struct {
- u64 pmpaddr0;
- u64 pmpaddr1;
- u64 pmpaddr2;
- u64 pmpaddr3;
- u64 pmpaddr4;
- u64 pmpaddr5;
- u64 pmpaddr6;
- u64 pmpaddr7;
- u64 pmpcfg0;
- u64 mcor;
- u64 mhcr;
- u64 mccr2;
- u64 mhint;
- u64 mxstatus;
- u64 plic_base_addr;
- u64 clint_base_addr;
-};
-
-#endif /* _C910_PLATFORM_H_ */
diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh
index c19af26..a8bd335 100755
--- a/scripts/create-binary-archive.sh
+++ b/scripts/create-binary-archive.sh
@@ -106,7 +106,6 @@ build_opensbi() {
BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
BUILD_PLATFORM_SUBDIR+=("andes/ae350")
- BUILD_PLATFORM_SUBDIR+=("thead/c910")
BUILD_PLATFORM_SUBDIR+=("generic")
;;
*)
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors
2021-04-24 2:01 [PATCH 1/2] platform: Remove platform/thead guoren
@ 2021-04-24 2:01 ` guoren
2021-04-25 4:50 ` Anup Patel
2021-04-25 4:48 ` [PATCH 1/2] platform: Remove platform/thead Anup Patel
1 sibling, 1 reply; 7+ messages in thread
From: guoren @ 2021-04-24 2:01 UTC (permalink / raw)
To: opensbi
From: Guo Ren <guoren@linux.alibaba.com>
Add description and dts examples for startup.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Anup Patel <anup.patel@wdc.com>
---
docs/platform/generic.md | 2 +
docs/platform/thead.md | 197 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 199 insertions(+)
create mode 100644 docs/platform/thead.md
diff --git a/docs/platform/generic.md b/docs/platform/generic.md
index f1f7f64..d09a5ee 100644
--- a/docs/platform/generic.md
+++ b/docs/platform/generic.md
@@ -48,7 +48,9 @@ RISC-V Platforms Using Generic Platform
* **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
* **Spike** (*[spike.md]*)
* **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
+* **T-HEAD C9xx series Processors** (*[thead.md]*)
[qemu_virt.md]: qemu_virt.md
[spike.md]: spike.md
[shakti_cclass.md]: shakti_cclass.md
+[thead.md]: thead.md
diff --git a/docs/platform/thead.md b/docs/platform/thead.md
new file mode 100644
index 0000000..932ca4b
--- /dev/null
+++ b/docs/platform/thead.md
@@ -0,0 +1,197 @@
+T-HEAD C9xx Series Processors
+=============================
+
+The **C9xx** series processors are high-performance RISC-V architecture
+multi-core processors with AI vector acceleration engine.
+
+For more details, refer [T-HEAD.CN](https://www.t-head.cn/)
+
+To build the platform-specific library and firmware images, provide the
+*PLATFORM=generic* parameter to the top level `make` command.
+
+Platform Options
+----------------
+
+The *T-HEAD C9xx* does not have any platform-specific compile options.
+
+CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y /usr/bin/make
+
+It depends on "riscv,clint0", "riscv,plic0", "thead,reset-sample" drivers.
+
+We recommend you use fw_dynamic for all platforms(qemu, sifive, spike, thead).
+
+DTS Example1: (Single core, eg: Allwinner D1 - c906)
+----------------------------------------------------
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ cpu at 0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcv";
+ mmu-type = "riscv,sv39";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ reset: reset-sample {
+ compatible = "thead,reset-sample";
+ plic-delegate = <0x0 0x101ffffc>;
+ };
+
+ clint0: clint at 14000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <
+ &cpu0_intc 3 &cpu0_intc 7
+ >;
+ reg = <0x0 0x14000000 0x0 0x04000000>;
+ clint,has-no-64bit-mmio;
+ };
+
+ intc: interrupt-controller at 10000000 {
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff &cpu0_intc 9
+ >;
+ reg = <0x0 0x10000000 0x0 0x04000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <200>;
+ };
+ }
+
+DTS Example2: (Multi cores with soc reset-regs)
+-----------------------------------------------
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ cpu at 0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu at 1 {
+ device_type = "cpu";
+ reg = <1>;
+ status = "fail";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu at 2 {
+ device_type = "cpu";
+ reg = <2>;
+ status = "fail";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu at 3 {
+ device_type = "cpu";
+ reg = <3>;
+ status = "fail";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ reset: reset-sample {
+ compatible = "thead,reset-sample";
+ plic-delegate = <0xff 0xd81ffffc>;
+ entry-reg = <0xff 0xff019050>;
+ entry-cnt = <4>;
+ control-reg = <0xff 0xff015004>;
+ control-val = <0x1c>;
+ csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+ };
+
+ clint0: clint at ffdc000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <
+ &cpu0_intc 3 &cpu0_intc 7
+ &cpu1_intc 3 &cpu1_intc 7
+ &cpu2_intc 3 &cpu2_intc 7
+ &cpu3_intc 3 &cpu3_intc 7
+ &cpu4_intc 3 &cpu4_intc 7
+ >;
+ reg = <0xff 0xdc000000 0x0 0x04000000>;
+ clint,has-no-64bit-mmio;
+ };
+
+ intc: interrupt-controller at ffd8000000 {
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff &cpu0_intc 9
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9
+ >;
+ reg = <0xff 0xd8000000 0x0 0x04000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <80>;
+ };
+ }
+
+DTS Example2: (Multi cores with old reset csrs)
+-----------------------------------------------
+
+reset: reset-sample {
+ compatible = "thead,reset-sample";
+ plic-delegate = <0xff 0xd81ffffc>;
+ using-csr-reset;
+ csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
+ 0x3b0 0x3b1 0x3b2 0x3b3
+ 0x3b4 0x3b5 0x3b6 0x3b7
+ 0x3a0>;
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 1/2] platform: Remove platform/thead
2021-04-24 2:01 [PATCH 1/2] platform: Remove platform/thead guoren
2021-04-24 2:01 ` [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors guoren
@ 2021-04-25 4:48 ` Anup Patel
1 sibling, 0 replies; 7+ messages in thread
From: Anup Patel @ 2021-04-25 4:48 UTC (permalink / raw)
To: opensbi
> -----Original Message-----
> From: guoren at kernel.org <guoren@kernel.org>
> Sent: 24 April 2021 07:31
> To: guoren at kernel.org; anup at brainfault.org
> Cc: opensbi at lists.infradead.org; Guo Ren <guoren@linux.alibaba.com>;
> Anup Patel <Anup.Patel@wdc.com>
> Subject: [PATCH 1/2] platform: Remove platform/thead
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> We could use platform/generic instead, and won't use it again.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Cc: Anup Patel <anup.patel@wdc.com>
Looks good to me.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Regards,
Anup
> ---
> docs/platform/platform.md | 3 -
> docs/platform/thead-c910.md | 34 ---------
> platform/thead/c910/config.mk | 14 ----
> platform/thead/c910/objects.mk | 5 --
> platform/thead/c910/platform.c | 156 ---------------------------------------
> platform/thead/c910/platform.h | 46 ------------
> scripts/create-binary-archive.sh | 1 -
> 7 files changed, 259 deletions(-)
> delete mode 100644 docs/platform/thead-c910.md delete mode 100644
> platform/thead/c910/config.mk delete mode 100644
> platform/thead/c910/objects.mk delete mode 100644
> platform/thead/c910/platform.c delete mode 100644
> platform/thead/c910/platform.h
>
> diff --git a/docs/platform/platform.md b/docs/platform/platform.md index
> 7f47068..b0cff37 100644
> --- a/docs/platform/platform.md
> +++ b/docs/platform/platform.md
> @@ -28,9 +28,6 @@ OpenSBI currently supports the following virtual and
> hardware platforms:
> * **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350).
> More
> details on this platform can be found in the file *[andes-ae350.md]*.
>
> -* **T-HEAD C910**: Platform support for the T-HEAD C910 Processor. More
> - details on this platform can be found in the file *[thead-c910.md]*.
> -
> * **Spike**: Platform support for the Spike emulator. More
> details on this platform can be found in the file *[spike.md]*.
>
> diff --git a/docs/platform/thead-c910.md b/docs/platform/thead-c910.md
> deleted file mode 100644 index 786b47d..0000000
> --- a/docs/platform/thead-c910.md
> +++ /dev/null
> @@ -1,34 +0,0 @@
> -T-HEAD C910 Processor
> -=====================
> -C910 is a 12-stage, 3 issues, 8 executions, out-of-order 64-bit RISC-V CPU
> which -supports 16 cores, runs with 2.5GHz, and is capable of running Linux.
> -
> -To build platform specific library and firmwares, provide the
> -*PLATFORM=thead/c910* parameter to the top level make command.
> -
> -Platform Options
> -----------------
> -
> -The *T-HEAD C910* platform does not have any platform-specific options.
> -
> -Building T-HEAD C910 Platform
> ------------------------------
> -
> -```
> -make PLATFORM=thead/c910
> -```
> -
> -Booting T-HEAD C910 Platform
> -----------------------------
> -
> -**No Payload**
> -
> -As there's no payload, you may download vmlinux or u-boot to
> FW_JUMP_ADDR which -specified in config.mk or compile commands with
> GDB. And the execution flow will -turn to vmlinux or u-boot when opensbi
> ends.
> -
> -**Linux Kernel Payload**
> -
> -You can also choose to use Linux kernel as payload by enabling
> FW_PAYLOAD=y -along with specifying FW_PAYLOAD_OFFSET. The kernel
> image will be embedded in -the OPENSBI firmware binary, T-head will
> directly boot into Linux after OpenSBI.
> diff --git a/platform/thead/c910/config.mk b/platform/thead/c910/config.mk
> deleted file mode 100644 index bd5eab7..0000000
> --- a/platform/thead/c910/config.mk
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -#
> -# SPDX-License-Identifier: BSD-2-Clause -#
> -
> -# Compiler flags
> -platform-cppflags-y =
> -platform-cflags-y =
> -platform-asflags-y =
> -platform-ldflags-y =
> -
> -# Blobs to build
> -FW_TEXT_START?=0x0
> -FW_JUMP=y
> -FW_JUMP_ADDR?=0x00200000
> diff --git a/platform/thead/c910/objects.mk
> b/platform/thead/c910/objects.mk deleted file mode 100644 index
> d025a36..0000000
> --- a/platform/thead/c910/objects.mk
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -#
> -# SPDX-License-Identifier: BSD-2-Clause -#
> -
> -platform-objs-y += platform.o
> diff --git a/platform/thead/c910/platform.c
> b/platform/thead/c910/platform.c deleted file mode 100644 index
> dfa484a..0000000
> --- a/platform/thead/c910/platform.c
> +++ /dev/null
> @@ -1,156 +0,0 @@
> -/*
> - * SPDX-License-Identifier: BSD-2-Clause
> - */
> -
> -#include <sbi/riscv_encoding.h>
> -#include <sbi/riscv_io.h>
> -#include <sbi/sbi_console.h>
> -#include <sbi/sbi_const.h>
> -#include <sbi/sbi_hart.h>
> -#include <sbi/sbi_platform.h>
> -#include <sbi_utils/irqchip/plic.h>
> -#include <sbi_utils/serial/uart8250.h>
> -#include <sbi_utils/sys/clint.h>
> -#include "platform.h"
> -
> -static struct c910_regs_struct c910_regs;
> -
> -static struct clint_data clint = {
> - .addr = 0, /* Updated at cold boot time */
> - .first_hartid = 0,
> - .hart_count = C910_HART_COUNT,
> - .has_64bit_mmio = FALSE,
> -};
> -
> -static int c910_early_init(bool cold_boot) -{
> - if (cold_boot) {
> - /* Load from boot core */
> - c910_regs.pmpaddr0 = csr_read(CSR_PMPADDR0);
> - c910_regs.pmpaddr1 = csr_read(CSR_PMPADDR1);
> - c910_regs.pmpaddr2 = csr_read(CSR_PMPADDR2);
> - c910_regs.pmpaddr3 = csr_read(CSR_PMPADDR3);
> - c910_regs.pmpaddr4 = csr_read(CSR_PMPADDR4);
> - c910_regs.pmpaddr5 = csr_read(CSR_PMPADDR5);
> - c910_regs.pmpaddr6 = csr_read(CSR_PMPADDR6);
> - c910_regs.pmpaddr7 = csr_read(CSR_PMPADDR7);
> - c910_regs.pmpcfg0 = csr_read(CSR_PMPCFG0);
> -
> - c910_regs.mcor = csr_read(CSR_MCOR);
> - c910_regs.mhcr = csr_read(CSR_MHCR);
> - c910_regs.mccr2 = csr_read(CSR_MCCR2);
> - c910_regs.mhint = csr_read(CSR_MHINT);
> - c910_regs.mxstatus = csr_read(CSR_MXSTATUS);
> -
> - c910_regs.plic_base_addr = csr_read(CSR_PLIC_BASE);
> - c910_regs.clint_base_addr =
> - c910_regs.plic_base_addr +
> C910_PLIC_CLINT_OFFSET;
> - } else {
> - /* Store to other core */
> - csr_write(CSR_PMPADDR0, c910_regs.pmpaddr0);
> - csr_write(CSR_PMPADDR1, c910_regs.pmpaddr1);
> - csr_write(CSR_PMPADDR2, c910_regs.pmpaddr2);
> - csr_write(CSR_PMPADDR3, c910_regs.pmpaddr3);
> - csr_write(CSR_PMPADDR4, c910_regs.pmpaddr4);
> - csr_write(CSR_PMPADDR5, c910_regs.pmpaddr5);
> - csr_write(CSR_PMPADDR6, c910_regs.pmpaddr6);
> - csr_write(CSR_PMPADDR7, c910_regs.pmpaddr7);
> - csr_write(CSR_PMPCFG0, c910_regs.pmpcfg0);
> -
> - csr_write(CSR_MCOR, c910_regs.mcor);
> - csr_write(CSR_MHCR, c910_regs.mhcr);
> - csr_write(CSR_MHINT, c910_regs.mhint);
> - csr_write(CSR_MXSTATUS, c910_regs.mxstatus);
> - }
> -
> - return 0;
> -}
> -
> -static int c910_final_init(bool cold_boot) -{
> - return 0;
> -}
> -
> -static int c910_irqchip_init(bool cold_boot) -{
> - /* Delegate plic enable into S-mode */
> - writel(C910_PLIC_DELEG_ENABLE,
> - (void *)c910_regs.plic_base_addr +
> C910_PLIC_DELEG_OFFSET);
> -
> - return 0;
> -}
> -
> -static int c910_ipi_init(bool cold_boot) -{
> - int rc;
> -
> - if (cold_boot) {
> - clint.addr = c910_regs.clint_base_addr;
> - rc = clint_cold_ipi_init(&clint);
> - if (rc)
> - return rc;
> - }
> -
> - return clint_warm_ipi_init();
> -}
> -
> -static int c910_timer_init(bool cold_boot) -{
> - int ret;
> -
> - if (cold_boot) {
> - clint.addr = c910_regs.clint_base_addr;
> - ret = clint_cold_timer_init(&clint, NULL);
> - if (ret)
> - return ret;
> - }
> -
> - return clint_warm_timer_init();
> -}
> -
> -static int c910_system_reset_check(u32 type, u32 reason) -{
> - return 1;
> -}
> -
> -static void c910_system_reset(u32 type, u32 reason) -{
> - asm volatile ("ebreak");
> -}
> -
> -int c910_hart_start(u32 hartid, ulong saddr) -{
> - csr_write(CSR_MRVBR, saddr);
> - csr_write(CSR_MRMR, csr_read(CSR_MRMR) | (1 << hartid));
> -
> - return 0;
> -}
> -
> -const struct sbi_platform_operations platform_ops = {
> - .early_init = c910_early_init,
> - .final_init = c910_final_init,
> -
> - .irqchip_init = c910_irqchip_init,
> -
> - .ipi_init = c910_ipi_init,
> - .ipi_send = clint_ipi_send,
> - .ipi_clear = clint_ipi_clear,
> -
> - .timer_init = c910_timer_init,
> - .timer_event_start = clint_timer_event_start,
> -
> - .system_reset_check = c910_system_reset_check,
> - .system_reset = c910_system_reset,
> -
> - .hart_start = c910_hart_start,
> -};
> -
> -const struct sbi_platform platform = {
> - .opensbi_version = OPENSBI_VERSION,
> - .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
> - .name = "T-HEAD Xuantie c910",
> - .features = SBI_THEAD_FEATURES,
> - .hart_count = C910_HART_COUNT,
> - .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
> - .platform_ops_addr = (unsigned long)&platform_ops
> -};
> diff --git a/platform/thead/c910/platform.h
> b/platform/thead/c910/platform.h deleted file mode 100644 index
> 354404e..0000000
> --- a/platform/thead/c910/platform.h
> +++ /dev/null
> @@ -1,46 +0,0 @@
> -/*
> - * SPDX-License-Identifier: BSD-2-Clause
> - */
> -
> -#ifndef _C910_PLATFORM_H_
> -#define _C910_PLATFORM_H_
> -
> -#define C910_HART_COUNT 16
> -
> -#define SBI_THEAD_FEATURES \
> - (SBI_PLATFORM_HAS_MFAULTS_DELEGATION | \
> - SBI_PLATFORM_HAS_HART_SECONDARY_BOOT)
> -
> -#define CSR_MCOR 0x7c2
> -#define CSR_MHCR 0x7c1
> -#define CSR_MCCR2 0x7c3
> -#define CSR_MHINT 0x7c5
> -#define CSR_MXSTATUS 0x7c0
> -#define CSR_PLIC_BASE 0xfc1
> -#define CSR_MRMR 0x7c6
> -#define CSR_MRVBR 0x7c7
> -
> -#define C910_PLIC_CLINT_OFFSET 0x04000000 /* 64M */
> -#define C910_PLIC_DELEG_OFFSET 0x001ffffc
> -#define C910_PLIC_DELEG_ENABLE 0x1
> -
> -struct c910_regs_struct {
> - u64 pmpaddr0;
> - u64 pmpaddr1;
> - u64 pmpaddr2;
> - u64 pmpaddr3;
> - u64 pmpaddr4;
> - u64 pmpaddr5;
> - u64 pmpaddr6;
> - u64 pmpaddr7;
> - u64 pmpcfg0;
> - u64 mcor;
> - u64 mhcr;
> - u64 mccr2;
> - u64 mhint;
> - u64 mxstatus;
> - u64 plic_base_addr;
> - u64 clint_base_addr;
> -};
> -
> -#endif /* _C910_PLATFORM_H_ */
> diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh
> index c19af26..a8bd335 100755
> --- a/scripts/create-binary-archive.sh
> +++ b/scripts/create-binary-archive.sh
> @@ -106,7 +106,6 @@ build_opensbi() {
> BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
> BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
> BUILD_PLATFORM_SUBDIR+=("andes/ae350")
> - BUILD_PLATFORM_SUBDIR+=("thead/c910")
> BUILD_PLATFORM_SUBDIR+=("generic")
> ;;
> *)
> --
> 2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors
2021-04-24 2:01 ` [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors guoren
@ 2021-04-25 4:50 ` Anup Patel
2021-04-25 7:42 ` Guo Ren
0 siblings, 1 reply; 7+ messages in thread
From: Anup Patel @ 2021-04-25 4:50 UTC (permalink / raw)
To: opensbi
> -----Original Message-----
> From: guoren at kernel.org <guoren@kernel.org>
> Sent: 24 April 2021 07:31
> To: guoren at kernel.org; anup at brainfault.org
> Cc: opensbi at lists.infradead.org; Guo Ren <guoren@linux.alibaba.com>;
> Anup Patel <Anup.Patel@wdc.com>
> Subject: [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Add description and dts examples for startup.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Cc: Anup Patel <anup.patel@wdc.com>
Rename thead.md to thead-c9xx.md to reflect processor family
name in MD filename.
Otherwise, looks good to me.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Regards,
Anup
> ---
> docs/platform/generic.md | 2 +
> docs/platform/thead.md | 197
> +++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 199 insertions(+)
> create mode 100644 docs/platform/thead.md
>
> diff --git a/docs/platform/generic.md b/docs/platform/generic.md index
> f1f7f64..d09a5ee 100644
> --- a/docs/platform/generic.md
> +++ b/docs/platform/generic.md
> @@ -48,7 +48,9 @@ RISC-V Platforms Using Generic Platform
> * **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
> * **Spike** (*[spike.md]*)
> * **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
> +* **T-HEAD C9xx series Processors** (*[thead.md]*)
>
> [qemu_virt.md]: qemu_virt.md
> [spike.md]: spike.md
> [shakti_cclass.md]: shakti_cclass.md
> +[thead.md]: thead.md
> diff --git a/docs/platform/thead.md b/docs/platform/thead.md new file
> mode 100644 index 0000000..932ca4b
> --- /dev/null
> +++ b/docs/platform/thead.md
> @@ -0,0 +1,197 @@
> +T-HEAD C9xx Series Processors
> +=============================
> +
> +The **C9xx** series processors are high-performance RISC-V architecture
> +multi-core processors with AI vector acceleration engine.
> +
> +For more details, refer [T-HEAD.CN](https://www.t-head.cn/)
> +
> +To build the platform-specific library and firmware images, provide the
> +*PLATFORM=generic* parameter to the top level `make` command.
> +
> +Platform Options
> +----------------
> +
> +The *T-HEAD C9xx* does not have any platform-specific compile options.
> +
> +CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y
> +/usr/bin/make
> +
> +It depends on "riscv,clint0", "riscv,plic0", "thead,reset-sample" drivers.
> +
> +We recommend you use fw_dynamic for all platforms(qemu, sifive, spike,
> thead).
> +
> +DTS Example1: (Single core, eg: Allwinner D1 - c906)
> +----------------------------------------------------
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <3000000>;
> + cpu at 0 {
> + device_type = "cpu";
> + reg = <0>;
> + status = "okay";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdcv";
> + mmu-type = "riscv,sv39";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + reset: reset-sample {
> + compatible = "thead,reset-sample";
> + plic-delegate = <0x0 0x101ffffc>;
> + };
> +
> + clint0: clint at 14000000 {
> + compatible = "riscv,clint0";
> + interrupts-extended = <
> + &cpu0_intc 3 &cpu0_intc 7
> + >;
> + reg = <0x0 0x14000000 0x0 0x04000000>;
> + clint,has-no-64bit-mmio;
> + };
> +
> + intc: interrupt-controller at 10000000 {
> + #interrupt-cells = <1>;
> + compatible = "riscv,plic0";
> + interrupt-controller;
> + interrupts-extended = <
> + &cpu0_intc 0xffffffff &cpu0_intc 9
> + >;
> + reg = <0x0 0x10000000 0x0 0x04000000>;
> + reg-names = "control";
> + riscv,max-priority = <7>;
> + riscv,ndev = <200>;
> + };
> + }
> +
> +DTS Example2: (Multi cores with soc reset-regs)
> +-----------------------------------------------
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <3000000>;
> + cpu at 0 {
> + device_type = "cpu";
> + reg = <0>;
> + status = "okay";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu at 1 {
> + device_type = "cpu";
> + reg = <1>;
> + status = "fail";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu at 2 {
> + device_type = "cpu";
> + reg = <2>;
> + status = "fail";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu at 3 {
> + device_type = "cpu";
> + reg = <3>;
> + status = "fail";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + cpu3_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + reset: reset-sample {
> + compatible = "thead,reset-sample";
> + plic-delegate = <0xff 0xd81ffffc>;
> + entry-reg = <0xff 0xff019050>;
> + entry-cnt = <4>;
> + control-reg = <0xff 0xff015004>;
> + control-val = <0x1c>;
> + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5
> 0x7cc>;
> + };
> +
> + clint0: clint at ffdc000000 {
> + compatible = "riscv,clint0";
> + interrupts-extended = <
> + &cpu0_intc 3 &cpu0_intc 7
> + &cpu1_intc 3 &cpu1_intc 7
> + &cpu2_intc 3 &cpu2_intc 7
> + &cpu3_intc 3 &cpu3_intc 7
> + &cpu4_intc 3 &cpu4_intc 7
> + >;
> + reg = <0xff 0xdc000000 0x0 0x04000000>;
> + clint,has-no-64bit-mmio;
> + };
> +
> + intc: interrupt-controller at ffd8000000 {
> + #interrupt-cells = <1>;
> + compatible = "riscv,plic0";
> + interrupt-controller;
> + interrupts-extended = <
> + &cpu0_intc 0xffffffff &cpu0_intc 9
> + &cpu1_intc 0xffffffff &cpu1_intc 9
> + &cpu2_intc 0xffffffff &cpu2_intc 9
> + &cpu3_intc 0xffffffff &cpu3_intc 9
> + >;
> + reg = <0xff 0xd8000000 0x0 0x04000000>;
> + reg-names = "control";
> + riscv,max-priority = <7>;
> + riscv,ndev = <80>;
> + };
> + }
> +
> +DTS Example2: (Multi cores with old reset csrs)
> +-----------------------------------------------
> +
> +reset: reset-sample {
> + compatible = "thead,reset-sample";
> + plic-delegate = <0xff 0xd81ffffc>;
> + using-csr-reset;
> + csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
> + 0x3b0 0x3b1 0x3b2 0x3b3
> + 0x3b4 0x3b5 0x3b6 0x3b7
> + 0x3a0>;
> +};
> --
> 2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors
2021-04-25 4:50 ` Anup Patel
@ 2021-04-25 7:42 ` Guo Ren
0 siblings, 0 replies; 7+ messages in thread
From: Guo Ren @ 2021-04-25 7:42 UTC (permalink / raw)
To: opensbi
On Sun, Apr 25, 2021 at 12:50 PM Anup Patel <Anup.Patel@wdc.com> wrote:
>
>
>
> > -----Original Message-----
> > From: guoren at kernel.org <guoren@kernel.org>
> > Sent: 24 April 2021 07:31
> > To: guoren at kernel.org; anup at brainfault.org
> > Cc: opensbi at lists.infradead.org; Guo Ren <guoren@linux.alibaba.com>;
> > Anup Patel <Anup.Patel@wdc.com>
> > Subject: [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors
> >
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > Add description and dts examples for startup.
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Cc: Anup Patel <anup.patel@wdc.com>
>
> Rename thead.md to thead-c9xx.md to reflect processor family
> name in MD filename.
Okay
>
> Otherwise, looks good to me.
>
> Reviewed-by: Anup Patel <anup.patel@wdc.com>
>
> Regards,
> Anup
>
> > ---
> > docs/platform/generic.md | 2 +
> > docs/platform/thead.md | 197
> > +++++++++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 199 insertions(+)
> > create mode 100644 docs/platform/thead.md
> >
> > diff --git a/docs/platform/generic.md b/docs/platform/generic.md index
> > f1f7f64..d09a5ee 100644
> > --- a/docs/platform/generic.md
> > +++ b/docs/platform/generic.md
> > @@ -48,7 +48,9 @@ RISC-V Platforms Using Generic Platform
> > * **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
> > * **Spike** (*[spike.md]*)
> > * **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
> > +* **T-HEAD C9xx series Processors** (*[thead.md]*)
> >
> > [qemu_virt.md]: qemu_virt.md
> > [spike.md]: spike.md
> > [shakti_cclass.md]: shakti_cclass.md
> > +[thead.md]: thead.md
> > diff --git a/docs/platform/thead.md b/docs/platform/thead.md new file
> > mode 100644 index 0000000..932ca4b
> > --- /dev/null
> > +++ b/docs/platform/thead.md
> > @@ -0,0 +1,197 @@
> > +T-HEAD C9xx Series Processors
> > +=============================
> > +
> > +The **C9xx** series processors are high-performance RISC-V architecture
> > +multi-core processors with AI vector acceleration engine.
> > +
> > +For more details, refer [T-HEAD.CN](https://www.t-head.cn/)
> > +
> > +To build the platform-specific library and firmware images, provide the
> > +*PLATFORM=generic* parameter to the top level `make` command.
> > +
> > +Platform Options
> > +----------------
> > +
> > +The *T-HEAD C9xx* does not have any platform-specific compile options.
> > +
> > +CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y
> > +/usr/bin/make
> > +
> > +It depends on "riscv,clint0", "riscv,plic0", "thead,reset-sample" drivers.
> > +
> > +We recommend you use fw_dynamic for all platforms(qemu, sifive, spike,
> > thead).
> > +
> > +DTS Example1: (Single core, eg: Allwinner D1 - c906)
> > +----------------------------------------------------
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <3000000>;
> > + cpu at 0 {
> > + device_type = "cpu";
> > + reg = <0>;
> > + status = "okay";
> > + compatible = "riscv";
> > + riscv,isa = "rv64imafdcv";
> > + mmu-type = "riscv,sv39";
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + compatible = "simple-bus";
> > + ranges;
> > +
> > + reset: reset-sample {
> > + compatible = "thead,reset-sample";
> > + plic-delegate = <0x0 0x101ffffc>;
> > + };
> > +
> > + clint0: clint at 14000000 {
> > + compatible = "riscv,clint0";
> > + interrupts-extended = <
> > + &cpu0_intc 3 &cpu0_intc 7
> > + >;
> > + reg = <0x0 0x14000000 0x0 0x04000000>;
> > + clint,has-no-64bit-mmio;
> > + };
> > +
> > + intc: interrupt-controller at 10000000 {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,plic0";
> > + interrupt-controller;
> > + interrupts-extended = <
> > + &cpu0_intc 0xffffffff &cpu0_intc 9
> > + >;
> > + reg = <0x0 0x10000000 0x0 0x04000000>;
> > + reg-names = "control";
> > + riscv,max-priority = <7>;
> > + riscv,ndev = <200>;
> > + };
> > + }
> > +
> > +DTS Example2: (Multi cores with soc reset-regs)
> > +-----------------------------------------------
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <3000000>;
> > + cpu at 0 {
> > + device_type = "cpu";
> > + reg = <0>;
> > + status = "okay";
> > + compatible = "riscv";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu at 1 {
> > + device_type = "cpu";
> > + reg = <1>;
> > + status = "fail";
> > + compatible = "riscv";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + cpu1_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu at 2 {
> > + device_type = "cpu";
> > + reg = <2>;
> > + status = "fail";
> > + compatible = "riscv";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + cpu2_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu at 3 {
> > + device_type = "cpu";
> > + reg = <3>;
> > + status = "fail";
> > + compatible = "riscv";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + cpu3_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + compatible = "simple-bus";
> > + ranges;
> > +
> > + reset: reset-sample {
> > + compatible = "thead,reset-sample";
> > + plic-delegate = <0xff 0xd81ffffc>;
> > + entry-reg = <0xff 0xff019050>;
> > + entry-cnt = <4>;
> > + control-reg = <0xff 0xff015004>;
> > + control-val = <0x1c>;
> > + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5
> > 0x7cc>;
> > + };
> > +
> > + clint0: clint at ffdc000000 {
> > + compatible = "riscv,clint0";
> > + interrupts-extended = <
> > + &cpu0_intc 3 &cpu0_intc 7
> > + &cpu1_intc 3 &cpu1_intc 7
> > + &cpu2_intc 3 &cpu2_intc 7
> > + &cpu3_intc 3 &cpu3_intc 7
> > + &cpu4_intc 3 &cpu4_intc 7
> > + >;
> > + reg = <0xff 0xdc000000 0x0 0x04000000>;
> > + clint,has-no-64bit-mmio;
> > + };
> > +
> > + intc: interrupt-controller at ffd8000000 {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,plic0";
> > + interrupt-controller;
> > + interrupts-extended = <
> > + &cpu0_intc 0xffffffff &cpu0_intc 9
> > + &cpu1_intc 0xffffffff &cpu1_intc 9
> > + &cpu2_intc 0xffffffff &cpu2_intc 9
> > + &cpu3_intc 0xffffffff &cpu3_intc 9
> > + >;
> > + reg = <0xff 0xd8000000 0x0 0x04000000>;
> > + reg-names = "control";
> > + riscv,max-priority = <7>;
> > + riscv,ndev = <80>;
> > + };
> > + }
> > +
> > +DTS Example2: (Multi cores with old reset csrs)
> > +-----------------------------------------------
> > +
> > +reset: reset-sample {
> > + compatible = "thead,reset-sample";
> > + plic-delegate = <0xff 0xd81ffffc>;
> > + using-csr-reset;
> > + csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
> > + 0x3b0 0x3b1 0x3b2 0x3b3
> > + 0x3b4 0x3b5 0x3b6 0x3b7
> > + 0x3a0>;
> > +};
> > --
> > 2.7.4
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors
2021-04-27 6:47 guoren
@ 2021-04-27 6:47 ` guoren
2021-04-28 10:46 ` Anup Patel
0 siblings, 1 reply; 7+ messages in thread
From: guoren @ 2021-04-27 6:47 UTC (permalink / raw)
To: opensbi
From: Guo Ren <guoren@linux.alibaba.com>
Add description and dts examples for startup.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
docs/platform/generic.md | 2 +
docs/platform/thead-c9xx.md | 197 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 199 insertions(+)
create mode 100644 docs/platform/thead-c9xx.md
diff --git a/docs/platform/generic.md b/docs/platform/generic.md
index f1f7f64..8c3b0dd 100644
--- a/docs/platform/generic.md
+++ b/docs/platform/generic.md
@@ -48,7 +48,9 @@ RISC-V Platforms Using Generic Platform
* **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
* **Spike** (*[spike.md]*)
* **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
+* **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
[qemu_virt.md]: qemu_virt.md
[spike.md]: spike.md
[shakti_cclass.md]: shakti_cclass.md
+[thead-c9xx.md]: thead-c9xx.md
diff --git a/docs/platform/thead-c9xx.md b/docs/platform/thead-c9xx.md
new file mode 100644
index 0000000..932ca4b
--- /dev/null
+++ b/docs/platform/thead-c9xx.md
@@ -0,0 +1,197 @@
+T-HEAD C9xx Series Processors
+=============================
+
+The **C9xx** series processors are high-performance RISC-V architecture
+multi-core processors with AI vector acceleration engine.
+
+For more details, refer [T-HEAD.CN](https://www.t-head.cn/)
+
+To build the platform-specific library and firmware images, provide the
+*PLATFORM=generic* parameter to the top level `make` command.
+
+Platform Options
+----------------
+
+The *T-HEAD C9xx* does not have any platform-specific compile options.
+
+CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y /usr/bin/make
+
+It depends on "riscv,clint0", "riscv,plic0", "thead,reset-sample" drivers.
+
+We recommend you use fw_dynamic for all platforms(qemu, sifive, spike, thead).
+
+DTS Example1: (Single core, eg: Allwinner D1 - c906)
+----------------------------------------------------
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ cpu at 0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcv";
+ mmu-type = "riscv,sv39";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ reset: reset-sample {
+ compatible = "thead,reset-sample";
+ plic-delegate = <0x0 0x101ffffc>;
+ };
+
+ clint0: clint at 14000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <
+ &cpu0_intc 3 &cpu0_intc 7
+ >;
+ reg = <0x0 0x14000000 0x0 0x04000000>;
+ clint,has-no-64bit-mmio;
+ };
+
+ intc: interrupt-controller at 10000000 {
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff &cpu0_intc 9
+ >;
+ reg = <0x0 0x10000000 0x0 0x04000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <200>;
+ };
+ }
+
+DTS Example2: (Multi cores with soc reset-regs)
+-----------------------------------------------
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ cpu at 0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu at 1 {
+ device_type = "cpu";
+ reg = <1>;
+ status = "fail";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu at 2 {
+ device_type = "cpu";
+ reg = <2>;
+ status = "fail";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu at 3 {
+ device_type = "cpu";
+ reg = <3>;
+ status = "fail";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ reset: reset-sample {
+ compatible = "thead,reset-sample";
+ plic-delegate = <0xff 0xd81ffffc>;
+ entry-reg = <0xff 0xff019050>;
+ entry-cnt = <4>;
+ control-reg = <0xff 0xff015004>;
+ control-val = <0x1c>;
+ csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+ };
+
+ clint0: clint at ffdc000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <
+ &cpu0_intc 3 &cpu0_intc 7
+ &cpu1_intc 3 &cpu1_intc 7
+ &cpu2_intc 3 &cpu2_intc 7
+ &cpu3_intc 3 &cpu3_intc 7
+ &cpu4_intc 3 &cpu4_intc 7
+ >;
+ reg = <0xff 0xdc000000 0x0 0x04000000>;
+ clint,has-no-64bit-mmio;
+ };
+
+ intc: interrupt-controller at ffd8000000 {
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff &cpu0_intc 9
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9
+ >;
+ reg = <0xff 0xd8000000 0x0 0x04000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <80>;
+ };
+ }
+
+DTS Example2: (Multi cores with old reset csrs)
+-----------------------------------------------
+
+reset: reset-sample {
+ compatible = "thead,reset-sample";
+ plic-delegate = <0xff 0xd81ffffc>;
+ using-csr-reset;
+ csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
+ 0x3b0 0x3b1 0x3b2 0x3b3
+ 0x3b4 0x3b5 0x3b6 0x3b7
+ 0x3a0>;
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors
2021-04-27 6:47 ` [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors guoren
@ 2021-04-28 10:46 ` Anup Patel
0 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2021-04-28 10:46 UTC (permalink / raw)
To: opensbi
> -----Original Message-----
> From: opensbi <opensbi-bounces@lists.infradead.org> On Behalf Of
> guoren at kernel.org
> Sent: 27 April 2021 12:18
> To: guoren at kernel.org; anup at brainfault.org
> Cc: opensbi at lists.infradead.org; Guo Ren <guoren@linux.alibaba.com>
> Subject: [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Add description and dts examples for startup.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Reviewed-by: Anup Patel <anup.patel@wdc.com>
I did some minor fixes in thead-c9xx.md at time of merging.
Applied this patch to the riscv/opensbi repo
Thanks,
Anup
> ---
> docs/platform/generic.md | 2 +
> docs/platform/thead-c9xx.md | 197
> ++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 199 insertions(+)
> create mode 100644 docs/platform/thead-c9xx.md
>
> diff --git a/docs/platform/generic.md b/docs/platform/generic.md index
> f1f7f64..8c3b0dd 100644
> --- a/docs/platform/generic.md
> +++ b/docs/platform/generic.md
> @@ -48,7 +48,9 @@ RISC-V Platforms Using Generic Platform
> * **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
> * **Spike** (*[spike.md]*)
> * **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
> +* **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
>
> [qemu_virt.md]: qemu_virt.md
> [spike.md]: spike.md
> [shakti_cclass.md]: shakti_cclass.md
> +[thead-c9xx.md]: thead-c9xx.md
> diff --git a/docs/platform/thead-c9xx.md b/docs/platform/thead-c9xx.md
> new file mode 100644 index 0000000..932ca4b
> --- /dev/null
> +++ b/docs/platform/thead-c9xx.md
> @@ -0,0 +1,197 @@
> +T-HEAD C9xx Series Processors
> +=============================
> +
> +The **C9xx** series processors are high-performance RISC-V architecture
> +multi-core processors with AI vector acceleration engine.
> +
> +For more details, refer [T-HEAD.CN](https://www.t-head.cn/)
> +
> +To build the platform-specific library and firmware images, provide the
> +*PLATFORM=generic* parameter to the top level `make` command.
> +
> +Platform Options
> +----------------
> +
> +The *T-HEAD C9xx* does not have any platform-specific compile options.
> +
> +CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y
> +/usr/bin/make
> +
> +It depends on "riscv,clint0", "riscv,plic0", "thead,reset-sample" drivers.
> +
> +We recommend you use fw_dynamic for all platforms(qemu, sifive, spike,
> thead).
> +
> +DTS Example1: (Single core, eg: Allwinner D1 - c906)
> +----------------------------------------------------
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <3000000>;
> + cpu at 0 {
> + device_type = "cpu";
> + reg = <0>;
> + status = "okay";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdcv";
> + mmu-type = "riscv,sv39";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + reset: reset-sample {
> + compatible = "thead,reset-sample";
> + plic-delegate = <0x0 0x101ffffc>;
> + };
> +
> + clint0: clint at 14000000 {
> + compatible = "riscv,clint0";
> + interrupts-extended = <
> + &cpu0_intc 3 &cpu0_intc 7
> + >;
> + reg = <0x0 0x14000000 0x0 0x04000000>;
> + clint,has-no-64bit-mmio;
> + };
> +
> + intc: interrupt-controller at 10000000 {
> + #interrupt-cells = <1>;
> + compatible = "riscv,plic0";
> + interrupt-controller;
> + interrupts-extended = <
> + &cpu0_intc 0xffffffff &cpu0_intc 9
> + >;
> + reg = <0x0 0x10000000 0x0 0x04000000>;
> + reg-names = "control";
> + riscv,max-priority = <7>;
> + riscv,ndev = <200>;
> + };
> + }
> +
> +DTS Example2: (Multi cores with soc reset-regs)
> +-----------------------------------------------
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <3000000>;
> + cpu at 0 {
> + device_type = "cpu";
> + reg = <0>;
> + status = "okay";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu at 1 {
> + device_type = "cpu";
> + reg = <1>;
> + status = "fail";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu at 2 {
> + device_type = "cpu";
> + reg = <2>;
> + status = "fail";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu at 3 {
> + device_type = "cpu";
> + reg = <3>;
> + status = "fail";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + cpu3_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + reset: reset-sample {
> + compatible = "thead,reset-sample";
> + plic-delegate = <0xff 0xd81ffffc>;
> + entry-reg = <0xff 0xff019050>;
> + entry-cnt = <4>;
> + control-reg = <0xff 0xff015004>;
> + control-val = <0x1c>;
> + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5
> 0x7cc>;
> + };
> +
> + clint0: clint at ffdc000000 {
> + compatible = "riscv,clint0";
> + interrupts-extended = <
> + &cpu0_intc 3 &cpu0_intc 7
> + &cpu1_intc 3 &cpu1_intc 7
> + &cpu2_intc 3 &cpu2_intc 7
> + &cpu3_intc 3 &cpu3_intc 7
> + &cpu4_intc 3 &cpu4_intc 7
> + >;
> + reg = <0xff 0xdc000000 0x0 0x04000000>;
> + clint,has-no-64bit-mmio;
> + };
> +
> + intc: interrupt-controller at ffd8000000 {
> + #interrupt-cells = <1>;
> + compatible = "riscv,plic0";
> + interrupt-controller;
> + interrupts-extended = <
> + &cpu0_intc 0xffffffff &cpu0_intc 9
> + &cpu1_intc 0xffffffff &cpu1_intc 9
> + &cpu2_intc 0xffffffff &cpu2_intc 9
> + &cpu3_intc 0xffffffff &cpu3_intc 9
> + >;
> + reg = <0xff 0xd8000000 0x0 0x04000000>;
> + reg-names = "control";
> + riscv,max-priority = <7>;
> + riscv,ndev = <80>;
> + };
> + }
> +
> +DTS Example2: (Multi cores with old reset csrs)
> +-----------------------------------------------
> +
> +reset: reset-sample {
> + compatible = "thead,reset-sample";
> + plic-delegate = <0xff 0xd81ffffc>;
> + using-csr-reset;
> + csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
> + 0x3b0 0x3b1 0x3b2 0x3b3
> + 0x3b4 0x3b5 0x3b6 0x3b7
> + 0x3a0>;
> +};
> --
> 2.7.4
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 7+ messages in thread
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2021-04-24 2:01 [PATCH 1/2] platform: Remove platform/thead guoren
2021-04-24 2:01 ` [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors guoren
2021-04-25 4:50 ` Anup Patel
2021-04-25 7:42 ` Guo Ren
2021-04-25 4:48 ` [PATCH 1/2] platform: Remove platform/thead Anup Patel
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2021-04-27 6:47 guoren
2021-04-27 6:47 ` [PATCH 2/2] doc: generic: Add T-HEAD C9xx series processors guoren
2021-04-28 10:46 ` Anup Patel
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