* [PATCH] gpio/starfive: add gpio driver and support gpio reset
@ 2023-02-16 9:21 minda.chen
2023-02-27 6:44 ` Anup Patel
2023-03-01 3:47 ` Anup Patel
0 siblings, 2 replies; 6+ messages in thread
From: minda.chen @ 2023-02-16 9:21 UTC (permalink / raw)
To: opensbi
Add gpio driver and gpio reset function in Starfive
JH7110 SOC platform.
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
---
lib/utils/gpio/Kconfig | 3 +
lib/utils/gpio/fdt_gpio_starfive.c | 117 +++++++++++++++++++++++++++++
lib/utils/gpio/objects.mk | 3 +
platform/generic/configs/defconfig | 1 +
4 files changed, 124 insertions(+)
create mode 100644 lib/utils/gpio/fdt_gpio_starfive.c
diff --git a/lib/utils/gpio/Kconfig b/lib/utils/gpio/Kconfig
index 38a9d75..1b338a6 100644
--- a/lib/utils/gpio/Kconfig
+++ b/lib/utils/gpio/Kconfig
@@ -14,6 +14,9 @@ config FDT_GPIO_SIFIVE
bool "SiFive GPIO FDT driver"
default n
+config FDT_GPIO_STARFIVE
+ bool "StarFive GPIO FDT driver"
+ default n
endif
config GPIO
diff --git a/lib/utils/gpio/fdt_gpio_starfive.c b/lib/utils/gpio/fdt_gpio_starfive.c
new file mode 100644
index 0000000..18cca72
--- /dev/null
+++ b/lib/utils/gpio/fdt_gpio_starfive.c
@@ -0,0 +1,117 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Starfive
+ *
+ * Authors:
+ * Minda.chen <Minda.chen@starfivetech.com>
+ */
+
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_console.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/gpio/fdt_gpio.h>
+
+#define STARFIVE_GPIO_CHIP_MAX 2
+#define STARFIVE_GPIO_PINS_DEF 64
+#define STARFIVE_GPIO_OUTVAL 0x40
+#define STARFIVE_GPIO_MASK 0xff
+#define STARFIVE_GPIO_REG_SHIFT_MASK 0x3
+#define STARFIVE_GPIO_SHIFT_BITS 0x3
+
+struct starfive_gpio_chip {
+ unsigned long addr;
+ struct gpio_chip chip;
+};
+
+static unsigned int starfive_gpio_chip_count;
+static struct starfive_gpio_chip starfive_gpio_chip_array[STARFIVE_GPIO_CHIP_MAX];
+
+static int starfive_gpio_direction_output(struct gpio_pin *gp, int value)
+{
+ u32 val;
+ unsigned long reg_addr;
+ u32 bit_mask, shift_bits;
+ struct starfive_gpio_chip *chip =
+ container_of(gp->chip, struct starfive_gpio_chip, chip);
+
+ /* set out en*/
+ reg_addr = chip->addr + gp->offset;
+ reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
+
+ val = readl((void *)(reg_addr));
+ shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
+ << STARFIVE_GPIO_SHIFT_BITS;
+ bit_mask = STARFIVE_GPIO_MASK << shift_bits;
+
+ val = readl((void *)reg_addr);
+ val &= ~bit_mask;
+ writel(val, (void *)reg_addr);
+
+ return 0;
+}
+
+static void starfive_gpio_set(struct gpio_pin *gp, int value)
+{
+ u32 val;
+ unsigned long reg_addr;
+ u32 bit_mask, shift_bits;
+ struct starfive_gpio_chip *chip =
+ container_of(gp->chip, struct starfive_gpio_chip, chip);
+
+ reg_addr = chip->addr + gp->offset;
+ reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
+
+ shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
+ << STARFIVE_GPIO_SHIFT_BITS;
+ bit_mask = STARFIVE_GPIO_MASK << shift_bits;
+ /* set output value */
+ val = readl((void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
+ val &= ~bit_mask;
+ val |= value << shift_bits;
+ writel(val, (void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
+}
+
+extern struct fdt_gpio fdt_gpio_starfive;
+
+static int starfive_gpio_init(void *fdt, int nodeoff, u32 phandle,
+ const struct fdt_match *match)
+{
+ int rc;
+ struct starfive_gpio_chip *chip;
+ u64 addr;
+
+ if (starfive_gpio_chip_count >= STARFIVE_GPIO_CHIP_MAX)
+ return SBI_ENOSPC;
+ chip = &starfive_gpio_chip_array[starfive_gpio_chip_count];
+
+ rc = fdt_get_node_addr_size(fdt, nodeoff, 0, &addr, NULL);
+ if (rc)
+ return rc;
+
+ chip->addr = addr;
+ chip->chip.driver = &fdt_gpio_starfive;
+ chip->chip.id = phandle;
+ chip->chip.ngpio = STARFIVE_GPIO_PINS_DEF;
+ chip->chip.direction_output = starfive_gpio_direction_output;
+ chip->chip.set = starfive_gpio_set;
+ rc = gpio_chip_add(&chip->chip);
+ if (rc)
+ return rc;
+
+ starfive_gpio_chip_count++;
+ return 0;
+}
+
+static const struct fdt_match starfive_gpio_match[] = {
+ { .compatible = "starfive,jh7110-sys-pinctrl" },
+ { .compatible = "starfive,iomux-pinctrl" },
+ { },
+};
+
+struct fdt_gpio fdt_gpio_starfive = {
+ .match_table = starfive_gpio_match,
+ .xlate = fdt_gpio_simple_xlate,
+ .init = starfive_gpio_init,
+};
diff --git a/lib/utils/gpio/objects.mk b/lib/utils/gpio/objects.mk
index eedd699..8f4a6a8 100644
--- a/lib/utils/gpio/objects.mk
+++ b/lib/utils/gpio/objects.mk
@@ -13,4 +13,7 @@ libsbiutils-objs-$(CONFIG_FDT_GPIO) += gpio/fdt_gpio_drivers.o
carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_SIFIVE) += fdt_gpio_sifive
libsbiutils-objs-$(CONFIG_FDT_GPIO_SIFIVE) += gpio/fdt_gpio_sifive.o
+carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_STARFIVE) += fdt_gpio_starfive
+libsbiutils-objs-$(CONFIG_FDT_GPIO_STARFIVE) += gpio/fdt_gpio_starfive.o
+
libsbiutils-objs-$(CONFIG_GPIO) += gpio/gpio.o
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index 4b0842e..2ad953d 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -6,6 +6,7 @@ CONFIG_PLATFORM_SIFIVE_FU740=y
CONFIG_PLATFORM_STARFIVE_JH7110=y
CONFIG_FDT_GPIO=y
CONFIG_FDT_GPIO_SIFIVE=y
+CONFIG_FDT_GPIO_STARFIVE=y
CONFIG_FDT_I2C=y
CONFIG_FDT_I2C_SIFIVE=y
CONFIG_FDT_IPI=y
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] gpio/starfive: add gpio driver and support gpio reset
2023-02-16 9:21 [PATCH] gpio/starfive: add gpio driver and support gpio reset minda.chen
@ 2023-02-27 6:44 ` Anup Patel
2023-02-27 11:23 ` Minda Chen
2023-03-01 3:47 ` Anup Patel
1 sibling, 1 reply; 6+ messages in thread
From: Anup Patel @ 2023-02-27 6:44 UTC (permalink / raw)
To: opensbi
On Thu, Feb 16, 2023 at 2:52 PM minda.chen <minda.chen@starfivetech.com> wrote:
>
> Add gpio driver and gpio reset function in Starfive
> JH7110 SOC platform.
>
> Signed-off-by: minda.chen <minda.chen@starfivetech.com>
I don't see a PATCH enabling it in defconfig.
How is this driver used in OpenSBI ?
Regards,
Anup
> ---
> lib/utils/gpio/Kconfig | 3 +
> lib/utils/gpio/fdt_gpio_starfive.c | 117 +++++++++++++++++++++++++++++
> lib/utils/gpio/objects.mk | 3 +
> platform/generic/configs/defconfig | 1 +
> 4 files changed, 124 insertions(+)
> create mode 100644 lib/utils/gpio/fdt_gpio_starfive.c
>
> diff --git a/lib/utils/gpio/Kconfig b/lib/utils/gpio/Kconfig
> index 38a9d75..1b338a6 100644
> --- a/lib/utils/gpio/Kconfig
> +++ b/lib/utils/gpio/Kconfig
> @@ -14,6 +14,9 @@ config FDT_GPIO_SIFIVE
> bool "SiFive GPIO FDT driver"
> default n
>
> +config FDT_GPIO_STARFIVE
> + bool "StarFive GPIO FDT driver"
> + default n
> endif
>
> config GPIO
> diff --git a/lib/utils/gpio/fdt_gpio_starfive.c b/lib/utils/gpio/fdt_gpio_starfive.c
> new file mode 100644
> index 0000000..18cca72
> --- /dev/null
> +++ b/lib/utils/gpio/fdt_gpio_starfive.c
> @@ -0,0 +1,117 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Starfive
> + *
> + * Authors:
> + * Minda.chen <Minda.chen@starfivetech.com>
> + */
> +
> +#include <sbi/riscv_io.h>
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +#include <sbi_utils/gpio/fdt_gpio.h>
> +
> +#define STARFIVE_GPIO_CHIP_MAX 2
> +#define STARFIVE_GPIO_PINS_DEF 64
> +#define STARFIVE_GPIO_OUTVAL 0x40
> +#define STARFIVE_GPIO_MASK 0xff
> +#define STARFIVE_GPIO_REG_SHIFT_MASK 0x3
> +#define STARFIVE_GPIO_SHIFT_BITS 0x3
> +
> +struct starfive_gpio_chip {
> + unsigned long addr;
> + struct gpio_chip chip;
> +};
> +
> +static unsigned int starfive_gpio_chip_count;
> +static struct starfive_gpio_chip starfive_gpio_chip_array[STARFIVE_GPIO_CHIP_MAX];
> +
> +static int starfive_gpio_direction_output(struct gpio_pin *gp, int value)
> +{
> + u32 val;
> + unsigned long reg_addr;
> + u32 bit_mask, shift_bits;
> + struct starfive_gpio_chip *chip =
> + container_of(gp->chip, struct starfive_gpio_chip, chip);
> +
> + /* set out en*/
> + reg_addr = chip->addr + gp->offset;
> + reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
> +
> + val = readl((void *)(reg_addr));
> + shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
> + << STARFIVE_GPIO_SHIFT_BITS;
> + bit_mask = STARFIVE_GPIO_MASK << shift_bits;
> +
> + val = readl((void *)reg_addr);
> + val &= ~bit_mask;
> + writel(val, (void *)reg_addr);
> +
> + return 0;
> +}
> +
> +static void starfive_gpio_set(struct gpio_pin *gp, int value)
> +{
> + u32 val;
> + unsigned long reg_addr;
> + u32 bit_mask, shift_bits;
> + struct starfive_gpio_chip *chip =
> + container_of(gp->chip, struct starfive_gpio_chip, chip);
> +
> + reg_addr = chip->addr + gp->offset;
> + reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
> +
> + shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
> + << STARFIVE_GPIO_SHIFT_BITS;
> + bit_mask = STARFIVE_GPIO_MASK << shift_bits;
> + /* set output value */
> + val = readl((void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
> + val &= ~bit_mask;
> + val |= value << shift_bits;
> + writel(val, (void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
> +}
> +
> +extern struct fdt_gpio fdt_gpio_starfive;
> +
> +static int starfive_gpio_init(void *fdt, int nodeoff, u32 phandle,
> + const struct fdt_match *match)
> +{
> + int rc;
> + struct starfive_gpio_chip *chip;
> + u64 addr;
> +
> + if (starfive_gpio_chip_count >= STARFIVE_GPIO_CHIP_MAX)
> + return SBI_ENOSPC;
> + chip = &starfive_gpio_chip_array[starfive_gpio_chip_count];
> +
> + rc = fdt_get_node_addr_size(fdt, nodeoff, 0, &addr, NULL);
> + if (rc)
> + return rc;
> +
> + chip->addr = addr;
> + chip->chip.driver = &fdt_gpio_starfive;
> + chip->chip.id = phandle;
> + chip->chip.ngpio = STARFIVE_GPIO_PINS_DEF;
> + chip->chip.direction_output = starfive_gpio_direction_output;
> + chip->chip.set = starfive_gpio_set;
> + rc = gpio_chip_add(&chip->chip);
> + if (rc)
> + return rc;
> +
> + starfive_gpio_chip_count++;
> + return 0;
> +}
> +
> +static const struct fdt_match starfive_gpio_match[] = {
> + { .compatible = "starfive,jh7110-sys-pinctrl" },
> + { .compatible = "starfive,iomux-pinctrl" },
> + { },
> +};
> +
> +struct fdt_gpio fdt_gpio_starfive = {
> + .match_table = starfive_gpio_match,
> + .xlate = fdt_gpio_simple_xlate,
> + .init = starfive_gpio_init,
> +};
> diff --git a/lib/utils/gpio/objects.mk b/lib/utils/gpio/objects.mk
> index eedd699..8f4a6a8 100644
> --- a/lib/utils/gpio/objects.mk
> +++ b/lib/utils/gpio/objects.mk
> @@ -13,4 +13,7 @@ libsbiutils-objs-$(CONFIG_FDT_GPIO) += gpio/fdt_gpio_drivers.o
> carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_SIFIVE) += fdt_gpio_sifive
> libsbiutils-objs-$(CONFIG_FDT_GPIO_SIFIVE) += gpio/fdt_gpio_sifive.o
>
> +carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_STARFIVE) += fdt_gpio_starfive
> +libsbiutils-objs-$(CONFIG_FDT_GPIO_STARFIVE) += gpio/fdt_gpio_starfive.o
> +
> libsbiutils-objs-$(CONFIG_GPIO) += gpio/gpio.o
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index 4b0842e..2ad953d 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -6,6 +6,7 @@ CONFIG_PLATFORM_SIFIVE_FU740=y
> CONFIG_PLATFORM_STARFIVE_JH7110=y
> CONFIG_FDT_GPIO=y
> CONFIG_FDT_GPIO_SIFIVE=y
> +CONFIG_FDT_GPIO_STARFIVE=y
> CONFIG_FDT_I2C=y
> CONFIG_FDT_I2C_SIFIVE=y
> CONFIG_FDT_IPI=y
> --
> 2.17.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] gpio/starfive: add gpio driver and support gpio reset
2023-02-27 6:44 ` Anup Patel
@ 2023-02-27 11:23 ` Minda Chen
2023-02-27 14:00 ` Anup Patel
0 siblings, 1 reply; 6+ messages in thread
From: Minda Chen @ 2023-02-27 11:23 UTC (permalink / raw)
To: opensbi
On 2023/2/27 14:44, Anup Patel wrote:
> On Thu, Feb 16, 2023 at 2:52 PM minda.chen <minda.chen@starfivetech.com> wrote:
>>
>> Add gpio driver and gpio reset function in Starfive
>> JH7110 SOC platform.
>>
>> Signed-off-by: minda.chen <minda.chen@starfivetech.com>
>
> I don't see a PATCH enabling it in defconfig.
>
> How is this driver used in OpenSBI ?
>
> Regards,
> Anup
>
I have enabled CONFIG_FDT_GPIO_STARFIVE in defconfig in this patch.
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -6,6 +6,7 @@ CONFIG_PLATFORM_SIFIVE_FU740=y
CONFIG_PLATFORM_STARFIVE_JH7110=y
CONFIG_FDT_GPIO=y
CONFIG_FDT_GPIO_SIFIVE=y
+CONFIG_FDT_GPIO_STARFIVE=y
May I set this change to second commit ?
This patch is a gpio reset implementation for sbi ecall SBI_EXT_SRST_RESET.
>> ---
>> lib/utils/gpio/Kconfig | 3 +
>> lib/utils/gpio/fdt_gpio_starfive.c | 117 +++++++++++++++++++++++++++++
>> lib/utils/gpio/objects.mk | 3 +
>> platform/generic/configs/defconfig | 1 +
defconfig have been changed.
>> 4 files changed, 124 insertions(+)
>> create mode 100644 lib/utils/gpio/fdt_gpio_starfive.c
>>
>> diff --git a/lib/utils/gpio/Kconfig b/lib/utils/gpio/Kconfig
>> index 38a9d75..1b338a6 100644
>> --- a/lib/utils/gpio/Kconfig
>> +++ b/lib/utils/gpio/Kconfig
>> @@ -14,6 +14,9 @@ config FDT_GPIO_SIFIVE
>> bool "SiFive GPIO FDT driver"
>> default n
>>
>> +config FDT_GPIO_STARFIVE
>> + bool "StarFive GPIO FDT driver"
>> + default n
>> endif
>>
>> config GPIO
>> diff --git a/lib/utils/gpio/fdt_gpio_starfive.c b/lib/utils/gpio/fdt_gpio_starfive.c
>> new file mode 100644
>> index 0000000..18cca72
>> --- /dev/null
>> +++ b/lib/utils/gpio/fdt_gpio_starfive.c
>> @@ -0,0 +1,117 @@
>> +/*
>> + * SPDX-License-Identifier: BSD-2-Clause
>> + *
>> + * Copyright (c) 2022 Starfive
>> + *
>> + * Authors:
>> + * Minda.chen <Minda.chen@starfivetech.com>
>> + */
>> +
>> +#include <sbi/riscv_io.h>
>> +#include <sbi/sbi_error.h>
>> +#include <sbi/sbi_console.h>
>> +#include <sbi_utils/fdt/fdt_helper.h>
>> +#include <sbi_utils/gpio/fdt_gpio.h>
>> +
>> +#define STARFIVE_GPIO_CHIP_MAX 2
>> +#define STARFIVE_GPIO_PINS_DEF 64
>> +#define STARFIVE_GPIO_OUTVAL 0x40
>> +#define STARFIVE_GPIO_MASK 0xff
>> +#define STARFIVE_GPIO_REG_SHIFT_MASK 0x3
>> +#define STARFIVE_GPIO_SHIFT_BITS 0x3
>> +
>> +struct starfive_gpio_chip {
>> + unsigned long addr;
>> + struct gpio_chip chip;
>> +};
>> +
>> +static unsigned int starfive_gpio_chip_count;
>> +static struct starfive_gpio_chip starfive_gpio_chip_array[STARFIVE_GPIO_CHIP_MAX];
>> +
>> +static int starfive_gpio_direction_output(struct gpio_pin *gp, int value)
>> +{
>> + u32 val;
>> + unsigned long reg_addr;
>> + u32 bit_mask, shift_bits;
>> + struct starfive_gpio_chip *chip =
>> + container_of(gp->chip, struct starfive_gpio_chip, chip);
>> +
>> + /* set out en*/
>> + reg_addr = chip->addr + gp->offset;
>> + reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
>> +
>> + val = readl((void *)(reg_addr));
>> + shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
>> + << STARFIVE_GPIO_SHIFT_BITS;
>> + bit_mask = STARFIVE_GPIO_MASK << shift_bits;
>> +
>> + val = readl((void *)reg_addr);
>> + val &= ~bit_mask;
>> + writel(val, (void *)reg_addr);
>> +
>> + return 0;
>> +}
>> +
>> +static void starfive_gpio_set(struct gpio_pin *gp, int value)
>> +{
>> + u32 val;
>> + unsigned long reg_addr;
>> + u32 bit_mask, shift_bits;
>> + struct starfive_gpio_chip *chip =
>> + container_of(gp->chip, struct starfive_gpio_chip, chip);
>> +
>> + reg_addr = chip->addr + gp->offset;
>> + reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
>> +
>> + shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
>> + << STARFIVE_GPIO_SHIFT_BITS;
>> + bit_mask = STARFIVE_GPIO_MASK << shift_bits;
>> + /* set output value */
>> + val = readl((void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
>> + val &= ~bit_mask;
>> + val |= value << shift_bits;
>> + writel(val, (void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
>> +}
>> +
>> +extern struct fdt_gpio fdt_gpio_starfive;
>> +
>> +static int starfive_gpio_init(void *fdt, int nodeoff, u32 phandle,
>> + const struct fdt_match *match)
>> +{
>> + int rc;
>> + struct starfive_gpio_chip *chip;
>> + u64 addr;
>> +
>> + if (starfive_gpio_chip_count >= STARFIVE_GPIO_CHIP_MAX)
>> + return SBI_ENOSPC;
>> + chip = &starfive_gpio_chip_array[starfive_gpio_chip_count];
>> +
>> + rc = fdt_get_node_addr_size(fdt, nodeoff, 0, &addr, NULL);
>> + if (rc)
>> + return rc;
>> +
>> + chip->addr = addr;
>> + chip->chip.driver = &fdt_gpio_starfive;
>> + chip->chip.id = phandle;
>> + chip->chip.ngpio = STARFIVE_GPIO_PINS_DEF;
>> + chip->chip.direction_output = starfive_gpio_direction_output;
>> + chip->chip.set = starfive_gpio_set;
>> + rc = gpio_chip_add(&chip->chip);
>> + if (rc)
>> + return rc;
>> +
>> + starfive_gpio_chip_count++;
>> + return 0;
>> +}
>> +
>> +static const struct fdt_match starfive_gpio_match[] = {
>> + { .compatible = "starfive,jh7110-sys-pinctrl" },
>> + { .compatible = "starfive,iomux-pinctrl" },
>> + { },
>> +};
>> +
>> +struct fdt_gpio fdt_gpio_starfive = {
>> + .match_table = starfive_gpio_match,
>> + .xlate = fdt_gpio_simple_xlate,
>> + .init = starfive_gpio_init,
>> +};
>> diff --git a/lib/utils/gpio/objects.mk b/lib/utils/gpio/objects.mk
>> index eedd699..8f4a6a8 100644
>> --- a/lib/utils/gpio/objects.mk
>> +++ b/lib/utils/gpio/objects.mk
>> @@ -13,4 +13,7 @@ libsbiutils-objs-$(CONFIG_FDT_GPIO) += gpio/fdt_gpio_drivers.o
>> carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_SIFIVE) += fdt_gpio_sifive
>> libsbiutils-objs-$(CONFIG_FDT_GPIO_SIFIVE) += gpio/fdt_gpio_sifive.o
>>
>> +carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_STARFIVE) += fdt_gpio_starfive
>> +libsbiutils-objs-$(CONFIG_FDT_GPIO_STARFIVE) += gpio/fdt_gpio_starfive.o
>> +
>> libsbiutils-objs-$(CONFIG_GPIO) += gpio/gpio.o
>> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
>> index 4b0842e..2ad953d 100644
>> --- a/platform/generic/configs/defconfig
>> +++ b/platform/generic/configs/defconfig
>> @@ -6,6 +6,7 @@ CONFIG_PLATFORM_SIFIVE_FU740=y
>> CONFIG_PLATFORM_STARFIVE_JH7110=y
>> CONFIG_FDT_GPIO=y
>> CONFIG_FDT_GPIO_SIFIVE=y
>> +CONFIG_FDT_GPIO_STARFIVE=y
>> CONFIG_FDT_I2C=y
>> CONFIG_FDT_I2C_SIFIVE=y
>> CONFIG_FDT_IPI=y
>> --
>> 2.17.1
>>
>>
>> --
>> opensbi mailing list
>> opensbi at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] gpio/starfive: add gpio driver and support gpio reset
2023-02-27 11:23 ` Minda Chen
@ 2023-02-27 14:00 ` Anup Patel
2023-02-28 10:30 ` Minda Chen
0 siblings, 1 reply; 6+ messages in thread
From: Anup Patel @ 2023-02-27 14:00 UTC (permalink / raw)
To: opensbi
On Mon, Feb 27, 2023 at 4:53 PM Minda Chen <minda.chen@starfivetech.com> wrote:
>
>
>
> On 2023/2/27 14:44, Anup Patel wrote:
> > On Thu, Feb 16, 2023 at 2:52 PM minda.chen <minda.chen@starfivetech.com> wrote:
> >>
> >> Add gpio driver and gpio reset function in Starfive
> >> JH7110 SOC platform.
> >>
> >> Signed-off-by: minda.chen <minda.chen@starfivetech.com>
> >
> > I don't see a PATCH enabling it in defconfig.
> >
> > How is this driver used in OpenSBI ?
> >
> > Regards,
> > Anup
> >
> I have enabled CONFIG_FDT_GPIO_STARFIVE in defconfig in this patch.
Okay.
>
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -6,6 +6,7 @@ CONFIG_PLATFORM_SIFIVE_FU740=y
> CONFIG_PLATFORM_STARFIVE_JH7110=y
> CONFIG_FDT_GPIO=y
> CONFIG_FDT_GPIO_SIFIVE=y
> +CONFIG_FDT_GPIO_STARFIVE=y
>
> May I set this change to second commit ?
No need for a separate patch.
>
> This patch is a gpio reset implementation for sbi ecall SBI_EXT_SRST_RESET.
Fare enough but you also send another series
"Add StarFive JH7110 SoC shutdown and reboot ops"
which provides system reboot based on I2C PMIC.
Basically, we have two separate system reboot ops
for JH7110, is that right ?
Regards,
Anup
>
> >> ---
> >> lib/utils/gpio/Kconfig | 3 +
> >> lib/utils/gpio/fdt_gpio_starfive.c | 117 +++++++++++++++++++++++++++++
> >> lib/utils/gpio/objects.mk | 3 +
> >> platform/generic/configs/defconfig | 1 +
> defconfig have been changed.
>
> >> 4 files changed, 124 insertions(+)
> >> create mode 100644 lib/utils/gpio/fdt_gpio_starfive.c
> >>
> >> diff --git a/lib/utils/gpio/Kconfig b/lib/utils/gpio/Kconfig
> >> index 38a9d75..1b338a6 100644
> >> --- a/lib/utils/gpio/Kconfig
> >> +++ b/lib/utils/gpio/Kconfig
> >> @@ -14,6 +14,9 @@ config FDT_GPIO_SIFIVE
> >> bool "SiFive GPIO FDT driver"
> >> default n
> >>
> >> +config FDT_GPIO_STARFIVE
> >> + bool "StarFive GPIO FDT driver"
> >> + default n
> >> endif
> >>
> >> config GPIO
> >> diff --git a/lib/utils/gpio/fdt_gpio_starfive.c b/lib/utils/gpio/fdt_gpio_starfive.c
> >> new file mode 100644
> >> index 0000000..18cca72
> >> --- /dev/null
> >> +++ b/lib/utils/gpio/fdt_gpio_starfive.c
> >> @@ -0,0 +1,117 @@
> >> +/*
> >> + * SPDX-License-Identifier: BSD-2-Clause
> >> + *
> >> + * Copyright (c) 2022 Starfive
> >> + *
> >> + * Authors:
> >> + * Minda.chen <Minda.chen@starfivetech.com>
> >> + */
> >> +
> >> +#include <sbi/riscv_io.h>
> >> +#include <sbi/sbi_error.h>
> >> +#include <sbi/sbi_console.h>
> >> +#include <sbi_utils/fdt/fdt_helper.h>
> >> +#include <sbi_utils/gpio/fdt_gpio.h>
> >> +
> >> +#define STARFIVE_GPIO_CHIP_MAX 2
> >> +#define STARFIVE_GPIO_PINS_DEF 64
> >> +#define STARFIVE_GPIO_OUTVAL 0x40
> >> +#define STARFIVE_GPIO_MASK 0xff
> >> +#define STARFIVE_GPIO_REG_SHIFT_MASK 0x3
> >> +#define STARFIVE_GPIO_SHIFT_BITS 0x3
> >> +
> >> +struct starfive_gpio_chip {
> >> + unsigned long addr;
> >> + struct gpio_chip chip;
> >> +};
> >> +
> >> +static unsigned int starfive_gpio_chip_count;
> >> +static struct starfive_gpio_chip starfive_gpio_chip_array[STARFIVE_GPIO_CHIP_MAX];
> >> +
> >> +static int starfive_gpio_direction_output(struct gpio_pin *gp, int value)
> >> +{
> >> + u32 val;
> >> + unsigned long reg_addr;
> >> + u32 bit_mask, shift_bits;
> >> + struct starfive_gpio_chip *chip =
> >> + container_of(gp->chip, struct starfive_gpio_chip, chip);
> >> +
> >> + /* set out en*/
> >> + reg_addr = chip->addr + gp->offset;
> >> + reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
> >> +
> >> + val = readl((void *)(reg_addr));
> >> + shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
> >> + << STARFIVE_GPIO_SHIFT_BITS;
> >> + bit_mask = STARFIVE_GPIO_MASK << shift_bits;
> >> +
> >> + val = readl((void *)reg_addr);
> >> + val &= ~bit_mask;
> >> + writel(val, (void *)reg_addr);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static void starfive_gpio_set(struct gpio_pin *gp, int value)
> >> +{
> >> + u32 val;
> >> + unsigned long reg_addr;
> >> + u32 bit_mask, shift_bits;
> >> + struct starfive_gpio_chip *chip =
> >> + container_of(gp->chip, struct starfive_gpio_chip, chip);
> >> +
> >> + reg_addr = chip->addr + gp->offset;
> >> + reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
> >> +
> >> + shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
> >> + << STARFIVE_GPIO_SHIFT_BITS;
> >> + bit_mask = STARFIVE_GPIO_MASK << shift_bits;
> >> + /* set output value */
> >> + val = readl((void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
> >> + val &= ~bit_mask;
> >> + val |= value << shift_bits;
> >> + writel(val, (void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
> >> +}
> >> +
> >> +extern struct fdt_gpio fdt_gpio_starfive;
> >> +
> >> +static int starfive_gpio_init(void *fdt, int nodeoff, u32 phandle,
> >> + const struct fdt_match *match)
> >> +{
> >> + int rc;
> >> + struct starfive_gpio_chip *chip;
> >> + u64 addr;
> >> +
> >> + if (starfive_gpio_chip_count >= STARFIVE_GPIO_CHIP_MAX)
> >> + return SBI_ENOSPC;
> >> + chip = &starfive_gpio_chip_array[starfive_gpio_chip_count];
> >> +
> >> + rc = fdt_get_node_addr_size(fdt, nodeoff, 0, &addr, NULL);
> >> + if (rc)
> >> + return rc;
> >> +
> >> + chip->addr = addr;
> >> + chip->chip.driver = &fdt_gpio_starfive;
> >> + chip->chip.id = phandle;
> >> + chip->chip.ngpio = STARFIVE_GPIO_PINS_DEF;
> >> + chip->chip.direction_output = starfive_gpio_direction_output;
> >> + chip->chip.set = starfive_gpio_set;
> >> + rc = gpio_chip_add(&chip->chip);
> >> + if (rc)
> >> + return rc;
> >> +
> >> + starfive_gpio_chip_count++;
> >> + return 0;
> >> +}
> >> +
> >> +static const struct fdt_match starfive_gpio_match[] = {
> >> + { .compatible = "starfive,jh7110-sys-pinctrl" },
> >> + { .compatible = "starfive,iomux-pinctrl" },
> >> + { },
> >> +};
> >> +
> >> +struct fdt_gpio fdt_gpio_starfive = {
> >> + .match_table = starfive_gpio_match,
> >> + .xlate = fdt_gpio_simple_xlate,
> >> + .init = starfive_gpio_init,
> >> +};
> >> diff --git a/lib/utils/gpio/objects.mk b/lib/utils/gpio/objects.mk
> >> index eedd699..8f4a6a8 100644
> >> --- a/lib/utils/gpio/objects.mk
> >> +++ b/lib/utils/gpio/objects.mk
> >> @@ -13,4 +13,7 @@ libsbiutils-objs-$(CONFIG_FDT_GPIO) += gpio/fdt_gpio_drivers.o
> >> carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_SIFIVE) += fdt_gpio_sifive
> >> libsbiutils-objs-$(CONFIG_FDT_GPIO_SIFIVE) += gpio/fdt_gpio_sifive.o
> >>
> >> +carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_STARFIVE) += fdt_gpio_starfive
> >> +libsbiutils-objs-$(CONFIG_FDT_GPIO_STARFIVE) += gpio/fdt_gpio_starfive.o
> >> +
> >> libsbiutils-objs-$(CONFIG_GPIO) += gpio/gpio.o
> >> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> >> index 4b0842e..2ad953d 100644
> >> --- a/platform/generic/configs/defconfig
> >> +++ b/platform/generic/configs/defconfig
> >> @@ -6,6 +6,7 @@ CONFIG_PLATFORM_SIFIVE_FU740=y
> >> CONFIG_PLATFORM_STARFIVE_JH7110=y
> >> CONFIG_FDT_GPIO=y
> >> CONFIG_FDT_GPIO_SIFIVE=y
> >> +CONFIG_FDT_GPIO_STARFIVE=y
> >> CONFIG_FDT_I2C=y
> >> CONFIG_FDT_I2C_SIFIVE=y
> >> CONFIG_FDT_IPI=y
> >> --
> >> 2.17.1
> >>
> >>
> >> --
> >> opensbi mailing list
> >> opensbi at lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] gpio/starfive: add gpio driver and support gpio reset
2023-02-27 14:00 ` Anup Patel
@ 2023-02-28 10:30 ` Minda Chen
0 siblings, 0 replies; 6+ messages in thread
From: Minda Chen @ 2023-02-28 10:30 UTC (permalink / raw)
To: opensbi
On 2023/2/27 22:00, Anup Patel wrote:
> On Mon, Feb 27, 2023 at 4:53 PM Minda Chen <minda.chen@starfivetech.com> wrote:
>>
>>
>>
>> On 2023/2/27 14:44, Anup Patel wrote:
>> > On Thu, Feb 16, 2023 at 2:52 PM minda.chen <minda.chen@starfivetech.com> wrote:
>> >>
>> >> Add gpio driver and gpio reset function in Starfive
>> >> JH7110 SOC platform.
>> >>
>> >> Signed-off-by: minda.chen <minda.chen@starfivetech.com>
>> >
>> > I don't see a PATCH enabling it in defconfig.
>> >
>> > How is this driver used in OpenSBI ?
>> >
>> > Regards,
>> > Anup
>> >
>> I have enabled CONFIG_FDT_GPIO_STARFIVE in defconfig in this patch.
>
> Okay.
>
>>
>> --- a/platform/generic/configs/defconfig
>> +++ b/platform/generic/configs/defconfig
>> @@ -6,6 +6,7 @@ CONFIG_PLATFORM_SIFIVE_FU740=y
>> CONFIG_PLATFORM_STARFIVE_JH7110=y
>> CONFIG_FDT_GPIO=y
>> CONFIG_FDT_GPIO_SIFIVE=y
>> +CONFIG_FDT_GPIO_STARFIVE=y
>>
>> May I set this change to second commit ?
>
> No need for a separate patch.
>
>>
>> This patch is a gpio reset implementation for sbi ecall SBI_EXT_SRST_RESET.
>
> Fare enough but you also send another series
> "Add StarFive JH7110 SoC shutdown and reboot ops"
> which provides system reboot based on I2C PMIC.
>
> Basically, we have two separate system reboot ops
> for JH7110, is that right ?
>
> Regards,
> Anup
>
Yes, GPIO reset is for uboot warm reset, PMIC reset is for uboot cold reset and linux reboot.
>
>>
>> >> ---
>> >> lib/utils/gpio/Kconfig | 3 +
>> >> lib/utils/gpio/fdt_gpio_starfive.c | 117 +++++++++++++++++++++++++++++
>> >> lib/utils/gpio/objects.mk | 3 +
>> >> platform/generic/configs/defconfig | 1 +
>> defconfig have been changed.
>>
>> >> 4 files changed, 124 insertions(+)
>> >> create mode 100644 lib/utils/gpio/fdt_gpio_starfive.c
>> >>
>> >> diff --git a/lib/utils/gpio/Kconfig b/lib/utils/gpio/Kconfig
>> >> index 38a9d75..1b338a6 100644
>> >> --- a/lib/utils/gpio/Kconfig
>> >> +++ b/lib/utils/gpio/Kconfig
>> >> @@ -14,6 +14,9 @@ config FDT_GPIO_SIFIVE
>> >> bool "SiFive GPIO FDT driver"
>> >> default n
>> >>
>> >> +config FDT_GPIO_STARFIVE
>> >> + bool "StarFive GPIO FDT driver"
>> >> + default n
>> >> endif
>> >>
>> >> config GPIO
>> >> diff --git a/lib/utils/gpio/fdt_gpio_starfive.c b/lib/utils/gpio/fdt_gpio_starfive.c
>> >> new file mode 100644
>> >> index 0000000..18cca72
>> >> --- /dev/null
>> >> +++ b/lib/utils/gpio/fdt_gpio_starfive.c
>> >> @@ -0,0 +1,117 @@
>> >> +/*
>> >> + * SPDX-License-Identifier: BSD-2-Clause
>> >> + *
>> >> + * Copyright (c) 2022 Starfive
>> >> + *
>> >> + * Authors:
>> >> + * Minda.chen <Minda.chen@starfivetech.com>
>> >> + */
>> >> +
>> >> +#include <sbi/riscv_io.h>
>> >> +#include <sbi/sbi_error.h>
>> >> +#include <sbi/sbi_console.h>
>> >> +#include <sbi_utils/fdt/fdt_helper.h>
>> >> +#include <sbi_utils/gpio/fdt_gpio.h>
>> >> +
>> >> +#define STARFIVE_GPIO_CHIP_MAX 2
>> >> +#define STARFIVE_GPIO_PINS_DEF 64
>> >> +#define STARFIVE_GPIO_OUTVAL 0x40
>> >> +#define STARFIVE_GPIO_MASK 0xff
>> >> +#define STARFIVE_GPIO_REG_SHIFT_MASK 0x3
>> >> +#define STARFIVE_GPIO_SHIFT_BITS 0x3
>> >> +
>> >> +struct starfive_gpio_chip {
>> >> + unsigned long addr;
>> >> + struct gpio_chip chip;
>> >> +};
>> >> +
>> >> +static unsigned int starfive_gpio_chip_count;
>> >> +static struct starfive_gpio_chip starfive_gpio_chip_array[STARFIVE_GPIO_CHIP_MAX];
>> >> +
>> >> +static int starfive_gpio_direction_output(struct gpio_pin *gp, int value)
>> >> +{
>> >> + u32 val;
>> >> + unsigned long reg_addr;
>> >> + u32 bit_mask, shift_bits;
>> >> + struct starfive_gpio_chip *chip =
>> >> + container_of(gp->chip, struct starfive_gpio_chip, chip);
>> >> +
>> >> + /* set out en*/
>> >> + reg_addr = chip->addr + gp->offset;
>> >> + reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
>> >> +
>> >> + val = readl((void *)(reg_addr));
>> >> + shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
>> >> + << STARFIVE_GPIO_SHIFT_BITS;
>> >> + bit_mask = STARFIVE_GPIO_MASK << shift_bits;
>> >> +
>> >> + val = readl((void *)reg_addr);
>> >> + val &= ~bit_mask;
>> >> + writel(val, (void *)reg_addr);
>> >> +
>> >> + return 0;
>> >> +}
>> >> +
>> >> +static void starfive_gpio_set(struct gpio_pin *gp, int value)
>> >> +{
>> >> + u32 val;
>> >> + unsigned long reg_addr;
>> >> + u32 bit_mask, shift_bits;
>> >> + struct starfive_gpio_chip *chip =
>> >> + container_of(gp->chip, struct starfive_gpio_chip, chip);
>> >> +
>> >> + reg_addr = chip->addr + gp->offset;
>> >> + reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
>> >> +
>> >> + shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
>> >> + << STARFIVE_GPIO_SHIFT_BITS;
>> >> + bit_mask = STARFIVE_GPIO_MASK << shift_bits;
>> >> + /* set output value */
>> >> + val = readl((void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
>> >> + val &= ~bit_mask;
>> >> + val |= value << shift_bits;
>> >> + writel(val, (void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
>> >> +}
>> >> +
>> >> +extern struct fdt_gpio fdt_gpio_starfive;
>> >> +
>> >> +static int starfive_gpio_init(void *fdt, int nodeoff, u32 phandle,
>> >> + const struct fdt_match *match)
>> >> +{
>> >> + int rc;
>> >> + struct starfive_gpio_chip *chip;
>> >> + u64 addr;
>> >> +
>> >> + if (starfive_gpio_chip_count >= STARFIVE_GPIO_CHIP_MAX)
>> >> + return SBI_ENOSPC;
>> >> + chip = &starfive_gpio_chip_array[starfive_gpio_chip_count];
>> >> +
>> >> + rc = fdt_get_node_addr_size(fdt, nodeoff, 0, &addr, NULL);
>> >> + if (rc)
>> >> + return rc;
>> >> +
>> >> + chip->addr = addr;
>> >> + chip->chip.driver = &fdt_gpio_starfive;
>> >> + chip->chip.id = phandle;
>> >> + chip->chip.ngpio = STARFIVE_GPIO_PINS_DEF;
>> >> + chip->chip.direction_output = starfive_gpio_direction_output;
>> >> + chip->chip.set = starfive_gpio_set;
>> >> + rc = gpio_chip_add(&chip->chip);
>> >> + if (rc)
>> >> + return rc;
>> >> +
>> >> + starfive_gpio_chip_count++;
>> >> + return 0;
>> >> +}
>> >> +
>> >> +static const struct fdt_match starfive_gpio_match[] = {
>> >> + { .compatible = "starfive,jh7110-sys-pinctrl" },
>> >> + { .compatible = "starfive,iomux-pinctrl" },
>> >> + { },
>> >> +};
>> >> +
>> >> +struct fdt_gpio fdt_gpio_starfive = {
>> >> + .match_table = starfive_gpio_match,
>> >> + .xlate = fdt_gpio_simple_xlate,
>> >> + .init = starfive_gpio_init,
>> >> +};
>> >> diff --git a/lib/utils/gpio/objects.mk b/lib/utils/gpio/objects.mk
>> >> index eedd699..8f4a6a8 100644
>> >> --- a/lib/utils/gpio/objects.mk
>> >> +++ b/lib/utils/gpio/objects.mk
>> >> @@ -13,4 +13,7 @@ libsbiutils-objs-$(CONFIG_FDT_GPIO) += gpio/fdt_gpio_drivers.o
>> >> carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_SIFIVE) += fdt_gpio_sifive
>> >> libsbiutils-objs-$(CONFIG_FDT_GPIO_SIFIVE) += gpio/fdt_gpio_sifive.o
>> >>
>> >> +carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_STARFIVE) += fdt_gpio_starfive
>> >> +libsbiutils-objs-$(CONFIG_FDT_GPIO_STARFIVE) += gpio/fdt_gpio_starfive.o
>> >> +
>> >> libsbiutils-objs-$(CONFIG_GPIO) += gpio/gpio.o
>> >> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
>> >> index 4b0842e..2ad953d 100644
>> >> --- a/platform/generic/configs/defconfig
>> >> +++ b/platform/generic/configs/defconfig
>> >> @@ -6,6 +6,7 @@ CONFIG_PLATFORM_SIFIVE_FU740=y
>> >> CONFIG_PLATFORM_STARFIVE_JH7110=y
>> >> CONFIG_FDT_GPIO=y
>> >> CONFIG_FDT_GPIO_SIFIVE=y
>> >> +CONFIG_FDT_GPIO_STARFIVE=y
>> >> CONFIG_FDT_I2C=y
>> >> CONFIG_FDT_I2C_SIFIVE=y
>> >> CONFIG_FDT_IPI=y
>> >> --
>> >> 2.17.1
>> >>
>> >>
>> >> --
>> >> opensbi mailing list
>> >> opensbi at lists.infradead.org
>> >> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] gpio/starfive: add gpio driver and support gpio reset
2023-02-16 9:21 [PATCH] gpio/starfive: add gpio driver and support gpio reset minda.chen
2023-02-27 6:44 ` Anup Patel
@ 2023-03-01 3:47 ` Anup Patel
1 sibling, 0 replies; 6+ messages in thread
From: Anup Patel @ 2023-03-01 3:47 UTC (permalink / raw)
To: opensbi
On Thu, Feb 16, 2023 at 2:52 PM minda.chen <minda.chen@starfivetech.com> wrote:
>
> Add gpio driver and gpio reset function in Starfive
> JH7110 SOC platform.
>
> Signed-off-by: minda.chen <minda.chen@starfivetech.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Applied this patch to the riscv/opensbi repo.
Thanks,
Anup
> ---
> lib/utils/gpio/Kconfig | 3 +
> lib/utils/gpio/fdt_gpio_starfive.c | 117 +++++++++++++++++++++++++++++
> lib/utils/gpio/objects.mk | 3 +
> platform/generic/configs/defconfig | 1 +
> 4 files changed, 124 insertions(+)
> create mode 100644 lib/utils/gpio/fdt_gpio_starfive.c
>
> diff --git a/lib/utils/gpio/Kconfig b/lib/utils/gpio/Kconfig
> index 38a9d75..1b338a6 100644
> --- a/lib/utils/gpio/Kconfig
> +++ b/lib/utils/gpio/Kconfig
> @@ -14,6 +14,9 @@ config FDT_GPIO_SIFIVE
> bool "SiFive GPIO FDT driver"
> default n
>
> +config FDT_GPIO_STARFIVE
> + bool "StarFive GPIO FDT driver"
> + default n
> endif
>
> config GPIO
> diff --git a/lib/utils/gpio/fdt_gpio_starfive.c b/lib/utils/gpio/fdt_gpio_starfive.c
> new file mode 100644
> index 0000000..18cca72
> --- /dev/null
> +++ b/lib/utils/gpio/fdt_gpio_starfive.c
> @@ -0,0 +1,117 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Starfive
> + *
> + * Authors:
> + * Minda.chen <Minda.chen@starfivetech.com>
> + */
> +
> +#include <sbi/riscv_io.h>
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +#include <sbi_utils/gpio/fdt_gpio.h>
> +
> +#define STARFIVE_GPIO_CHIP_MAX 2
> +#define STARFIVE_GPIO_PINS_DEF 64
> +#define STARFIVE_GPIO_OUTVAL 0x40
> +#define STARFIVE_GPIO_MASK 0xff
> +#define STARFIVE_GPIO_REG_SHIFT_MASK 0x3
> +#define STARFIVE_GPIO_SHIFT_BITS 0x3
> +
> +struct starfive_gpio_chip {
> + unsigned long addr;
> + struct gpio_chip chip;
> +};
> +
> +static unsigned int starfive_gpio_chip_count;
> +static struct starfive_gpio_chip starfive_gpio_chip_array[STARFIVE_GPIO_CHIP_MAX];
> +
> +static int starfive_gpio_direction_output(struct gpio_pin *gp, int value)
> +{
> + u32 val;
> + unsigned long reg_addr;
> + u32 bit_mask, shift_bits;
> + struct starfive_gpio_chip *chip =
> + container_of(gp->chip, struct starfive_gpio_chip, chip);
> +
> + /* set out en*/
> + reg_addr = chip->addr + gp->offset;
> + reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
> +
> + val = readl((void *)(reg_addr));
> + shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
> + << STARFIVE_GPIO_SHIFT_BITS;
> + bit_mask = STARFIVE_GPIO_MASK << shift_bits;
> +
> + val = readl((void *)reg_addr);
> + val &= ~bit_mask;
> + writel(val, (void *)reg_addr);
> +
> + return 0;
> +}
> +
> +static void starfive_gpio_set(struct gpio_pin *gp, int value)
> +{
> + u32 val;
> + unsigned long reg_addr;
> + u32 bit_mask, shift_bits;
> + struct starfive_gpio_chip *chip =
> + container_of(gp->chip, struct starfive_gpio_chip, chip);
> +
> + reg_addr = chip->addr + gp->offset;
> + reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
> +
> + shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
> + << STARFIVE_GPIO_SHIFT_BITS;
> + bit_mask = STARFIVE_GPIO_MASK << shift_bits;
> + /* set output value */
> + val = readl((void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
> + val &= ~bit_mask;
> + val |= value << shift_bits;
> + writel(val, (void *)(reg_addr + STARFIVE_GPIO_OUTVAL));
> +}
> +
> +extern struct fdt_gpio fdt_gpio_starfive;
> +
> +static int starfive_gpio_init(void *fdt, int nodeoff, u32 phandle,
> + const struct fdt_match *match)
> +{
> + int rc;
> + struct starfive_gpio_chip *chip;
> + u64 addr;
> +
> + if (starfive_gpio_chip_count >= STARFIVE_GPIO_CHIP_MAX)
> + return SBI_ENOSPC;
> + chip = &starfive_gpio_chip_array[starfive_gpio_chip_count];
> +
> + rc = fdt_get_node_addr_size(fdt, nodeoff, 0, &addr, NULL);
> + if (rc)
> + return rc;
> +
> + chip->addr = addr;
> + chip->chip.driver = &fdt_gpio_starfive;
> + chip->chip.id = phandle;
> + chip->chip.ngpio = STARFIVE_GPIO_PINS_DEF;
> + chip->chip.direction_output = starfive_gpio_direction_output;
> + chip->chip.set = starfive_gpio_set;
> + rc = gpio_chip_add(&chip->chip);
> + if (rc)
> + return rc;
> +
> + starfive_gpio_chip_count++;
> + return 0;
> +}
> +
> +static const struct fdt_match starfive_gpio_match[] = {
> + { .compatible = "starfive,jh7110-sys-pinctrl" },
> + { .compatible = "starfive,iomux-pinctrl" },
> + { },
> +};
> +
> +struct fdt_gpio fdt_gpio_starfive = {
> + .match_table = starfive_gpio_match,
> + .xlate = fdt_gpio_simple_xlate,
> + .init = starfive_gpio_init,
> +};
> diff --git a/lib/utils/gpio/objects.mk b/lib/utils/gpio/objects.mk
> index eedd699..8f4a6a8 100644
> --- a/lib/utils/gpio/objects.mk
> +++ b/lib/utils/gpio/objects.mk
> @@ -13,4 +13,7 @@ libsbiutils-objs-$(CONFIG_FDT_GPIO) += gpio/fdt_gpio_drivers.o
> carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_SIFIVE) += fdt_gpio_sifive
> libsbiutils-objs-$(CONFIG_FDT_GPIO_SIFIVE) += gpio/fdt_gpio_sifive.o
>
> +carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_STARFIVE) += fdt_gpio_starfive
> +libsbiutils-objs-$(CONFIG_FDT_GPIO_STARFIVE) += gpio/fdt_gpio_starfive.o
> +
> libsbiutils-objs-$(CONFIG_GPIO) += gpio/gpio.o
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index 4b0842e..2ad953d 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -6,6 +6,7 @@ CONFIG_PLATFORM_SIFIVE_FU740=y
> CONFIG_PLATFORM_STARFIVE_JH7110=y
> CONFIG_FDT_GPIO=y
> CONFIG_FDT_GPIO_SIFIVE=y
> +CONFIG_FDT_GPIO_STARFIVE=y
> CONFIG_FDT_I2C=y
> CONFIG_FDT_I2C_SIFIVE=y
> CONFIG_FDT_IPI=y
> --
> 2.17.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-03-01 3:47 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-02-16 9:21 [PATCH] gpio/starfive: add gpio driver and support gpio reset minda.chen
2023-02-27 6:44 ` Anup Patel
2023-02-27 11:23 ` Minda Chen
2023-02-27 14:00 ` Anup Patel
2023-02-28 10:30 ` Minda Chen
2023-03-01 3:47 ` Anup Patel
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