From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: opensbi@lists.infradead.org
Cc: anup@brainfault.org, pawandeep.oza@oss.qualcomm.com,
rkrcmar@qti.qualcomm.com, raymond.mao@riscstar.com,
robin.randhawa@sifive.com, samuel.holland@sifive.com,
zong.li@sifive.com, greentime.hu@sifive.com,
Yu-Chien Peter Lin <peter.lin@sifive.com>
Subject: [PATCH v4 2/9] lib: utils: fdt_helper: parse RISC-V Worlds per-hart WID properties
Date: Fri, 30 Oct 2026 18:45:11 +0800 [thread overview]
Message-ID: <20261030104518.3297875-3-peter.lin@sifive.com> (raw)
In-Reply-To: <20261030104518.3297875-1-peter.lin@sifive.com>
Extend fdt_parse_isa_extensions_all_harts() to also parse the
platform-defined RISC-V Worlds DT properties in /cpus/cpu@X:
- riscv,pmwid: M-mode World ID
- riscv,pmwidlist: bitmap of permitted M-mode WIDs
- riscv,pmlwidlist: bitmap of permitted lower-privilege WIDs
and store the parsed values in struct sbi_hart_features.
These platform-defined values serve as the root-of-trust constraints
for per-domain WID assignment during domain creation and context
switching.
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
---
Change v3->v4:
- Parse Worlds properties in fdt_parse_isa_extensions_all_harts()
instead of a separate fdt_parse_worlds_all_harts() (Anup).
- Drop RB-tag from Oza
---
include/sbi/sbi_hart.h | 5 +++
lib/utils/fdt/fdt_helper.c | 69 ++++++++++++++++++++++++++++++++++----
2 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index ed344783..629e3f64 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -138,6 +138,11 @@ struct sbi_hart_features {
unsigned int mhpm_mask;
unsigned int mhpm_bits;
unsigned long expected_trap;
+ u32 pmwid;
+ u64 pmwidlist;
+ u64 pmlwidlist;
+ bool has_pmwid;
+ bool has_pmlwidlist;
};
extern unsigned long hart_features_offset;
diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 747ba028..fdd25648 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -442,16 +442,71 @@ int fdt_parse_isa_extensions_all_harts(const void *fdt)
if (val && len > 0) {
fdt_parse_isa_extensions_one_hart((const char *)val,
hfeatures->extensions, len);
- continue;
+ } else {
+ val = fdt_getprop(fdt, cpu_offset, "riscv,isa", &len);
+ if (!val || len <= 0)
+ return SBI_ENOENT;
+
+ err = fdt_parse_isa_one_hart((const char *)val,
+ hfeatures->extensions);
+ if (err)
+ return err;
}
- val = fdt_getprop(fdt, cpu_offset, "riscv,isa", &len);
- if (!val || len <= 0)
- return SBI_ENOENT;
+ val = fdt_getprop(fdt, cpu_offset, "riscv,pmwid", &len);
+ if (val && len == sizeof(fdt32_t)) {
+ hfeatures->pmwid = fdt32_to_cpu(*val);
+ hfeatures->has_pmwid = true;
+ }
- err = fdt_parse_isa_one_hart((const char *)val, hfeatures->extensions);
- if (err)
- return err;
+ val = fdt_getprop(fdt, cpu_offset, "riscv,pmwidlist", &len);
+ if (val && len == 2 * sizeof(fdt32_t)) {
+ hfeatures->pmwidlist = ((u64)fdt32_to_cpu(val[0]) << 32) |
+ fdt32_to_cpu(val[1]);
+ if (!hfeatures->pmwidlist) {
+ sbi_printf("%s: hart%u riscv,pmwidlist is empty\n",
+ __func__, hartid);
+ return SBI_EINVAL;
+ }
+ }
+
+ val = fdt_getprop(fdt, cpu_offset, "riscv,pmlwidlist", &len);
+ if (val && len == 2 * sizeof(fdt32_t)) {
+ hfeatures->pmlwidlist = ((u64)fdt32_to_cpu(val[0]) << 32) |
+ fdt32_to_cpu(val[1]);
+ hfeatures->has_pmlwidlist = true;
+ }
+
+ /* Sanity checks */
+#if __riscv_xlen == 32
+ if (hfeatures->pmwidlist &&
+ (hfeatures->pmwidlist >> 32)) {
+ sbi_printf("%s: hart%u riscv,pmwidlist has bits beyond XLEN\n",
+ __func__, hartid);
+ return SBI_EINVAL;
+ }
+
+ if (hfeatures->has_pmlwidlist &&
+ (hfeatures->pmlwidlist >> 32)) {
+ sbi_printf("%s: hart%u riscv,pmlwidlist has bits beyond XLEN\n",
+ __func__, hartid);
+ return SBI_EINVAL;
+ }
+#endif
+
+ if (hfeatures->has_pmwid &&
+ hfeatures->pmwid >= __riscv_xlen) {
+ sbi_printf("%s: hart%u riscv,pmwid (%u) exceeds max WID\n",
+ __func__, hartid, hfeatures->pmwid);
+ return SBI_EINVAL;
+ }
+
+ if (hfeatures->pmwidlist && hfeatures->has_pmwid &&
+ !(hfeatures->pmwidlist & BIT_ULL(hfeatures->pmwid))) {
+ sbi_printf("%s: hart%u riscv,pmwid (%u) not in pmwidlist\n",
+ __func__, hartid, hfeatures->pmwid);
+ return SBI_EINVAL;
+ }
}
return 0;
--
2.43.7
--
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next prev parent reply other threads:[~2026-10-30 10:45 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-30 10:45 [PATCH v4 0/9] Add RISC-V Worlds ISA support to OpenSBI Yu-Chien Peter Lin
2026-10-30 10:45 ` [PATCH v4 1/9] lib: sbi_hart: add RISC-V Worlds ISA extensions Yu-Chien Peter Lin
2026-10-31 12:48 ` Anup Patel
2026-10-30 10:45 ` Yu-Chien Peter Lin [this message]
2026-10-31 12:48 ` [PATCH v4 2/9] lib: utils: fdt_helper: parse RISC-V Worlds per-hart WID properties Anup Patel
2026-10-30 10:45 ` [PATCH v4 3/9] lib: fdt_domain: parse domain " Yu-Chien Peter Lin
2026-10-31 12:49 ` Anup Patel
2026-10-30 10:45 ` [PATCH v4 4/9] lib: sbi_hart: lock mwid CSR for RoT immutability Yu-Chien Peter Lin
2026-10-30 10:45 ` [PATCH v4 5/9] lib: sbi_domain_context: propagate error from sbi_hart_protection_reconfigure Yu-Chien Peter Lin
2026-10-30 10:45 ` [PATCH v4 6/9] lib: sbi_hart_worlds: Implement WID hart protection backend Yu-Chien Peter Lin
2026-10-30 10:45 ` [PATCH v4 7/9] include: sbi_types: add PRIx64 format macro Yu-Chien Peter Lin
2026-10-30 10:45 ` [PATCH v4 8/9] lib: sbi: display World ID configuration at boot Yu-Chien Peter Lin
2026-10-30 10:45 ` [PATCH v4 9/9] docs: document WID DT properties Yu-Chien Peter Lin
2026-10-31 12:49 ` Anup Patel
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