* [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system
@ 2021-10-02 9:32 Vadim Pasternak
2021-10-02 9:32 ` [PATCH platform-next 01/10] platform_data/mlxreg: Add new type to support modular systems Vadim Pasternak
` (8 more replies)
0 siblings, 9 replies; 13+ messages in thread
From: Vadim Pasternak @ 2021-10-02 9:32 UTC (permalink / raw)
To: hdegoede; +Cc: platform-driver-x86, michaelsh, Vadim Pasternak
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Add initial chassis management support for Nvidia modular Ethernet
switch systems MSN4800, providing a high performance switching solution
for Enterprise Data Centers (EDC) for building Ethernet based clusters,
High-Performance Computing (HPC) and embedded environments.
This system could be equipped with the different types of replaceable
line cards and management board. The first system flavor will support
the line card type MSN4800-C16 equipped with Lattice CPLD devices aimed
for system and ASIC control, one Nvidia FPGA for gearboxes (PHYs)
management, and four Nvidia gearboxes for the port control and with
16x100GbE QSFP28 ports and with various devices for electrical control.
The system is equipped with eight slots for line cards, four slots for
power supplies and six slots for fans. It could be configured as fully
populated or with even only one line card. The line cards are
hot-pluggable.
In the future when more line card flavors are to be available (for
example line cards with 8x200Gb Eth port, with 4x400 Eth ports, or with
some kind of smart cards for offloading purpose), any type of line card
could be inserted at any slot.
The system is based on Nvidia Spectrum-3 ASIC. The switch height is 4U
and it fits standard rack size.
The next coming card generations are supposed to support:
- Line cards with 8x200Gbe QSFP28 Ethernet ports.
- Line cards with 4x400Gbe QSFP-DD Ethernet ports.
- Smart cards equipped with Nvidia ARM CPU for offloading and for fast
access to the storage (EBoF).
- Fabric cards for inter-connection.
Patch set contains:
Patch #1 – adds new types for modular system support.
Patch #2 - adds support for the modular system equipped with replicable
line cards.
Patches #3-#4 - extend logic for hotplug devices operations for the
modular system support.
Patch #5 - extends number of hwmon attributes for mlxreg-io driver,
since modular system introduces more attributes.
Patch #6 - adds field for security access validation.
Patch #7 - introduces initial support for Mellanox line card devices.
Patches #8-#9 – add documentation.
Patch #10 - extend support for cooling devices.
Vadim Pasternak (10):
platform_data/mlxreg: Add new type to support modular systems
platform/x86: mlx-platform: Add initial support for new modular system
platform/mellanox: mlxreg-hotplug: Extend logic for hotplug devices
operations
platform/x86: mlx-platform: Configure notifier callbacks for modular
system
platform/mellanox: mlxreg-io: Extend number of hwmon attributes
platform_data/mlxreg: Add new field for secured access
platform/mellanox: mlxreg-lc: Add initial support for Nvidia line card
devices
Documentation/ABI: Add new attributes for mlxreg-io sysfs interfaces
Documentation/ABI: Add new line card attributes for mlxreg-io sysfs
interfaces
platform/x86: mlx-platform: Add support for multiply cooling devices
.../ABI/stable/sysfs-driver-mlxreg-io | 241 ++
drivers/platform/mellanox/Kconfig | 12 +
drivers/platform/mellanox/Makefile | 1 +
drivers/platform/mellanox/mlxreg-hotplug.c | 123 +-
drivers/platform/mellanox/mlxreg-io.c | 2 +-
drivers/platform/mellanox/mlxreg-lc.c | 906 +++++++
drivers/platform/x86/mlx-platform.c | 2279 +++++++++++++++--
include/linux/platform_data/mlxreg.h | 82 +
8 files changed, 3351 insertions(+), 295 deletions(-)
create mode 100644 drivers/platform/mellanox/mlxreg-lc.c
--
2.20.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH platform-next 01/10] platform_data/mlxreg: Add new type to support modular systems 2021-10-02 9:32 [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system Vadim Pasternak @ 2021-10-02 9:32 ` Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 02/10] platform/x86: mlx-platform: Add initial support for new modular system Vadim Pasternak ` (7 subsequent siblings) 8 siblings, 0 replies; 13+ messages in thread From: Vadim Pasternak @ 2021-10-02 9:32 UTC (permalink / raw) To: hdegoede; +Cc: platform-driver-x86, michaelsh, Vadim Pasternak Add new types for the Nvidia modular systems MSN4800 which could be equipped with the different types of replaceable line cards. Add new type to specify the kind of hotplug events for the line cards. The line card events are generated by the programmable device located on the main board. This device implements interrupt controller logic. Line card interrupts are associated with different line cards states during its initialization: insertion, security signature validation, power good state, security validation, hardware-firmware synchronization state, line card PHYs readiness state, firmware availability for line card ports. Also under some circumstances hardware can generate thermal shutdown for particular line card. Add new type specifying the action, which should be performed when particular hotplug event is received. This action defines in which way hotplug event should be handled by hotplug driver. There are the next actions types: - Connect I2C device with empty 'platform_data' field according to the platform topology, if device is configured (for example, power unit micro-controller driver, when power unit is connected to power source (this is what is currently supported). - Connect device with 'platform_data' field set according to the platform topology. The purpose is to pass 'platform_data' through hotplug driver to underlying device (for example line card driver). - No device is associated with hotplug event - just send "udev" event (this is what is currently supported). Extend structure 'mlxreg_hotplug_device' with hotplug action field. Extend structure 'mlxreg_core_data' with: - Registers for line card power and enabling control. - Slot number field, to indicate at which physical slot replaceable line card device is located. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> --- include/linux/platform_data/mlxreg.h | 57 ++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index 101333fe2b8d..49f0e15a10dd 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -24,6 +24,51 @@ enum mlxreg_wdt_type { MLX_WDT_TYPE3, }; +/** + * enum mlxreg_hotplug_kind - kind of hotplug entry + * + * @MLXREG_HOTPLUG_DEVICE_NA: do not care; + * @MLXREG_HOTPLUG_LC_PRESENT: entry for line card presence in/out events; + * @MLXREG_HOTPLUG_LC_VERIFIED: entry for line card verification status events + * coming after line card security signature validation; + * @MLXREG_HOTPLUG_LC_POWERED: entry for line card power on/off events; + * @MLXREG_HOTPLUG_LC_SYNCED: entry for line card synchronization events, coming + * after hardware-firmware synchronization handshake; + * @MLXREG_HOTPLUG_LC_READY: entry for line card ready events, indicating line card + PHYs ready / unready state; + * @MLXREG_HOTPLUG_LC_ACTIVE: entry for line card active events, indicating firmware + * availability / unavailability for the ports on line card; + * @MLXREG_HOTPLUG_LC_THERMAL: entry for line card thermal shutdown events, positive + * event indicates that system should power off the line + * card for which this event has been received; + */ +enum mlxreg_hotplug_kind { + MLXREG_HOTPLUG_DEVICE_NA = 0, + MLXREG_HOTPLUG_LC_PRESENT = 1, + MLXREG_HOTPLUG_LC_VERIFIED = 2, + MLXREG_HOTPLUG_LC_POWERED = 3, + MLXREG_HOTPLUG_LC_SYNCED = 4, + MLXREG_HOTPLUG_LC_READY = 5, + MLXREG_HOTPLUG_LC_ACTIVE = 6, + MLXREG_HOTPLUG_LC_THERMAL = 7, +}; + +/** + * enum mlxreg_hotplug_device_action - hotplug device action required for + * driver's connectivity + * + * @MLXREG_HOTPLUG_DEVICE_DEFAULT_ACTION: probe device for 'on' event, remove + * for 'off' event; + * @MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION: probe platform device for 'on' + * event, remove for 'off' event; + * @MLXREG_HOTPLUG_DEVICE_NO_ACTION: no connectivity action is required; + */ +enum mlxreg_hotplug_device_action { + MLXREG_HOTPLUG_DEVICE_DEFAULT_ACTION = 0, + MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION = 1, + MLXREG_HOTPLUG_DEVICE_NO_ACTION = 2, +}; + /** * struct mlxreg_hotplug_device - I2C device data: * @@ -31,6 +76,7 @@ enum mlxreg_wdt_type { * @client: I2C device client; * @brdinfo: device board information; * @nr: I2C device adapter number, to which device is to be attached; + * @action: action to be performed upon event receiving; * * Structure represents I2C hotplug device static data (board topology) and * dynamic data (related kernel objects handles). @@ -40,6 +86,7 @@ struct mlxreg_hotplug_device { struct i2c_client *client; struct i2c_board_info *brdinfo; int nr; + enum mlxreg_hotplug_device_action action; }; /** @@ -51,12 +98,16 @@ struct mlxreg_hotplug_device { * @bit: attribute effective bit; * @capability: attribute capability register; * @reg_prsnt: attribute presence register; + * @reg_sync: attribute synch register; + * @reg_pwr: attribute power register; + * @reg_ena: attribute enable register; * @mode: access mode; * @np - pointer to node platform associated with attribute; * @hpdev - hotplug device data; * @health_cntr: dynamic device health indication counter; * @attached: true if device has been attached after good health indication; * @regnum: number of registers occupied by multi-register attribute; + * @slot: slot number, at which device is located; */ struct mlxreg_core_data { char label[MLXREG_CORE_LABEL_MAX_SIZE]; @@ -65,18 +116,23 @@ struct mlxreg_core_data { u32 bit; u32 capability; u32 reg_prsnt; + u32 reg_sync; + u32 reg_pwr; + u32 reg_ena; umode_t mode; struct device_node *np; struct mlxreg_hotplug_device hpdev; u32 health_cntr; bool attached; u8 regnum; + u8 slot; }; /** * struct mlxreg_core_item - same type components controlled by the driver: * * @data: component data; + * @kind: kind of hotplug attribute; * @aggr_mask: group aggregation mask; * @reg: group interrupt status register; * @mask: group interrupt mask; @@ -89,6 +145,7 @@ struct mlxreg_core_data { */ struct mlxreg_core_item { struct mlxreg_core_data *data; + enum mlxreg_hotplug_kind kind; u32 aggr_mask; u32 reg; u32 mask; -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH platform-next 02/10] platform/x86: mlx-platform: Add initial support for new modular system 2021-10-02 9:32 [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 01/10] platform_data/mlxreg: Add new type to support modular systems Vadim Pasternak @ 2021-10-02 9:32 ` Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 03/10] platform/mellanox: mlxreg-hotplug: Extend logic for hotplug devices operations Vadim Pasternak ` (6 subsequent siblings) 8 siblings, 0 replies; 13+ messages in thread From: Vadim Pasternak @ 2021-10-02 9:32 UTC (permalink / raw) To: hdegoede; +Cc: platform-driver-x86, michaelsh, Vadim Pasternak Add initial chassis management support for Nvidia modular Ethernet switch systems MSN4800, providing a high performance switching solution for Enterprise Data Centers (EDC) for building Ethernet based clusters, High-Performance Computing (HPC) and embedded environments. This system could be equipped with the different types of replaceable line cards and management board. The first system flavor will support the line card type MSN4800-C16 equipped with Lattice CPLD devices aimed for system and ASIC control, one Nvidia FPGA for gearboxes (PHYs) management, and four Nvidia gearboxes for the port control and with 16x100GbE QSFP28 ports and also with various devices for electrical control. The system is equipped with eight slots for line cards, four slots for power supplies and six slots for fans. It could be configured as fully populated or with even only one line card. The line cards are hot-pluggable. In the future when more line card flavors are to be available (for example line cards with 8x200Gb Eth port, with 4x400 Eth ports, or with some kind of smart cards for offloading purpose), any type of line card could be inserted at any slot. The system is based on Nvidia Spectrum-3 ASIC. The switch height is 4U and it fits standard rack size. System could be configured as fully populated or with even only one line card. The line cards are hot-pluggable. Line cards are connected to the chassis through I2C interface for the chassis management operations and through PCIe for the networking operations. Future line cards could be connected to the chassis through InfiniBand fabric, instead of PCIe. The first type of line card supports 16x100GbE QSFP28 Ethernet ports. Those line cards equipped with the programmable devices aimed for system control of Nvidia Ethernet switch ASIC control, Nvidia FPGA, Nvidia gearboxes (PHYs). The next coming card generations are supposed to support: - Line cards with 8x200Gbe QSFP28 Ethernet ports. - Line cards with 4x400Gbe QSFP-DD Ethernet ports. - Smart cards equipped with Nvidia ARM CPU for offloading and for fast access to the storage (EBoF). - Fabric cards for inter-connection. The basic system initialization flow with input signals from the programmable device to kernel hotplug driver and with OS response to some of these signals is depicted below. lc#n_prsnt *-> Input: line card presence in/out events. Informational event. Required action - 'udev' event generation for logging. lc#n_verified *-> Input: line card verification status events coming after line card security signature validation by hardware. Required action - connect line card driver and initialized line card devices feeding from system auxiliary power domain. lc#n_pwr <-* Output: line card power on / off from OS. Action should be performed by platform power management driver. lc#n_powered *-> Input: line card power on/off events coming after line card "power good" on/off events, mean that line card power up sequence has been successfully completed or line card "power good" status has been dropped. Required action - connect line card devices feeding from system main power domain. lc#n_synced *-> Input: line card synchronization events, coming after hardware-firmware synchronization handshake. Required action - to enable line card, in case lc#n_ready has been received before. lc#n_ready *-> Input: line card ready events, indicating line card PHYs ready / unready states. Required action - enable line card, in case lc#n_synced has been received before. lc#n_enable <-* Output: line card enable from OS - release FPGA and PHYs line card devices from reset state. Action should be performed by platform power management driver. lc#n_active *-> Input: when line card "active event" is received for particular line card, its network, hardware monitoring and thermal interfaces should be configured according to the configuration obtained from the firmware. When opposite "inactive event" is received all the above interfaces should be teared down. Required action - connect / disconnect the above line card interfaces through ASIC I2C chassis management driver. For initial support: - Define new system type 'VMOD0011' to support new modular system. - Provide initial platform configuration for new system type. - Extend the registers definitions. - Add support for modular system registers related to line card specific events - insertion/removal, power on/off, verification and activation. - Add hotplug configuration for the above events. - Add configurations for hotplug actions for the modular system. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> --- drivers/platform/x86/mlx-platform.c | 2171 +++++++++++++++++++++++---- 1 file changed, 1911 insertions(+), 260 deletions(-) diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index 8bce3da32a42..a30af1fc5c75 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -30,6 +30,7 @@ #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a +#define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f @@ -38,13 +39,20 @@ #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 +#define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 +#define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b +#define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e +#define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33 +#define MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE 0x34 +#define MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET 0x35 +#define MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET 0x36 #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b @@ -57,15 +65,39 @@ #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 +#define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56 +#define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57 #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 +#define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 +#define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 +#define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a +#define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a +#define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b +#define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c +#define MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET 0x9d +#define MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET 0x9e +#define MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET 0x9f +#define MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET 0xa0 +#define MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET 0xa1 +#define MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET 0xa2 +#define MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET 0xa3 +#define MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET 0xa4 +#define MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET 0xa5 +#define MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET 0xa6 +#define MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET 0xa7 +#define MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET 0xa8 +#define MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET 0xa9 +#define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa +#define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab +#define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 @@ -99,12 +131,14 @@ #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 #define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8 #define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9 +#define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0xfa #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda #define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc +#define MLXPLAT_CPLD_LPC_I2C_CH4_OFF 0xdd #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ @@ -116,6 +150,9 @@ #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \ MLXPLAT_CPLD_LPC_PIO_OFFSET) +#define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ + MLXPLAT_CPLD_LPC_I2C_CH4_OFF) | \ + MLXPLAT_CPLD_LPC_PIO_OFFSET) /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ #define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04 @@ -128,6 +165,24 @@ #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01 #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) +#define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3) +#define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ + MLXPLAT_CPLD_AGGR_MASK_COMEX | \ + MLXPLAT_CPLD_AGGR_MASK_LC) +#define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0) +#define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1) +#define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2) +#define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3) +#define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4) +#define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5) +#define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6) +#define MLXPLAT_CPLD_AGGR_MASK_LC_LOW (MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT | \ + MLXPLAT_CPLD_AGGR_MASK_LC_RDY | \ + MLXPLAT_CPLD_AGGR_MASK_LC_PG | \ + MLXPLAT_CPLD_AGGR_MASK_LC_SCRD | \ + MLXPLAT_CPLD_AGGR_MASK_LC_SYNC | \ + MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \ + MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) @@ -149,6 +204,9 @@ MLXPLAT_CPLD_AGGR_MASK_CARRIER) #define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1 +/* Masks for aggregation for modular systems */ +#define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) + /* Default I2C parent bus number */ #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 @@ -163,9 +221,12 @@ #define MLXPLAT_CPLD_CH1 2 #define MLXPLAT_CPLD_CH2 10 #define MLXPLAT_CPLD_CH3 18 +#define MLXPLAT_CPLD_CH2_ETH_MODULAR 3 +#define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 +#define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 /* Number of LPC attached MUX platform devices */ -#define MLXPLAT_CPLD_LPC_MUX_DEVS 3 +#define MLXPLAT_CPLD_LPC_MUX_DEVS 4 /* Hotplug devices adapter numbers */ #define MLXPLAT_CPLD_NR_NONE -1 @@ -175,6 +236,11 @@ #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 +#define MLXPLAT_CPLD_NR_ASIC 3 +#define MLXPLAT_CPLD_NR_LC_BASE 34 + +#define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr)) +#define MLXPLAT_CPLD_LC_ADDR 0x32 /* Masks and default values for watchdogs */ #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) @@ -190,6 +256,11 @@ #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 +#define MLXPLAT_CPLD_LPC_SYSIRQ 17 + +/* Minimum power required for turning on Ethernet modular system (WATT) */ +#define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50 + /* mlxplat_priv - platform private data * @pdev_i2c - i2c controller platform device * @pdev_mux - array of mux platform devices @@ -318,6 +389,58 @@ static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { }; +/* Platform channels for modular system family */ +static const int mlxplat_modular_upper_channel[] = { 1 }; +static const int mlxplat_modular_channels[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, + 38, 39, 40 +}; + +/* Platform modular mux data */ +static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = { + { + .parent = 1, + .base_nr = MLXPLAT_CPLD_CH1, + .write_only = 1, + .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG4, + .reg_size = 1, + .idle_in_use = 1, + .values = mlxplat_modular_upper_channel, + .n_values = ARRAY_SIZE(mlxplat_modular_upper_channel), + }, + { + .parent = 1, + .base_nr = MLXPLAT_CPLD_CH2_ETH_MODULAR, + .write_only = 1, + .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, + .reg_size = 1, + .idle_in_use = 1, + .values = mlxplat_modular_channels, + .n_values = ARRAY_SIZE(mlxplat_modular_channels), + }, + { + .parent = MLXPLAT_CPLD_CH1, + .base_nr = MLXPLAT_CPLD_CH3_ETH_MODULAR, + .write_only = 1, + .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, + .reg_size = 1, + .idle_in_use = 1, + .values = mlxplat_msn21xx_channels, + .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), + }, + { + .parent = 1, + .base_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR, + .write_only = 1, + .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, + .reg_size = 1, + .idle_in_use = 1, + .values = mlxplat_msn21xx_channels, + .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), + }, +}; + /* Platform hotplug devices */ static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { { @@ -968,245 +1091,1003 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, }; -/* Platform led default data */ -static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { +static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { { - .label = "status:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "pwr1", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(0), + .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, }, { - .label = "status:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + .label = "pwr2", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(1), + .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, }, { - .label = "psu:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "pwr3", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(2), + .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, }, { - .label = "psu:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "pwr4", + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = BIT(3), + .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, }, +}; + +static +struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = { + .irq = MLXPLAT_CPLD_LPC_SYSIRQ, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_modular_asic_items_data[] = { { - .label = "fan1:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "asic1", + .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, + .mask = MLXPLAT_CPLD_ASIC_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, }, +}; + +static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = { { - .label = "fan1:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), + .platform_data = &mlxplat_mlxcpld_lc_act, }, { - .label = "fan2:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), + .platform_data = &mlxplat_mlxcpld_lc_act, }, { - .label = "fan2:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), + .platform_data = &mlxplat_mlxcpld_lc_act, }, { - .label = "fan3:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), + .platform_data = &mlxplat_mlxcpld_lc_act, }, { - .label = "fan3:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), + .platform_data = &mlxplat_mlxcpld_lc_act, }, { - .label = "fan4:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), + .platform_data = &mlxplat_mlxcpld_lc_act, }, { - .label = "fan4:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), + .platform_data = &mlxplat_mlxcpld_lc_act, }, -}; - -static struct mlxreg_core_platform_data mlxplat_default_led_data = { - .data = mlxplat_mlxcpld_default_led_data, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), -}; - -/* Platform led MSN21xx system family data */ -static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { { - .label = "status:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), + .platform_data = &mlxplat_mlxcpld_lc_act, }, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { { - .label = "status:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + .label = "lc1_present", + .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, + .mask = BIT(0), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 1, }, { - .label = "fan:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "lc2_present", + .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, + .mask = BIT(1), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 2, }, { - .label = "fan:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "lc3_present", + .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, + .mask = BIT(2), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 3, }, { - .label = "psu1:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "lc4_present", + .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, + .mask = BIT(3), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 4, }, { - .label = "psu1:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "lc5_present", + .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, + .mask = BIT(4), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 5, }, { - .label = "psu2:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "lc6_present", + .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, + .mask = BIT(5), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 6, }, { - .label = "psu2:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "lc7_present", + .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, + .mask = BIT(6), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 7, }, { - .label = "uid:blue", - .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "lc8_present", + .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, + .mask = BIT(7), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 8, }, }; -static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { - .data = mlxplat_mlxcpld_msn21xx_led_data, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), -}; - -/* Platform led for default data for 200GbE systems */ -static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { +static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { { - .label = "status:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "lc1_verified", + .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, + .mask = BIT(0), + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .slot = 1, + }, + { + .label = "lc2_verified", + .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, + .mask = BIT(1), + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .slot = 2, + }, + { + .label = "lc3_verified", + .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, + .mask = BIT(2), + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .slot = 3, + }, + { + .label = "lc4_verified", + .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, + .mask = BIT(3), + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .slot = 4, + }, + { + .label = "lc5_verified", + .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, + .mask = BIT(4), + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .slot = 5, + }, + { + .label = "lc6_verified", + .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, + .mask = BIT(5), + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .slot = 6, + }, + { + .label = "lc7_verified", + .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, + .mask = BIT(6), + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .slot = 7, + }, + { + .label = "lc8_verified", + .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, + .mask = BIT(7), + .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .slot = 8, }, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { { - .label = "status:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + .label = "lc1_powered", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .mask = BIT(0), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 1, }, { - .label = "psu:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "lc2_powered", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .mask = BIT(1), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 2, }, { - .label = "psu:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "lc3_powered", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .mask = BIT(2), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 3, }, { - .label = "fan1:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(0), + .label = "lc4_powered", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .mask = BIT(3), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 4, }, { - .label = "fan1:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(0), + .label = "lc5_powered", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .mask = BIT(4), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 5, }, { - .label = "fan2:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(1), + .label = "lc6_powered", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .mask = BIT(5), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 6, }, { - .label = "fan2:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(1), + .label = "lc7_powered", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .mask = BIT(6), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 7, }, { - .label = "fan3:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(2), + .label = "lc8_powered", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .mask = BIT(7), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 8, }, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { { - .label = "fan3:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(2), + .label = "lc1_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(0), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 1, }, { - .label = "fan4:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(3), + .label = "lc2_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(1), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 2, }, { - .label = "fan4:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(3), + .label = "lc3_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(2), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 3, }, { - .label = "fan5:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(4), + .label = "lc4_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(3), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 4, }, { - .label = "fan5:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(4), + .label = "lc5_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(4), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 5, }, { - .label = "fan6:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(5), + .label = "lc6_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(5), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 6, }, { - .label = "fan6:orange", - .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - .bit = BIT(5), + .label = "lc7_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(6), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 7, }, { - .label = "uid:blue", - .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "lc8_ready", + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = BIT(7), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 8, }, }; -static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { - .data = mlxplat_mlxcpld_default_ng_led_data, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), +static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { + { + .label = "lc1_synced", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(0), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 1, + }, + { + .label = "lc2_synced", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(1), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 2, + }, + { + .label = "lc3_synced", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(2), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 3, + }, + { + .label = "lc4_synced", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(3), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 4, + }, + { + .label = "lc5_synced", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(4), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 5, + }, + { + .label = "lc6_synced", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(5), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 6, + }, + { + .label = "lc7_synced", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(6), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 7, + }, + { + .label = "lc8_synced", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = BIT(7), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 8, + }, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { + { + .label = "lc1_active", + .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, + .mask = BIT(0), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 1, + }, + { + .label = "lc2_active", + .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, + .mask = BIT(1), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 2, + }, + { + .label = "lc3_active", + .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, + .mask = BIT(2), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 3, + }, + { + .label = "lc4_active", + .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, + .mask = BIT(3), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 4, + }, + { + .label = "lc5_active", + .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, + .mask = BIT(4), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 5, + }, + { + .label = "lc6_active", + .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, + .mask = BIT(5), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 6, + }, + { + .label = "lc7_active", + .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, + .mask = BIT(6), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 7, + }, + { + .label = "lc8_active", + .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, + .mask = BIT(7), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 8, + }, +}; + +static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { + { + .label = "lc1_shutdown", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, + .mask = BIT(0), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 1, + }, + { + .label = "lc2_shutdown", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, + .mask = BIT(1), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 2, + }, + { + .label = "lc3_shutdown", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, + .mask = BIT(2), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 3, + }, + { + .label = "lc4_shutdown", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, + .mask = BIT(3), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 4, + }, + { + .label = "lc5_shutdown", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, + .mask = BIT(4), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 5, + }, + { + .label = "lc6_shutdown", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, + .mask = BIT(5), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 6, + }, + { + .label = "lc7_shutdown", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, + .mask = BIT(6), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 7, + }, + { + .label = "lc8_shutdown", + .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, + .mask = BIT(7), + .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], + .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), + .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .slot = 8, + }, +}; + +static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = { + { + .data = mlxplat_mlxcpld_ext_psu_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, + .mask = MLXPLAT_CPLD_PSU_EXT_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_modular_pwr_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, + .mask = MLXPLAT_CPLD_PWR_EXT_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), + .inversed = 0, + .health = false, + }, + { + .data = mlxplat_mlxcpld_default_ng_fan_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = MLXPLAT_CPLD_FAN_NG_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_modular_asic_items_data, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, + .mask = MLXPLAT_CPLD_ASIC_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_asic_items_data), + .inversed = 0, + .health = true, + }, + { + .data = mlxplat_mlxcpld_modular_lc_pr_items_data, + .kind = MLXREG_HOTPLUG_LC_PRESENT, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, + .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, + .mask = MLXPLAT_CPLD_LPC_LC_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pr_items_data), + .inversed = 1, + .health = false, + }, + { + .data = mlxplat_mlxcpld_modular_lc_ver_items_data, + .kind = MLXREG_HOTPLUG_LC_VERIFIED, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, + .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, + .mask = MLXPLAT_CPLD_LPC_LC_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ver_items_data), + .inversed = 0, + .health = false, + }, + { + .data = mlxplat_mlxcpld_modular_lc_pg_data, + .kind = MLXREG_HOTPLUG_LC_POWERED, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, + .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, + .mask = MLXPLAT_CPLD_LPC_LC_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pg_data), + .inversed = 0, + .health = false, + }, + { + .data = mlxplat_mlxcpld_modular_lc_ready_data, + .kind = MLXREG_HOTPLUG_LC_READY, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, + .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, + .mask = MLXPLAT_CPLD_LPC_LC_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ready_data), + .inversed = 0, + .health = false, + }, + { + .data = mlxplat_mlxcpld_modular_lc_synced_data, + .kind = MLXREG_HOTPLUG_LC_SYNCED, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, + .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, + .mask = MLXPLAT_CPLD_LPC_LC_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_synced_data), + .inversed = 0, + .health = false, + }, + { + .data = mlxplat_mlxcpld_modular_lc_act_data, + .kind = MLXREG_HOTPLUG_LC_ACTIVE, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, + .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, + .mask = MLXPLAT_CPLD_LPC_LC_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_act_data), + .inversed = 0, + .health = false, + }, + { + .data = mlxplat_mlxcpld_modular_lc_sd_data, + .kind = MLXREG_HOTPLUG_LC_THERMAL, + .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, + .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, + .mask = MLXPLAT_CPLD_LPC_LC_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_sd_data), + .inversed = 0, + .health = false, + }, +}; + +static +struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { + .items = mlxplat_mlxcpld_modular_items, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_MODULAR, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, +}; + +/* Platform led default data */ +static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { + { + .label = "status:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "status:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + }, + { + .label = "psu:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "psu:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan1:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan1:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan2:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan2:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan3:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan3:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan4:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan4:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, +}; + +static struct mlxreg_core_platform_data mlxplat_default_led_data = { + .data = mlxplat_mlxcpld_default_led_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), +}; + +/* Platform led MSN21xx system family data */ +static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { + { + .label = "status:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "status:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + }, + { + .label = "fan:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "psu1:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "psu1:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "psu2:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "psu2:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "uid:blue", + .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, +}; + +static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { + .data = mlxplat_mlxcpld_msn21xx_led_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), +}; + +/* Platform led for default data for 200GbE systems */ +static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { + { + .label = "status:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "status:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + }, + { + .label = "psu:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "psu:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan1:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(0), + }, + { + .label = "fan1:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(0), + }, + { + .label = "fan2:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(1), + }, + { + .label = "fan2:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(1), + }, + { + .label = "fan3:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(2), + }, + { + .label = "fan3:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(2), + }, + { + .label = "fan4:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(3), + }, + { + .label = "fan4:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(3), + }, + { + .label = "fan5:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(4), + }, + { + .label = "fan5:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(4), + }, + { + .label = "fan6:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(5), + }, + { + .label = "fan6:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(5), + }, + { + .label = "uid:blue", + .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, +}; + +static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { + .data = mlxplat_mlxcpld_default_ng_led_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), }; /* Platform led for Comex based 100GbE systems */ @@ -1232,59 +2113,343 @@ static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, }, { - .label = "fan1:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "fan1:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan1:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan2:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan2:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan3:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan3:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan4:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan4:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "uid:blue", + .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, +}; + +static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { + .data = mlxplat_mlxcpld_comex_100G_led_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), +}; + +/* Platform led for data for modular systems */ +static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { + { + .label = "status:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "status:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + }, + { + .label = "psu:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "psu:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { + .label = "fan1:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(0), + }, + { + .label = "fan1:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(0), + }, + { + .label = "fan2:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(1), + }, + { + .label = "fan2:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(1), + }, + { + .label = "fan3:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(2), + }, + { + .label = "fan3:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(2), + }, + { + .label = "fan4:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(3), + }, + { + .label = "fan4:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(3), + }, + { + .label = "fan5:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(4), + }, + { + .label = "fan5:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(4), + }, + { + .label = "fan6:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(5), + }, + { + .label = "fan6:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(5), + }, + { + .label = "fan7:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(6), + }, + { + .label = "fan7:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(6), + }, + { + .label = "uid:blue", + .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan_front:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "fan_front:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "mgmt:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { + .label = "mgmt:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, +}; + +static struct mlxreg_core_platform_data mlxplat_modular_led_data = { + .data = mlxplat_mlxcpld_modular_led_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data), +}; + +/* Platform register access default */ +static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { + { + .label = "cpld1_version", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "cpld2_version", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "cpld1_pn", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, + { + .label = "cpld2_pn", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, + { + .label = "cpld1_version_min", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "cpld2_version_min", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "reset_long_pb", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { + .label = "reset_short_pb", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0444, + }, + { + .label = "reset_aux_pwr_or_ref", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { + .label = "reset_main_pwr_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { + .label = "reset_sw_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, }, { - .label = "fan1:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "reset_fw_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, }, { - .label = "fan2:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "reset_hotswap_or_wd", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, }, { - .label = "fan2:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "reset_asic_thermal", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, }, { - .label = "fan3:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "psu1_on", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0200, }, { - .label = "fan3:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "psu2_on", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0200, }, { - .label = "fan4:green", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "pwr_cycle", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0200, }, { - .label = "fan4:red", - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .label = "pwr_down", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0200, }, { - .label = "uid:blue", - .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .label = "select_iio", + .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0644, + }, + { + .label = "asic_health", + .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, + .mask = MLXPLAT_CPLD_ASIC_MASK, + .bit = 1, + .mode = 0444, }, }; -static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { - .data = mlxplat_mlxcpld_comex_100G_led_data, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), +static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { + .data = mlxplat_mlxcpld_default_regs_io_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), }; -/* Platform register access default */ -static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { +/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ +static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { { .label = "cpld1_version", .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, @@ -1342,33 +2507,33 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { .mode = 0444, }, { - .label = "reset_main_pwr_fail", + .label = "reset_sw_reset", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, .mask = GENMASK(7, 0) & ~BIT(3), .mode = 0444, }, { - .label = "reset_sw_reset", + .label = "reset_main_pwr_fail", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, .mask = GENMASK(7, 0) & ~BIT(4), .mode = 0444, }, { - .label = "reset_fw_reset", + .label = "reset_asic_thermal", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, .mask = GENMASK(7, 0) & ~BIT(5), .mode = 0444, }, { - .label = "reset_hotswap_or_wd", + .label = "reset_hotswap_or_halt", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, .mask = GENMASK(7, 0) & ~BIT(6), .mode = 0444, }, { - .label = "reset_asic_thermal", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(7), + .label = "reset_sff_wd", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), .mode = 0444, }, { @@ -1410,13 +2575,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { }, }; -static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { - .data = mlxplat_mlxcpld_default_regs_io_data, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), +static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { + .data = mlxplat_mlxcpld_msn21xx_regs_io_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), }; -/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ -static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { +/* Platform register access for next generation systems families data */ +static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { { .label = "cpld1_version", .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, @@ -1429,6 +2594,18 @@ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { .bit = GENMASK(7, 0), .mode = 0444, }, + { + .label = "cpld3_version", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "cpld4_version", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, { .label = "cpld1_pn", .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, @@ -1443,6 +2620,20 @@ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { .mode = 0444, .regnum = 2, }, + { + .label = "cpld3_pn", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, + { + .label = "cpld4_pn", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, { .label = "cpld1_version_min", .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, @@ -1455,6 +2646,18 @@ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { .bit = GENMASK(7, 0), .mode = 0444, }, + { + .label = "cpld3_version_min", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "cpld4_version_min", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, { .label = "reset_long_pb", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, @@ -1474,32 +2677,86 @@ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { .mode = 0444, }, { - .label = "reset_sw_reset", + .label = "reset_from_comex", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(3), + .mask = GENMASK(7, 0) & ~BIT(4), .mode = 0444, }, { - .label = "reset_main_pwr_fail", + .label = "reset_from_asic", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(4), + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { + .label = "reset_swb_wd", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), .mode = 0444, }, { .label = "reset_asic_thermal", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { + .label = "reset_comex_pwr_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { + .label = "reset_platform", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { + .label = "reset_soc", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, .mask = GENMASK(7, 0) & ~BIT(5), .mode = 0444, }, { - .label = "reset_hotswap_or_halt", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .label = "reset_comex_wd", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, .mask = GENMASK(7, 0) & ~BIT(6), .mode = 0444, }, { - .label = "reset_sff_wd", - .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .label = "reset_voltmon_upgrade_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { + .label = "reset_system", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0444, + }, + { + .label = "reset_sw_pwr_off", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { + .label = "reset_comex_thermal", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { + .label = "reset_reload_bios", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { + .label = "reset_ac_pwr_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, .mask = GENMASK(7, 0) & ~BIT(6), .mode = 0444, }, @@ -1528,27 +2785,70 @@ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { .mode = 0200, }, { - .label = "select_iio", + .label = "jtag_enable", .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(6), + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { + .label = "asic_health", + .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, + .mask = MLXPLAT_CPLD_ASIC_MASK, + .bit = 1, + .mode = 0444, + }, + { + .label = "fan_dir", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "voltreg_update_status", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, + .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, + .bit = 5, + .mode = 0444, + }, + { + .label = "vpd_wp", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, + { + .label = "pcie_asic_reset_dis", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), .mode = 0644, }, { - .label = "asic_health", - .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, - .mask = MLXPLAT_CPLD_ASIC_MASK, - .bit = 1, + .label = "config1", + .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "config2", + .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "ufm_version", + .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, + .bit = GENMASK(7, 0), .mode = 0444, }, }; -static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { - .data = mlxplat_mlxcpld_msn21xx_regs_io_data, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), +static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { + .data = mlxplat_mlxcpld_default_ng_regs_io_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), }; -/* Platform register access for next generation systems families data */ -static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { +/* Platform register access for modular systems families data */ +static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { { .label = "cpld1_version", .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, @@ -1625,6 +2925,54 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .bit = GENMASK(7, 0), .mode = 0444, }, + { + .label = "lc1_enable", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, + { + .label = "lc2_enable", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { + .label = "lc3_enable", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0644, + }, + { + .label = "lc4_enable", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, + { + .label = "lc5_enable", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { + .label = "lc6_enable", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + }, + { + .label = "lc7_enable", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0644, + }, + { + .label = "lc8_enable", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0644, + }, { .label = "reset_long_pb", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, @@ -1638,33 +2986,33 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .mode = 0444, }, { - .label = "reset_aux_pwr_or_ref", + .label = "reset_aux_pwr_or_fu", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, .mask = GENMASK(7, 0) & ~BIT(2), .mode = 0444, }, { - .label = "reset_from_comex", + .label = "reset_mgmt_dc_dc_pwr_fail", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(4), + .mask = GENMASK(7, 0) & ~BIT(3), .mode = 0444, }, { - .label = "reset_from_asic", + .label = "reset_sys_comex_bios", .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, .mask = GENMASK(7, 0) & ~BIT(5), .mode = 0444, }, { - .label = "reset_swb_wd", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(6), + .label = "reset_sw_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), .mode = 0444, }, { - .label = "reset_asic_thermal", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(7), + .label = "reset_aux_pwr_or_reload", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), .mode = 0444, }, { @@ -1686,47 +3034,144 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .mode = 0444, }, { - .label = "reset_comex_wd", + .label = "reset_pwr_off_from_carrier", .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(6), + .mask = GENMASK(7, 0) & ~BIT(7), .mode = 0444, }, { - .label = "reset_voltmon_upgrade_fail", + .label = "reset_swb_wd", .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, .mask = GENMASK(7, 0) & ~BIT(0), .mode = 0444, }, { - .label = "reset_system", - .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(1), + .label = "reset_swb_aux_pwr_or_fu", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), .mode = 0444, }, { - .label = "reset_sw_pwr_off", + .label = "reset_swb_dc_dc_pwr_fail", .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(2), + .mask = GENMASK(7, 0) & ~BIT(3), .mode = 0444, }, { - .label = "reset_comex_thermal", + .label = "reset_swb_12v_fail", .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(3), + .mask = GENMASK(7, 0) & ~BIT(4), .mode = 0444, }, { - .label = "reset_reload_bios", + .label = "reset_system", .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, .mask = GENMASK(7, 0) & ~BIT(5), .mode = 0444, }, { - .label = "reset_ac_pwr_fail", + .label = "reset_thermal_spc_or_pciesw", .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { + .label = "bios_safe_mode", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { + .label = "bios_active_image", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { + .label = "bios_auth_fail", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, .mask = GENMASK(7, 0) & ~BIT(6), .mode = 0444, }, + { + .label = "bios_upgrade_fail", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { + .label = "voltreg_update_status", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, + .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, + .bit = 5, + .mode = 0444, + }, + { + .label = "vpd_wp", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, + { + .label = "pcie_asic_reset_dis", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { + .label = "shutdown_unlock", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + }, + { + .label = "lc1_rst_mask", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0200, + }, + { + .label = "lc2_rst_mask", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0200, + }, + { + .label = "lc3_rst_mask", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0200, + }, + { + .label = "lc4_rst_mask", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0200, + }, + { + .label = "lc5_rst_mask", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0200, + }, + { + .label = "lc6_rst_mask", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0200, + }, + { + .label = "lc7_rst_mask", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0200, + }, + { + .label = "lc8_rst_mask", + .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0200, + }, { .label = "psu1_on", .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, @@ -1752,9 +3197,46 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .mode = 0200, }, { - .label = "jtag_enable", - .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, + .label = "psu3_on", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0200, + }, + { + .label = "psu4_on", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0200, + }, + { + .label = "auto_power_mode", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0644, + }, + { + .label = "pm_mgmt_en", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0644, + }, + { + .label = "jtag_enable", + .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, + .mask = GENMASK(3, 0), + .bit = 1, + .mode = 0644, + }, + { + .label = "safe_bios_dis", + .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + }, + { + .label = "safe_bios_dis_wp", + .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), .mode = 0644, }, { @@ -1771,24 +3253,53 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .mode = 0444, }, { - .label = "voltreg_update_status", - .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, - .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, - .bit = 5, - .mode = 0444, + .label = "lc1_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, }, { - .label = "vpd_wp", - .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .label = "lc2_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { + .label = "lc3_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0644, + }, + { + .label = "lc4_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, .mask = GENMASK(7, 0) & ~BIT(3), .mode = 0644, }, { - .label = "pcie_asic_reset_dis", - .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .label = "lc5_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, .mask = GENMASK(7, 0) & ~BIT(4), .mode = 0644, }, + { + .label = "lc6_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + }, + { + .label = "lc7_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0644, + }, + { + .label = "lc8_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0644, + }, { .label = "config1", .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, @@ -1809,9 +3320,9 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { }, }; -static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { - .data = mlxplat_mlxcpld_default_ng_regs_io_data, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), +static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { + .data = mlxplat_mlxcpld_modular_regs_io_data, + .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), }; /* Platform FAN default */ @@ -2152,16 +3663,23 @@ static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = { static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) { switch (reg) { + case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: @@ -2174,6 +3692,23 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: @@ -2202,6 +3737,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: @@ -2210,13 +3746,20 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: @@ -2237,6 +3780,30 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: @@ -2270,6 +3837,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: + case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: @@ -2289,6 +3857,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: @@ -2297,11 +3866,18 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: @@ -2322,6 +3898,30 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: @@ -2349,6 +3949,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: + case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: @@ -2382,6 +3983,16 @@ static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, }; +static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { + { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 }, + { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET, + MLXPLAT_CPLD_AGGR_MASK_LC_LOW }, +}; + struct mlxplat_mlxcpld_regmap_context { void __iomem *base; }; @@ -2462,8 +4073,22 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { .reg_write = mlxplat_mlxcpld_reg_write, }; +static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 255, + .cache_type = REGCACHE_FLAT, + .writeable_reg = mlxplat_mlxcpld_writeable_reg, + .readable_reg = mlxplat_mlxcpld_readable_reg, + .volatile_reg = mlxplat_mlxcpld_volatile_reg, + .reg_defaults = mlxplat_mlxcpld_regmap_eth_modular, + .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_eth_modular), + .reg_read = mlxplat_mlxcpld_reg_read, + .reg_write = mlxplat_mlxcpld_reg_write, +}; + static struct resource mlxplat_mlxcpld_resources[] = { - [0] = DEFINE_RES_IRQ_NAMED(17, "mlxreg-hotplug"), + [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), }; static struct platform_device *mlxplat_dev; @@ -2640,6 +4265,26 @@ static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) return 1; } +static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) +{ + int i; + + mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; + mlxplat_mux_num = ARRAY_SIZE(mlxplat_modular_mux_data); + mlxplat_mux_data = mlxplat_modular_mux_data; + mlxplat_hotplug = &mlxplat_mlxcpld_modular_data; + mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR; + mlxplat_led = &mlxplat_modular_led_data; + mlxplat_regs_io = &mlxplat_modular_regs_io_data; + mlxplat_fan = &mlxplat_default_fan_data; + for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) + mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; + mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; + mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_eth_modular; + + return 1; +} + static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { { .callback = mlxplat_dmi_default_matched, @@ -2689,6 +4334,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), }, }, + { + .callback = mlxplat_dmi_modular_matched, + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"), + }, + }, { .callback = mlxplat_dmi_msn274x_matched, .matches = { -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH platform-next 03/10] platform/mellanox: mlxreg-hotplug: Extend logic for hotplug devices operations 2021-10-02 9:32 [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 01/10] platform_data/mlxreg: Add new type to support modular systems Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 02/10] platform/x86: mlx-platform: Add initial support for new modular system Vadim Pasternak @ 2021-10-02 9:32 ` Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 04/10] platform/x86: mlx-platform: Configure notifier callbacks for modular system Vadim Pasternak ` (5 subsequent siblings) 8 siblings, 0 replies; 13+ messages in thread From: Vadim Pasternak @ 2021-10-02 9:32 UTC (permalink / raw) To: hdegoede; +Cc: platform-driver-x86, michaelsh, Vadim Pasternak Extend the structure 'mlxreg_hotplug_device" with platform device field to allow transition of the register map and system interrupt line number to underlying hotplug devices, sharing the same register map and same interrupt line with 'mlxreg-hotplug' driver. Extend logic for hotplug devices creation and removing according to the action associated with the hotplug device description. Previously hotplug driver was capable to attach / de-attach upon hotplug events only I2C devices handled by simple I2C drivers. Now it should be able to attach also devices handled by the platform drivers. The motivation is to allow transition of platform data like: - system interrupt line number, sharing with 'mlxreg-hotplug' to underlying hotplug devices. - shared register map of programmable devices on main board to underlying hotplug devices. Additioanlly the number of 'sysfs' attributes is increased, since modular system defines more 'sysfs' attributes. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> --- drivers/platform/mellanox/mlxreg-hotplug.c | 123 +++++++++++++++------ include/linux/platform_data/mlxreg.h | 24 ++++ 2 files changed, 112 insertions(+), 35 deletions(-) diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c index b013445147dd..117bc3f395fd 100644 --- a/drivers/platform/mellanox/mlxreg-hotplug.c +++ b/drivers/platform/mellanox/mlxreg-hotplug.c @@ -28,7 +28,7 @@ /* ASIC good health mask. */ #define MLXREG_HOTPLUG_GOOD_HEALTH_MASK 0x02 -#define MLXREG_HOTPLUG_ATTRS_MAX 24 +#define MLXREG_HOTPLUG_ATTRS_MAX 128 #define MLXREG_HOTPLUG_NOT_ASSERT 3 /** @@ -89,9 +89,20 @@ mlxreg_hotplug_udev_event_send(struct kobject *kobj, return kobject_uevent_env(kobj, KOBJ_CHANGE, mlxreg_hotplug_udev_envp); } +static void +mlxreg_hotplug_pdata_export(void *pdata, void *regmap) +{ + struct mlxreg_core_hotplug_platform_data *dev_pdata = pdata; + + /* Export regmap to underlying device. */ + dev_pdata->regmap = regmap; +} + static int mlxreg_hotplug_device_create(struct mlxreg_hotplug_priv_data *priv, - struct mlxreg_core_data *data) + struct mlxreg_core_data *data, + enum mlxreg_hotplug_kind kind) { + struct i2c_board_info *brdinfo = data->hpdev.brdinfo; struct mlxreg_core_hotplug_platform_data *pdata; struct i2c_client *client; @@ -106,46 +117,88 @@ static int mlxreg_hotplug_device_create(struct mlxreg_hotplug_priv_data *priv, return 0; pdata = dev_get_platdata(&priv->pdev->dev); - data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr + - pdata->shift_nr); - if (!data->hpdev.adapter) { - dev_err(priv->dev, "Failed to get adapter for bus %d\n", - data->hpdev.nr + pdata->shift_nr); - return -EFAULT; - } + switch (data->hpdev.action) { + case MLXREG_HOTPLUG_DEVICE_DEFAULT_ACTION: + data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr + + pdata->shift_nr); + if (!data->hpdev.adapter) { + dev_err(priv->dev, "Failed to get adapter for bus %d\n", + data->hpdev.nr + pdata->shift_nr); + return -EFAULT; + } - client = i2c_new_client_device(data->hpdev.adapter, - data->hpdev.brdinfo); - if (IS_ERR(client)) { - dev_err(priv->dev, "Failed to create client %s at bus %d at addr 0x%02x\n", - data->hpdev.brdinfo->type, data->hpdev.nr + - pdata->shift_nr, data->hpdev.brdinfo->addr); + /* Export platform data to underlying device. */ + if (brdinfo->platform_data) + mlxreg_hotplug_pdata_export(brdinfo->platform_data, pdata->regmap); - i2c_put_adapter(data->hpdev.adapter); - data->hpdev.adapter = NULL; - return PTR_ERR(client); + client = i2c_new_client_device(data->hpdev.adapter, + brdinfo); + if (IS_ERR(client)) { + dev_err(priv->dev, "Failed to create client %s at bus %d at addr 0x%02x\n", + brdinfo->type, data->hpdev.nr + + pdata->shift_nr, brdinfo->addr); + + i2c_put_adapter(data->hpdev.adapter); + data->hpdev.adapter = NULL; + return PTR_ERR(client); + } + + data->hpdev.client = client; + break; + case MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION: + /* Export platform data to underlying device. */ + if (data->hpdev.brdinfo && data->hpdev.brdinfo->platform_data) + mlxreg_hotplug_pdata_export(data->hpdev.brdinfo->platform_data, + pdata->regmap); + /* Pass parent hotplug device handle to underlying device. */ + data->notifier = data->hpdev.notifier; + data->hpdev.pdev = platform_device_register_resndata(&priv->pdev->dev, + brdinfo->type, + data->hpdev.nr, + NULL, 0, data, + sizeof(*data)); + if (IS_ERR(data->hpdev.pdev)) + return PTR_ERR(data->hpdev.pdev); + + break; + default: + break; } - data->hpdev.client = client; + if (data->hpdev.notifier && data->hpdev.notifier->user_handler) + return data->hpdev.notifier->user_handler(data->hpdev.notifier->handle, kind, 1); return 0; } static void mlxreg_hotplug_device_destroy(struct mlxreg_hotplug_priv_data *priv, - struct mlxreg_core_data *data) + struct mlxreg_core_data *data, + enum mlxreg_hotplug_kind kind) { /* Notify user by sending hwmon uevent. */ mlxreg_hotplug_udev_event_send(&priv->hwmon->kobj, data, false); + if (data->hpdev.notifier && data->hpdev.notifier->user_handler) + data->hpdev.notifier->user_handler(data->hpdev.notifier->handle, kind, 0); + + switch (data->hpdev.action) { + case MLXREG_HOTPLUG_DEVICE_DEFAULT_ACTION: + if (data->hpdev.client) { + i2c_unregister_device(data->hpdev.client); + data->hpdev.client = NULL; + } - if (data->hpdev.client) { - i2c_unregister_device(data->hpdev.client); - data->hpdev.client = NULL; - } - - if (data->hpdev.adapter) { - i2c_put_adapter(data->hpdev.adapter); - data->hpdev.adapter = NULL; + if (data->hpdev.adapter) { + i2c_put_adapter(data->hpdev.adapter); + data->hpdev.adapter = NULL; + } + break; + case MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION: + if (data->hpdev.pdev) + platform_device_unregister(data->hpdev.pdev); + break; + default: + break; } } @@ -317,14 +370,14 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv, data = item->data + bit; if (regval & BIT(bit)) { if (item->inversed) - mlxreg_hotplug_device_destroy(priv, data); + mlxreg_hotplug_device_destroy(priv, data, item->kind); else - mlxreg_hotplug_device_create(priv, data); + mlxreg_hotplug_device_create(priv, data, item->kind); } else { if (item->inversed) - mlxreg_hotplug_device_create(priv, data); + mlxreg_hotplug_device_create(priv, data, item->kind); else - mlxreg_hotplug_device_destroy(priv, data); + mlxreg_hotplug_device_destroy(priv, data, item->kind); } } @@ -381,7 +434,7 @@ mlxreg_hotplug_health_work_helper(struct mlxreg_hotplug_priv_data *priv, * ASIC is in steady state. Connect associated * device, if configured. */ - mlxreg_hotplug_device_create(priv, data); + mlxreg_hotplug_device_create(priv, data, item->kind); data->attached = true; } } else { @@ -391,7 +444,7 @@ mlxreg_hotplug_health_work_helper(struct mlxreg_hotplug_priv_data *priv, * in steady state. Disconnect associated * device, if it has been connected. */ - mlxreg_hotplug_device_destroy(priv, data); + mlxreg_hotplug_device_destroy(priv, data, item->kind); data->attached = false; data->health_cntr = 0; } @@ -630,7 +683,7 @@ static void mlxreg_hotplug_unset_irq(struct mlxreg_hotplug_priv_data *priv) /* Remove all the attached devices in group. */ count = item->count; for (j = 0; j < count; j++, data++) - mlxreg_hotplug_device_destroy(priv, data); + mlxreg_hotplug_device_destroy(priv, data, item->kind); } } diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index 49f0e15a10dd..3122d550dc00 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -69,6 +69,19 @@ enum mlxreg_hotplug_device_action { MLXREG_HOTPLUG_DEVICE_NO_ACTION = 2, }; +/** + * struct mlxreg_core_hotplug_notifier - hotplug notifier block: + * + * @identity: notifier identity name; + * @handle: user handle to be passed by user handler function; + * @user_handler: user handler function associated with the event; + */ +struct mlxreg_core_hotplug_notifier { + char identity[MLXREG_CORE_LABEL_MAX_SIZE]; + void *handle; + int (*user_handler)(void *handle, enum mlxreg_hotplug_kind kind, u8 action); +}; + /** * struct mlxreg_hotplug_device - I2C device data: * @@ -76,7 +89,11 @@ enum mlxreg_hotplug_device_action { * @client: I2C device client; * @brdinfo: device board information; * @nr: I2C device adapter number, to which device is to be attached; + * @pdev: platform device, if device is instantiated as a platform device; * @action: action to be performed upon event receiving; + * @handle: user handle to be passed by user handler function; + * @user_handler: user handler function associated with the event; + * @notifier: pointer to event notifier block; * * Structure represents I2C hotplug device static data (board topology) and * dynamic data (related kernel objects handles). @@ -86,7 +103,11 @@ struct mlxreg_hotplug_device { struct i2c_client *client; struct i2c_board_info *brdinfo; int nr; + struct platform_device *pdev; enum mlxreg_hotplug_device_action action; + void *handle; + int (*user_handler)(void *handle, enum mlxreg_hotplug_kind kind, u8 action); + struct mlxreg_core_hotplug_notifier *notifier; }; /** @@ -104,10 +125,12 @@ struct mlxreg_hotplug_device { * @mode: access mode; * @np - pointer to node platform associated with attribute; * @hpdev - hotplug device data; + * @notifier: pointer to event notifier block; * @health_cntr: dynamic device health indication counter; * @attached: true if device has been attached after good health indication; * @regnum: number of registers occupied by multi-register attribute; * @slot: slot number, at which device is located; + * @secured: if set indicates that entry access is secured; */ struct mlxreg_core_data { char label[MLXREG_CORE_LABEL_MAX_SIZE]; @@ -122,6 +145,7 @@ struct mlxreg_core_data { umode_t mode; struct device_node *np; struct mlxreg_hotplug_device hpdev; + struct mlxreg_core_hotplug_notifier *notifier; u32 health_cntr; bool attached; u8 regnum; -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH platform-next 04/10] platform/x86: mlx-platform: Configure notifier callbacks for modular system 2021-10-02 9:32 [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system Vadim Pasternak ` (2 preceding siblings ...) 2021-10-02 9:32 ` [PATCH platform-next 03/10] platform/mellanox: mlxreg-hotplug: Extend logic for hotplug devices operations Vadim Pasternak @ 2021-10-02 9:32 ` Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 05/10] platform/mellanox: mlxreg-io: Extend number of hwmon attributes Vadim Pasternak ` (4 subsequent siblings) 8 siblings, 0 replies; 13+ messages in thread From: Vadim Pasternak @ 2021-10-02 9:32 UTC (permalink / raw) To: hdegoede; +Cc: platform-driver-x86, michaelsh, Vadim Pasternak Add event notifier callbacks for modular system line cards. These callbacks are to be passed to "mlxreg-hotplug" driver by line card driver during probing. Then, when any line card related hotplug event is received (insertion ,power, synch, ready), hotplug driver will invoke callback for the relevant line card. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> --- drivers/platform/x86/mlx-platform.c | 83 +++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index a30af1fc5c75..2ab499686564 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -1171,6 +1171,33 @@ static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = { }, }; +static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_modular_lc_notifier[] = { + { + .identity = "lc1", + }, + { + .identity = "lc2", + }, + { + .identity = "lc3", + }, + { + .identity = "lc4", + }, + { + .identity = "lc5", + }, + { + .identity = "lc6", + }, + { + .identity = "lc7", + }, + { + .identity = "lc8", + }, +}; + static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { { .label = "lc1_present", @@ -1179,6 +1206,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], .slot = 1, }, { @@ -1188,6 +1216,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], .slot = 2, }, { @@ -1197,6 +1226,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], .slot = 3, }, { @@ -1206,6 +1236,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], .slot = 4, }, { @@ -1215,6 +1246,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], .slot = 5, }, { @@ -1224,6 +1256,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], .slot = 6, }, { @@ -1233,6 +1266,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], .slot = 7, }, { @@ -1242,6 +1276,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], .slot = 8, }, }; @@ -1258,6 +1293,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], .slot = 1, }, { @@ -1271,6 +1307,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], .slot = 2, }, { @@ -1284,6 +1321,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], .slot = 3, }, { @@ -1297,6 +1335,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], .slot = 4, }, { @@ -1310,6 +1349,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], .slot = 5, }, { @@ -1323,6 +1363,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], .slot = 6, }, { @@ -1336,6 +1377,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], .slot = 7, }, { @@ -1349,6 +1391,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], .slot = 8, }, }; @@ -1361,6 +1404,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], .slot = 1, }, { @@ -1370,6 +1414,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], .slot = 2, }, { @@ -1379,6 +1424,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], .slot = 3, }, { @@ -1388,6 +1434,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], .slot = 4, }, { @@ -1397,6 +1444,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], .slot = 5, }, { @@ -1406,6 +1454,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], .slot = 6, }, { @@ -1415,6 +1464,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], .slot = 7, }, { @@ -1424,6 +1474,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], .slot = 8, }, }; @@ -1436,6 +1487,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], .slot = 1, }, { @@ -1445,6 +1497,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], .slot = 2, }, { @@ -1454,6 +1507,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], .slot = 3, }, { @@ -1463,6 +1517,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], .slot = 4, }, { @@ -1472,6 +1527,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], .slot = 5, }, { @@ -1481,6 +1537,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], .slot = 6, }, { @@ -1490,6 +1547,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], .slot = 7, }, { @@ -1499,6 +1557,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], .slot = 8, }, }; @@ -1511,6 +1570,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], .slot = 1, }, { @@ -1520,6 +1580,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], .slot = 2, }, { @@ -1529,6 +1590,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], .slot = 3, }, { @@ -1538,6 +1600,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], .slot = 4, }, { @@ -1547,6 +1610,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], .slot = 5, }, { @@ -1556,6 +1620,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], .slot = 6, }, { @@ -1565,6 +1630,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], .slot = 7, }, { @@ -1574,6 +1640,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], .slot = 8, }, }; @@ -1586,6 +1653,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], .slot = 1, }, { @@ -1595,6 +1663,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], .slot = 2, }, { @@ -1604,6 +1673,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], .slot = 3, }, { @@ -1613,6 +1683,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], .slot = 4, }, { @@ -1622,6 +1693,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], .slot = 5, }, { @@ -1631,6 +1703,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], .slot = 6, }, { @@ -1640,6 +1713,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], .slot = 7, }, { @@ -1649,6 +1723,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], .slot = 8, }, }; @@ -1661,6 +1736,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], .slot = 1, }, { @@ -1670,6 +1746,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], .slot = 2, }, { @@ -1679,6 +1756,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], .slot = 3, }, { @@ -1688,6 +1766,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], .slot = 4, }, { @@ -1697,6 +1776,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], .slot = 5, }, { @@ -1706,6 +1786,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], .slot = 6, }, { @@ -1715,6 +1796,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], .slot = 7, }, { @@ -1724,6 +1806,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, + .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], .slot = 8, }, }; -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH platform-next 05/10] platform/mellanox: mlxreg-io: Extend number of hwmon attributes 2021-10-02 9:32 [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system Vadim Pasternak ` (3 preceding siblings ...) 2021-10-02 9:32 ` [PATCH platform-next 04/10] platform/x86: mlx-platform: Configure notifier callbacks for modular system Vadim Pasternak @ 2021-10-02 9:32 ` Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 06/10] platform_data/mlxreg: Add new field for secured access Vadim Pasternak ` (3 subsequent siblings) 8 siblings, 0 replies; 13+ messages in thread From: Vadim Pasternak @ 2021-10-02 9:32 UTC (permalink / raw) To: hdegoede; +Cc: platform-driver-x86, michaelsh, Vadim Pasternak Extend maximum number of the attributes, exposed to 'sysfs'. It is requires in order to support modular systems, which provide more attributes for system control, statuses and info. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> --- drivers/platform/mellanox/mlxreg-io.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/mellanox/mlxreg-io.c b/drivers/platform/mellanox/mlxreg-io.c index 7646708d57e4..43e9228a8fd3 100644 --- a/drivers/platform/mellanox/mlxreg-io.c +++ b/drivers/platform/mellanox/mlxreg-io.c @@ -18,7 +18,7 @@ /* Attribute parameters. */ #define MLXREG_IO_ATT_SIZE 10 -#define MLXREG_IO_ATT_NUM 48 +#define MLXREG_IO_ATT_NUM 96 /** * struct mlxreg_io_priv_data - driver's private data: -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH platform-next 06/10] platform_data/mlxreg: Add new field for secured access 2021-10-02 9:32 [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system Vadim Pasternak ` (4 preceding siblings ...) 2021-10-02 9:32 ` [PATCH platform-next 05/10] platform/mellanox: mlxreg-io: Extend number of hwmon attributes Vadim Pasternak @ 2021-10-02 9:32 ` Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 07/10] platform/mellanox: mlxreg-lc: Add initial support for Nvidia line card devices Vadim Pasternak ` (2 subsequent siblings) 8 siblings, 0 replies; 13+ messages in thread From: Vadim Pasternak @ 2021-10-02 9:32 UTC (permalink / raw) To: hdegoede; +Cc: platform-driver-x86, michaelsh, Vadim Pasternak Extend structure 'mlxreg_core_data' with the field "secured". The purpose of this field is to restrict access to some attributes, if kernel is configured with security options, like: LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY. Access to some attributes, which for example, allow burning of some hardware components, like FPGA, CPLD, SPI, etcetera can break the system. In case user does not want to allow such access, it can disable it by setting security options. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> --- include/linux/platform_data/mlxreg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index 3122d550dc00..40185f9d7c14 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -150,6 +150,7 @@ struct mlxreg_core_data { bool attached; u8 regnum; u8 slot; + u8 secured; }; /** -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH platform-next 07/10] platform/mellanox: mlxreg-lc: Add initial support for Nvidia line card devices 2021-10-02 9:32 [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system Vadim Pasternak ` (5 preceding siblings ...) 2021-10-02 9:32 ` [PATCH platform-next 06/10] platform_data/mlxreg: Add new field for secured access Vadim Pasternak @ 2021-10-02 9:32 ` Vadim Pasternak [not found] ` <76a93a22-a3ff-e65f-1334-defb886724dc@redhat.com> 2021-10-02 9:32 ` [PATCH platform-next 08/10] Documentation/ABI: Add new attributes for mlxreg-io sysfs interfaces Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 09/10] Documentation/ABI: Add new line card " Vadim Pasternak 8 siblings, 1 reply; 13+ messages in thread From: Vadim Pasternak @ 2021-10-02 9:32 UTC (permalink / raw) To: hdegoede; +Cc: platform-driver-x86, michaelsh, Vadim Pasternak [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #1: Type: text/plain; charset="y", Size: 29167 bytes --] Provide support for the Nvidia MSN4800-XX line cards for MSN4800 Ethernet modular switch system, providing a high performance switching solution for Enterprise Data Centers (EDC) for building Ethernet based clusters, High-Performance Computing (HPC) and embedded environments. Initial version provides support for line card type MSN4800-C16. This type of line card is equipped with: - Lattice CPLD device, used for system and ports control. - four Nvidia gearbox devices, used for port splitting. - FPGA device, used for gearboxes management. - 16x100G QSFP28 ports. - hotpswap controllers, voltage regulators, analog-to-digital convertors, nvram devices. - status LED. During initialization driver creates: - line card's I2C tree through "i2c-mux-mlxcpd" driver. - line card's LED objects through "leds-mlxreg" driver. - line card's CPLD register space input / output "hwmon" attributes for line control and monitoring through "mlxreg-io" driver. These attributes provide CPLD and FPAG versioning, control for upgradable components burning, NVRAM devices write protection, line card revision, line card power consuming, line card reset cause indication, etcetera. Lattice CPLD device and nvram devices are feeding from auxiliary power domain and accessible, when line card is powered off. These devices are connected by line card driver probing routine, invoked after line card security verification is done by hardware and event lc#n_verified is received for line card located in slot #n. Gearboxes, FPGA, hotpswap controllers, voltage regulators, analog-to-digital convertors are feeding from main power domain. These devices are connected after power good event "lc#n_powered" is received for line card located in slot #n. The driver 'mlxreg-lc' is driven by 'mlxreg-hotplug' driver following relevant "hotplug" events. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> --- drivers/platform/mellanox/Kconfig | 12 + drivers/platform/mellanox/Makefile | 1 + drivers/platform/mellanox/mlxreg-lc.c | 906 ++++++++++++++++++++++++++ 3 files changed, 919 insertions(+) create mode 100644 drivers/platform/mellanox/mlxreg-lc.c diff --git a/drivers/platform/mellanox/Kconfig b/drivers/platform/mellanox/Kconfig index edd17e1a1f88..d4c5c170bca0 100644 --- a/drivers/platform/mellanox/Kconfig +++ b/drivers/platform/mellanox/Kconfig @@ -34,6 +34,18 @@ config MLXREG_IO to system resets operation, system reset causes monitoring and some kinds of mux selection. +config MLXREG_LC + tristate "Mellanox line card platform driver support" + depends on REGMAP + depends on HWMON + depends on I2C + help + This driver provides support for the Mellanox MSN4800-XX line cards, + which are the part of MSN4800 Ethernet modular switch systems + providing a high performance switching solution for Enterprise Data + Centers (EDC) for building Ethernet based clusters, High-Performance + Computing (HPC) and embedded environments. + config MLXBF_TMFIFO tristate "Mellanox BlueField SoC TmFifo platform driver" depends on ARM64 diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile index 000ddaa74c98..a4868366ff18 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_MLXBF_PMC) += mlxbf-pmc.o obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o +obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o diff --git a/drivers/platform/mellanox/mlxreg-lc.c b/drivers/platform/mellanox/mlxreg-lc.c new file mode 100644 index 000000000000..0b7f58feb701 --- /dev/null +++ b/drivers/platform/mellanox/mlxreg-lc.c @@ -0,0 +1,906 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nvidia line card driver + * + * Copyright (C) 2020 Nvidia Technologies Ltd. + */ + +#include <linux/device.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/platform_data/mlxcpld.h> +#include <linux/platform_data/mlxreg.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +/* I2C bus IO offsets */ +#define MLXREG_LC_REG_CPLD1_VER_OFFSET 0x2500 +#define MLXREG_LC_REG_FPGA1_VER_OFFSET 0x2501 +#define MLXREG_LC_REG_CPLD1_PN_OFFSET 0x2504 +#define MLXREG_LC_REG_FPGA1_PN_OFFSET 0x2506 +#define MLXREG_LC_REG_RESET_CAUSE_OFFSET 0x251d +#define MLXREG_LC_REG_LED1_OFFSET 0x2520 +#define MLXREG_LC_REG_GP0_OFFSET 0x252e +#define MLXREG_LC_REG_FIELD_UPGRADE 0x2534 +#define MLXREG_LC_CHANNEL_I2C_REG 0x25dc +#define MLXREG_LC_REG_CPLD1_MVER_OFFSET 0x25de +#define MLXREG_LC_REG_FPGA1_MVER_OFFSET 0x25df +#define MLXREG_LC_REG_MAX_POWER_OFFSET 0x25f1 +#define MLXREG_LC_REG_CONFIG_OFFSET 0x25fb +#define MLXREG_LC_REG_MAX 0x3fff + +/** + * enum mlxreg_lc_type - line cards types + * + * @MLXREG_LC_SN4800_C16: 100GbE line card with 16 QSFP28 ports; + */ +enum mlxreg_lc_type { + MLXREG_LC_SN4800_C16 = 0x0000, +}; + +/** + * enum mlxreg_lc_state - line cards state + * + * @MLXREG_LC_INITIALIZED: line card is initialized; + * @MLXREG_LC_POWERED: line card is powered; + * @MLXREG_LC_SYNCED: line card is synchronized between hardware and firmware; + */ +enum mlxreg_lc_state { + MLXREG_LC_INITIALIZED = BIT(0), + MLXREG_LC_POWERED = BIT(1), + MLXREG_LC_SYNCED = BIT(2), +}; + +#define MLXREG_LC_CONFIGURED (MLXREG_LC_INITIALIZED | MLXREG_LC_POWERED | MLXREG_LC_SYNCED) + +/* mlxreg_lc - device private data + * @dev: platform device; + * @lock: line card lock; + * @par_regmap: parent device regmap handle; + * @data: pltaform core data; + * @io_data: register access platform data; + * @led_data: LED platform data ; + * @mux_data: MUX platform data; + * @led: LED device; + * @io_regs: register access device; + * @mux_brdinfo: mux configuration; + * @mux: mux devices; + * @aux_devs: I2C devices feeding by auxiliary power; + * @aux_devs_num: number of I2C devices feeding by auxiliary power; + * @main_devs: I2C devices feeding by main power; + * @main_devs_num: number of I2C devices feeding by main power; + * @state: line card state; + */ +struct mlxreg_lc { + struct device *dev; + struct mutex lock; /* line card access lock */ + void *par_regmap; + struct mlxreg_core_data *data; + struct mlxreg_core_platform_data *io_data; + struct mlxreg_core_platform_data *led_data; + struct mlxcpld_mux_plat_data *mux_data; + struct platform_device *led; + struct platform_device *io_regs; + struct i2c_board_info *mux_brdinfo; + struct platform_device *mux; + struct mlxreg_hotplug_device *aux_devs; + int aux_devs_num; + struct mlxreg_hotplug_device *main_devs; + int main_devs_num; + enum mlxreg_lc_state state; +}; + +static bool mlxreg_lc_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MLXREG_LC_REG_LED1_OFFSET: + case MLXREG_LC_REG_GP0_OFFSET: + case MLXREG_LC_REG_FIELD_UPGRADE: + case MLXREG_LC_CHANNEL_I2C_REG: + return true; + } + return false; +} + +static bool mlxreg_lc_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MLXREG_LC_REG_CPLD1_VER_OFFSET: + case MLXREG_LC_REG_FPGA1_VER_OFFSET: + case MLXREG_LC_REG_CPLD1_PN_OFFSET: + case MLXREG_LC_REG_FPGA1_PN_OFFSET: + case MLXREG_LC_REG_RESET_CAUSE_OFFSET: + case MLXREG_LC_REG_LED1_OFFSET: + case MLXREG_LC_REG_GP0_OFFSET: + case MLXREG_LC_REG_FIELD_UPGRADE: + case MLXREG_LC_CHANNEL_I2C_REG: + case MLXREG_LC_REG_CPLD1_MVER_OFFSET: + case MLXREG_LC_REG_FPGA1_MVER_OFFSET: + case MLXREG_LC_REG_MAX_POWER_OFFSET: + case MLXREG_LC_REG_CONFIG_OFFSET: + return true; + } + return false; +} + +static bool mlxreg_lc_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MLXREG_LC_REG_CPLD1_VER_OFFSET: + case MLXREG_LC_REG_FPGA1_VER_OFFSET: + case MLXREG_LC_REG_CPLD1_PN_OFFSET: + case MLXREG_LC_REG_FPGA1_PN_OFFSET: + case MLXREG_LC_REG_RESET_CAUSE_OFFSET: + case MLXREG_LC_REG_LED1_OFFSET: + case MLXREG_LC_REG_GP0_OFFSET: + case MLXREG_LC_REG_FIELD_UPGRADE: + case MLXREG_LC_CHANNEL_I2C_REG: + case MLXREG_LC_REG_CPLD1_MVER_OFFSET: + case MLXREG_LC_REG_FPGA1_MVER_OFFSET: + case MLXREG_LC_REG_MAX_POWER_OFFSET: + case MLXREG_LC_REG_CONFIG_OFFSET: + return true; + } + return false; +} + +static const struct reg_default mlxreg_lc_regmap_default[] = { + { MLXREG_LC_CHANNEL_I2C_REG, 0x00 }, +}; + +/* Configuration for the register map of a device with 2 bytes address space. */ +static const struct regmap_config mlxreg_lc_regmap_conf = { + .reg_bits = 16, + .val_bits = 8, + .max_register = MLXREG_LC_REG_MAX, + .cache_type = REGCACHE_FLAT, + .writeable_reg = mlxreg_lc_writeable_reg, + .readable_reg = mlxreg_lc_readable_reg, + .volatile_reg = mlxreg_lc_volatile_reg, + .reg_defaults = mlxreg_lc_regmap_default, + .num_reg_defaults = ARRAY_SIZE(mlxreg_lc_regmap_default), +}; + +/* Default channels vector. + * It contains only the channels, which physically connected to the devices, + * empty channels are skipped. + */ +static int mlxreg_lc_chan[] = { + 0x04, 0x05, 0x06, 0x07, 0x08, 0x10, 0x20, 0x21, 0x22, 0x23, 0x40, 0x41, + 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, + 0x4e, 0x4f +}; + +/* Defaul mux configuration. */ +static struct mlxcpld_mux_plat_data mlxreg_lc_mux_data[] = { + { + .chan_ids = mlxreg_lc_chan, + .num_adaps = ARRAY_SIZE(mlxreg_lc_chan), + .sel_reg_addr = MLXREG_LC_CHANNEL_I2C_REG, + .reg_size = 2, + }, +}; + +/* Defaul mux board info. */ +static struct i2c_board_info mlxreg_lc_mux_brdinfo = { + I2C_BOARD_INFO("i2c-mux-mlxcpld", 0x32), +}; + +/* Line card default auxiliary power static devices. */ +static struct i2c_board_info mlxreg_lc_aux_pwr_devices[] = { + { + I2C_BOARD_INFO("24c32", 0x51), + }, + { + I2C_BOARD_INFO("24c32", 0x51), + }, +}; + +/* Line card default auxiliary power board info. */ +static struct mlxreg_hotplug_device mlxreg_lc_aux_pwr_brdinfo[] = { + { + .brdinfo = &mlxreg_lc_aux_pwr_devices[0], + .nr = 3, + }, + { + .brdinfo = &mlxreg_lc_aux_pwr_devices[1], + .nr = 4, + }, +}; + +/* Line card default main power static devices. */ +static struct i2c_board_info mlxreg_lc_main_pwr_devices[] = { + { + I2C_BOARD_INFO("mp2975", 0x62), + }, + { + I2C_BOARD_INFO("mp2975", 0x64), + }, + { + I2C_BOARD_INFO("max11603", 0x6d), + }, + { + I2C_BOARD_INFO("lm25066", 0x15), + }, +}; + +/* Line card default main power board info. */ +static struct mlxreg_hotplug_device mlxreg_lc_main_pwr_brdinfo[] = { + { + .brdinfo = &mlxreg_lc_main_pwr_devices[0], + .nr = 0, + }, + { + .brdinfo = &mlxreg_lc_main_pwr_devices[1], + .nr = 0, + }, + { + .brdinfo = &mlxreg_lc_main_pwr_devices[2], + .nr = 1, + }, + { + .brdinfo = &mlxreg_lc_main_pwr_devices[3], + .nr = 2, + }, +}; + +/* LED default data. */ +static struct mlxreg_core_data mlxreg_lc_led_data[] = { + { + .label = "status:green", + .reg = MLXREG_LC_REG_LED1_OFFSET, + .mask = GENMASK(7, 4), + }, + { + .label = "status:orange", + .reg = MLXREG_LC_REG_LED1_OFFSET, + .mask = GENMASK(7, 4), + }, +}; + +static struct mlxreg_core_platform_data mlxreg_lc_led = { + .identity = "pci", + .data = mlxreg_lc_led_data, + .counter = ARRAY_SIZE(mlxreg_lc_led_data), +}; + +/* Default register access data. */ +static struct mlxreg_core_data mlxreg_lc_io_data[] = { + { + .label = "cpld1_version", + .reg = MLXREG_LC_REG_CPLD1_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "fpga1_version", + .reg = MLXREG_LC_REG_FPGA1_VER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "cpld1_pn", + .reg = MLXREG_LC_REG_CPLD1_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, + { + .label = "fpga1_pn", + .reg = MLXREG_LC_REG_FPGA1_PN_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, + { + .label = "cpld1_version_min", + .reg = MLXREG_LC_REG_CPLD1_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "fpga1_version_min", + .reg = MLXREG_LC_REG_FPGA1_MVER_OFFSET, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { + .label = "reset_fpga_not_done", + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0444, + }, + { + .label = "reset_aux_pwr_or_ref", + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { + .label = "reset_dc_dc_pwr_fail", + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { + .label = "reset_from_chassis", + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { + .label = "reset_pwr_off_from_chassis", + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { + .label = "reset_line_card", + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { + .label = "reset_line_card_pwr_en", + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { + .label = "cpld_upgrade_en", + .reg = MLXREG_LC_REG_FIELD_UPGRADE, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + .secured = 1, + }, + { + .label = "fpga_upgrade_en", + .reg = MLXREG_LC_REG_FIELD_UPGRADE, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + .secured = 1, + }, + { + .label = "qsfp_pwr_en", + .reg = MLXREG_LC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, + { + .label = "vpd_wp", + .reg = MLXREG_LC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + .secured = 1, + }, + { + .label = "agb_spi_burn_en", + .reg = MLXREG_LC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + .secured = 1, + }, + { + .label = "fpga_spi_burn_en", + .reg = MLXREG_LC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0644, + .secured = 1, + }, + { + .label = "max_power", + .reg = MLXREG_LC_REG_MAX_POWER_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, + { + .label = "config", + .reg = MLXREG_LC_REG_CONFIG_OFFSET, + .bit = GENMASK(15, 0), + .mode = 0444, + .regnum = 2, + }, +}; + +static struct mlxreg_core_platform_data mlxreg_lc_regs_io = { + .data = mlxreg_lc_io_data, + .counter = ARRAY_SIZE(mlxreg_lc_io_data), +}; + +static int +mlxreg_lc_create_static_devices(struct mlxreg_lc *mlxreg_lc, struct mlxreg_hotplug_device *devs, + int size) +{ + struct mlxreg_hotplug_device *dev = devs; + int i; + + /* Create static I2C device feeding by auxiliary or main power. */ + for (i = 0; i < size; i++, dev++) { + dev->client = i2c_new_client_device(dev->adapter, dev->brdinfo); + if (IS_ERR(dev->client)) { + dev_err(mlxreg_lc->dev, "Failed to create client %s at bus %d at addr 0x%02x\n", + dev->brdinfo->type, dev->nr, dev->brdinfo->addr); + + dev->adapter = NULL; + goto fail_create_static_devices; + } + } + + return 0; + +fail_create_static_devices: + while (--i >= 0) { + dev = devs + i; + i2c_unregister_device(dev->client); + dev->client = NULL; + } + return IS_ERR(dev->client); +} + +static void +mlxreg_lc_destroy_static_devices(struct mlxreg_lc *mlxreg_lc, struct mlxreg_hotplug_device *devs, + int size) +{ + struct mlxreg_hotplug_device *dev = devs; + int i; + + /* Destroy static I2C device feeding by auxiliary or main power. */ + for (i = 0; i < size; i++, dev++) { + if (dev->client) { + i2c_unregister_device(dev->client); + dev->client = NULL; + } + } +} + +static int mlxreg_lc_power_on_off(struct mlxreg_lc *mlxreg_lc, u8 action) +{ + u32 regval; + int err; + + mutex_lock(&mlxreg_lc->lock); + + err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_pwr, ®val); + if (err) + goto regmap_read_fail; + + if (action) + regval |= BIT(mlxreg_lc->data->slot - 1); + else + regval &= ~BIT(mlxreg_lc->data->slot - 1); + + err = regmap_write(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_pwr, regval); + +regmap_read_fail: + mutex_unlock(&mlxreg_lc->lock); + return err; +} + +static int mlxreg_lc_enable_disable(struct mlxreg_lc *mlxreg_lc, bool action) +{ + u32 regval; + int err; + + /* + * Hardware holds the line card after powering on in the disabled state. Holding line card + * in disabled state protects access to the line components, like FPGA and gearboxes. + * Line card should be enabled in order to get it in operational state. Line card could be + * disabled for moving it to non-operational state. Enabling line card does not affect the + * line card which is already has been enabled. Disabling does not affect the disabled line + * card. + */ + mutex_lock(&mlxreg_lc->lock); + + err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_ena, ®val); + if (err) + goto regmap_read_fail; + + if (action) + regval |= BIT(mlxreg_lc->data->slot - 1); + else + regval &= ~BIT(mlxreg_lc->data->slot - 1); + + err = regmap_write(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_ena, regval); + +regmap_read_fail: + mutex_unlock(&mlxreg_lc->lock); + return err; +} + +static int +mlxreg_lc_sn4800_c16_config_init(struct mlxreg_lc *mlxreg_lc, void *regmap, + struct mlxreg_core_data *data) +{ + struct device *dev = &data->hpdev.client->dev; + + /* Set line card configuration according to the type. */ + mlxreg_lc->mux_data = mlxreg_lc_mux_data; + mlxreg_lc->io_data = &mlxreg_lc_regs_io; + mlxreg_lc->led_data = &mlxreg_lc_led; + mlxreg_lc->mux_brdinfo = &mlxreg_lc_mux_brdinfo; + + mlxreg_lc->aux_devs = devm_kmemdup(dev, mlxreg_lc_aux_pwr_brdinfo, + sizeof(mlxreg_lc_aux_pwr_brdinfo), GFP_KERNEL); + if (!mlxreg_lc->aux_devs) + return -ENOMEM; + mlxreg_lc->aux_devs_num = ARRAY_SIZE(mlxreg_lc_aux_pwr_brdinfo); + mlxreg_lc->main_devs = devm_kmemdup(dev, mlxreg_lc_main_pwr_brdinfo, + sizeof(mlxreg_lc_main_pwr_brdinfo), GFP_KERNEL); + if (!mlxreg_lc->main_devs) + return -ENOMEM; + mlxreg_lc->main_devs_num = ARRAY_SIZE(mlxreg_lc_main_pwr_brdinfo); + + return 0; +} + +static void +mlxreg_lc_state_update(struct mlxreg_lc *mlxreg_lc, enum mlxreg_lc_state state, u8 action) +{ + mutex_lock(&mlxreg_lc->lock); + + if (action) + mlxreg_lc->state |= state; + else + mlxreg_lc->state &= ~state; + + mutex_unlock(&mlxreg_lc->lock); +} + +/* + * Callback is to be called from mlxreg-hotplug driver to notify about line card about received + * event. + */ +static int mlxreg_lc_event_handler(void *handle, enum mlxreg_hotplug_kind kind, u8 action) +{ + struct mlxreg_lc *mlxreg_lc = handle; + int err = 0; + + dev_info(mlxreg_lc->dev, "linecard#%d state %d event kind %d action %d\n", + mlxreg_lc->data->slot, mlxreg_lc->state, kind, action); + + if (!(mlxreg_lc->state & MLXREG_LC_INITIALIZED)) + return 0; + + switch (kind) { + case MLXREG_HOTPLUG_LC_SYNCED: + /* + * Synchronization event - hardware and firmware are synchronized. Power on/off + * line card - to allow/disallow main power source. + */ + mlxreg_lc_state_update(mlxreg_lc, MLXREG_LC_SYNCED, action); + /* Power line card if it is not powered yet. */ + if (!(mlxreg_lc->state & MLXREG_LC_POWERED) && action) { + err = mlxreg_lc_power_on_off(mlxreg_lc, 1); + if (err) + return err; + } + /* In case line card is configured - enable it. */ + if (mlxreg_lc->state & MLXREG_LC_CONFIGURED && action) + err = mlxreg_lc_enable_disable(mlxreg_lc, 1); + break; + case MLXREG_HOTPLUG_LC_POWERED: + /* Power event - attach or de-attach line card device feeding by the main power. */ + if (action) { + /* Do not create devices, if line card is already powered. */ + if (mlxreg_lc->state & MLXREG_LC_POWERED) { + /* In case line card is configured - enable it. */ + if (mlxreg_lc->state & MLXREG_LC_CONFIGURED) + err = mlxreg_lc_enable_disable(mlxreg_lc, 1); + return err; + } + err = mlxreg_lc_create_static_devices(mlxreg_lc, mlxreg_lc->main_devs, + mlxreg_lc->main_devs_num); + if (err) + return err; + + /* In case line card is already in ready state - enable it. */ + if (mlxreg_lc->state & MLXREG_LC_CONFIGURED) + err = mlxreg_lc_enable_disable(mlxreg_lc, 1); + } else { + mlxreg_lc_destroy_static_devices(mlxreg_lc, mlxreg_lc->main_devs, + mlxreg_lc->main_devs_num); + } + mlxreg_lc_state_update(mlxreg_lc, MLXREG_LC_POWERED, action); + break; + case MLXREG_HOTPLUG_LC_READY: + /* + * Ready event – enable line card by releasing it from reset or disable it by put + * to reset state. + */ + err = mlxreg_lc_enable_disable(mlxreg_lc, !!action); + break; + case MLXREG_HOTPLUG_LC_THERMAL: + /* Thermal shutdown event – power off line card. */ + if (action) + err = mlxreg_lc_power_on_off(mlxreg_lc, 0); + break; + default: + break; + } + + return err; +} + +/* + * Callback is to be called from i2c-mux-mlxcpld driver to indicate that all adapter devices has + * been created. + */ +static int mlxreg_lc_completion_notify(void *handle, struct i2c_adapter *parent, + struct i2c_adapter *adapters[]) +{ + struct mlxreg_hotplug_device *main_dev, *aux_dev; + struct mlxreg_lc *mlxreg_lc = handle; + u32 regval; + int i, err; + + /* Update I2C devices feeding by auxiliary power. */ + aux_dev = mlxreg_lc->aux_devs; + for (i = 0; i < mlxreg_lc->aux_devs_num; i++, aux_dev++) { + aux_dev->adapter = adapters[aux_dev->nr]; + aux_dev->nr = adapters[aux_dev->nr]->nr; + } + + err = mlxreg_lc_create_static_devices(mlxreg_lc, mlxreg_lc->aux_devs, + mlxreg_lc->aux_devs_num); + if (err) + return err; + + /* Update I2C devices feeding by main power. */ + main_dev = mlxreg_lc->main_devs; + for (i = 0; i < mlxreg_lc->main_devs_num; i++, main_dev++) { + main_dev->adapter = adapters[main_dev->nr]; + main_dev->nr = adapters[main_dev->nr]->nr; + } + + /* Verify if line card is powered. */ + err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_pwr, ®val); + if (err) + goto mlxreg_lc_regmap_read_power_fail; + + if (regval & mlxreg_lc->data->mask) { + err = mlxreg_lc_create_static_devices(mlxreg_lc, mlxreg_lc->main_devs, + mlxreg_lc->main_devs_num); + if (err) + goto mlxreg_lc_create_static_devices_failed; + + mlxreg_lc_state_update(mlxreg_lc, MLXREG_LC_POWERED, 1); + } + + /* Verify if line card is synchronized. */ + err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data->reg_sync, ®val); + if (err) + goto mlxreg_lc_regmap_read_sync_fail; + + /* Power on line card if necessary. */ + if (regval & mlxreg_lc->data->mask) { + mlxreg_lc->state |= MLXREG_LC_SYNCED; + mlxreg_lc_state_update(mlxreg_lc, MLXREG_LC_SYNCED, 1); + if (mlxreg_lc->state & ~MLXREG_LC_POWERED) { + err = mlxreg_lc_power_on_off(mlxreg_lc, 1); + if (err) + goto mlxreg_lc_regmap_power_on_off_fail; + } + } + + mlxreg_lc_state_update(mlxreg_lc, MLXREG_LC_INITIALIZED, 1); + + return 0; + +mlxreg_lc_regmap_power_on_off_fail: +mlxreg_lc_regmap_read_sync_fail: + if (mlxreg_lc->state & MLXREG_LC_POWERED) + mlxreg_lc_destroy_static_devices(mlxreg_lc, mlxreg_lc->main_devs, + mlxreg_lc->main_devs_num); +mlxreg_lc_create_static_devices_failed: + mlxreg_lc_destroy_static_devices(mlxreg_lc, mlxreg_lc->aux_devs, mlxreg_lc->aux_devs_num); +mlxreg_lc_regmap_read_power_fail: + return err; +} + +static int +mlxreg_lc_config_init(struct mlxreg_lc *mlxreg_lc, void *regmap, + struct mlxreg_core_data *data) +{ + struct device *dev = &data->hpdev.client->dev; + int lsb, err; + u32 regval; + + /* Validate line card type. */ + err = regmap_read(regmap, MLXREG_LC_REG_CONFIG_OFFSET, &lsb); + err = (!err) ? regmap_read(regmap, MLXREG_LC_REG_CONFIG_OFFSET, ®val) : err; + if (err) + return err; + regval = (regval & GENMASK(7, 0)) << 8 | (lsb & GENMASK(7, 0)); + switch (regval) { + case MLXREG_LC_SN4800_C16: + err = mlxreg_lc_sn4800_c16_config_init(mlxreg_lc, regmap, data); + if (err) + return err; + break; + default: + return -ENODEV; + } + + /* Create mux infrastructure. */ + mlxreg_lc->mux_data->handle = mlxreg_lc; + mlxreg_lc->mux_data->completion_notify = mlxreg_lc_completion_notify; + mlxreg_lc->mux_brdinfo->platform_data = mlxreg_lc->mux_data; + mlxreg_lc->mux = platform_device_register_resndata(dev, "i2c-mux-mlxcpld", data->hpdev.nr, + NULL, 0, mlxreg_lc->mux_data, + sizeof(*mlxreg_lc->mux_data)); + if (IS_ERR(mlxreg_lc->mux)) + return PTR_ERR(mlxreg_lc->mux); + + /* Register IO access driver. */ + if (mlxreg_lc->io_data) { + mlxreg_lc->io_data->regmap = regmap; + mlxreg_lc->io_regs = + platform_device_register_resndata(dev, "mlxreg-io", data->hpdev.nr, NULL, 0, + mlxreg_lc->io_data, sizeof(*mlxreg_lc->io_data)); + if (IS_ERR(mlxreg_lc->io_regs)) { + err = PTR_ERR(mlxreg_lc->io_regs); + goto fail_register_io; + } + } + + /* Register LED driver. */ + if (mlxreg_lc->led_data) { + mlxreg_lc->led_data->regmap = regmap; + mlxreg_lc->led = + platform_device_register_resndata(dev, "leds-mlxreg", data->hpdev.nr, NULL, 0, + mlxreg_lc->led_data, + sizeof(*mlxreg_lc->led_data)); + if (IS_ERR(mlxreg_lc->led)) { + err = PTR_ERR(mlxreg_lc->led); + goto fail_register_led; + } + } + + return 0; + +fail_register_led: + if (mlxreg_lc->io_regs) + platform_device_unregister(mlxreg_lc->io_regs); +fail_register_io: + if (mlxreg_lc->mux) + platform_device_unregister(mlxreg_lc->mux); + + return err; +} + +static void mlxreg_lc_config_exit(struct mlxreg_lc *mlxreg_lc) +{ + /* Unregister LED driver. */ + if (mlxreg_lc->led) + platform_device_unregister(mlxreg_lc->led); + /* Unregister IO access driver. */ + if (mlxreg_lc->io_regs) + platform_device_unregister(mlxreg_lc->io_regs); + /* Remove mux infrastructure. */ + if (mlxreg_lc->mux) + platform_device_unregister(mlxreg_lc->mux); +} + +static int mlxreg_lc_probe(struct platform_device *pdev) +{ + struct mlxreg_core_hotplug_platform_data *par_pdata; + struct mlxreg_core_data *data; + struct mlxreg_lc *mlxreg_lc; + void *regmap; + int i, err; + + data = dev_get_platdata(&pdev->dev); + if (!data) + return -EINVAL; + + mlxreg_lc = devm_kzalloc(&pdev->dev, sizeof(*mlxreg_lc), GFP_KERNEL); + if (!mlxreg_lc) + return -ENOMEM; + + mutex_init(&mlxreg_lc->lock); + /* Set event notification callback. */ + if (data->notifier) { + data->notifier->user_handler = mlxreg_lc_event_handler; + data->notifier->handle = mlxreg_lc; + } + data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr); + if (!data->hpdev.adapter) { + dev_err(&pdev->dev, "Failed to get adapter for bus %d\n", + data->hpdev.nr); + return -EFAULT; + } + + /* Create device at the top of line card I2C tree.*/ + data->hpdev.client = i2c_new_client_device(data->hpdev.adapter, + data->hpdev.brdinfo); + if (IS_ERR(data->hpdev.client)) { + dev_err(&pdev->dev, "Failed to create client %s at bus %d at addr 0x%02x\n", + data->hpdev.brdinfo->type, data->hpdev.nr, data->hpdev.brdinfo->addr); + + i2c_put_adapter(data->hpdev.adapter); + data->hpdev.adapter = NULL; + return PTR_ERR(data->hpdev.client); + } + + regmap = devm_regmap_init_i2c(data->hpdev.client, + &mlxreg_lc_regmap_conf); + if (IS_ERR(regmap)) { + err = PTR_ERR(regmap); + goto mlxreg_lc_probe_fail; + } + + /* Set default registers. */ + for (i = 0; i < mlxreg_lc_regmap_conf.num_reg_defaults; i++) { + err = regmap_write(regmap, mlxreg_lc_regmap_default[i].reg, + mlxreg_lc_regmap_default[i].def); + if (err) + goto mlxreg_lc_probe_fail; + } + + /* Sync registers with hardware. */ + regcache_mark_dirty(regmap); + err = regcache_sync(regmap); + if (err) + goto mlxreg_lc_probe_fail; + + par_pdata = data->hpdev.brdinfo->platform_data; + mlxreg_lc->par_regmap = par_pdata->regmap; + mlxreg_lc->data = data; + mlxreg_lc->dev = &pdev->dev; + platform_set_drvdata(pdev, mlxreg_lc); + + /* Configure line card. */ + err = mlxreg_lc_config_init(mlxreg_lc, regmap, data); + if (err) + goto mlxreg_lc_probe_fail; + + return err; + +mlxreg_lc_probe_fail: + i2c_put_adapter(data->hpdev.adapter); + return err; +} + +static int mlxreg_lc_remove(struct platform_device *pdev) +{ + struct mlxreg_core_data *data = dev_get_platdata(&pdev->dev); + struct mlxreg_lc *mlxreg_lc = platform_get_drvdata(pdev); + + /* Clear event notification callback. */ + if (data->notifier) { + data->notifier->user_handler = NULL; + data->notifier->handle = NULL; + } + + /* Destroy static I2C device feeding by main power. */ + mlxreg_lc_destroy_static_devices(mlxreg_lc, mlxreg_lc->main_devs, + mlxreg_lc->main_devs_num); + /* Destroy static I2C device feeding by auxiliary power. */ + mlxreg_lc_destroy_static_devices(mlxreg_lc, mlxreg_lc->aux_devs, mlxreg_lc->aux_devs_num); + /* Unregister underlying drivers. */ + mlxreg_lc_config_exit(mlxreg_lc); + if (data->hpdev.client) { + i2c_unregister_device(data->hpdev.client); + data->hpdev.client = NULL; + i2c_put_adapter(data->hpdev.adapter); + data->hpdev.adapter = NULL; + } + + return 0; +} + +static struct platform_driver mlxreg_lc_driver = { + .probe = mlxreg_lc_probe, + .remove = mlxreg_lc_remove, + .driver = { + .name = "mlxreg-lc", + }, +}; + +module_platform_driver(mlxreg_lc_driver); + +MODULE_AUTHOR("Vadim Pasternak <vadimp@nvidia.com>"); +MODULE_DESCRIPTION("Nvidia line card platform driver"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_ALIAS("platform:mlxreg-lc"); -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
[parent not found: <76a93a22-a3ff-e65f-1334-defb886724dc@redhat.com>]
[parent not found: <6d9e4402-a8c2-d043-4129-4da6b250ea53@redhat.com>]
* RE: [PATCH platform-next 07/10] platform/mellanox: mlxreg-lc: Add initial support for Nvidia line card devices [not found] ` <6d9e4402-a8c2-d043-4129-4da6b250ea53@redhat.com> @ 2021-10-19 8:57 ` Vadim Pasternak 0 siblings, 0 replies; 13+ messages in thread From: Vadim Pasternak @ 2021-10-19 8:57 UTC (permalink / raw) To: Hans de Goede; +Cc: platform-driver-x86@vger.kernel.org, Michael Shych > -----Original Message----- > From: Hans de Goede <hdegoede@redhat.com> > Sent: Tuesday, October 19, 2021 11:47 AM > To: Vadim Pasternak <vadimp@nvidia.com> > Cc: platform-driver-x86@vger.kernel.org; Michael Shych > <michaelsh@nvidia.com> > Subject: Re: [PATCH platform-next 07/10] platform/mellanox: mlxreg-lc: Add > initial support for Nvidia line card devices > > Hi again, > > On 10/19/21 10:45, Hans de Goede wrote: > > Hi, > > > > The headers of this email contain: > > > > Content-Type: text/plain; charset="y" > > > > With "y" not being any known / valid character encoding. > > I wonder if git send-email asked you to specify an encoding and instead of > hitting enter to get the default you input 'y' because you thought it was > asking for confirmation for something... ? Hi Hans, Sorry for this issue. To be honest I don't remember, but maybe I really put 'y' by mistake. I should be more careful next time. Thanks, Vadim. > > Regards, > > Hans > > > > > > I've fixed this up by editing the raw email before git am-ing it, > > dropping the '; charset="y"' part. > > > > If you can figure out what happened here and avoid this next time that > > would be good. > > > > If you cannot figure it out, will just leave it as some mysterious > > glitch. > > > > Regards, > > > > Hans > > > > > > > > > > On 10/2/21 11:32, Vadim Pasternak wrote: > >> Provide support for the Nvidia MSN4800-XX line cards for MSN4800 > >> Ethernet modular switch system, providing a high performance > >> switching solution for Enterprise Data Centers (EDC) for building > >> Ethernet based clusters, High-Performance Computing (HPC) and > embedded environments. > >> Initial version provides support for line card type MSN4800-C16. This > >> type of line card is equipped with: > >> - Lattice CPLD device, used for system and ports control. > >> - four Nvidia gearbox devices, used for port splitting. > >> - FPGA device, used for gearboxes management. > >> - 16x100G QSFP28 ports. > >> - hotpswap controllers, voltage regulators, analog-to-digital > >> convertors, nvram devices. > >> - status LED. > >> > >> During initialization driver creates: > >> - line card's I2C tree through "i2c-mux-mlxcpd" driver. > >> - line card's LED objects through "leds-mlxreg" driver. > >> - line card's CPLD register space input / output "hwmon" attributes for > >> line control and monitoring through "mlxreg-io" driver. These > >> attributes provide CPLD and FPAG versioning, control for upgradable > >> components burning, NVRAM devices write protection, line card > >> revision, line card power consuming, line card reset cause > >> indication, etcetera. > >> > >> Lattice CPLD device and nvram devices are feeding from auxiliary > >> power domain and accessible, when line card is powered off. These > >> devices are connected by line card driver probing routine, invoked > >> after line card security verification is done by hardware and event > >> lc#n_verified is received for line card located in slot #n. > >> > >> Gearboxes, FPGA, hotpswap controllers, voltage regulators, > >> analog-to-digital convertors are feeding from main power domain. > >> These devices are connected after power good event "lc#n_powered" is > >> received for line card located in slot #n. > >> > >> The driver 'mlxreg-lc' is driven by 'mlxreg-hotplug' driver following > >> relevant "hotplug" events. > >> > >> Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> > >> Reviewed-by: Michael Shych <michaelsh@nvidia.com> > >> --- > >> drivers/platform/mellanox/Kconfig | 12 + > >> drivers/platform/mellanox/Makefile | 1 + > >> drivers/platform/mellanox/mlxreg-lc.c | 906 > >> ++++++++++++++++++++++++++ > >> 3 files changed, 919 insertions(+) > >> create mode 100644 drivers/platform/mellanox/mlxreg-lc.c > >> > >> diff --git a/drivers/platform/mellanox/Kconfig > >> b/drivers/platform/mellanox/Kconfig > >> index edd17e1a1f88..d4c5c170bca0 100644 > >> --- a/drivers/platform/mellanox/Kconfig > >> +++ b/drivers/platform/mellanox/Kconfig > >> @@ -34,6 +34,18 @@ config MLXREG_IO > >> to system resets operation, system reset causes monitoring and > some > >> kinds of mux selection. > >> > >> +config MLXREG_LC > >> + tristate "Mellanox line card platform driver support" > >> + depends on REGMAP > >> + depends on HWMON > >> + depends on I2C > >> + help > >> + This driver provides support for the Mellanox MSN4800-XX line > cards, > >> + which are the part of MSN4800 Ethernet modular switch systems > >> + providing a high performance switching solution for Enterprise Data > >> + Centers (EDC) for building Ethernet based clusters, High- > Performance > >> + Computing (HPC) and embedded environments. > >> + > >> config MLXBF_TMFIFO > >> tristate "Mellanox BlueField SoC TmFifo platform driver" > >> depends on ARM64 > >> diff --git a/drivers/platform/mellanox/Makefile > >> b/drivers/platform/mellanox/Makefile > >> index 000ddaa74c98..a4868366ff18 100644 > >> --- a/drivers/platform/mellanox/Makefile > >> +++ b/drivers/platform/mellanox/Makefile > >> @@ -8,3 +8,4 @@ obj-$(CONFIG_MLXBF_PMC) += mlxbf- > pmc.o > >> obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o > >> obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o > >> obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o > >> +obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o > >> diff --git a/drivers/platform/mellanox/mlxreg-lc.c > >> b/drivers/platform/mellanox/mlxreg-lc.c > >> new file mode 100644 > >> index 000000000000..0b7f58feb701 > >> --- /dev/null > >> +++ b/drivers/platform/mellanox/mlxreg-lc.c > >> @@ -0,0 +1,906 @@ > >> +// SPDX-License-Identifier: GPL-2.0+ > >> +/* > >> + * Nvidia line card driver > >> + * > >> + * Copyright (C) 2020 Nvidia Technologies Ltd. > >> + */ > >> + > >> +#include <linux/device.h> > >> +#include <linux/i2c.h> > >> +#include <linux/module.h> > >> +#include <linux/platform_data/mlxcpld.h> #include > >> +<linux/platform_data/mlxreg.h> #include <linux/platform_device.h> > >> +#include <linux/regmap.h> > >> + > >> +/* I2C bus IO offsets */ > >> +#define MLXREG_LC_REG_CPLD1_VER_OFFSET 0x2500 > >> +#define MLXREG_LC_REG_FPGA1_VER_OFFSET 0x2501 > >> +#define MLXREG_LC_REG_CPLD1_PN_OFFSET 0x2504 > >> +#define MLXREG_LC_REG_FPGA1_PN_OFFSET 0x2506 > >> +#define MLXREG_LC_REG_RESET_CAUSE_OFFSET 0x251d > >> +#define MLXREG_LC_REG_LED1_OFFSET 0x2520 > >> +#define MLXREG_LC_REG_GP0_OFFSET 0x252e > >> +#define MLXREG_LC_REG_FIELD_UPGRADE 0x2534 > >> +#define MLXREG_LC_CHANNEL_I2C_REG 0x25dc > >> +#define MLXREG_LC_REG_CPLD1_MVER_OFFSET 0x25de > >> +#define MLXREG_LC_REG_FPGA1_MVER_OFFSET 0x25df > >> +#define MLXREG_LC_REG_MAX_POWER_OFFSET 0x25f1 > >> +#define MLXREG_LC_REG_CONFIG_OFFSET 0x25fb > >> +#define MLXREG_LC_REG_MAX 0x3fff > >> + > >> +/** > >> + * enum mlxreg_lc_type - line cards types > >> + * > >> + * @MLXREG_LC_SN4800_C16: 100GbE line card with 16 QSFP28 ports; > */ > >> +enum mlxreg_lc_type { > >> + MLXREG_LC_SN4800_C16 = 0x0000, > >> +}; > >> + > >> +/** > >> + * enum mlxreg_lc_state - line cards state > >> + * > >> + * @MLXREG_LC_INITIALIZED: line card is initialized; > >> + * @MLXREG_LC_POWERED: line card is powered; > >> + * @MLXREG_LC_SYNCED: line card is synchronized between hardware > and > >> +firmware; */ enum mlxreg_lc_state { > >> + MLXREG_LC_INITIALIZED = BIT(0), > >> + MLXREG_LC_POWERED = BIT(1), > >> + MLXREG_LC_SYNCED = BIT(2), > >> +}; > >> + > >> +#define MLXREG_LC_CONFIGURED (MLXREG_LC_INITIALIZED | > MLXREG_LC_POWERED | MLXREG_LC_SYNCED) > >> + > >> +/* mlxreg_lc - device private data > >> + * @dev: platform device; > >> + * @lock: line card lock; > >> + * @par_regmap: parent device regmap handle; > >> + * @data: pltaform core data; > >> + * @io_data: register access platform data; > >> + * @led_data: LED platform data ; > >> + * @mux_data: MUX platform data; > >> + * @led: LED device; > >> + * @io_regs: register access device; > >> + * @mux_brdinfo: mux configuration; > >> + * @mux: mux devices; > >> + * @aux_devs: I2C devices feeding by auxiliary power; > >> + * @aux_devs_num: number of I2C devices feeding by auxiliary power; > >> + * @main_devs: I2C devices feeding by main power; > >> + * @main_devs_num: number of I2C devices feeding by main power; > >> + * @state: line card state; > >> + */ > >> +struct mlxreg_lc { > >> + struct device *dev; > >> + struct mutex lock; /* line card access lock */ > >> + void *par_regmap; > >> + struct mlxreg_core_data *data; > >> + struct mlxreg_core_platform_data *io_data; > >> + struct mlxreg_core_platform_data *led_data; > >> + struct mlxcpld_mux_plat_data *mux_data; > >> + struct platform_device *led; > >> + struct platform_device *io_regs; > >> + struct i2c_board_info *mux_brdinfo; > >> + struct platform_device *mux; > >> + struct mlxreg_hotplug_device *aux_devs; > >> + int aux_devs_num; > >> + struct mlxreg_hotplug_device *main_devs; > >> + int main_devs_num; > >> + enum mlxreg_lc_state state; > >> +}; > >> + > >> +static bool mlxreg_lc_writeable_reg(struct device *dev, unsigned int > >> +reg) { > >> + switch (reg) { > >> + case MLXREG_LC_REG_LED1_OFFSET: > >> + case MLXREG_LC_REG_GP0_OFFSET: > >> + case MLXREG_LC_REG_FIELD_UPGRADE: > >> + case MLXREG_LC_CHANNEL_I2C_REG: > >> + return true; > >> + } > >> + return false; > >> +} > >> + > >> +static bool mlxreg_lc_readable_reg(struct device *dev, unsigned int > >> +reg) { > >> + switch (reg) { > >> + case MLXREG_LC_REG_CPLD1_VER_OFFSET: > >> + case MLXREG_LC_REG_FPGA1_VER_OFFSET: > >> + case MLXREG_LC_REG_CPLD1_PN_OFFSET: > >> + case MLXREG_LC_REG_FPGA1_PN_OFFSET: > >> + case MLXREG_LC_REG_RESET_CAUSE_OFFSET: > >> + case MLXREG_LC_REG_LED1_OFFSET: > >> + case MLXREG_LC_REG_GP0_OFFSET: > >> + case MLXREG_LC_REG_FIELD_UPGRADE: > >> + case MLXREG_LC_CHANNEL_I2C_REG: > >> + case MLXREG_LC_REG_CPLD1_MVER_OFFSET: > >> + case MLXREG_LC_REG_FPGA1_MVER_OFFSET: > >> + case MLXREG_LC_REG_MAX_POWER_OFFSET: > >> + case MLXREG_LC_REG_CONFIG_OFFSET: > >> + return true; > >> + } > >> + return false; > >> +} > >> + > >> +static bool mlxreg_lc_volatile_reg(struct device *dev, unsigned int > >> +reg) { > >> + switch (reg) { > >> + case MLXREG_LC_REG_CPLD1_VER_OFFSET: > >> + case MLXREG_LC_REG_FPGA1_VER_OFFSET: > >> + case MLXREG_LC_REG_CPLD1_PN_OFFSET: > >> + case MLXREG_LC_REG_FPGA1_PN_OFFSET: > >> + case MLXREG_LC_REG_RESET_CAUSE_OFFSET: > >> + case MLXREG_LC_REG_LED1_OFFSET: > >> + case MLXREG_LC_REG_GP0_OFFSET: > >> + case MLXREG_LC_REG_FIELD_UPGRADE: > >> + case MLXREG_LC_CHANNEL_I2C_REG: > >> + case MLXREG_LC_REG_CPLD1_MVER_OFFSET: > >> + case MLXREG_LC_REG_FPGA1_MVER_OFFSET: > >> + case MLXREG_LC_REG_MAX_POWER_OFFSET: > >> + case MLXREG_LC_REG_CONFIG_OFFSET: > >> + return true; > >> + } > >> + return false; > >> +} > >> + > >> +static const struct reg_default mlxreg_lc_regmap_default[] = { > >> + { MLXREG_LC_CHANNEL_I2C_REG, 0x00 }, }; > >> + > >> +/* Configuration for the register map of a device with 2 bytes > >> +address space. */ static const struct regmap_config > mlxreg_lc_regmap_conf = { > >> + .reg_bits = 16, > >> + .val_bits = 8, > >> + .max_register = MLXREG_LC_REG_MAX, > >> + .cache_type = REGCACHE_FLAT, > >> + .writeable_reg = mlxreg_lc_writeable_reg, > >> + .readable_reg = mlxreg_lc_readable_reg, > >> + .volatile_reg = mlxreg_lc_volatile_reg, > >> + .reg_defaults = mlxreg_lc_regmap_default, > >> + .num_reg_defaults = ARRAY_SIZE(mlxreg_lc_regmap_default), > >> +}; > >> + > >> +/* Default channels vector. > >> + * It contains only the channels, which physically connected to the > >> +devices, > >> + * empty channels are skipped. > >> + */ > >> +static int mlxreg_lc_chan[] = { > >> + 0x04, 0x05, 0x06, 0x07, 0x08, 0x10, 0x20, 0x21, 0x22, 0x23, 0x40, 0x41, > >> + 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, > >> + 0x4e, 0x4f > >> +}; > >> + > >> +/* Defaul mux configuration. */ > >> +static struct mlxcpld_mux_plat_data mlxreg_lc_mux_data[] = { > >> + { > >> + .chan_ids = mlxreg_lc_chan, > >> + .num_adaps = ARRAY_SIZE(mlxreg_lc_chan), > >> + .sel_reg_addr = MLXREG_LC_CHANNEL_I2C_REG, > >> + .reg_size = 2, > >> + }, > >> +}; > >> + > >> +/* Defaul mux board info. */ > >> +static struct i2c_board_info mlxreg_lc_mux_brdinfo = { > >> + I2C_BOARD_INFO("i2c-mux-mlxcpld", 0x32), }; > >> + > >> +/* Line card default auxiliary power static devices. */ static > >> +struct i2c_board_info mlxreg_lc_aux_pwr_devices[] = { > >> + { > >> + I2C_BOARD_INFO("24c32", 0x51), > >> + }, > >> + { > >> + I2C_BOARD_INFO("24c32", 0x51), > >> + }, > >> +}; > >> + > >> +/* Line card default auxiliary power board info. */ static struct > >> +mlxreg_hotplug_device mlxreg_lc_aux_pwr_brdinfo[] = { > >> + { > >> + .brdinfo = &mlxreg_lc_aux_pwr_devices[0], > >> + .nr = 3, > >> + }, > >> + { > >> + .brdinfo = &mlxreg_lc_aux_pwr_devices[1], > >> + .nr = 4, > >> + }, > >> +}; > >> + > >> +/* Line card default main power static devices. */ static struct > >> +i2c_board_info mlxreg_lc_main_pwr_devices[] = { > >> + { > >> + I2C_BOARD_INFO("mp2975", 0x62), > >> + }, > >> + { > >> + I2C_BOARD_INFO("mp2975", 0x64), > >> + }, > >> + { > >> + I2C_BOARD_INFO("max11603", 0x6d), > >> + }, > >> + { > >> + I2C_BOARD_INFO("lm25066", 0x15), > >> + }, > >> +}; > >> + > >> +/* Line card default main power board info. */ static struct > >> +mlxreg_hotplug_device mlxreg_lc_main_pwr_brdinfo[] = { > >> + { > >> + .brdinfo = &mlxreg_lc_main_pwr_devices[0], > >> + .nr = 0, > >> + }, > >> + { > >> + .brdinfo = &mlxreg_lc_main_pwr_devices[1], > >> + .nr = 0, > >> + }, > >> + { > >> + .brdinfo = &mlxreg_lc_main_pwr_devices[2], > >> + .nr = 1, > >> + }, > >> + { > >> + .brdinfo = &mlxreg_lc_main_pwr_devices[3], > >> + .nr = 2, > >> + }, > >> +}; > >> + > >> +/* LED default data. */ > >> +static struct mlxreg_core_data mlxreg_lc_led_data[] = { > >> + { > >> + .label = "status:green", > >> + .reg = MLXREG_LC_REG_LED1_OFFSET, > >> + .mask = GENMASK(7, 4), > >> + }, > >> + { > >> + .label = "status:orange", > >> + .reg = MLXREG_LC_REG_LED1_OFFSET, > >> + .mask = GENMASK(7, 4), > >> + }, > >> +}; > >> + > >> +static struct mlxreg_core_platform_data mlxreg_lc_led = { > >> + .identity = "pci", > >> + .data = mlxreg_lc_led_data, > >> + .counter = ARRAY_SIZE(mlxreg_lc_led_data), }; > >> + > >> +/* Default register access data. */ > >> +static struct mlxreg_core_data mlxreg_lc_io_data[] = { > >> + { > >> + .label = "cpld1_version", > >> + .reg = MLXREG_LC_REG_CPLD1_VER_OFFSET, > >> + .bit = GENMASK(7, 0), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "fpga1_version", > >> + .reg = MLXREG_LC_REG_FPGA1_VER_OFFSET, > >> + .bit = GENMASK(7, 0), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "cpld1_pn", > >> + .reg = MLXREG_LC_REG_CPLD1_PN_OFFSET, > >> + .bit = GENMASK(15, 0), > >> + .mode = 0444, > >> + .regnum = 2, > >> + }, > >> + { > >> + .label = "fpga1_pn", > >> + .reg = MLXREG_LC_REG_FPGA1_PN_OFFSET, > >> + .bit = GENMASK(15, 0), > >> + .mode = 0444, > >> + .regnum = 2, > >> + }, > >> + { > >> + .label = "cpld1_version_min", > >> + .reg = MLXREG_LC_REG_CPLD1_MVER_OFFSET, > >> + .bit = GENMASK(7, 0), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "fpga1_version_min", > >> + .reg = MLXREG_LC_REG_FPGA1_MVER_OFFSET, > >> + .bit = GENMASK(7, 0), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "reset_fpga_not_done", > >> + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(1), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "reset_aux_pwr_or_ref", > >> + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(2), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "reset_dc_dc_pwr_fail", > >> + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(3), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "reset_from_chassis", > >> + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(4), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "reset_pwr_off_from_chassis", > >> + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(5), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "reset_line_card", > >> + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(6), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "reset_line_card_pwr_en", > >> + .reg = MLXREG_LC_REG_RESET_CAUSE_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(7), > >> + .mode = 0444, > >> + }, > >> + { > >> + .label = "cpld_upgrade_en", > >> + .reg = MLXREG_LC_REG_FIELD_UPGRADE, > >> + .mask = GENMASK(7, 0) & ~BIT(0), > >> + .mode = 0644, > >> + .secured = 1, > >> + }, > >> + { > >> + .label = "fpga_upgrade_en", > >> + .reg = MLXREG_LC_REG_FIELD_UPGRADE, > >> + .mask = GENMASK(7, 0) & ~BIT(1), > >> + .mode = 0644, > >> + .secured = 1, > >> + }, > >> + { > >> + .label = "qsfp_pwr_en", > >> + .reg = MLXREG_LC_REG_GP0_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(0), > >> + .mode = 0644, > >> + }, > >> + { > >> + .label = "vpd_wp", > >> + .reg = MLXREG_LC_REG_GP0_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(3), > >> + .mode = 0644, > >> + .secured = 1, > >> + }, > >> + { > >> + .label = "agb_spi_burn_en", > >> + .reg = MLXREG_LC_REG_GP0_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(5), > >> + .mode = 0644, > >> + .secured = 1, > >> + }, > >> + { > >> + .label = "fpga_spi_burn_en", > >> + .reg = MLXREG_LC_REG_GP0_OFFSET, > >> + .mask = GENMASK(7, 0) & ~BIT(6), > >> + .mode = 0644, > >> + .secured = 1, > >> + }, > >> + { > >> + .label = "max_power", > >> + .reg = MLXREG_LC_REG_MAX_POWER_OFFSET, > >> + .bit = GENMASK(15, 0), > >> + .mode = 0444, > >> + .regnum = 2, > >> + }, > >> + { > >> + .label = "config", > >> + .reg = MLXREG_LC_REG_CONFIG_OFFSET, > >> + .bit = GENMASK(15, 0), > >> + .mode = 0444, > >> + .regnum = 2, > >> + }, > >> +}; > >> + > >> +static struct mlxreg_core_platform_data mlxreg_lc_regs_io = { > >> + .data = mlxreg_lc_io_data, > >> + .counter = ARRAY_SIZE(mlxreg_lc_io_data), }; > >> + > >> +static int > >> +mlxreg_lc_create_static_devices(struct mlxreg_lc *mlxreg_lc, struct > mlxreg_hotplug_device *devs, > >> + int size) > >> +{ > >> + struct mlxreg_hotplug_device *dev = devs; > >> + int i; > >> + > >> + /* Create static I2C device feeding by auxiliary or main power. */ > >> + for (i = 0; i < size; i++, dev++) { > >> + dev->client = i2c_new_client_device(dev->adapter, dev- > >brdinfo); > >> + if (IS_ERR(dev->client)) { > >> + dev_err(mlxreg_lc->dev, "Failed to create client %s > at bus %d at addr 0x%02x\n", > >> + dev->brdinfo->type, dev->nr, dev->brdinfo- > >addr); > >> + > >> + dev->adapter = NULL; > >> + goto fail_create_static_devices; > >> + } > >> + } > >> + > >> + return 0; > >> + > >> +fail_create_static_devices: > >> + while (--i >= 0) { > >> + dev = devs + i; > >> + i2c_unregister_device(dev->client); > >> + dev->client = NULL; > >> + } > >> + return IS_ERR(dev->client); > >> +} > >> + > >> +static void > >> +mlxreg_lc_destroy_static_devices(struct mlxreg_lc *mlxreg_lc, struct > mlxreg_hotplug_device *devs, > >> + int size) > >> +{ > >> + struct mlxreg_hotplug_device *dev = devs; > >> + int i; > >> + > >> + /* Destroy static I2C device feeding by auxiliary or main power. */ > >> + for (i = 0; i < size; i++, dev++) { > >> + if (dev->client) { > >> + i2c_unregister_device(dev->client); > >> + dev->client = NULL; > >> + } > >> + } > >> +} > >> + > >> +static int mlxreg_lc_power_on_off(struct mlxreg_lc *mlxreg_lc, u8 > >> +action) { > >> + u32 regval; > >> + int err; > >> + > >> + mutex_lock(&mlxreg_lc->lock); > >> + > >> + err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data- > >reg_pwr, ®val); > >> + if (err) > >> + goto regmap_read_fail; > >> + > >> + if (action) > >> + regval |= BIT(mlxreg_lc->data->slot - 1); > >> + else > >> + regval &= ~BIT(mlxreg_lc->data->slot - 1); > >> + > >> + err = regmap_write(mlxreg_lc->par_regmap, mlxreg_lc->data- > >reg_pwr, > >> +regval); > >> + > >> +regmap_read_fail: > >> + mutex_unlock(&mlxreg_lc->lock); > >> + return err; > >> +} > >> + > >> +static int mlxreg_lc_enable_disable(struct mlxreg_lc *mlxreg_lc, > >> +bool action) { > >> + u32 regval; > >> + int err; > >> + > >> + /* > >> + * Hardware holds the line card after powering on in the disabled > state. Holding line card > >> + * in disabled state protects access to the line components, like FPGA > and gearboxes. > >> + * Line card should be enabled in order to get it in operational state. > Line card could be > >> + * disabled for moving it to non-operational state. Enabling line card > does not affect the > >> + * line card which is already has been enabled. Disabling does not > affect the disabled line > >> + * card. > >> + */ > >> + mutex_lock(&mlxreg_lc->lock); > >> + > >> + err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data- > >reg_ena, ®val); > >> + if (err) > >> + goto regmap_read_fail; > >> + > >> + if (action) > >> + regval |= BIT(mlxreg_lc->data->slot - 1); > >> + else > >> + regval &= ~BIT(mlxreg_lc->data->slot - 1); > >> + > >> + err = regmap_write(mlxreg_lc->par_regmap, mlxreg_lc->data- > >reg_ena, > >> +regval); > >> + > >> +regmap_read_fail: > >> + mutex_unlock(&mlxreg_lc->lock); > >> + return err; > >> +} > >> + > >> +static int > >> +mlxreg_lc_sn4800_c16_config_init(struct mlxreg_lc *mlxreg_lc, void > *regmap, > >> + struct mlxreg_core_data *data) > >> +{ > >> + struct device *dev = &data->hpdev.client->dev; > >> + > >> + /* Set line card configuration according to the type. */ > >> + mlxreg_lc->mux_data = mlxreg_lc_mux_data; > >> + mlxreg_lc->io_data = &mlxreg_lc_regs_io; > >> + mlxreg_lc->led_data = &mlxreg_lc_led; > >> + mlxreg_lc->mux_brdinfo = &mlxreg_lc_mux_brdinfo; > >> + > >> + mlxreg_lc->aux_devs = devm_kmemdup(dev, > mlxreg_lc_aux_pwr_brdinfo, > >> + > sizeof(mlxreg_lc_aux_pwr_brdinfo), GFP_KERNEL); > >> + if (!mlxreg_lc->aux_devs) > >> + return -ENOMEM; > >> + mlxreg_lc->aux_devs_num = > ARRAY_SIZE(mlxreg_lc_aux_pwr_brdinfo); > >> + mlxreg_lc->main_devs = devm_kmemdup(dev, > mlxreg_lc_main_pwr_brdinfo, > >> + > sizeof(mlxreg_lc_main_pwr_brdinfo), GFP_KERNEL); > >> + if (!mlxreg_lc->main_devs) > >> + return -ENOMEM; > >> + mlxreg_lc->main_devs_num = > ARRAY_SIZE(mlxreg_lc_main_pwr_brdinfo); > >> + > >> + return 0; > >> +} > >> + > >> +static void > >> +mlxreg_lc_state_update(struct mlxreg_lc *mlxreg_lc, enum > >> +mlxreg_lc_state state, u8 action) { > >> + mutex_lock(&mlxreg_lc->lock); > >> + > >> + if (action) > >> + mlxreg_lc->state |= state; > >> + else > >> + mlxreg_lc->state &= ~state; > >> + > >> + mutex_unlock(&mlxreg_lc->lock); > >> +} > >> + > >> +/* > >> + * Callback is to be called from mlxreg-hotplug driver to notify > >> +about line card about received > >> + * event. > >> + */ > >> +static int mlxreg_lc_event_handler(void *handle, enum > >> +mlxreg_hotplug_kind kind, u8 action) { > >> + struct mlxreg_lc *mlxreg_lc = handle; > >> + int err = 0; > >> + > >> + dev_info(mlxreg_lc->dev, "linecard#%d state %d event kind %d > action %d\n", > >> + mlxreg_lc->data->slot, mlxreg_lc->state, kind, action); > >> + > >> + if (!(mlxreg_lc->state & MLXREG_LC_INITIALIZED)) > >> + return 0; > >> + > >> + switch (kind) { > >> + case MLXREG_HOTPLUG_LC_SYNCED: > >> + /* > >> + * Synchronization event - hardware and firmware are > synchronized. Power on/off > >> + * line card - to allow/disallow main power source. > >> + */ > >> + mlxreg_lc_state_update(mlxreg_lc, MLXREG_LC_SYNCED, > action); > >> + /* Power line card if it is not powered yet. */ > >> + if (!(mlxreg_lc->state & MLXREG_LC_POWERED) && action) { > >> + err = mlxreg_lc_power_on_off(mlxreg_lc, 1); > >> + if (err) > >> + return err; > >> + } > >> + /* In case line card is configured - enable it. */ > >> + if (mlxreg_lc->state & MLXREG_LC_CONFIGURED && action) > >> + err = mlxreg_lc_enable_disable(mlxreg_lc, 1); > >> + break; > >> + case MLXREG_HOTPLUG_LC_POWERED: > >> + /* Power event - attach or de-attach line card device feeding > by the main power. */ > >> + if (action) { > >> + /* Do not create devices, if line card is already > powered. */ > >> + if (mlxreg_lc->state & MLXREG_LC_POWERED) { > >> + /* In case line card is configured - enable it. > */ > >> + if (mlxreg_lc->state & > MLXREG_LC_CONFIGURED) > >> + err = > mlxreg_lc_enable_disable(mlxreg_lc, 1); > >> + return err; > >> + } > >> + err = mlxreg_lc_create_static_devices(mlxreg_lc, > mlxreg_lc->main_devs, > >> + mlxreg_lc- > >main_devs_num); > >> + if (err) > >> + return err; > >> + > >> + /* In case line card is already in ready state - enable > it. */ > >> + if (mlxreg_lc->state & MLXREG_LC_CONFIGURED) > >> + err = mlxreg_lc_enable_disable(mlxreg_lc, > 1); > >> + } else { > >> + mlxreg_lc_destroy_static_devices(mlxreg_lc, > mlxreg_lc->main_devs, > >> + mlxreg_lc- > >main_devs_num); > >> + } > >> + mlxreg_lc_state_update(mlxreg_lc, MLXREG_LC_POWERED, > action); > >> + break; > >> + case MLXREG_HOTPLUG_LC_READY: > >> + /* > >> + * Ready event – enable line card by releasing it from reset or > disable it by put > >> + * to reset state. > >> + */ > >> + err = mlxreg_lc_enable_disable(mlxreg_lc, !!action); > >> + break; > >> + case MLXREG_HOTPLUG_LC_THERMAL: > >> + /* Thermal shutdown event – power off line card. */ > >> + if (action) > >> + err = mlxreg_lc_power_on_off(mlxreg_lc, 0); > >> + break; > >> + default: > >> + break; > >> + } > >> + > >> + return err; > >> +} > >> + > >> +/* > >> + * Callback is to be called from i2c-mux-mlxcpld driver to indicate > >> +that all adapter devices has > >> + * been created. > >> + */ > >> +static int mlxreg_lc_completion_notify(void *handle, struct i2c_adapter > *parent, > >> + struct i2c_adapter *adapters[]) { > >> + struct mlxreg_hotplug_device *main_dev, *aux_dev; > >> + struct mlxreg_lc *mlxreg_lc = handle; > >> + u32 regval; > >> + int i, err; > >> + > >> + /* Update I2C devices feeding by auxiliary power. */ > >> + aux_dev = mlxreg_lc->aux_devs; > >> + for (i = 0; i < mlxreg_lc->aux_devs_num; i++, aux_dev++) { > >> + aux_dev->adapter = adapters[aux_dev->nr]; > >> + aux_dev->nr = adapters[aux_dev->nr]->nr; > >> + } > >> + > >> + err = mlxreg_lc_create_static_devices(mlxreg_lc, mlxreg_lc- > >aux_devs, > >> + mlxreg_lc->aux_devs_num); > >> + if (err) > >> + return err; > >> + > >> + /* Update I2C devices feeding by main power. */ > >> + main_dev = mlxreg_lc->main_devs; > >> + for (i = 0; i < mlxreg_lc->main_devs_num; i++, main_dev++) { > >> + main_dev->adapter = adapters[main_dev->nr]; > >> + main_dev->nr = adapters[main_dev->nr]->nr; > >> + } > >> + > >> + /* Verify if line card is powered. */ > >> + err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data- > >reg_pwr, ®val); > >> + if (err) > >> + goto mlxreg_lc_regmap_read_power_fail; > >> + > >> + if (regval & mlxreg_lc->data->mask) { > >> + err = mlxreg_lc_create_static_devices(mlxreg_lc, mlxreg_lc- > >main_devs, > >> + mlxreg_lc- > >main_devs_num); > >> + if (err) > >> + goto mlxreg_lc_create_static_devices_failed; > >> + > >> + mlxreg_lc_state_update(mlxreg_lc, MLXREG_LC_POWERED, > 1); > >> + } > >> + > >> + /* Verify if line card is synchronized. */ > >> + err = regmap_read(mlxreg_lc->par_regmap, mlxreg_lc->data- > >reg_sync, ®val); > >> + if (err) > >> + goto mlxreg_lc_regmap_read_sync_fail; > >> + > >> + /* Power on line card if necessary. */ > >> + if (regval & mlxreg_lc->data->mask) { > >> + mlxreg_lc->state |= MLXREG_LC_SYNCED; > >> + mlxreg_lc_state_update(mlxreg_lc, MLXREG_LC_SYNCED, 1); > >> + if (mlxreg_lc->state & ~MLXREG_LC_POWERED) { > >> + err = mlxreg_lc_power_on_off(mlxreg_lc, 1); > >> + if (err) > >> + goto mlxreg_lc_regmap_power_on_off_fail; > >> + } > >> + } > >> + > >> + mlxreg_lc_state_update(mlxreg_lc, MLXREG_LC_INITIALIZED, 1); > >> + > >> + return 0; > >> + > >> +mlxreg_lc_regmap_power_on_off_fail: > >> +mlxreg_lc_regmap_read_sync_fail: > >> + if (mlxreg_lc->state & MLXREG_LC_POWERED) > >> + mlxreg_lc_destroy_static_devices(mlxreg_lc, mlxreg_lc- > >main_devs, > >> + mlxreg_lc- > >main_devs_num); > >> +mlxreg_lc_create_static_devices_failed: > >> + mlxreg_lc_destroy_static_devices(mlxreg_lc, mlxreg_lc->aux_devs, > >> +mlxreg_lc->aux_devs_num); > >> +mlxreg_lc_regmap_read_power_fail: > >> + return err; > >> +} > >> + > >> +static int > >> +mlxreg_lc_config_init(struct mlxreg_lc *mlxreg_lc, void *regmap, > >> + struct mlxreg_core_data *data) { > >> + struct device *dev = &data->hpdev.client->dev; > >> + int lsb, err; > >> + u32 regval; > >> + > >> + /* Validate line card type. */ > >> + err = regmap_read(regmap, MLXREG_LC_REG_CONFIG_OFFSET, > &lsb); > >> + err = (!err) ? regmap_read(regmap, > MLXREG_LC_REG_CONFIG_OFFSET, ®val) : err; > >> + if (err) > >> + return err; > >> + regval = (regval & GENMASK(7, 0)) << 8 | (lsb & GENMASK(7, 0)); > >> + switch (regval) { > >> + case MLXREG_LC_SN4800_C16: > >> + err = mlxreg_lc_sn4800_c16_config_init(mlxreg_lc, regmap, > data); > >> + if (err) > >> + return err; > >> + break; > >> + default: > >> + return -ENODEV; > >> + } > >> + > >> + /* Create mux infrastructure. */ > >> + mlxreg_lc->mux_data->handle = mlxreg_lc; > >> + mlxreg_lc->mux_data->completion_notify = > mlxreg_lc_completion_notify; > >> + mlxreg_lc->mux_brdinfo->platform_data = mlxreg_lc->mux_data; > >> + mlxreg_lc->mux = platform_device_register_resndata(dev, "i2c- > mux-mlxcpld", data->hpdev.nr, > >> + NULL, 0, mlxreg_lc- > >mux_data, > >> + sizeof(*mlxreg_lc- > >mux_data)); > >> + if (IS_ERR(mlxreg_lc->mux)) > >> + return PTR_ERR(mlxreg_lc->mux); > >> + > >> + /* Register IO access driver. */ > >> + if (mlxreg_lc->io_data) { > >> + mlxreg_lc->io_data->regmap = regmap; > >> + mlxreg_lc->io_regs = > >> + platform_device_register_resndata(dev, "mlxreg-io", data- > >hpdev.nr, NULL, 0, > >> + mlxreg_lc->io_data, > sizeof(*mlxreg_lc->io_data)); > >> + if (IS_ERR(mlxreg_lc->io_regs)) { > >> + err = PTR_ERR(mlxreg_lc->io_regs); > >> + goto fail_register_io; > >> + } > >> + } > >> + > >> + /* Register LED driver. */ > >> + if (mlxreg_lc->led_data) { > >> + mlxreg_lc->led_data->regmap = regmap; > >> + mlxreg_lc->led = > >> + platform_device_register_resndata(dev, "leds-mlxreg", > data->hpdev.nr, NULL, 0, > >> + mlxreg_lc->led_data, > >> + sizeof(*mlxreg_lc- > >led_data)); > >> + if (IS_ERR(mlxreg_lc->led)) { > >> + err = PTR_ERR(mlxreg_lc->led); > >> + goto fail_register_led; > >> + } > >> + } > >> + > >> + return 0; > >> + > >> +fail_register_led: > >> + if (mlxreg_lc->io_regs) > >> + platform_device_unregister(mlxreg_lc->io_regs); > >> +fail_register_io: > >> + if (mlxreg_lc->mux) > >> + platform_device_unregister(mlxreg_lc->mux); > >> + > >> + return err; > >> +} > >> + > >> +static void mlxreg_lc_config_exit(struct mlxreg_lc *mlxreg_lc) { > >> + /* Unregister LED driver. */ > >> + if (mlxreg_lc->led) > >> + platform_device_unregister(mlxreg_lc->led); > >> + /* Unregister IO access driver. */ > >> + if (mlxreg_lc->io_regs) > >> + platform_device_unregister(mlxreg_lc->io_regs); > >> + /* Remove mux infrastructure. */ > >> + if (mlxreg_lc->mux) > >> + platform_device_unregister(mlxreg_lc->mux); > >> +} > >> + > >> +static int mlxreg_lc_probe(struct platform_device *pdev) { > >> + struct mlxreg_core_hotplug_platform_data *par_pdata; > >> + struct mlxreg_core_data *data; > >> + struct mlxreg_lc *mlxreg_lc; > >> + void *regmap; > >> + int i, err; > >> + > >> + data = dev_get_platdata(&pdev->dev); > >> + if (!data) > >> + return -EINVAL; > >> + > >> + mlxreg_lc = devm_kzalloc(&pdev->dev, sizeof(*mlxreg_lc), > GFP_KERNEL); > >> + if (!mlxreg_lc) > >> + return -ENOMEM; > >> + > >> + mutex_init(&mlxreg_lc->lock); > >> + /* Set event notification callback. */ > >> + if (data->notifier) { > >> + data->notifier->user_handler = mlxreg_lc_event_handler; > >> + data->notifier->handle = mlxreg_lc; > >> + } > >> + data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr); > >> + if (!data->hpdev.adapter) { > >> + dev_err(&pdev->dev, "Failed to get adapter for bus %d\n", > >> + data->hpdev.nr); > >> + return -EFAULT; > >> + } > >> + > >> + /* Create device at the top of line card I2C tree.*/ > >> + data->hpdev.client = i2c_new_client_device(data->hpdev.adapter, > >> + data->hpdev.brdinfo); > >> + if (IS_ERR(data->hpdev.client)) { > >> + dev_err(&pdev->dev, "Failed to create client %s at bus %d at > addr 0x%02x\n", > >> + data->hpdev.brdinfo->type, data->hpdev.nr, > >> +data->hpdev.brdinfo->addr); > >> + > >> + i2c_put_adapter(data->hpdev.adapter); > >> + data->hpdev.adapter = NULL; > >> + return PTR_ERR(data->hpdev.client); > >> + } > >> + > >> + regmap = devm_regmap_init_i2c(data->hpdev.client, > >> + &mlxreg_lc_regmap_conf); > >> + if (IS_ERR(regmap)) { > >> + err = PTR_ERR(regmap); > >> + goto mlxreg_lc_probe_fail; > >> + } > >> + > >> + /* Set default registers. */ > >> + for (i = 0; i < mlxreg_lc_regmap_conf.num_reg_defaults; i++) { > >> + err = regmap_write(regmap, > mlxreg_lc_regmap_default[i].reg, > >> + mlxreg_lc_regmap_default[i].def); > >> + if (err) > >> + goto mlxreg_lc_probe_fail; > >> + } > >> + > >> + /* Sync registers with hardware. */ > >> + regcache_mark_dirty(regmap); > >> + err = regcache_sync(regmap); > >> + if (err) > >> + goto mlxreg_lc_probe_fail; > >> + > >> + par_pdata = data->hpdev.brdinfo->platform_data; > >> + mlxreg_lc->par_regmap = par_pdata->regmap; > >> + mlxreg_lc->data = data; > >> + mlxreg_lc->dev = &pdev->dev; > >> + platform_set_drvdata(pdev, mlxreg_lc); > >> + > >> + /* Configure line card. */ > >> + err = mlxreg_lc_config_init(mlxreg_lc, regmap, data); > >> + if (err) > >> + goto mlxreg_lc_probe_fail; > >> + > >> + return err; > >> + > >> +mlxreg_lc_probe_fail: > >> + i2c_put_adapter(data->hpdev.adapter); > >> + return err; > >> +} > >> + > >> +static int mlxreg_lc_remove(struct platform_device *pdev) { > >> + struct mlxreg_core_data *data = dev_get_platdata(&pdev->dev); > >> + struct mlxreg_lc *mlxreg_lc = platform_get_drvdata(pdev); > >> + > >> + /* Clear event notification callback. */ > >> + if (data->notifier) { > >> + data->notifier->user_handler = NULL; > >> + data->notifier->handle = NULL; > >> + } > >> + > >> + /* Destroy static I2C device feeding by main power. */ > >> + mlxreg_lc_destroy_static_devices(mlxreg_lc, mlxreg_lc->main_devs, > >> + mlxreg_lc->main_devs_num); > >> + /* Destroy static I2C device feeding by auxiliary power. */ > >> + mlxreg_lc_destroy_static_devices(mlxreg_lc, mlxreg_lc->aux_devs, > mlxreg_lc->aux_devs_num); > >> + /* Unregister underlying drivers. */ > >> + mlxreg_lc_config_exit(mlxreg_lc); > >> + if (data->hpdev.client) { > >> + i2c_unregister_device(data->hpdev.client); > >> + data->hpdev.client = NULL; > >> + i2c_put_adapter(data->hpdev.adapter); > >> + data->hpdev.adapter = NULL; > >> + } > >> + > >> + return 0; > >> +} > >> + > >> +static struct platform_driver mlxreg_lc_driver = { > >> + .probe = mlxreg_lc_probe, > >> + .remove = mlxreg_lc_remove, > >> + .driver = { > >> + .name = "mlxreg-lc", > >> + }, > >> +}; > >> + > >> +module_platform_driver(mlxreg_lc_driver); > >> + > >> +MODULE_AUTHOR("Vadim Pasternak <vadimp@nvidia.com>"); > >> +MODULE_DESCRIPTION("Nvidia line card platform driver"); > >> +MODULE_LICENSE("Dual BSD/GPL"); MODULE_ALIAS("platform:mlxreg- > lc"); > >> ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH platform-next 08/10] Documentation/ABI: Add new attributes for mlxreg-io sysfs interfaces 2021-10-02 9:32 [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system Vadim Pasternak ` (6 preceding siblings ...) 2021-10-02 9:32 ` [PATCH platform-next 07/10] platform/mellanox: mlxreg-lc: Add initial support for Nvidia line card devices Vadim Pasternak @ 2021-10-02 9:32 ` Vadim Pasternak 2021-10-02 9:32 ` [PATCH platform-next 09/10] Documentation/ABI: Add new line card " Vadim Pasternak 8 siblings, 0 replies; 13+ messages in thread From: Vadim Pasternak @ 2021-10-02 9:32 UTC (permalink / raw) To: hdegoede; +Cc: platform-driver-x86, michaelsh, Vadim Pasternak Add documentation for the new attributes: - "bios_active_image"; "bios_auth_fail"; "bios_upgrade_fail"; "bios_safe_mode" to represent various BIOS statuses. - "lc{n}_enable" - for put/release the line card to/from enable state. - "lc{n}_pwr" - for power on/off the line card. - "lc{n}_rst_mask" - for line card reset state enforced by ASIC, when it sets it due to some abnormal ASIC behavior. - "psu3_on"; "psu4_on" - for connection/disconnection power supply unit to/from the power source. - "pm_mgmt_en" - for setting power management control ownership. When power management control is provided by hardware, it means that hardware will automatically power off one or more line cards in case system power budget is under power required for feeding all powered on line cards. It could be a case, when some of power units lost power good state. - "shutdown_unlock" - for unlocking system after hardware or firmware thermal shutdown, which causes locking of the all interfaces to ASIC. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> --- .../ABI/stable/sysfs-driver-mlxreg-io | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io index b2553df2e786..6ef6979c9448 100644 --- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io +++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io @@ -223,3 +223,141 @@ Description: These files show with which CPLD part numbers and minor system. The files are read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/bios_active_image +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/bios_auth_fail +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/bios_upgrade_fail +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: The files represent BIOS statuses: + - bios_active_image: location of current active BIOS image: + 0: Top, 1: Bottom. + The reported value should correspond to value expected by OS + in case of BIOS safe mode is 0. This bit is related to Intel + top-swap feature of DualBios on the same flash. + - bios_auth_fail: BIOS upgrade is failed because provided BIOS + image is not signed correctly. + - bios_upgrade_fail: BIOS upgrade is failed by some other + reason not because authentication. For example due to + physical SPI flash problem. + + The files are read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc1_enable +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc2_enable +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc3_enable +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc4_enable +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc5_enable +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc6_enable +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc7_enable +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc8_enable +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files allow line cards enable state control. + Expected behavior: + When lc{n}_enable is written 1, related line card is released + from the reset state, when 0 - is hold in reset state. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc1_pwr +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc2_pwr +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc3_pwr +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc4_pwr +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc5_pwr +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc6_pwr +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc7_pwr +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc8_pwr +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files switching line cards power on and off. + Expected behavior: + When lc{n}_pwr is written 1, related line card is powered + on, when written 0 - powered off. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc1_rst_mask +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc2_rst_mask +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc3_rst_mask +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc4_rst_mask +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc5_rst_mask +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc6_rst_mask +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc7_rst_mask +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lc8_rst_mask +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files clear line card reset bit enforced by ASIC, when it + sets it due to some abnormal ASIC behavior. + Expected behavior: + When lc{n}_rst_mask is written 1, related line card reset bit + is cleared, when written 0 - no effect. + + The files are write only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/os_started +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file, when written 1, indicates to programmable devices + that OS is taking control over it. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pm_mgmt_en +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file assigns power management control ownership. + When power management control is provided by hardware, hardware + will automatically power off one or more line previously + powered line cards in case system power budget is getting + insufficient. It could be in case when some of power units lost + power good state. + When pm_mgmt_en is written 1, power management control by + software is enabled, 0 - power management control by hardware. + Note that for any setting of pm_mgmt_en attribute hardware will + not allow to power on any new line card in case system power + budget is insufficient. + Same in case software will try to power on several line cards + at once - hardware will power line cards while system has + enough power budget. + Default is 0. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu3_on +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/psu4_on +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files switching power supply units on and off. + Expected behavior: + When psu3_on or psu4_on is written 1, related unit will be + disconnected from the power source, when written 0 - connected. + + The files are write only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/shutdown_unlock +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file allows to unlock ASIC after thermal shutdown event. + When system thermal shutdown is enforced by ASIC, ASIC is + getting locked and after system boot it will not be available. + Software can decide to unlock it by setting this attribute to + 1 and then perform system power cycle by setting pwr_cycle + attribute to 1 (power cycle of main power domain). + Before setting shutdown_unlock to 1 it is recommended to + validate that system reboot cause is reset_asic_thermal or + reset_thermal_spc_or_pciesw. + In case shutdown_unlock is not set 1, the only way to release + ASIC from locking - is full system power cycle through the + external power distribution unit. + Default is 1. + + The file is read/write. -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH platform-next 09/10] Documentation/ABI: Add new line card attributes for mlxreg-io sysfs interfaces 2021-10-02 9:32 [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system Vadim Pasternak ` (7 preceding siblings ...) 2021-10-02 9:32 ` [PATCH platform-next 08/10] Documentation/ABI: Add new attributes for mlxreg-io sysfs interfaces Vadim Pasternak @ 2021-10-02 9:32 ` Vadim Pasternak 2021-10-19 8:57 ` Hans de Goede 8 siblings, 1 reply; 13+ messages in thread From: Vadim Pasternak @ 2021-10-02 9:32 UTC (permalink / raw) To: hdegoede; +Cc: platform-driver-x86, michaelsh, Vadim Pasternak Add documentation for the new attributes for line cards: - CPLDs versioning. - Write protection control for 'nvram' devices. - Line card reset reasons. - Enabling burning of FPGA and CPLDs. - Enabling burning of FPGA and gearbox SPI flashes, - Enabling power of whole line card. - Enabling power of QSFP ports equipped on line card. - The maximum powered required for line card feeding. - Line card configuration Id. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> --- .../ABI/stable/sysfs-driver-mlxreg-io | 103 ++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io index 6ef6979c9448..b25e963ec0fa 100644 --- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io +++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io @@ -361,3 +361,106 @@ Description: This file allows to unlock ASIC after thermal shutdown event. Default is 1. The file is read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_pn +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_version +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_version_min +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files show with which CPLD major and minor versions + and part number has been burned CPLD device on line card. + + The files are read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_pn +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_version +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_version_min +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files show with which FPGA major and minor versions + and part number has been burned FPGA device on line card. + + The files are read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/vpd_wp +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: This file allow to overwrite line card VPD hardware write + protection mode. When attribute is set 1 - write protection is + disabled, when 0 - enabled. + Default is 0. + If the system is in locked-down mode writing this file will not + be allowed. + The purpose if this file is to allow line card VPD burning + during production flow. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_aux_pwr_or_ref +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_dc_dc_pwr_fail +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_fpga_not_done +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_from_chassis +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_line_card +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_pwr_off_from_chassis +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files show the line reset cause, as following: power + auxiliary outage or power refresh, DC-to-DC power failure, FPGA reset + failed, line card reset failed, power off from chassis. + Value 1 in file means this is reset cause, 0 - otherwise. Only one of + the above causes could be 1 at the same time, representing only last + reset cause. + + The files are read only. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld_upgrade_en +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga_upgrade_en +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files allow CPLD and FPGA burning. Value 1 in file means burning + is enabled, 0 - otherwise. + If the system is in locked-down mode writing these files will + not be allowed. + The purpose of these files to allow line card CPLD and FPGA + upgrade through the JTAG daisy-chain. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/qsfp_pwr_en +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/pwr_en +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files allow to power on/off all QSFP ports and whole line card. + The attributes are set 1 for power on, 0 - for power off. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/agb_spi_burn_en +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga_spi_burn_en +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files allow gearboxes and FPGA SPI flash burning. + The attributes are set 1 to enable burning, 0 - to disable. + If the system is in locked-down mode writing these files will + not be allowed. + The purpose of these files to allow line card Gearboxes and FPGA + burning during production flow. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/max_power +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/config +Date: October 2021 +KernelVersion: 5.16 +Contact: Vadim Pasternak <vadimp@nvidia.com> +Description: These files provide the maximum powered required for line card + feeding and line card configuration Id. + + The files are read only. -- 2.20.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH platform-next 09/10] Documentation/ABI: Add new line card attributes for mlxreg-io sysfs interfaces 2021-10-02 9:32 ` [PATCH platform-next 09/10] Documentation/ABI: Add new line card " Vadim Pasternak @ 2021-10-19 8:57 ` Hans de Goede 2021-10-19 9:04 ` Vadim Pasternak 0 siblings, 1 reply; 13+ messages in thread From: Hans de Goede @ 2021-10-19 8:57 UTC (permalink / raw) To: Vadim Pasternak; +Cc: platform-driver-x86, michaelsh Hi, On 10/2/21 11:32, Vadim Pasternak wrote: > Add documentation for the new attributes for line cards: > - CPLDs versioning. > - Write protection control for 'nvram' devices. > - Line card reset reasons. > - Enabling burning of FPGA and CPLDs. > - Enabling burning of FPGA and gearbox SPI flashes, > - Enabling power of whole line card. > - Enabling power of QSFP ports equipped on line card. > - The maximum powered required for line card feeding. > - Line card configuration Id. > > Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> > Reviewed-by: Michael Shych <michaelsh@nvidia.com> Applying this gave the following warnings: Applying: Documentation/ABI: Add new line card attributes for mlxreg-io sysfs interfaces /home/hans/projects/linux/.git/worktrees/platform-drivers-x86/rebase-apply/patch:44: space before tab in indent. If the system is in locked-down mode writing this file will not /home/hans/projects/linux/.git/worktrees/platform-drivers-x86/rebase-apply/patch:76: space before tab in indent. If the system is in locked-down mode writing these files will /home/hans/projects/linux/.git/worktrees/platform-drivers-x86/rebase-apply/patch:100: space before tab in indent. If the system is in locked-down mode writing these files will warning: 3 lines add whitespace errors. I've fixed this up locally. FYI the 3 "If the system is in locked-down mode writing this file will not" lines started with <tab><space><tab> which I've replaced with <tab><tab>. Regards, Hans > --- > .../ABI/stable/sysfs-driver-mlxreg-io | 103 ++++++++++++++++++ > 1 file changed, 103 insertions(+) > > diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io > index 6ef6979c9448..b25e963ec0fa 100644 > --- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io > +++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io > @@ -361,3 +361,106 @@ Description: This file allows to unlock ASIC after thermal shutdown event. > Default is 1. > > The file is read/write. > + > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_pn > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_version > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_version_min > +Date: October 2021 > +KernelVersion: 5.16 > +Contact: Vadim Pasternak <vadimp@nvidia.com> > +Description: These files show with which CPLD major and minor versions > + and part number has been burned CPLD device on line card. > + > + The files are read only. > + > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_pn > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_version > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_version_min > +Date: October 2021 > +KernelVersion: 5.16 > +Contact: Vadim Pasternak <vadimp@nvidia.com> > +Description: These files show with which FPGA major and minor versions > + and part number has been burned FPGA device on line card. > + > + The files are read only. > + > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/vpd_wp > +Date: October 2021 > +KernelVersion: 5.16 > +Contact: Vadim Pasternak <vadimp@nvidia.com> > +Description: This file allow to overwrite line card VPD hardware write > + protection mode. When attribute is set 1 - write protection is > + disabled, when 0 - enabled. > + Default is 0. > + If the system is in locked-down mode writing this file will not > + be allowed. > + The purpose if this file is to allow line card VPD burning > + during production flow. > + > + The file is read/write. > + > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_aux_pwr_or_ref > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_dc_dc_pwr_fail > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_fpga_not_done > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_from_chassis > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_line_card > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_pwr_off_from_chassis > +Date: October 2021 > +KernelVersion: 5.16 > +Contact: Vadim Pasternak <vadimp@nvidia.com> > +Description: These files show the line reset cause, as following: power > + auxiliary outage or power refresh, DC-to-DC power failure, FPGA reset > + failed, line card reset failed, power off from chassis. > + Value 1 in file means this is reset cause, 0 - otherwise. Only one of > + the above causes could be 1 at the same time, representing only last > + reset cause. > + > + The files are read only. > + > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld_upgrade_en > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga_upgrade_en > +Date: October 2021 > +KernelVersion: 5.16 > +Contact: Vadim Pasternak <vadimp@nvidia.com> > +Description: These files allow CPLD and FPGA burning. Value 1 in file means burning > + is enabled, 0 - otherwise. > + If the system is in locked-down mode writing these files will > + not be allowed. > + The purpose of these files to allow line card CPLD and FPGA > + upgrade through the JTAG daisy-chain. > + > + The files are read/write. > + > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/qsfp_pwr_en > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/pwr_en > +Date: October 2021 > +KernelVersion: 5.16 > +Contact: Vadim Pasternak <vadimp@nvidia.com> > +Description: These files allow to power on/off all QSFP ports and whole line card. > + The attributes are set 1 for power on, 0 - for power off. > + > + The files are read/write. > + > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/agb_spi_burn_en > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga_spi_burn_en > +Date: October 2021 > +KernelVersion: 5.16 > +Contact: Vadim Pasternak <vadimp@nvidia.com> > +Description: These files allow gearboxes and FPGA SPI flash burning. > + The attributes are set 1 to enable burning, 0 - to disable. > + If the system is in locked-down mode writing these files will > + not be allowed. > + The purpose of these files to allow line card Gearboxes and FPGA > + burning during production flow. > + > + The file is read/write. > + > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/max_power > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c-*/i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/config > +Date: October 2021 > +KernelVersion: 5.16 > +Contact: Vadim Pasternak <vadimp@nvidia.com> > +Description: These files provide the maximum powered required for line card > + feeding and line card configuration Id. > + > + The files are read only. > ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH platform-next 09/10] Documentation/ABI: Add new line card attributes for mlxreg-io sysfs interfaces 2021-10-19 8:57 ` Hans de Goede @ 2021-10-19 9:04 ` Vadim Pasternak 0 siblings, 0 replies; 13+ messages in thread From: Vadim Pasternak @ 2021-10-19 9:04 UTC (permalink / raw) To: Hans de Goede; +Cc: platform-driver-x86@vger.kernel.org, Michael Shych > -----Original Message----- > From: Hans de Goede <hdegoede@redhat.com> > Sent: Tuesday, October 19, 2021 11:57 AM > To: Vadim Pasternak <vadimp@nvidia.com> > Cc: platform-driver-x86@vger.kernel.org; Michael Shych > <michaelsh@nvidia.com> > Subject: Re: [PATCH platform-next 09/10] Documentation/ABI: Add new line > card attributes for mlxreg-io sysfs interfaces > > Hi, > > On 10/2/21 11:32, Vadim Pasternak wrote: > > Add documentation for the new attributes for line cards: > > - CPLDs versioning. > > - Write protection control for 'nvram' devices. > > - Line card reset reasons. > > - Enabling burning of FPGA and CPLDs. > > - Enabling burning of FPGA and gearbox SPI flashes, > > - Enabling power of whole line card. > > - Enabling power of QSFP ports equipped on line card. > > - The maximum powered required for line card feeding. > > - Line card configuration Id. > > > > Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> > > Reviewed-by: Michael Shych <michaelsh@nvidia.com> > > Applying this gave the following warnings: > > Applying: Documentation/ABI: Add new line card attributes for mlxreg-io > sysfs interfaces > /home/hans/projects/linux/.git/worktrees/platform-drivers-x86/rebase- > apply/patch:44: space before tab in indent. > If the system is in locked-down mode writing this file will not > /home/hans/projects/linux/.git/worktrees/platform-drivers-x86/rebase- > apply/patch:76: space before tab in indent. > If the system is in locked-down mode writing these files will > /home/hans/projects/linux/.git/worktrees/platform-drivers-x86/rebase- > apply/patch:100: space before tab in indent. > If the system is in locked-down mode writing these files will > warning: 3 lines add whitespace errors. > > I've fixed this up locally. Thank you very much for fixing it. > > FYI the 3 "If the system is in locked-down mode writing this file will not" > lines started with <tab><space><tab> which I've replaced with <tab><tab>. > > Regards, > > Hans > > > > --- > > .../ABI/stable/sysfs-driver-mlxreg-io | 103 ++++++++++++++++++ > > 1 file changed, 103 insertions(+) > > > > diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io > b/Documentation/ABI/stable/sysfs-driver-mlxreg-io > > index 6ef6979c9448..b25e963ec0fa 100644 > > --- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io > > +++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io > > @@ -361,3 +361,106 @@ Description: This file allows to unlock ASIC > after thermal shutdown event. > > Default is 1. > > > > The file is read/write. > > + > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_pn > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_version > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld1_version_min > > +Date: October 2021 > > +KernelVersion: 5.16 > > +Contact: Vadim Pasternak <vadimp@nvidia.com> > > +Description: These files show with which CPLD major and minor versions > > + and part number has been burned CPLD device on line card. > > + > > + The files are read only. > > + > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_pn > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_version > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga1_version_min > > +Date: October 2021 > > +KernelVersion: 5.16 > > +Contact: Vadim Pasternak <vadimp@nvidia.com> > > +Description: These files show with which FPGA major and minor versions > > + and part number has been burned FPGA device on line card. > > + > > + The files are read only. > > + > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/vpd_wp > > +Date: October 2021 > > +KernelVersion: 5.16 > > +Contact: Vadim Pasternak <vadimp@nvidia.com> > > +Description: This file allow to overwrite line card VPD hardware write > > + protection mode. When attribute is set 1 - write protection is > > + disabled, when 0 - enabled. > > + Default is 0. > > + If the system is in locked-down mode writing this file will not > > + be allowed. > > + The purpose if this file is to allow line card VPD burning > > + during production flow. > > + > > + The file is read/write. > > + > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_aux_pwr_or_ref > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_dc_dc_pwr_fail > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_fpga_not_done > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_from_chassis > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/reset_line_card > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg- > io.*/hwmon/hwmon*/reset_pwr_off_from_chassis > > +Date: October 2021 > > +KernelVersion: 5.16 > > +Contact: Vadim Pasternak <vadimp@nvidia.com> > > +Description: These files show the line reset cause, as following: power > > + auxiliary outage or power refresh, DC-to-DC power failure, > FPGA reset > > + failed, line card reset failed, power off from chassis. > > + Value 1 in file means this is reset cause, 0 - otherwise. Only > one of > > + the above causes could be 1 at the same time, representing > only last > > + reset cause. > > + > > + The files are read only. > > + > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/cpld_upgrade_en > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga_upgrade_en > > +Date: October 2021 > > +KernelVersion: 5.16 > > +Contact: Vadim Pasternak <vadimp@nvidia.com> > > +Description: These files allow CPLD and FPGA burning. Value 1 in file > means burning > > + is enabled, 0 - otherwise. > > + If the system is in locked-down mode writing these files will > > + not be allowed. > > + The purpose of these files to allow line card CPLD and FPGA > > + upgrade through the JTAG daisy-chain. > > + > > + The files are read/write. > > + > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/qsfp_pwr_en > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/pwr_en > > +Date: October 2021 > > +KernelVersion: 5.16 > > +Contact: Vadim Pasternak <vadimp@nvidia.com> > > +Description: These files allow to power on/off all QSFP ports and whole > line card. > > + The attributes are set 1 for power on, 0 - for power off. > > + > > + The files are read/write. > > + > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/agb_spi_burn_en > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/fpga_spi_burn_en > > +Date: October 2021 > > +KernelVersion: 5.16 > > +Contact: Vadim Pasternak <vadimp@nvidia.com> > > +Description: These files allow gearboxes and FPGA SPI flash burning. > > + The attributes are set 1 to enable burning, 0 - to disable. > > + If the system is in locked-down mode writing these files will > > + not be allowed. > > + The purpose of these files to allow line card Gearboxes and > FPGA > > + burning during production flow. > > + > > + The file is read/write. > > + > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/max_power > > +What: /sys/devices/platform/mlxplat/i2c_mlxcpld.*/i2c- > */i2c-*/i2c-*/*-0032/mlxreg-io.*/hwmon/hwmon*/config > > +Date: October 2021 > > +KernelVersion: 5.16 > > +Contact: Vadim Pasternak <vadimp@nvidia.com> > > +Description: These files provide the maximum powered required for line > card > > + feeding and line card configuration Id. > > + > > + The files are read only. > > ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-10-19 9:04 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
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2021-10-02 9:32 [PATCH platform-next 00/10] platform: mellanox: Introduce initial chassis management support for modular Ethernet system Vadim Pasternak
2021-10-02 9:32 ` [PATCH platform-next 01/10] platform_data/mlxreg: Add new type to support modular systems Vadim Pasternak
2021-10-02 9:32 ` [PATCH platform-next 02/10] platform/x86: mlx-platform: Add initial support for new modular system Vadim Pasternak
2021-10-02 9:32 ` [PATCH platform-next 03/10] platform/mellanox: mlxreg-hotplug: Extend logic for hotplug devices operations Vadim Pasternak
2021-10-02 9:32 ` [PATCH platform-next 04/10] platform/x86: mlx-platform: Configure notifier callbacks for modular system Vadim Pasternak
2021-10-02 9:32 ` [PATCH platform-next 05/10] platform/mellanox: mlxreg-io: Extend number of hwmon attributes Vadim Pasternak
2021-10-02 9:32 ` [PATCH platform-next 06/10] platform_data/mlxreg: Add new field for secured access Vadim Pasternak
2021-10-02 9:32 ` [PATCH platform-next 07/10] platform/mellanox: mlxreg-lc: Add initial support for Nvidia line card devices Vadim Pasternak
[not found] ` <76a93a22-a3ff-e65f-1334-defb886724dc@redhat.com>
[not found] ` <6d9e4402-a8c2-d043-4129-4da6b250ea53@redhat.com>
2021-10-19 8:57 ` Vadim Pasternak
2021-10-02 9:32 ` [PATCH platform-next 08/10] Documentation/ABI: Add new attributes for mlxreg-io sysfs interfaces Vadim Pasternak
2021-10-02 9:32 ` [PATCH platform-next 09/10] Documentation/ABI: Add new line card " Vadim Pasternak
2021-10-19 8:57 ` Hans de Goede
2021-10-19 9:04 ` Vadim Pasternak
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