[PATCH] platform/x86: ISST: Check HWP support before MSR access

[PATCH] platform/x86: ISST: Check HWP support before MSR access

[lirongqing]

From: Li RongQing <lirongqing@baidu.com>

On some systems, HWP can be explicitly disabled in the BIOS settings
When HWP is disabled by firmware, the HWP CPUID bit is not set, and
attempting to read MSR_PM_ENABLE will result in a General Protection
(GP) fault.

[  426.715441] unchecked MSR access error: RDMSR from 0x770 at rIP: 0xffffffffc33db92e (disable_dynamic_sst_features+0xe/0x50 [isst_tpmi_core])
[  426.715450] Call Trace:
[  426.715453]  <TASK>
[  426.715454]  ? ex_handler_msr+0xf6/0x150
[  426.715461]  ? fixup_exception+0x1ad/0x340
[  426.715462]  ? gp_try_fixup_and_notify+0x1e/0xb0
[  426.715466]  ? exc_general_protection+0xc9/0x390
[  426.715470]  ? terminate_walk+0x64/0x100
[  426.715474]  ? asm_exc_general_protection+0x22/0x30
[  426.715477]  ? disable_dynamic_sst_features+0xe/0x50 [isst_tpmi_core]
[  426.715480]  isst_if_def_ioctl+0xece/0x1050 [isst_tpmi_core]
[  426.715484]  ? ioctl_has_perm.constprop.42+0xe0/0x130
[  426.715489]  isst_if_def_ioctl+0x10d/0x1a0 [isst_if_common]
[  426.715495]  __se_sys_ioctl+0x86/0xc0
[  426.715498]  do_syscall_64+0x8a/0x100
[  426.715500]  entry_SYSCALL_64_after_hwframe+0x78/0xe2
[  426.715503] RIP: 0033:0x7f36eaef54a7

Add a check for X86_FEATURE_HWP before accessing the MSR. If HWP is
not available, return false safely.

Fixes: 12a7d2cb811dd8a ("platform/x86: ISST: Add SST-CP support via TPMI")
Signed-off-by: Li RongQing <lirongqing@baidu.com>
---
 drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
index b8cdaa2..6f46cbb 100644
--- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
+++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
@@ -558,6 +558,9 @@ static bool disable_dynamic_sst_features(void)
 {
 	u64 value;
 
+	if (!static_cpu_has(X86_FEATURE_HWP))
+		return true;
+
 	rdmsrq(MSR_PM_ENABLE, value);
 	return !(value & 0x1);
 }
-- 
2.9.4

Re: [PATCH] platform/x86: ISST: Check HWP support before MSR access

[srinivas pandruvada]

On Sat, 2026-02-28 at 07:24 -0500, lirongqing wrote:
> From: Li RongQing <lirongqing@baidu.com>
> 
> On some systems, HWP can be explicitly disabled in the BIOS settings
> When HWP is disabled by firmware, the HWP CPUID bit is not set, and
> attempting to read MSR_PM_ENABLE will result in a General Protection
> (GP) fault.
> 
> [  426.715441] unchecked MSR access error: RDMSR from 0x770 at rIP:
> 0xffffffffc33db92e (disable_dynamic_sst_features+0xe/0x50
> [isst_tpmi_core])
> [  426.715450] Call Trace:
> [  426.715453]  <TASK>
> [  426.715454]  ? ex_handler_msr+0xf6/0x150
> [  426.715461]  ? fixup_exception+0x1ad/0x340
> [  426.715462]  ? gp_try_fixup_and_notify+0x1e/0xb0
> [  426.715466]  ? exc_general_protection+0xc9/0x390
> [  426.715470]  ? terminate_walk+0x64/0x100
> [  426.715474]  ? asm_exc_general_protection+0x22/0x30
> [  426.715477]  ? disable_dynamic_sst_features+0xe/0x50
> [isst_tpmi_core]
> [  426.715480]  isst_if_def_ioctl+0xece/0x1050 [isst_tpmi_core]
> [  426.715484]  ? ioctl_has_perm.constprop.42+0xe0/0x130
> [  426.715489]  isst_if_def_ioctl+0x10d/0x1a0 [isst_if_common]
> [  426.715495]  __se_sys_ioctl+0x86/0xc0
> [  426.715498]  do_syscall_64+0x8a/0x100
> [  426.715500]  entry_SYSCALL_64_after_hwframe+0x78/0xe2
> [  426.715503] RIP: 0033:0x7f36eaef54a7
> 
> Add a check for X86_FEATURE_HWP before accessing the MSR. If HWP is
> not available, return false safely.
> 
> Fixes: 12a7d2cb811dd8a ("platform/x86: ISST: Add SST-CP support via
> TPMI")
> Signed-off-by: Li RongQing <lirongqing@baidu.com>
> ---
>  drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git
> a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> index b8cdaa2..6f46cbb 100644
> --- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> +++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> @@ -558,6 +558,9 @@ static bool disable_dynamic_sst_features(void)
>  {
>  	u64 value;
>  
> +	if (!static_cpu_has(X86_FEATURE_HWP))
> +		return true;
> +
>  	rdmsrq(MSR_PM_ENABLE, value);
>  	return !(value & 0x1);
>  }

Re: [PATCH] platform/x86: ISST: Check HWP support before MSR access

[srinivas pandruvada]

On Sat, 2026-02-28 at 07:24 -0500, lirongqing wrote:
> From: Li RongQing <lirongqing@baidu.com>
> 
> On some systems, HWP can be explicitly disabled in the BIOS settings
> When HWP is disabled by firmware, the HWP CPUID bit is not set, and
> attempting to read MSR_PM_ENABLE will result in a General Protection
> (GP) fault.
> 
> [  426.715441] unchecked MSR access error: RDMSR from 0x770 at rIP:
> 0xffffffffc33db92e (disable_dynamic_sst_features+0xe/0x50
> [isst_tpmi_core])
> [  426.715450] Call Trace:
> [  426.715453]  <TASK>
> [  426.715454]  ? ex_handler_msr+0xf6/0x150
> [  426.715461]  ? fixup_exception+0x1ad/0x340
> [  426.715462]  ? gp_try_fixup_and_notify+0x1e/0xb0
> [  426.715466]  ? exc_general_protection+0xc9/0x390
> [  426.715470]  ? terminate_walk+0x64/0x100
> [  426.715474]  ? asm_exc_general_protection+0x22/0x30
> [  426.715477]  ? disable_dynamic_sst_features+0xe/0x50
> [isst_tpmi_core]
> [  426.715480]  isst_if_def_ioctl+0xece/0x1050 [isst_tpmi_core]
> [  426.715484]  ? ioctl_has_perm.constprop.42+0xe0/0x130
> [  426.715489]  isst_if_def_ioctl+0x10d/0x1a0 [isst_if_common]
> [  426.715495]  __se_sys_ioctl+0x86/0xc0
> [  426.715498]  do_syscall_64+0x8a/0x100
> [  426.715500]  entry_SYSCALL_64_after_hwframe+0x78/0xe2
> [  426.715503] RIP: 0033:0x7f36eaef54a7
> 
> Add a check for X86_FEATURE_HWP before accessing the MSR. If HWP is
> not available, return false safely.
> 
> Fixes: 12a7d2cb811dd8a ("platform/x86: ISST: Add SST-CP support via
> TPMI")
> Signed-off-by: Li RongQing <lirongqing@baidu.com>

Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>


> ---
>  drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git
> a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> index b8cdaa2..6f46cbb 100644
> --- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> +++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> @@ -558,6 +558,9 @@ static bool disable_dynamic_sst_features(void)
>  {
>  	u64 value;
>  
> +	if (!static_cpu_has(X86_FEATURE_HWP))
> +		return true;
> +
>  	rdmsrq(MSR_PM_ENABLE, value);
>  	return !(value & 0x1);
>  }

答复: [PATCH] platform/x86: ISST: Check HWP support before MSR access

[Li,Rongqing(ACG CCN)]

> On some systems, HWP can be explicitly disabled in the BIOS settings When
> HWP is disabled by firmware, the HWP CPUID bit is not set, and attempting to
> read MSR_PM_ENABLE will result in a General Protection
> (GP) fault.
> 
> [  426.715441] unchecked MSR access error: RDMSR from 0x770 at rIP:
> 0xffffffffc33db92e (disable_dynamic_sst_features+0xe/0x50 [isst_tpmi_core])
> [  426.715450] Call Trace:
> [  426.715453]  <TASK>
> [  426.715454]  ? ex_handler_msr+0xf6/0x150 [  426.715461]  ?
> fixup_exception+0x1ad/0x340 [  426.715462]  ?
> gp_try_fixup_and_notify+0x1e/0xb0 [  426.715466]  ?
> exc_general_protection+0xc9/0x390 [  426.715470]  ?
> terminate_walk+0x64/0x100 [  426.715474]  ?
> asm_exc_general_protection+0x22/0x30
> [  426.715477]  ? disable_dynamic_sst_features+0xe/0x50 [isst_tpmi_core]
> [  426.715480]  isst_if_def_ioctl+0xece/0x1050 [isst_tpmi_core]
> [  426.715484]  ? ioctl_has_perm.constprop.42+0xe0/0x130
> [  426.715489]  isst_if_def_ioctl+0x10d/0x1a0 [isst_if_common]
> [  426.715495]  __se_sys_ioctl+0x86/0xc0 [  426.715498]
> do_syscall_64+0x8a/0x100 [  426.715500]
> entry_SYSCALL_64_after_hwframe+0x78/0xe2
> [  426.715503] RIP: 0033:0x7f36eaef54a7
> 
> Add a check for X86_FEATURE_HWP before accessing the MSR. If HWP is not
> available, return false safely.

It returns true, not false. Could you revise this commit message in the merge?

[Li,Rongqing] 


> 
> Fixes: 12a7d2cb811dd8a ("platform/x86: ISST: Add SST-CP support via TPMI")
> Signed-off-by: Li RongQing <lirongqing@baidu.com>
> ---
>  drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> index b8cdaa2..6f46cbb 100644
> --- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> +++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> @@ -558,6 +558,9 @@ static bool disable_dynamic_sst_features(void)
>  {
>  	u64 value;
> 
> +	if (!static_cpu_has(X86_FEATURE_HWP))
> +		return true;
> +
>  	rdmsrq(MSR_PM_ENABLE, value);
>  	return !(value & 0x1);
>  }
> --
> 2.9.4

Re: 答复: [PATCH] platform/x86: ISST: Check HWP support before MSR access

[srinivas pandruvada]

On Mon, 2026-03-02 at 02:20 +0000, Li,Rongqing(ACG CCN) wrote:
> > On some systems, HWP can be explicitly disabled in the BIOS
> > settings When
> > HWP is disabled by firmware, the HWP CPUID bit is not set, and
> > attempting to
> > read MSR_PM_ENABLE will result in a General Protection
> > (GP) fault.
> > 
> > [  426.715441] unchecked MSR access error: RDMSR from 0x770 at rIP:
> > 0xffffffffc33db92e (disable_dynamic_sst_features+0xe/0x50
> > [isst_tpmi_core])
> > [  426.715450] Call Trace:
> > [  426.715453]  <TASK>
> > [  426.715454]  ? ex_handler_msr+0xf6/0x150 [  426.715461]  ?
> > fixup_exception+0x1ad/0x340 [  426.715462]  ?
> > gp_try_fixup_and_notify+0x1e/0xb0 [  426.715466]  ?
> > exc_general_protection+0xc9/0x390 [  426.715470]  ?
> > terminate_walk+0x64/0x100 [  426.715474]  ?
> > asm_exc_general_protection+0x22/0x30
> > [  426.715477]  ? disable_dynamic_sst_features+0xe/0x50
> > [isst_tpmi_core]
> > [  426.715480]  isst_if_def_ioctl+0xece/0x1050 [isst_tpmi_core]
> > [  426.715484]  ? ioctl_has_perm.constprop.42+0xe0/0x130
> > [  426.715489]  isst_if_def_ioctl+0x10d/0x1a0 [isst_if_common]
> > [  426.715495]  __se_sys_ioctl+0x86/0xc0 [  426.715498]
> > do_syscall_64+0x8a/0x100 [  426.715500]
> > entry_SYSCALL_64_after_hwframe+0x78/0xe2
> > [  426.715503] RIP: 0033:0x7f36eaef54a7
> > 
> > Add a check for X86_FEATURE_HWP before accessing the MSR. If HWP is
> > not
> > available, return false safely.
> 
> It returns true, not false. Could you revise this commit message in
> the merge?

You should submit V2.

Thanks,
Srinivas

> 
> [Li,Rongqing] 
> 
> 
> > 
> > Fixes: 12a7d2cb811dd8a ("platform/x86: ISST: Add SST-CP support via
> > TPMI")
> > Signed-off-by: Li RongQing <lirongqing@baidu.com>
> > ---
> >  drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c | 3
> > +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git
> > a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> > b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> > index b8cdaa2..6f46cbb 100644
> > --- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> > +++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> > @@ -558,6 +558,9 @@ static bool disable_dynamic_sst_features(void)
> >  {
> >  	u64 value;
> > 
> > +	if (!static_cpu_has(X86_FEATURE_HWP))
> > +		return true;
> > +
> >  	rdmsrq(MSR_PM_ENABLE, value);
> >  	return !(value & 0x1);
> >  }
> > --
> > 2.9.4