* [PATCH v2 1/2] platform/x86/amd/pmf: Relocate CPU ID macros to the PMF header @ 2024-08-13 9:00 Shyam Sundar S K 2024-08-13 9:00 ` [PATCH v2 2/2] platform/x86/amd/pmf: Update SMU metrics table for 1AH family series Shyam Sundar S K 0 siblings, 1 reply; 4+ messages in thread From: Shyam Sundar S K @ 2024-08-13 9:00 UTC (permalink / raw) To: hdegoede, ilpo.jarvinen Cc: platform-driver-x86, Patil.Reddy, Shyam Sundar S K The CPU ID macros are needed by the Smart PC builder. Therefore, transfer the CPU ID macros from core.c to the common PMF header file. Co-developed-by: Patil Rajesh Reddy <Patil.Reddy@amd.com> Signed-off-by: Patil Rajesh Reddy <Patil.Reddy@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> --- v2: - No change drivers/platform/x86/amd/pmf/core.c | 6 ------ drivers/platform/x86/amd/pmf/pmf.h | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index 8f1f719befa3..88314b0277a3 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -37,12 +37,6 @@ #define AMD_PMF_RESULT_CMD_UNKNOWN 0xFE #define AMD_PMF_RESULT_FAILED 0xFF -/* List of supported CPU ids */ -#define AMD_CPU_ID_RMB 0x14b5 -#define AMD_CPU_ID_PS 0x14e8 -#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 -#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 - #define PMF_MSG_DELAY_MIN_US 50 #define RESPONSE_REGISTER_LOOP_MAX 20000 diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 9bf4326d06c3..9fc26f672f12 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -19,6 +19,12 @@ #define POLICY_SIGN_COOKIE 0x31535024 #define POLICY_COOKIE_OFFSET 0x10 +/* List of supported CPU ids */ +#define AMD_CPU_ID_RMB 0x14b5 +#define AMD_CPU_ID_PS 0x14e8 +#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 +#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 + struct cookie_header { u32 sign; u32 length; -- 2.25.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 2/2] platform/x86/amd/pmf: Update SMU metrics table for 1AH family series 2024-08-13 9:00 [PATCH v2 1/2] platform/x86/amd/pmf: Relocate CPU ID macros to the PMF header Shyam Sundar S K @ 2024-08-13 9:00 ` Shyam Sundar S K 2024-08-13 9:08 ` Ilpo Järvinen 0 siblings, 1 reply; 4+ messages in thread From: Shyam Sundar S K @ 2024-08-13 9:00 UTC (permalink / raw) To: hdegoede, ilpo.jarvinen Cc: platform-driver-x86, Patil.Reddy, Shyam Sundar S K The SMU metrics table has been revised for the 1AH family series. Introduce a new metrics table structure to retrieve comprehensive metrics information from the PMFW. This information will be utilized by the PMF driver to adjust system thermals. Co-developed-by: Patil Rajesh Reddy <Patil.Reddy@amd.com> Signed-off-by: Patil Rajesh Reddy <Patil.Reddy@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> --- v2: - Align comments - add helper for max and avg calculation of C0 residency drivers/platform/x86/amd/pmf/core.c | 14 ++++++- drivers/platform/x86/amd/pmf/pmf.h | 49 +++++++++++++++++++++++ drivers/platform/x86/amd/pmf/spc.c | 61 ++++++++++++++++++++++------- 3 files changed, 108 insertions(+), 16 deletions(-) diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index 88314b0277a3..0ba9045224d9 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -255,7 +255,19 @@ int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer) /* Get Metrics Table Address */ if (alloc_buffer) { - dev->buf = kzalloc(sizeof(dev->m_table), GFP_KERNEL); + switch (dev->cpu_id) { + case AMD_CPU_ID_PS: + case AMD_CPU_ID_RMB: + dev->mtable_size = sizeof(dev->m_table); + break; + case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: + dev->mtable_size = sizeof(dev->m_table_v2); + break; + default: + dev_err(dev->dev, "Invalid cpu id: 0x%x", dev->cpu_id); + } + + dev->buf = kzalloc(dev->mtable_size, GFP_KERNEL); if (!dev->buf) return -ENOMEM; } diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 9fc26f672f12..8ce8816da9c1 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -198,6 +198,53 @@ struct apmf_fan_idx { u32 fan_ctl_idx; } __packed; +struct smu_pmf_metrics_v2 { + u16 core_frequency[16]; /* MHz */ + u16 core_power[16]; /* mW */ + u16 core_temp[16]; /* centi-C */ + u16 gfx_temp; /* centi-C */ + u16 soc_temp; /* centi-C */ + u16 stapm_opn_limit; /* mW */ + u16 stapm_cur_limit; /* mW */ + u16 infra_cpu_maxfreq; /* MHz */ + u16 infra_gfx_maxfreq; /* MHz */ + u16 skin_temp; /* centi-C */ + u16 gfxclk_freq; /* MHz */ + u16 fclk_freq; /* MHz */ + u16 gfx_activity; /* GFX busy % [0-100] */ + u16 socclk_freq; /* MHz */ + u16 vclk_freq; /* MHz */ + u16 vcn_activity; /* VCN busy % [0-100] */ + u16 vpeclk_freq; /* MHz */ + u16 ipuclk_freq; /* MHz */ + u16 ipu_busy[8]; /* NPU busy % [0-100] */ + u16 dram_reads; /* MB/sec */ + u16 dram_writes; /* MB/sec */ + u16 core_c0residency[16]; /* C0 residency % [0-100] */ + u16 ipu_power; /* mW */ + u32 apu_power; /* mW */ + u32 gfx_power; /* mW */ + u32 dgpu_power; /* mW */ + u32 socket_power; /* mW */ + u32 all_core_power; /* mW */ + u32 filter_alpha_value; /* time constant [us] */ + u32 metrics_counter; + u16 memclk_freq; /* MHz */ + u16 mpipuclk_freq; /* MHz */ + u16 ipu_reads; /* MB/sec */ + u16 ipu_writes; /* MB/sec */ + u32 throttle_residency_prochot; + u32 throttle_residency_spl; + u32 throttle_residency_fppt; + u32 throttle_residency_sppt; + u32 throttle_residency_thm_core; + u32 throttle_residency_thm_gfx; + u32 throttle_residency_thm_soc; + u16 psys; + u16 spare1; + u32 spare[6]; +} __packed; + struct smu_pmf_metrics { u16 gfxclk_freq; /* in MHz */ u16 socclk_freq; /* in MHz */ @@ -295,6 +342,7 @@ struct amd_pmf_dev { int hb_interval; /* SBIOS heartbeat interval */ struct delayed_work heart_beat; struct smu_pmf_metrics m_table; + struct smu_pmf_metrics_v2 m_table_v2; struct delayed_work work_buffer; ktime_t start_time; int socket_power_history[AVG_SAMPLE_SIZE]; @@ -319,6 +367,7 @@ struct amd_pmf_dev { bool smart_pc_enabled; u16 pmf_if_version; struct input_dev *pmf_idev; + size_t mtable_size; }; struct apmf_sps_prop_granular_v2 { diff --git a/drivers/platform/x86/amd/pmf/spc.c b/drivers/platform/x86/amd/pmf/spc.c index 3c153fb1425e..910ba7925f13 100644 --- a/drivers/platform/x86/amd/pmf/spc.c +++ b/drivers/platform/x86/amd/pmf/spc.c @@ -53,30 +53,61 @@ void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table * void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) {} #endif -static void amd_pmf_get_smu_info(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) +static void amd_pmf_get_c0_residency(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) { u16 max, avg = 0; int i; - memset(dev->buf, 0, sizeof(dev->m_table)); - amd_pmf_send_cmd(dev, SET_TRANSFER_TABLE, 0, 7, NULL); - memcpy(&dev->m_table, dev->buf, sizeof(dev->m_table)); - - in->ev_info.socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; - in->ev_info.skin_temperature = dev->m_table.skin_temp; - /* Get the avg and max C0 residency of all the cores */ - max = dev->m_table.avg_core_c0residency[0]; - for (i = 0; i < ARRAY_SIZE(dev->m_table.avg_core_c0residency); i++) { - avg += dev->m_table.avg_core_c0residency[i]; - if (dev->m_table.avg_core_c0residency[i] > max) - max = dev->m_table.avg_core_c0residency[i]; + switch (dev->cpu_id) { + case AMD_CPU_ID_PS: + max = dev->m_table.avg_core_c0residency[0]; + for (i = 0; i < ARRAY_SIZE(dev->m_table.avg_core_c0residency); i++) { + avg += dev->m_table.avg_core_c0residency[i]; + if (dev->m_table.avg_core_c0residency[i] > max) + max = dev->m_table.avg_core_c0residency[i]; + } + avg = DIV_ROUND_CLOSEST(avg, ARRAY_SIZE(dev->m_table.avg_core_c0residency)); + break; + case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: + max = dev->m_table_v2.core_c0residency[0]; + for (i = 0; i < ARRAY_SIZE(dev->m_table_v2.core_c0residency); i++) { + avg += dev->m_table_v2.core_c0residency[i]; + if (dev->m_table_v2.core_c0residency[i] > max) + max = dev->m_table_v2.core_c0residency[i]; + } + avg = DIV_ROUND_CLOSEST(avg, ARRAY_SIZE(dev->m_table_v2.core_c0residency)); + break; } - avg = DIV_ROUND_CLOSEST(avg, ARRAY_SIZE(dev->m_table.avg_core_c0residency)); in->ev_info.avg_c0residency = avg; in->ev_info.max_c0residency = max; - in->ev_info.gfx_busy = dev->m_table.avg_gfx_activity; +} + +static void amd_pmf_get_smu_info(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) +{ + /* Get the updated metrics table data */ + memset(dev->buf, 0, dev->mtable_size); + amd_pmf_send_cmd(dev, SET_TRANSFER_TABLE, 0, 7, NULL); + + switch (dev->cpu_id) { + case AMD_CPU_ID_PS: + memcpy(&dev->m_table, dev->buf, dev->mtable_size); + in->ev_info.socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; + in->ev_info.skin_temperature = dev->m_table.skin_temp; + in->ev_info.gfx_busy = dev->m_table.avg_gfx_activity; + amd_pmf_get_c0_residency(dev, in); + break; + case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: + memcpy(&dev->m_table_v2, dev->buf, dev->mtable_size); + in->ev_info.socket_power = dev->m_table_v2.apu_power + dev->m_table_v2.dgpu_power; + in->ev_info.skin_temperature = dev->m_table_v2.skin_temp; + in->ev_info.gfx_busy = dev->m_table_v2.gfx_activity; + amd_pmf_get_c0_residency(dev, in); + break; + default: + dev_err(dev->dev, "Unsupported cpuid: 0x%x", dev->cpu_id); + } } static const char * const pmf_battery_supply_name[] = { -- 2.25.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/2] platform/x86/amd/pmf: Update SMU metrics table for 1AH family series 2024-08-13 9:00 ` [PATCH v2 2/2] platform/x86/amd/pmf: Update SMU metrics table for 1AH family series Shyam Sundar S K @ 2024-08-13 9:08 ` Ilpo Järvinen 2024-08-13 13:33 ` Shyam Sundar S K 0 siblings, 1 reply; 4+ messages in thread From: Ilpo Järvinen @ 2024-08-13 9:08 UTC (permalink / raw) To: Shyam Sundar S K; +Cc: Hans de Goede, platform-driver-x86, Patil.Reddy On Tue, 13 Aug 2024, Shyam Sundar S K wrote: > The SMU metrics table has been revised for the 1AH family series. > Introduce a new metrics table structure to retrieve comprehensive metrics > information from the PMFW. This information will be utilized by the PMF > driver to adjust system thermals. > > Co-developed-by: Patil Rajesh Reddy <Patil.Reddy@amd.com> > Signed-off-by: Patil Rajesh Reddy <Patil.Reddy@amd.com> > Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> > --- > v2: > - Align comments > - add helper for max and avg calculation of C0 residency > > drivers/platform/x86/amd/pmf/core.c | 14 ++++++- > drivers/platform/x86/amd/pmf/pmf.h | 49 +++++++++++++++++++++++ > drivers/platform/x86/amd/pmf/spc.c | 61 ++++++++++++++++++++++------- > 3 files changed, 108 insertions(+), 16 deletions(-) > > diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c > index 88314b0277a3..0ba9045224d9 100644 > --- a/drivers/platform/x86/amd/pmf/core.c > +++ b/drivers/platform/x86/amd/pmf/core.c > @@ -255,7 +255,19 @@ int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer) > > /* Get Metrics Table Address */ > if (alloc_buffer) { > - dev->buf = kzalloc(sizeof(dev->m_table), GFP_KERNEL); > + switch (dev->cpu_id) { > + case AMD_CPU_ID_PS: > + case AMD_CPU_ID_RMB: > + dev->mtable_size = sizeof(dev->m_table); > + break; > + case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: > + dev->mtable_size = sizeof(dev->m_table_v2); > + break; > + default: > + dev_err(dev->dev, "Invalid cpu id: 0x%x", dev->cpu_id); > + } > + > + dev->buf = kzalloc(dev->mtable_size, GFP_KERNEL); > if (!dev->buf) > return -ENOMEM; > } > diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h > index 9fc26f672f12..8ce8816da9c1 100644 > --- a/drivers/platform/x86/amd/pmf/pmf.h > +++ b/drivers/platform/x86/amd/pmf/pmf.h > @@ -198,6 +198,53 @@ struct apmf_fan_idx { > u32 fan_ctl_idx; > } __packed; > > +struct smu_pmf_metrics_v2 { > + u16 core_frequency[16]; /* MHz */ > + u16 core_power[16]; /* mW */ > + u16 core_temp[16]; /* centi-C */ > + u16 gfx_temp; /* centi-C */ > + u16 soc_temp; /* centi-C */ > + u16 stapm_opn_limit; /* mW */ > + u16 stapm_cur_limit; /* mW */ > + u16 infra_cpu_maxfreq; /* MHz */ > + u16 infra_gfx_maxfreq; /* MHz */ > + u16 skin_temp; /* centi-C */ > + u16 gfxclk_freq; /* MHz */ > + u16 fclk_freq; /* MHz */ > + u16 gfx_activity; /* GFX busy % [0-100] */ > + u16 socclk_freq; /* MHz */ > + u16 vclk_freq; /* MHz */ > + u16 vcn_activity; /* VCN busy % [0-100] */ > + u16 vpeclk_freq; /* MHz */ > + u16 ipuclk_freq; /* MHz */ > + u16 ipu_busy[8]; /* NPU busy % [0-100] */ > + u16 dram_reads; /* MB/sec */ > + u16 dram_writes; /* MB/sec */ > + u16 core_c0residency[16]; /* C0 residency % [0-100] */ > + u16 ipu_power; /* mW */ > + u32 apu_power; /* mW */ > + u32 gfx_power; /* mW */ > + u32 dgpu_power; /* mW */ > + u32 socket_power; /* mW */ > + u32 all_core_power; /* mW */ > + u32 filter_alpha_value; /* time constant [us] */ > + u32 metrics_counter; > + u16 memclk_freq; /* MHz */ > + u16 mpipuclk_freq; /* MHz */ > + u16 ipu_reads; /* MB/sec */ > + u16 ipu_writes; /* MB/sec */ > + u32 throttle_residency_prochot; > + u32 throttle_residency_spl; > + u32 throttle_residency_fppt; > + u32 throttle_residency_sppt; > + u32 throttle_residency_thm_core; > + u32 throttle_residency_thm_gfx; > + u32 throttle_residency_thm_soc; > + u16 psys; > + u16 spare1; > + u32 spare[6]; > +} __packed; > + > struct smu_pmf_metrics { > u16 gfxclk_freq; /* in MHz */ > u16 socclk_freq; /* in MHz */ > @@ -295,6 +342,7 @@ struct amd_pmf_dev { > int hb_interval; /* SBIOS heartbeat interval */ > struct delayed_work heart_beat; > struct smu_pmf_metrics m_table; > + struct smu_pmf_metrics_v2 m_table_v2; > struct delayed_work work_buffer; > ktime_t start_time; > int socket_power_history[AVG_SAMPLE_SIZE]; > @@ -319,6 +367,7 @@ struct amd_pmf_dev { > bool smart_pc_enabled; > u16 pmf_if_version; > struct input_dev *pmf_idev; > + size_t mtable_size; > }; > > struct apmf_sps_prop_granular_v2 { > diff --git a/drivers/platform/x86/amd/pmf/spc.c b/drivers/platform/x86/amd/pmf/spc.c > index 3c153fb1425e..910ba7925f13 100644 > --- a/drivers/platform/x86/amd/pmf/spc.c > +++ b/drivers/platform/x86/amd/pmf/spc.c > @@ -53,30 +53,61 @@ void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table * > void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) {} > #endif > > -static void amd_pmf_get_smu_info(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) > +static void amd_pmf_get_c0_residency(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) > { > u16 max, avg = 0; > int i; > > - memset(dev->buf, 0, sizeof(dev->m_table)); > - amd_pmf_send_cmd(dev, SET_TRANSFER_TABLE, 0, 7, NULL); > - memcpy(&dev->m_table, dev->buf, sizeof(dev->m_table)); > - > - in->ev_info.socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; > - in->ev_info.skin_temperature = dev->m_table.skin_temp; > - > /* Get the avg and max C0 residency of all the cores */ > - max = dev->m_table.avg_core_c0residency[0]; > - for (i = 0; i < ARRAY_SIZE(dev->m_table.avg_core_c0residency); i++) { > - avg += dev->m_table.avg_core_c0residency[i]; > - if (dev->m_table.avg_core_c0residency[i] > max) > - max = dev->m_table.avg_core_c0residency[i]; > + switch (dev->cpu_id) { > + case AMD_CPU_ID_PS: > + max = dev->m_table.avg_core_c0residency[0]; > + for (i = 0; i < ARRAY_SIZE(dev->m_table.avg_core_c0residency); i++) { > + avg += dev->m_table.avg_core_c0residency[i]; > + if (dev->m_table.avg_core_c0residency[i] > max) > + max = dev->m_table.avg_core_c0residency[i]; > + } > + avg = DIV_ROUND_CLOSEST(avg, ARRAY_SIZE(dev->m_table.avg_core_c0residency)); > + break; > + case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: > + max = dev->m_table_v2.core_c0residency[0]; > + for (i = 0; i < ARRAY_SIZE(dev->m_table_v2.core_c0residency); i++) { > + avg += dev->m_table_v2.core_c0residency[i]; > + if (dev->m_table_v2.core_c0residency[i] > max) > + max = dev->m_table_v2.core_c0residency[i]; > + } > + avg = DIV_ROUND_CLOSEST(avg, ARRAY_SIZE(dev->m_table_v2.core_c0residency)); This is not what I meant. Add a helper which takes the c0residency array as a pointer and the number of elements (+ the pointers to result variables, obviously). The helper should not care which struct the values come from. -- i. > + break; > } > > - avg = DIV_ROUND_CLOSEST(avg, ARRAY_SIZE(dev->m_table.avg_core_c0residency)); > in->ev_info.avg_c0residency = avg; > in->ev_info.max_c0residency = max; > - in->ev_info.gfx_busy = dev->m_table.avg_gfx_activity; > +} > + > +static void amd_pmf_get_smu_info(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) > +{ > + /* Get the updated metrics table data */ > + memset(dev->buf, 0, dev->mtable_size); > + amd_pmf_send_cmd(dev, SET_TRANSFER_TABLE, 0, 7, NULL); > + > + switch (dev->cpu_id) { > + case AMD_CPU_ID_PS: > + memcpy(&dev->m_table, dev->buf, dev->mtable_size); > + in->ev_info.socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; > + in->ev_info.skin_temperature = dev->m_table.skin_temp; > + in->ev_info.gfx_busy = dev->m_table.avg_gfx_activity; > + amd_pmf_get_c0_residency(dev, in); > + break; > + case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: > + memcpy(&dev->m_table_v2, dev->buf, dev->mtable_size); > + in->ev_info.socket_power = dev->m_table_v2.apu_power + dev->m_table_v2.dgpu_power; > + in->ev_info.skin_temperature = dev->m_table_v2.skin_temp; > + in->ev_info.gfx_busy = dev->m_table_v2.gfx_activity; > + amd_pmf_get_c0_residency(dev, in); > + break; > + default: > + dev_err(dev->dev, "Unsupported cpuid: 0x%x", dev->cpu_id); > + } > } > > static const char * const pmf_battery_supply_name[] = { > ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/2] platform/x86/amd/pmf: Update SMU metrics table for 1AH family series 2024-08-13 9:08 ` Ilpo Järvinen @ 2024-08-13 13:33 ` Shyam Sundar S K 0 siblings, 0 replies; 4+ messages in thread From: Shyam Sundar S K @ 2024-08-13 13:33 UTC (permalink / raw) To: Ilpo Järvinen; +Cc: Hans de Goede, platform-driver-x86, Patil.Reddy Hi Ilpo, On 8/13/2024 14:38, Ilpo Järvinen wrote: > On Tue, 13 Aug 2024, Shyam Sundar S K wrote: > >> The SMU metrics table has been revised for the 1AH family series. >> Introduce a new metrics table structure to retrieve comprehensive metrics >> information from the PMFW. This information will be utilized by the PMF >> driver to adjust system thermals. >> >> Co-developed-by: Patil Rajesh Reddy <Patil.Reddy@amd.com> >> Signed-off-by: Patil Rajesh Reddy <Patil.Reddy@amd.com> >> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> >> --- >> v2: >> - Align comments >> - add helper for max and avg calculation of C0 residency >> >> drivers/platform/x86/amd/pmf/core.c | 14 ++++++- >> drivers/platform/x86/amd/pmf/pmf.h | 49 +++++++++++++++++++++++ >> drivers/platform/x86/amd/pmf/spc.c | 61 ++++++++++++++++++++++------- >> 3 files changed, 108 insertions(+), 16 deletions(-) >> >> diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c >> index 88314b0277a3..0ba9045224d9 100644 >> --- a/drivers/platform/x86/amd/pmf/core.c >> +++ b/drivers/platform/x86/amd/pmf/core.c >> @@ -255,7 +255,19 @@ int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer) >> >> /* Get Metrics Table Address */ >> if (alloc_buffer) { >> - dev->buf = kzalloc(sizeof(dev->m_table), GFP_KERNEL); >> + switch (dev->cpu_id) { >> + case AMD_CPU_ID_PS: >> + case AMD_CPU_ID_RMB: >> + dev->mtable_size = sizeof(dev->m_table); >> + break; >> + case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: >> + dev->mtable_size = sizeof(dev->m_table_v2); >> + break; >> + default: >> + dev_err(dev->dev, "Invalid cpu id: 0x%x", dev->cpu_id); >> + } >> + >> + dev->buf = kzalloc(dev->mtable_size, GFP_KERNEL); >> if (!dev->buf) >> return -ENOMEM; >> } >> diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h >> index 9fc26f672f12..8ce8816da9c1 100644 >> --- a/drivers/platform/x86/amd/pmf/pmf.h >> +++ b/drivers/platform/x86/amd/pmf/pmf.h >> @@ -198,6 +198,53 @@ struct apmf_fan_idx { >> u32 fan_ctl_idx; >> } __packed; >> >> +struct smu_pmf_metrics_v2 { >> + u16 core_frequency[16]; /* MHz */ >> + u16 core_power[16]; /* mW */ >> + u16 core_temp[16]; /* centi-C */ >> + u16 gfx_temp; /* centi-C */ >> + u16 soc_temp; /* centi-C */ >> + u16 stapm_opn_limit; /* mW */ >> + u16 stapm_cur_limit; /* mW */ >> + u16 infra_cpu_maxfreq; /* MHz */ >> + u16 infra_gfx_maxfreq; /* MHz */ >> + u16 skin_temp; /* centi-C */ >> + u16 gfxclk_freq; /* MHz */ >> + u16 fclk_freq; /* MHz */ >> + u16 gfx_activity; /* GFX busy % [0-100] */ >> + u16 socclk_freq; /* MHz */ >> + u16 vclk_freq; /* MHz */ >> + u16 vcn_activity; /* VCN busy % [0-100] */ >> + u16 vpeclk_freq; /* MHz */ >> + u16 ipuclk_freq; /* MHz */ >> + u16 ipu_busy[8]; /* NPU busy % [0-100] */ >> + u16 dram_reads; /* MB/sec */ >> + u16 dram_writes; /* MB/sec */ >> + u16 core_c0residency[16]; /* C0 residency % [0-100] */ >> + u16 ipu_power; /* mW */ >> + u32 apu_power; /* mW */ >> + u32 gfx_power; /* mW */ >> + u32 dgpu_power; /* mW */ >> + u32 socket_power; /* mW */ >> + u32 all_core_power; /* mW */ >> + u32 filter_alpha_value; /* time constant [us] */ >> + u32 metrics_counter; >> + u16 memclk_freq; /* MHz */ >> + u16 mpipuclk_freq; /* MHz */ >> + u16 ipu_reads; /* MB/sec */ >> + u16 ipu_writes; /* MB/sec */ >> + u32 throttle_residency_prochot; >> + u32 throttle_residency_spl; >> + u32 throttle_residency_fppt; >> + u32 throttle_residency_sppt; >> + u32 throttle_residency_thm_core; >> + u32 throttle_residency_thm_gfx; >> + u32 throttle_residency_thm_soc; >> + u16 psys; >> + u16 spare1; >> + u32 spare[6]; >> +} __packed; >> + >> struct smu_pmf_metrics { >> u16 gfxclk_freq; /* in MHz */ >> u16 socclk_freq; /* in MHz */ >> @@ -295,6 +342,7 @@ struct amd_pmf_dev { >> int hb_interval; /* SBIOS heartbeat interval */ >> struct delayed_work heart_beat; >> struct smu_pmf_metrics m_table; >> + struct smu_pmf_metrics_v2 m_table_v2; >> struct delayed_work work_buffer; >> ktime_t start_time; >> int socket_power_history[AVG_SAMPLE_SIZE]; >> @@ -319,6 +367,7 @@ struct amd_pmf_dev { >> bool smart_pc_enabled; >> u16 pmf_if_version; >> struct input_dev *pmf_idev; >> + size_t mtable_size; >> }; >> >> struct apmf_sps_prop_granular_v2 { >> diff --git a/drivers/platform/x86/amd/pmf/spc.c b/drivers/platform/x86/amd/pmf/spc.c >> index 3c153fb1425e..910ba7925f13 100644 >> --- a/drivers/platform/x86/amd/pmf/spc.c >> +++ b/drivers/platform/x86/amd/pmf/spc.c >> @@ -53,30 +53,61 @@ void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table * >> void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) {} >> #endif >> >> -static void amd_pmf_get_smu_info(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) >> +static void amd_pmf_get_c0_residency(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) >> { >> u16 max, avg = 0; >> int i; >> >> - memset(dev->buf, 0, sizeof(dev->m_table)); >> - amd_pmf_send_cmd(dev, SET_TRANSFER_TABLE, 0, 7, NULL); >> - memcpy(&dev->m_table, dev->buf, sizeof(dev->m_table)); >> - >> - in->ev_info.socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; >> - in->ev_info.skin_temperature = dev->m_table.skin_temp; >> - >> /* Get the avg and max C0 residency of all the cores */ >> - max = dev->m_table.avg_core_c0residency[0]; >> - for (i = 0; i < ARRAY_SIZE(dev->m_table.avg_core_c0residency); i++) { >> - avg += dev->m_table.avg_core_c0residency[i]; >> - if (dev->m_table.avg_core_c0residency[i] > max) >> - max = dev->m_table.avg_core_c0residency[i]; >> + switch (dev->cpu_id) { >> + case AMD_CPU_ID_PS: >> + max = dev->m_table.avg_core_c0residency[0]; >> + for (i = 0; i < ARRAY_SIZE(dev->m_table.avg_core_c0residency); i++) { >> + avg += dev->m_table.avg_core_c0residency[i]; >> + if (dev->m_table.avg_core_c0residency[i] > max) >> + max = dev->m_table.avg_core_c0residency[i]; >> + } >> + avg = DIV_ROUND_CLOSEST(avg, ARRAY_SIZE(dev->m_table.avg_core_c0residency)); >> + break; >> + case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: >> + max = dev->m_table_v2.core_c0residency[0]; >> + for (i = 0; i < ARRAY_SIZE(dev->m_table_v2.core_c0residency); i++) { >> + avg += dev->m_table_v2.core_c0residency[i]; >> + if (dev->m_table_v2.core_c0residency[i] > max) >> + max = dev->m_table_v2.core_c0residency[i]; >> + } >> + avg = DIV_ROUND_CLOSEST(avg, ARRAY_SIZE(dev->m_table_v2.core_c0residency)); > > This is not what I meant. Add a helper which takes the c0residency array > as a pointer and the number of elements (+ the pointers to result > variables, obviously). The helper should not care which struct the values > come from. > Sorry, misunderstood your remarks. Shall send a revised version now. Thanks, Shyam ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2024-08-13 13:33 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-08-13 9:00 [PATCH v2 1/2] platform/x86/amd/pmf: Relocate CPU ID macros to the PMF header Shyam Sundar S K 2024-08-13 9:00 ` [PATCH v2 2/2] platform/x86/amd/pmf: Update SMU metrics table for 1AH family series Shyam Sundar S K 2024-08-13 9:08 ` Ilpo Järvinen 2024-08-13 13:33 ` Shyam Sundar S K
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