Re: [PATCH 3/5] target/riscv: Add a config option for native debug

[Richard Henderson <richard.henderson@linaro.org>]

On 10/29/21 8:25 AM, Bin Meng wrote:
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index eface73e7d..3a2fa97098 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -439,6 +439,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>           }
>       }
>   
> +    if (cpu->cfg.debug) {
> +        set_feature(env, RISCV_FEATURE_DEBUG);
> +    }
> +
>       set_resetvec(env, cpu->cfg.resetvec);
>   
>       /* Validate that MISA_MXL is set properly. */
> @@ -619,6 +623,7 @@ static Property riscv_cpu_properties[] = {
>       DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>       DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>       DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> +    DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>   
>       DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),

This half of the patch needs to come as the last patch, after you've finished 
implementation.  The first two hunks might as well fold into the first patch.


r~