Re: [PATCH v3 2/3] arm: handle CCSIDR_EL1 as a demuxed register

[Cornelia Huck <cohuck@redhat.com>]

On Mon, Jun 29 2026, Eric Auger <eauger@redhat.com> wrote:

> Hi Sebastian,
>
> On 6/22/26 3:56 PM, Sebastian Ott wrote:

(...)

>> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
>> index 6e8b335b8f..d9e058a57e 100644
>> --- a/target/arm/cpu-sysregs.h.inc
>> +++ b/target/arm/cpu-sysregs.h.inc
>> @@ -39,6 +39,7 @@ DEF(MVFR2_EL1, 3, 0, 0, 3, 2)
>>  DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4)
>>  DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5)
>>  DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6)
>> +DEF_MUX(CCSIDR_EL1, 3, 1, 0, 0, 0, 16)
> As I mentionned earlier, if this file were to be generated at some
> point, I don't see how I can infer the size of the muxed register from
> the AARCHMRS.
>
> Nevertheless I can move this definition somewhere else later and I think
> this shall not be a blocker for this series

Can we move this to some cpu-sysregs-demux.h.inc file? It would mess up
the order, but that should not be a problem in practice?

>
> Also I wonder if 16 is enough (although it is the current size in
> ArchCPU). In the future might end up = 8 levels x Ind 2 value x 2 value
> TnD = 32
>
> May be Tnd is not featured yet because it is relevant if FEAT_MTE2 is
> supported.

The KVM interface is also limited IIRC, so I guess it would need to be
extended.

>
>>  DEF(CLIDR_EL1, 3, 1, 0, 0, 1)
>>  DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4)
>>  DEF(CTR_EL0, 3, 3, 0, 0, 1)