* [PATCH v3 0/3] arm: demuxed ID registers (CCSIDR_EL1)
@ 2026-06-22 13:56 Sebastian Ott
2026-06-22 13:56 ` [PATCH v3 1/3] arm: handle demuxed ID registers Sebastian Ott
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Sebastian Ott @ 2026-06-22 13:56 UTC (permalink / raw)
To: Peter Maydell, Eric Auger, Jonathan Cameron, Alireza Sanaee,
Richard Henderson, Cornelia Huck
Cc: qemu-arm, qemu-devel, Sebastian Ott
Handle the demuxed ID register CCSIDR_EL1 as part of the
idregs array. V2 of this series was posted here:
https://lore.kernel.org/qemu-devel/20260204133229.297061-1-cohuck@redhat.com/
Connie asked me to carry these forward.
Changes V2->V3:
* removed extra idregs_demux[] array based on suggestion from Richard
* removed COPY_IDREG_DEMUX suggested from Eric
* add CSSELR_MAX define
* rebased to current master
* removed my R-Bs
We still manually add the register definition to target/arm/cpu-sysregs.h.inc
- can we add special handling for that in the script that generates this?
Cornelia Huck (3):
arm: handle demuxed ID registers
arm: handle CCSIDR_EL1 as a demuxed register
arm/kvm: get demuxed ID registers from kvm
hw/arm/virt.c | 23 ++++++------
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu-max.c | 6 ++--
target/arm/cpu-sysregs.h | 9 +++++
target/arm/cpu-sysregs.h.inc | 1 +
target/arm/cpu.h | 18 ++++++----
target/arm/cpu64.c | 14 ++++++--
target/arm/helper.c | 2 +-
target/arm/kvm.c | 32 +++++++++++++++++
target/arm/tcg/cpu32-system.c | 26 +++++++-------
target/arm/tcg/cpu64.c | 68 +++++++++++++++++------------------
11 files changed, 129 insertions(+), 72 deletions(-)
--
2.54.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v3 1/3] arm: handle demuxed ID registers 2026-06-22 13:56 [PATCH v3 0/3] arm: demuxed ID registers (CCSIDR_EL1) Sebastian Ott @ 2026-06-22 13:56 ` Sebastian Ott 2026-06-29 14:33 ` Eric Auger 2026-06-22 13:56 ` [PATCH v3 2/3] arm: handle CCSIDR_EL1 as a demuxed register Sebastian Ott 2026-06-22 13:56 ` [PATCH v3 3/3] arm/kvm: get demuxed ID registers from kvm Sebastian Ott 2 siblings, 1 reply; 8+ messages in thread From: Sebastian Ott @ 2026-06-22 13:56 UTC (permalink / raw) To: Peter Maydell, Eric Auger, Jonathan Cameron, Alireza Sanaee, Richard Henderson, Cornelia Huck Cc: qemu-arm, qemu-devel, Sebastian Ott From: Cornelia Huck <cohuck@redhat.com> For some registers, we do not have a single ID register, but actually an array of values (e.g. CCSIDR_EL1, where the actual value is determined by whatever CSSELR_EL1 points to.) If we want to avoid using a different way to handle registers like that for every instance, we should provide some kind of infrastructure. Therefore, add accessors {GET,SET}_IDREG_DEMUX that are similar to the accessors we already use for regular ID registers. Tested-by: Alireza Sanaee <alireza.sanaee@huawei.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Sebastian Ott <sebott@redhat.com> --- target/arm/cpu-sysregs.h | 9 +++++++++ target/arm/cpu.h | 12 ++++++++++++ target/arm/cpu64.c | 8 ++++++++ 3 files changed, 29 insertions(+) diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h index 7877a3b06a..a4b9621a7e 100644 --- a/target/arm/cpu-sysregs.h +++ b/target/arm/cpu-sysregs.h @@ -20,20 +20,29 @@ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX, +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ + NAME##_IDX, \ + NAME##_IDX_LAST = NAME##_IDX + NUM - 1, + typedef enum ARMIDRegisterIdx { #include "cpu-sysregs.h.inc" NUM_ID_IDX, } ARMIDRegisterIdx; #undef DEF +#undef DEF_MUX #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2), +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ + DEF(NAME, OP0, OP1, CRN, CRM, OP2) + typedef enum ARMSysRegs { #include "cpu-sysregs.h.inc" } ARMSysRegs; #undef DEF +#undef DEF_MUX extern const uint32_t id_register_sysreg[NUM_ID_IDX]; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 31a5567c95..fe0046b02e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -919,6 +919,18 @@ typedef struct { i_->idregs[REG ## _EL1_IDX]; \ }) +#define SET_IDREG_DEMUX(ISAR, REG, INDEX, VALUE) \ + ({ \ + ARMISARegisters *i_ = (ISAR); \ + i_->idregs[REG ## _IDX + INDEX] = VALUE; \ + }) + +#define GET_IDREG_DEMUX(ISAR, REG, INDEX) \ + ({ \ + ARMISARegisters *i_ = (ISAR); \ + i_->idregs[REG ## _IDX + INDEX]; \ + }) + /** * ARMCPU: * @env: #CPUARMState diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2816735577..48a0421674 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -42,14 +42,21 @@ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ [NAME##_IDX] = SYS_##NAME, +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ + DEF(NAME, OP0, OP1, CRN, CRM, OP2) + const uint32_t id_register_sysreg[NUM_ID_IDX] = { #include "cpu-sysregs.h.inc" }; #undef DEF +#undef DEF_MUX #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ case SYS_##NAME: return NAME##_IDX; +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ + DEF(NAME, OP0, OP1, CRN, CRM, OP2) + int get_sysreg_idx(ARMSysRegs sysreg) { switch (sysreg) { @@ -59,6 +66,7 @@ int get_sysreg_idx(ARMSysRegs sysreg) } #undef DEF +#undef DEF_MUX void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { -- 2.54.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/3] arm: handle demuxed ID registers 2026-06-22 13:56 ` [PATCH v3 1/3] arm: handle demuxed ID registers Sebastian Ott @ 2026-06-29 14:33 ` Eric Auger 0 siblings, 0 replies; 8+ messages in thread From: Eric Auger @ 2026-06-29 14:33 UTC (permalink / raw) To: Sebastian Ott, Peter Maydell, Jonathan Cameron, Alireza Sanaee, Richard Henderson, Cornelia Huck Cc: qemu-arm, qemu-devel On 6/22/26 3:56 PM, Sebastian Ott wrote: > From: Cornelia Huck <cohuck@redhat.com> > > For some registers, we do not have a single ID register, but actually > an array of values (e.g. CCSIDR_EL1, where the actual value is > determined by whatever CSSELR_EL1 points to.) If we want to avoid > using a different way to handle registers like that for every > instance, we should provide some kind of infrastructure. Therefore, > add accessors {GET,SET}_IDREG_DEMUX that are similar to the accessors > we already use for regular ID registers. > > Tested-by: Alireza Sanaee <alireza.sanaee@huawei.com> > Signed-off-by: Cornelia Huck <cohuck@redhat.com> > Signed-off-by: Sebastian Ott <sebott@redhat.com> With actual implementation Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Eric > --- > target/arm/cpu-sysregs.h | 9 +++++++++ > target/arm/cpu.h | 12 ++++++++++++ > target/arm/cpu64.c | 8 ++++++++ > 3 files changed, 29 insertions(+) > > diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h > index 7877a3b06a..a4b9621a7e 100644 > --- a/target/arm/cpu-sysregs.h > +++ b/target/arm/cpu-sysregs.h > @@ -20,20 +20,29 @@ > > #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX, > > +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ > + NAME##_IDX, \ > + NAME##_IDX_LAST = NAME##_IDX + NUM - 1, > + > typedef enum ARMIDRegisterIdx { > #include "cpu-sysregs.h.inc" > NUM_ID_IDX, > } ARMIDRegisterIdx; > > #undef DEF > +#undef DEF_MUX > #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ > SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2), > > +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ > + DEF(NAME, OP0, OP1, CRN, CRM, OP2) > + > typedef enum ARMSysRegs { > #include "cpu-sysregs.h.inc" > } ARMSysRegs; > > #undef DEF > +#undef DEF_MUX > > extern const uint32_t id_register_sysreg[NUM_ID_IDX]; > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 31a5567c95..fe0046b02e 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -919,6 +919,18 @@ typedef struct { > i_->idregs[REG ## _EL1_IDX]; \ > }) > > +#define SET_IDREG_DEMUX(ISAR, REG, INDEX, VALUE) \ > + ({ \ > + ARMISARegisters *i_ = (ISAR); \ > + i_->idregs[REG ## _IDX + INDEX] = VALUE; \ > + }) > + > +#define GET_IDREG_DEMUX(ISAR, REG, INDEX) \ > + ({ \ > + ARMISARegisters *i_ = (ISAR); \ > + i_->idregs[REG ## _IDX + INDEX]; \ > + }) > + > /** > * ARMCPU: > * @env: #CPUARMState > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 2816735577..48a0421674 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -42,14 +42,21 @@ > #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ > [NAME##_IDX] = SYS_##NAME, > > +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ > + DEF(NAME, OP0, OP1, CRN, CRM, OP2) > + > const uint32_t id_register_sysreg[NUM_ID_IDX] = { > #include "cpu-sysregs.h.inc" > }; > > #undef DEF > +#undef DEF_MUX > #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ > case SYS_##NAME: return NAME##_IDX; > > +#define DEF_MUX(NAME, OP0, OP1, CRN, CRM, OP2, NUM) \ > + DEF(NAME, OP0, OP1, CRN, CRM, OP2) > + > int get_sysreg_idx(ARMSysRegs sysreg) > { > switch (sysreg) { > @@ -59,6 +66,7 @@ int get_sysreg_idx(ARMSysRegs sysreg) > } > > #undef DEF > +#undef DEF_MUX > > void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) > { ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 2/3] arm: handle CCSIDR_EL1 as a demuxed register 2026-06-22 13:56 [PATCH v3 0/3] arm: demuxed ID registers (CCSIDR_EL1) Sebastian Ott 2026-06-22 13:56 ` [PATCH v3 1/3] arm: handle demuxed ID registers Sebastian Ott @ 2026-06-22 13:56 ` Sebastian Ott 2026-06-29 15:23 ` Eric Auger 2026-06-22 13:56 ` [PATCH v3 3/3] arm/kvm: get demuxed ID registers from kvm Sebastian Ott 2 siblings, 1 reply; 8+ messages in thread From: Sebastian Ott @ 2026-06-22 13:56 UTC (permalink / raw) To: Peter Maydell, Eric Auger, Jonathan Cameron, Alireza Sanaee, Richard Henderson, Cornelia Huck Cc: qemu-arm, qemu-devel, Sebastian Ott From: Cornelia Huck <cohuck@redhat.com> Move handling of CCSIDR_EL1 over to the new *_IDREG_DEMUX infrastructure. Tested-by: Alireza Sanaee <alireza.sanaee@huawei.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Sebastian Ott <sebott@redhat.com> --- hw/arm/virt.c | 23 ++++++------ hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu-max.c | 6 ++-- target/arm/cpu-sysregs.h.inc | 1 + target/arm/cpu.h | 6 ---- target/arm/cpu64.c | 6 ++-- target/arm/helper.c | 2 +- target/arm/tcg/cpu32-system.c | 26 +++++++------- target/arm/tcg/cpu64.c | 68 +++++++++++++++++------------------ 9 files changed, 68 insertions(+), 72 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d8d27f2ef6..ab2b566e69 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -307,21 +307,22 @@ void set_cpu_cache(CPUCoreCaches *cpu_cache, enum CacheType cache_type, if (ccidx) { *cpu_cache = (CPUCoreCaches){ - .linesize = 1 << (FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, - CCIDX_LINESIZE) + 4), - .associativity = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, - CCIDX_ASSOCIATIVITY) + 1, - .sets = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, - CCIDX_NUMSETS) + 1, + .linesize = 1 << (FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), + CCSIDR_EL1, CCIDX_LINESIZE) + 4), + .associativity = FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), + CCSIDR_EL1, CCIDX_ASSOCIATIVITY) + 1, + .sets = FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), + CCSIDR_EL1, CCIDX_NUMSETS) + 1, }; } else { *cpu_cache = (CPUCoreCaches){ - .linesize = 1 << (FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, - LINESIZE) + 4), - .associativity = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, - ASSOCIATIVITY) + 1, + .linesize = 1 << (FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), + CCSIDR_EL1, LINESIZE) + 4), + .associativity = FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), + CCSIDR_EL1, ASSOCIATIVITY) + 1, .sets = - FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, NUMSETS) + 1, + FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), + CCSIDR_EL1, NUMSETS) + 1, }; } cpu_cache->type = cache_type; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a7651f831e..5dd867242b 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1360,7 +1360,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) case 0xd80: /* CSSIDR */ { int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK; - return cpu->ccsidr[idx]; + return GET_IDREG_DEMUX(&cpu->isar, CCSIDR_EL1, idx); } case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index d38bdfcf81..d2f69b6bcf 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -72,11 +72,11 @@ void aarch64_aa32_a57_init(Object *obj, bool aa32_only) cpu->isar.reset_pmcr_el0 = 0x41013000; SET_IDREG(isar, CLIDR, 0x0a200023); /* 32KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7)); /* 48KB L1 icache */ - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2)); /* 2048KB L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7)); if (aarch64_enabled) { set_dczid_bs(cpu, 4); /* 64 bytes */ cpu->gic_num_lrs = 4; diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 6e8b335b8f..d9e058a57e 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -39,6 +39,7 @@ DEF(MVFR2_EL1, 3, 0, 0, 3, 2) DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) +DEF_MUX(CCSIDR_EL1, 3, 1, 0, 0, 0, 16) DEF(CLIDR_EL1, 3, 1, 0, 0, 1) DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) DEF(CTR_EL0, 3, 3, 0, 0, 1) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fe0046b02e..437e72d475 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1121,10 +1121,6 @@ struct ArchCPU { uint64_t pmceid0; uint64_t pmceid1; uint64_t mp_affinity; /* MP ID without feature bits */ - /* The elements of this array are the CCSIDR values for each cache, - * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. - */ - uint64_t ccsidr[16]; uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; @@ -2132,8 +2128,6 @@ FIELD(MFAR, FPA, 12, 40) FIELD(MFAR, NSE, 62, 1) FIELD(MFAR, NS, 63, 1) -QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); - /* If adding a feature bit which corresponds to a Linux ELF * HWCAP bit, remember to update the feature-bit-to-hwcap * mapping in linux-user/elfload.c:get_elf_hwcap(). diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 48a0421674..9bcef81dce 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,11 +748,11 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.reset_pmcr_el0 = 0x41033000; SET_IDREG(isar, CLIDR, 0x0a200023); /* 32KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7)); /* 32KB L1 icache */ - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2)); /* 1024KB L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7)); set_dczid_bs(cpu, 4); /* 64 bytes */ cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; diff --git a/target/arm/helper.c b/target/arm/helper.c index a234aa031c..4bc616fff5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -873,7 +873,7 @@ static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) uint32_t index = A32_BANKED_REG_GET(env, csselr, ri->secure & ARM_CP_SECSTATE_S); - return cpu->ccsidr[index]; + return GET_IDREG_DEMUX(&cpu->isar, CCSIDR_EL1, index); } static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/tcg/cpu32-system.c b/target/arm/tcg/cpu32-system.c index 6e98390089..f00c996db3 100644 --- a/target/arm/tcg/cpu32-system.c +++ b/target/arm/tcg/cpu32-system.c @@ -270,9 +270,9 @@ static void cortex_a8_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr = 0x15141000; SET_IDREG(isar, CLIDR, (1 << 27) | (2 << 24) | 3); - cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ - cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ - cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, 0xe007e01a); /* 16k L1 dcache. */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, 0x2007e01a); /* 16k L1 icache. */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, 0xf0000000); /* No L2 icache. */ cpu->reset_auxcr = 2; cpu->isar.reset_pmcr_el0 = 0x41002000; define_arm_cp_regs(cpu, cortexa8_cp_reginfo); @@ -346,8 +346,8 @@ static void cortex_a9_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr = 0x35141000; SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 3); - cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ - cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, 0xe00fe019); /* 16k L1 dcache. */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, 0x200fe019); /* 16k L1 icache. */ cpu->isar.reset_pmcr_el0 = 0x41093000; define_arm_cp_regs(cpu, cortexa9_cp_reginfo); } @@ -418,9 +418,9 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.dbgdevid = 0x01110f13; cpu->isar.dbgdevid1 = 0x1; SET_IDREG(isar, CLIDR, 0x0a200023); - cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, 0x701fe00a); /* 32K L1 dcache */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, 0x201fe00a); /* 32K L1 icache */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, 0x711fe07a); /* 4096K L2 unified cache */ cpu->isar.reset_pmcr_el0 = 0x41072000; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ } @@ -466,9 +466,9 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.dbgdevid = 0x01110f13; cpu->isar.dbgdevid1 = 0x0; SET_IDREG(isar, CLIDR, 0x0a200023); - cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, 0x701fe00a); /* 32K L1 dcache */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, 0x201fe00a); /* 32K L1 icache */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, 0x711fe07a); /* 4096K L2 unified cache */ cpu->isar.reset_pmcr_el0 = 0x410F3000; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } @@ -657,8 +657,8 @@ static void cortex_r52_initfn(Object *obj) SET_IDREG(isar, ID_ISAR5, 0x00010001); cpu->isar.dbgdidr = 0x77168000; SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 0x3); - cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ - cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, 0x700fe01a); /* 32KB L1 dcache */ + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, 0x201fe00a); /* 32KB L1 icache */ cpu->pmsav7_dregion = 16; cpu->pmsav8r_hdregion = 16; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index f7a920a202..1d6e0362b1 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -82,11 +82,11 @@ static void aarch64_a35_initfn(Object *obj) /* From B2.29 Cache ID registers */ /* 32KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7)); /* 32KB L1 icache */ - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2)); /* 512KB L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7)); /* From B3.5 VGIC Type register */ cpu->gic_num_lrs = 4; @@ -250,11 +250,11 @@ static void aarch64_a55_initfn(Object *obj) /* From B2.23 CCSIDR_EL1 */ /* 32KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7)); /* 32KB L1 icache */ - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2)); /* 512KB L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7)); /* From B2.96 SCTLR_EL3 */ cpu->reset_sctlr = 0x30c50838; @@ -320,11 +320,11 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.reset_pmcr_el0 = 0x41023000; SET_IDREG(isar, CLIDR, 0x0a200023); /* 32KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7)); /* 48KB L1 dcache */ - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2)); /* 1MB L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7)); set_dczid_bs(cpu, 4); /* 64 bytes */ cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; @@ -383,11 +383,11 @@ static void aarch64_a76_initfn(Object *obj) /* From B2.18 CCSIDR_EL1 */ /* 64KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7)); /* 64KB L1 icache */ - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2)); /* 512KB L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7)); /* From B2.93 SCTLR_EL3 */ cpu->reset_sctlr = 0x30c50838; @@ -455,11 +455,11 @@ static void aarch64_a78ae_initfn(Object *obj) /* From 3.2.33 CCSIDR_EL1 */ /* 64KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7)); /* 64KB L1 icache */ - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2)); /* 512KB L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7)); /* From 3.2.118 SCTLR_EL3 */ cpu->reset_sctlr = 0x30c50838; @@ -512,11 +512,11 @@ static void aarch64_a64fx_initfn(Object *obj) SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); SET_IDREG(isar, CLIDR, 0x0000000080000023); /* 64KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7)); /* 64KB L1 icache */ - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 2); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 2)); /* 8MB L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB, 7)); set_dczid_bs(cpu, 6); /* 256 bytes */ cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; @@ -704,11 +704,11 @@ static void aarch64_neoverse_n1_initfn(Object *obj) /* From B2.23 CCSIDR_EL1 */ /* 64KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7)); /* 64KB L1 icache */ - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2)); /* 1MB L2 dcache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7)); /* From B2.98 SCTLR_EL3 */ cpu->reset_sctlr = 0x30c50838; @@ -792,11 +792,11 @@ static void aarch64_neoverse_v1_initfn(Object *obj) * L3: No L3 (this matches the CLIDR_EL1 value). */ /* 64KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); /* 64KB L1 icache */ - cpu->ccsidr[1] = cpu->ccsidr[0]; + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); /* 1MB L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0)); /* From 3.2.115 SCTLR_EL3 */ cpu->reset_sctlr = 0x30c50838; @@ -1034,11 +1034,11 @@ static void aarch64_a710_initfn(Object *obj) * L2: 8-way set associative 64 byte line size, total either 256K or 512K. */ /* L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); /* L1 icache */ - cpu->ccsidr[1] = cpu->ccsidr[0]; + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); /* L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0)); /* FIXME: Not documented -- copied from neoverse-v1 */ cpu->reset_sctlr = 0x30c50838; @@ -1136,11 +1136,11 @@ static void aarch64_neoverse_n2_initfn(Object *obj) * L2: 8-way set associative 64 byte line size, total either 512K or 1024K. */ /* L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); /* L1 icache */ - cpu->ccsidr[1] = cpu->ccsidr[0]; + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); /* L2 cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0)); /* FIXME: Not documented -- copied from neoverse-v1 */ cpu->reset_sctlr = 0x30c50838; @@ -1169,13 +1169,13 @@ void aarch64_max_tcg_initfn(Object *obj) SET_IDREG(isar, CLIDR, 0x8200123); /* 64KB L1 dcache */ - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7)); /* 64KB L1 icache */ - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2)); /* 1MB L2 unified cache */ - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7)); /* 2MB L3 unified cache */ - cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7); + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 4, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7)); /* * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default -- 2.54.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/3] arm: handle CCSIDR_EL1 as a demuxed register 2026-06-22 13:56 ` [PATCH v3 2/3] arm: handle CCSIDR_EL1 as a demuxed register Sebastian Ott @ 2026-06-29 15:23 ` Eric Auger 2026-06-30 13:49 ` Cornelia Huck 0 siblings, 1 reply; 8+ messages in thread From: Eric Auger @ 2026-06-29 15:23 UTC (permalink / raw) To: Sebastian Ott, Peter Maydell, Jonathan Cameron, Alireza Sanaee, Richard Henderson, Cornelia Huck Cc: qemu-arm, qemu-devel Hi Sebastian, On 6/22/26 3:56 PM, Sebastian Ott wrote: > From: Cornelia Huck <cohuck@redhat.com> > > Move handling of CCSIDR_EL1 over to the new *_IDREG_DEMUX > infrastructure. > > Tested-by: Alireza Sanaee <alireza.sanaee@huawei.com> > Signed-off-by: Cornelia Huck <cohuck@redhat.com> > Signed-off-by: Sebastian Ott <sebott@redhat.com> > --- > hw/arm/virt.c | 23 ++++++------ > hw/intc/armv7m_nvic.c | 2 +- > target/arm/cpu-max.c | 6 ++-- > target/arm/cpu-sysregs.h.inc | 1 + > target/arm/cpu.h | 6 ---- > target/arm/cpu64.c | 6 ++-- > target/arm/helper.c | 2 +- > target/arm/tcg/cpu32-system.c | 26 +++++++------- > target/arm/tcg/cpu64.c | 68 +++++++++++++++++------------------ > 9 files changed, 68 insertions(+), 72 deletions(-) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index d8d27f2ef6..ab2b566e69 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -307,21 +307,22 @@ void set_cpu_cache(CPUCoreCaches *cpu_cache, enum CacheType cache_type, > I think you would gain in readibility to use a local variable ccsdir = GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index); > if (ccidx) { > *cpu_cache = (CPUCoreCaches){ > - .linesize = 1 << (FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, > - CCIDX_LINESIZE) + 4), > - .associativity = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, > - CCIDX_ASSOCIATIVITY) + 1, > - .sets = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, > - CCIDX_NUMSETS) + 1, > + .linesize = 1 << (FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), > + CCSIDR_EL1, CCIDX_LINESIZE) + 4), > + .associativity = FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), > + CCSIDR_EL1, CCIDX_ASSOCIATIVITY) + 1, > + .sets = FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), > + CCSIDR_EL1, CCIDX_NUMSETS) + 1, > }; > } else { > *cpu_cache = (CPUCoreCaches){ > - .linesize = 1 << (FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, > - LINESIZE) + 4), > - .associativity = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, > - ASSOCIATIVITY) + 1, > + .linesize = 1 << (FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), > + CCSIDR_EL1, LINESIZE) + 4), > + .associativity = FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), > + CCSIDR_EL1, ASSOCIATIVITY) + 1, > .sets = > - FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, NUMSETS) + 1, > + FIELD_EX64(GET_IDREG_DEMUX(&armcpu->isar, CCSIDR_EL1, bank_index), > + CCSIDR_EL1, NUMSETS) + 1, > }; > } > cpu_cache->type = cache_type; > diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c > index a7651f831e..5dd867242b 100644 > --- a/hw/intc/armv7m_nvic.c > +++ b/hw/intc/armv7m_nvic.c > @@ -1360,7 +1360,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) > case 0xd80: /* CSSIDR */ > { > int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK; > - return cpu->ccsidr[idx]; > + return GET_IDREG_DEMUX(&cpu->isar, CCSIDR_EL1, idx); > } > case 0xd84: /* CSSELR */ > return cpu->env.v7m.csselr[attrs.secure]; > diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c > index d38bdfcf81..d2f69b6bcf 100644 > --- a/target/arm/cpu-max.c > +++ b/target/arm/cpu-max.c > @@ -72,11 +72,11 @@ void aarch64_aa32_a57_init(Object *obj, bool aa32_only) > cpu->isar.reset_pmcr_el0 = 0x41013000; > SET_IDREG(isar, CLIDR, 0x0a200023); > /* 32KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7)); > /* 48KB L1 icache */ > - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2)); > /* 2048KB L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7)); > if (aarch64_enabled) { > set_dczid_bs(cpu, 4); /* 64 bytes */ > cpu->gic_num_lrs = 4; > diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc > index 6e8b335b8f..d9e058a57e 100644 > --- a/target/arm/cpu-sysregs.h.inc > +++ b/target/arm/cpu-sysregs.h.inc > @@ -39,6 +39,7 @@ DEF(MVFR2_EL1, 3, 0, 0, 3, 2) > DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) > DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) > DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) > +DEF_MUX(CCSIDR_EL1, 3, 1, 0, 0, 0, 16) As I mentionned earlier, if this file were to be generated at some point, I don't see how I can infer the size of the muxed register from the AARCHMRS. Nevertheless I can move this definition somewhere else later and I think this shall not be a blocker for this series Also I wonder if 16 is enough (although it is the current size in ArchCPU). In the future might end up = 8 levels x Ind 2 value x 2 value TnD = 32 May be Tnd is not featured yet because it is relevant if FEAT_MTE2 is supported. > DEF(CLIDR_EL1, 3, 1, 0, 0, 1) > DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) > DEF(CTR_EL0, 3, 3, 0, 0, 1) > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index fe0046b02e..437e72d475 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1121,10 +1121,6 @@ struct ArchCPU { > uint64_t pmceid0; > uint64_t pmceid1; > uint64_t mp_affinity; /* MP ID without feature bits */ > - /* The elements of this array are the CCSIDR values for each cache, > - * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. > - */ > - uint64_t ccsidr[16]; > uint64_t reset_cbar; > uint32_t reset_auxcr; > bool reset_hivecs; > @@ -2132,8 +2128,6 @@ FIELD(MFAR, FPA, 12, 40) > FIELD(MFAR, NSE, 62, 1) > FIELD(MFAR, NS, 63, 1) > > -QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); > - > /* If adding a feature bit which corresponds to a Linux ELF > * HWCAP bit, remember to update the feature-bit-to-hwcap > * mapping in linux-user/elfload.c:get_elf_hwcap(). > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 48a0421674..9bcef81dce 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -748,11 +748,11 @@ static void aarch64_a53_initfn(Object *obj) > cpu->isar.reset_pmcr_el0 = 0x41033000; > SET_IDREG(isar, CLIDR, 0x0a200023); > /* 32KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7)); > /* 32KB L1 icache */ > - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2)); > /* 1024KB L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7)); > set_dczid_bs(cpu, 4); /* 64 bytes */ > cpu->gic_num_lrs = 4; > cpu->gic_vpribits = 5; > diff --git a/target/arm/helper.c b/target/arm/helper.c > index a234aa031c..4bc616fff5 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -873,7 +873,7 @@ static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) > uint32_t index = A32_BANKED_REG_GET(env, csselr, > ri->secure & ARM_CP_SECSTATE_S); > > - return cpu->ccsidr[index]; > + return GET_IDREG_DEMUX(&cpu->isar, CCSIDR_EL1, index); > } > > static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, > diff --git a/target/arm/tcg/cpu32-system.c b/target/arm/tcg/cpu32-system.c > index 6e98390089..f00c996db3 100644 > --- a/target/arm/tcg/cpu32-system.c > +++ b/target/arm/tcg/cpu32-system.c > @@ -270,9 +270,9 @@ static void cortex_a8_initfn(Object *obj) > SET_IDREG(isar, ID_ISAR4, 0x00111142); > cpu->isar.dbgdidr = 0x15141000; > SET_IDREG(isar, CLIDR, (1 << 27) | (2 << 24) | 3); > - cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ > - cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ > - cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, 0xe007e01a); /* 16k L1 dcache. */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, 0x2007e01a); /* 16k L1 icache. */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, 0xf0000000); /* No L2 icache. */ > cpu->reset_auxcr = 2; > cpu->isar.reset_pmcr_el0 = 0x41002000; > define_arm_cp_regs(cpu, cortexa8_cp_reginfo); > @@ -346,8 +346,8 @@ static void cortex_a9_initfn(Object *obj) > SET_IDREG(isar, ID_ISAR4, 0x00111142); > cpu->isar.dbgdidr = 0x35141000; > SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 3); > - cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ > - cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, 0xe00fe019); /* 16k L1 dcache. */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, 0x200fe019); /* 16k L1 icache. */ > cpu->isar.reset_pmcr_el0 = 0x41093000; > define_arm_cp_regs(cpu, cortexa9_cp_reginfo); > } > @@ -418,9 +418,9 @@ static void cortex_a7_initfn(Object *obj) > cpu->isar.dbgdevid = 0x01110f13; > cpu->isar.dbgdevid1 = 0x1; > SET_IDREG(isar, CLIDR, 0x0a200023); > - cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ > - cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ > - cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, 0x701fe00a); /* 32K L1 dcache */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, 0x201fe00a); /* 32K L1 icache */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, 0x711fe07a); /* 4096K L2 unified cache */ > cpu->isar.reset_pmcr_el0 = 0x41072000; > define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ > } > @@ -466,9 +466,9 @@ static void cortex_a15_initfn(Object *obj) > cpu->isar.dbgdevid = 0x01110f13; > cpu->isar.dbgdevid1 = 0x0; > SET_IDREG(isar, CLIDR, 0x0a200023); > - cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ > - cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ > - cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, 0x701fe00a); /* 32K L1 dcache */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, 0x201fe00a); /* 32K L1 icache */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, 0x711fe07a); /* 4096K L2 unified cache */ > cpu->isar.reset_pmcr_el0 = 0x410F3000; > define_arm_cp_regs(cpu, cortexa15_cp_reginfo); > } > @@ -657,8 +657,8 @@ static void cortex_r52_initfn(Object *obj) > SET_IDREG(isar, ID_ISAR5, 0x00010001); > cpu->isar.dbgdidr = 0x77168000; > SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 0x3); > - cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ > - cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, 0x700fe01a); /* 32KB L1 dcache */ > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, 0x201fe00a); /* 32KB L1 icache */ > > cpu->pmsav7_dregion = 16; > cpu->pmsav8r_hdregion = 16; > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > index f7a920a202..1d6e0362b1 100644 > --- a/target/arm/tcg/cpu64.c > +++ b/target/arm/tcg/cpu64.c > @@ -82,11 +82,11 @@ static void aarch64_a35_initfn(Object *obj) > > /* From B2.29 Cache ID registers */ > /* 32KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7)); > /* 32KB L1 icache */ > - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2)); > /* 512KB L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7)); > > /* From B3.5 VGIC Type register */ > cpu->gic_num_lrs = 4; > @@ -250,11 +250,11 @@ static void aarch64_a55_initfn(Object *obj) > > /* From B2.23 CCSIDR_EL1 */ > /* 32KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7)); > /* 32KB L1 icache */ > - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2)); > /* 512KB L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7)); > > /* From B2.96 SCTLR_EL3 */ > cpu->reset_sctlr = 0x30c50838; > @@ -320,11 +320,11 @@ static void aarch64_a72_initfn(Object *obj) > cpu->isar.reset_pmcr_el0 = 0x41023000; > SET_IDREG(isar, CLIDR, 0x0a200023); > /* 32KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7)); > /* 48KB L1 dcache */ > - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2)); > /* 1MB L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7)); > set_dczid_bs(cpu, 4); /* 64 bytes */ > cpu->gic_num_lrs = 4; > cpu->gic_vpribits = 5; > @@ -383,11 +383,11 @@ static void aarch64_a76_initfn(Object *obj) > > /* From B2.18 CCSIDR_EL1 */ > /* 64KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7)); > /* 64KB L1 icache */ > - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2)); > /* 512KB L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7)); > > /* From B2.93 SCTLR_EL3 */ > cpu->reset_sctlr = 0x30c50838; > @@ -455,11 +455,11 @@ static void aarch64_a78ae_initfn(Object *obj) > > /* From 3.2.33 CCSIDR_EL1 */ > /* 64KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7)); > /* 64KB L1 icache */ > - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2)); > /* 512KB L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7)); > > /* From 3.2.118 SCTLR_EL3 */ > cpu->reset_sctlr = 0x30c50838; > @@ -512,11 +512,11 @@ static void aarch64_a64fx_initfn(Object *obj) > SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); > SET_IDREG(isar, CLIDR, 0x0000000080000023); > /* 64KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7)); > /* 64KB L1 icache */ > - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 2); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 2)); > /* 8MB L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB, 7)); > set_dczid_bs(cpu, 6); /* 256 bytes */ > cpu->gic_num_lrs = 4; > cpu->gic_vpribits = 5; > @@ -704,11 +704,11 @@ static void aarch64_neoverse_n1_initfn(Object *obj) > > /* From B2.23 CCSIDR_EL1 */ > /* 64KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7)); > /* 64KB L1 icache */ > - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2)); > /* 1MB L2 dcache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7)); > > /* From B2.98 SCTLR_EL3 */ > cpu->reset_sctlr = 0x30c50838; > @@ -792,11 +792,11 @@ static void aarch64_neoverse_v1_initfn(Object *obj) > * L3: No L3 (this matches the CLIDR_EL1 value). > */ > /* 64KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); > /* 64KB L1 icache */ > - cpu->ccsidr[1] = cpu->ccsidr[0]; > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); > /* 1MB L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0)); > > /* From 3.2.115 SCTLR_EL3 */ > cpu->reset_sctlr = 0x30c50838; > @@ -1034,11 +1034,11 @@ static void aarch64_a710_initfn(Object *obj) > * L2: 8-way set associative 64 byte line size, total either 256K or 512K. > */ > /* L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); > /* L1 icache */ > - cpu->ccsidr[1] = cpu->ccsidr[0]; > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); > /* L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0)); > > /* FIXME: Not documented -- copied from neoverse-v1 */ > cpu->reset_sctlr = 0x30c50838; > @@ -1136,11 +1136,11 @@ static void aarch64_neoverse_n2_initfn(Object *obj) > * L2: 8-way set associative 64 byte line size, total either 512K or 1024K. > */ > /* L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); > /* L1 icache */ > - cpu->ccsidr[1] = cpu->ccsidr[0]; > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0)); > /* L2 cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0)); > /* FIXME: Not documented -- copied from neoverse-v1 */ > cpu->reset_sctlr = 0x30c50838; > > @@ -1169,13 +1169,13 @@ void aarch64_max_tcg_initfn(Object *obj) > > SET_IDREG(isar, CLIDR, 0x8200123); > /* 64KB L1 dcache */ > - cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7)); > /* 64KB L1 icache */ > - cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2)); > /* 1MB L2 unified cache */ > - cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7)); > /* 2MB L3 unified cache */ > - cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7); > + SET_IDREG_DEMUX(isar, CCSIDR_EL1, 4, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7)); > > /* > * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default Thanks Eric ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/3] arm: handle CCSIDR_EL1 as a demuxed register 2026-06-29 15:23 ` Eric Auger @ 2026-06-30 13:49 ` Cornelia Huck 0 siblings, 0 replies; 8+ messages in thread From: Cornelia Huck @ 2026-06-30 13:49 UTC (permalink / raw) To: Eric Auger, Sebastian Ott, Peter Maydell, Jonathan Cameron, Alireza Sanaee, Richard Henderson Cc: qemu-arm, qemu-devel On Mon, Jun 29 2026, Eric Auger <eauger@redhat.com> wrote: > Hi Sebastian, > > On 6/22/26 3:56 PM, Sebastian Ott wrote: (...) >> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc >> index 6e8b335b8f..d9e058a57e 100644 >> --- a/target/arm/cpu-sysregs.h.inc >> +++ b/target/arm/cpu-sysregs.h.inc >> @@ -39,6 +39,7 @@ DEF(MVFR2_EL1, 3, 0, 0, 3, 2) >> DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) >> DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) >> DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) >> +DEF_MUX(CCSIDR_EL1, 3, 1, 0, 0, 0, 16) > As I mentionned earlier, if this file were to be generated at some > point, I don't see how I can infer the size of the muxed register from > the AARCHMRS. > > Nevertheless I can move this definition somewhere else later and I think > this shall not be a blocker for this series Can we move this to some cpu-sysregs-demux.h.inc file? It would mess up the order, but that should not be a problem in practice? > > Also I wonder if 16 is enough (although it is the current size in > ArchCPU). In the future might end up = 8 levels x Ind 2 value x 2 value > TnD = 32 > > May be Tnd is not featured yet because it is relevant if FEAT_MTE2 is > supported. The KVM interface is also limited IIRC, so I guess it would need to be extended. > >> DEF(CLIDR_EL1, 3, 1, 0, 0, 1) >> DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) >> DEF(CTR_EL0, 3, 3, 0, 0, 1) ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 3/3] arm/kvm: get demuxed ID registers from kvm 2026-06-22 13:56 [PATCH v3 0/3] arm: demuxed ID registers (CCSIDR_EL1) Sebastian Ott 2026-06-22 13:56 ` [PATCH v3 1/3] arm: handle demuxed ID registers Sebastian Ott 2026-06-22 13:56 ` [PATCH v3 2/3] arm: handle CCSIDR_EL1 as a demuxed register Sebastian Ott @ 2026-06-22 13:56 ` Sebastian Ott 2026-06-29 15:28 ` Eric Auger 2 siblings, 1 reply; 8+ messages in thread From: Sebastian Ott @ 2026-06-22 13:56 UTC (permalink / raw) To: Peter Maydell, Eric Auger, Jonathan Cameron, Alireza Sanaee, Richard Henderson, Cornelia Huck Cc: qemu-arm, qemu-devel, Sebastian Ott From: Cornelia Huck <cohuck@redhat.com> We now have the infrastructure in place to handle demuxed ID registers from kvm. Use it to get the values that kvm emulates for CCSIDR_EL1. Tested-by: Alireza Sanaee <alireza.sanaee@huawei.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Sebastian Ott <sebott@redhat.com> --- target/arm/kvm.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index a54ef51ec2..059d361d88 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -244,6 +244,33 @@ static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, return ret; } + +/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ +#define CSSELR_MAX 14 + +static int get_host_cpu_reg_demux(int fd, ARMHostCPUFeatures *ahcf, + ARMIDRegisterIdx index, int subindex) +{ + + struct kvm_one_reg one_reg = { + .id = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX, + }; + + switch (index) { + case CCSIDR_EL1_IDX: + if (subindex >= CSSELR_MAX) { + return -EINVAL; + } + one_reg.id |= KVM_REG_ARM_DEMUX_ID_CCSIDR | subindex; + one_reg.addr = (uintptr_t)&ahcf->isar.idregs[index + subindex]; + break; + default: + return -EINVAL; + } + + return ioctl(fd, KVM_GET_ONE_REG, &one_reg); +} + static uint32_t kvm_arm_sve_get_vls(int fd) { uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; @@ -286,6 +313,7 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) bool pmu_supported = false; uint64_t features = 0; int err; + int i; ahcf->target = QEMU_KVM_ARM_TARGET_NONE; ahcf->dtb_compatible = "arm,armv8"; @@ -454,6 +482,10 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) /* Read the set of supported vector lengths. */ arm_host_cpu_features.sve_vq_supported = kvm_arm_sve_get_vls(fd); } + /* Grab demuxed registers. */ + for (i = 0; i < CSSELR_MAX; i++) { + err |= get_host_cpu_reg_demux(fd, ahcf, CCSIDR_EL1_IDX, i); + } } kvm_arm_destroy_scratch_host_vcpu(fdarray); -- 2.54.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 3/3] arm/kvm: get demuxed ID registers from kvm 2026-06-22 13:56 ` [PATCH v3 3/3] arm/kvm: get demuxed ID registers from kvm Sebastian Ott @ 2026-06-29 15:28 ` Eric Auger 0 siblings, 0 replies; 8+ messages in thread From: Eric Auger @ 2026-06-29 15:28 UTC (permalink / raw) To: Sebastian Ott, Peter Maydell, Jonathan Cameron, Alireza Sanaee, Richard Henderson, Cornelia Huck Cc: qemu-arm, qemu-devel Hi Sebastian, On 6/22/26 3:56 PM, Sebastian Ott wrote: > From: Cornelia Huck <cohuck@redhat.com> > > We now have the infrastructure in place to handle demuxed ID registers > from kvm. Use it to get the values that kvm emulates for CCSIDR_EL1. > > Tested-by: Alireza Sanaee <alireza.sanaee@huawei.com> > Signed-off-by: Cornelia Huck <cohuck@redhat.com> > Signed-off-by: Sebastian Ott <sebott@redhat.com> > --- > target/arm/kvm.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/target/arm/kvm.c b/target/arm/kvm.c > index a54ef51ec2..059d361d88 100644 > --- a/target/arm/kvm.c > +++ b/target/arm/kvm.c > @@ -244,6 +244,33 @@ static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, > return ret; > } > > + > +/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ > +#define CSSELR_MAX 14 where does this value come from? Worth to document > + > +static int get_host_cpu_reg_demux(int fd, ARMHostCPUFeatures *ahcf, > + ARMIDRegisterIdx index, int subindex) > +{ > + > + struct kvm_one_reg one_reg = { > + .id = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX, > + }; > + > + switch (index) { > + case CCSIDR_EL1_IDX: > + if (subindex >= CSSELR_MAX) { Can't we introduce a macro that gets the size of the DEMUX register instead of hardcoding it? > + return -EINVAL; > + } > + one_reg.id |= KVM_REG_ARM_DEMUX_ID_CCSIDR | subindex; > + one_reg.addr = (uintptr_t)&ahcf->isar.idregs[index + subindex]; > + break; > + default: > + return -EINVAL; > + } > + > + return ioctl(fd, KVM_GET_ONE_REG, &one_reg); > +} > + > static uint32_t kvm_arm_sve_get_vls(int fd) > { > uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; > @@ -286,6 +313,7 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) > bool pmu_supported = false; > uint64_t features = 0; > int err; > + int i; nit: you can declare it directly with the for (int i = 0 > > ahcf->target = QEMU_KVM_ARM_TARGET_NONE; > ahcf->dtb_compatible = "arm,armv8"; > @@ -454,6 +482,10 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) > /* Read the set of supported vector lengths. */ > arm_host_cpu_features.sve_vq_supported = kvm_arm_sve_get_vls(fd); > } > + /* Grab demuxed registers. */ > + for (i = 0; i < CSSELR_MAX; i++) { > + err |= get_host_cpu_reg_demux(fd, ahcf, CCSIDR_EL1_IDX, i); > + } > } > > kvm_arm_destroy_scratch_host_vcpu(fdarray); Thanks Eric ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-06-30 13:50 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-06-22 13:56 [PATCH v3 0/3] arm: demuxed ID registers (CCSIDR_EL1) Sebastian Ott 2026-06-22 13:56 ` [PATCH v3 1/3] arm: handle demuxed ID registers Sebastian Ott 2026-06-29 14:33 ` Eric Auger 2026-06-22 13:56 ` [PATCH v3 2/3] arm: handle CCSIDR_EL1 as a demuxed register Sebastian Ott 2026-06-29 15:23 ` Eric Auger 2026-06-30 13:49 ` Cornelia Huck 2026-06-22 13:56 ` [PATCH v3 3/3] arm/kvm: get demuxed ID registers from kvm Sebastian Ott 2026-06-29 15:28 ` Eric Auger
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