From: Alistair Francis <alistair23@gmail.com>
To: Anup Patel <anup@brainfault.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Frank Chang <frank.chang@sifive.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
Date: Fri, 21 Jan 2022 09:59:07 +1000 [thread overview]
Message-ID: <CAKmqyKNBnRxkFRBBSdS0oeSwNU_uw1hW29Eo7VVT=3og=gT-dw@mail.gmail.com> (raw)
In-Reply-To: <20220119152614.27548-15-anup@brainfault.org>
On Thu, Jan 20, 2022 at 2:32 AM Anup Patel <anup@brainfault.org> wrote:
>
> From: Anup Patel <anup.patel@wdc.com>
>
> The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
> which allow indirect access to interrupt priority arrays and per-HART
> IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Signed-off-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 7 ++
> target/riscv/csr.c | 175 +++++++++++++++++++++++++++++++++++++++++
> target/riscv/machine.c | 3 +
> 3 files changed, 185 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 65ffd31801..058ea9ce99 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -195,6 +195,10 @@ struct CPURISCVState {
> uint8_t miprio[64];
> uint8_t siprio[64];
>
> + /* AIA CSRs */
> + target_ulong miselect;
> + target_ulong siselect;
> +
> /* Hypervisor CSRs */
> target_ulong hstatus;
> target_ulong hedeleg;
> @@ -228,6 +232,9 @@ struct CPURISCVState {
> target_ulong vstval;
> target_ulong vsatp;
>
> + /* AIA VS-mode CSRs */
> + target_ulong vsiselect;
> +
> target_ulong mtval2;
> target_ulong mtinst;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index f7904c003f..e40620f455 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -916,6 +916,169 @@ static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
> return RISCV_EXCP_NONE;
> }
>
> +static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
> +{
> + if (!riscv_cpu_virt_enabled(env)) {
> + return csrno;
> + }
> +
> + switch (csrno) {
> + case CSR_SISELECT:
> + return CSR_VSISELECT;
> + case CSR_SIREG:
> + return CSR_VSIREG;
> + default:
> + return csrno;
> + };
> +}
> +
> +static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + target_ulong *iselect;
> +
> + /* Translate CSR number for VS-mode */
> + csrno = aia_xlate_vs_csrno(env, csrno);
> +
> + /* Find the iselect CSR based on CSR number */
> + switch (csrno) {
> + case CSR_MISELECT:
> + iselect = &env->miselect;
> + break;
> + case CSR_SISELECT:
> + iselect = &env->siselect;
> + break;
> + case CSR_VSISELECT:
> + iselect = &env->vsiselect;
> + break;
> + default:
> + return RISCV_EXCP_ILLEGAL_INST;
> + };
> +
> + if (val) {
> + *val = *iselect;
> + }
> +
> + wr_mask &= ISELECT_MASK;
> + if (wr_mask) {
> + *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
> + }
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> +static int rmw_iprio(target_ulong xlen,
> + target_ulong iselect, uint8_t *iprio,
> + target_ulong *val, target_ulong new_val,
> + target_ulong wr_mask, int ext_irq_no)
> +{
> + int i, firq, nirqs;
> + target_ulong old_val;
> +
> + if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
> + return -EINVAL;
> + }
> + if (xlen != 32 && iselect & 0x1) {
> + return -EINVAL;
> + }
> +
> + nirqs = 4 * (xlen / 32);
> + firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs);
> +
> + old_val = 0;
> + for (i = 0; i < nirqs; i++) {
> + old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i);
> + }
> +
> + if (val) {
> + *val = old_val;
> + }
> +
> + if (wr_mask) {
> + new_val = (old_val & ~wr_mask) | (new_val & wr_mask);
> + for (i = 0; i < nirqs; i++) {
> + /*
> + * M-level and S-level external IRQ priority always read-only
> + * zero. This means default priority order is always preferred
> + * for M-level and S-level external IRQs.
> + */
> + if ((firq + i) == ext_irq_no) {
> + continue;
> + }
> + iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
> + target_ulong new_val, target_ulong wr_mask)
> +{
> + bool virt;
> + uint8_t *iprio;
> + int ret = -EINVAL;
> + target_ulong priv, isel, vgein;
> +
> + /* Translate CSR number for VS-mode */
> + csrno = aia_xlate_vs_csrno(env, csrno);
> +
> + /* Decode register details from CSR number */
> + virt = false;
> + switch (csrno) {
> + case CSR_MIREG:
> + iprio = env->miprio;
> + isel = env->miselect;
> + priv = PRV_M;
> + break;
> + case CSR_SIREG:
> + iprio = env->siprio;
> + isel = env->siselect;
> + priv = PRV_S;
> + break;
> + case CSR_VSIREG:
> + iprio = env->hviprio;
> + isel = env->vsiselect;
> + priv = PRV_S;
> + virt = true;
> + break;
> + default:
> + goto done;
> + };
> +
> + /* Find the selected guest interrupt file */
> + vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
> +
> + if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) {
> + /* Local interrupt priority registers not available for VS-mode */
> + if (!virt) {
> + ret = rmw_iprio(riscv_cpu_mxl_bits(env),
> + isel, iprio, val, new_val, wr_mask,
> + (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT);
> + }
> + } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) {
> + /* IMSIC registers only available when machine implements it. */
> + if (env->aia_ireg_rmw_fn[priv]) {
> + /* Selected guest interrupt file should not be zero */
> + if (virt && (!vgein || env->geilen < vgein)) {
> + goto done;
> + }
> + /* Call machine specific IMSIC register emulation */
> + ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
> + AIA_MAKE_IREG(isel, priv, virt, vgein,
> + riscv_cpu_mxl_bits(env)),
> + val, new_val, wr_mask);
> + }
> + }
> +
> +done:
> + if (ret) {
> + return (riscv_cpu_virt_enabled(env) && virt) ?
> + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
> + }
> + return RISCV_EXCP_NONE;
> +}
> +
> static RISCVException read_mtvec(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> @@ -2690,6 +2853,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
> [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
>
> + /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
> + [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect },
> + [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg },
> +
> /* Machine-Level Interrupts (AIA) */
> [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
>
> @@ -2722,6 +2889,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> /* Supervisor Protection and Translation */
> [CSR_SATP] = { "satp", smode, read_satp, write_satp },
>
> + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
> + [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect },
> + [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg },
> +
> /* Supervisor-Level Interrupts (AIA) */
> [CSR_STOPI] = { "stopi", aia_smode, read_stopi },
>
> @@ -2763,6 +2934,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
> [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
>
> + /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
> + [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect },
> + [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg },
> +
> /* VS-Level Interrupts (H-extension with AIA) */
> [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index c6a01ba953..9895930b29 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -103,6 +103,7 @@ static const VMStateDescription vmstate_hyper = {
> VMSTATE_UINTTL(env.vscause, RISCVCPU),
> VMSTATE_UINTTL(env.vstval, RISCVCPU),
> VMSTATE_UINTTL(env.vsatp, RISCVCPU),
> + VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
>
> VMSTATE_UINTTL(env.mtval2, RISCVCPU),
> VMSTATE_UINTTL(env.mtinst, RISCVCPU),
> @@ -260,6 +261,8 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.mepc, RISCVCPU),
> VMSTATE_UINTTL(env.mcause, RISCVCPU),
> VMSTATE_UINTTL(env.mtval, RISCVCPU),
> + VMSTATE_UINTTL(env.miselect, RISCVCPU),
> + VMSTATE_UINTTL(env.siselect, RISCVCPU),
> VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2022-01-21 0:04 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-19 15:25 [PATCH v8 00/23] QEMU RISC-V AIA support Anup Patel
2022-01-19 15:25 ` [PATCH v8 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2022-01-19 15:25 ` [PATCH v8 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2022-01-19 15:25 ` [PATCH v8 03/23] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2022-01-19 15:25 ` [PATCH v8 04/23] target/riscv: Improve delivery of guest external interrupts Anup Patel
2022-01-19 15:25 ` [PATCH v8 05/23] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2022-01-19 15:25 ` [PATCH v8 06/23] target/riscv: Add AIA cpu feature Anup Patel
2022-01-19 15:25 ` [PATCH v8 07/23] target/riscv: Add defines for AIA CSRs Anup Patel
2022-01-19 15:25 ` [PATCH v8 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2022-01-19 15:26 ` [PATCH v8 09/23] target/riscv: Implement AIA local interrupt priorities Anup Patel
2022-01-20 7:52 ` Frank Chang
2022-01-19 15:26 ` [PATCH v8 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2022-01-19 15:26 ` [PATCH v8 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2022-01-19 15:26 ` [PATCH v8 12/23] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2022-01-19 15:26 ` [PATCH v8 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2022-01-20 23:55 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2022-01-20 23:59 ` Alistair Francis [this message]
2022-01-19 15:26 ` [PATCH v8 15/23] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2022-01-19 15:26 ` [PATCH v8 16/23] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2022-01-19 15:26 ` [PATCH v8 17/23] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2022-01-19 15:26 ` [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2022-01-19 15:37 ` Frank Chang
2022-01-19 16:20 ` Anup Patel
2022-01-20 8:19 ` Frank Chang
2022-01-20 12:05 ` Anup Patel
2022-01-20 13:25 ` Frank Chang
2022-01-19 15:26 ` [PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2022-01-24 21:35 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2022-01-28 1:54 ` Alistair Francis
2022-01-28 3:50 ` Anup Patel
2022-01-19 15:26 ` [PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2022-01-28 1:50 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 22/23] docs/system: riscv: Document AIA options for " Anup Patel
2022-01-19 15:26 ` [PATCH v8 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs Anup Patel
2022-01-20 12:11 ` [PATCH v8 00/23] QEMU RISC-V AIA support Anup Patel
2022-01-21 6:16 ` Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAKmqyKNBnRxkFRBBSdS0oeSwNU_uw1hW29Eo7VVT=3og=gT-dw@mail.gmail.com' \
--to=alistair23@gmail.com \
--cc=Alistair.Francis@wdc.com \
--cc=anup@brainfault.org \
--cc=atishp@atishpatra.org \
--cc=bmeng.cn@gmail.com \
--cc=frank.chang@sifive.com \
--cc=palmer@dabbelt.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).