messages from 2022-01-18 01:46:59 to 2022-01-21 00:04:07 UTC [more...]
[PATCH v8 00/23] Support UXL filed in xstatus
2022-01-21 0:03 UTC (26+ messages)
` [PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl
` [PATCH v8 02/23] target/riscv: Don't save pc when exception return
` [PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr
` [PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN
` [PATCH v8 05/23] target/riscv: Create xl field in env
` [PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN
` [PATCH v8 07/23] target/riscv: Extend pc for runtime pc write
` [PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen
` [PATCH v8 09/23] target/riscv: Relax debug check for pm write
` [PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN
` [PATCH v8 11/23] target/riscv: Create current pm fields in env
` [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base]
` [PATCH v8 13/23] target/riscv: Calculate address according to XLEN
` [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base
` [PATCH v8 15/23] target/riscv: Split out the vill from vtype
` [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN
` [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE
` [PATCH v8 18/23] target/riscv: Fix check range for first fault only
` [PATCH v8 19/23] target/riscv: Adjust vector address with mask
` [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN
` [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor
` [PATCH v8 22/23] target/riscv: Enable uxl field write
` [PATCH v8 23/23] target/riscv: Relax UXL field for debugging
[PATCH v8 00/23] QEMU RISC-V AIA support
2022-01-20 23:59 UTC (33+ messages)
` [PATCH v8 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
` [PATCH v8 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs
` [PATCH v8 03/23] target/riscv: Implement hgeie and hgeip CSRs
` [PATCH v8 04/23] target/riscv: Improve delivery of guest external interrupts
` [PATCH v8 05/23] target/riscv: Allow setting CPU feature from machine/device emulation
` [PATCH v8 06/23] target/riscv: Add AIA cpu feature
` [PATCH v8 07/23] target/riscv: Add defines for AIA CSRs
` [PATCH v8 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
` [PATCH v8 09/23] target/riscv: Implement AIA local interrupt priorities
` [PATCH v8 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
` [PATCH v8 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
` [PATCH v8 12/23] target/riscv: Implement AIA interrupt filtering CSRs
` [PATCH v8 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
` [PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
` [PATCH v8 15/23] target/riscv: Implement AIA IMSIC interface CSRs
` [PATCH v8 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
` [PATCH v8 17/23] target/riscv: Allow users to force enable AIA CSRs in HART
` [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
` [PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
` [PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
` [PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
` [PATCH v8 22/23] docs/system: riscv: Document AIA options for "
` [PATCH v8 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
[PATCH v5 0/5] support subsets of virtual memory extension
2022-01-20 22:28 UTC (24+ messages)
` [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
` [PATCH v5 3/5] target/riscv: add support for svnapot extension
` [PATCH v5 5/5] target/riscv: add support for svpbmt extension
[PATCH v3 0/3] Improve RISC-V spike machine bios support
2022-01-20 21:23 UTC (5+ messages)
` [PATCH v3 1/3] hw/riscv: spike: Allow using binary firmware as bios
` [PATCH v3 2/3] hw/riscv: Remove macros for ELF BIOS image names
` [PATCH v3 3/3] roms/opensbi: Remove ELF images
[RFC 0/5] Privilege version update
2022-01-20 20:07 UTC (6+ messages)
` [RFC 1/5] target/riscv: Add the privileged spec version 1.12.0
` [RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops
` [RFC 3/5] target/riscv: Add support for mconfigptr
` [RFC 4/5] target/riscv: Add *envcfg* CSRs support
` [RFC 5/5] target/riscv: Enable privileged spec version 1.12
[PATCH v2 1/2] target/riscv: iterate over a table of decoders
2022-01-20 20:05 UTC (11+ messages)
` [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
[RESEND] target/riscv: fix RV128 lq encoding
2022-01-20 10:57 UTC (4+ messages)
[PATCH v2 0/3] Improve RISC-V spike machine bios support
2022-01-20 10:38 UTC (11+ messages)
` [PATCH v2 1/3] hw/riscv: spike: Allow using binary firmware as bios
` [PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names
` [PATCH v2 3/3] roms/opensbi: Remove ELF images
[PATCH v7 00/22] Support UXL filed in xstatus
2022-01-20 5:15 UTC (28+ messages)
` [PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl
` [PATCH v7 02/22] target/riscv: Don't save pc when exception return
` [PATCH v7 03/22] target/riscv: Sign extend link reg for jal and jalr
` [PATCH v7 04/22] target/riscv: Sign extend pc for different XLEN
` [PATCH v7 05/22] target/riscv: Create xl field in env
` [PATCH v7 06/22] target/riscv: Ignore the pc bits above XLEN
` [PATCH v7 07/22] target/riscv: Extend pc for runtime pc write
` [PATCH v7 08/22] target/riscv: Use gdb xml according to max mxlen
` [PATCH v7 09/22] target/riscv: Relax debug check for pm write
` [PATCH v7 10/22] target/riscv: Adjust csr write mask with XLEN
` [PATCH v7 11/22] target/riscv: Create current pm fields in env
` [PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base]
` [PATCH v7 13/22] target/riscv: Calculate address according to XLEN
` [PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base
` [PATCH v7 15/22] target/riscv: Split out the vill from vtype
` [PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN
` [PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE
` [PATCH v7 18/22] target/riscv: Fix check range for first fault only
` [PATCH v7 19/22] target/riscv: Adjust vector address with mask
` [PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN
` [PATCH v7 21/22] target/riscv: Enable uxl field write
` [PATCH v7 22/22] target/riscv: Relax UXL field for debugging
[RFC PATCH v5 00/14] support subsets of scalar crypto extension
2022-01-19 11:37 UTC (15+ messages)
` [RFC PATCH v5 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*
` [RFC PATCH v5 02/14] target/riscv: rvk: add support for zbkb extension
` [RFC PATCH v5 03/14] target/riscv: rvk: add support for zbkc extension
` [RFC PATCH v5 04/14] target/riscv: rvk: add support for zbkx extension
` [RFC PATCH v5 05/14] crypto: move sm4_sbox from target/arm
` [RFC PATCH v5 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32
` [RFC PATCH v5 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64
` [RFC PATCH v5 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension
` [RFC PATCH v5 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 "
` [RFC PATCH v5 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 "
` [RFC PATCH v5 11/14] target/riscv: rvk: add support for zksed/zksh extension
` [RFC PATCH v5 12/14] target/riscv: rvk: add CSR support for Zkr
` [RFC PATCH v5 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
` [RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties
[PATCH v6 00/22] Support UXL filed in xstatus
2022-01-19 3:43 UTC (13+ messages)
` [PATCH v6 01/22] target/riscv: Adjust pmpcfg access with mxl
` [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr
` [PATCH v6 05/22] target/riscv: Create xl field in env
` [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN
` [PATCH v6 22/22] target/riscv: Relax UXL field for debugging
[RESEND PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
2022-01-19 3:15 UTC (5+ messages)
` [RESEND PATCH v3 1/7] target/riscv: Add initial support for native debug
` [RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write
[PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions
2022-01-18 22:25 UTC (9+ messages)
` [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
` [PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
` [PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
` [PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
` [PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing "
` [PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
[RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
2022-01-18 20:31 UTC (2+ messages)
[PATCH] target/riscv: fix RV128 lq encoding
2022-01-18 16:07 UTC (2+ messages)
[PATCH] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
2022-01-18 16:21 UTC (2+ messages)
[PATCH v4 0/7] support subsets of scalar crypto extension
2022-01-18 8:24 UTC (15+ messages)
` [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
` [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
` [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
` [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
[PATCH v7 00/23] QEMU RISC-V AIA support
2022-01-18 7:43 UTC (11+ messages)
` [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities
` [PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs
` [PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
` [PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC "
[PATCH] hw/riscv: spike: Allow using binary firmware as bios
2022-01-18 7:39 UTC (5+ messages)
[PATCH] target/riscv: Ignore reserved bits in PTE for RV64
2022-01-18 4:51 UTC (2+ messages)
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