messages from 2022-01-21 00:04:07 to 2022-02-16 15:48:56 UTC [more...]
[PATCH v4 0/2] riscv: Add support for Zicbo[m,z,p] instructions
2022-02-16 15:48 UTC (2+ messages)
` [PATCH v4 1/2] accel/tcg: Add probe_access_range_flags interface
[PATCH v3] target/riscv: Enable Zicbo[m,z,p] instructions
2022-02-16 13:51 UTC (5+ messages)
[PATCH v2] target/riscv: Add isa extenstion strings to the device tree
2022-02-16 11:42 UTC (3+ messages)
[PATCH v1] hw: riscv: opentitan: fixup SPI addresses
2022-02-16 7:39 UTC (3+ messages)
[PATCH] target/riscv: Add isa extenstion strings to the device tree
2022-02-15 21:20 UTC (5+ messages)
[PATCH 0/1] target/riscv: misa to ISA string conversion fix
2022-02-12 11:14 UTC (2+ messages)
` [PATCH 1/1] "
[RESEND PATCH 0/1] target/riscv: misa to ISA string conversion fix
2022-02-12 11:59 UTC (2+ messages)
` [RESEND PATCH 1/1] "
[PATCH v9 00/23] QEMU RISC-V AIA support
2022-02-11 8:28 UTC (30+ messages)
` [PATCH v9 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
` [PATCH v9 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs
` [PATCH v9 03/23] target/riscv: Implement hgeie and hgeip CSRs
` [PATCH v9 04/23] target/riscv: Improve delivery of guest external interrupts
` [PATCH v9 05/23] target/riscv: Allow setting CPU feature from machine/device emulation
` [PATCH v9 06/23] target/riscv: Add AIA cpu feature
` [PATCH v9 07/23] target/riscv: Add defines for AIA CSRs
` [PATCH v9 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
` [PATCH v9 09/23] target/riscv: Implement AIA local interrupt priorities
` [PATCH v9 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
` [PATCH v9 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
` [PATCH v9 12/23] target/riscv: Implement AIA interrupt filtering CSRs
` [PATCH v9 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
` [PATCH v9 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
` [PATCH v9 15/23] target/riscv: Implement AIA IMSIC interface CSRs
` [PATCH v9 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
` [PATCH v9 17/23] target/riscv: Allow users to force enable AIA CSRs in HART
` [PATCH v9 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
` [PATCH v9 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
` [PATCH v9 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
` [PATCH v9 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
` [PATCH v9 22/23] docs/system: riscv: Document AIA options for "
` [PATCH v9 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
[PATCH v6 0/6] support subsets of Float-Point in Integer Registers extensions
2022-02-11 4:39 UTC (7+ messages)
` [PATCH v6 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
` [PATCH v6 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
` [PATCH v6 3/6] target/riscv: add support for zfinx
` [PATCH v6 4/6] target/riscv: add support for zdinx
` [PATCH v6 5/6] target/riscv: add support for zhinx/zhinxmin
` [PATCH v6 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
[RFC PATCH v2 0/3] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses
2022-02-10 6:17 UTC (4+ messages)
` [RFC PATCH v2 1/3] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
` [RFC PATCH v2 2/3] hw/intc: Support 32/64-bit mtimecmp and mtime accesses "
` [RFC PATCH v2 3/3] hw/intc: Make RISC-V ACLINT mtime MMIO register writable
[PATCH] docs/system: riscv: Update description of CPU
2022-02-10 3:10 UTC (3+ messages)
[PATCH v9 0/5] support subsets of virtual memory extension
2022-02-10 3:07 UTC (7+ messages)
` [PATCH v9 1/5] target/riscv: Ignore reserved bits in PTE for RV64
` [PATCH v9 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
` [PATCH v9 3/5] target/riscv: add support for svnapot extension
` [PATCH v9 4/5] target/riscv: add support for svinval extension
` [PATCH v9 5/5] target/riscv: add support for svpbmt extension
[PATCH] target/riscv: Call probe_write() before atomic operations
2022-02-09 7:26 UTC (2+ messages)
[RFC PATCH] hw/intc: Make RISC-V ACLINT mtime MMIO register writable
2022-02-09 2:36 UTC (3+ messages)
[PATCH] build: fix build failure with gcc 11.2 by disabling -fcf-protection
2022-02-08 21:19 UTC
[PATCH v3 0/6] Privilege version update
2022-02-06 9:18 UTC (7+ messages)
` [PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering
` [PATCH v3 2/6] target/riscv: Add the privileged spec version 1.12.0
` [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops
` [PATCH v3 4/6] target/riscv: Add support for mconfigptr
` [PATCH v3 5/6] target/riscv: Add *envcfg* CSRs support
` [PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12
[PATCH v2 0/6] Privilege version update
2022-02-05 11:26 UTC (9+ messages)
` [PATCH v2 1/6] target/riscv: Define simpler privileged spec version numbering
` [PATCH v2 2/6] target/riscv: Add the privileged spec version 1.12.0
` [PATCH v2 3/6] target/riscv: Introduce privilege version field in the CSR ops
` [PATCH v2 4/6] target/riscv: Add support for mconfigptr
` [PATCH v2 5/6] target/riscv: Add *envcfg* CSRs support
` [PATCH v2 6/6] target/riscv: Enable privileged spec version 1.12
[PATCH 0/2] RISC-V: Correctly generate store/amo faults
2022-02-04 20:33 UTC (11+ messages)
` [PATCH 1/2] accel: tcg: Allow forcing a store fault on read ops
` [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault
[RFC 0/5] Privilege version update
2022-02-03 20:39 UTC (17+ messages)
` [RFC 1/5] target/riscv: Add the privileged spec version 1.12.0
` [RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops
` [RFC 4/5] target/riscv: Add *envcfg* CSRs support
` [RFC 5/5] target/riscv: Enable privileged spec version 1.12
[PATCH v8 0/5] support subsets of virtual memory extension
2022-02-03 2:45 UTC (10+ messages)
` [PATCH v8 1/5] target/riscv: Ignore reserved bits in PTE for RV64
` [PATCH v8 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
` [PATCH v8 3/5] target/riscv: add support for svnapot extension
` [PATCH v8 4/5] target/riscv: add support for svinval extension
` [PATCH v8 5/5] target/riscv: add support for svpbmt extension
[PATCH] target/riscv: Fix vill field write in vtype
2022-02-02 6:38 UTC (3+ messages)
[PATCH v7 0/5] support subsets of virtual memory extension
2022-02-01 12:55 UTC (11+ messages)
` [PATCH v7 1/5] target/riscv: Ignore reserved bits in PTE for RV64
` [PATCH v7 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
` [PATCH v7 3/5] target/riscv: add support for svnapot extension
` [PATCH v7 4/5] target/riscv: add support for svinval extension
` [PATCH v7 5/5] target/riscv: add support for svpbmt extension
[PATCH v5 0/6] support subsets of Float-Point in Integer Registers extensions
2022-01-28 13:16 UTC (7+ messages)
` [PATCH v5 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
` [PATCH v5 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
` [PATCH v5 3/6] target/riscv: add support for zfinx
` [PATCH v5 4/6] target/riscv: add support for zdinx
` [PATCH v5 5/6] target/riscv: add support for zhinx/zhinxmin
` [PATCH v5 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
[PATCH v6 0/5] support subsets of virtual memory extension
2022-01-28 7:37 UTC (15+ messages)
` [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
` [PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
` [PATCH v6 3/5] target/riscv: add support for svnapot extension
` [PATCH v6 4/5] target/riscv: add support for svinval extension
` [PATCH v6 5/5] target/riscv: add support for svpbmt extension
[PATCH v4 0/6] support subsets of Float-Point in Integer Registers extensions
2022-01-28 7:36 UTC (10+ messages)
` [PATCH v4 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
` [PATCH v4 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
` [PATCH v4 3/6] target/riscv: add support for zfinx
` [PATCH v4 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
[PATCH] target/riscv: correct "code should not be reached" for x-rv128
2022-01-28 5:19 UTC (4+ messages)
[PATCH v8 00/23] QEMU RISC-V AIA support
2022-01-28 3:50 UTC (10+ messages)
` [PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
` [PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
` [PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
[PATCH v2] target/riscv: correct "code should not be reached" for x-rv128
2022-01-28 1:55 UTC (4+ messages)
[PATCH v2] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
2022-01-26 8:08 UTC (3+ messages)
[PATCH v2 1/2] target/riscv: iterate over a table of decoders
2022-01-25 21:42 UTC (10+ messages)
` [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
[PATCH v1] include: hw: remove ibex_plic.h
2022-01-23 23:28 UTC (4+ messages)
[RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
2022-01-22 3:30 UTC (4+ messages)
[RFC PATCH v5 00/14] support subsets of scalar crypto extension
2022-01-21 8:15 UTC (8+ messages)
` [RFC PATCH v5 02/14] target/riscv: rvk: add support for zbkb extension
` [RFC PATCH v5 03/14] target/riscv: rvk: add support for zbkc extension
` [RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties
[PATCH v5 0/5] support subsets of virtual memory extension
2022-01-21 2:08 UTC (8+ messages)
` [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
[PATCH v8 00/23] Support UXL filed in xstatus
2022-01-21 0:03 UTC (2+ messages)
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).