From: "Doru Blânzeanu" <dblanzeanu@linux.microsoft.com>
To: Magnus Kulke <magnuskulke@linux.microsoft.com>
Cc: qemu-devel@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Magnus Kulke" <magnuskulke@microsoft.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Wei Liu" <wei.liu@kernel.org>,
"Doru Blânzeanu" <doru.blanzeanu@microsoft.com>,
"Wei Liu" <liuwe@microsoft.com>
Subject: Re: [PATCH 06/12] target/i386/mshv: migrate Synic SINT MSRs
Date: Wed, 22 Jul 2026 17:03:22 +0300 [thread overview]
Message-ID: <amDNqvZ37qZX5Yd1@linux.microsoft.com> (raw)
In-Reply-To: <20260710101534.664604-7-magnuskulke@linux.microsoft.com>
On Fri, Jul 10, 2026 at 12:15:28PM +0200, Magnus Kulke wrote:
> Migrate HyperV SynIC SINT MSRs. We can only read/write those if SCONTROL
> is enabled in the guest, hence we have to split the SINT MSR out and
> make reading/writing them dependent on that MSR.
>
> Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
> ---
> target/i386/mshv/msr.c | 41 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/target/i386/mshv/msr.c b/target/i386/mshv/msr.c
> index a5f639c3ca..5288e32b6d 100644
> --- a/target/i386/mshv/msr.c
> +++ b/target/i386/mshv/msr.c
> @@ -331,6 +331,8 @@ int mshv_get_msrs(CPUState *cpu)
> struct hv_register_assoc assocs[MSHV_MSR_TOTAL_COUNT];
> size_t i, j;
> uint32_t name;
> + X86CPU *x86cpu = X86_CPU(cpu);
> + bool synic_enabled;
>
> set_hv_name_in_assocs(assocs, n_assocs);
>
> @@ -357,6 +359,27 @@ int mshv_get_msrs(CPUState *cpu)
>
> store_in_env(cpu, assocs, n_assocs);
>
> + /* Read SINT MSRs only if SynIC is enabled */
> + synic_enabled = x86cpu->env.msr_hv_synic_control & 1;
> + if (synic_enabled) {
> + QEMU_BUILD_BUG_ON(MSHV_MSR_TOTAL_COUNT < HV_SINT_COUNT);
> +
> + for (i = 0; i < HV_SINT_COUNT; i++) {
> + assocs[i].name = HV_REGISTER_SINT0 + i;
> + }
> +
> + ret = mshv_get_generic_regs(cpu, assocs, HV_SINT_COUNT);
> + if (ret < 0) {
> + error_report("Failed to get SynIC SINT MSRs");
> + return -errno;
> + }
> +
> + for (i = 0; i < HV_SINT_COUNT; i++) {
> + uint64_t hv_sint_value = assocs[i].value.reg64;
> + x86cpu->env.msr_hv_synic_sint[i] = hv_sint_value;
> + }
> + }
> +
> return 0;
> }
>
> @@ -391,6 +414,8 @@ int mshv_set_msrs(const CPUState *cpu)
> struct hv_register_assoc assocs[MSHV_MSR_TOTAL_COUNT];
> int ret;
> size_t i, j;
> + X86CPU *x86cpu = X86_CPU(cpu);
> + bool synic_enabled = x86cpu->env.msr_hv_synic_control & 1;
>
> load_from_env(cpu, assocs, n_assocs);
>
> @@ -423,5 +448,21 @@ int mshv_set_msrs(const CPUState *cpu)
> return -errno;
> }
>
> + /* SINT MSRs can only be written if SCONTROL has been set, so we split */
> + if (synic_enabled) {
> + QEMU_BUILD_BUG_ON(MSHV_MSR_TOTAL_COUNT < HV_SINT_COUNT);
> +
> + for (i = 0; i < HV_SINT_COUNT; i++) {
> + assocs[i].name = HV_REGISTER_SINT0 + i;
> + assocs[i].value.reg64 = x86cpu->env.msr_hv_synic_sint[i];
> + }
> +
> + ret = mshv_set_generic_regs(cpu, assocs, HV_SINT_COUNT);
> + if (ret < 0) {
> + error_report("Failed to set SynIC SINT MSRs");
> + return -errno;
> + }
> + }
> +
> return 0;
> }
> --
> 2.34.1
Reviewed-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
next prev parent reply other threads:[~2026-07-22 14:03 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-10 10:15 [PATCH 00/12] Add migration support to MSHV accelerator, Part 2 Magnus Kulke
2026-07-10 10:15 ` [PATCH 01/12] target/i386/mshv: disable AMX TILE features Magnus Kulke
2026-07-16 11:06 ` Doru Blânzeanu
2026-07-10 10:15 ` [PATCH 02/12] accel/mshv: introduce SaveVMHandler Magnus Kulke
2026-07-16 11:10 ` Doru Blânzeanu
2026-07-10 10:15 ` [PATCH 03/12] hw/i386/mshv: migrate REFERENCE_TIME Magnus Kulke
2026-07-16 12:01 ` Doru Blânzeanu
2026-07-10 10:15 ` [PATCH 04/12] accel/mshv: install dummy handler for SIG_IPI Magnus Kulke
2026-07-17 14:43 ` Doru Blânzeanu
2026-07-10 10:15 ` [PATCH 05/12] target/i386/mshv: migrate LAPIC state Magnus Kulke
2026-07-22 11:57 ` Doru Blânzeanu
2026-07-10 10:15 ` [PATCH 06/12] target/i386/mshv: migrate Synic SINT MSRs Magnus Kulke
2026-07-22 14:03 ` Doru Blânzeanu [this message]
2026-07-10 10:15 ` [PATCH 07/12] target/i386/mshv: migrate SIMP and SIEFP state Magnus Kulke
2026-07-22 14:12 ` Doru Blânzeanu
2026-07-10 10:15 ` [PATCH 08/12] target/i386/mshv: migrate STIMER state Magnus Kulke
2026-07-22 14:24 ` Doru Blânzeanu
2026-07-10 10:15 ` [PATCH 09/12] accel/mshv: write synthetic MSRs after migration Magnus Kulke
2026-07-10 10:15 ` [PATCH 10/12] target/i386/mshv: migrate MP_STATE Magnus Kulke
2026-07-10 10:15 ` [PATCH 11/12] target/i386/mshv: toggle fpu/xsave migration Magnus Kulke
2026-07-10 10:15 ` [PATCH 12/12] hw/i386/mshv: drop initial msi vector 0 Magnus Kulke
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