messages from 2020-02-07 14:23:51 to 2020-02-25 10:35:41 UTC [more...]
[PATCH v4 0/5] target/riscv: support vector extension part 2
2020-02-25 10:35 UTC (6+ messages)
` [PATCH v4 1/5] target/riscv: add vector unit stride load and store instructions
` [PATCH v4 2/5] target/riscv: add vector "
` [PATCH v4 3/5] target/riscv: add vector index "
` [PATCH v4 4/5] target/riscv: add fault-only-first unit stride load
` [PATCH v4 5/5] target/riscv: add vector amo operations
[PATCH RESEND v2 00/32] hw: Sanitize various MemoryRegion calls
2020-02-25 10:05 UTC (38+ messages)
` [PATCH RESEND v2 01/32] memory: Correctly return alias region type
` [PATCH RESEND v2 02/32] memory: Simplify memory_region_init_rom_nomigrate() to ease review
` [PATCH RESEND v2 03/32] scripts/cocci: Rename memory-region-{init-ram -> housekeeping}
` [PATCH RESEND v2 04/32] scripts/cocci: Patch to replace memory_region_init_{ram, readonly -> rom}
` [PATCH RESEND v2 05/32] hw/arm: Use memory_region_init_rom() with read-only regions
` [PATCH RESEND v2 06/32] hw/display: "
` [PATCH RESEND v2 07/32] hw/mips: "
` [PATCH RESEND v2 08/32] hw/m68k: "
` [PATCH RESEND v2 09/32] hw/net: "
` [PATCH RESEND v2 10/32] hw/pci-host: "
` [PATCH RESEND v2 11/32] hw/ppc: "
` [PATCH RESEND v2 12/32] hw/riscv: "
` [PATCH RESEND v2 13/32] hw/sh4: "
` [PATCH RESEND v2 14/32] hw/sparc: "
` [PATCH RESEND v2 15/32] scripts/cocci: Patch to detect potential use of memory_region_init_rom
` [PATCH RESEND v2 16/32] hw/arm/stm32: Use memory_region_init_rom() with read-only regions
` [PATCH RESEND v2 17/32] hw/ppc/ppc405: "
` [PATCH RESEND v2 18/32] hw/i386/pc_sysfw: Simplify using memory_region_init_alias()
` [PATCH RESEND v2 19/32] hw/i386/pc_sysfw: Remove unused 'ram_size' argument
` [PATCH RESEND v2 20/32] scripts/cocci: Patch to remove unnecessary memory_region_set_readonly()
` [PATCH RESEND v2 21/32] hw/arm: Remove unnecessary memory_region_set_readonly() on ROM alias
` [PATCH RESEND v2 22/32] scripts/cocci: Patch to let devices own their MemoryRegions
` [PATCH RESEND v2 23/32] hw/arm: Let devices own the MemoryRegion they create
` [PATCH RESEND v2 24/32] hw/char: "
` [PATCH RESEND v2 25/32] hw/core: "
` [PATCH RESEND v2 26/32] hw/display: "
` [PATCH RESEND v2 27/32] hw/dma: "
` [PATCH RESEND v2 28/32] hw/riscv: "
` [PATCH RESEND v2 29/32] hw/input/milkymist-softusb: Remove unused 'pmem_ptr' field
` [RFC PATCH RESEND v2 30/32] hw/input/milkymist-softusb: Let devices own the MemoryRegion they create
` [RFC PATCH RESEND v2 31/32] hw/net/milkymist-minimac2: "
` [RFC PATCH RESEND v2 32/32] hw/block/onenand: "
[PATCH v2 00/32] hw: Sanitize various MemoryRegion uses
2020-02-25 10:02 UTC (12+ messages)
` [PATCH v2 01/32] memory: Correctly return alias region type
` [PATCH v2 02/32] memory: Simplify memory_region_init_rom_nomigrate() to ease review
` [PATCH v2 03/32] scripts/cocci: Rename memory-region-{init-ram -> housekeeping}
` [PATCH v2 04/32] scripts/cocci: Patch to replace memory_region_init_{ram, readonly -> rom}
` [PATCH v2 05/32] hw/arm: Use memory_region_init_rom() with read-only regions
` [PATCH v2 06/32] hw/display: "
` [PATCH v2 07/32] hw/mips: "
` [PATCH v2 08/32] hw/m68k: "
[PATCH v2] riscv: sifive_u: Add a "serial" property for board serial number
2020-02-25 5:02 UTC (4+ messages)
[PATCH v2 0/2] linux-user: generate syscall_nr.sh for RISC-V
2020-02-24 23:21 UTC (3+ messages)
` [PATCH v2 1/2] linux-user: Protect more syscalls
` [PATCH v2 2/2] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel
[PATCH v1 0/2] linux-user: generate syscall_nr.sh for RISC-V
2020-02-24 19:30 UTC (7+ messages)
` [PATCH v1 1/2] linux-user: Protect more syscalls
` [PATCH v1 2/2] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel
[PATCH v2 0/4] riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image
2020-02-24 19:15 UTC (8+ messages)
` [PATCH v2 1/4] roms: opensbi: Upgrade from v0.5 to v0.6
` [PATCH v2 2/4] roms: opensbi: Add 32-bit firmware image for sifive_u machine
` [PATCH v2 3/4] riscv: sifive_u: Update BIOS_FILENAME for 32-bit
` [PATCH v2 4/4] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries
[PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding
2020-02-24 18:59 UTC (7+ messages)
[PATCH v3 0/3] Make MachineClass::is_default boolean, refuse multiple default machines
2020-02-23 9:04 UTC (7+ messages)
` [PATCH v3 2/3] hw: Make MachineClass::is_default a boolean type
[PATCH 1/2] riscv: roms: Add 32-bit OpenSBI firmware image for sifive_u
2020-02-22 14:53 UTC (10+ messages)
` [PATCH 2/2] riscv: sifive_u: Update BIOS_FILENAME for 32-bit
[PATCH 0/3] RISC-V Spike machine improvements
2020-02-21 19:49 UTC (7+ messages)
` [PATCH 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
` [PATCH 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option
` [PATCH 3/3] hw/riscv/spike: Allow more than one CPUs
[PATCH 0/7] hw: Let devices own the MemoryRegion they create
2020-02-21 17:36 UTC (9+ messages)
` [PATCH 1/7] scripts/coccinelle: Add a script to let devices own their MemoryRegions
` [PATCH 2/7] hw/arm: Let devices own the MemoryRegion they create
` [PATCH 3/7] hw/char: "
` [PATCH 4/7] hw/core: "
` [PATCH 5/7] hw/display: "
` [PATCH 6/7] hw/dma: "
` [PATCH 7/7] hw/riscv: "
[PATCH v5 0/4] target-riscv: support vector extension part 1
2020-02-21 9:45 UTC (5+ messages)
` [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState
` [PATCH v5 2/4] target/riscv: implementation-defined constant parameters
` [PATCH v5 3/4] target/riscv: support vector extension csr
` [PATCH v5 4/4] target/riscv: add vector configure instruction
[PATCH v1 1/1] target/riscv: Correctly implement TSR trap
2020-02-20 18:41 UTC (2+ messages)
about qemu display
2020-02-20 7:31 UTC
about qemu display
2020-02-20 7:42 UTC
[PATCH v3 0/5] target/riscv: support vector extension part 2
2020-02-19 8:57 UTC (9+ messages)
` [PATCH v3 1/5] target/riscv: add vector unit stride load and store instructions
` [PATCH v3 2/5] target/riscv: add vector "
` [PATCH v3 3/5] target/riscv: add vector index "
` [PATCH v3 4/5] target/riscv: add fault-only-first unit stride load
` [PATCH v3 5/5] target/riscv: add vector amo operations
[PATCH v4 0/4]target-riscv: support vector extension part 1
2020-02-19 1:05 UTC (17+ messages)
` [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState
` [PATCH v4 2/4] target/riscv: configure and turn on vector extension from command line
` [PATCH v4 3/4] target/riscv: support vector extension csr
` [PATCH v4 4/4] target/riscv: add vector configure instruction
[PATCH v3 0/2] RISC-V TIME CSR for privileged mode
2020-02-18 19:08 UTC (2+ messages)
[PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5
2020-02-18 18:11 UTC (5+ messages)
[PATCH] riscv: virt: Allow PCI address 0
2020-02-18 16:30 UTC (2+ messages)
[PATCH v2 33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR
2020-02-17 19:04 UTC (2+ messages)
[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 2
2020-02-16 21:14 UTC (8+ messages)
` [PULL 1/5] riscv/virt: Add syscon reboot and poweroff DT nodes
` [PULL 2/5] riscv: Separate FPU register size from core register size in gdbstub [v2]
` [PULL 3/5] hw: rtc: Add Goldfish RTC device
` [PULL 4/5] riscv: virt: Use "
` [PULL 5/5] MAINTAINERS: Add maintainer entry for Goldfish RTC
[PATCH v2 14/19] target/riscv: progressively load the instruction during decode
2020-02-14 19:34 UTC (3+ messages)
[PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty
2020-02-13 18:44 UTC (2+ messages)
[PATCH v2 26/35] target/riscv: Disable guest FP support based on virtual status
2020-02-13 18:39 UTC (2+ messages)
[PATCH v2 25/35] target/riscv: Only set TB flags with FP status if enabled
2020-02-13 18:31 UTC (2+ messages)
[PATCH v2 21/35] target/riscv: Add hypvervisor trap support
2020-02-12 20:03 UTC (2+ messages)
[PATCH v1 4/5] target/riscv: progressively load the instruction during decode
2020-02-11 18:00 UTC (4+ messages)
[PATCH] riscv: sifive_u: Add a "serial" property for board serial number
2020-02-11 15:57 UTC (3+ messages)
[PATCH v2 07/35] target/riscv: Add the force HS exception mode
2020-02-10 21:46 UTC (2+ messages)
[PATCH] riscv: Separate FPU register size from core register size in gdbstub [v2]
2020-02-10 17:59 UTC (2+ messages)
[PATCH v4 0/3] Make MachineClass::is_default boolean, refuse multiple default machines
2020-02-10 13:25 UTC (21+ messages)
` [PATCH v4 1/3] hw: Do not initialize MachineClass::is_default to 0
` Tricore default machine (was: [PATCH v4 1/3] hw: Do not initialize MachineClass::is_default to 0)
` Tricore default machine
` [PATCH v4 2/3] hw: Make MachineClass::is_default a boolean type
` [PATCH v4 3/3] vl: Abort if multiple machines are registered as default
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).