messages from 2020-09-06 16:16:56 to 2020-10-07 10:35:34 UTC [more...]
Purpose of QOM properties registered at realize time?
2020-10-07 10:35 UTC (2+ messages)
[PATCH 01/16] hw/core/cpu: Let CPU object have a clock source
2020-10-06 19:53 UTC (10+ messages)
[PATCH 0/5] Support RISC-V migration
2020-10-05 22:10 UTC (11+ messages)
` [PATCH 1/5] target/riscv: Add basic vmstate description of CPU
` [PATCH 2/5] target/riscv: Add PMP state description
` [PATCH 3/5] target/riscv: Add H extention "
` [PATCH 4/5] target/riscv: Add V "
` [PATCH 5/5] target/riscv: Add sifive_plic vmstate
[RFC v5 00/68] support vector extension v1.0
2020-10-05 14:10 UTC (73+ messages)
` [RFC v5 01/68] target/riscv: drop vector 0.7.1 and add 1.0 support
` [RFC v5 02/68] target/riscv: Use FIELD_EX32() to extract wd field
` [RFC v5 03/68] target/riscv: rvv-1.0: add mstatus VS field
` [RFC v5 04/68] target/riscv: rvv-1.0: add sstatus "
` [RFC v5 05/68] target/riscv: rvv-1.0: introduce writable misa.v field
` [RFC v5 06/68] target/riscv: rvv-1.0: add translation-time vector context status
` [RFC v5 07/68] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
` [RFC v5 08/68] target/riscv: rvv-1.0: add vcsr register
` [RFC v5 09/68] target/riscv: rvv-1.0: add vlenb register
` [RFC v5 10/68] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
` [RFC v5 11/68] target/riscv: rvv-1.0: remove MLEN calculations
` [RFC v5 12/68] target/riscv: rvv-1.0: add fractional LMUL
` [RFC v5 13/68] target/riscv: rvv-1.0: add VMA and VTA
` [RFC v5 14/68] target/riscv: rvv-1.0: update check functions
` [RFC v5 15/68] target/riscv: introduce more imm value modes in translator functions
` [RFC v5 16/68] target/riscv: rvv:1.0: add translation-time nan-box helper function
` [RFC v5 17/68] target/riscv: rvv-1.0: configure instructions
` [RFC v5 18/68] target/riscv: rvv-1.0: stride load and store instructions
` [RFC v5 19/68] target/riscv: rvv-1.0: index "
` [RFC v5 20/68] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
` [RFC v5 21/68] target/riscv: rvv-1.0: fault-only-first unit stride load
` [RFC v5 22/68] target/riscv: rvv-1.0: amo operations
` [RFC v5 23/68] target/riscv: rvv-1.0: load/store whole register instructions
` [RFC v5 24/68] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
` [RFC v5 25/68] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
` [RFC v5 26/68] target/riscv: rvv-1.0: floating-point square-root instruction
` [RFC v5 27/68] target/riscv: rvv-1.0: floating-point classify instructions
` [RFC v5 28/68] target/riscv: rvv-1.0: mask population count instruction
` [RFC v5 29/68] target/riscv: rvv-1.0: find-first-set mask bit instruction
` [RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions
` [RFC v5 31/68] target/riscv: rvv-1.0: iota instruction
` [RFC v5 32/68] target/riscv: rvv-1.0: element index instruction
` [RFC v5 33/68] target/riscv: rvv-1.0: allow load element with sign-extended
` [RFC v5 34/68] target/riscv: rvv-1.0: register gather instructions
` [RFC v5 35/68] target/riscv: rvv-1.0: integer scalar move instructions
` [RFC v5 36/68] target/riscv: rvv-1.0: floating-point move instruction
` [RFC v5 37/68] target/riscv: rvv-1.0: floating-point scalar move instructions
` [RFC v5 38/68] target/riscv: rvv-1.0: whole register "
` [RFC v5 39/68] target/riscv: rvv-1.0: integer extension instructions
` [RFC v5 40/68] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
` [RFC v5 41/68] target/riscv: rvv-1.0: single-width bit shift instructions
` [RFC v5 42/68] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
` [RFC v5 43/68] target/riscv: rvv-1.0: narrowing integer right shift instructions
` [RFC v5 44/68] target/riscv: rvv-1.0: widening integer multiply-add instructions
` [RFC v5 45/68] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
` [RFC v5 46/68] target/riscv: rvv-1.0: integer comparison instructions
` [RFC v5 47/68] target/riscv: rvv-1.0: floating-point compare instructions
` [RFC v5 48/68] target/riscv: rvv-1.0: mask-register logical instructions
` [RFC v5 49/68] target/riscv: rvv-1.0: slide instructions
` [RFC v5 50/68] target/riscv: rvv-1.0: floating-point "
` [RFC v5 51/68] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
` [RFC v5 52/68] target/riscv: rvv-1.0: single-width floating-point reduction
` [RFC v5 53/68] target/riscv: rvv-1.0: widening floating-point reduction instructions
` [RFC v5 54/68] target/riscv: rvv-1.0: single-width scaling shift instructions
` [RFC v5 55/68] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
` [RFC v5 56/68] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
` [RFC v5 57/68] target/riscv: rvv-1.0: remove integer extract instruction
` [RFC v5 58/68] target/riscv: rvv-1.0: floating-point min/max instructions
` [RFC v5 59/68] target/riscv: introduce floating-point rounding mode enum
` [RFC v5 60/68] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
` [RFC v5 61/68] target/riscv: rvv-1.0: widening floating-point/integer type-convert
` [RFC v5 62/68] target/riscv: add "set round to odd" rounding mode helper function
` [RFC v5 63/68] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
` [RFC v5 64/68] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
` [RFC v5 65/68] target/riscv: gdb: modify gdb csr xml file to align with csr register map
` [RFC v5 66/68] target/riscv: gdb: support vector registers for rv64 & rv32
` [RFC v5 67/68] target/riscv: implement vstart CSR
` [RFC v5 68/68] target/riscv: trigger illegal instruction exception if frm is not valid
Pointer Masking prototype for RISC-V QEMU
2020-10-05 13:05 UTC (4+ messages)
[PATCH v3] qemu/atomic.h: rename atomic_ to qatomic_
2020-10-03 8:48 UTC (7+ messages)
[PATCH v1 0/4] Allow loading a no MMU kernel
2020-10-02 15:31 UTC (5+ messages)
` [PATCH v1 1/4] hw/riscv: sifive_u: Allow specifying the CPU
` [PATCH v1 2/4] hw/riscv: Return the end address of the loaded firmware
` [PATCH v1 3/4] hw/riscv: Add a riscv_is_32_bit() function
` [PATCH v1 4/4] hw/riscv: Load the kernel after the firmware
[PATCH v2 1/1] riscv: Convert interrupt logs to use qemu_log_mask()
2020-10-02 15:24 UTC
[PATCH] target/riscv: raise exception to HS-mode at get_physical_address
2020-10-01 0:00 UTC (4+ messages)
[PATCH v1 1/1] riscv: Convert interrupt logs to use qemu_log_mask()
2020-09-30 16:59 UTC (3+ messages)
[RFC PATCH v5 0/2] Add file-backed and write-once features to OTP
2020-09-30 7:10 UTC (8+ messages)
` [RFC PATCH v5 1/2] hw/riscv: sifive_u: Add write operation and write-once protection
` [RFC PATCH v5 2/2] hw/riscv: sifive_u: Add backend drive support
[RFC PATCH v6 0/2] Add file-backed and write-once features to OTP
2020-09-28 11:43 UTC (4+ messages)
` [RFC PATCH v6 1/2] hw/misc/sifive_u_otp: Add write function and write-once protection
` [RFC PATCH v6 2/2] hw/misc/sifive_u_otp: Add backend drive support
[RFC v4 00/70] support vector extension v1.0
2020-09-26 5:05 UTC (9+ messages)
` [RFC v4 17/70] target/riscv: rvv-1.0: configure instructions
` [RFC v4 53/70] target/riscv: rvv-1.0: floating-point slide instructions
[PATCH] load_elf: Remove unused address variables from callers
2020-09-25 23:53 UTC (6+ messages)
[PATCH v2] qemu/atomic.h: prefix qemu_ to solve <stdatomic.h> collisions
2020-09-23 9:15 UTC (4+ messages)
[PATCH] qemu/atomic.h: prefix qemu_ to solve <stdatomic.h> collisions
2020-09-23 9:14 UTC (12+ messages)
[PATCH 23/24] sifive_e: Register "revb" as class property
2020-09-22 21:00 UTC (5+ messages)
` [PATCH 24/24] sifive_u: Register "start-in-flash" "
` [PATCH 00/24] qom: Convert some properties to class properties
Fwd: riscv32 wait() problem, qemu or glibc?
2020-09-19 20:41 UTC (3+ messages)
Rom regions overlap
2020-09-19 15:32 UTC
[PATCH 3/5] qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros
2020-09-18 18:17 UTC (9+ messages)
` [PATCH 5/5] [automated] Use OBJECT_DECLARE_SIMPLE_TYPE when possible
` [PATCH 0/5] qom: Convert more declarations to OBJECT_DECLARE*
[PATCH v2 0/6] qom: Allow object to be aligned
2020-09-18 18:00 UTC (4+ messages)
` [PATCH v2 5/6] target/riscv: Set instance_align on RISCVCPU TypeInfo
[PATCH] riscv: Add semihosting support [v7]
2020-09-17 21:18 UTC (4+ messages)
` [PATCH] riscv: Add semihosting support [v8]
riscv32 wait() problem, qemu or glibc?
2020-09-15 18:57 UTC
[PATCH 0/5] qom: Allow object to be aligned
2020-09-15 17:46 UTC (2+ messages)
` [PATCH 4/5] target/riscv: Set instance_align on RISCVCPU TypeInfo
[PATCH] riscv: sifive_test: Allow 16-bit writes to memory region
2020-09-14 21:09 UTC (7+ messages)
[PATCH v4 0/2] riscv: Rename memmap enum constants
2020-09-11 20:33 UTC (5+ messages)
` [PATCH v4 1/2] sifive_e: "
` [PATCH v4 2/2] sifive_u: "
[PATCH v5 00/11] RISC-V Add the OpenTitan Machine
2020-09-10 18:48 UTC (7+ messages)
` [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine
[PULL 0/9] Tracing patches
2020-09-09 10:20 UTC (3+ messages)
[PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support
2020-09-08 1:15 UTC (5+ messages)
[PATCH 00/12] hw/riscv: Clean up the directory
2020-09-06 16:05 UTC (2+ messages)
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