messages from 2021-09-08 04:54:49 to 2021-09-16 13:42:53 UTC [more...]
[PATCH v2 00/22] QEMU RISC-V AIA support
2021-09-16 13:42 UTC (17+ messages)
` [PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
` [PATCH v2 03/22] target/riscv: Implement hgeie and hgeip CSRs
` [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts
` [PATCH v2 16/22] hw/riscv: virt: Use AIA INTC compatible string when available
` [PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs in HART
` [PATCH v2 22/22] docs/system: riscv: Document AIA options for virt machine
[PATCH v2 00/53] monitor: explicitly permit QMP commands to be added for all use cases
2021-09-16 10:54 UTC (99+ messages)
` [PATCH v2 01/53] docs/devel: rename file for writing monitor commands
` [PATCH v2 02/53] docs/devel: tweak headings in monitor command docs
` [PATCH v2 03/53] docs/devel: document expectations for QAPI data modelling for QMP
` [PATCH v2 04/53] docs/devel: add example of command returning unstructured text
` [PATCH v2 05/53] docs/devel: document expectations for HMP commands in the future
` [PATCH v2 06/53] hw/core: introduce 'format_state' callback to replace 'dump_state'
` [PATCH v2 07/53] target/alpha: convert to use format_state instead of dump_state
` [PATCH v2 08/53] target/arm: "
` [PATCH v2 09/53] target/avr: "
` [PATCH v2 10/53] target/cris: "
` [PATCH v2 11/53] target/hexagon: delete unused hexagon_debug() method
` [PATCH v2 12/53] target/hexagon: convert to use format_state instead of dump_state
` [PATCH v2 13/53] target/hppa: "
` [PATCH v2 14/53] target/i386: "
` [PATCH v2 15/53] target/m68k: "
` [PATCH v2 16/53] target/microblaze: "
` [PATCH v2 17/53] target/mips: "
` [PATCH v2 18/53] target/nios2: "
` [PATCH v2 19/53] target/openrisc: "
` [PATCH v2 20/53] target/ppc: "
` [PATCH v2 21/53] target/riscv: "
` [PATCH v2 22/53] target/rx: "
` [PATCH v2 23/53] target/s390x: "
` [PATCH v2 24/53] target/sh: "
` [PATCH v2 25/53] target/sparc: "
` [PATCH v2 26/53] target/tricore: "
` [PATCH v2 27/53] target/xtensa: "
` [PATCH v2 28/53] monitor: remove 'info ioapic' HMP command
` [PATCH v2 29/53] qapi: introduce x-query-registers QMP command
` [PATCH v2 30/53] qapi: introduce x-query-roms "
` [PATCH v2 31/53] qapi: introduce x-query-profile "
` [PATCH v2 32/53] qapi: introduce x-query-numa "
` [PATCH v2 33/53] qapi: introduce x-query-usb "
` [PATCH v2 34/53] qapi: introduce x-query-rdma "
` [PATCH v2 35/53] qapi: introduce x-query-ramblock "
` [PATCH v2 36/53] qapi: introduce x-query-skeys "
` [PATCH v2 37/53] qapi: introduce x-query-cmma "
` [PATCH v2 38/53] qapi: introduce x-query-lapic "
` [PATCH v2 39/53] qapi: introduce x-query-irq "
` [PATCH v2 40/53] hw/core: drop "dump_state" callback from CPU targets
` [PATCH v2 41/53] hw/core: drop support for NULL pointer for FILE * in cpu_dump_state
` [PATCH v2 42/53] hw/core: introduce a 'format_tlb' callback
` [PATCH v2 43/53] target/i386: convert to use format_tlb callback
` [PATCH v2 44/53] target/m68k: "
` [PATCH v2 45/53] target/nios2: "
` [PATCH v2 46/53] target/ppc: "
` [PATCH v2 47/53] target/sh4: "
` [PATCH v2 48/53] target/sparc: "
` [PATCH v2 49/53] target/xtensa: "
` [PATCH v2 50/53] monitor: merge duplicate "info tlb" handlers
` [PATCH v2 51/53] qapi: introduce x-query-tlb QMP command
` [PATCH v2 52/53] qapi: introduce x-query-jit "
` [PATCH v2 53/53] qapi: introduce x-query-opcount "
[PATCH v1 1/1] hw/riscv: opentitan: Correct the USB Dev address
2021-09-16 5:07 UTC (2+ messages)
[ RFC v2 0/9] Improve PMU support
2021-09-16 4:49 UTC (15+ messages)
` [ RFC v2 1/9] target/riscv: Fix PMU CSR predicate function
` [ RFC v2 2/9] target/riscv: pmu: Rename the counters extension to pmu
` [ RFC v2 3/9] target/riscv: pmu: Make number of counters configurable
` [ RFC v2 4/9] target/riscv: Implement mcountinhibit CSR
` [ RFC v2 5/9] target/riscv: Add support for hpmcounters/hpmevents
` [ RFC v2 6/9] target/riscv: Support mcycle/minstret write operation
` [ RFC v2 7/9] target/riscv: Add sscofpmf extension support
` [ RFC v2 8/9] target/riscv: Add few cache related PMU events
` [ RFC v2 9/9] hw/riscv: virt: Add PMU DT node to the device tree
[PATCH] target/riscv: csr: Rename HCOUNTEREN_CY and friends
2021-09-16 4:42 UTC (2+ messages)
[PATCH] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped
2021-09-15 0:25 UTC (3+ messages)
[PATCH] docs/system/riscv: sifive_u: Update U-Boot instructions
2021-09-15 0:24 UTC (3+ messages)
[PATCH RESEND v2 0/4] hw/dma: Align SiFive PDMA behavior with real hardware
2021-09-14 2:24 UTC (6+ messages)
` [PATCH RESEND v2 1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
` [PATCH RESEND v2 2/4] hw/dma: sifive_pdma: claim bit must be set before DMA transactions
` [PATCH RESEND v2 3/4] hw/dma: sifive_pdma: allow non-multiple transaction size transactions
` [PATCH RESEND v2 4/4] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
[PATCH] target/riscv: Force to set mstatus_hs.[SD|FS] bits in mark_fs_dirty()
2021-09-14 2:13 UTC (3+ messages)
Question about riscv-qemu trace
2021-09-12 16:05 UTC (3+ messages)
[PATCH v2 0/4] hw/dma: Align SiFive PDMA behavior with real hardware
2021-09-12 13:05 UTC (2+ messages)
[PATCH v2 1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
2021-09-12 12:44 UTC (4+ messages)
` [PATCH v2 2/4] hw/dma: sifive_pdma: claim bit must be set before DMA transactions
` [PATCH v2 3/4] hw/dma: sifive_pdma: allow non-multiple transaction size transactions
` [PATCH v2 4/4] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
[PATCH 0/4] hw/dma: Align SiFive PDMA behavior with real hardware
2021-09-12 12:42 UTC (12+ messages)
` [PATCH 1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
` [PATCH 2/4] hw/dma: sifive_pdma: claim bit must be set before DMA transactions
` [PATCH 3/4] hw/dma: sifive_pdma: allow non-multiple transaction size transactions
` [PATCH 4/4] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
[PATCH v3 00/30] accel: Move has_work() from SysemuCPUOps to AccelOpsClass
2021-09-12 12:31 UTC (7+ messages)
` [PATCH v3 21/30] target/ppc: Introduce PowerPCCPUClass::has_work()
[PATCH v11 0/7] RISC-V Pointer Masking implementation
2021-09-10 7:15 UTC (11+ messages)
` [PATCH v11 1/7] [RISCV_PM] Add J-extension into RISC-V
` [PATCH v11 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension
` [PATCH v11 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v11 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs
` [PATCH v11 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
` [PATCH v11 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
` [PATCH v11 7/7] [RISCV_PM] Allow experimental J-ext to be turned on
[RFC PATCH v1 0/3] PCIe Root complex event collector
2021-09-09 11:02 UTC (4+ messages)
` [RFC PATCH v1 1/3] hw/pci/pcie.c: modify PCIe Express capability for RCiEP and RCEC
` [RFC PATCH v1 2/3] hw/pci: Add PCIe RCEC support
` [RFC PATCH v1 3/3] docs: pcie: RCEC
[PATCH v3 0/2] Add the SiFive PWM device
2021-09-09 6:35 UTC (6+ messages)
` [PATCH v3 1/2] hw/timer: Add SiFive PWM support
` [PATCH v3 2/2] sifive_u: Connect the SiFive PWM device
[RFC PATCH 0/2] riscv: Adding custom CSR related Kconfig options
2021-09-09 6:30 UTC (10+ messages)
[PATCH v10 0/7] RISC-V Pointer Masking implementation
2021-09-09 5:57 UTC (5+ messages)
` [PATCH v10 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension
` [PATCH v10 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
[PATCH v2 0/3] RISC-V: Populate mtval and stval
2021-09-08 6:48 UTC (9+ messages)
` [PATCH v2 1/3] target/riscv: Set the opcode in DisasContext
` [PATCH v2 2/3] target/riscv: Implement the stval/mtval illegal instruction
` [PATCH v2 3/3] target/riscv: Set mtval and stval support
[PATCH v4 0/4] QEMU RISC-V ACLINT Support
2021-09-08 6:14 UTC (3+ messages)
` [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
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