messages from 2021-09-14 19:29:02 to 2021-09-29 10:36:13 UTC [more...]
[PATCH 00/29] [RFC] build more i386 tcg code modular
2021-09-29 10:35 UTC (10+ messages)
` [PATCH 09/29] tcg/module: add tcg-module.[ch] infrastructure
` [PATCH 10/29] tcg_funcs: Add tlb_flush to TCGModuleOps
[PATCH v2 1/1] hw/riscv: shakti_c: Mark as not user creatable
2021-09-29 9:47 UTC (3+ messages)
[PATCH] hw/riscv: virt: bugfix the memory-backend-file command is invalid
2021-09-29 9:12 UTC
[PATCH v4 0/4] QEMU RISC-V ACLINT Support
2021-09-29 4:25 UTC (4+ messages)
[PATCH v2 0/3] RISC-V: Populate mtval and stval
2021-09-29 3:56 UTC (6+ messages)
` [PATCH v2 2/3] target/riscv: Implement the stval/mtval illegal instruction
[RFC PATCH 00/11] RISC-V: support clic v0.9 specification
2021-09-29 3:55 UTC (10+ messages)
` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus
[PATCH v2 1/2] hw/dma: sifive_pdma: Fix Control.claim bit detection
2021-09-28 23:15 UTC (7+ messages)
` [PATCH v2 2/2] hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
[PATCH v2 0/3] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
2021-09-28 22:42 UTC (13+ messages)
` [PATCH v2 1/3] hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition
` [PATCH v2 2/3] hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
` [PATCH v2 3/3] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
[PATCH v12 0/7] RISC-V Pointer Masking implementatio
2021-09-28 19:00 UTC (8+ messages)
` [PATCH v12 1/7] [RISCV_PM] Add J-extension into RISC-V
` [PATCH v12 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension
` [PATCH v12 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
` [PATCH v12 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs
` [PATCH v12 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
` [PATCH v12 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
` [PATCH v12 7/7] [RISCV_PM] Allow experimental J-ext to be turned on
[PATCH 1/3] hw/char: ibex_uart: Register device in 'input' category
2021-09-28 9:18 UTC (10+ messages)
` [PATCH 2/3] hw/char: shakti_uart: "
` [PATCH 3/3] hw/char: sifive_uart: "
[PATCH v1 1/1] hw/riscv: shakti_c: Mark as not user creatable
2021-09-27 15:35 UTC (3+ messages)
[PATCH] tcg/riscv: Fix potential bug in clobbered call register set
2021-09-27 13:10 UTC (4+ messages)
[PATCH 1/2] hw/dma: sifive_pdma: Improve code readability for "!!foo & bar"
2021-09-27 7:16 UTC (8+ messages)
` [PATCH 2/2] hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
[PATCH] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
2021-09-26 7:59 UTC (9+ messages)
[PATCH v7 31/40] target/riscv: Restrict has_work() handler to sysemu and TCG
2021-09-25 14:51 UTC
[PATCH v6 31/40] target/riscv: Restrict has_work() handler to sysemu and TCG
2021-09-24 9:38 UTC
[PATCH v3] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
2021-09-24 6:55 UTC (3+ messages)
[RFC 00/10] add the rest of riscv bitmapip-0.93 instructions
2021-09-24 5:48 UTC (13+ messages)
` [RFC 01/10] target/riscv: rvb: fixed an error about srow/sroiw instructions
` [RFC 02/10] target/riscv: rvb: add carry-less multiply instructions
` [RFC 03/10] target/riscv: rvb: add cmix/cmov instructions
` [RFC 04/10] target/riscv: rvb: add generalized shuffle instructions
` [RFC 05/10] target/riscv: rvb: add crossbar permutation instructions
` [RFC 06/10] target/riscv: rvb: add bfp/bfpw instructions
` [RFC 07/10] target/riscv: rvb: add CRC instructions
` [RFC 08/10] target/riscv: rvb: add bit-matrix instructions
` [RFC 09/10] target/riscv: rvb: fixed an issue about clzw instruction
` [RFC 10/10] target/riscv: rvb: add funnel shfit instructions
[RFC PATCH v2 00/16] Initial support for machine creation via QMP
2021-09-23 14:04 UTC (29+ messages)
` [RFC PATCH v2 01/16] rename MachineInitPhase enum constants for QAPI compatibility
` [RFC PATCH v2 02/16] qapi: Implement query-machine-phase QMP command
` [RFC PATCH v2 03/16] qapi: Implement x-machine-init "
` [RFC PATCH v2 04/16] softmmu/qdev-monitor: add error handling in qdev_set_id
` [RFC PATCH v2 05/16] qdev-monitor: prevent conflicts between qmp/device_add and cli/-device
` [RFC PATCH v2 06/16] qapi: Allow device_add to execute in machine initialized phase
` [RFC PATCH v2 07/16] hw/core/machine: add machine_class_is_dynamic_sysbus_dev_allowed
` [RFC PATCH v2 08/16] qdev-monitor: Check sysbus device type before creating it
` [RFC PATCH v2 09/16] hw/core/machine: Remove the dynamic sysbus devices type check
` [RFC PATCH v2 10/16] qdev-monitor: allow adding any sysbus device before machine is ready
` [RFC PATCH v2 11/16] softmmu/memory: add memory_region_try_add_subregion function
` [RFC PATCH v2 12/16] add x-sysbus-mmio-map qmp command
` [RFC PATCH v2 13/16] hw/mem/system-memory: add a memory sysbus device
` [RFC PATCH v2 14/16] docs/system: add doc about the initialized machine phase and an example
` [RFC PATCH v2 15/16] hw/char/ibex_uart: set user_creatable
` [RFC PATCH v2 16/16] hw/intc/ibex_plic: "
[PATCH v2 00/53] monitor: explicitly permit QMP commands to be added for all use cases
2021-09-22 16:30 UTC (72+ messages)
` [PATCH v2 01/53] docs/devel: rename file for writing monitor commands
` [PATCH v2 02/53] docs/devel: tweak headings in monitor command docs
` [PATCH v2 03/53] docs/devel: document expectations for QAPI data modelling for QMP
` [PATCH v2 04/53] docs/devel: add example of command returning unstructured text
` [PATCH v2 05/53] docs/devel: document expectations for HMP commands in the future
` [PATCH v2 06/53] hw/core: introduce 'format_state' callback to replace 'dump_state'
` [PATCH v2 07/53] target/alpha: convert to use format_state instead of dump_state
` [PATCH v2 09/53] target/avr: "
` [PATCH v2 10/53] target/cris: "
` [PATCH v2 11/53] target/hexagon: delete unused hexagon_debug() method
` [PATCH v2 12/53] target/hexagon: convert to use format_state instead of dump_state
` [PATCH v2 13/53] target/hppa: "
` [PATCH v2 15/53] target/m68k: "
` [PATCH v2 16/53] target/microblaze: "
` [PATCH v2 17/53] target/mips: "
` [PATCH v2 18/53] target/nios2: "
` [PATCH v2 19/53] target/openrisc: "
` [PATCH v2 20/53] target/ppc: "
` [PATCH v2 22/53] target/rx: "
` [PATCH v2 24/53] target/sh: "
` [PATCH v2 25/53] target/sparc: "
` [PATCH v2 26/53] target/tricore: "
` [PATCH v2 27/53] target/xtensa: "
` [PATCH v2 38/53] qapi: introduce x-query-lapic QMP command
` [PATCH v2 44/53] target/m68k: convert to use format_tlb callback
` [PATCH v2 46/53] target/ppc: "
` [PATCH v2 48/53] target/sparc: "
` [PATCH v2 49/53] target/xtensa: "
` [PATCH v2 50/53] monitor: merge duplicate "info tlb" handlers
[PATCH RESEND v2] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
2021-09-19 16:32 UTC (4+ messages)
[PATCH v11 0/7] RISC-V Pointer Masking implementation
2021-09-18 5:08 UTC (4+ messages)
` [PATCH v11 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
[PATCH v2] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
2021-09-17 6:38 UTC (2+ messages)
[PATCH v1 1/1] hw/riscv: opentitan: Correct the USB Dev address
2021-09-16 21:42 UTC (3+ messages)
[PATCH] target/riscv: csr: Rename HCOUNTEREN_CY and friends
2021-09-16 21:41 UTC (3+ messages)
[ RFC v2 0/9] Improve PMU support
2021-09-16 18:52 UTC (13+ messages)
` [ RFC v2 1/9] target/riscv: Fix PMU CSR predicate function
` [ RFC v2 2/9] target/riscv: pmu: Rename the counters extension to pmu
` [ RFC v2 3/9] target/riscv: pmu: Make number of counters configurable
` [ RFC v2 4/9] target/riscv: Implement mcountinhibit CSR
[PATCH v2 00/22] QEMU RISC-V AIA support
2021-09-16 13:42 UTC (14+ messages)
` [PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
` [PATCH v2 03/22] target/riscv: Implement hgeie and hgeip CSRs
` [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts
` [PATCH v2 16/22] hw/riscv: virt: Use AIA INTC compatible string when available
` [PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs in HART
[PATCH] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped
2021-09-15 0:25 UTC (3+ messages)
[PATCH] docs/system/riscv: sifive_u: Update U-Boot instructions
2021-09-15 0:24 UTC (3+ messages)
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