messages from 2022-10-04 09:24:13 to 2022-11-08 12:58:33 UTC [more...]
[PATCH v2 0/5] Nested virtualization fixes for QEMU
2022-11-08 12:57 UTC (6+ messages)
` [PATCH v2 1/5] target/riscv: Typo fix in sstc() predicate
` [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes
` [PATCH v2 3/5] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
` [PATCH v2 4/5] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX
` [PATCH v2 5/5] target/riscv: Ensure opcode is saved for all relevant instructions
[PATCH v1 0/4] Support native debug icount trigger
2022-11-08 1:54 UTC (9+ messages)
` [PATCH v1 1/4] target/riscv: Add itrigger support when icount is not enabled
` [PATCH v1 2/4] target/riscv: Add itrigger support when icount is enabled
` [PATCH v1 3/4] target/riscv: Enable native debug itrigger
` [PATCH v1 4/4] target/riscv: Add itrigger_enabled field to CPURISCVState
[PATCH V2] hw/riscv: virt: Remove size restriction for pflash
2022-11-07 17:34 UTC (10+ messages)
[PATCH] hw/riscv: virt: Remove size restriction for pflash
2022-11-07 11:23 UTC (8+ messages)
[PATCH 0/5] Nested virtualization fixes for QEMU
2022-11-07 2:48 UTC (13+ messages)
` [PATCH 1/5] target/riscv: Typo fix in sstc() predicate
` [PATCH 2/5] target/riscv: Update VS timer whenever htimedelta changes
` [PATCH 3/5] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
` [PATCH 4/5] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX
` [PATCH 5/5] target/riscv: Ensure opcode is saved for all relevant instructions
[PATCH 0/3] Implement the watchdog timer of HiFive 1 rev b
2022-11-01 2:57 UTC (7+ messages)
` [PATCH 1/3] hw/misc: sifive_e_aon: Support "
` [PATCH 2/3] hw/riscv: sifive_e: "
[PATCH v2 0/3] Implement the watchdog timer of HiFive 1 rev b
2022-11-01 2:46 UTC (4+ messages)
` [PATCH v2 1/3] hw/misc: sifive_e_aon: Support "
` [PATCH v2 2/3] hw/riscv: sifive_e: "
` [PATCH v2 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e
[PATCH v1 0/3] target/riscv: Apply KVM policy to ISA extensions
2022-10-27 23:09 UTC (6+ messages)
` [PATCH v1 1/3] update-linux-headers: Version 6.1-rc2
` [PATCH v1 2/3] target/riscv: Extend isa_ext_data for single letter extensions
` [PATCH v1 3/3] target/riscv: kvm: Support selecting VCPU extensions
[PATCH v4] RISC-V: Add Zawrs ISA extension support
2022-10-27 3:27 UTC (3+ messages)
[PATCH v1 0/2] hw/riscv/opentitan: bump opentitan version
2022-10-25 23:37 UTC (4+ messages)
` [PATCH v1 1/2] hw/riscv/opentitan: bump opentitan
` [PATCH v1 2/2] hw/riscv/opentitan: add aon_timer base unimpl
[PATCH] tcg/riscv: Fix base register for user-only qemu_ld/st
2022-10-25 23:34 UTC (4+ messages)
[RFC 0/8] support subsets of code size reduction extension
2022-10-25 7:03 UTC (8+ messages)
` [RFC 1/8] target/riscv: add cfg properties for Zc* extension
` [RFC 6/8] target/riscv: delete redundant check for zcd instructions in decode_opc
` [RFC 7/8] target/riscv: expose properties for Zc* extension
[PATCH v0 0/2] hw/riscv/opentitan: bump opentitan version
2022-10-25 4:05 UTC (7+ messages)
` [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan
` [PATCH v0 2/2] hw/riscv/opentitan: add aon_timer base unimpl
[PATCH] target/riscv/pmp: fix non-translated page size address checks w/ MPU
2022-10-25 2:19 UTC (4+ messages)
[PATCH v4 05/11] riscv: re-randomize rng-seed on reboot
2022-10-25 1:31 UTC (2+ messages)
[PATCH] tcg/riscv: Fix range matched by TCG_CT_CONST_M12
2022-10-25 1:30 UTC (4+ messages)
add qemu_fdt_setprop_strings
2022-10-24 15:18 UTC (12+ messages)
` [PATCH v5 1/6] device_tree: add qemu_fdt_setprop_strings() helper
` [PATCH v5 2/6] hw/core: don't check return on qemu_fdt_setprop_string_array()
` [PATCH v5 3/6] hw/riscv: use qemu_fdt_setprop_strings() for string arrays
` [PATCH v5 4/6] hw/core: use qemu_fdt_setprop_strings()
` [PATCH v5 5/6] hw/mips: "
` [PATCH v5 6/6] hw/arm: change to "
[PATCH] treewide: Remove the unnecessary space before semicolon
2022-10-24 11:42 UTC (6+ messages)
[PATCH v3 0/2] implement `FIELDx_1CLEAR() macro
2022-10-24 5:02 UTC (6+ messages)
` [PATCH v3 1/2] hw/registerfields: add `FIELDx_1CLEAR()` macro
` [PATCH v3 2/2] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro
[PATCH] target/riscv: Fix PMP propagation for tlb
2022-10-24 3:16 UTC (4+ messages)
[PATCH 1/1] tcg/riscv: Fix base regsiter for qemu_ld/st
2022-10-23 15:42 UTC (2+ messages)
[RFC PATCH 0/3] Fix some TCG RISC-V backend bugs
2022-10-21 4:29 UTC (15+ messages)
` [RFC PATCH 1/3] tcg/riscv: Fix base regsiter for qemu_ld/st
` [RFC PATCH 2/3] tcg/riscv: Fix tcg_out_opc_imm when imm exceeds
` [RFC PATCH 3/3] tcg/riscv: Remove a wrong optimization for addsub2
Question about TCG backend correctness
2022-10-19 13:46 UTC (8+ messages)
[PATCH v4 0/2] riscv: Add support for Zicbo[m,z,p] instructions
2022-10-17 18:35 UTC (4+ messages)
` [PATCH v4 2/2] target/riscv: Enable "
[PATCH v11 0/5] RISC-V Smstateen support
2022-10-17 1:37 UTC (7+ messages)
` [PATCH v11 1/5] target/riscv: Add smstateen support
` [PATCH v11 2/5] target/riscv: smstateen check for h/s/envcfg
` [PATCH v11 3/5] target/riscv: generate virtual instruction exception
` [PATCH v11 4/5] target/riscv: smstateen check for fcsr
` [PATCH v11 5/5] target/riscv: smstateen knobs
[PATCH] target/riscv: pmp: Fixup TLB size calculation
2022-10-14 4:36 UTC (6+ messages)
[PATCH v3 5/8] riscv: re-randomize rng-seed on reboot
2022-10-14 2:16 UTC
[PATCH v4 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings
2022-10-13 5:15 UTC (2+ messages)
` (subset) "
[PATCH v2 3/8] riscv: re-randomize rng-seed on reboot
2022-10-12 5:04 UTC (2+ messages)
[PATCH v3 0/2] Enhance maximum priority support of PLIC
2022-10-11 22:47 UTC (8+ messages)
` [PATCH v3 1/2] hw/intc: sifive_plic: fix hard-coded max priority level
` [PATCH v3 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field
[PATCH v5 0/2] hw/ssi/ibex_spi: bug fixes
2022-10-11 22:42 UTC (2+ messages)
[PATCH V5 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
2022-10-11 22:39 UTC (7+ messages)
` [PATCH V5 1/3] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
` [PATCH V5 2/3] hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
` [PATCH V5 3/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
[PULL 00/10] Dump patches
2022-10-11 15:12 UTC (12+ messages)
` [PULL 01/10] dump: Replace opaque DumpState pointer with a typed one
` [PULL 02/10] dump: Rename write_elf_loads to write_elf_phdr_loads
` [PULL 03/10] dump: Refactor dump_iterate and introduce dump_filter_memblock_*()
` [PULL 04/10] dump: Rework get_start_block
` [PULL 05/10] dump: Rework filter area variables
` [PULL 06/10] dump: Rework dump_calculate_size function
` [PULL 07/10] dump: Split elf header functions into prepare and write
` [PULL 08/10] dump: Rename write_elf*_phdr_note to prepare_elf*_phdr_note
` [PULL 09/10] dump: simplify a bit kdump get_next_page()
` [PULL 10/10] dump: fix kdump to work over non-aligned blocks
[PATCH v10 0/5] RISC-V Smstateen support
2022-10-10 14:47 UTC (9+ messages)
` [PATCH v10 3/5] target/riscv: generate virtual instruction exception
` [PATCH v10 4/5] target/riscv: smstateen check for fcsr
[PATCH v3] disas/riscv.c: rvv: Add disas support for vector instructions
2022-10-10 7:35 UTC (3+ messages)
[PATCH 3/6] riscv: re-randomize rng-seed on reboot
2022-10-10 2:56 UTC (2+ messages)
[PATCH v1 0/2] Add OpenTitan lifecycle controller
2022-10-10 2:47 UTC (5+ messages)
` [PATCH v1 1/2] hw/misc: add ibex "
` [PATCH v1 2/2] riscv/opentitan: connect "
[PATCH] hw/riscv: Update comment for qtest check in riscv_find_firmware()
2022-10-10 1:40 UTC (3+ messages)
Question about RISC-V brom register a1 set value
2022-10-05 10:53 UTC (3+ messages)
` 回复：Question "
[PULL 16/20] hw/core: Add CPUClass.get_pc
2022-10-04 19:52 UTC
[PATCH v7 16/18] hw/core: Add CPUClass.get_pc
2022-10-04 14:10 UTC
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