messages from 2022-11-28 15:59:37 to 2022-12-15 03:25:58 UTC [more...]
[PATCH v2 0/5] Nested virtualization fixes for QEMU
2022-12-15 3:25 UTC (7+ messages)
` [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes
[PATCH v4 4/4] hw/nvme: fix missing cq eventidx update
2022-12-14 18:33 UTC (2+ messages)
[PATCH] include: Don't include qemu/osdep.h
2022-12-12 21:54 UTC (6+ messages)
[PATCH 0/2] Clean up includes
2022-12-12 11:33 UTC (7+ messages)
` [PATCH 1/2] include/hw/virtio: Break inclusion loop
` [PATCH 2/2] include: Include headers where needed
[PATCH v3 4/4] hw/nvme: fix missing cq eventidx update
2022-12-12 11:39 UTC (3+ messages)
[PATCH v4] riscv: Allow user to set the satp mode
2022-12-12 10:22 UTC
[PATCH 00/11] Add support for the T-Head vendor extensions
2022-12-12 9:21 UTC (5+ messages)
` [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions
[PATCH v3 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
2022-12-12 6:11 UTC (17+ messages)
` [PATCH v3 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
` [PATCH v3 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order
` [PATCH v3 05/16] hw/riscv: spike: Remove misleading comments
` [PATCH v3 06/16] hw/intc: sifive_plic: Drop PLICMode_H
` [PATCH v3 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser
` [PATCH v3 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
` [PATCH v3 09/16] hw/intc: sifive_plic: Update "num-sources" property default value
` [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
` [PATCH v3 11/16] hw/riscv: sifive_e: "
` [PATCH v3 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
` [PATCH v3 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
` [PATCH v3 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
` [PATCH v3 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
` [PATCH v3 16/16] hw/intc: sifive_plic: Fix the pending register range check
[PATCH v3 0/3] target/riscv: Apply KVM policy to ISA extensions
2022-12-12 6:01 UTC (5+ messages)
` [PATCH v3 1/3] update-linux-headers: Version 6.1-rc8
` [PATCH v3 2/3] target/riscv: Extend isa_ext_data for single letter extensions
` [PATCH v3 3/3] target/riscv: kvm: Support selecting VCPU extensions
[RFC PATCH] RISC-V: Save mmu_idx using FIELD_DP32 not OR
2022-12-12 5:51 UTC (3+ messages)
[PATCH] hw/riscv: Add support to change default RISCV hart memory region
2022-12-11 5:27 UTC
[PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
2022-12-08 22:49 UTC (22+ messages)
` [PATCH v2 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
` [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order
` [PATCH v2 05/16] hw/riscv: spike: Remove misleading comments
` [PATCH v2 06/16] hw/intc: sifive_plic: Drop PLICMode_H
` [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser
` [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
` [PATCH v2 09/16] hw/intc: sifive_plic: Update "num-sources" property default value
` [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
` [PATCH v2 11/16] hw/riscv: sifive_e: "
` [PATCH v2 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
` [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
` [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
` [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
` [PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range check
[PATCH 1/2] target/riscv: Simplify helper_sret() a little bit
2022-12-08 22:43 UTC (6+ messages)
` [PATCH 2/2] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
[PATCH v2 3/3] hw/nvme: fix missing cq eventidx update
2022-12-08 18:37 UTC (2+ messages)
[PATCH 0/1] hw/nvme: shadow doorbells broken on riscv64
2022-12-08 10:31 UTC
[PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
2022-12-07 10:11 UTC (40+ messages)
` [PATCH 03/15] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
` [PATCH 04/15] hw/riscv: Sort machines Kconfig options in alphabetical order
` [PATCH 05/15] hw/riscv: spike: Remove misleading comments
` [PATCH 06/15] hw/intc: sifive_plic: Drop PLICMode_H
` [PATCH 07/15] hw/intc: sifive_plic: Improve robustness of the PLIC config parser
` [PATCH 08/15] hw/intc: sifive_plic: Update "num-sources" property default value
` [PATCH 09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
` [PATCH 10/15] hw/riscv: sifive_e: "
` [PATCH 11/15] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
` [PATCH 12/15] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
` [PATCH 13/15] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
` [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
` [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check
[PATCH] target/riscv: Set pc_succ_insn for !rvc illegal insn
2022-12-07 7:00 UTC (4+ messages)
[PATCH] target/riscv: Fix mret exception cause when no pmp rule is configured
2022-12-07 5:18 UTC (4+ messages)
[PATCH v3 0/3] Implement the watchdog timer of HiFive 1 rev b
2022-12-07 4:02 UTC (7+ messages)
` [PATCH v3 1/3] hw/misc: sifive_e_aon: Support "
` [PATCH v3 2/3] hw/riscv: sifive_e: "
` [PATCH v3 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e
[PATCH v4] RISC-V: Add Zawrs ISA extension support
2022-12-07 3:01 UTC (2+ messages)
[PATCH] hw/intc: sifive_plic: fix out-of-bound access of source_priority array
2022-12-07 2:59 UTC (2+ messages)
[PATCH v3 0/3] Add (more) missing PolarFire SoC io regions
2022-12-06 6:57 UTC (4+ messages)
` [PATCH v3 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented
[PATCH v3] riscv: Allow user to set the satp mode
2022-12-06 6:08 UTC (4+ messages)
[PATCH v2 0/3] target/riscv: Apply KVM policy to ISA extensions
2022-12-05 15:37 UTC (6+ messages)
` [PATCH v2 1/3] update-linux-headers: Version 6.1-rc8
` [PATCH v2 2/3] target/riscv: Extend isa_ext_data for single letter extensions
` [PATCH v2 3/3] target/riscv: kvm: Support selecting VCPU extensions
[PATCH-for-8.0 0/3] tcg: Replace tcg_target_[u]long -> [u]intptr_t
2022-12-01 3:22 UTC (5+ messages)
` [PATCH-for-8.0 1/3] tcg/s390x: Fix coding style
` [PATCH-for-8.0 2/3] tcg: Replace tcg_target_long -> intptr_t
` [PATCH-for-8.0 3/3] tcg: Replace tcg_target_ulong -> uintptr_t
[PATCH for-8.0 00/19] Convert most CPU classes to 3-phase reset
2022-11-30 13:22 UTC (9+ messages)
` [PATCH for-8.0 05/19] target/hexagon: Convert "
` [PATCH for-8.0 17/19] target/sparc: "
[PATCH v14 0/5] Improve PMU support
2022-11-30 8:31 UTC (14+ messages)
` [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree
[PATCH v8 0/9] support subsets of code size reduction extension
2022-11-30 7:50 UTC (10+ messages)
` [PATCH v8 1/9] target/riscv: add cfg properties for Zc* extension
` [PATCH v8 2/9] target/riscv: add support for Zca extension
` [PATCH v8 3/9] target/riscv: add support for Zcf extension
` [PATCH v8 4/9] target/riscv: add support for Zcd extension
` [PATCH v8 5/9] target/riscv: add support for Zcb extension
` [PATCH v8 6/9] target/riscv: add support for Zcmp extension
` [PATCH v8 7/9] target/riscv: add support for Zcmt extension
` [PATCH v8 8/9] target/riscv: expose properties for Zc* extension
` [PATCH v8 9/9] disas/riscv.c: add disasm support for Zc*
[PATCH v7 0/9] support subsets of code size reduction extension
2022-11-30 7:08 UTC (13+ messages)
` [PATCH v7 1/9] target/riscv: add cfg properties for Zc* extension
` [PATCH v7 2/9] target/riscv: add support for Zca extension
` [PATCH v7 3/9] target/riscv: add support for Zcf extension
` [PATCH v7 4/9] target/riscv: add support for Zcd extension
` [PATCH v7 5/9] target/riscv: add support for Zcb extension
` [PATCH v7 6/9] target/riscv: add support for Zcmp extension
` [PATCH v7 7/9] target/riscv: add support for Zcmt extension
` [PATCH v7 8/9] target/riscv: expose properties for Zc* extension
` [PATCH v7 9/9] disas/riscv.c: add disasm support for Zc*
` "
[PATCH v6 0/9] support subsets of code size reduction extension
2022-11-29 2:22 UTC (5+ messages)
` [PATCH v6 2/9] target/riscv: add support for Zca extension
[PATCH v3 0/3] cleanup: Tweak and re-run return_directly.cocci
2022-11-28 15:59 UTC (3+ messages)
` [PATCH v3 3/3] ppc4xx_sdram: Simplify sdram_ddr_size() to return directly
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