messages from 2023-07-05 21:41:39 to 2023-07-12 21:00:07 UTC [more...]
[PATCH for-8.2 v2 0/7] target/riscv: add 'max' CPU type
2023-07-12 20:57 UTC (7+ messages)
` [PATCH for-8.2 v2 1/7] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
` [PATCH for-8.2 v2 2/7] target/riscv/cpu.c: skip 'bool' check when filtering KVM props
` [PATCH for-8.2 v2 4/7] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
` [PATCH for-8.2 v2 5/7] target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro
` [PATCH for-8.2 v2 6/7] target/riscv: add 'max' CPU type
` [PATCH for-8.2 v2 7/7] avocado, risc-v: add opensbi tests for 'max' CPU
[PATCH for-8.2 0/7] target/riscv: add 'max' CPU type
2023-07-12 20:30 UTC (10+ messages)
` [PATCH for-8.2 1/7] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
` [PATCH for-8.2 2/7] target/riscv/cpu.c: skip 'bool' check when filtering KVM props
` [PATCH for-8.2 3/7] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
` [PATCH for-8.2 4/7] target/riscv/cpu.c: split non-ratified "
` [PATCH for-8.2 5/7] target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro
` [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type
` [PATCH for-8.2 7/7] avocado, risc-v: add opensbi tests for 'max' CPU
[PATCH 00/10] RISC-V: ACPI: Enable AIA and update RHC
2023-07-12 20:21 UTC (14+ messages)
` [PATCH 01/10] hw/arm/virt-acpi-build.c: Move fw_cfg and virtio to common location
` [PATCH 02/10] hw/riscv: virt: Add PCI bus reference in RISCVVirtState
` [PATCH 03/10] hw/riscv: virt: Make few IMSIC macros and functions public
` [PATCH 04/10] hw/riscv: virt: Add PCIe HIGHMEM in memmap
` [PATCH 05/10] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC
` [PATCH 06/10] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
` [PATCH 07/10] hw/riscv/virt-acpi-build.c: Add APLIC "
` [PATCH 08/10] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
` [PATCH 09/10] hw/riscv/virt-acpi-build.c: Add MMU node "
` [PATCH 10/10] hw/riscv/virt-acpi-build.c: Add IO controllers and devices
[PATCH-for-8.2 v3 00/16] target/riscv: Allow building without TCG (KVM-only so far)
2023-07-12 15:18 UTC (18+ messages)
` [PATCH v3 01/16] target/riscv: Remove unuseful KVM stubs
` [PATCH v3 02/16] target/riscv: Remove unused 'instmap.h' header in translate.c
` [PATCH v3 03/16] target/riscv: Restrict sysemu specific header to user emulation
` [PATCH v3 04/16] target/riscv: Restrict 'rv128' machine to TCG accelerator
` [PATCH v3 05/16] target/riscv: Move sysemu-specific files to target/riscv/sysemu/
` [PATCH v3 06/16] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu
` [PATCH v3 07/16] target/riscv: Move TCG-specific files to target/riscv/tcg/
` [PATCH v3 08/16] target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c
` [PATCH v3 09/16] target/riscv: Expose some 'trigger' prototypes from debug.c
` [PATCH v3 10/16] target/riscv: Extract TCG-specific code "
` [PATCH v3 11/16] target/riscv: Move sysemu-specific debug files to target/riscv/sysemu/
` [PATCH v3 12/16] target/riscv: Expose riscv_cpu_pending_to_irq() from cpu_helper.c
` [RFC PATCH v3 13/16] target/riscv: Move TCG/sysemu-specific code to tcg/sysemu/cpu_helper.c
` [PATCH v3 14/16] target/riscv: Move sysemu-specific code to sysemu/cpu_helper.c
` [PATCH v3 15/16] target/riscv: Restrict TCG-specific prototype declarations
` [PATCH v3 16/16] gitlab-ci.d/crossbuilds: Add KVM riscv64 cross-build jobs
[PATCH] docs/system/target-riscv.rst: tidy CPU firmware section
2023-07-12 14:37 UTC
[PATCH v7 00/15] Add RISC-V vector cryptographic instruction set support
2023-07-11 17:12 UTC (7+ messages)
` [PATCH v7 12/15] target/riscv: Add Zvkg ISA extension support
riscv kvm breakage
2023-07-11 17:02 UTC (4+ messages)
[PATCH v8 00/15] Add RISC-V vector cryptographic instruction set support
2023-07-11 16:59 UTC (16+ messages)
` [PATCH v8 01/15] target/riscv: Refactor some of the generic vector functionality
` [PATCH v8 02/15] target/riscv: Refactor vector-vector translation macro
` [PATCH v8 03/15] target/riscv: Remove redundant "cpu_vl == 0" checks
` [PATCH v8 04/15] target/riscv: Add Zvbc ISA extension support
` [PATCH v8 05/15] target/riscv: Move vector translation checks
` [PATCH v8 06/15] target/riscv: Refactor translation of vector-widening instruction
` [PATCH v8 07/15] target/riscv: Refactor some of the generic vector functionality
` [PATCH v8 08/15] target/riscv: Add Zvbb ISA extension support
` [PATCH v8 09/15] target/riscv: Add Zvkned "
` [PATCH v8 10/15] target/riscv: Add Zvknh "
` [PATCH v8 11/15] target/riscv: Add Zvksh "
` [PATCH v8 12/15] target/riscv: Add Zvkg "
` [PATCH v8 13/15] crypto: Create sm4_subword
` [PATCH v8 14/15] crypto: Add SM4 constant parameter CK
` [PATCH v8 15/15] target/riscv: Add Zvksed ISA extension support
RFC: QEMU rv64/rv32 CPU, 'max' CPU and profile support
2023-07-11 12:19 UTC (8+ messages)
[PATCH] riscv/disas: Fix disas output of upper immediates
2023-07-11 7:50 UTC
[PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string to DTS
2023-07-11 7:03 UTC (2+ messages)
` [PATCH v3 1/1] "
[PATCH v2] target/riscv: Add Zihintntl extension ISA string to DTS
2023-07-11 6:46 UTC (2+ messages)
[PATCH 0/4] chardev/char-fe: Document FEWatchFunc and use G_SOURCE_CONTINUE/REMOVE
2023-07-10 13:42 UTC (9+ messages)
` [PATCH 2/4] chardev/char-fe: Clarify qemu_chr_fe_add_watch 'condition' arg is a mask
` [PATCH 3/4] chardev/char-fe: Document FEWatchFunc typedef
` [PATCH 4/4] hw/char: Have FEWatchFunc handlers return G_SOURCE_CONTINUE/REMOVE
[PATCH v8] riscv: Add support for the Zfa extension
2023-07-10 11:28 UTC (2+ messages)
[PATCH v7] riscv: Add support for the Zfa extension
2023-07-10 7:13 UTC (3+ messages)
[PATCH v4 0/6] Add RISC-V KVM AIA Support
2023-07-10 4:00 UTC (3+ messages)
[PATCH v9 00/20] target/riscv, KVM: fixes and enhancements
2023-07-10 2:48 UTC (36+ messages)
` [PATCH v9 01/20] target/riscv: skip features setup for KVM CPUs
` [PATCH v9 02/20] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set
` [PATCH v9 03/20] target/riscv/cpu.c: restrict 'mvendorid' value
` [PATCH v9 04/20] target/riscv/cpu.c: restrict 'mimpid' value
` [PATCH v9 05/20] target/riscv/cpu.c: restrict 'marchid' value
` [PATCH v9 06/20] target/riscv: use KVM scratch CPUs to init KVM properties
` [PATCH v9 07/20] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids()
` [PATCH v9 08/20] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs
` [PATCH v9 09/20] linux-headers: Update to v6.4-rc1
` [PATCH v9 10/20] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU
` [PATCH v9 11/20] target/riscv/cpu: add misa_ext_info_arr[]
` [PATCH v9 12/20] target/riscv: add KVM specific MISA properties
` [PATCH v9 13/20] target/riscv/kvm.c: update KVM MISA bits
` [PATCH v9 14/20] target/riscv/kvm.c: add multi-letter extension KVM properties
` [PATCH v9 15/20] target/riscv/cpu.c: add satp_mode properties earlier
` [PATCH v9 16/20] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()
` [PATCH v9 17/20] target/riscv/cpu.c: create KVM mock properties
` [PATCH v9 18/20] target/riscv: update multi-letter extension KVM properties
` [PATCH v9 19/20] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper
` [PATCH v9 20/20] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM
[PATCH qemu v3 0/1] [Ping] [PATCH qemu v3] fdt_load_addr is getting assigned as the result of riscv_compute_fdt_addr(), which is an uint64_t
2023-07-10 1:22 UTC (4+ messages)
` [PATCH qemu v3 1/1] "
[PATCH] target/riscv: Add Zihintntl extension ISA string to DTS
2023-07-10 1:10 UTC (3+ messages)
[PATCH v2] riscv: Generate devicetree only after machine initialization is complete
2023-07-10 1:02 UTC (4+ messages)
[PATCH] target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly
2023-07-10 1:01 UTC (4+ messages)
[RISC-V] ERROR:../accel/tcg/cpu-exec.c:1028:cpu_exec_setjmp: assertion failed: (cpu == current_cpu)
2023-07-09 6:12 UTC (6+ messages)
[PATCH v3 0/2] target/riscv: improve code accuracy and
2023-07-09 9:17 UTC (4+ messages)
` [PATCH v3 1/2] target/riscv: Remove redundant check in pmp_is_locked
` [PATCH v3 2/2] target/riscv: Optimize ambiguous local variable in pmp_hart_has_privs
[PATCH v4 00/37] crypto: Provide aes-round.h and host accel
2023-07-08 17:38 UTC (31+ messages)
` [PATCH v4 13/37] host/include/aarch64: Implement aes-round.h
` [PATCH v4 17/37] target/ppc: Use aesenc_SB_SR_MC_AK
` [PATCH v4 21/37] target/i386: Use aesdec_IMC
` [PATCH v4 22/37] target/i386: Use aesenc_SB_SR_MC_AK
` [PATCH v4 23/37] target/i386: Use aesdec_ISB_ISR_IMC_AK
` [PATCH v4 25/37] target/arm: Use aesenc_SB_SR_AK
` [PATCH v4 26/37] target/arm: Use aesdec_ISB_ISR_AK
` [PATCH v4 27/37] target/arm: Use aesenc_MC
` [PATCH v4 28/37] target/arm: Use aesdec_IMC
` [PATCH v4 29/37] target/riscv: Use aesenc_SB_SR_AK
` [PATCH v4 30/37] target/riscv: Use aesdec_ISB_ISR_AK
` [PATCH v4 31/37] target/riscv: Use aesdec_IMC
` [PATCH v4 32/37] target/riscv: Use aesenc_SB_SR_MC_AK
` [PATCH v4 33/37] target/riscv: Use aesdec_ISB_ISR_IMC_AK
[PATCH v3 1/2] target/riscv: Remove redundant check in pmp_is_locked
2023-07-08 5:36 UTC (2+ messages)
` [PATCH v3 2/2] target/riscv: Optimize ambiguous local variable in pmp_hart_has_privs
[PATCH v2 1/2] target/riscv: Remove redundant check in pmp_is_locked
2023-07-07 19:31 UTC (2+ messages)
[PATCH] target/riscv: Fix LMUL check to use minimum SEW
2023-07-06 13:22 UTC (3+ messages)
[PATCH v8 00/20] target/riscv, KVM: fixes and enhancements
2023-07-06 9:37 UTC (24+ messages)
` [PATCH v8 01/20] target/riscv: skip features setup for KVM CPUs
` [PATCH v8 02/20] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set
` [PATCH v8 03/20] target/riscv/cpu.c: restrict 'mvendorid' value
` [PATCH v8 05/20] target/riscv/cpu.c: restrict 'marchid' value
` [PATCH v8 06/20] target/riscv: use KVM scratch CPUs to init KVM properties
` [PATCH v8 07/20] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids()
` [PATCH v8 08/20] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs
` [PATCH v8 09/20] linux-headers: Update to v6.4-rc1
` [PATCH v8 10/20] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU
` [PATCH v8 11/20] target/riscv/cpu: add misa_ext_info_arr[]
` [PATCH v8 14/20] target/riscv/kvm.c: add multi-letter extension KVM properties
` [PATCH v8 15/20] target/riscv/cpu.c: add satp_mode properties earlier
` [PATCH v8 16/20] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()
` [PATCH v8 17/20] target/riscv/cpu.c: create KVM mock properties
` [PATCH v8 18/20] target/riscv: update multi-letter extension KVM properties
` [PATCH v8 19/20] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper
` [PATCH v8 20/20] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM
[PATCH v3 0/1] target/riscv: Add support for BF16 extensions
2023-07-06 5:51 UTC (3+ messages)
` [PATCH v3 1/1] target/riscv: Add disas "
[PATCH v5] dt-bindings: riscv: deprecate riscv,isa
2023-07-05 23:50 UTC (3+ messages)
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