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From: Chao Liu <chao.liu.zevorn@gmail.com>
To: Nicholas Piggin <npiggin@gmail.com>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	 Weiwei Li <liwei1518@gmail.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	 Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	bin.meng@windriver.com, vivahavey@gmail.com,
	 Alvin Chang <alvinga@andestech.com>,
	Yu-Ming Chang <yumin686@andestech.com>,
	 Joel Stanley <joel@jms.id.au>
Subject: Re: [RFC PATCH 03/25] target/riscv/debug: Implement permissive type unavailable trigger
Date: Mon, 6 Jul 2026 14:13:56 +0800	[thread overview]
Message-ID: <aktHmmmRu6cb_Jav@ChaodeMacBook-Pro.local> (raw)
In-Reply-To: <20260114044701.1173347-4-npiggin@gmail.com>

On Wed, Jan 14, 2026 at 02:46:36PM +0800, Nicholas Piggin wrote:
> When a trigger type is "disabled", tdata2 and tdata3 must accept values
> that are valid for some supported trigger type. Additionally, writing 0
> to tdata1 must result in the type becoming "disabled". This is important
> for the prescribed sequences for updating triggers.
> 
> Implement write tdata=0 -> disabled behaviour and permissive accepting
> of tdata2/3 values in disabled state. This implementation could be
> improved by checking tdata2/3 values against supported trigger types,
> but it is good enough to be usable by software.
> 
> From the RISC-V Debug Specification for tdata1:
> 
>   Writing 0 to this register must result in a trigger that is disabled.
>   If this trigger supports multiple types, then the hardware should
>   disable it by changing type to 15.
> 
> and, when type=15:
> 
>   This trigger is disabled. In this state, tdata2 and tdata3 can be
>   written with any value that is supported for any of the types this
>   trigger implements.
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

> ---
>  target/riscv/debug.c | 30 +++++++++++++++++++++++++++++-
>  1 file changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index 2190c25f23..c92bd9860e 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -827,6 +827,28 @@ static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
>      }
>  }
>  
> +static void anytype_reg_write(CPURISCVState *env, target_ulong index,
> +                              int tdata_index, target_ulong val)
> +{
> +    /*
> +     * This should check the value is valid for at least one of the supported
> +     * trigger types.
> +     */
> +    switch (tdata_index) {
> +    case TDATA1:
> +        env->tdata1[env->trigger_cur] = val;
> +        break;
> +    case TDATA2:
> +        env->tdata2[env->trigger_cur] = val;
> +        break;
> +    case TDATA3:
> +        env->tdata3[env->trigger_cur] = val;
> +        break;
> +    default:
> +        g_assert_not_reached();
> +    }
> +}
> +
>  static int itrigger_get_adjust_count(CPURISCVState *env)
>  {
>      int count = itrigger_get_count(env, env->trigger_cur), executed;
> @@ -883,6 +905,10 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
>      }
>  
>      if (tdata_index == TDATA1) {
> +        if (val == 0) {
> +            /* special case, writing 0 results in disabled trigger */
> +            val = build_tdata1(env, TRIGGER_TYPE_UNAVAIL, 0, 0);
> +        }
>          trigger_type = extract_trigger_type(env, val);
>      }
>  
> @@ -897,6 +923,9 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
>          itrigger_reg_write(env, env->trigger_cur, tdata_index, val);
>          check_itrigger = true;
>          break;
> +    case TRIGGER_TYPE_UNAVAIL:
> +        anytype_reg_write(env, env->trigger_cur, tdata_index, val);
> +        break;
>      case TRIGGER_TYPE_INT:
>      case TRIGGER_TYPE_EXCP:
>      case TRIGGER_TYPE_EXT_SRC:
> @@ -904,7 +933,6 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
>                        trigger_type);
>          break;
>      case TRIGGER_TYPE_NO_EXIST:
> -    case TRIGGER_TYPE_UNAVAIL:
>          qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
>                        trigger_type);
>          break;
> -- 
> 2.51.0
> 
> 


      parent reply	other threads:[~2026-07-06  6:14 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20260114044701.1173347-1-npiggin@gmail.com>
     [not found] ` <20260114044701.1173347-2-npiggin@gmail.com>
2026-06-04  9:55   ` [RFC PATCH 01/25] target/riscv/debug: Check only mcontrol triggers for break/watchpoint matching Daniel Henrique Barboza
2026-06-08  2:57   ` Chao Liu
     [not found] ` <20260114044701.1173347-5-npiggin@gmail.com>
2026-06-04 10:12   ` [RFC PATCH 04/25] target/riscv/debug: Fix icount trigger privilege check Daniel Henrique Barboza
2026-07-06  5:00   ` Chao Liu
     [not found] ` <20260114044701.1173347-6-npiggin@gmail.com>
2026-06-04 10:29   ` [RFC PATCH 05/25] target/riscv/debug: Update itrigger_enabled after changing privilege Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-7-npiggin@gmail.com>
2026-06-04 10:29   ` [RFC PATCH 06/25] target/riscv/debug: Implement get_trigger_action for icount type trigger Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-8-npiggin@gmail.com>
2026-06-04 10:30   ` [RFC PATCH 07/25] target/riscv/debug: Fix migration post_load icount_enabled() test Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-9-npiggin@gmail.com>
2026-06-04 10:30   ` [RFC PATCH 08/25] target/riscv/debug: Fix icount privilege matching " Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-10-npiggin@gmail.com>
2026-06-04 10:31   ` [RFC PATCH 09/25] target/riscv/debug: Implement icount trigger textra matching Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-11-npiggin@gmail.com>
2026-06-04 10:32   ` [RFC PATCH 10/25] target/riscv/debug: Maintain itrigger_enabled in helper_itrigger_match() Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-26-npiggin@gmail.com>
2026-06-04 10:32   ` [RFC PATCH 25/25] target/riscv/debug: Fix minor comment typos Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-12-npiggin@gmail.com>
2026-06-04 11:35   ` [RFC PATCH 11/25] target/riscv/debug: Fix breakpoint matching action Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-13-npiggin@gmail.com>
2026-06-04 11:38   ` [RFC PATCH 12/25] target/riscv/debug: Put mcontrol load/store match address into tval Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-14-npiggin@gmail.com>
2026-06-04 11:38   ` [RFC PATCH 13/25] target/riscv/debug: Remove breakpoints on reset Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-15-npiggin@gmail.com>
2026-06-04 12:52   ` [RFC PATCH 14/25] target/riscv/debug: Move debug CPU post_load details into debug.c Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-16-npiggin@gmail.com>
2026-06-04 12:53   ` [RFC PATCH 15/25] target/riscv/debug: Insert breakpoints after migration Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-18-npiggin@gmail.com>
2026-06-04 12:55   ` [RFC PATCH 17/25] target/riscv/debug: Advertise icount trigger type in tinfo Daniel Henrique Barboza
     [not found] ` <20260114044701.1173347-19-npiggin@gmail.com>
2026-06-04 12:56   ` [RFC PATCH 18/25] target/riscv/debug: Reset trigger type to unavailable Daniel Henrique Barboza
2026-06-04 13:12 ` [RFC PATCH 00/25] target/riscv/debug: Sdtrig fixes and TT Ascalon support Daniel Henrique Barboza
2026-07-03 21:36 ` Daniel Henrique Barboza
2026-07-04  3:22   ` Chao Liu
     [not found] ` <20260114044701.1173347-3-npiggin@gmail.com>
2026-07-06  6:13   ` [RFC PATCH 02/25] target/riscv/debug: Handle changing trigger types Chao Liu
     [not found] ` <20260114044701.1173347-4-npiggin@gmail.com>
2026-06-04 10:10   ` [RFC PATCH 03/25] target/riscv/debug: Implement permissive type unavailable trigger Daniel Henrique Barboza
2026-07-06  6:13   ` Chao Liu [this message]

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