From: Max Chou <max.chou@sifive.com>
To: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Chao Liu <chao.liu@processmission.com>,
Frank Chang <frank.chang@sifive.com>
Subject: Re: [PATCH 2/5] target/riscv: Add SiFive custom int8 matmul extension implied rules
Date: Fri, 7 Aug 2026 16:32:10 +0800 [thread overview]
Message-ID: <anWW2Z-t0OEqZFt2@sifive.com> (raw)
In-Reply-To: <0a052a0c-ab06-410a-a163-4ca6e8b7211f@oss.qualcomm.com>
On 2026-08-06 18:07, Daniel Henrique Barboza wrote:
>
>
> On 7/21/2026 9:20 AM, Max Chou wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > Add SiFive custom int8 matmul extension implied rules to enable the
> > implied extensions of SiFive custom int8 matmul extension recursively.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > Signed-off-by: Max Chou <max.chou@sifive.com>
> > ---
> > target/riscv/cpu.c | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index e643d7c7af..70baa054f9 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -2811,6 +2811,24 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {
> > },
> > };
> > +static RISCVCPUImpliedExtsRule XSFVQMACCDOD_IMPLIED = {
> > + .ext = CPU_CFG_OFFSET(ext_xsfvqmaccdod),
> > + .implied_multi_exts = {
> > + CPU_CFG_OFFSET(ext_zve32x),
> > +
> > + RISCV_IMPLIED_EXTS_RULE_END
> > + },
> > +};
> > +
> > +static RISCVCPUImpliedExtsRule XSFVQMACCQOQ_IMPLIED = {
> > + .ext = CPU_CFG_OFFSET(ext_xsfvqmaccqoq),
> > + .implied_multi_exts = {
> > + CPU_CFG_OFFSET(ext_zve32x),
> > +
> > + RISCV_IMPLIED_EXTS_RULE_END
> > + },
> > +};
> > +
> > RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
> > &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> > &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED,
> > @@ -2832,6 +2850,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
> > &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SHA_IMPLIED,
> > &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED,
> > &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED,
> > + &XSFVQMACCDOD_IMPLIED, &XSFVQMACCQOQ_IMPLIED,
>
> Not related to this patch but I wonder if we should put one rule per line
> in this array. Every once in a while we have to add a rule that is
> in a line that already has a lot of stuff, then we need to change multiple
> lines to accommodate the new rule.
>
>
Hi Daniel,
Actually, I share the same observation and thought, and I agree with
you. Let me update this part in v2.
Thanks for the suggestion!
rnax
> As for the patch:
>
>
>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
>
>
>
>
>
> > NULL
> > };
>
next prev parent reply other threads:[~2026-08-07 8:32 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-21 12:20 [PATCH 0/5] target/riscv: Add SiFive Xsfvqmaccdod/Xsfvqmaccqoq int8 matmul extensions Max Chou
2026-07-21 12:20 ` [PATCH 1/5] target/riscv: Add cfg property for SiFive " Max Chou
2026-08-06 21:04 ` Daniel Henrique Barboza
2026-07-21 12:20 ` [PATCH 2/5] target/riscv: Add SiFive custom int8 matmul extension implied rules Max Chou
2026-08-06 21:07 ` Daniel Henrique Barboza
2026-08-07 8:32 ` Max Chou [this message]
2026-07-21 12:20 ` [PATCH 3/5] target/riscv: rvv: Add SiFive custom int8 matmul instructions Max Chou
2026-08-06 21:13 ` Daniel Henrique Barboza
2026-08-07 8:50 ` Max Chou
2026-07-21 12:20 ` [PATCH 4/5] disas/riscv: Add disassembler support for Xsfvqmaccdod/Xsfvqmaccqoq Max Chou
2026-08-06 21:15 ` Daniel Henrique Barboza
2026-07-21 12:20 ` [PATCH 5/5] tests/tcg/riscv64: Add tests for SiFive int8 matmul extensions Max Chou
2026-08-06 21:15 ` Daniel Henrique Barboza
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