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From: "Alexandre Courbot" <acourbot@nvidia.com>
To: "Zhi Wang" <zhiw@nvidia.com>
Cc: <rust-for-linux@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <dakr@kernel.org>,
	<aliceryhl@google.com>, <bhelgaas@google.com>,
	<kwilczynski@kernel.org>, <ojeda@kernel.org>, <boqun@kernel.org>,
	<gary@garyguo.net>, <bjorn3_gh@protonmail.com>,
	<lossin@kernel.org>, <a.hindborg@kernel.org>, <tmgross@umich.edu>,
	<markus.probst@posteo.de>, <cjia@nvidia.com>, <smitra@nvidia.com>,
	<ankita@nvidia.com>, <aniketa@nvidia.com>, <kwankhede@nvidia.com>,
	<targupta@nvidia.com>, <kjaju@nvidia.com>, <alkumar@nvidia.com>,
	<joelagnelf@nvidia.com>, <jhubbard@nvidia.com>,
	<zhiwang@kernel.org>
Subject: Re: [PATCH v6 1/1] rust: pci: add extended capability and SR-IOV support
Date: Sun, 09 Aug 2026 11:28:08 +0900	[thread overview]
Message-ID: <DKK246QYKWR1.I2FB90993SZS@nvidia.com> (raw)
In-Reply-To: <20260804121116.23d9347d@inno-dell>

On Tue Aug 4, 2026 at 6:11 PM JST, Zhi Wang wrote:
<...>
>> > +/// SR-IOV register layout per PCIe spec (64 bytes starting at cap
>> > offset). +#[repr(C)]
>> > +#[derive(FromBytes, IntoBytes)]
>> > +pub struct ExtSriovRegs {
>> > +    /// Extended capability header.
>> > +    pub header: u32,
>> > +    /// SR-IOV capabilities.
>> > +    pub cap: u32,
>> > +    /// SR-IOV control.
>> > +    pub ctrl: u16,
>> > +    /// SR-IOV status.
>> > +    pub status: u16,
>> > +    /// Initial VFs.
>> > +    pub initial_vfs: u16,
>> > +    /// Total VFs.
>> > +    pub total_vfs: u16,
>> > +    /// Number of VFs.
>> > +    pub num_vfs: u16,
>> > +    /// Function dependency link.
>> > +    pub func_dep_link: u8,
>> > +    _reserved_0: u8,
>> > +    /// First VF offset.
>> > +    pub vf_offset: u16,
>> > +    /// VF stride.
>> > +    pub vf_stride: u16,
>> > +    _reserved_1: u16,
>> > +    /// VF device ID.
>> > +    pub vf_device_id: u16,
>> > +    /// Supported page sizes.
>> > +    pub supported_page_sizes: u32,
>> > +    /// System page size.
>> > +    pub system_page_size: u32,
>> > +    /// VF BARs (BAR0–BAR5).
>> > +    pub vf_bar: [u32; NUM_VF_BARS],
>> > +    /// VF migration state array offset.
>> > +    pub migration_state: u32,
>> > +}
>> 
>> Side-note: It would be interesting if we could end up representing
>> every I/O space this way, although padding and keeping the fields
>> offsets visible would make this challenging. But if we can eventually
>> generalize this, then I guess we can retire the `register!` macro. :)
>> 
>
> That sounds interesting idea. :) My understanding is io projection
> covers the operations of the registers but not about the fields in the
> registers. Are you thinking to extend it to cover the register fields
> as well?

Registers are basically bitfields with I/O location information. If you
store a bitfield type in the struct, and use projections to access it,
then you can access the individual fields through the bitfield type.

      reply	other threads:[~2026-08-09  2:28 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-30 18:29 [PATCH v6 0/1] Rust PCI capability infrastructure and SR-IOV support Zhi Wang
2026-07-30 18:29 ` [PATCH v6 1/1] rust: pci: add extended capability " Zhi Wang
2026-07-30 18:45   ` Gary Guo
2026-07-31  9:32     ` Zhi Wang
2026-07-31  9:57     ` Alexandre Courbot
2026-07-31 12:38       ` Gary Guo
2026-07-31 12:52         ` Alexandre Courbot
2026-07-31 10:35   ` Alexandre Courbot
2026-08-04  9:11     ` Zhi Wang
2026-08-09  2:28       ` Alexandre Courbot [this message]

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