[PATCH v5 0/6] Add support for Blaize BLZP1600 SoC

[PATCH v5 0/6] Add support for Blaize BLZP1600 SoC

[Niko Pasaloukos]

Blaize, Inc. (www.blaize.com) is a SoC designer and manufacturer
with integrated programmable Graph-Streaming-Processors for AI
and ML. This series adds support for the Blaize BLZP1600 SoC.

The SoC can run as either a PCIe based accelerator in a host
system, or as a stand alone SoC running Linux on its integrated
dual core ARM Cortex A53 cluster.

The SoC includes a suite of peripherals, support for which will
be added later.

This first series is just the basics to get the upstream
kernel to boot with a UART console and ARM SCMI based
clocks and resets.

V5 changes:
 * Add more information on patches and on files
 * Rename arch to ARCH_BLAIZE

V4 changes:
 * Add maintainer for blaize in arm64 dts
 * Fix Blaize schema & dts code style
 * Add range and reserved-memory as suggested

V3 changes:
 * Removed unnecessary dt-bindings
 * Update SoBs

V2 changes:
 * Update SoBs
 * `make dtbs_check` has no warnings
 * Fix dts names and removed dead code
 * DTS is separated from anything else

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
Nikolaos Pasaloukos (6):
      dt-bindings: Add Blaize vendor prefix
      dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
      arm64: Add Blaize BLZP1600 SoC family
      arm64: Add initial support for Blaize BLZP1600 CB2
      arm64: defconfig: Enable Blaize BLZP1600 platform
      MAINTAINER: Add entry for Blaize SoC

 Documentation/devicetree/bindings/arm/blaize.yaml  |  40 ++++
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 MAINTAINERS                                        |   9 +
 arch/arm64/Kconfig.platforms                       |   5 +
 arch/arm64/boot/dts/Makefile                       |   1 +
 arch/arm64/boot/dts/blaize/Makefile                |   2 +
 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts |  83 +++++++++
 .../arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi |  23 +++
 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi    | 205 +++++++++++++++++++++
 arch/arm64/configs/defconfig                       |   1 +
 10 files changed, 371 insertions(+)
---
base-commit: 83d67c257f4d045ff477309b5617d931f9a7be66
change-id: 20241111-blaize-blzp1600_init_board_support-1128194ca976

Best regards,
-- 
Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>

Re: [PATCH v5 0/6] Add support for Blaize BLZP1600 SoC

[Arnd Bergmann]

On Fri, Nov 15, 2024, at 15:58, Niko Pasaloukos wrote:
> Blaize, Inc. (www.blaize.com) is a SoC designer and manufacturer
> with integrated programmable Graph-Streaming-Processors for AI
> and ML. This series adds support for the Blaize BLZP1600 SoC.
>
> The SoC can run as either a PCIe based accelerator in a host
> system, or as a stand alone SoC running Linux on its integrated
> dual core ARM Cortex A53 cluster.
>
> The SoC includes a suite of peripherals, support for which will
> be added later.
>
> This first series is just the basics to get the upstream
> kernel to boot with a UART console and ARM SCMI based
> clocks and resets.
>

Hi Niko,

This version looks good to me, but it's likely that others
still have review comments. Either way I should let you know
of the next steps for merging the series.

Since the 6.13 development cycle is now over (the
merge window starts once Linus publishes 6.12
this weekend), the earliest release to merge this
into is now 6.14.

Once 6.13-rc1 is out and the patch review is complete,
you can submit the patches for inclusion by sending
to:soc@lists.linux.dev (formerly soc@kernel.org).
This is usually done as a pull request, but separate
patches are fine as well, especially if you don't yet
have a kernel.org account.

After the entry to the MAINTAINERS file is merged,
I suggest you also apply for a kernel.org account,
see [1]. You probably also read the documentation at
[2] about the usual process, let me know if you
have questions about that.

       Arnd

[1] https://korg.docs.kernel.org/accounts.html
[2] https://www.kernel.org/doc/Documentation/process/maintainer-soc.rst

Re: [PATCH v5 0/6] Add support for Blaize BLZP1600 SoC

[Nikolaos Pasaloukos]

On 15/11/2024 15:09, Arnd Bergmann wrote:

> On Fri, Nov 15, 2024, at 15:58, Niko Pasaloukos wrote:
>> Blaize, Inc. (http://www.blaize.com) is a SoC designer and manufacturer
>> with integrated programmable Graph-Streaming-Processors for AI
>> and ML. This series adds support for the Blaize BLZP1600 SoC.
>>
>> The SoC can run as either a PCIe based accelerator in a host
>> system, or as a stand alone SoC running Linux on its integrated
>> dual core ARM Cortex A53 cluster.
>>
>> The SoC includes a suite of peripherals, support for which will
>> be added later.
>>
>> This first series is just the basics to get the upstream
>> kernel to boot with a UART console and ARM SCMI based
>> clocks and resets.
>>
> Hi Niko,
>
> This version looks good to me, but it's likely that others
> still have review comments. Either way I should let you know
> of the next steps for merging the series.
>
> Since the 6.13 development cycle is now over (the
> merge window starts once Linus publishes 6.12
> this weekend), the earliest release to merge this
> into is now 6.14.
>
> Once 6.13-rc1 is out and the patch review is complete,
> you can submit the patches for inclusion by sending
> to:soc@lists.linux.dev (formerly soc@kernel.org).
> This is usually done as a pull request, but separate
> patches are fine as well, especially if you don't yet
> have a kernel.org account.
>
> After the entry to the MAINTAINERS file is merged,
> I suggest you also apply for a kernel.org account,
> see [1]. You probably also read the documentation at
> [2] about the usual process, let me know if you
> have questions about that.
>
>         Arnd
>
> [1] https://urldefense.com/v3/__https://korg.docs.kernel.org/accounts.html__;!!FddXBOku!ny-gN1hGaRTxNpi1ADJf_s3xLmuIdAZzGy4uj6kacOw-p3lLhZfSFLF2Mb9UcuIbd1By_ERGVnHqEbEiXhbK1g$
> [2] https://urldefense.com/v3/__https://www.kernel.org/doc/Documentation/process/maintainer-soc.rst__;!!FddXBOku!ny-gN1hGaRTxNpi1ADJf_s3xLmuIdAZzGy4uj6kacOw-p3lLhZfSFLF2Mb9UcuIbd1By_ERGVnHqEbHSKH7PdA$

Hi Arnd,

Thank you very much for the detailed explanation of the merging process and release
cycles.
Also, I would like to thank all the people who help me during the review process
and for their helpful comments.

Best regards,
Niko

[PATCH v5 0/6] Add support for Blaize BLZP1600 SoC

[Nikolaos Pasaloukos via B4 Relay]

Blaize, Inc. (www.blaize.com) is a SoC designer and manufacturer
with integrated programmable Graph-Streaming-Processors for AI
and ML. This series adds support for the Blaize BLZP1600 SoC.

The SoC can run as either a PCIe based accelerator in a host
system, or as a stand alone SoC running Linux on its integrated
dual core ARM Cortex A53 cluster.

The SoC includes a suite of peripherals, support for which will
be added later.

This first series is just the basics to get the upstream
kernel to boot with a UART console and ARM SCMI based
clocks and resets.

Resending V5 with tags applied and 'From' fixed.

V5 changes:
 * Add more information on patches and on files
 * Rename arch to ARCH_BLAIZE

V4 changes:
 * Add maintainer for blaize in arm64 dts
 * Fix Blaize schema & dts code style
 * Add range and reserved-memory as suggested

V3 changes:
 * Removed unnecessary dt-bindings
 * Update SoBs

V2 changes:
 * Update SoBs
 * `make dtbs_check` has no warnings
 * Fix dts names and removed dead code
 * DTS is separated from anything else

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
Nikolaos Pasaloukos (6):
      dt-bindings: Add Blaize vendor prefix
      dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
      arm64: Add Blaize BLZP1600 SoC family
      arm64: dts: Add initial support for Blaize BLZP1600 CB2
      arm64: defconfig: Enable Blaize BLZP1600 platform
      MAINTAINER: Add entry for Blaize SoC

 Documentation/devicetree/bindings/arm/blaize.yaml  |  40 ++++
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 MAINTAINERS                                        |   9 +
 arch/arm64/Kconfig.platforms                       |   5 +
 arch/arm64/boot/dts/Makefile                       |   1 +
 arch/arm64/boot/dts/blaize/Makefile                |   2 +
 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts |  83 +++++++++
 .../arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi |  23 +++
 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi    | 205 +++++++++++++++++++++
 arch/arm64/configs/defconfig                       |   1 +
 10 files changed, 371 insertions(+)
---
base-commit: 83d67c257f4d045ff477309b5617d931f9a7be66
change-id: 20241111-blaize-blzp1600_init_board_support-1128194ca976

Best regards,
-- 
Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>

[PATCH v5 1/6] dt-bindings: Add Blaize vendor prefix

[Nikolaos Pasaloukos via B4 Relay]

From: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>

Blaize, Inc. (www.blaize.com) is a SoC manufacturer with integrated
programmable Graph-Streaming-Processors for AI and ML.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index b320a39de7fe40ce4d97ed3ea264a5971a3428dd..809086061a1992567ca6c5d404fbcee8a33ee300 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -216,6 +216,8 @@ patternProperties:
     description: Shenzhen BigTree Tech Co., LTD
   "^bitmain,.*":
     description: Bitmain Technologies
+  "^blaize,.*":
+    description: Blaize, Inc.
   "^blutek,.*":
     description: BluTek Power
   "^boe,.*":

-- 
2.43.0

[PATCH v5 2/6] dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC

[Nikolaos Pasaloukos via B4 Relay]

From: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>

Add device tree bindings for the Blaize BLZP1600 CB2 development
board (carrier board). This board integrates a Blaize BLZP1600
SoM (System on Module) which is based on the Blaize BLZP1600 SoC.

The Blaize BLZP1600 SoC integrates a dual core ARM Cortex A53
cluster and a Blaize Graph Streaming Processor for AI and ML
workloads, plus a suite of connectivity and other peripherals.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/arm/blaize.yaml | 40 +++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/blaize.yaml b/Documentation/devicetree/bindings/arm/blaize.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..af39e2756407baacee3030f6909cf2aa7dc5776c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/blaize.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/blaize.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Blaize Platforms
+
+maintainers:
+  - James Cowgill <james.cowgill@blaize.com>
+  - Matt Redfearn <matt.redfearn@blaize.com>
+  - Neil Jones <neil.jones@blaize.com>
+  - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
+
+description: |
+  Blaize Platforms using SoCs designed by Blaize Inc.
+
+  The products based on the BLZP1600 SoC:
+
+  - BLZP1600-SoM: SoM (System on Module)
+  - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
+
+  BLZP1600 SoC integrates a dual core ARM Cortex A53 cluster
+  and a Blaize Graph Streaming Processor for AI and ML workloads,
+  plus a suite of connectivity and other peripherals.
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Blaize BLZP1600 based boards
+        items:
+          - enum:
+              - blaize,blzp1600-cb2
+          - const: blaize,blzp1600
+
+additionalProperties: true
+
+...

-- 
2.43.0

[PATCH v5 3/6] arm64: Add Blaize BLZP1600 SoC family

[Nikolaos Pasaloukos via B4 Relay]

From: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>

Add ARCH_BLAIZE SoC family to the arm64 architecture to
support the BLZP1600 System-On-Module and the Carrier-Board-2
development board.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/Kconfig.platforms | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6c6d11536b42ec6e878db8d355c17994c2500d7b..08dd5b3b2d7381a01bd5c4347c29202edff3495f 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -101,6 +101,11 @@ config ARCH_BITMAIN
 	help
 	  This enables support for the Bitmain SoC Family.
 
+config ARCH_BLAIZE
+	bool "Blaize SoC Platforms"
+	help
+	  This enables support for the Blaize SoC family
+
 config ARCH_EXYNOS
 	bool "Samsung Exynos SoC family"
 	select COMMON_CLK_SAMSUNG

-- 
2.43.0

[PATCH v5 4/6] arm64: dts: Add initial support for Blaize BLZP1600 CB2

[Nikolaos Pasaloukos via B4 Relay]

From: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>

Add support for the Blaize CB2 development board based on
the BLZP1600 SoC. This consists of a Carrier-Board-2 and a
System-on-Module.

Both BLZP1600 SoM and CB2 are available as products.
CB2 (Pathfinder) has multiple peripherals like UART, I2C,
SPI, GPIO, CSI (camera), DSI (display), USB-3.0 and Ethernet.

Enable support for the Cryptocell, UART and I2C which are
already fully supported by the drivers.

The blaize-blzp1600.dtsi is the common part for the SoC,
blaize-blzp1600-som.dtsi is the common part for the SoM and
blaize-blzp1600-cb2.dts is the board specific file.

Co-developed-by: James Cowgill <james.cowgill@blaize.com>
Signed-off-by: James Cowgill <james.cowgill@blaize.com>
Co-developed-by: Matt Redfearn <matt.redfearn@blaize.com>
Signed-off-by: Matt Redfearn <matt.redfearn@blaize.com>
Co-developed-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/boot/dts/Makefile                       |   1 +
 arch/arm64/boot/dts/blaize/Makefile                |   2 +
 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts |  83 +++++++++
 .../arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi |  23 +++
 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi    | 205 +++++++++++++++++++++
 5 files changed, 314 insertions(+)

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 21cd3a87f385309c3a655a67a3bee5f0abed7545..79b73a21ddc22b17308554e502f8207392935b45 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -10,6 +10,7 @@ subdir-y += apm
 subdir-y += apple
 subdir-y += arm
 subdir-y += bitmain
+subdir-y += blaize
 subdir-y += broadcom
 subdir-y += cavium
 subdir-y += exynos
diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blaize/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7e10b3199e6c73b64c826fef1aa4058c7b3e898b
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0+
+dtb-$(CONFIG_ARCH_BLAIZE) += blaize-blzp1600-cb2.dtb
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
new file mode 100644
index 0000000000000000000000000000000000000000..7e3cef2ed3522e202487e799b2021cd45398e006
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "blaize-blzp1600-som.dtsi"
+
+/ {
+	model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
+
+	compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200";
+	};
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	status = "okay";
+
+	gpio_expander: gpio@74 {
+		compatible = "ti,tca9539";
+		reg = <0x74>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "RSP_PIN_7",	/* GPIO_0 */
+				  "RSP_PIN_11",	/* GPIO_1 */
+				  "RSP_PIN_13",	/* GPIO_2 */
+				  "RSP_PIN_15",	/* GPIO_3 */
+				  "RSP_PIN_27",	/* GPIO_4 */
+				  "RSP_PIN_29",	/* GPIO_5 */
+				  "RSP_PIN_31",	/* GPIO_6 */
+				  "RSP_PIN_33",	/* GPIO_7 */
+				  "RSP_PIN_37",	/* GPIO_8 */
+				  "RSP_PIN_16",	/* GPIO_9 */
+				  "RSP_PIN_18",	/* GPIO_10 */
+				  "RSP_PIN_22",	/* GPIO_11 */
+				  "RSP_PIN_28",	/* GPIO_12 */
+				  "RSP_PIN_32",	/* GPIO_13 */
+				  "RSP_PIN_36",	/* GPIO_14 */
+				  "TP31";	/* GPIO_15 */
+	};
+
+	gpio_expander_m2: gpio@75 {
+		compatible = "ti,tca9539";
+		reg = <0x75>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "M2_W_DIS1_N",	/* GPIO_0 */
+				  "M2_W_DIS2_N",	/* GPIO_1 */
+				  "M2_UART_WAKE_N",	/* GPIO_2 */
+				  "M2_COEX3",		/* GPIO_3 */
+				  "M2_COEX_RXD",	/* GPIO_4 */
+				  "M2_COEX_TXD",	/* GPIO_5 */
+				  "M2_VENDOR_PIN40",	/* GPIO_6 */
+				  "M2_VENDOR_PIN42",	/* GPIO_7 */
+				  "M2_VENDOR_PIN38",	/* GPIO_8 */
+				  "M2_SDIO_RST_N",	/* GPIO_9 */
+				  "M2_SDIO_WAKE_N",	/* GPIO_10 */
+				  "M2_PETN1",		/* GPIO_11 */
+				  "M2_PERP1",		/* GPIO_12 */
+				  "M2_PERN1",		/* GPIO_13 */
+				  "UIM_SWP",		/* GPIO_14 */
+				  "UART1_TO_RSP";	/* GPIO_15 */
+	};
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..bfdff5953edd95341440aa98569a019adcc0425d
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.
+ */
+
+#include "blaize-blzp1600.dtsi"
+
+/ {
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x1 0x0>;
+	};
+};
+
+/* i2c4 bus is available only on the SoM, not on the board */
+&i2c4 {
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..7d399e6a532f5b24385dd837be965be771c7d24c
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+		};
+	};
+
+	firmware {
+		scmi {
+			compatible = "arm,scmi-smc";
+			arm,smc-id = <0x82002000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			shmem = <&scmi0_shm>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			scmi_rst: protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <1>;
+			};
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* SCMI reserved buffer space on DDR space */
+		scmi0_shm: scmi-shmem@800 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x800 0x0 0x80>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = /* Physical Secure PPI */
+			     <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Physical Non-Secure PPI */
+			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Hypervisor PPI */
+			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Virtual PPI */
+			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc@200000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x2 0x0 0x850000>;
+
+		gic: interrupt-controller@410000 {
+			compatible = "arm,gic-400";
+			reg = <0x410000 0x20000>,
+			      <0x420000 0x20000>,
+			      <0x440000 0x20000>,
+			      <0x460000 0x20000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
+						 IRQ_TYPE_LEVEL_LOW)>;
+		};
+
+		uart0: serial@4d0000 {
+			compatible = "ns16550a";
+			reg = <0x4d0000 0x1000>;
+			clocks = <&scmi_clk 59>;
+			resets = <&scmi_rst 59>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart1: serial@4e0000 {
+			compatible = "ns16550a";
+			reg = <0x4e0000 0x1000>;
+			clocks = <&scmi_clk 60>;
+			resets = <&scmi_rst 60>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@4f0000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x4f0000 0x1000>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 54>;
+			resets = <&scmi_rst 54>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@500000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x500000 0x1000>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 55>;
+			resets = <&scmi_rst 55>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@510000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x510000 0x1000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 56>;
+			resets = <&scmi_rst 56>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@520000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x520000 0x1000>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 57>;
+			resets = <&scmi_rst 57>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@530000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x530000 0x1000>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 58>;
+			resets = <&scmi_rst 58>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		arm_cc712: crypto@550000 {
+			compatible = "arm,cryptocell-712-ree";
+			reg = <0x550000 0x1000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 7>;
+		};
+	};
+};

-- 
2.43.0

[PATCH v5 5/6] arm64: defconfig: Enable Blaize BLZP1600 platform

[Nikolaos Pasaloukos via B4 Relay]

From: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>

Enable ARCH_BLAIZE to support the BLZP1600 SoC and the CB2
development board.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5fdbfea7a5b295c4569f34773394ffe6eda778e9..4921669f89ae0a89e0c1489a2a4359be9698e5a2 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -44,6 +44,7 @@ CONFIG_ARCH_BCM_IPROC=y
 CONFIG_ARCH_BCMBCA=y
 CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
+CONFIG_ARCH_BLAIZE=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_SPARX5=y
 CONFIG_ARCH_K3=y

-- 
2.43.0

[PATCH v5 6/6] MAINTAINER: Add entry for Blaize SoC

[Nikolaos Pasaloukos via B4 Relay]

From: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>

Add MAINTAINERS entry for Blaize SoC platform with a list of
maintainers.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
 MAINTAINERS | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 273a84483b74543b510de7b08804bbd1f6514358..43846a23f9d990ae9fe066e65ed2bdd36376e327 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2238,6 +2238,15 @@ F:	arch/arm64/boot/dts/bitmain/
 F:	drivers/clk/clk-bm1880.c
 F:	drivers/pinctrl/pinctrl-bm1880.c
 
+ARM/BLAIZE ARCHITECTURE
+M:	James Cowgill <james.cowgill@blaize.com>
+M:	Matt Redfearn <matt.redfearn@blaize.com>
+M:	Neil Jones <neil.jones@blaize.com>
+M:	Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/arm/blaize.yaml
+F:	arch/arm64/boot/dts/blaize/
+
 ARM/CALXEDA HIGHBANK ARCHITECTURE
 M:	Andre Przywara <andre.przywara@arm.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

-- 
2.43.0

Re: [PATCH v5 6/6] MAINTAINER: Add entry for Blaize SoC

[Krzysztof Kozlowski]

On Wed, Dec 04, 2024 at 04:05:29PM +0000, Nikolaos Pasaloukos wrote:
> Add MAINTAINERS entry for Blaize SoC platform with a list of
> maintainers.
> 
> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> ---
>  MAINTAINERS | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 273a84483b74543b510de7b08804bbd1f6514358..43846a23f9d990ae9fe066e65ed2bdd36376e327 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2238,6 +2238,15 @@ F:	arch/arm64/boot/dts/bitmain/
>  F:	drivers/clk/clk-bm1880.c
>  F:	drivers/pinctrl/pinctrl-bm1880.c
>  
> +ARM/BLAIZE ARCHITECTURE
> +M:	James Cowgill <james.cowgill@blaize.com>
> +M:	Matt Redfearn <matt.redfearn@blaize.com>
> +M:	Neil Jones <neil.jones@blaize.com>
> +M:	Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>

Just to be clear: this is list of active maintainers, so all above are
supposed to perform reviews or maintainer duties. This is not
credits/managers/I-need-to-please-someone list.

With the assumption these are active maintainers:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

They should also ack it to confirm they understand the burden.

Best regards,
Krzysztof

Re: [PATCH v5 6/6] MAINTAINER: Add entry for Blaize SoC

[Matt Redfearn]

On 05/12/2024 08:16, Krzysztof Kozlowski wrote:
> On Wed, Dec 04, 2024 at 04:05:29PM +0000, Nikolaos Pasaloukos wrote:
>> Add MAINTAINERS entry for Blaize SoC platform with a list of
>> maintainers.
>>
>> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
>> ---
>>   MAINTAINERS | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 273a84483b74543b510de7b08804bbd1f6514358..43846a23f9d990ae9fe066e65ed2bdd36376e327 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -2238,6 +2238,15 @@ F:	arch/arm64/boot/dts/bitmain/
>>   F:	drivers/clk/clk-bm1880.c
>>   F:	drivers/pinctrl/pinctrl-bm1880.c
>>   
>> +ARM/BLAIZE ARCHITECTURE
>> +M:	James Cowgill <james.cowgill@blaize.com>
>> +M:	Matt Redfearn <matt.redfearn@blaize.com>
>> +M:	Neil Jones <neil.jones@blaize.com>
>> +M:	Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> Just to be clear: this is list of active maintainers, so all above are
> supposed to perform reviews or maintainer duties. This is not
> credits/managers/I-need-to-please-someone list.

Hi Krzysztof,

Yes, I will be an active maintainer of the board upstream.

>
> With the assumption these are active maintainers:
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> They should also ack it to confirm they understand the burden.

Acked-by: Matt Redfearn <matt.redfearn@blaize.com>


A question about process: should Niko resend V5 with all of the acks?

Thanks,

Matt


>
> Best regards,
> Krzysztof
>

Re: [PATCH v5 6/6] MAINTAINER: Add entry for Blaize SoC

[Krzysztof Kozlowski]

On 05/12/2024 12:22, Matt Redfearn wrote:
>>
>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> They should also ack it to confirm they understand the burden.
> 
> Acked-by: Matt Redfearn <matt.redfearn@blaize.com>
> 
> 
> A question about process: should Niko resend V5 with all of the acks?

Normally not, here however after finished review expectation was to send
it to soc tree (I think Arnd described the process).

Best regards,
Krzysztof

Re: [PATCH v5 6/6] MAINTAINER: Add entry for Blaize SoC

[James Cowgill]

On 05/12/2024 08:16, Krzysztof Kozlowski wrote:
> On Wed, Dec 04, 2024 at 04:05:29PM +0000, Nikolaos Pasaloukos wrote:
>> Add MAINTAINERS entry for Blaize SoC platform with a list of
>> maintainers.
>>
>> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
>> ---
>>  MAINTAINERS | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 273a84483b74543b510de7b08804bbd1f6514358..43846a23f9d990ae9fe066e65ed2bdd36376e327 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -2238,6 +2238,15 @@ F:	arch/arm64/boot/dts/bitmain/
>>  F:	drivers/clk/clk-bm1880.c
>>  F:	drivers/pinctrl/pinctrl-bm1880.c
>>  
>> +ARM/BLAIZE ARCHITECTURE
>> +M:	James Cowgill <james.cowgill@blaize.com>
>> +M:	Matt Redfearn <matt.redfearn@blaize.com>
>> +M:	Neil Jones <neil.jones@blaize.com>
>> +M:	Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> 
> Just to be clear: this is list of active maintainers, so all above are
> supposed to perform reviews or maintainer duties. This is not
> credits/managers/I-need-to-please-someone list.
> 
> With the assumption these are active maintainers:
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> They should also ack it to confirm they understand the burden.

Acked-by: James Cowgill <james.cowgill@blaize.com>

James

Re: [PATCH v5 6/6] MAINTAINER: Add entry for Blaize SoC

[Neil Jones]

On 05/12/2024 08:16, Krzysztof Kozlowski wrote:

> On Wed, Dec 04, 2024 at 04:05:29PM +0000, Nikolaos Pasaloukos wrote:
>> Add MAINTAINERS entry for Blaize SoC platform with a list of
>> maintainers.
>>
>> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
>> ---
>>   MAINTAINERS | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 273a84483b74543b510de7b08804bbd1f6514358..43846a23f9d990ae9fe066e65ed2bdd36376e327 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -2238,6 +2238,15 @@ F:	arch/arm64/boot/dts/bitmain/
>>   F:	drivers/clk/clk-bm1880.c
>>   F:	drivers/pinctrl/pinctrl-bm1880.c
>>   
>> +ARM/BLAIZE ARCHITECTURE
>> +M:	James Cowgill <james.cowgill@blaize.com>
>> +M:	Matt Redfearn <matt.redfearn@blaize.com>
>> +M:	Neil Jones <neil.jones@blaize.com>
>> +M:	Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> Just to be clear: this is list of active maintainers, so all above are
> supposed to perform reviews or maintainer duties. This is not
> credits/managers/I-need-to-please-someone list.
>
> With the assumption these are active maintainers:
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> They should also ack it to confirm they understand the burden.
>
> Best regards,
> Krzysztof
>
Acked-by: Neil Jones <neil.jones@blaize.com>

Cheers,

Neil

On 05/12/2024 08:16, Krzysztof Kozlowski wrote:
> On Wed, Dec 04, 2024 at 04:05:29PM +0000, Nikolaos Pasaloukos wrote:
>> Add MAINTAINERS entry for Blaize SoC platform with a list of
>> maintainers.
>>
>> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
>> ---
>>   MAINTAINERS | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 273a84483b74543b510de7b08804bbd1f6514358..43846a23f9d990ae9fe066e65ed2bdd36376e327 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -2238,6 +2238,15 @@ F:	arch/arm64/boot/dts/bitmain/
>>   F:	drivers/clk/clk-bm1880.c
>>   F:	drivers/pinctrl/pinctrl-bm1880.c
>>   
>> +ARM/BLAIZE ARCHITECTURE
>> +M:	James Cowgill <james.cowgill@blaize.com>
>> +M:	Matt Redfearn <matt.redfearn@blaize.com>
>> +M:	Neil Jones <neil.jones@blaize.com>
>> +M:	Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> Just to be clear: this is list of active maintainers, so all above are
> supposed to perform reviews or maintainer duties. This is not
> credits/managers/I-need-to-please-someone list.
>
> With the assumption these are active maintainers:
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> They should also ack it to confirm they understand the burden.
>
> Best regards,
> Krzysztof
>

Re: [PATCH v5 0/6] Add support for Blaize BLZP1600 SoC

[patchwork-bot+linux-soc]

Hello:

This series was applied to soc/soc.git (for-next)
by Arnd Bergmann <arnd@arndb.de>:

On Wed, 04 Dec 2024 16:05:23 +0000 you wrote:
> Blaize, Inc. (www.blaize.com) is a SoC designer and manufacturer
> with integrated programmable Graph-Streaming-Processors for AI
> and ML. This series adds support for the Blaize BLZP1600 SoC.
> 
> The SoC can run as either a PCIe based accelerator in a host
> system, or as a stand alone SoC running Linux on its integrated
> dual core ARM Cortex A53 cluster.
> 
> [...]

Here is the summary with links:
  - [v5,1/6] dt-bindings: Add Blaize vendor prefix
    https://git.kernel.org/soc/soc/c/1fa9ce7e525d
  - [v5,2/6] dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
    https://git.kernel.org/soc/soc/c/f156403c2c8d
  - [v5,3/6] arm64: Add Blaize BLZP1600 SoC family
    https://git.kernel.org/soc/soc/c/c0b454a51755
  - [v5,4/6] arm64: dts: Add initial support for Blaize BLZP1600 CB2
    https://git.kernel.org/soc/soc/c/2e976f19d9c2
  - [v5,5/6] arm64: defconfig: Enable Blaize BLZP1600 platform
    https://git.kernel.org/soc/soc/c/b0837ce07980
  - [v5,6/6] MAINTAINER: Add entry for Blaize SoC
    https://git.kernel.org/soc/soc/c/d4c0d167b1f6

You are awesome, thank you!
-- 
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