[RFC PATCH 0/2] ARM: mstar: Internal bus madness

[Daniel Palmer <daniel@0x0f.com>]

The MStar/SigmaStar SoCs have some very weird internal
bus bridges called RIU and XIU. These seem to be a left
over from when the CPU core was 8051 or MIPS.

Basically they act as a bridge between the ARM CPU and the
lump of standard peripherals (ethernet, usb, sd host etc)
that has been used throughout all of their designs.

RIU has 16bit registers 32bits apart from the CPU view while
XIU has 32bit registers 64bits apart from the CPU view.
Older chips (MSC313) only have RIU, newer chips (MSC313E)
have both RIU and XIU with some IPs accessible via RIU with
the original address and via XIU with an additional address.
To make things really fun some IPs (memory mapped ethernet PHY)
have registers that are completely accessible via RIU but only
partially accessible via XIU.

The main issue is for non-MStar IPs connected to these bridges.
All of the MStar IPs seem to have 16bit registers but the
ethernet controller and usb controller are third party and
have 32bit registers.

The kernel drivers expect the registers to be at normal
offsets and not broken into two parts so they don't work
out of the box here.

I want to hide this stuff as much as possible so it seemed
like a good idea to hide it in a header and use the headers
in the unfortunate drivers.

RFC because maybe this isn't the right approach and I'm
sure the two readw()/writew()s for RIU need to be protected
somehow but I wasn't sure how.

Daniel Palmer (2):
  ARM: mstar: Add header with macros for RIU register access
  ARM: mstar: Add header with macros for XIU register access

 MAINTAINERS             |  1 +
 include/soc/mstar/riu.h | 28 ++++++++++++++++++++++++++++
 include/soc/mstar/xiu.h | 22 ++++++++++++++++++++++
 3 files changed, 51 insertions(+)
 create mode 100644 include/soc/mstar/riu.h
 create mode 100644 include/soc/mstar/xiu.h

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2.31.0