From: Stephen Boyd <sboyd@kernel.org>
To: Qin Jian <qinjian@cqplus1.com>
Cc: krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
mturquette@baylibre.com, linux@armlinux.org.uk, arnd@arndb.de,
olof@lixom.net, soc@kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
Qin Jian <qinjian@cqplus1.com>
Subject: Re: [PATCH v18 05/10] clk: Add Sunplus SP7021 clock driver
Date: Tue, 14 Jun 2022 12:25:53 -0700 [thread overview]
Message-ID: <20220614192555.86436C3411B@smtp.kernel.org> (raw)
In-Reply-To: <42ed93cf0e5cfeaffdf50d63da558a3f1f6c1021.1655194858.git.qinjian@cqplus1.com>
Quoting Qin Jian (2022-06-14 01:31:04)
> diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c
> new file mode 100644
> index 000000000..0caef1bc7
> --- /dev/null
> +++ b/drivers/clk/clk-sp7021.c
> @@ -0,0 +1,725 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
This isn't a common license on driver files. Is it intended? Or
copy/paste from DT?
> +/*
> + * Copyright (C) Sunplus Technology Co., Ltd.
> + * All rights reserved.
> + */
[...]
> +
> +static int sp7021_clk_probe(struct platform_device *pdev)
> +{
[...]
> +
> + /* gates */
> + for (i = 0; i < ARRAY_SIZE(sp_clk_gates); i++) {
> + char name[10];
> + u32 j = sp_clk_gates[i].reg;
> + struct clk_parent_data *pd = sp_clk_gates[i].ext_parent ? &pd_ext : &pd_sys;
> +
> + sprintf(name, "%02d_0x%02x", i, j);
> + hws[i] = clk_hw_register_gate_parent_data(dev, name, pd, 0,
This needs to be devm as well. Otherwise if the driver is unbound we'll
leak these registered clks.
> + clk_base + (j >> 4) * 4,
> + j & 0x0f,
> + CLK_GATE_HIWORD_MASK,
> + NULL);
> + if (IS_ERR(hws[i])) {
> + ret = PTR_ERR(hws[i]);
> + goto unregister_gates;
> + }
> + }
> +
> + clk_data->num = CLK_MAX;
> + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
> + if (ret)
> + goto unregister_gates;
> +
> + return 0;
> +
> +unregister_gates:
> + while (i--)
> + clk_hw_unregister_gate(hws[i]);
> +
> + return ret;
> +}
> +
next prev parent reply other threads:[~2022-06-14 19:25 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-14 8:30 [PATCH v18 00/10] Add Sunplus SP7021 SoC Support Qin Jian
2022-06-14 8:31 ` [PATCH v18 01/10] dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards Qin Jian
2022-06-14 8:31 ` [PATCH v18 02/10] dt-bindings: reset: Add bindings for SP7021 reset driver Qin Jian
2022-06-14 8:31 ` [PATCH v18 03/10] reset: Add Sunplus " Qin Jian
2022-06-14 14:50 ` Randy Dunlap
2022-06-14 8:31 ` [PATCH v18 04/10] dt-bindings: clock: Add bindings for SP7021 clock driver Qin Jian
2022-06-14 19:26 ` Stephen Boyd
2022-06-14 8:31 ` [PATCH v18 05/10] clk: Add Sunplus " Qin Jian
2022-06-14 10:44 ` Arnd Bergmann
2022-06-15 3:43 ` qinjian[覃健]
2022-06-14 19:25 ` Stephen Boyd [this message]
2022-06-15 2:25 ` qinjian[覃健]
2022-06-15 19:01 ` Stephen Boyd
2022-06-14 8:31 ` [PATCH v18 06/10] dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller Qin Jian
2022-06-14 8:31 ` [PATCH v18 07/10] irqchip: Add Sunplus SP7021 interrupt controller driver Qin Jian
2022-06-14 8:31 ` [PATCH v18 08/10] ARM: sunplus: Add initial support for Sunplus SP7021 SoC Qin Jian
2022-06-14 14:51 ` Randy Dunlap
2022-06-14 8:31 ` [PATCH v18 09/10] ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig Qin Jian
2022-06-14 8:31 ` [PATCH v18 10/10] ARM: dts: Add Sunplus SP7021-Demo-V3 board device tree Qin Jian
2022-06-14 10:42 ` Arnd Bergmann
2022-06-15 3:31 ` qinjian[覃健]
2022-06-15 14:02 ` Krzysztof Kozlowski
2022-06-19 14:12 ` Pavel Machek
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