Linux SOC development
 help / color / mirror / Atom feed
From: Conor Dooley <conor@kernel.org>
To: Emil Renner Berthing <kernel@esmil.dk>,
	Arnd Bergmann <arnd@arndb.de>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Nicolas Ferre <nicolas.ferre@microchip.com>,
	soc@kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v1 2/4] MAINTAINERS: generify the Microchip RISC-V entry name
Date: Wed,  9 Nov 2022 21:22:18 +0000	[thread overview]
Message-ID: <20221109212219.1598355-3-conor@kernel.org> (raw)
In-Reply-To: <20221109212219.1598355-1-conor@kernel.org>

From: Conor Dooley <conor.dooley@microchip.com>

These drivers work on our other FPGAs, for example the non-SoC PolarFire
connected to an FU-540 via chiplink. Make the entry a wee bit more
generic to match. While at it, remove the / from the heading so that it
matches other, neighbouring RISC-V entries.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b88ced1ff72c..a57c90be001f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17732,7 +17732,7 @@ F:	arch/riscv/
 N:	riscv
 K:	riscv
 
-RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
+RISC-V MICROCHIP FPGA SUPPORT
 M:	Conor Dooley <conor.dooley@microchip.com>
 M:	Daire McNamara <daire.mcnamara@microchip.com>
 L:	linux-riscv@lists.infradead.org
-- 
2.37.2


  parent reply	other threads:[~2022-11-09 21:23 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-09 21:22 [PATCH v1 0/4] Route RISC-V SoC drivers/firmware/DT via the soc tree Conor Dooley
2022-11-09 21:22 ` [PATCH v1 1/4] MAINTAINERS: add entries for misc. RISC-V SoC drivers and devicetrees Conor Dooley
2022-11-14  8:59   ` Nicolas Ferre
2022-11-14 19:44   ` Palmer Dabbelt
2022-11-09 21:22 ` Conor Dooley [this message]
2022-11-09 21:22 ` [PATCH v1 3/4] MAINTAINERS: add an entry for StarFive devicetrees Conor Dooley
2022-11-10  8:48   ` Emil Renner Berthing
2022-11-09 21:22 ` [PATCH v1 4/4] MAINTAINERS: repair Microchip corei2c driver entry Conor Dooley
2022-11-14 13:00 ` [PATCH v1 0/4] Route RISC-V SoC drivers/firmware/DT via the soc tree patchwork-bot+linux-soc

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221109212219.1598355-3-conor@kernel.org \
    --to=conor@kernel.org \
    --cc=aou@eecs.berkeley.edu \
    --cc=arnd@arndb.de \
    --cc=conor.dooley@microchip.com \
    --cc=kernel@esmil.dk \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=nicolas.ferre@microchip.com \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=soc@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox