[PATCH 0/8] spacemit: k3: add clock and reset support

[PATCH 0/8] spacemit: k3: add clock and reset support

[Yixun Lan]

This series try to add clock and reset driver support for SpacemiT K3 SoC,
the patches are largely based on upstream linux framework. Patch [6/8]
truncates the full clock to make it better fit for supporting SPL image.

The reset BITs definition lives in the same register with clock
controller which make them tight coupled, so I'm also putting reset
patches in this series.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Yixun Lan (8):
      clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc()
      clk: spacemit: ccu_mix: add inverted enable gate clock
      clk: spacemit: ccu_pll: add plla type clock
      clk: spacemit: k3: extract common header
      clk: spacemit: k3: add the clock tree
      clk: spacemit: k3: reduce clock tree for SPL build
      reset: spacemit: Extract common K1 reset code
      reset: spacemit: Add SpacemiT K3 reset driver

 drivers/clk/spacemit/Kconfig                   |    9 +
 drivers/clk/spacemit/Makefile                  |    1 +
 drivers/clk/spacemit/clk-k3.c                  | 2084 ++++++++++++++++++++++++
 drivers/clk/spacemit/clk_common.h              |    1 +
 drivers/clk/spacemit/clk_mix.c                 |    9 +-
 drivers/clk/spacemit/clk_mix.h                 |   27 +-
 drivers/clk/spacemit/clk_pll.c                 |  124 +-
 drivers/clk/spacemit/clk_pll.h                 |   43 +-
 drivers/reset/Kconfig                          |    1 +
 drivers/reset/Makefile                         |    2 +-
 drivers/reset/spacemit/Kconfig                 |   22 +
 drivers/reset/spacemit/Makefile                |    4 +-
 drivers/reset/spacemit/reset-spacemit-common.c |   93 ++
 drivers/reset/spacemit/reset-spacemit-common.h |   40 +
 drivers/reset/spacemit/reset-spacemit-k1.c     |  128 +-
 drivers/reset/spacemit/reset-spacemit-k3.c     |  244 +++
 include/soc/spacemit/k3-reset.h                |   21 +
 include/soc/spacemit/k3-syscon.h               |  271 +++
 18 files changed, 2992 insertions(+), 132 deletions(-)
---
base-commit: 36c377b9859ffb53eb1e39ea31e8d96d1e0fe1e5
change-id: 20260824-01-k3-clock-reset-support-815a0045526a

Best regards,
--  
Yixun Lan <dlan@kernel.org>

[PATCH 1/8] clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc()

[Yixun Lan]

Based on upstream commit:
  54e97360b44b ("clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc()")

Fix inverted condition that skips frequency change trigger,
causing kernel panics during cpufreq scaling.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 drivers/clk/spacemit/clk_mix.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/spacemit/clk_mix.c b/drivers/clk/spacemit/clk_mix.c
index a1158512a92..45bf2c72375 100644
--- a/drivers/clk/spacemit/clk_mix.c
+++ b/drivers/clk/spacemit/clk_mix.c
@@ -78,7 +78,7 @@ static int ccu_mix_trigger_fc(struct clk *clk)
 	struct ccu_common *common = clk_to_ccu_common(clk);
 	unsigned int val;
 
-	if (common->reg_fc)
+	if (!common->reg_fc)
 		return 0;
 
 	ccu_update(common, fc, common->mask_fc, common->mask_fc);

-- 
2.55.0

[PATCH 2/8] clk: spacemit: ccu_mix: add inverted enable gate clock

[Yixun Lan]

Based on upstream linux:
  ace73b7e2763 ("clk: spacemit: ccu_mix: add inverted enable gate clock")

K3 SoC has the clock IP which support to write value 0 for enabling the
clock, while write 1 for disabling it, thus the enable BIT is inverted.
So, introduce a flag to support the inverted gate clock.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 drivers/clk/spacemit/clk_mix.c |  7 +++++--
 drivers/clk/spacemit/clk_mix.h | 17 +++++++++++++----
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/spacemit/clk_mix.c b/drivers/clk/spacemit/clk_mix.c
index 45bf2c72375..b0d1a506851 100644
--- a/drivers/clk/spacemit/clk_mix.c
+++ b/drivers/clk/spacemit/clk_mix.c
@@ -33,8 +33,10 @@
 int ccu_gate_disable(struct clk *clk)
 {
 	struct ccu_mix *mix = clk_to_ccu_mix(clk);
+	struct ccu_gate_config *gate = &mix->gate;
+	u32 val = gate->inverted ? gate->mask : 0;
 
-	ccu_update(&mix->common, ctrl, mix->gate.mask, 0);
+	ccu_update(&mix->common, ctrl, gate->mask, val);
 
 	return 0;
 }
@@ -43,8 +45,9 @@ int ccu_gate_enable(struct clk *clk)
 {
 	struct ccu_mix *mix = clk_to_ccu_mix(clk);
 	struct ccu_gate_config *gate = &mix->gate;
+	u32 val = gate->inverted ? 0 : gate->mask;
 
-	ccu_update(&mix->common, ctrl, gate->mask, gate->mask);
+	ccu_update(&mix->common, ctrl, gate->mask, val);
 
 	return 0;
 }
diff --git a/drivers/clk/spacemit/clk_mix.h b/drivers/clk/spacemit/clk_mix.h
index 26a12cedd0d..4ac61b55546 100644
--- a/drivers/clk/spacemit/clk_mix.h
+++ b/drivers/clk/spacemit/clk_mix.h
@@ -20,9 +20,11 @@
  *
  * @mask:	Mask to enable the gate. Some clocks may have more than one bit
  *		set in this field.
+ * @inverted:	Enable bit is inverted, 1 - disable clock, 0 - enable clock
  */
 struct ccu_gate_config {
 	u32 mask;
+	bool inverted;
 };
 
 struct ccu_factor_config {
@@ -48,15 +50,17 @@ struct ccu_mix {
 	struct ccu_common common;
 };
 
-#define CCU_GATE_INIT(_mask)		{ .mask = _mask }
+#define CCU_GATE_INIT(_mask)		{ .mask = _mask, .inverted = false }
+#define CCU_GATE_FLAGS_INIT(_mask, _inverted)	\
+	{ .mask = _mask, .inverted = _inverted }
 #define CCU_FACTOR_INIT(_div, _mul)	{ .div = _div, .mul = _mul }
 #define CCU_MUX_INIT(_shift, _width)	{ .shift = _shift, .width = _width }
 #define CCU_DIV_INIT(_shift, _width)	{ .shift = _shift, .width = _width }
 
-#define CCU_GATE_DEFINE(_id, _var, _name, _parent, _reg_ctrl,		\
-			_mask_gate, _flags)				\
+#define CCU_GATE_FLAGS_DEFINE(_id, _var, _name, _parent, _reg_ctrl,	\
+			      _mask_gate, _inverted, _flags)		\
 static struct ccu_mix _var = {						\
-	.gate	= CCU_GATE_INIT(_mask_gate),				\
+	.gate	= CCU_GATE_FLAGS_INIT(_mask_gate, _inverted),		\
 	.common	= {							\
 		.reg_ctrl	= _reg_ctrl,				\
 		CCU_COMMON(_id, _name, _parent, spacemit_gate_init,	\
@@ -64,6 +68,11 @@ static struct ccu_mix _var = {						\
 	}								\
 }
 
+#define CCU_GATE_DEFINE(_id, _var, _name, _parent, _reg_ctrl,		\
+			_mask_gate, _flags)				\
+	CCU_GATE_FLAGS_DEFINE(_id, _var, _name, _parent, _reg_ctrl,	\
+			      _mask_gate, false, _flags)
+
 #define CCU_FACTOR_DEFINE(_id, _var, _name, _parent, _div, _mul)	\
 static struct ccu_mix _var = {						\
 	.factor	= CCU_FACTOR_INIT(_div, _mul),				\

-- 
2.55.0

[PATCH 3/8] clk: spacemit: ccu_pll: add plla type clock

[Yixun Lan]

Based on upstream Linux:
  3a086236c600 ("clk: spacemit: ccu_pll: add plla type clock")

Introduce a new clock PLLA for SpacemiT's K3 SoC which has a different
register layout comparing to previous PPL type. And, It is configured
by swcr1, swcr3 and swcr2 BIT[15:8].

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 drivers/clk/spacemit/clk_common.h |   1 +
 drivers/clk/spacemit/clk_pll.c    | 124 +++++++++++++++++++++++++++++++++++++-
 drivers/clk/spacemit/clk_pll.h    |  43 +++++++++++--
 3 files changed, 163 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/spacemit/clk_common.h b/drivers/clk/spacemit/clk_common.h
index ea5ebf57784..60702414f2b 100644
--- a/drivers/clk/spacemit/clk_common.h
+++ b/drivers/clk/spacemit/clk_common.h
@@ -36,6 +36,7 @@ struct ccu_common {
 		/* For PLL */
 		struct {
 			u32 reg_swcr1;
+			u32 reg_swcr2;
 			u32 reg_swcr3;
 		};
 	};
diff --git a/drivers/clk/spacemit/clk_pll.c b/drivers/clk/spacemit/clk_pll.c
index 56da70af58a..36de37c3a25 100644
--- a/drivers/clk/spacemit/clk_pll.c
+++ b/drivers/clk/spacemit/clk_pll.c
@@ -13,7 +13,8 @@
 
 #include "clk_pll.h"
 
-#define UBOOT_DM_SPACEMIT_CLK_PLL "spacemit_clk_pll"
+#define UBOOT_DM_SPACEMIT_CLK_PLL	"spacemit_clk_pll"
+#define UBOOT_DM_SPACEMIT_CLK_PLLA	"spacemit_clk_plla"
 
 #define PLL_TIMEOUT_US		3000
 #define PLL_DELAY_US		5
@@ -21,6 +22,9 @@
 #define PLL_SWCR3_EN		((u32)BIT(31))
 #define PLL_SWCR3_MASK		GENMASK(30, 0)
 
+#define PLLA_SWCR2_EN		((u32)BIT(16))
+#define PLLA_SWCR2_MASK		GENMASK(15, 8)
+
 static const struct ccu_pll_rate_tbl *ccu_pll_lookup_best_rate(struct ccu_pll *pll,
 							       unsigned long rate)
 {
@@ -155,3 +159,121 @@ U_BOOT_DRIVER(spacemit_clk_pll) = {
 	.ops	= &spacemit_clk_pll_ops,
 	.flags	= DM_FLAG_PRE_RELOC,
 };
+
+static const struct ccu_pll_rate_tbl *ccu_plla_lookup_matched_entry(struct ccu_pll *pll)
+{
+	struct ccu_pll_config *config = &pll->config;
+	const struct ccu_pll_rate_tbl *entry;
+	u32 i, swcr1, swcr2, swcr3;
+
+	swcr1 = ccu_read(&pll->common, swcr1);
+	swcr2 = ccu_read(&pll->common, swcr2);
+	swcr2 &= PLLA_SWCR2_MASK;
+	swcr3 = ccu_read(&pll->common, swcr3);
+
+	for (i = 0; i < config->tbl_num; i++) {
+		entry = &config->rate_tbl[i];
+
+		if (swcr1 == entry->swcr1 &&
+		    swcr2 == entry->swcr2 &&
+		    swcr3 == entry->swcr3)
+			return entry;
+	}
+
+	return NULL;
+}
+
+static void ccu_plla_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry)
+{
+	struct ccu_common *common = &pll->common;
+
+	regmap_write(common->regmap, common->reg_swcr1, entry->swcr1);
+	regmap_write(common->regmap, common->reg_swcr3, entry->swcr3);
+	ccu_update(common, swcr2, PLLA_SWCR2_MASK, entry->swcr2);
+}
+
+static int ccu_plla_enable(struct clk *clk)
+{
+	struct ccu_pll *pll = clk_to_ccu_pll(clk);
+	struct ccu_common *common = &pll->common;
+	unsigned int tmp;
+
+	ccu_update(common, swcr2, PLLA_SWCR2_EN, PLLA_SWCR2_EN);
+
+	/* check lock status */
+	return regmap_read_poll_timeout(common->lock_regmap,
+					pll->config.reg_lock,
+					tmp,
+					tmp & pll->config.mask_lock,
+					PLL_DELAY_US, PLL_TIMEOUT_US);
+}
+
+static int ccu_plla_disable(struct clk *clk)
+{
+	struct ccu_common *common = clk_to_ccu_common(clk);
+
+	ccu_update(common, swcr2, PLLA_SWCR2_EN, 0);
+
+	return 0;
+}
+
+/*
+ * PLLAs must be gated before changing rate, which is ensured by
+ * flag CLK_SET_RATE_GATE.
+ */
+static unsigned long ccu_plla_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct ccu_pll *pll = clk_to_ccu_pll(clk);
+	const struct ccu_pll_rate_tbl *entry;
+
+	entry = ccu_pll_lookup_best_rate(pll, rate);
+	ccu_plla_update_param(pll, entry);
+
+	return 0;
+}
+
+static unsigned long ccu_plla_recalc_rate(struct clk *clk)
+{
+	struct ccu_pll *pll = clk_to_ccu_pll(clk);
+	const struct ccu_pll_rate_tbl *entry;
+
+	entry = ccu_plla_lookup_matched_entry(pll);
+
+	WARN_ON_ONCE(!entry);
+
+	return entry ? entry->rate : 0;
+}
+
+static const struct clk_ops spacemit_clk_plla_ops = {
+	.enable = ccu_plla_enable,
+	.disable = ccu_plla_disable,
+	.set_rate = ccu_plla_set_rate,
+	.get_rate = ccu_plla_recalc_rate,
+};
+
+int spacemit_plla_init(struct ccu_common *common)
+{
+	struct clk *clk = &common->clk;
+	struct ccu_pll *pll = clk_to_ccu_pll(clk);
+	int ret;
+
+	ret = clk_register(clk, UBOOT_DM_SPACEMIT_CLK_PLLA,
+			   common->name, common->parents[0]);
+	if (ret)
+		return ret;
+
+	if (ccu_plla_lookup_matched_entry(pll))
+		return 0;
+
+	ccu_plla_disable(clk);
+	ccu_plla_update_param(pll, &pll->config.rate_tbl[0]);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(spacemit_clk_plla) = {
+	.name	= UBOOT_DM_SPACEMIT_CLK_PLLA,
+	.id	= UCLASS_CLK,
+	.ops	= &spacemit_clk_plla_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/spacemit/clk_pll.h b/drivers/clk/spacemit/clk_pll.h
index 3987cc1141b..0de027dc7a6 100644
--- a/drivers/clk/spacemit/clk_pll.h
+++ b/drivers/clk/spacemit/clk_pll.h
@@ -20,14 +20,28 @@
  * configuration.
  *
  * @rate:	PLL rate
- * @swcr1:	Register value of PLLX_SW1_CTRL (PLLx_SWCR1).
- * @swcr3:	Register value of the PLLx_SW3_CTRL's lowest 31 bits of
- *		PLLx_SW3_CTRL (PLLx_SWCR3). This highest bit is for enabling
- *		the PLL and not contained in this field.
+ * @swcr1:	Value of register PLLx_SW1_CTRL.
+ * @swcr2:	Value of register PLLAx_SW2_CTRL (PLLA only).
+ * @swcr3:	Value of register PLLx_SW3_CTRL.
+ *
+ * Regular PLL type
+ *  | Enable | swcr3 | PLLx_SW3_CTRL - BIT[31]    |
+ *  -----------------------------------------------
+ *  | Config | swcr1 | PLLx_SW1_CTRL - BIT[31:0]  |
+ *  |        | swcr2 | Not used                   |
+ *  |        | swcr3 | PLLx_SW3_CTRL - BIT[30:0]  |
+ *
+ * Special PLL type A
+ *  | Enable | swcr2 | PLLAx_SW2_CTRL - BIT[16]   |
+ *  -----------------------------------------------
+ *  | Config | swcr1 | PLLAx_SW1_CTRL - BIT[31:0] |
+ *  |        | swcr2 | PLLAx_SW2_CTRL - BIT[15:8] |
+ *  |        | swcr3 | PLLAx_SW3_CTRL - BIT[31:0] |
  */
 struct ccu_pll_rate_tbl {
 	unsigned long rate;
 	u32 swcr1;
+	u32 swcr2;
 	u32 swcr3;
 };
 
@@ -38,6 +52,14 @@ struct ccu_pll_rate_tbl {
 		.swcr3	= _swcr3,		\
 	}
 
+#define CCU_PLLA_RATE(_rate, _swcr1, _swcr2, _swcr3)	\
+	{						\
+		.rate	= _rate,			\
+		.swcr1	= _swcr1,			\
+		.swcr2	= _swcr2,			\
+		.swcr3	= _swcr3,			\
+	}
+
 struct ccu_pll_config {
 	const struct ccu_pll_rate_tbl *rate_tbl;
 	u32 tbl_num;
@@ -69,6 +91,18 @@ static struct ccu_pll _var = {							\
 	}									\
 }
 
+#define CCU_PLLA_DEFINE(_id, _var, _name, _parent, _table, _reg_swcr1,		\
+			_reg_swcr2, _reg_swcr3, _reg_lock, _mask_lock, _flags)	\
+static struct ccu_pll _var = {							\
+	.config	= CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock),		\
+	.common = {								\
+		.reg_swcr1	= _reg_swcr1,					\
+		.reg_swcr2	= _reg_swcr2,					\
+		.reg_swcr3	= _reg_swcr3,					\
+		CCU_COMMON(_id, _name, _parent, spacemit_plla_init, _flags)	\
+	}									\
+}
+
 static inline struct ccu_pll *clk_to_ccu_pll(struct clk *clk)
 {
 	struct ccu_common *common = clk_to_ccu_common(clk);
@@ -77,5 +111,6 @@ static inline struct ccu_pll *clk_to_ccu_pll(struct clk *clk)
 }
 
 int spacemit_pll_init(struct ccu_common *common);
+int spacemit_plla_init(struct ccu_common *common);
 
 #endif /* _CLK_PLL_H_ */

-- 
2.55.0

[PATCH 4/8] clk: spacemit: k3: extract common header

[Yixun Lan]

Based on upstream linux:
  091d19cc2401 ("clk: spacemit: k3: extract common header")

Extracting common header file, which will be shared by clock and reset
drivers. So will make it easy to add reset driver for K3 SoC later.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 include/soc/spacemit/k3-syscon.h | 271 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 271 insertions(+)

diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h
new file mode 100644
index 00000000000..0b91ccf6ec5
--- /dev/null
+++ b/include/soc/spacemit/k3-syscon.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* SpacemiT clock and reset driver definitions for the K3 SoC */
+
+#ifndef __SOC_K3_SYSCON_H__
+#define __SOC_K3_SYSCON_H__
+
+/* APBS register offset */
+#define APBS_PLL1_SWCR1			0x100
+#define APBS_PLL1_SWCR2			0x104
+#define APBS_PLL1_SWCR3			0x108
+#define APBS_PLL2_SWCR1			0x118
+#define APBS_PLL2_SWCR2			0x11c
+#define APBS_PLL2_SWCR3			0x120
+#define APBS_PLL3_SWCR1			0x124
+#define APBS_PLL3_SWCR2			0x128
+#define APBS_PLL3_SWCR3			0x12c
+#define APBS_PLL4_SWCR1			0x130
+#define APBS_PLL4_SWCR2			0x134
+#define APBS_PLL4_SWCR3			0x138
+#define APBS_PLL5_SWCR1			0x13c
+#define APBS_PLL5_SWCR2			0x140
+#define APBS_PLL5_SWCR3			0x144
+#define APBS_PLL6_SWCR1			0x148
+#define APBS_PLL6_SWCR2			0x14c
+#define APBS_PLL6_SWCR3			0x150
+#define APBS_PLL7_SWCR1			0x158
+#define APBS_PLL7_SWCR2			0x15c
+#define APBS_PLL7_SWCR3			0x160
+#define APBS_PLL8_SWCR1			0x180
+#define APBS_PLL8_SWCR2			0x184
+#define APBS_PLL8_SWCR3			0x188
+
+/* MPMU register offset */
+#define MPMU_FCCR			0x0008
+#define MPMU_POSR			0x0010
+#define POSR_PLL1_LOCK			BIT(24)
+#define POSR_PLL2_LOCK			BIT(25)
+#define POSR_PLL3_LOCK			BIT(26)
+#define POSR_PLL4_LOCK			BIT(27)
+#define POSR_PLL5_LOCK			BIT(28)
+#define POSR_PLL6_LOCK			BIT(29)
+#define POSR_PLL7_LOCK			BIT(30)
+#define POSR_PLL8_LOCK			BIT(31)
+#define MPMU_SUCCR			0x0014
+#define MPMU_ISCCR			0x0044
+#define MPMU_WDTPCR			0x0200
+#define MPMU_RIPCCR			0x0210
+#define MPMU_ACGR			0x1024
+#define MPMU_APBCSCR			0x1050
+#define MPMU_SUCCR_1			0x10b0
+
+#define MPMU_I2S0_SYSCLK		0x1100
+#define MPMU_I2S2_SYSCLK		0x1104
+#define MPMU_I2S3_SYSCLK		0x1108
+#define MPMU_I2S4_SYSCLK		0x110c
+#define MPMU_I2S5_SYSCLK		0x1110
+#define MPMU_I2S_SYSCLK_CTRL		0x1114
+
+/* APBC register offset */
+#define APBC_UART0_CLK_RST		0x00
+#define APBC_UART2_CLK_RST		0x04
+#define APBC_GPIO_CLK_RST		0x08
+#define APBC_PWM0_CLK_RST		0x0c
+#define APBC_PWM1_CLK_RST		0x10
+#define APBC_PWM2_CLK_RST		0x14
+#define APBC_PWM3_CLK_RST		0x18
+#define APBC_TWSI8_CLK_RST		0x20
+#define APBC_UART3_CLK_RST		0x24
+#define APBC_RTC_CLK_RST		0x28
+#define APBC_TWSI0_CLK_RST		0x2c
+#define APBC_TWSI1_CLK_RST		0x30
+#define APBC_TIMERS0_CLK_RST		0x34
+#define APBC_TWSI2_CLK_RST		0x38
+#define APBC_AIB_CLK_RST		0x3c
+#define APBC_TWSI4_CLK_RST		0x40
+#define APBC_TIMERS1_CLK_RST		0x44
+#define APBC_ONEWIRE_CLK_RST		0x48
+#define APBC_TWSI5_CLK_RST		0x4c
+#define APBC_DRO_CLK_RST		0x58
+#define APBC_IR0_CLK_RST		0x5c
+#define APBC_IR1_CLK_RST		0x1c
+#define APBC_TWSI6_CLK_RST		0x60
+#define APBC_COUNTER_CLK_SEL		0x64
+#define APBC_TSEN_CLK_RST		0x6c
+#define APBC_UART4_CLK_RST		0x70
+#define APBC_UART5_CLK_RST		0x74
+#define APBC_UART6_CLK_RST		0x78
+#define APBC_SSP3_CLK_RST		0x7c
+#define APBC_SSPA0_CLK_RST		0x80
+#define APBC_SSPA1_CLK_RST		0x84
+#define APBC_SSPA2_CLK_RST		0x88
+#define APBC_SSPA3_CLK_RST		0x8c
+#define APBC_IPC_AP2AUD_CLK_RST		0x90
+#define APBC_UART7_CLK_RST		0x94
+#define APBC_UART8_CLK_RST		0x98
+#define APBC_UART9_CLK_RST		0x9c
+#define APBC_CAN0_CLK_RST		0xa0
+#define APBC_CAN1_CLK_RST		0xa4
+#define APBC_PWM4_CLK_RST		0xa8
+#define APBC_PWM5_CLK_RST		0xac
+#define APBC_PWM6_CLK_RST		0xb0
+#define APBC_PWM7_CLK_RST		0xb4
+#define APBC_PWM8_CLK_RST		0xb8
+#define APBC_PWM9_CLK_RST		0xbc
+#define APBC_PWM10_CLK_RST		0xc0
+#define APBC_PWM11_CLK_RST		0xc4
+#define APBC_PWM12_CLK_RST		0xc8
+#define APBC_PWM13_CLK_RST		0xcc
+#define APBC_PWM14_CLK_RST		0xd0
+#define APBC_PWM15_CLK_RST		0xd4
+#define APBC_PWM16_CLK_RST		0xd8
+#define APBC_PWM17_CLK_RST		0xdc
+#define APBC_PWM18_CLK_RST		0xe0
+#define APBC_PWM19_CLK_RST		0xe4
+#define APBC_TIMERS2_CLK_RST		0x11c
+#define APBC_TIMERS3_CLK_RST		0x120
+#define APBC_TIMERS4_CLK_RST		0x124
+#define APBC_TIMERS5_CLK_RST		0x128
+#define APBC_TIMERS6_CLK_RST		0x12c
+#define APBC_TIMERS7_CLK_RST		0x130
+
+#define APBC_CAN2_CLK_RST		0x148
+#define APBC_CAN3_CLK_RST		0x14c
+#define APBC_CAN4_CLK_RST		0x150
+#define APBC_UART10_CLK_RST		0x154
+#define APBC_SSP0_CLK_RST		0x158
+#define APBC_SSP1_CLK_RST		0x15c
+#define APBC_SSPA4_CLK_RST		0x160
+#define APBC_SSPA5_CLK_RST		0x164
+
+/* APMU register offset */
+#define APMU_CSI_CCIC2_CLK_RES_CTRL	0x024
+#define APMU_ISP_CLK_RES_CTRL		0x038
+#define APMU_PMU_CLK_GATE_CTRL		0x040
+#define APMU_LCD_CLK_RES_CTRL1		0x044
+#define APMU_LCD_SPI_CLK_RES_CTRL	0x048
+#define APMU_LCD_CLK_RES_CTRL2		0x04c
+#define APMU_CCIC_CLK_RES_CTRL		0x050
+#define APMU_SDH0_CLK_RES_CTRL		0x054
+#define APMU_SDH1_CLK_RES_CTRL		0x058
+#define APMU_USB_CLK_RES_CTRL		0x05c
+#define APMU_QSPI_CLK_RES_CTRL		0x060
+#define APMU_DMA_CLK_RES_CTRL		0x064
+#define APMU_AES_CLK_RES_CTRL		0x068
+#define APMU_MCB_CLK_RES_CTRL		0x06c
+#define APMU_VPU_CLK_RES_CTRL		0x0a4
+#define APMU_DTC_CLK_RES_CTRL		0x0ac
+#define APMU_GPU_CLK_RES_CTRL		0x0cc
+#define APMU_SDH2_CLK_RES_CTRL		0x0e0
+#define APMU_PMUA_MC_CTRL		0x0e8
+#define APMU_PMU_CC2_AP			0x100
+#define APMU_PMUA_EM_CLK_RES_CTRL	0x104
+#define APMU_UCIE_CTRL			0x11c
+#define APMU_RCPU_CLK_RES_CTRL		0x14c
+#define APMU_TOP_DCLK_CTRL		0x158
+#define APMU_LCD_EDP_CTRL		0x23c
+#define APMU_UFS_CLK_RES_CTRL		0x268
+#define APMU_LCD_CLK_RES_CTRL3		0x26c
+#define APMU_LCD_CLK_RES_CTRL4		0x270
+#define APMU_LCD_CLK_RES_CTRL5		0x274
+#define APMU_CCI550_CLK_CTRL		0x300
+#define APMU_ACLK_CLK_CTRL		0x388
+#define APMU_CPU_C0_CLK_CTRL		0x38C
+#define APMU_CPU_C1_CLK_CTRL		0x390
+#define APMU_CPU_C2_CLK_CTRL		0x394
+#define APMU_CPU_C3_CLK_CTRL		0x208
+#define APMU_PCIE_CLK_RES_CTRL_A	0x1f0
+#define APMU_PCIE_CLK_RES_CTRL_B	0x1d0
+#define APMU_PCIE_CLK_RES_CTRL_C	0x1c8
+#define APMU_PCIE_CLK_RES_CTRL_D	0x1e0
+#define APMU_PCIE_CLK_RES_CTRL_E	0x1e8
+#define APMU_EMAC0_CLK_RES_CTRL		0x3e4
+#define APMU_EMAC1_CLK_RES_CTRL		0x3ec
+#define APMU_EMAC2_CLK_RES_CTRL		0x248
+#define APMU_ESPI_CLK_RES_CTRL		0x240
+#define APMU_SNR_ISIM_VCLK_CTRL		0x3f8
+
+/* DCIU register offsets */
+#define DCIU_DMASYS_CLK_EN		0x234
+#define DCIU_DMASYS_SDMA_CLK_EN		0x238
+#define DCIU_C2_TCM_PIPE_CLK		0x244
+#define DCIU_C3_TCM_PIPE_CLK		0x248
+
+#define DCIU_DMASYS_S0_RSTN		0x204
+#define DCIU_DMASYS_S1_RSTN		0x208
+#define DCIU_DMASYS_A0_RSTN		0x20C
+#define DCIU_DMASYS_A1_RSTN		0x210
+#define DCIU_DMASYS_A2_RSTN		0x214
+#define DCIU_DMASYS_A3_RSTN		0x218
+#define DCIU_DMASYS_A4_RSTN		0x21C
+#define DCIU_DMASYS_A5_RSTN		0x220
+#define DCIU_DMASYS_A6_RSTN		0x224
+#define DCIU_DMASYS_A7_RSTN		0x228
+#define DCIU_DMASYS_RSTN		0x22C
+#define DCIU_DMASYS_SDMA_RSTN		0x230
+
+/* RCPU SYSCTRL register offsets */
+#define RCPU_CAN_CLK_RST		0x4c
+#define RCPU_CAN1_CLK_RST		0xF0
+#define RCPU_CAN2_CLK_RST		0xF4
+#define RCPU_CAN3_CLK_RST		0xF8
+#define RCPU_CAN4_CLK_RST		0xFC
+#define RCPU_IRC_CLK_RST		0x48
+#define RCPU_IRC1_CLK_RST		0xEC
+#define RCPU_GMAC_CLK_RST		0xE4
+#define RCPU_ESPI_CLK_RST		0xDC
+#define RCPU_AUDIO_I2S0_SYS_CLK_CTRL	0x70
+#define RCPU_AUDIO_I2S1_SYS_CLK_CTRL	0x44
+
+/* RCPU UARTCTRL register offsets */
+#define RCPU1_UART0_CLK_RST		0x00
+#define RCPU1_UART1_CLK_RST		0x04
+#define RCPU1_UART2_CLK_RST		0x08
+#define RCPU1_UART3_CLK_RST		0x0c
+#define RCPU1_UART4_CLK_RST		0x10
+#define RCPU1_UART5_CLK_RST		0x14
+
+/* RCPU I2SCTRL register offsets */
+#define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL	0x60
+#define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL	0x64
+#define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL	0x68
+#define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL	0x6C
+
+#define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL	0x44
+#define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL	0x54
+
+/* RCPU SPICTRL register offsets */
+#define RCPU3_SSP0_CLK_RST		0x00
+#define RCPU3_SSP1_CLK_RST		0x04
+#define RCPU3_PWR_SSP_CLK_RST		0x08
+
+/* RCPU I2CCTRL register offsets */
+#define RCPU4_I2C0_CLK_RST		0x00
+#define RCPU4_I2C1_CLK_RST		0x04
+#define RCPU4_PWR_I2C_CLK_RST		0x08
+
+/* RPMU register offsets */
+#define RCPU5_AON_PER_CLK_RST_CTRL	0x2C
+#define RCPU5_TIMER1_CLK_RST		0x4C
+#define RCPU5_TIMER2_CLK_RST		0x70
+#define RCPU5_TIMER3_CLK_RST		0x78
+#define RCPU5_TIMER4_CLK_RST		0x7C
+#define RCPU5_GPIO_AND_EDGE_CLK_RST	0x74
+#define RCPU5_RCPU_BUS_CLK_CTRL		0xC0
+#define RCPU5_RT24_CORE0_CLK_CTRL	0xC4
+#define RCPU5_RT24_CORE1_CLK_CTRL	0xC8
+#define RCPU5_RT24_CORE0_SW_RESET	0xCC
+#define RCPU5_RT24_CORE1_SW_RESET	0xD0
+
+/* RCPU PWMCTRL register offsets */
+#define RCPU6_PWM0_CLK_RST		0x00
+#define RCPU6_PWM1_CLK_RST		0x04
+#define RCPU6_PWM2_CLK_RST		0x08
+#define RCPU6_PWM3_CLK_RST		0x0c
+#define RCPU6_PWM4_CLK_RST		0x10
+#define RCPU6_PWM5_CLK_RST		0x14
+#define RCPU6_PWM6_CLK_RST		0x18
+#define RCPU6_PWM7_CLK_RST		0x1c
+#define RCPU6_PWM8_CLK_RST		0x20
+#define RCPU6_PWM9_CLK_RST		0x24
+
+/* APBC2 SEC register offsets */
+#define APBC2_UART1_CLK_RST		0x00
+#define APBC2_SSP2_CLK_RST		0x04
+#define APBC2_TWSI3_CLK_RST		0x08
+#define APBC2_RTC_CLK_RST		0x0c
+#define APBC2_TIMERS_CLK_RST		0x10
+#define APBC2_GPIO_CLK_RST		0x1c
+
+#endif /* __SOC_K3_SYSCON_H__ */

-- 
2.55.0

[PATCH 5/8] clk: spacemit: k3: add the clock tree

[Yixun Lan]

Based on upstream Linux:
  e371a77255b8 ("clk: spacemit: k3: add the clock tree")

Also some bug fixes are folded here:
  3e75021f615c ("clk: spacemit: k3: mark top_dclk as CLK_IS_CRITICAL")
  d8a4cef90b1a ("clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock")
  8abba78dc0ee ("clk: spacemit: k3: fix parent clock of UFS aclk")

Add clock support for the SpacemiT K3 SoC. The clock tree covers the
APBC, APBS, APMU, DCIU and MPMU blocks.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 drivers/clk/spacemit/Kconfig   |    7 +
 drivers/clk/spacemit/Makefile  |    1 +
 drivers/clk/spacemit/clk-k3.c  | 1932 ++++++++++++++++++++++++++++++++++++++++
 drivers/clk/spacemit/clk_mix.h |   10 +
 4 files changed, 1950 insertions(+)

diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig
index 25a3c1e4a45..b22f65f2547 100644
--- a/drivers/clk/spacemit/Kconfig
+++ b/drivers/clk/spacemit/Kconfig
@@ -20,4 +20,11 @@ config CLK_SPACEMIT_K1
 	  This enables support clock driver for Spacemit K1 SoC.
 	  It's based on Common Clock Framework.
 
+config CLK_SPACEMIT_K3
+	bool "SpacemiT K3 clock support"
+	select CLK_CCF
+	help
+	  This enables support clock driver for Spacemit K3 SoC.
+	  It's based on Common Clock Framework.
+
 endif
diff --git a/drivers/clk/spacemit/Makefile b/drivers/clk/spacemit/Makefile
index 824e94d1f74..5cebfede1f1 100644
--- a/drivers/clk/spacemit/Makefile
+++ b/drivers/clk/spacemit/Makefile
@@ -5,3 +5,4 @@
 obj-$(CONFIG_CLK_SPACEMIT) += clk_ddn.o clk_mix.o clk_pll.o
 
 obj-$(CONFIG_CLK_SPACEMIT_K1)	+= clk-k1.o
+obj-$(CONFIG_CLK_SPACEMIT_K3)	+= clk-k3.o
diff --git a/drivers/clk/spacemit/clk-k3.c b/drivers/clk/spacemit/clk-k3.c
new file mode 100644
index 00000000000..1ac64aec6ba
--- /dev/null
+++ b/drivers/clk/spacemit/clk-k3.c
@@ -0,0 +1,1932 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd
+ *
+ * Port of Linux drivers/clk/spacemit/ccu-k3.c for U-Boot.
+ */
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <regmap.h>
+#include <linux/clk-provider.h>
+#include <soc/spacemit/k3-syscon.h>
+
+#include "clk_common.h"
+#include "clk_ddn.h"
+#include "clk_mix.h"
+#include "clk_pll.h"
+
+#include <dt-bindings/clock/spacemit,k3-clocks.h>
+
+/* Region base IDs — must exceed per-region binding ID ranges */
+#define K3_PLL_ID		200
+#define K3_MPMU_ID		400
+#define K3_APBC_ID		600
+#define K3_APMU_ID		900
+#define K3_DCIU_ID		1200
+
+struct spacemit_ccu_data {
+	struct clk **clks;
+	size_t num;
+	unsigned long offset;
+};
+
+/* APBS clocks start, APBS region contains and only contains all PLL clocks */
+
+/*
+ * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for
+ * peripherals.
+ */
+static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = {
+	CCU_PLLA_RATE(2457600000UL, 0x0b330ccc, 0x0000cd00, 0xa0558989),
+};
+
+static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
+	CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c),
+};
+
+static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
+	CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787),
+};
+
+static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = {
+	CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787),
+};
+
+static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = {
+	CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
+};
+
+static const struct ccu_pll_rate_tbl pll6_rate_tbl[] = {
+	CCU_PLLA_RATE(3200000000UL, 0x0b422aaa, 0x0000ab00, 0xa0558e8e),
+};
+
+static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = {
+	CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b),
+};
+
+static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = {
+	CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
+};
+
+CCU_PLLA_DEFINE(CLK_PLL1, pll1, pll1, "clock-24m", pll1_rate_tbl,
+		APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK,
+		CLK_SET_RATE_GATE);
+CCU_PLLA_DEFINE(CLK_PLL2, pll2, pll2, "clock-24m", pll2_rate_tbl,
+		APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK,
+		CLK_SET_RATE_GATE);
+CCU_PLLA_DEFINE(CLK_PLL3, pll3, pll3, "clock-24m", pll3_rate_tbl,
+		APBS_PLL3_SWCR1, APBS_PLL3_SWCR2, APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK,
+		CLK_SET_RATE_GATE);
+CCU_PLLA_DEFINE(CLK_PLL4, pll4, pll4, "clock-24m", pll4_rate_tbl,
+		APBS_PLL4_SWCR1, APBS_PLL4_SWCR2, APBS_PLL4_SWCR3, MPMU_POSR, POSR_PLL4_LOCK,
+		CLK_SET_RATE_GATE);
+CCU_PLLA_DEFINE(CLK_PLL5, pll5, pll5, "clock-24m", pll5_rate_tbl,
+		APBS_PLL5_SWCR1, APBS_PLL5_SWCR2, APBS_PLL5_SWCR3, MPMU_POSR, POSR_PLL5_LOCK,
+		CLK_SET_RATE_GATE);
+CCU_PLLA_DEFINE(CLK_PLL6, pll6, pll6, "clock-24m", pll6_rate_tbl,
+		APBS_PLL6_SWCR1, APBS_PLL6_SWCR2, APBS_PLL6_SWCR3, MPMU_POSR, POSR_PLL6_LOCK,
+		CLK_SET_RATE_GATE);
+CCU_PLLA_DEFINE(CLK_PLL7, pll7, pll7, "clock-24m", pll7_rate_tbl,
+		APBS_PLL7_SWCR1, APBS_PLL7_SWCR2, APBS_PLL7_SWCR3, MPMU_POSR, POSR_PLL7_LOCK,
+		CLK_SET_RATE_GATE);
+CCU_PLLA_DEFINE(CLK_PLL8, pll8, pll8, "clock-24m", pll8_rate_tbl,
+		APBS_PLL8_SWCR1, APBS_PLL8_SWCR2, APBS_PLL8_SWCR3, MPMU_POSR, POSR_PLL8_LOCK,
+		CLK_SET_RATE_GATE);
+
+CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D2, pll1_d2, pll1_d2, "pll1",
+		       APBS_PLL1_SWCR2, BIT(1), 2, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D3, pll1_d3, pll1_d3, "pll1",
+		       APBS_PLL1_SWCR2, BIT(2), 3, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D4, pll1_d4, pll1_d4, "pll1",
+		       APBS_PLL1_SWCR2, BIT(3), 4, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D5, pll1_d5, pll1_d5, "pll1",
+		       APBS_PLL1_SWCR2, BIT(4), 5, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D6, pll1_d6, pll1_d6, "pll1",
+		       APBS_PLL1_SWCR2, BIT(5), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D7, pll1_d7, pll1_d7, "pll1",
+		       APBS_PLL1_SWCR2, BIT(6), 7, 1);
+CCU_FACTOR_GATE_FLAGS_DEFINE(CLK_PLL1_D8, pll1_d8, pll1_d8, "pll1",
+			     APBS_PLL1_SWCR2, BIT(7), 8, 1, CLK_IS_CRITICAL);
+CCU_DIV_GATE_DEFINE(CLK_PLL1_DX, pll1_dx, pll1_dx, "pll1",
+		    APBS_PLL1_SWCR2, 23, 5, BIT(22), 0);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D64, pll1_d64_38p4, pll1_d64_38p4, "pll1",
+		       APBS_PLL1_SWCR2, BIT(31), 64, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D10_AUD, pll1_aud_245p7, pll1_aud_245p7, "pll1",
+		       APBS_PLL1_SWCR2, BIT(21), 10, 1);
+CCU_FACTOR_DEFINE(CLK_PLL1_D100_AUD, pll1_aud_24p5, pll1_aud_24p5, "pll1_aud_245p7", 10, 1);
+
+CCU_FACTOR_GATE_DEFINE(CLK_PLL2_D1, pll2_d1, pll2_d1, "pll2",
+		       APBS_PLL2_SWCR2, BIT(0), 1, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL2_D2, pll2_d2, pll2_d2, "pll2",
+		       APBS_PLL2_SWCR2, BIT(1), 2, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL2_D3, pll2_d3, pll2_d3, "pll2",
+		       APBS_PLL2_SWCR2, BIT(2), 3, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL2_D4, pll2_d4, pll2_d4, "pll2",
+		       APBS_PLL2_SWCR2, BIT(3), 4, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL2_D5, pll2_d5, pll2_d5, "pll2",
+		       APBS_PLL2_SWCR2, BIT(4), 5, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL2_D6, pll2_d6, pll2_d6, "pll2",
+		       APBS_PLL2_SWCR2, BIT(5), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL2_D7, pll2_d7, pll2_d7, "pll2",
+		       APBS_PLL2_SWCR2, BIT(6), 7, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL2_D8, pll2_d8, pll2_d8, "pll2",
+		       APBS_PLL2_SWCR2, BIT(7), 8, 1);
+CCU_FACTOR_DEFINE(CLK_PLL2_66, pll2_66, pll2_66, "pll2_d5", 9, 1);
+CCU_FACTOR_DEFINE(CLK_PLL2_33, pll2_33, pll2_33, "pll2_66", 2, 1);
+CCU_FACTOR_DEFINE(CLK_PLL2_50, pll2_50, pll2_50, "pll2_d5", 12, 1);
+CCU_FACTOR_DEFINE(CLK_PLL2_25, pll2_25, pll2_25, "pll2_50", 2, 1);
+CCU_FACTOR_DEFINE(CLK_PLL2_20, pll2_20, pll2_20, "pll2_d5", 30, 1);
+CCU_FACTOR_DEFINE(CLK_PLL2_D24_125, pll2_d24_125, pll2_d24_125, "pll2_d3", 8, 1);
+CCU_FACTOR_DEFINE(CLK_PLL2_D120_25, pll2_d120_25, pll2_d120_25, "pll2_d3", 40, 1);
+
+CCU_FACTOR_GATE_DEFINE(CLK_PLL3_D1, pll3_d1, pll3_d1, "pll3",
+		       APBS_PLL3_SWCR2, BIT(0), 1, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL3_D2, pll3_d2, pll3_d2, "pll3",
+		       APBS_PLL3_SWCR2, BIT(1), 2, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL3_D3, pll3_d3, pll3_d3, "pll3",
+		       APBS_PLL3_SWCR2, BIT(2), 3, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL3_D4, pll3_d4, pll3_d4, "pll3",
+		       APBS_PLL3_SWCR2, BIT(3), 4, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL3_D5, pll3_d5, pll3_d5, "pll3",
+		       APBS_PLL3_SWCR2, BIT(4), 5, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL3_D6, pll3_d6, pll3_d6, "pll3",
+		       APBS_PLL3_SWCR2, BIT(5), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL3_D7, pll3_d7, pll3_d7, "pll3",
+		       APBS_PLL3_SWCR2, BIT(6), 7, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL3_D8, pll3_d8, pll3_d8, "pll3",
+		       APBS_PLL3_SWCR2, BIT(7), 8, 1);
+
+CCU_FACTOR_GATE_DEFINE(CLK_PLL4_D1, pll4_d1, pll4_d1, "pll4",
+		       APBS_PLL4_SWCR2, BIT(0), 1, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL4_D2, pll4_d2, pll4_d2, "pll4",
+		       APBS_PLL4_SWCR2, BIT(1), 2, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL4_D3, pll4_d3, pll4_d3, "pll4",
+		       APBS_PLL4_SWCR2, BIT(2), 3, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL4_D4, pll4_d4, pll4_d4, "pll4",
+		       APBS_PLL4_SWCR2, BIT(3), 4, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL4_D5, pll4_d5, pll4_d5, "pll4",
+		       APBS_PLL4_SWCR2, BIT(4), 5, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL4_D6, pll4_d6, pll4_d6, "pll4",
+		       APBS_PLL4_SWCR2, BIT(5), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL4_D7, pll4_d7, pll4_d7, "pll4",
+		       APBS_PLL4_SWCR2, BIT(6), 7, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL4_D8, pll4_d8, pll4_d8, "pll4",
+		       APBS_PLL4_SWCR2, BIT(7), 8, 1);
+
+CCU_FACTOR_GATE_DEFINE(CLK_PLL5_D1, pll5_d1, pll5_d1, "pll5",
+		       APBS_PLL5_SWCR2, BIT(0), 1, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL5_D2, pll5_d2, pll5_d2, "pll5",
+		       APBS_PLL5_SWCR2, BIT(1), 2, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL5_D3, pll5_d3, pll5_d3, "pll5",
+		       APBS_PLL5_SWCR2, BIT(2), 3, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL5_D4, pll5_d4, pll5_d4, "pll5",
+		       APBS_PLL5_SWCR2, BIT(3), 4, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL5_D5, pll5_d5, pll5_d5, "pll5",
+		       APBS_PLL5_SWCR2, BIT(4), 5, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL5_D6, pll5_d6, pll5_d6, "pll5",
+		       APBS_PLL5_SWCR2, BIT(5), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL5_D7, pll5_d7, pll5_d7, "pll5",
+		       APBS_PLL5_SWCR2, BIT(6), 7, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL5_D8, pll5_d8, pll5_d8, "pll5",
+		       APBS_PLL5_SWCR2, BIT(7), 8, 1);
+
+CCU_FACTOR_GATE_DEFINE(CLK_PLL6_D1, pll6_d1, pll6_d1, "pll6",
+		       APBS_PLL6_SWCR2, BIT(0), 1, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL6_D2, pll6_d2, pll6_d2, "pll6",
+		       APBS_PLL6_SWCR2, BIT(1), 2, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL6_D3, pll6_d3, pll6_d3, "pll6",
+		       APBS_PLL6_SWCR2, BIT(2), 3, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL6_D4, pll6_d4, pll6_d4, "pll6",
+		       APBS_PLL6_SWCR2, BIT(3), 4, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL6_D5, pll6_d5, pll6_d5, "pll6",
+		       APBS_PLL6_SWCR2, BIT(4), 5, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL6_D6, pll6_d6, pll6_d6, "pll6",
+		       APBS_PLL6_SWCR2, BIT(5), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL6_D7, pll6_d7, pll6_d7, "pll6",
+		       APBS_PLL6_SWCR2, BIT(6), 7, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL6_D8, pll6_d8, pll6_d8, "pll6",
+		       APBS_PLL6_SWCR2, BIT(7), 8, 1);
+CCU_FACTOR_DEFINE(CLK_PLL6_80, pll6_80, pll6_80, "pll6_d5", 8, 1);
+CCU_FACTOR_DEFINE(CLK_PLL6_40, pll6_40, pll6_40, "pll6_d5", 16, 1);
+CCU_FACTOR_DEFINE(CLK_PLL6_20, pll6_20, pll6_20, "pll6_d5", 32, 1);
+
+CCU_FACTOR_GATE_DEFINE(CLK_PLL7_D1, pll7_d1, pll7_d1, "pll7",
+		       APBS_PLL7_SWCR2, BIT(0), 1, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL7_D2, pll7_d2, pll7_d2, "pll7",
+		       APBS_PLL7_SWCR2, BIT(1), 2, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL7_D3, pll7_d3, pll7_d3, "pll7",
+		       APBS_PLL7_SWCR2, BIT(2), 3, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL7_D4, pll7_d4, pll7_d4, "pll7",
+		       APBS_PLL7_SWCR2, BIT(3), 4, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL7_D5, pll7_d5, pll7_d5, "pll7",
+		       APBS_PLL7_SWCR2, BIT(4), 5, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL7_D6, pll7_d6, pll7_d6, "pll7",
+		       APBS_PLL7_SWCR2, BIT(5), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL7_D7, pll7_d7, pll7_d7, "pll7",
+		       APBS_PLL7_SWCR2, BIT(6), 7, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL7_D8, pll7_d8, pll7_d8, "pll7",
+		       APBS_PLL7_SWCR2, BIT(7), 8, 1);
+
+CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D1, pll8_d1, pll8_d1, "pll8",
+		       APBS_PLL8_SWCR2, BIT(0), 1, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D2, pll8_d2, pll8_d2, "pll8",
+		       APBS_PLL8_SWCR2, BIT(1), 2, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D3, pll8_d3, pll8_d3, "pll8",
+		       APBS_PLL8_SWCR2, BIT(2), 3, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D4, pll8_d4, pll8_d4, "pll8",
+		       APBS_PLL8_SWCR2, BIT(3), 4, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D5, pll8_d5, pll8_d5, "pll8",
+		       APBS_PLL8_SWCR2, BIT(4), 5, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D6, pll8_d6, pll8_d6, "pll8",
+		       APBS_PLL8_SWCR2, BIT(5), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D7, pll8_d7, pll8_d7, "pll8",
+		       APBS_PLL8_SWCR2, BIT(6), 7, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D8, pll8_d8, pll8_d8, "pll8",
+		       APBS_PLL8_SWCR2, BIT(7), 8, 1);
+/* APBS clocks end */
+
+/* MPMU clocks start */
+CCU_GATE_DEFINE(CLK_MPMU_PLL1_307P2, pll1_d8_307p2, pll1_d8_307p2, "pll1_d8",
+		MPMU_ACGR, BIT(13), 0);
+CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_76P8, pll1_d32_76p8, pll1_d32_76p8, "pll1_d8_307p2", 4, 1);
+CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_61P44, pll1_d40_61p44, pll1_d40_61p44, "pll1_d8_307p2", 5, 1);
+CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_153P6, pll1_d16_153p6, pll1_d16_153p6, "pll1_d8", 2, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_102P4, pll1_d24_102p4, pll1_d24_102p4, "pll1_d8",
+		       MPMU_ACGR, BIT(12), 3, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_51P2, pll1_d48_51p2, pll1_d48_51p2, "pll1_d8",
+		       MPMU_ACGR, BIT(7), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_51P2_AP, pll1_d48_51p2_ap, pll1_d48_51p2_ap, "pll1_d8",
+		       MPMU_ACGR, BIT(11), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_57P6, pll1_m3d128_57p6, pll1_m3d128_57p6, "pll1_d8",
+		       MPMU_ACGR, BIT(8), 16, 3);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_25P6, pll1_d96_25p6, pll1_d96_25p6, "pll1_d8",
+		       MPMU_ACGR, BIT(4), 12, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_12P8, pll1_d192_12p8, pll1_d192_12p8, "pll1_d8",
+		       MPMU_ACGR, BIT(3), 24, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_12P8_WDT, pll1_d192_12p8_wdt, pll1_d192_12p8_wdt, "pll1_d8",
+		       MPMU_ACGR, BIT(19), 24, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_6P4, pll1_d384_6p4, pll1_d384_6p4, "pll1_d8",
+		       MPMU_ACGR, BIT(2), 48, 1);
+
+CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_3P2, pll1_d768_3p2, pll1_d768_3p2, "pll1_d384_6p4", 2, 1);
+CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_1P6, pll1_d1536_1p6, pll1_d1536_1p6, "pll1_d384_6p4", 4, 1);
+CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_0P8, pll1_d3072_0p8, pll1_d3072_0p8, "pll1_d384_6p4", 8, 1);
+
+CCU_GATE_DEFINE(CLK_MPMU_PLL1_409P6, pll1_d6_409p6, pll1_d6_409p6, "pll1_d6",
+		MPMU_ACGR, BIT(0), 0);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_204P8, pll1_d12_204p8, pll1_d12_204p8, "pll1_d6",
+		       MPMU_ACGR, BIT(5), 2, 1);
+
+CCU_GATE_DEFINE(CLK_MPMU_PLL1_491, pll1_d5_491p52, pll1_d5_491p52, "pll1_d5",
+		MPMU_ACGR, BIT(21), 0);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_245P76, pll1_d10_245p76, pll1_d10_245p76, "pll1_d5",
+		       MPMU_ACGR, BIT(18), 2, 1);
+
+CCU_GATE_DEFINE(CLK_MPMU_PLL1_614, pll1_d4_614p4, pll1_d4_614p4, "pll1_d4",
+		MPMU_ACGR, BIT(15), 0);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_47P26, pll1_d52_47p26, pll1_d52_47p26, "pll1_d4",
+		       MPMU_ACGR, BIT(10), 13, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_31P5, pll1_d78_31p5, pll1_d78_31p5, "pll1_d4",
+		       MPMU_ACGR, BIT(6), 39, 2);
+
+CCU_GATE_DEFINE(CLK_MPMU_PLL1_819, pll1_d3_819p2, pll1_d3_819p2, "pll1_d3",
+		MPMU_ACGR, BIT(14), 0);
+
+CCU_GATE_DEFINE(CLK_MPMU_PLL1_1228, pll1_d2_1228p8, pll1_d2_1228p8, "pll1_d2",
+		MPMU_ACGR, BIT(16), 0);
+
+static const char * const apb_parents[] = {
+	"pll1_d96_25p6", "pll1_d48_51p2", "pll1_d96_25p6", "pll1_d24_102p4",
+};
+CCU_MUX_DEFINE(CLK_MPMU_APB, apb_clk, apb_clk, apb_parents, ARRAY_SIZE(apb_parents),
+		MPMU_APBCSCR, 0, 2, 0);
+
+CCU_GATE_DEFINE(CLK_MPMU_SLOW_UART, slow_uart, slow_uart, "clock-32k",
+		MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED);
+CCU_DDN_DEFINE(CLK_MPMU_SLOW_UART1, slow_uart1_14p74, slow_uart1_14p74, "pll1_d16_153p6", MPMU_SUCCR,
+		CCU_DDN_MASK(16, 13), 16, CCU_DDN_MASK(0, 13), 0,
+		2, 0);
+CCU_DDN_DEFINE(CLK_MPMU_SLOW_UART2, slow_uart2_48, slow_uart2_48, "pll1_d4_614p4", MPMU_SUCCR_1,
+		CCU_DDN_MASK(16, 13), 16, CCU_DDN_MASK(0, 13), 0,
+		2, 0);
+
+CCU_GATE_DEFINE(CLK_MPMU_WDT, wdt_clk, wdt_clk, "pll1_d96_25p6",
+		MPMU_WDTPCR, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_MPMU_WDT_BUS, wdt_bus_clk, wdt_bus_clk, "apb_clk",
+		MPMU_WDTPCR, BIT(0), 0);
+
+CCU_GATE_DEFINE(CLK_MPMU_RIPC, r_ipc_clk, r_ipc_clk, "apb_clk",
+		MPMU_RIPCCR, BIT(0), 0);
+
+CCU_FACTOR_DEFINE(CLK_MPMU_I2S_153P6, i2s_153p6, i2s_153p6, "pll1_d8_307p2", 2, 1);
+
+static const char * const i2s_153p6_base_parents[] = {
+	"i2s_153p6", "pll1_d8_307p2",
+};
+CCU_MUX_DEFINE(CLK_MPMU_I2S_153P6_BASE, i2s_153p6_base, i2s_153p6_base, i2s_153p6_base_parents, ARRAY_SIZE(i2s_153p6_base_parents),
+		MPMU_FCCR, 29, 1, 0);
+
+static const char * const i2s_sysclk_src_parents[] = {
+	"pll1_d96_25p6", "i2s_153p6_base",
+};
+CCU_MUX_GATE_DEFINE(CLK_MPMU_I2S_SYSCLK_SRC, i2s_sysclk_src, i2s_sysclk_src, i2s_sysclk_src_parents, ARRAY_SIZE(i2s_sysclk_src_parents),
+		    MPMU_ISCCR, 30, 1, BIT(31), 0);
+
+CCU_DDN_DEFINE(CLK_MPMU_I2S1_SYSCLK, i2s1_sysclk, i2s1_sysclk, "i2s_sysclk_src", MPMU_ISCCR,
+		CCU_DDN_MASK(0, 15), 0, CCU_DDN_MASK(15, 12), 15,
+		1, 0);
+
+CCU_DIV_GATE_DEFINE(CLK_MPMU_I2S_BCLK, i2s_bclk, i2s_bclk, "i2s1_sysclk",
+		    MPMU_ISCCR, 27, 2, BIT(29), 0);
+
+static const char * const i2s_sysclk_parents[] = {
+	"pll1_d4_614p4", "clock-24m", "pll2_d5", "clock-24m",
+};
+CCU_MUX_DEFINE(CLK_MPMU_I2S0_SYSCLK_SEL, i2s0_sysclk_sel, i2s0_sysclk_sel, i2s_sysclk_parents, ARRAY_SIZE(i2s_sysclk_parents),
+		MPMU_I2S_SYSCLK_CTRL, 0, 2, 0);
+CCU_MUX_DEFINE(CLK_MPMU_I2S2_SYSCLK_SEL, i2s2_sysclk_sel, i2s2_sysclk_sel, i2s_sysclk_parents, ARRAY_SIZE(i2s_sysclk_parents),
+		MPMU_I2S_SYSCLK_CTRL, 4, 2, 0);
+CCU_MUX_DEFINE(CLK_MPMU_I2S3_SYSCLK_SEL, i2s3_sysclk_sel, i2s3_sysclk_sel, i2s_sysclk_parents, ARRAY_SIZE(i2s_sysclk_parents),
+		MPMU_I2S_SYSCLK_CTRL, 12, 2, 0);
+CCU_MUX_DEFINE(CLK_MPMU_I2S4_SYSCLK_SEL, i2s4_sysclk_sel, i2s4_sysclk_sel, i2s_sysclk_parents, ARRAY_SIZE(i2s_sysclk_parents),
+		MPMU_I2S_SYSCLK_CTRL, 16, 2, 0);
+CCU_MUX_DEFINE(CLK_MPMU_I2S5_SYSCLK_SEL, i2s5_sysclk_sel, i2s5_sysclk_sel, i2s_sysclk_parents, ARRAY_SIZE(i2s_sysclk_parents),
+		MPMU_I2S_SYSCLK_CTRL, 20, 2, 0);
+
+CCU_DDN_DEFINE(CLK_MPMU_I2S0_SYSCLK_DIV, i2s0_sysclk_div, i2s0_sysclk_div, "i2s0_sysclk_sel", MPMU_I2S0_SYSCLK,
+		CCU_DDN_MASK(0, 16), 0, CCU_DDN_MASK(16, 16), 16,
+		1, 0);
+CCU_DDN_DEFINE(CLK_MPMU_I2S2_SYSCLK_DIV, i2s2_sysclk_div, i2s2_sysclk_div, "i2s2_sysclk_sel", MPMU_I2S2_SYSCLK,
+		CCU_DDN_MASK(0, 16), 0, CCU_DDN_MASK(16, 16), 16,
+		1, 0);
+CCU_DDN_DEFINE(CLK_MPMU_I2S3_SYSCLK_DIV, i2s3_sysclk_div, i2s3_sysclk_div, "i2s3_sysclk_sel", MPMU_I2S3_SYSCLK,
+		CCU_DDN_MASK(0, 16), 0, CCU_DDN_MASK(16, 16), 16,
+		1, 0);
+CCU_DDN_DEFINE(CLK_MPMU_I2S4_SYSCLK_DIV, i2s4_sysclk_div, i2s4_sysclk_div, "i2s4_sysclk_sel", MPMU_I2S4_SYSCLK,
+		CCU_DDN_MASK(0, 16), 0, CCU_DDN_MASK(16, 16), 16,
+		1, 0);
+CCU_DDN_DEFINE(CLK_MPMU_I2S5_SYSCLK_DIV, i2s5_sysclk_div, i2s5_sysclk_div, "i2s5_sysclk_sel", MPMU_I2S5_SYSCLK,
+		CCU_DDN_MASK(0, 16), 0, CCU_DDN_MASK(16, 16), 16,
+		1, 0);
+
+static const char * const i2s2_sysclk_parents[] = {
+	"i2s1_sysclk", "i2s2_sysclk_div",
+};
+CCU_GATE_DEFINE(CLK_MPMU_I2S0_SYSCLK, i2s0_sysclk, i2s0_sysclk, "i2s0_sysclk_div",
+		MPMU_I2S_SYSCLK_CTRL, BIT(2), 0);
+CCU_MUX_GATE_DEFINE(CLK_MPMU_I2S2_SYSCLK, i2s2_sysclk, i2s2_sysclk, i2s2_sysclk_parents, ARRAY_SIZE(i2s2_sysclk_parents),
+		    MPMU_I2S_SYSCLK_CTRL, 8, 1, BIT(6), 0);
+CCU_GATE_DEFINE(CLK_MPMU_I2S3_SYSCLK, i2s3_sysclk, i2s3_sysclk, "i2s3_sysclk_div",
+		MPMU_I2S_SYSCLK_CTRL, BIT(14), 0);
+CCU_GATE_DEFINE(CLK_MPMU_I2S4_SYSCLK, i2s4_sysclk, i2s4_sysclk, "i2s4_sysclk_div",
+		MPMU_I2S_SYSCLK_CTRL, BIT(18), 0);
+CCU_GATE_DEFINE(CLK_MPMU_I2S5_SYSCLK, i2s5_sysclk, i2s5_sysclk, "i2s5_sysclk_div",
+		MPMU_I2S_SYSCLK_CTRL, BIT(22), 0);
+/* MPMU clocks end */
+
+/* APBC clocks start */
+static const char * const uart_clk_parents[] = {
+	"pll1_m3d128_57p6", "slow_uart1_14p74", "slow_uart2_48",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART0, uart0_clk, uart0_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART0_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART2, uart2_clk, uart2_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART2_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART3, uart3_clk, uart3_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART3_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART4, uart4_clk, uart4_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART4_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART5, uart5_clk, uart5_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART5_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART6, uart6_clk, uart6_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART6_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART7, uart7_clk, uart7_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART7_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART8, uart8_clk, uart8_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART8_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART9, uart9_clk, uart9_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART9_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART10, uart10_clk, uart10_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART10_CLK_RST, 4, 3, BIT(1), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_UART0_BUS, uart0_bus_clk, uart0_bus_clk, "apb_clk",
+		APBC_UART0_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_UART2_BUS, uart2_bus_clk, uart2_bus_clk, "apb_clk",
+		APBC_UART2_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_UART3_BUS, uart3_bus_clk, uart3_bus_clk, "apb_clk",
+		APBC_UART3_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_UART4_BUS, uart4_bus_clk, uart4_bus_clk, "apb_clk",
+		APBC_UART4_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_UART5_BUS, uart5_bus_clk, uart5_bus_clk, "apb_clk",
+		APBC_UART5_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_UART6_BUS, uart6_bus_clk, uart6_bus_clk, "apb_clk",
+		APBC_UART6_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_UART7_BUS, uart7_bus_clk, uart7_bus_clk, "apb_clk",
+		APBC_UART7_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_UART8_BUS, uart8_bus_clk, uart8_bus_clk, "apb_clk",
+		APBC_UART8_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_UART9_BUS, uart9_bus_clk, uart9_bus_clk, "apb_clk",
+		APBC_UART9_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_UART10_BUS, uart10_bus_clk, uart10_bus_clk, "apb_clk",
+		APBC_UART10_CLK_RST, BIT(0), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_GPIO, gpio_clk, gpio_clk, "clock-24m",
+		APBC_GPIO_CLK_RST, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_GPIO_BUS, gpio_bus_clk, gpio_bus_clk, "apb_clk",
+		APBC_GPIO_CLK_RST, BIT(0), 0);
+
+static const char * const pwm_parents[] = {
+	"pll1_d192_12p8", "clock-32k",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM0, pwm0_clk, pwm0_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM1, pwm1_clk, pwm1_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM2, pwm2_clk, pwm2_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM3, pwm3_clk, pwm3_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM4, pwm4_clk, pwm4_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM5, pwm5_clk, pwm5_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM6, pwm6_clk, pwm6_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM7, pwm7_clk, pwm7_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM8, pwm8_clk, pwm8_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM9, pwm9_clk, pwm9_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM10, pwm10_clk, pwm10_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM11, pwm11_clk, pwm11_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM12, pwm12_clk, pwm12_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM13, pwm13_clk, pwm13_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM14, pwm14_clk, pwm14_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM15, pwm15_clk, pwm15_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM16, pwm16_clk, pwm16_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM17, pwm17_clk, pwm17_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM18, pwm18_clk, pwm18_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_PWM19, pwm19_clk, pwm19_clk, pwm_parents, ARRAY_SIZE(pwm_parents),
+		    APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_PWM0_BUS, pwm0_bus_clk, pwm0_bus_clk, "apb_clk",
+		APBC_PWM0_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM1_BUS, pwm1_bus_clk, pwm1_bus_clk, "apb_clk",
+		APBC_PWM1_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM2_BUS, pwm2_bus_clk, pwm2_bus_clk, "apb_clk",
+		APBC_PWM2_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM3_BUS, pwm3_bus_clk, pwm3_bus_clk, "apb_clk",
+		APBC_PWM3_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM4_BUS, pwm4_bus_clk, pwm4_bus_clk, "apb_clk",
+		APBC_PWM4_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM5_BUS, pwm5_bus_clk, pwm5_bus_clk, "apb_clk",
+		APBC_PWM5_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM6_BUS, pwm6_bus_clk, pwm6_bus_clk, "apb_clk",
+		APBC_PWM6_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM7_BUS, pwm7_bus_clk, pwm7_bus_clk, "apb_clk",
+		APBC_PWM7_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM8_BUS, pwm8_bus_clk, pwm8_bus_clk, "apb_clk",
+		APBC_PWM8_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM9_BUS, pwm9_bus_clk, pwm9_bus_clk, "apb_clk",
+		APBC_PWM9_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM10_BUS, pwm10_bus_clk, pwm10_bus_clk, "apb_clk",
+		APBC_PWM10_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM11_BUS, pwm11_bus_clk, pwm11_bus_clk, "apb_clk",
+		APBC_PWM11_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM12_BUS, pwm12_bus_clk, pwm12_bus_clk, "apb_clk",
+		APBC_PWM12_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM13_BUS, pwm13_bus_clk, pwm13_bus_clk, "apb_clk",
+		APBC_PWM13_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM14_BUS, pwm14_bus_clk, pwm14_bus_clk, "apb_clk",
+		APBC_PWM14_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM15_BUS, pwm15_bus_clk, pwm15_bus_clk, "apb_clk",
+		APBC_PWM15_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM16_BUS, pwm16_bus_clk, pwm16_bus_clk, "apb_clk",
+		APBC_PWM16_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM17_BUS, pwm17_bus_clk, pwm17_bus_clk, "apb_clk",
+		APBC_PWM17_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM18_BUS, pwm18_bus_clk, pwm18_bus_clk, "apb_clk",
+		APBC_PWM18_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_PWM19_BUS, pwm19_bus_clk, pwm19_bus_clk, "apb_clk",
+		APBC_PWM19_CLK_RST, BIT(0), 0);
+
+static const char * const i2s_bclk_parents[] = {
+	"clock-1m", "i2s_bclk",
+};
+CCU_MUX_DEFINE(CLK_APBC_SPI0_I2S_BCLK, spi0_i2s_bclk, spi0_i2s_bclk, i2s_bclk_parents, ARRAY_SIZE(i2s_bclk_parents),
+		APBC_SSP0_CLK_RST, 3, 1, 0);
+CCU_MUX_DEFINE(CLK_APBC_SPI1_I2S_BCLK, spi1_i2s_bclk, spi1_i2s_bclk, i2s_bclk_parents, ARRAY_SIZE(i2s_bclk_parents),
+		APBC_SSP1_CLK_RST, 3, 1, 0);
+CCU_MUX_DEFINE(CLK_APBC_SPI3_I2S_BCLK, spi3_i2s_bclk, spi3_i2s_bclk, i2s_bclk_parents, ARRAY_SIZE(i2s_bclk_parents),
+		APBC_SSP3_CLK_RST, 3, 1, 0);
+
+static const char * const spi0_parents[] = {
+	"pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", "pll1_d3072_0p8", "spi0_i2s_bclk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_SPI0, spi0_clk, spi0_clk, spi0_parents, ARRAY_SIZE(spi0_parents),
+		    APBC_SSP0_CLK_RST, 4, 3, BIT(1), 0);
+
+static const char * const spi1_parents[] = {
+	"pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", "pll1_d3072_0p8", "spi1_i2s_bclk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_SPI1, spi1_clk, spi1_clk, spi1_parents, ARRAY_SIZE(spi1_parents),
+		    APBC_SSP1_CLK_RST, 4, 3, BIT(1), 0);
+
+static const char * const spi3_parents[] = {
+	"pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", "pll1_d3072_0p8", "spi3_i2s_bclk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_SPI3, spi3_clk, spi3_clk, spi3_parents, ARRAY_SIZE(spi3_parents),
+		    APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_SPI0_BUS, spi0_bus_clk, spi0_bus_clk, "apb_clk",
+		APBC_SSP0_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_SPI1_BUS, spi1_bus_clk, spi1_bus_clk, "apb_clk",
+		APBC_SSP1_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_SPI3_BUS, spi3_bus_clk, spi3_bus_clk, "apb_clk",
+		APBC_SSP3_CLK_RST, BIT(0), 0);
+
+
+CCU_GATE_DEFINE(CLK_APBC_RTC, rtc_clk, rtc_clk, "clock-32k",
+		APBC_RTC_CLK_RST, BIT(7) | BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_RTC_BUS, rtc_bus_clk, rtc_bus_clk, "apb_clk",
+		APBC_RTC_CLK_RST, BIT(0), 0);
+
+static const char * const twsi_parents[] = {
+	"pll1_d78_31p5", "pll1_d48_51p2", "pll1_d40_61p44",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_TWSI0, twsi0_clk, twsi0_clk, twsi_parents, ARRAY_SIZE(twsi_parents),
+		    APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TWSI1, twsi1_clk, twsi1_clk, twsi_parents, ARRAY_SIZE(twsi_parents),
+		    APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TWSI2, twsi2_clk, twsi2_clk, twsi_parents, ARRAY_SIZE(twsi_parents),
+		    APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TWSI4, twsi4_clk, twsi4_clk, twsi_parents, ARRAY_SIZE(twsi_parents),
+		    APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TWSI5, twsi5_clk, twsi5_clk, twsi_parents, ARRAY_SIZE(twsi_parents),
+		    APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TWSI6, twsi6_clk, twsi6_clk, twsi_parents, ARRAY_SIZE(twsi_parents),
+		    APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TWSI8, twsi8_clk, twsi8_clk, twsi_parents, ARRAY_SIZE(twsi_parents),
+		    APBC_TWSI8_CLK_RST, 4, 3, BIT(1), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_TWSI0_BUS, twsi0_bus_clk, twsi0_bus_clk, "apb_clk",
+		APBC_TWSI0_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TWSI1_BUS, twsi1_bus_clk, twsi1_bus_clk, "apb_clk",
+		APBC_TWSI1_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TWSI2_BUS, twsi2_bus_clk, twsi2_bus_clk, "apb_clk",
+		APBC_TWSI2_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TWSI4_BUS, twsi4_bus_clk, twsi4_bus_clk, "apb_clk",
+		APBC_TWSI4_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TWSI5_BUS, twsi5_bus_clk, twsi5_bus_clk, "apb_clk",
+		APBC_TWSI5_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TWSI6_BUS, twsi6_bus_clk, twsi6_bus_clk, "apb_clk",
+		APBC_TWSI6_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TWSI8_BUS, twsi8_bus_clk, twsi8_bus_clk, "apb_clk",
+		APBC_TWSI8_CLK_RST, BIT(0), 0);
+
+static const char * const timer_parents[] = {
+	"pll1_d192_12p8", "clock-32k", "pll1_d384_6p4", "clock-3m", "clock-1m",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_TIMERS0, timers0_clk, timers0_clk, timer_parents, ARRAY_SIZE(timer_parents),
+		    APBC_TIMERS0_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TIMERS1, timers1_clk, timers1_clk, timer_parents, ARRAY_SIZE(timer_parents),
+		    APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TIMERS2, timers2_clk, timers2_clk, timer_parents, ARRAY_SIZE(timer_parents),
+		    APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TIMERS3, timers3_clk, timers3_clk, timer_parents, ARRAY_SIZE(timer_parents),
+		    APBC_TIMERS3_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TIMERS4, timers4_clk, timers4_clk, timer_parents, ARRAY_SIZE(timer_parents),
+		    APBC_TIMERS4_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TIMERS5, timers5_clk, timers5_clk, timer_parents, ARRAY_SIZE(timer_parents),
+		    APBC_TIMERS5_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TIMERS6, timers6_clk, timers6_clk, timer_parents, ARRAY_SIZE(timer_parents),
+		    APBC_TIMERS6_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_TIMERS7, timers7_clk, timers7_clk, timer_parents, ARRAY_SIZE(timer_parents),
+		    APBC_TIMERS7_CLK_RST, 4, 3, BIT(1), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_TIMERS0_BUS, timers0_bus_clk, timers0_bus_clk, "apb_clk",
+		APBC_TIMERS0_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TIMERS1_BUS, timers1_bus_clk, timers1_bus_clk, "apb_clk",
+		APBC_TIMERS1_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TIMERS2_BUS, timers2_bus_clk, timers2_bus_clk, "apb_clk",
+		APBC_TIMERS2_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TIMERS3_BUS, timers3_bus_clk, timers3_bus_clk, "apb_clk",
+		APBC_TIMERS3_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TIMERS4_BUS, timers4_bus_clk, timers4_bus_clk, "apb_clk",
+		APBC_TIMERS4_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TIMERS5_BUS, timers5_bus_clk, timers5_bus_clk, "apb_clk",
+		APBC_TIMERS5_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TIMERS6_BUS, timers6_bus_clk, timers6_bus_clk, "apb_clk",
+		APBC_TIMERS6_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_TIMERS7_BUS, timers7_bus_clk, timers7_bus_clk, "apb_clk",
+		APBC_TIMERS7_CLK_RST, BIT(0), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_AIB, aib_clk, aib_clk, "clock-24m",
+		APBC_AIB_CLK_RST, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_AIB_BUS, aib_bus_clk, aib_bus_clk, "apb_clk",
+		APBC_AIB_CLK_RST, BIT(0), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_ONEWIRE, onewire_clk, onewire_clk, "clock-24m",
+		APBC_ONEWIRE_CLK_RST, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_ONEWIRE_BUS, onewire_bus_clk, onewire_bus_clk, "apb_clk",
+		APBC_ONEWIRE_CLK_RST, BIT(0), 0);
+
+/*
+ * When i2s_bclk is selected as the parent clock of sspa,
+ * the hardware requires bit3 to be set
+ */
+
+CCU_MUX_DEFINE(CLK_APBC_I2S0_BCLK, i2s0_i2s_bclk, i2s0_i2s_bclk, i2s_bclk_parents, ARRAY_SIZE(i2s_bclk_parents),
+		APBC_SSPA0_CLK_RST, 3, 1, 0);
+CCU_MUX_DEFINE(CLK_APBC_I2S1_BCLK, i2s1_i2s_bclk, i2s1_i2s_bclk, i2s_bclk_parents, ARRAY_SIZE(i2s_bclk_parents),
+		APBC_SSPA1_CLK_RST, 3, 1, 0);
+CCU_MUX_DEFINE(CLK_APBC_I2S2_BCLK, i2s2_i2s_bclk, i2s2_i2s_bclk, i2s_bclk_parents, ARRAY_SIZE(i2s_bclk_parents),
+		APBC_SSPA2_CLK_RST, 3, 1, 0);
+CCU_MUX_DEFINE(CLK_APBC_I2S3_BCLK, i2s3_i2s_bclk, i2s3_i2s_bclk, i2s_bclk_parents, ARRAY_SIZE(i2s_bclk_parents),
+		APBC_SSPA3_CLK_RST, 3, 1, 0);
+CCU_MUX_DEFINE(CLK_APBC_I2S4_BCLK, i2s4_i2s_bclk, i2s4_i2s_bclk, i2s_bclk_parents, ARRAY_SIZE(i2s_bclk_parents),
+		APBC_SSPA4_CLK_RST, 3, 1, 0);
+CCU_MUX_DEFINE(CLK_APBC_I2S5_BCLK, i2s5_i2s_bclk, i2s5_i2s_bclk, i2s_bclk_parents, ARRAY_SIZE(i2s_bclk_parents),
+		APBC_SSPA5_CLK_RST, 3, 1, 0);
+
+static const char * const i2s0_parents[] = {
+	"pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", "pll1_d3072_0p8", "i2s0_i2s_bclk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_I2S0, i2s0_clk, i2s0_clk, i2s0_parents, ARRAY_SIZE(i2s0_parents),
+		    APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);
+
+static const char * const i2s1_parents[] = {
+	"pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", "pll1_d3072_0p8", "i2s1_i2s_bclk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_I2S1, i2s1_clk, i2s1_clk, i2s1_parents, ARRAY_SIZE(i2s1_parents),
+		    APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);
+
+static const char * const i2s2_parents[] = {
+	"pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", "pll1_d3072_0p8", "i2s2_i2s_bclk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_I2S2, i2s2_clk, i2s2_clk, i2s2_parents, ARRAY_SIZE(i2s2_parents),
+		    APBC_SSPA2_CLK_RST, 4, 3, BIT(1), 0);
+
+static const char * const i2s3_parents[] = {
+	"pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", "pll1_d3072_0p8", "i2s3_i2s_bclk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_I2S3, i2s3_clk, i2s3_clk, i2s3_parents, ARRAY_SIZE(i2s3_parents),
+		    APBC_SSPA3_CLK_RST, 4, 3, BIT(1), 0);
+
+static const char * const i2s4_parents[] = {
+	"pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", "pll1_d3072_0p8", "i2s4_i2s_bclk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_I2S4, i2s4_clk, i2s4_clk, i2s4_parents, ARRAY_SIZE(i2s4_parents),
+		    APBC_SSPA4_CLK_RST, 4, 3, BIT(1), 0);
+
+static const char * const i2s5_parents[] = {
+	"pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", "pll1_d3072_0p8", "i2s5_i2s_bclk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_I2S5, i2s5_clk, i2s5_clk, i2s5_parents, ARRAY_SIZE(i2s5_parents),
+		    APBC_SSPA5_CLK_RST, 4, 3, BIT(1), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_I2S0_BUS, i2s0_bus_clk, i2s0_bus_clk, "apb_clk",
+		APBC_SSPA0_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_I2S1_BUS, i2s1_bus_clk, i2s1_bus_clk, "apb_clk",
+		APBC_SSPA1_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_I2S2_BUS, i2s2_bus_clk, i2s2_bus_clk, "apb_clk",
+		APBC_SSPA2_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_I2S3_BUS, i2s3_bus_clk, i2s3_bus_clk, "apb_clk",
+		APBC_SSPA3_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_I2S4_BUS, i2s4_bus_clk, i2s4_bus_clk, "apb_clk",
+		APBC_SSPA4_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_I2S5_BUS, i2s5_bus_clk, i2s5_bus_clk, "apb_clk",
+		APBC_SSPA5_CLK_RST, BIT(0), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_DRO, dro_clk, dro_clk, "apb_clk",
+		APBC_DRO_CLK_RST, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_IR0, ir0_clk, ir0_clk, "apb_clk",
+		APBC_IR0_CLK_RST, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_IR1, ir1_clk, ir1_clk, "apb_clk",
+		APBC_IR1_CLK_RST, BIT(1), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_TSEN, tsen_clk, tsen_clk, "apb_clk",
+		APBC_TSEN_CLK_RST, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_TSEN_BUS, tsen_bus_clk, tsen_bus_clk, "apb_clk",
+		APBC_TSEN_CLK_RST, BIT(0), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_IPC_AP2RCPU, ipc_ap2rcpu_clk, ipc_ap2rcpu_clk, "apb_clk",
+		APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_IPC_AP2RCPU_BUS, ipc_ap2rcpu_bus_clk, ipc_ap2rcpu_bus_clk, "apb_clk",
+		APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0);
+
+static const char * const can_parents[] = {
+	"pll6_20", "pll6_40", "pll6_80",
+};
+CCU_MUX_GATE_DEFINE(CLK_APBC_CAN0, can0_clk, can0_clk, can_parents, ARRAY_SIZE(can_parents),
+		    APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_CAN1, can1_clk, can1_clk, can_parents, ARRAY_SIZE(can_parents),
+		    APBC_CAN1_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_CAN2, can2_clk, can2_clk, can_parents, ARRAY_SIZE(can_parents),
+		    APBC_CAN2_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_CAN3, can3_clk, can3_clk, can_parents, ARRAY_SIZE(can_parents),
+		    APBC_CAN3_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(CLK_APBC_CAN4, can4_clk, can4_clk, can_parents, ARRAY_SIZE(can_parents),
+		    APBC_CAN4_CLK_RST, 4, 3, BIT(1), 0);
+
+CCU_GATE_DEFINE(CLK_APBC_CAN0_BUS, can0_bus_clk, can0_bus_clk, "apb_clk",
+		APBC_CAN0_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_CAN1_BUS, can1_bus_clk, can1_bus_clk, "apb_clk",
+		APBC_CAN1_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_CAN2_BUS, can2_bus_clk, can2_bus_clk, "apb_clk",
+		APBC_CAN2_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_CAN3_BUS, can3_bus_clk, can3_bus_clk, "apb_clk",
+		APBC_CAN3_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_CAN4_BUS, can4_bus_clk, can4_bus_clk, "apb_clk",
+		APBC_CAN4_CLK_RST, BIT(0), 0);
+/* APBC clocks end */
+
+/* APMU clocks start */
+static const char * const axi_clk_parents[] = {
+	"pll1_d8_307p2", "pll1_d6_409p6",
+};
+CCU_MUX_DIV_FC_DEFINE(CLK_APMU_AXICLK, axi_clk, axi_clk, axi_clk_parents, ARRAY_SIZE(axi_clk_parents),
+		      APMU_ACLK_CLK_CTRL, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4),
+		      0, 1, 0);
+
+static const char * const cci550_clk_parents[] = {
+	"pll1_d10_245p76", "pll1_d6_409p6", "pll1_d4_614p4", "pll1_d3_819p2", "pll7_d3", "pll2_d3", "pll1_d2_1228p8", "pll7_d2",
+};
+CCU_MUX_DIV_FC_DEFINE(CLK_APMU_CCI550, cci550_clk, cci550_clk, cci550_clk_parents, ARRAY_SIZE(cci550_clk_parents),
+		      APMU_CCI550_CLK_CTRL, APMU_CCI550_CLK_CTRL, 8, 2, BIT(12),
+		      0, 3, CLK_IS_CRITICAL);
+
+static const char * const cpu_c0_clk_parents[] = {
+	"pll1_d3_819p2", "pll1_d5_491p52", "pll1_d4_614p4", "pll2_d3", "pll3_d2", "pll1_d2_1228p8", "pll2_d2", "pll3_d1",
+};
+CCU_MUX_DIV_FC_DEFINE(CLK_APMU_CPU_C0_CORE, cpu_c0_core_clk, cpu_c0_core_clk, cpu_c0_clk_parents, ARRAY_SIZE(cpu_c0_clk_parents),
+		      APMU_CPU_C0_CLK_CTRL, APMU_CPU_C0_CLK_CTRL, 3, 3, BIT(12),
+		      0, 3, CLK_IS_CRITICAL);
+
+static const char * const cpu_c1_clk_parents[] = {
+	"pll1_d3_819p2", "pll1_d5_491p52", "pll1_d4_614p4", "pll2_d3", "pll4_d2", "pll1_d2_1228p8", "pll2_d2", "pll4_d1",
+};
+CCU_MUX_DIV_FC_DEFINE(CLK_APMU_CPU_C1_CORE, cpu_c1_core_clk, cpu_c1_core_clk, cpu_c1_clk_parents, ARRAY_SIZE(cpu_c1_clk_parents),
+		      APMU_CPU_C1_CLK_CTRL, APMU_CPU_C1_CLK_CTRL, 3, 3, BIT(12),
+		      0, 3, CLK_IS_CRITICAL);
+
+static const char * const cpu_c2_clk_parents[] = {
+	"pll1_d3_819p2", "pll1_d5_491p52", "pll1_d4_614p4", "pll2_d3", "pll5_d2", "pll1_d2_1228p8", "pll2_d2", "pll5_d1",
+};
+CCU_MUX_DIV_FC_DEFINE(CLK_APMU_CPU_C2_CORE, cpu_c2_core_clk, cpu_c2_core_clk, cpu_c2_clk_parents, ARRAY_SIZE(cpu_c2_clk_parents),
+		      APMU_CPU_C2_CLK_CTRL, APMU_CPU_C2_CLK_CTRL, 3, 3, BIT(12),
+		      0, 3, CLK_IS_CRITICAL);
+
+static const char * const cpu_c3_clk_parents[] = {
+	"pll1_d3_819p2", "pll1_d5_491p52", "pll1_d4_614p4", "pll2_d3", "pll8_d2", "pll1_d2_1228p8", "pll2_d2", "pll8_d1",
+};
+CCU_MUX_DIV_FC_DEFINE(CLK_APMU_CPU_C3_CORE, cpu_c3_core_clk, cpu_c3_core_clk, cpu_c3_clk_parents, ARRAY_SIZE(cpu_c3_clk_parents),
+		      APMU_CPU_C3_CLK_CTRL, APMU_CPU_C3_CLK_CTRL, 3, 3, BIT(12),
+		      0, 3, CLK_IS_CRITICAL);
+
+static const char * const ccic2phy_parents[] = {
+	"pll1_d24_102p4", "pll1_d48_51p2_ap",
+};
+CCU_MUX_GATE_DEFINE(CLK_APMU_CCIC2PHY, ccic2phy_clk, ccic2phy_clk, ccic2phy_parents, ARRAY_SIZE(ccic2phy_parents),
+		    APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0);
+
+static const char * const ccic3phy_parents[] = {
+	"pll1_d24_102p4", "pll1_d48_51p2_ap",
+};
+CCU_MUX_GATE_DEFINE(CLK_APMU_CCIC3PHY, ccic3phy_clk, ccic3phy_clk, ccic3phy_parents, ARRAY_SIZE(ccic3phy_parents),
+		    APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0);
+
+static const char * const csi_parents[] = {
+	"pll1_d5_491p52", "pll1_d6_409p6", "pll1_d4_614p4", "pll1_d3_819p2", "pll2_d2", "pll2_d3", "pll2_d4", "pll1_d2_1228p8",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_CSI, csi_clk, csi_clk, csi_parents, ARRAY_SIZE(csi_parents),
+			   APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15),
+			   16, 3, BIT(4), 0);
+
+static const char * const isp_bus_parents[] = {
+	"pll1_d6_409p6", "pll1_d5_491p52", "pll1_d4_614p4", "pll1_d10_245p76",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_ISP_BUS, isp_bus_clk, isp_bus_clk, isp_bus_parents, ARRAY_SIZE(isp_bus_parents),
+			   APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23),
+			   21, 2, BIT(17), 0);
+
+CCU_GATE_DEFINE(CLK_APMU_D1P_1228P8, d1p_1228p8, d1p_1228p8, "pll1_d2_1228p8",
+		APMU_PMU_CLK_GATE_CTRL, BIT(31), 0);
+CCU_GATE_DEFINE(CLK_APMU_D1P_819P2, d1p_819p2, d1p_819p2, "pll1_d3_819p2",
+		APMU_PMU_CLK_GATE_CTRL, BIT(30), 0);
+CCU_GATE_DEFINE(CLK_APMU_D1P_614P4, d1p_614p4, d1p_614p4, "pll1_d4_614p4",
+		APMU_PMU_CLK_GATE_CTRL, BIT(29), 0);
+CCU_GATE_DEFINE(CLK_APMU_D1P_491P52, d1p_491p52, d1p_491p52, "pll1_d5_491p52",
+		APMU_PMU_CLK_GATE_CTRL, BIT(28), 0);
+CCU_GATE_DEFINE(CLK_APMU_D1P_409P6, d1p_409p6, d1p_409p6, "pll1_d6_409p6",
+		APMU_PMU_CLK_GATE_CTRL, BIT(27), 0);
+CCU_GATE_DEFINE(CLK_APMU_D1P_307P2, d1p_307p2, d1p_307p2, "pll1_d8_307p2",
+		APMU_PMU_CLK_GATE_CTRL, BIT(26), 0);
+CCU_GATE_DEFINE(CLK_APMU_D1P_245P76, d1p_245p76, d1p_245p76, "pll1_d10_245p76",
+		APMU_PMU_CLK_GATE_CTRL, BIT(22), 0);
+
+static const char * const v2d_parents[] = {
+	"pll1_d5_491p52", "pll2_d4", "pll1_d8_307p2", "pll1_d4_614p4",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_V2D, v2d_clk, v2d_clk, v2d_parents, ARRAY_SIZE(v2d_parents),
+			   APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28),
+			   12, 2, BIT(8), 0);
+
+static const char * const dsiesc_parents[] = {
+	"pll1_d48_51p2_ap", "pll1_d52_47p26", "pll1_d96_25p6", "pll1_d32_76p8",
+};
+CCU_MUX_GATE_DEFINE(CLK_APMU_DSI_ESC, dsi_esc_clk, dsi_esc_clk, dsiesc_parents, ARRAY_SIZE(dsiesc_parents),
+		    APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0);
+
+CCU_GATE_DEFINE(CLK_APMU_LCD_HCLK, lcd_hclk, lcd_hclk, "axi_clk",
+		APMU_LCD_CLK_RES_CTRL1, BIT(5), 0);
+
+static const char * const lcd_dsc_parents[] = {
+	"pll1_d4_614p4", "pll1_d5_491p52", "pll1_d10_245p76", "pll7_d5", "pll2_d7", "pll1_d6_409p6", "pll1_d48_51p2_ap", "pll2_d8",
+};
+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(CLK_APMU_LCD_DSC, lcd_dsc_clk, lcd_dsc_clk, lcd_dsc_parents, ARRAY_SIZE(lcd_dsc_parents),
+				 APMU_LCD_CLK_RES_CTRL2, APMU_LCD_CLK_RES_CTRL1, 25, 3, BIT(26),
+				 29, 3, BIT(14), 0);
+
+static const char * const lcdpx_parents[] = {
+	"pll1_d4_614p4", "pll1_d5_491p52", "pll1_d10_245p76", "pll7_d5", "pll2_d7", "pll2_d4", "pll1_d48_51p2_ap", "pll2_d8",
+};
+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(CLK_APMU_LCD_PXCLK, lcd_pxclk, lcd_pxclk, lcdpx_parents, ARRAY_SIZE(lcdpx_parents),
+				 APMU_LCD_CLK_RES_CTRL2, APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(30),
+				 21, 3, BIT(16), 0);
+
+static const char * const lcdmclk_parents[] = {
+	"pll1_d6_409p6", "pll1_d5_491p52", "pll1_d4_614p4", "pll1_d8_307p2",
+};
+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(CLK_APMU_LCD_MCLK, lcd_mclk, lcd_mclk, lcdmclk_parents, ARRAY_SIZE(lcdmclk_parents),
+				 APMU_LCD_CLK_RES_CTRL2, APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29),
+				 5, 3, BIT(0), 0);
+
+static const char * const ccic_4x_parents[] = {
+	"pll1_d5_491p52", "pll1_d6_409p6", "pll1_d4_614p4", "pll1_d3_819p2", "pll2_d2", "pll2_d3", "pll2_d4", "pll1_d2_1228p8",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_CCIC_4X, ccic_4x_clk, ccic_4x_clk, ccic_4x_parents, ARRAY_SIZE(ccic_4x_parents),
+			   APMU_CCIC_CLK_RES_CTRL, 18, 3, BIT(15),
+			   23, 2, BIT(4), 0);
+
+static const char * const ccic1phy_parents[] = {
+	"pll1_d24_102p4", "pll1_d48_51p2_ap",
+};
+CCU_MUX_GATE_DEFINE(CLK_APMU_CCIC1PHY, ccic1phy_clk, ccic1phy_clk, ccic1phy_parents, ARRAY_SIZE(ccic1phy_parents),
+		    APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0);
+
+
+static const char * const sc2hclk_parents[] = {
+	"pll1_d8_307p2", "pll1_d4_614p4", "pll1_d5_491p52", "pll2_d4",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_SC2_HCLK, sc2_hclk, sc2_hclk, sc2hclk_parents, ARRAY_SIZE(sc2hclk_parents),
+			   APMU_CCIC_CLK_RES_CTRL, 10, 3, BIT(16),
+			   8, 2, BIT(3), 0);
+
+CCU_GATE_DEFINE(CLK_APMU_SDH_AXI, sdh_axi_aclk, sdh_axi_aclk, "axi_clk",
+		APMU_SDH0_CLK_RES_CTRL, BIT(3), 0);
+static const char * const sdh01_parents[] = {
+	"pll1_d6_409p6", "pll1_d4_614p4", "pll2_d8", "pll2_d5", "reserved_clk", "reserved_clk", "pll1_dx",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_SDH0, sdh0_clk, sdh0_clk, sdh01_parents, ARRAY_SIZE(sdh01_parents),
+			   APMU_SDH0_CLK_RES_CTRL, 8, 3, BIT(11),
+			   5, 3, BIT(4), 0);
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_SDH1, sdh1_clk, sdh1_clk, sdh01_parents, ARRAY_SIZE(sdh01_parents),
+			   APMU_SDH1_CLK_RES_CTRL, 8, 3, BIT(11),
+			   5, 3, BIT(4), 0);
+static const char * const sdh2_parents[] = {
+	"pll1_d6_409p6", "pll1_d4_614p4", "pll2_d8", "pll1_d3_819p2", "reserved_clk", "reserved_clk", "pll1_dx",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_SDH2, sdh2_clk, sdh2_clk, sdh2_parents, ARRAY_SIZE(sdh2_parents),
+			   APMU_SDH2_CLK_RES_CTRL, 8, 3, BIT(11),
+			   5, 3, BIT(4), 0);
+
+CCU_GATE_DEFINE(CLK_APMU_USB2_BUS, usb2_bus_clk, usb2_bus_clk, "axi_clk",
+		APMU_USB_CLK_RES_CTRL, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APMU_USB3_PORTA_BUS, usb3_porta_bus_clk, usb3_porta_bus_clk, "axi_clk",
+		APMU_USB_CLK_RES_CTRL, BIT(4), 0);
+CCU_GATE_DEFINE(CLK_APMU_USB3_PORTB_BUS, usb3_portb_bus_clk, usb3_portb_bus_clk, "axi_clk",
+		APMU_USB_CLK_RES_CTRL, BIT(8), 0);
+CCU_GATE_DEFINE(CLK_APMU_USB3_PORTC_BUS, usb3_portc_bus_clk, usb3_portc_bus_clk, "axi_clk",
+		APMU_USB_CLK_RES_CTRL, BIT(12), 0);
+CCU_GATE_DEFINE(CLK_APMU_USB3_PORTD_BUS, usb3_portd_bus_clk, usb3_portd_bus_clk, "axi_clk",
+		APMU_USB_CLK_RES_CTRL, BIT(16), 0);
+
+static const char * const qspi_parents[] = {
+	"pll1_d6_409p6", "pll2_d8", "pll1_d8_307p2", "pll1_d10_245p76", "reserved_clk", "pll1_dx", "pll1_d5_491p52", "reserved_clk",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_QSPI, qspi_clk, qspi_clk, qspi_parents, ARRAY_SIZE(qspi_parents),
+			   APMU_QSPI_CLK_RES_CTRL, 9, 3, BIT(12),
+			   6, 3, BIT(4), 0);
+CCU_GATE_DEFINE(CLK_APMU_QSPI_BUS, qspi_bus_clk, qspi_bus_clk, "axi_clk",
+		APMU_QSPI_CLK_RES_CTRL, BIT(3), 0);
+
+CCU_GATE_DEFINE(CLK_APMU_DMA, dma_clk, dma_clk, "axi_clk",
+		APMU_DMA_CLK_RES_CTRL, BIT(3), 0);
+
+static const char * const aes_wtm_parents[] = {
+	"pll1_d12_204p8", "pll1_d24_102p4",
+};
+CCU_MUX_GATE_DEFINE(CLK_APMU_AES_WTM, aes_wtm_clk, aes_wtm_clk, aes_wtm_parents, ARRAY_SIZE(aes_wtm_parents),
+		    APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0);
+
+static const char * const vpu_parents[] = {
+	"pll1_d4_614p4", "pll1_d5_491p52", "pll1_d3_819p2", "pll1_d6_409p6", "pll1_d2_1228p8", "pll2_d3", "pll2_d4", "pll2_d5",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_VPU, vpu_clk, vpu_clk, vpu_parents, ARRAY_SIZE(vpu_parents),
+			   APMU_VPU_CLK_RES_CTRL, 13, 3, BIT(21),
+			   10, 3, BIT(3), 0);
+
+CCU_GATE_DEFINE(CLK_APMU_DTC, dtc_clk, dtc_clk, "axi_clk",
+		APMU_DTC_CLK_RES_CTRL, BIT(3), 0);
+
+static const char * const gpu_parents[] = {
+	"pll1_d4_614p4", "pll1_d5_491p52", "pll1_d3_819p2", "pll1_d6_409p6", "pll1_d2_1228p8", "pll2_d3", "pll2_d4", "pll2_d5",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_GPU, gpu_clk, gpu_clk, gpu_parents, ARRAY_SIZE(gpu_parents),
+			   APMU_GPU_CLK_RES_CTRL, 12, 3, BIT(15),
+			   18, 3, BIT(4), 0);
+
+CCU_GATE_DEFINE(CLK_APMU_MC_AHB, mc_ahb_clk, mc_ahb_clk, "axi_clk",
+		APMU_PMUA_MC_CTRL, BIT(1), 0);
+
+static const char * const top_parents[] = {
+	"pll1_d8_307p2", "pll1_d6_409p6", "pll3_d4", "pll6_d5", "pll7_d4", "pll6_d4", "pll7_d3", "pll6_d3",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_TOP_DCLK, top_dclk, top_dclk, top_parents, ARRAY_SIZE(top_parents),
+			   APMU_TOP_DCLK_CTRL, 5, 3, BIT(8),
+			   2, 3, BIT(1), CLK_IS_CRITICAL);
+
+static const char * const ucie_parents[] = {
+	"pll1_d8_307p2", "pll1_d6_409p6", "pll3_d4", "pll6_d5", "pll7_d4", "pll6_d4",
+};
+CCU_MUX_GATE_DEFINE(CLK_APMU_UCIE, ucie_clk, ucie_clk, ucie_parents, ARRAY_SIZE(ucie_parents),
+		    APMU_UCIE_CTRL, 4, 3, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APMU_UCIE_SBCLK, ucie_sbclk, ucie_sbclk, "axi_clk",
+		APMU_UCIE_CTRL, BIT(8), 0);
+
+static const char * const rcpu_clk_parents[] = {
+	"pll1_aud_245p7", "pll1_d8_307p2", "pll1_d5_491p52", "pll1_d6_409p6",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_RCPU, rcpu_clk, rcpu_clk, rcpu_clk_parents, ARRAY_SIZE(rcpu_clk_parents),
+			   APMU_RCPU_CLK_RES_CTRL, 4, 3, BIT(15),
+			   7, 3, BIT(12), 0);
+
+static const char * const dsi4ln2_dsi_esc_parents[] = {
+	"pll1_d48_51p2_ap", "pll1_d52_47p26", "pll1_d96_25p6", "pll1_d32_76p8",
+};
+CCU_MUX_GATE_DEFINE(CLK_APMU_DSI4LN2_DSI_ESC, dsi4ln2_dsi_esc_clk, dsi4ln2_dsi_esc_clk, dsi4ln2_dsi_esc_parents, ARRAY_SIZE(dsi4ln2_dsi_esc_parents),
+		    APMU_LCD_CLK_RES_CTRL3, 0, 1, BIT(2), 0);
+
+static const char * const dsi4ln2_lcd_dsc_parents[] = {
+	"pll1_d4_614p4", "pll1_d5_491p52", "pll7_d5", "pll6_d6", "pll2_d7", "pll1_d6_409p6", "pll1_d48_51p2_ap",
+};
+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(CLK_APMU_DSI4LN2_LCD_DSC, dsi4ln2_lcd_dsc_clk, dsi4ln2_lcd_dsc_clk, dsi4ln2_lcd_dsc_parents, ARRAY_SIZE(dsi4ln2_lcd_dsc_parents),
+				 APMU_LCD_CLK_RES_CTRL4, APMU_LCD_CLK_RES_CTRL3, 25, 3, BIT(26),
+				 29, 3, BIT(14), 0);
+
+static const char * const dsi4ln2_lcdpx_parents[] = {
+	"pll1_d4_614p4", "pll1_d5_491p52", "pll7_d5", "pll6_d6", "pll2_d7", "pll2_d4", "pll1_d48_51p2_ap", "pll2_d8",
+};
+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(CLK_APMU_DSI4LN2_LCD_PXCLK, dsi4ln2_lcd_pxclk, dsi4ln2_lcd_pxclk, dsi4ln2_lcdpx_parents, ARRAY_SIZE(dsi4ln2_lcdpx_parents),
+				 APMU_LCD_CLK_RES_CTRL4, APMU_LCD_CLK_RES_CTRL3, 17, 3, BIT(30),
+				 21, 3, BIT(16), 0);
+
+static const char * const dsi4ln2_lcd_mclk_parents[] = {
+	"pll1_d6_409p6", "pll1_d5_491p52", "pll1_d4_614p4", "pll1_d8_307p2",
+};
+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(CLK_APMU_DSI4LN2_LCD_MCLK, dsi4ln2_lcd_mclk, dsi4ln2_lcd_mclk, dsi4ln2_lcd_mclk_parents, ARRAY_SIZE(dsi4ln2_lcd_mclk_parents),
+				 APMU_LCD_CLK_RES_CTRL4, APMU_LCD_CLK_RES_CTRL3, 1, 4, BIT(29),
+				 5, 3, BIT(0), 0);
+
+static const char * const dpu_aclk_parents[] = {
+	"pll1_d6_409p6", "pll1_d5_491p52", "pll1_d4_614p4", "pll1_d8_307p2", "pll2_d4",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_DSI4LN2_DPU_ACLK, dsi4ln2_dpu_aclk, dsi4ln2_dpu_aclk, dpu_aclk_parents, ARRAY_SIZE(dpu_aclk_parents),
+			   APMU_LCD_CLK_RES_CTRL5, 2, 3, BIT(30),
+			   5, 3, BIT(1), 0);
+
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_DPU_ACLK, dpu_aclk, dpu_aclk, dpu_aclk_parents, ARRAY_SIZE(dpu_aclk_parents),
+			   APMU_LCD_CLK_RES_CTRL5, 17, 3, BIT(31),
+			   20, 3, BIT(16), 0);
+
+static const char * const ufs_aclk_parents[] = {
+	"pll1_d5_491p52", "pll1_d6_409p6", "pll2_d6", "pll2_d5",
+};
+CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_UFS_ACLK, ufs_aclk, ufs_aclk, ufs_aclk_parents, ARRAY_SIZE(ufs_aclk_parents),
+			   APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8),
+			   2, 3, BIT(1), 0);
+
+static const char * const edp0_pclk_parents[] = {
+	"lcd_pxclk", "external_clk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APMU_EDP0_PXCLK, edp0_pxclk, edp0_pxclk, edp0_pclk_parents, ARRAY_SIZE(edp0_pclk_parents),
+		    APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0);
+
+static const char * const edp1_pclk_parents[] = {
+	"dsi4ln2_lcd_pxclk", "external_clk",
+};
+CCU_MUX_GATE_DEFINE(CLK_APMU_EDP1_PXCLK, edp1_pxclk, edp1_pxclk, edp1_pclk_parents, ARRAY_SIZE(edp1_pclk_parents),
+		    APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0);
+
+CCU_GATE_DEFINE(CLK_APMU_PCIE_PORTA_MSTE, pciea_mstr_clk, pciea_mstr_clk, "pll2_d6",
+		APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0);
+CCU_GATE_DEFINE(CLK_APMU_PCIE_PORTA_SLV, pciea_slv_clk, pciea_slv_clk, "pll2_d6",
+		APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APMU_PCIE_PORTB_MSTE, pcieb_mstr_clk, pcieb_mstr_clk, "pll2_d6",
+		APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0);
+CCU_GATE_DEFINE(CLK_APMU_PCIE_PORTB_SLV, pcieb_slv_clk, pcieb_slv_clk, "pll2_d6",
+		APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APMU_PCIE_PORTC_MSTE, pciec_mstr_clk, pciec_mstr_clk, "pll2_d6",
+		APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0);
+CCU_GATE_DEFINE(CLK_APMU_PCIE_PORTC_SLV, pciec_slv_clk, pciec_slv_clk, "pll2_d6",
+		APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APMU_PCIE_PORTD_MSTE, pcied_mstr_clk, pcied_mstr_clk, "pll2_d6",
+		APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0);
+CCU_GATE_DEFINE(CLK_APMU_PCIE_PORTD_SLV, pcied_slv_clk, pcied_slv_clk, "pll2_d6",
+		APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APMU_PCIE_PORTE_MSTE, pciee_mstr_clk, pciee_mstr_clk, "pll2_d6",
+		APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0);
+CCU_GATE_DEFINE(CLK_APMU_PCIE_PORTE_SLV, pciee_slv_clk, pciee_slv_clk, "pll2_d6",
+		APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0);
+
+static const char * const emac_1588_parents[] = {
+	"clock-24m", "pll2_d24_125",
+};
+CCU_GATE_DEFINE(CLK_APMU_EMAC0_BUS, emac0_bus_clk, emac0_bus_clk, "axi_clk",
+		APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0);
+CCU_GATE_FLAGS_DEFINE(CLK_APMU_EMAC0_REF, emac0_ref_clk, emac0_ref_clk, "pll2_d120_25",
+		      APMU_EMAC0_CLK_RES_CTRL, BIT(14), true, 0);
+CCU_MUX_DEFINE(CLK_APMU_EMAC0_1588, emac0_1588_clk, emac0_1588_clk, emac_1588_parents, ARRAY_SIZE(emac_1588_parents),
+		APMU_EMAC0_CLK_RES_CTRL, 15, 1, 0);
+CCU_GATE_DEFINE(CLK_APMU_EMAC0_RGMII_TX, emac0_rgmii_tx_clk, emac0_rgmii_tx_clk, "pll2_d24_125",
+		APMU_EMAC0_CLK_RES_CTRL, BIT(8), 0);
+CCU_GATE_DEFINE(CLK_APMU_EMAC1_BUS, emac1_bus_clk, emac1_bus_clk, "axi_clk",
+		APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0);
+CCU_GATE_FLAGS_DEFINE(CLK_APMU_EMAC1_REF, emac1_ref_clk, emac1_ref_clk, "pll2_d120_25",
+		      APMU_EMAC1_CLK_RES_CTRL, BIT(14), true, 0);
+CCU_MUX_DEFINE(CLK_APMU_EMAC1_1588, emac1_1588_clk, emac1_1588_clk, emac_1588_parents, ARRAY_SIZE(emac_1588_parents),
+		APMU_EMAC1_CLK_RES_CTRL, 15, 1, 0);
+CCU_GATE_DEFINE(CLK_APMU_EMAC1_RGMII_TX, emac1_rgmii_tx_clk, emac1_rgmii_tx_clk, "pll2_d24_125",
+		APMU_EMAC1_CLK_RES_CTRL, BIT(8), 0);
+CCU_GATE_DEFINE(CLK_APMU_EMAC2_BUS, emac2_bus_clk, emac2_bus_clk, "axi_clk",
+		APMU_EMAC2_CLK_RES_CTRL, BIT(0), 0);
+CCU_GATE_FLAGS_DEFINE(CLK_APMU_EMAC2_REF, emac2_ref_clk, emac2_ref_clk, "pll2_d120_25",
+		      APMU_EMAC2_CLK_RES_CTRL, BIT(14), true, 0);
+CCU_MUX_DEFINE(CLK_APMU_EMAC2_1588, emac2_1588_clk, emac2_1588_clk, emac_1588_parents, ARRAY_SIZE(emac_1588_parents),
+		APMU_EMAC2_CLK_RES_CTRL, 15, 1, 0);
+CCU_GATE_DEFINE(CLK_APMU_EMAC2_RGMII_TX, emac2_rgmii_tx_clk, emac2_rgmii_tx_clk, "pll2_d24_125",
+		APMU_EMAC2_CLK_RES_CTRL, BIT(8), 0);
+
+static const char * const espi_sclk_src_parents[] = {
+	"pll2_20", "pll2_25", "pll2_33", "pll2_50", "pll2_66",
+};
+CCU_MUX_DEFINE(CLK_APMU_ESPI_SCLK_SRC, espi_sclk_src, espi_sclk_src, espi_sclk_src_parents, ARRAY_SIZE(espi_sclk_src_parents),
+		APMU_ESPI_CLK_RES_CTRL, 4, 3, 0);
+
+static const char * const espi_sclk_parents[] = {
+	"external_clk", "espi_sclk_src",
+};
+CCU_MUX_GATE_DEFINE(CLK_APMU_ESPI_SCLK, espi_sclk, espi_sclk, espi_sclk_parents, ARRAY_SIZE(espi_sclk_parents),
+		    APMU_ESPI_CLK_RES_CTRL, 7, 1, BIT(3), 0);
+
+CCU_GATE_DEFINE(CLK_APMU_ESPI_MCLK, espi_mclk, espi_mclk, "axi_clk",
+		APMU_ESPI_CLK_RES_CTRL, BIT(1), 0);
+
+CCU_FACTOR_DEFINE(CLK_APMU_CAM_SRC1, cam_src1_clk, cam_src1_clk, "pll1_d6_409p6", 15, 1);
+CCU_FACTOR_DEFINE(CLK_APMU_CAM_SRC2, cam_src2_clk, cam_src2_clk, "pll2_d5", 25, 1);
+CCU_FACTOR_DEFINE(CLK_APMU_CAM_SRC3, cam_src3_clk, cam_src3_clk, "pll2_d6", 20, 1);
+CCU_FACTOR_DEFINE(CLK_APMU_CAM_SRC4, cam_src4_clk, cam_src4_clk, "pll1_d6_409p6", 16, 1);
+
+static const char * const isim_vclk_parents[] = {
+	"cam_src1_clk", "cam_src2_clk", "cam_src3_clk", "cam_src4_clk",
+};
+CCU_MUX_DIV_GATE_DEFINE(CLK_APMU_ISIM_VCLK0, isim_vclk_out0, isim_vclk_out0, isim_vclk_parents, ARRAY_SIZE(isim_vclk_parents),
+			APMU_SNR_ISIM_VCLK_CTRL, 3, 4, 1, 2,
+			BIT(0), 0);
+CCU_MUX_DIV_GATE_DEFINE(CLK_APMU_ISIM_VCLK1, isim_vclk_out1, isim_vclk_out1, isim_vclk_parents, ARRAY_SIZE(isim_vclk_parents),
+			APMU_SNR_ISIM_VCLK_CTRL, 11, 4, 9, 2,
+			BIT(8), 0);
+CCU_MUX_DIV_GATE_DEFINE(CLK_APMU_ISIM_VCLK2, isim_vclk_out2, isim_vclk_out2, isim_vclk_parents, ARRAY_SIZE(isim_vclk_parents),
+			APMU_SNR_ISIM_VCLK_CTRL, 19, 4, 17, 2,
+			BIT(16), 0);
+CCU_MUX_DIV_GATE_DEFINE(CLK_APMU_ISIM_VCLK3, isim_vclk_out3, isim_vclk_out3, isim_vclk_parents, ARRAY_SIZE(isim_vclk_parents),
+			APMU_SNR_ISIM_VCLK_CTRL, 27, 4, 25, 2,
+			BIT(24), 0);
+/* APMU clocks end */
+
+/* DCIU clocks start */
+CCU_GATE_DEFINE(CLK_DCIU_HDMA, hdma_clk, hdma_clk, "axi_clk",
+		DCIU_DMASYS_CLK_EN, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_DCIU_DMA350, dma350_clk, dma350_clk, "axi_clk",
+		DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_DCIU_C2_TCM_PIPE, c2_tcm_pipe_clk, c2_tcm_pipe_clk, "axi_clk",
+		DCIU_C2_TCM_PIPE_CLK, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_DCIU_C3_TCM_PIPE, c3_tcm_pipe_clk, c3_tcm_pipe_clk, "axi_clk",
+		DCIU_C3_TCM_PIPE_CLK, BIT(0), 0);
+/* DCIU clocks end */
+
+
+
+
+
+
+
+
+
+
+
+
+static struct clk *k3_ccu_pll_clks[] = {
+	&pll1.common.clk,
+	&pll2.common.clk,
+	&pll3.common.clk,
+	&pll4.common.clk,
+	&pll5.common.clk,
+	&pll6.common.clk,
+	&pll7.common.clk,
+	&pll8.common.clk,
+	&pll1_d2.common.clk,
+	&pll1_d3.common.clk,
+	&pll1_d4.common.clk,
+	&pll1_d5.common.clk,
+	&pll1_d6.common.clk,
+	&pll1_d7.common.clk,
+	&pll1_d8.common.clk,
+	&pll1_dx.common.clk,
+	&pll1_d64_38p4.common.clk,
+	&pll1_aud_245p7.common.clk,
+	&pll1_aud_24p5.common.clk,
+	&pll2_d1.common.clk,
+	&pll2_d2.common.clk,
+	&pll2_d3.common.clk,
+	&pll2_d4.common.clk,
+	&pll2_d5.common.clk,
+	&pll2_d6.common.clk,
+	&pll2_d7.common.clk,
+	&pll2_d8.common.clk,
+	&pll2_66.common.clk,
+	&pll2_33.common.clk,
+	&pll2_50.common.clk,
+	&pll2_25.common.clk,
+	&pll2_20.common.clk,
+	&pll2_d24_125.common.clk,
+	&pll2_d120_25.common.clk,
+	&pll3_d1.common.clk,
+	&pll3_d2.common.clk,
+	&pll3_d3.common.clk,
+	&pll3_d4.common.clk,
+	&pll3_d5.common.clk,
+	&pll3_d6.common.clk,
+	&pll3_d7.common.clk,
+	&pll3_d8.common.clk,
+	&pll4_d1.common.clk,
+	&pll4_d2.common.clk,
+	&pll4_d3.common.clk,
+	&pll4_d4.common.clk,
+	&pll4_d5.common.clk,
+	&pll4_d6.common.clk,
+	&pll4_d7.common.clk,
+	&pll4_d8.common.clk,
+	&pll5_d1.common.clk,
+	&pll5_d2.common.clk,
+	&pll5_d3.common.clk,
+	&pll5_d4.common.clk,
+	&pll5_d5.common.clk,
+	&pll5_d6.common.clk,
+	&pll5_d7.common.clk,
+	&pll5_d8.common.clk,
+	&pll6_d1.common.clk,
+	&pll6_d2.common.clk,
+	&pll6_d3.common.clk,
+	&pll6_d4.common.clk,
+	&pll6_d5.common.clk,
+	&pll6_d6.common.clk,
+	&pll6_d7.common.clk,
+	&pll6_d8.common.clk,
+	&pll6_80.common.clk,
+	&pll6_40.common.clk,
+	&pll6_20.common.clk,
+	&pll7_d1.common.clk,
+	&pll7_d2.common.clk,
+	&pll7_d3.common.clk,
+	&pll7_d4.common.clk,
+	&pll7_d5.common.clk,
+	&pll7_d6.common.clk,
+	&pll7_d7.common.clk,
+	&pll7_d8.common.clk,
+	&pll8_d1.common.clk,
+	&pll8_d2.common.clk,
+	&pll8_d3.common.clk,
+	&pll8_d4.common.clk,
+	&pll8_d5.common.clk,
+	&pll8_d6.common.clk,
+	&pll8_d7.common.clk,
+	&pll8_d8.common.clk,
+};
+
+static const struct spacemit_ccu_data k3_ccu_pll_data = {
+	.clks		= k3_ccu_pll_clks,
+	.num		= ARRAY_SIZE(k3_ccu_pll_clks),
+	.offset		= K3_PLL_ID,
+};
+
+static struct clk *k3_ccu_mpmu_clks[] = {
+	&pll1_d8_307p2.common.clk,
+	&pll1_d32_76p8.common.clk,
+	&pll1_d40_61p44.common.clk,
+	&pll1_d16_153p6.common.clk,
+	&pll1_d24_102p4.common.clk,
+	&pll1_d48_51p2.common.clk,
+	&pll1_d48_51p2_ap.common.clk,
+	&pll1_m3d128_57p6.common.clk,
+	&pll1_d96_25p6.common.clk,
+	&pll1_d192_12p8.common.clk,
+	&pll1_d192_12p8_wdt.common.clk,
+	&pll1_d384_6p4.common.clk,
+	&pll1_d768_3p2.common.clk,
+	&pll1_d1536_1p6.common.clk,
+	&pll1_d3072_0p8.common.clk,
+	&pll1_d6_409p6.common.clk,
+	&pll1_d12_204p8.common.clk,
+	&pll1_d5_491p52.common.clk,
+	&pll1_d10_245p76.common.clk,
+	&pll1_d4_614p4.common.clk,
+	&pll1_d52_47p26.common.clk,
+	&pll1_d78_31p5.common.clk,
+	&pll1_d3_819p2.common.clk,
+	&pll1_d2_1228p8.common.clk,
+	&apb_clk.common.clk,
+	&slow_uart.common.clk,
+	&slow_uart1_14p74.common.clk,
+	&slow_uart2_48.common.clk,
+	&wdt_clk.common.clk,
+	&wdt_bus_clk.common.clk,
+	&r_ipc_clk.common.clk,
+	&i2s_153p6.common.clk,
+	&i2s_153p6_base.common.clk,
+	&i2s_sysclk_src.common.clk,
+	&i2s1_sysclk.common.clk,
+	&i2s_bclk.common.clk,
+	&i2s0_sysclk_sel.common.clk,
+	&i2s2_sysclk_sel.common.clk,
+	&i2s3_sysclk_sel.common.clk,
+	&i2s4_sysclk_sel.common.clk,
+	&i2s5_sysclk_sel.common.clk,
+	&i2s0_sysclk_div.common.clk,
+	&i2s2_sysclk_div.common.clk,
+	&i2s3_sysclk_div.common.clk,
+	&i2s4_sysclk_div.common.clk,
+	&i2s5_sysclk_div.common.clk,
+	&i2s0_sysclk.common.clk,
+	&i2s2_sysclk.common.clk,
+	&i2s3_sysclk.common.clk,
+	&i2s4_sysclk.common.clk,
+	&i2s5_sysclk.common.clk,
+};
+
+static const struct spacemit_ccu_data k3_ccu_mpmu_data = {
+	.clks		= k3_ccu_mpmu_clks,
+	.num		= ARRAY_SIZE(k3_ccu_mpmu_clks),
+	.offset		= K3_MPMU_ID,
+};
+
+static struct clk *k3_ccu_apbc_clks[] = {
+	&uart0_clk.common.clk,
+	&uart2_clk.common.clk,
+	&uart3_clk.common.clk,
+	&uart4_clk.common.clk,
+	&uart5_clk.common.clk,
+	&uart6_clk.common.clk,
+	&uart7_clk.common.clk,
+	&uart8_clk.common.clk,
+	&uart9_clk.common.clk,
+	&uart10_clk.common.clk,
+	&uart0_bus_clk.common.clk,
+	&uart2_bus_clk.common.clk,
+	&uart3_bus_clk.common.clk,
+	&uart4_bus_clk.common.clk,
+	&uart5_bus_clk.common.clk,
+	&uart6_bus_clk.common.clk,
+	&uart7_bus_clk.common.clk,
+	&uart8_bus_clk.common.clk,
+	&uart9_bus_clk.common.clk,
+	&uart10_bus_clk.common.clk,
+	&gpio_clk.common.clk,
+	&gpio_bus_clk.common.clk,
+	&pwm0_clk.common.clk,
+	&pwm1_clk.common.clk,
+	&pwm2_clk.common.clk,
+	&pwm3_clk.common.clk,
+	&pwm4_clk.common.clk,
+	&pwm5_clk.common.clk,
+	&pwm6_clk.common.clk,
+	&pwm7_clk.common.clk,
+	&pwm8_clk.common.clk,
+	&pwm9_clk.common.clk,
+	&pwm10_clk.common.clk,
+	&pwm11_clk.common.clk,
+	&pwm12_clk.common.clk,
+	&pwm13_clk.common.clk,
+	&pwm14_clk.common.clk,
+	&pwm15_clk.common.clk,
+	&pwm16_clk.common.clk,
+	&pwm17_clk.common.clk,
+	&pwm18_clk.common.clk,
+	&pwm19_clk.common.clk,
+	&pwm0_bus_clk.common.clk,
+	&pwm1_bus_clk.common.clk,
+	&pwm2_bus_clk.common.clk,
+	&pwm3_bus_clk.common.clk,
+	&pwm4_bus_clk.common.clk,
+	&pwm5_bus_clk.common.clk,
+	&pwm6_bus_clk.common.clk,
+	&pwm7_bus_clk.common.clk,
+	&pwm8_bus_clk.common.clk,
+	&pwm9_bus_clk.common.clk,
+	&pwm10_bus_clk.common.clk,
+	&pwm11_bus_clk.common.clk,
+	&pwm12_bus_clk.common.clk,
+	&pwm13_bus_clk.common.clk,
+	&pwm14_bus_clk.common.clk,
+	&pwm15_bus_clk.common.clk,
+	&pwm16_bus_clk.common.clk,
+	&pwm17_bus_clk.common.clk,
+	&pwm18_bus_clk.common.clk,
+	&pwm19_bus_clk.common.clk,
+	&spi0_i2s_bclk.common.clk,
+	&spi1_i2s_bclk.common.clk,
+	&spi3_i2s_bclk.common.clk,
+	&spi0_clk.common.clk,
+	&spi1_clk.common.clk,
+	&spi3_clk.common.clk,
+	&spi0_bus_clk.common.clk,
+	&spi1_bus_clk.common.clk,
+	&spi3_bus_clk.common.clk,
+	&rtc_clk.common.clk,
+	&rtc_bus_clk.common.clk,
+	&twsi0_clk.common.clk,
+	&twsi1_clk.common.clk,
+	&twsi2_clk.common.clk,
+	&twsi4_clk.common.clk,
+	&twsi5_clk.common.clk,
+	&twsi6_clk.common.clk,
+	&twsi8_clk.common.clk,
+	&twsi0_bus_clk.common.clk,
+	&twsi1_bus_clk.common.clk,
+	&twsi2_bus_clk.common.clk,
+	&twsi4_bus_clk.common.clk,
+	&twsi5_bus_clk.common.clk,
+	&twsi6_bus_clk.common.clk,
+	&twsi8_bus_clk.common.clk,
+	&timers0_clk.common.clk,
+	&timers1_clk.common.clk,
+	&timers2_clk.common.clk,
+	&timers3_clk.common.clk,
+	&timers4_clk.common.clk,
+	&timers5_clk.common.clk,
+	&timers6_clk.common.clk,
+	&timers7_clk.common.clk,
+	&timers0_bus_clk.common.clk,
+	&timers1_bus_clk.common.clk,
+	&timers2_bus_clk.common.clk,
+	&timers3_bus_clk.common.clk,
+	&timers4_bus_clk.common.clk,
+	&timers5_bus_clk.common.clk,
+	&timers6_bus_clk.common.clk,
+	&timers7_bus_clk.common.clk,
+	&aib_clk.common.clk,
+	&aib_bus_clk.common.clk,
+	&onewire_clk.common.clk,
+	&onewire_bus_clk.common.clk,
+	&i2s0_i2s_bclk.common.clk,
+	&i2s1_i2s_bclk.common.clk,
+	&i2s2_i2s_bclk.common.clk,
+	&i2s3_i2s_bclk.common.clk,
+	&i2s4_i2s_bclk.common.clk,
+	&i2s5_i2s_bclk.common.clk,
+	&i2s0_clk.common.clk,
+	&i2s1_clk.common.clk,
+	&i2s2_clk.common.clk,
+	&i2s3_clk.common.clk,
+	&i2s4_clk.common.clk,
+	&i2s5_clk.common.clk,
+	&i2s0_bus_clk.common.clk,
+	&i2s1_bus_clk.common.clk,
+	&i2s2_bus_clk.common.clk,
+	&i2s3_bus_clk.common.clk,
+	&i2s4_bus_clk.common.clk,
+	&i2s5_bus_clk.common.clk,
+	&dro_clk.common.clk,
+	&ir0_clk.common.clk,
+	&ir1_clk.common.clk,
+	&tsen_clk.common.clk,
+	&tsen_bus_clk.common.clk,
+	&ipc_ap2rcpu_clk.common.clk,
+	&ipc_ap2rcpu_bus_clk.common.clk,
+	&can0_clk.common.clk,
+	&can1_clk.common.clk,
+	&can2_clk.common.clk,
+	&can3_clk.common.clk,
+	&can4_clk.common.clk,
+	&can0_bus_clk.common.clk,
+	&can1_bus_clk.common.clk,
+	&can2_bus_clk.common.clk,
+	&can3_bus_clk.common.clk,
+	&can4_bus_clk.common.clk,
+};
+
+static const struct spacemit_ccu_data k3_ccu_apbc_data = {
+	.clks		= k3_ccu_apbc_clks,
+	.num		= ARRAY_SIZE(k3_ccu_apbc_clks),
+	.offset		= K3_APBC_ID,
+};
+
+static struct clk *k3_ccu_apmu_clks[] = {
+	&axi_clk.common.clk,
+	&cci550_clk.common.clk,
+	&cpu_c0_core_clk.common.clk,
+	&cpu_c1_core_clk.common.clk,
+	&cpu_c2_core_clk.common.clk,
+	&cpu_c3_core_clk.common.clk,
+	&ccic2phy_clk.common.clk,
+	&ccic3phy_clk.common.clk,
+	&csi_clk.common.clk,
+	&isp_bus_clk.common.clk,
+	&d1p_1228p8.common.clk,
+	&d1p_819p2.common.clk,
+	&d1p_614p4.common.clk,
+	&d1p_491p52.common.clk,
+	&d1p_409p6.common.clk,
+	&d1p_307p2.common.clk,
+	&d1p_245p76.common.clk,
+	&v2d_clk.common.clk,
+	&dsi_esc_clk.common.clk,
+	&lcd_hclk.common.clk,
+	&lcd_dsc_clk.common.clk,
+	&lcd_pxclk.common.clk,
+	&lcd_mclk.common.clk,
+	&ccic_4x_clk.common.clk,
+	&ccic1phy_clk.common.clk,
+	&sc2_hclk.common.clk,
+	&sdh_axi_aclk.common.clk,
+	&sdh0_clk.common.clk,
+	&sdh1_clk.common.clk,
+	&sdh2_clk.common.clk,
+	&usb2_bus_clk.common.clk,
+	&usb3_porta_bus_clk.common.clk,
+	&usb3_portb_bus_clk.common.clk,
+	&usb3_portc_bus_clk.common.clk,
+	&usb3_portd_bus_clk.common.clk,
+	&qspi_clk.common.clk,
+	&qspi_bus_clk.common.clk,
+	&dma_clk.common.clk,
+	&aes_wtm_clk.common.clk,
+	&vpu_clk.common.clk,
+	&dtc_clk.common.clk,
+	&gpu_clk.common.clk,
+	&mc_ahb_clk.common.clk,
+	&top_dclk.common.clk,
+	&ucie_clk.common.clk,
+	&ucie_sbclk.common.clk,
+	&rcpu_clk.common.clk,
+	&dsi4ln2_dsi_esc_clk.common.clk,
+	&dsi4ln2_lcd_dsc_clk.common.clk,
+	&dsi4ln2_lcd_pxclk.common.clk,
+	&dsi4ln2_lcd_mclk.common.clk,
+	&dsi4ln2_dpu_aclk.common.clk,
+	&dpu_aclk.common.clk,
+	&ufs_aclk.common.clk,
+	&edp0_pxclk.common.clk,
+	&edp1_pxclk.common.clk,
+	&pciea_mstr_clk.common.clk,
+	&pciea_slv_clk.common.clk,
+	&pcieb_mstr_clk.common.clk,
+	&pcieb_slv_clk.common.clk,
+	&pciec_mstr_clk.common.clk,
+	&pciec_slv_clk.common.clk,
+	&pcied_mstr_clk.common.clk,
+	&pcied_slv_clk.common.clk,
+	&pciee_mstr_clk.common.clk,
+	&pciee_slv_clk.common.clk,
+	&emac0_bus_clk.common.clk,
+	&emac0_ref_clk.common.clk,
+	&emac0_1588_clk.common.clk,
+	&emac0_rgmii_tx_clk.common.clk,
+	&emac1_bus_clk.common.clk,
+	&emac1_ref_clk.common.clk,
+	&emac1_1588_clk.common.clk,
+	&emac1_rgmii_tx_clk.common.clk,
+	&emac2_bus_clk.common.clk,
+	&emac2_ref_clk.common.clk,
+	&emac2_1588_clk.common.clk,
+	&emac2_rgmii_tx_clk.common.clk,
+	&espi_sclk_src.common.clk,
+	&espi_sclk.common.clk,
+	&espi_mclk.common.clk,
+	&cam_src1_clk.common.clk,
+	&cam_src2_clk.common.clk,
+	&cam_src3_clk.common.clk,
+	&cam_src4_clk.common.clk,
+	&isim_vclk_out0.common.clk,
+	&isim_vclk_out1.common.clk,
+	&isim_vclk_out2.common.clk,
+	&isim_vclk_out3.common.clk,
+};
+
+static const struct spacemit_ccu_data k3_ccu_apmu_data = {
+	.clks		= k3_ccu_apmu_clks,
+	.num		= ARRAY_SIZE(k3_ccu_apmu_clks),
+	.offset		= K3_APMU_ID,
+};
+
+/*
+ * These clocks are marked as CLK_IS_CRITICAL, but unlike the
+ * kernel, U-Boot has no mechanism to enable critical clocks.
+ * Enable them explicitly here, otherwise Linux gets stuck
+ * halfway through boot.
+ */
+static struct clk *const k3_apmu_boot_clks[] = {
+	&cpu_c0_core_clk.common.clk,
+	&cpu_c1_core_clk.common.clk,
+	&cpu_c2_core_clk.common.clk,
+	&cpu_c3_core_clk.common.clk,
+};
+
+static struct clk *k3_ccu_dciu_clks[] = {
+	&hdma_clk.common.clk,
+	&dma350_clk.common.clk,
+	&c2_tcm_pipe_clk.common.clk,
+	&c3_tcm_pipe_clk.common.clk,
+};
+
+static const struct spacemit_ccu_data k3_ccu_dciu_data = {
+	.clks		= k3_ccu_dciu_clks,
+	.num		= ARRAY_SIZE(k3_ccu_dciu_clks),
+	.offset		= K3_DCIU_ID,
+};
+
+static int k3_clk_force_probe(const struct driver *drv)
+{
+	struct udevice *dev;
+
+	return uclass_get_device_by_driver(UCLASS_CLK, drv, &dev);
+}
+
+static int k3_clk_register(struct udevice *dev, struct regmap *regmap,
+			   struct regmap *lock_regmap,
+			   const struct spacemit_ccu_data *data)
+{
+	int i, ret;
+
+	for (i = 0; i < data->num; i++) {
+		struct clk *clk = data->clks[i];
+		struct ccu_common *common;
+
+		if (!clk)
+			continue;
+
+		common = clk_to_ccu_common(clk);
+		common->regmap = regmap;
+		common->lock_regmap = lock_regmap;
+
+		if (common->clk.id < K3_PLL_ID)
+			clk->id = common->clk.id + data->offset;
+		else
+			clk->id = common->clk.id;
+
+		ret = common->init(common);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int k3_pll_clk_probe(struct udevice *dev)
+{
+	struct regmap *base_regmap, *lock_regmap = NULL;
+	const struct spacemit_ccu_data *data;
+	int ret;
+
+	clk_register_fixed_rate(NULL, "clock-dummy", 0);
+
+	ret = regmap_init_mem(dev_ofnode(dev), &base_regmap);
+	if (ret)
+		return ret;
+
+	if (device_is_compatible(dev, "spacemit,k3-pll")) {
+		struct ofnode_phandle_args mpmu_args;
+
+		ret = dev_read_phandle_with_args(dev, "spacemit,mpmu", NULL, 0, 0,
+						 &mpmu_args);
+		if (ret)
+			return ret;
+
+		ret = regmap_init_mem(mpmu_args.node, &lock_regmap);
+		if (ret)
+			return ret;
+	}
+
+	data = (struct spacemit_ccu_data *)dev_get_driver_data(dev);
+
+	ret = k3_clk_register(dev, base_regmap, lock_regmap, data);
+	if (ret)
+		return -EPROBE_DEFER;
+
+	return 0;
+}
+
+static int k3_mpmu_clk_probe(struct udevice *dev)
+{
+	struct regmap *base_regmap;
+	const struct spacemit_ccu_data *data;
+	int ret;
+
+	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_pll_clk));
+	if (ret)
+		return ret;
+
+	ret = regmap_init_mem(dev_ofnode(dev), &base_regmap);
+	if (ret)
+		return ret;
+
+	data = (struct spacemit_ccu_data *)dev_get_driver_data(dev);
+
+	ret = k3_clk_register(dev, base_regmap, NULL, data);
+	if (ret)
+		return -EPROBE_DEFER;
+
+	return 0;
+}
+
+static int k3_apmu_clk_probe(struct udevice *dev)
+{
+	struct regmap *base_regmap;
+	const struct spacemit_ccu_data *data;
+	int i, ret;
+
+	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_pll_clk));
+	if (ret)
+		return ret;
+	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_mpmu_clk));
+	if (ret)
+		return ret;
+
+	ret = regmap_init_mem(dev_ofnode(dev), &base_regmap);
+	if (ret)
+		return ret;
+
+	data = (struct spacemit_ccu_data *)dev_get_driver_data(dev);
+
+	ret = k3_clk_register(dev, base_regmap, NULL, data);
+	if (ret)
+		return -EPROBE_DEFER;
+
+	for (i = 0; i < ARRAY_SIZE(k3_apmu_boot_clks); i++) {
+		ret = clk_enable(k3_apmu_boot_clks[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int k3_apbc_clk_probe(struct udevice *dev)
+{
+	struct regmap *base_regmap;
+	const struct spacemit_ccu_data *data;
+	int ret;
+
+	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_pll_clk));
+	if (ret)
+		return ret;
+	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_mpmu_clk));
+	if (ret)
+		return ret;
+	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_apmu_clk));
+	if (ret)
+		return ret;
+
+	ret = regmap_init_mem(dev_ofnode(dev), &base_regmap);
+	if (ret)
+		return ret;
+
+	data = (struct spacemit_ccu_data *)dev_get_driver_data(dev);
+
+	ret = k3_clk_register(dev, base_regmap, NULL, data);
+	if (ret)
+		return -EPROBE_DEFER;
+
+	return 0;
+}
+
+static int k3_dciu_clk_probe(struct udevice *dev)
+{
+	struct regmap *base_regmap;
+	const struct spacemit_ccu_data *data;
+	int ret;
+
+	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_pll_clk));
+	if (ret)
+		return ret;
+	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_mpmu_clk));
+	if (ret)
+		return ret;
+	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_apmu_clk));
+	if (ret)
+		return ret;
+
+	ret = regmap_init_mem(dev_ofnode(dev), &base_regmap);
+	if (ret)
+		return ret;
+
+	data = (struct spacemit_ccu_data *)dev_get_driver_data(dev);
+
+	ret = k3_clk_register(dev, base_regmap, NULL, data);
+	if (ret)
+		return -EPROBE_DEFER;
+
+	return 0;
+}
+
+static int k3_pll_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count > 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		clk->id = K3_PLL_ID + args->args[0];
+	else
+		clk->id = K3_PLL_ID;
+
+	return 0;
+}
+
+static int k3_mpmu_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count > 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		clk->id = K3_MPMU_ID + args->args[0];
+	else
+		clk->id = K3_MPMU_ID;
+
+	return 0;
+}
+
+static int k3_apbc_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count > 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		clk->id = K3_APBC_ID + args->args[0];
+	else
+		clk->id = K3_APBC_ID;
+
+	return 0;
+}
+
+static int k3_apmu_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count > 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		clk->id = K3_APMU_ID + args->args[0];
+	else
+		clk->id = K3_APMU_ID;
+
+	return 0;
+}
+
+static int k3_dciu_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+	if (args->args_count > 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		clk->id = K3_DCIU_ID + args->args[0];
+	else
+		clk->id = K3_DCIU_ID;
+
+	return 0;
+}
+
+#define K3_CLK_OPS(name)				\
+static const struct clk_ops k3_##name##_clk_ops = {	\
+		.set_rate = ccf_clk_set_rate,		\
+		.get_rate = ccf_clk_get_rate,		\
+		.enable = ccf_clk_enable,		\
+		.disable = ccf_clk_disable,		\
+		.set_parent = ccf_clk_set_parent,	\
+		.of_xlate = k3_##name##_clk_of_xlate,	\
+}
+
+static const struct udevice_id k3_pll_clk_match[] = {
+	{ .compatible = "spacemit,k3-pll",
+	  .data = (ulong)&k3_ccu_pll_data },
+	{ /* sentinel */ },
+};
+
+K3_CLK_OPS(pll);
+
+U_BOOT_DRIVER(k3_pll_clk) = {
+	.name		= "k3_pll_clk",
+	.id		= UCLASS_CLK,
+	.of_match	= k3_pll_clk_match,
+	.probe		= k3_pll_clk_probe,
+	.ops		= &k3_pll_clk_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
+
+static const struct udevice_id k3_mpmu_clk_match[] = {
+	{ .compatible = "spacemit,k3-syscon-mpmu",
+	  .data = (ulong)&k3_ccu_mpmu_data },
+	{ /* sentinel */ },
+};
+
+K3_CLK_OPS(mpmu);
+
+U_BOOT_DRIVER(k3_mpmu_clk) = {
+	.name		= "k3_mpmu_clk",
+	.id		= UCLASS_CLK,
+	.of_match	= k3_mpmu_clk_match,
+	.probe		= k3_mpmu_clk_probe,
+	.ops		= &k3_mpmu_clk_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
+
+static const struct udevice_id k3_apbc_clk_match[] = {
+	{ .compatible = "spacemit,k3-syscon-apbc",
+	  .data = (ulong)&k3_ccu_apbc_data },
+	{ /* sentinel */ },
+};
+
+K3_CLK_OPS(apbc);
+
+U_BOOT_DRIVER(k3_apbc_clk) = {
+	.name		= "k3_apbc_clk",
+	.id		= UCLASS_CLK,
+	.of_match	= k3_apbc_clk_match,
+	.probe		= k3_apbc_clk_probe,
+	.ops		= &k3_apbc_clk_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
+
+static const struct udevice_id k3_apmu_clk_match[] = {
+	{ .compatible = "spacemit,k3-syscon-apmu",
+	  .data = (ulong)&k3_ccu_apmu_data },
+	{ /* sentinel */ },
+};
+
+K3_CLK_OPS(apmu);
+
+U_BOOT_DRIVER(k3_apmu_clk) = {
+	.name		= "k3_apmu_clk",
+	.id		= UCLASS_CLK,
+	.of_match	= k3_apmu_clk_match,
+	.probe		= k3_apmu_clk_probe,
+	.ops		= &k3_apmu_clk_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
+
+static const struct udevice_id k3_dciu_clk_match[] = {
+	{ .compatible = "spacemit,k3-syscon-dciu",
+	  .data = (ulong)&k3_ccu_dciu_data },
+	{ /* sentinel */ },
+};
+
+K3_CLK_OPS(dciu);
+
+U_BOOT_DRIVER(k3_dciu_clk) = {
+	.name		= "k3_dciu_clk",
+	.id		= UCLASS_CLK,
+	.of_match	= k3_dciu_clk_match,
+	.probe		= k3_dciu_clk_probe,
+	.ops		= &k3_dciu_clk_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/spacemit/clk_mix.h b/drivers/clk/spacemit/clk_mix.h
index 4ac61b55546..3ba9abe413b 100644
--- a/drivers/clk/spacemit/clk_mix.h
+++ b/drivers/clk/spacemit/clk_mix.h
@@ -180,6 +180,16 @@ static struct ccu_mix _var = {						\
 	},								\
 }
 
+#define CCU_MUX_DIV_GATE_FC_DEFINE(_id, _var, _name, _parents, _num_p,	\
+				   _reg_ctrl, _mshift, _mwidth,		\
+				   _mask_fc, _muxshift, _muxwidth,	\
+				   _mask_gate, _flags)			\
+	CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(_id, _var, _name, _parents,	\
+					 _num_p, _reg_ctrl, _reg_ctrl,	\
+					 _mshift, _mwidth, _mask_fc,	\
+					 _muxshift, _muxwidth,		\
+					 _mask_gate, _flags)
+
 #define CCU_MUX_DIV_FC_DEFINE(_id, _var, _name, _parents, _num_p,	\
 			      _reg_ctrl, _reg_fc, _mshift, _mwidth,	\
 			      _mask_fc,	_muxshift, _muxwidth, _flags)	\

-- 
2.55.0

[PATCH 6/8] clk: spacemit: k3: reduce clock tree for SPL build

[Yixun Lan]

Due to SPL image running in a memory space constraint SRAM environment,
so reduce the whole clock tree a bit to make it fit for final runtime
requirement, only a subset clock tree is registered, which includes UART,
SDHCI, I2C (TWSI), and their PLL/MPMU/APMU/APBC ancestors; while the
full clock tree is retained in non-SPL build.

Where surviving SPL CCU definitions reference parent clocks outside
that subset tree, it will use "clock-dummy" as name of clock parent to
ensure the framework still successfully resolves the parent clock lookup.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 drivers/clk/spacemit/clk-k3.c | 141 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 134 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/spacemit/clk-k3.c b/drivers/clk/spacemit/clk-k3.c
index 1ac64aec6ba..c4ac0b18442 100644
--- a/drivers/clk/spacemit/clk-k3.c
+++ b/drivers/clk/spacemit/clk-k3.c
@@ -41,6 +41,16 @@ static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = {
 	CCU_PLLA_RATE(2457600000UL, 0x0b330ccc, 0x0000cd00, 0xa0558989),
 };
 
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+CCU_PLLA_DEFINE(CLK_PLL1, pll1, pll1, "clock-24m", pll1_rate_tbl,
+		APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APBS_PLL1_SWCR3,
+		MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE);
+CCU_FACTOR_GATE_DEFINE(CLK_PLL1_D4, pll1_d4, pll1_d4, "pll1",
+		       APBS_PLL1_SWCR2, BIT(3), 4, 1);
+CCU_FACTOR_GATE_FLAGS_DEFINE(CLK_PLL1_D8, pll1_d8, pll1_d8, "pll1",
+			     APBS_PLL1_SWCR2, BIT(7), 8, 1,
+			     CLK_IS_CRITICAL);
+#else
 static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
 	CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c),
 };
@@ -244,9 +254,44 @@ CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D7, pll8_d7, pll8_d7, "pll8",
 		       APBS_PLL8_SWCR2, BIT(6), 7, 1);
 CCU_FACTOR_GATE_DEFINE(CLK_PLL8_D8, pll8_d8, pll8_d8, "pll8",
 		       APBS_PLL8_SWCR2, BIT(7), 8, 1);
+#endif
 /* APBS clocks end */
 
 /* MPMU clocks start */
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_153P6, pll1_d16_153p6,
+		  pll1_d16_153p6, "pll1_d8", 2, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_102P4, pll1_d24_102p4,
+		       pll1_d24_102p4, "pll1_d8", MPMU_ACGR,
+		       BIT(12), 3, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_51P2, pll1_d48_51p2,
+		       pll1_d48_51p2, "pll1_d8", MPMU_ACGR,
+		       BIT(7), 6, 1);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_57P6, pll1_m3d128_57p6,
+		       pll1_m3d128_57p6, "pll1_d8", MPMU_ACGR,
+		       BIT(8), 16, 3);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_25P6, pll1_d96_25p6,
+		       pll1_d96_25p6, "pll1_d8", MPMU_ACGR,
+		       BIT(4), 12, 1);
+CCU_GATE_DEFINE(CLK_MPMU_PLL1_614, pll1_d4_614p4, pll1_d4_614p4,
+		"pll1_d4", MPMU_ACGR, BIT(15), 0);
+CCU_FACTOR_GATE_DEFINE(CLK_MPMU_PLL1_31P5, pll1_d78_31p5,
+		       pll1_d78_31p5, "pll1_d4", MPMU_ACGR,
+		       BIT(6), 39, 2);
+
+static const char * const apb_parents[] = {
+	"pll1_d96_25p6", "pll1_d48_51p2", "pll1_d96_25p6",
+	"pll1_d24_102p4",
+};
+CCU_MUX_DEFINE(CLK_MPMU_APB, apb_clk, apb_clk, apb_parents,
+	       ARRAY_SIZE(apb_parents), MPMU_APBCSCR, 0, 2, 0);
+CCU_DDN_DEFINE(CLK_MPMU_SLOW_UART1, slow_uart1_14p74,
+	       slow_uart1_14p74, "pll1_d16_153p6", MPMU_SUCCR,
+	       CCU_DDN_MASK(16, 13), 16, CCU_DDN_MASK(0, 13), 0, 2, 0);
+CCU_DDN_DEFINE(CLK_MPMU_SLOW_UART2, slow_uart2_48, slow_uart2_48,
+	       "pll1_d4_614p4", MPMU_SUCCR_1, CCU_DDN_MASK(16, 13), 16,
+	       CCU_DDN_MASK(0, 13), 0, 2, 0);
+#else
 CCU_GATE_DEFINE(CLK_MPMU_PLL1_307P2, pll1_d8_307p2, pll1_d8_307p2, "pll1_d8",
 		MPMU_ACGR, BIT(13), 0);
 CCU_FACTOR_DEFINE(CLK_MPMU_PLL1_76P8, pll1_d32_76p8, pll1_d32_76p8, "pll1_d8_307p2", 4, 1);
@@ -383,12 +428,34 @@ CCU_GATE_DEFINE(CLK_MPMU_I2S4_SYSCLK, i2s4_sysclk, i2s4_sysclk, "i2s4_sysclk_div
 		MPMU_I2S_SYSCLK_CTRL, BIT(18), 0);
 CCU_GATE_DEFINE(CLK_MPMU_I2S5_SYSCLK, i2s5_sysclk, i2s5_sysclk, "i2s5_sysclk_div",
 		MPMU_I2S_SYSCLK_CTRL, BIT(22), 0);
+#endif
 /* MPMU clocks end */
 
 /* APBC clocks start */
 static const char * const uart_clk_parents[] = {
 	"pll1_m3d128_57p6", "slow_uart1_14p74", "slow_uart2_48",
 };
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+CCU_MUX_GATE_DEFINE(CLK_APBC_UART0, uart0_clk, uart0_clk,
+		    uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
+		    APBC_UART0_CLK_RST, 4, 3, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_UART0_BUS, uart0_bus_clk, uart0_bus_clk,
+		"apb_clk", APBC_UART0_CLK_RST, BIT(0), 0);
+CCU_GATE_DEFINE(CLK_APBC_AIB, aib_clk, aib_clk, "clock-24m",
+		APBC_AIB_CLK_RST, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_AIB_BUS, aib_bus_clk, aib_bus_clk, "apb_clk",
+		APBC_AIB_CLK_RST, BIT(0), 0);
+
+static const char * const twsi_parents[] = {
+	"pll1_d78_31p5",
+};
+
+CCU_MUX_GATE_DEFINE(CLK_APBC_TWSI2, twsi2_clk, twsi2_clk,
+		    twsi_parents, ARRAY_SIZE(twsi_parents),
+		    APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0);
+CCU_GATE_DEFINE(CLK_APBC_TWSI2_BUS, twsi2_bus_clk, twsi2_bus_clk,
+		"apb_clk", APBC_TWSI2_CLK_RST, BIT(0), 0);
+#else
 CCU_MUX_GATE_DEFINE(CLK_APBC_UART0, uart0_clk, uart0_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
 		    APBC_UART0_CLK_RST, 4, 3, BIT(1), 0);
 CCU_MUX_GATE_DEFINE(CLK_APBC_UART2, uart2_clk, uart2_clk, uart_clk_parents, ARRAY_SIZE(uart_clk_parents),
@@ -750,9 +817,19 @@ CCU_GATE_DEFINE(CLK_APBC_CAN3_BUS, can3_bus_clk, can3_bus_clk, "apb_clk",
 		APBC_CAN3_CLK_RST, BIT(0), 0);
 CCU_GATE_DEFINE(CLK_APBC_CAN4_BUS, can4_bus_clk, can4_bus_clk, "apb_clk",
 		APBC_CAN4_CLK_RST, BIT(0), 0);
+#endif
 /* APBC clocks end */
 
 /* APMU clocks start */
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+static const char * const axi_clk_parents[] = {
+	"pll1_d8_307p2", "pll1_d6_409p6",
+};
+CCU_MUX_DIV_FC_DEFINE(CLK_APMU_AXICLK, axi_clk, axi_clk,
+		      axi_clk_parents, ARRAY_SIZE(axi_clk_parents),
+		      APMU_ACLK_CLK_CTRL, APMU_ACLK_CLK_CTRL, 1, 2,
+		      BIT(4), 0, 1, 0);
+#else
 static const char * const axi_clk_parents[] = {
 	"pll1_d8_307p2", "pll1_d6_409p6",
 };
@@ -1029,13 +1106,13 @@ CCU_MUX_DIV_GATE_FC_DEFINE(CLK_APMU_UFS_ACLK, ufs_aclk, ufs_aclk, ufs_aclk_paren
 			   2, 3, BIT(1), 0);
 
 static const char * const edp0_pclk_parents[] = {
-	"lcd_pxclk", "external_clk",
+	"lcd_pxclk", "clock-dummy",
 };
 CCU_MUX_GATE_DEFINE(CLK_APMU_EDP0_PXCLK, edp0_pxclk, edp0_pxclk, edp0_pclk_parents, ARRAY_SIZE(edp0_pclk_parents),
 		    APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0);
 
 static const char * const edp1_pclk_parents[] = {
-	"dsi4ln2_lcd_pxclk", "external_clk",
+	"dsi4ln2_lcd_pxclk", "clock-dummy",
 };
 CCU_MUX_GATE_DEFINE(CLK_APMU_EDP1_PXCLK, edp1_pxclk, edp1_pxclk, edp1_pclk_parents, ARRAY_SIZE(edp1_pclk_parents),
 		    APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0);
@@ -1096,7 +1173,7 @@ CCU_MUX_DEFINE(CLK_APMU_ESPI_SCLK_SRC, espi_sclk_src, espi_sclk_src, espi_sclk_s
 		APMU_ESPI_CLK_RES_CTRL, 4, 3, 0);
 
 static const char * const espi_sclk_parents[] = {
-	"external_clk", "espi_sclk_src",
+	"clock-dummy", "espi_sclk_src",
 };
 CCU_MUX_GATE_DEFINE(CLK_APMU_ESPI_SCLK, espi_sclk, espi_sclk, espi_sclk_parents, ARRAY_SIZE(espi_sclk_parents),
 		    APMU_ESPI_CLK_RES_CTRL, 7, 1, BIT(3), 0);
@@ -1124,6 +1201,7 @@ CCU_MUX_DIV_GATE_DEFINE(CLK_APMU_ISIM_VCLK2, isim_vclk_out2, isim_vclk_out2, isi
 CCU_MUX_DIV_GATE_DEFINE(CLK_APMU_ISIM_VCLK3, isim_vclk_out3, isim_vclk_out3, isim_vclk_parents, ARRAY_SIZE(isim_vclk_parents),
 			APMU_SNR_ISIM_VCLK_CTRL, 27, 4, 25, 2,
 			BIT(24), 0);
+#endif
 /* APMU clocks end */
 
 /* DCIU clocks start */
@@ -1148,6 +1226,13 @@ CCU_GATE_DEFINE(CLK_DCIU_C3_TCM_PIPE, c3_tcm_pipe_clk, c3_tcm_pipe_clk, "axi_clk
 
 
 
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+static struct clk *k3_ccu_pll_clks[] = {
+	&pll1.common.clk,
+	&pll1_d4.common.clk,
+	&pll1_d8.common.clk,
+};
+#else
 static struct clk *k3_ccu_pll_clks[] = {
 	&pll1.common.clk,
 	&pll2.common.clk,
@@ -1235,6 +1320,7 @@ static struct clk *k3_ccu_pll_clks[] = {
 	&pll8_d7.common.clk,
 	&pll8_d8.common.clk,
 };
+#endif
 
 static const struct spacemit_ccu_data k3_ccu_pll_data = {
 	.clks		= k3_ccu_pll_clks,
@@ -1242,6 +1328,20 @@ static const struct spacemit_ccu_data k3_ccu_pll_data = {
 	.offset		= K3_PLL_ID,
 };
 
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+static struct clk *k3_ccu_mpmu_clks[] = {
+	&pll1_d16_153p6.common.clk,
+	&pll1_d24_102p4.common.clk,
+	&pll1_d48_51p2.common.clk,
+	&pll1_m3d128_57p6.common.clk,
+	&pll1_d96_25p6.common.clk,
+	&pll1_d4_614p4.common.clk,
+	&pll1_d78_31p5.common.clk,
+	&apb_clk.common.clk,
+	&slow_uart1_14p74.common.clk,
+	&slow_uart2_48.common.clk,
+};
+#else
 static struct clk *k3_ccu_mpmu_clks[] = {
 	&pll1_d8_307p2.common.clk,
 	&pll1_d32_76p8.common.clk,
@@ -1295,6 +1395,7 @@ static struct clk *k3_ccu_mpmu_clks[] = {
 	&i2s4_sysclk.common.clk,
 	&i2s5_sysclk.common.clk,
 };
+#endif
 
 static const struct spacemit_ccu_data k3_ccu_mpmu_data = {
 	.clks		= k3_ccu_mpmu_clks,
@@ -1302,6 +1403,16 @@ static const struct spacemit_ccu_data k3_ccu_mpmu_data = {
 	.offset		= K3_MPMU_ID,
 };
 
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+static struct clk *k3_ccu_apbc_clks[] = {
+	&uart0_clk.common.clk,
+	&uart0_bus_clk.common.clk,
+	&aib_clk.common.clk,
+	&aib_bus_clk.common.clk,
+	&twsi2_clk.common.clk,
+	&twsi2_bus_clk.common.clk,
+};
+#else
 static struct clk *k3_ccu_apbc_clks[] = {
 	&uart0_clk.common.clk,
 	&uart2_clk.common.clk,
@@ -1446,6 +1557,7 @@ static struct clk *k3_ccu_apbc_clks[] = {
 	&can3_bus_clk.common.clk,
 	&can4_bus_clk.common.clk,
 };
+#endif
 
 static const struct spacemit_ccu_data k3_ccu_apbc_data = {
 	.clks		= k3_ccu_apbc_clks,
@@ -1453,6 +1565,11 @@ static const struct spacemit_ccu_data k3_ccu_apbc_data = {
 	.offset		= K3_APBC_ID,
 };
 
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+static struct clk *k3_ccu_apmu_clks[] = {
+	&axi_clk.common.clk,
+};
+#else
 static struct clk *k3_ccu_apmu_clks[] = {
 	&axi_clk.common.clk,
 	&cci550_clk.common.clk,
@@ -1544,6 +1661,7 @@ static struct clk *k3_ccu_apmu_clks[] = {
 	&isim_vclk_out2.common.clk,
 	&isim_vclk_out3.common.clk,
 };
+#endif
 
 static const struct spacemit_ccu_data k3_ccu_apmu_data = {
 	.clks		= k3_ccu_apmu_clks,
@@ -1557,12 +1675,14 @@ static const struct spacemit_ccu_data k3_ccu_apmu_data = {
  * Enable them explicitly here, otherwise Linux gets stuck
  * halfway through boot.
  */
+#if !IS_ENABLED(CONFIG_SPL_BUILD)
 static struct clk *const k3_apmu_boot_clks[] = {
 	&cpu_c0_core_clk.common.clk,
 	&cpu_c1_core_clk.common.clk,
 	&cpu_c2_core_clk.common.clk,
 	&cpu_c3_core_clk.common.clk,
 };
+#endif
 
 static struct clk *k3_ccu_dciu_clks[] = {
 	&hdma_clk.common.clk,
@@ -1675,7 +1795,10 @@ static int k3_apmu_clk_probe(struct udevice *dev)
 {
 	struct regmap *base_regmap;
 	const struct spacemit_ccu_data *data;
-	int i, ret;
+#if !IS_ENABLED(CONFIG_SPL_BUILD)
+	int i;
+#endif
+	int ret;
 
 	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_pll_clk));
 	if (ret)
@@ -1694,11 +1817,13 @@ static int k3_apmu_clk_probe(struct udevice *dev)
 	if (ret)
 		return -EPROBE_DEFER;
 
+#if !IS_ENABLED(CONFIG_SPL_BUILD)
 	for (i = 0; i < ARRAY_SIZE(k3_apmu_boot_clks); i++) {
 		ret = clk_enable(k3_apmu_boot_clks[i]);
 		if (ret)
 			return ret;
 	}
+#endif
 
 	return 0;
 }
@@ -1715,9 +1840,11 @@ static int k3_apbc_clk_probe(struct udevice *dev)
 	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_mpmu_clk));
 	if (ret)
 		return ret;
-	ret = k3_clk_force_probe(DM_DRIVER_GET(k3_apmu_clk));
-	if (ret)
-		return ret;
+	if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+		ret = k3_clk_force_probe(DM_DRIVER_GET(k3_apmu_clk));
+		if (ret)
+			return ret;
+	}
 
 	ret = regmap_init_mem(dev_ofnode(dev), &base_regmap);
 	if (ret)

-- 
2.55.0

Re: [PATCH 6/8] clk: spacemit: k3: reduce clock tree for SPL build

[Tim Ouyang]

On Tue, Aug 25, 2026 at 04:24:16AM +0000, Yixun Lan wrote:
> Due to SPL image running in a memory space constraint SRAM environment,
> so reduce the whole clock tree a bit to make it fit for final runtime
> requirement, only a subset clock tree is registered, which includes UART,
> SDHCI, I2C (TWSI), and their PLL/MPMU/APMU/APBC ancestors; while the
> full clock tree is retained in non-SPL build.
>
> Where surviving SPL CCU definitions reference parent clocks outside
> that subset tree, it will use "clock-dummy" as name of clock parent to
> ensure the framework still successfully resolves the parent clock lookup.
>
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---

[...]

>  /* APMU clocks start */
> +#if IS_ENABLED(CONFIG_SPL_BUILD)
> +static const char * const axi_clk_parents[] = {
> +       "pll1_d8_307p2", "pll1_d6_409p6",
> +};
> +CCU_MUX_DIV_FC_DEFINE(CLK_APMU_AXICLK, axi_clk, axi_clk,
> +                     axi_clk_parents, ARRAY_SIZE(axi_clk_parents),
> +                     APMU_ACLK_CLK_CTRL, APMU_ACLK_CLK_CTRL, 1, 2,
> +                     BIT(4), 0, 1, 0);
> +#else
>  static const char * const axi_clk_parents[] = {
>         "pll1_d8_307p2", "pll1_d6_409p6",
>  };

The SPL clock subset does not seem to include all the clocks described
in the commit message. For example, the SDH0/1/2 clocks are excluded
from the SPL build.

Is this intentional?
--
Best regards,
Tim Ouyang

Re: [PATCH 6/8] clk: spacemit: k3: reduce clock tree for SPL build

[Yixun Lan]

Hi Tim,

On 17:55 Wed 02 Sep     , Tim Ouyang wrote:
> On Tue, Aug 25, 2026 at 04:24:16AM +0000, Yixun Lan wrote:
> > Due to SPL image running in a memory space constraint SRAM environment,
> > so reduce the whole clock tree a bit to make it fit for final runtime
> > requirement, only a subset clock tree is registered, which includes UART,
> > SDHCI, I2C (TWSI), and their PLL/MPMU/APMU/APBC ancestors; while the
> > full clock tree is retained in non-SPL build.
> >
> > Where surviving SPL CCU definitions reference parent clocks outside
> > that subset tree, it will use "clock-dummy" as name of clock parent to
> > ensure the framework still successfully resolves the parent clock lookup.
> >
> > Signed-off-by: Yixun Lan <dlan@kernel.org>
> > ---
> 
> [...]
> 
> >  /* APMU clocks start */
> > +#if IS_ENABLED(CONFIG_SPL_BUILD)
> > +static const char * const axi_clk_parents[] = {
> > +       "pll1_d8_307p2", "pll1_d6_409p6",
> > +};
> > +CCU_MUX_DIV_FC_DEFINE(CLK_APMU_AXICLK, axi_clk, axi_clk,
> > +                     axi_clk_parents, ARRAY_SIZE(axi_clk_parents),
> > +                     APMU_ACLK_CLK_CTRL, APMU_ACLK_CLK_CTRL, 1, 2,
> > +                     BIT(4), 0, 1, 0);
> > +#else
> >  static const char * const axi_clk_parents[] = {
> >         "pll1_d8_307p2", "pll1_d6_409p6",
> >  };
> 
> The SPL clock subset does not seem to include all the clocks described
> in the commit message. For example, the SDH0/1/2 clocks are excluded
> from the SPL build.
> 
> Is this intentional?

You right, but I will update the commit message instead of changing the code.

The lastest dts in u-boot next branch just synced with upstream kernel v7.2
 which doesn't include SDHCI support (need to wait for v7.3), also the SDHCI
for SPL support still needs some testing, so I will postpone it in later patches

-- 
Yixun Lan (dlan)

[PATCH 7/8] reset: spacemit: Extract common K1 reset code

[Yixun Lan]

Based on upstream Linux:
  aba86f7bff0b ("reset: spacemit: Extract common K1 reset code")

Extract the common reset controller code from the K1 driver into
separate reset-spacemit-common.{c,h} files to prepare for additional
SpacemiT SoCs that share the same reset controller architecture.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 drivers/clk/spacemit/Kconfig                   |   1 +
 drivers/reset/Kconfig                          |   1 +
 drivers/reset/Makefile                         |   2 +-
 drivers/reset/spacemit/Kconfig                 |  15 +++
 drivers/reset/spacemit/Makefile                |   3 +-
 drivers/reset/spacemit/reset-spacemit-common.c |  93 ++++++++++++++++++
 drivers/reset/spacemit/reset-spacemit-common.h |  40 ++++++++
 drivers/reset/spacemit/reset-spacemit-k1.c     | 128 ++-----------------------
 8 files changed, 163 insertions(+), 120 deletions(-)

diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig
index b22f65f2547..c305f433871 100644
--- a/drivers/clk/spacemit/Kconfig
+++ b/drivers/clk/spacemit/Kconfig
@@ -16,6 +16,7 @@ if CLK_SPACEMIT
 config CLK_SPACEMIT_K1
 	bool "SpacemiT K1 clock support"
 	select CLK_CCF
+	select RESET_SPACEMIT_K1
 	help
 	  This enables support clock driver for Spacemit K1 SoC.
 	  It's based on Common Clock Framework.
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index db764ed5ace..ad61ebf344a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -280,4 +280,5 @@ config RESET_RZG2L_USBPHY_CTRL
 	  SoC.
 
 source "drivers/reset/stm32/Kconfig"
+source "drivers/reset/spacemit/Kconfig"
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 384f4336331..959aafe4d70 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -37,7 +37,7 @@ obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
 obj-$(CONFIG_RESET_AT91) += reset-at91.o
 obj-$(CONFIG_$(PHASE_)RESET_JH7110) += reset-jh7110.o
 obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
-obj-$(CONFIG_CLK_SPACEMIT_K1) += spacemit/
+obj-$(CONFIG_RESET_SPACEMIT_COMMON) += spacemit/
 
 obj-$(CONFIG_ARCH_STM32) += stm32/
 obj-$(CONFIG_ARCH_STM32MP) += stm32/
diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig
new file mode 100644
index 00000000000..20e4cc6e4d8
--- /dev/null
+++ b/drivers/reset/spacemit/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config RESET_SPACEMIT_COMMON
+	bool
+	select DM_RESET
+	help
+	  Common reset controller infrastructure for SpacemiT SoCs.
+	  Shared by the K1 and K3 reset drivers.
+
+config RESET_SPACEMIT_K1
+	bool "SpacemiT K1 reset support"
+	select RESET_SPACEMIT_COMMON
+	help
+	  Reset controller for SpacemiT K1 (MPMU/APBC/APMU/APBC2).
+	  Bound from the K1 CCU/syscon devices.
diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile
index 16722c68954..56f9fd1ab20 100644
--- a/drivers/reset/spacemit/Makefile
+++ b/drivers/reset/spacemit/Makefile
@@ -2,4 +2,5 @@
 #
 # SpacemiT reset drivers
 
-obj-y += reset-spacemit-k1.o
+obj-$(CONFIG_RESET_SPACEMIT_COMMON)	+= reset-spacemit-common.o
+obj-$(CONFIG_RESET_SPACEMIT_K1)		+= reset-spacemit-k1.o
diff --git a/drivers/reset/spacemit/reset-spacemit-common.c b/drivers/reset/spacemit/reset-spacemit-common.c
new file mode 100644
index 00000000000..34ed0862b9c
--- /dev/null
+++ b/drivers/reset/spacemit/reset-spacemit-common.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SpacemiT reset controller — common implementation (U-Boot)
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+
+#include "reset-spacemit-common.h"
+
+static int spacemit_reset_xfer(struct reset_ctl *rst, bool assert)
+{
+	struct spacemit_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct spacemit_reset_data *e;
+	u32 v;
+
+	if (rst->id >= priv->table_size)
+		return -EINVAL;
+
+	e = &priv->table[rst->id];
+	if (e->assert_mask == 0 && e->deassert_mask == 0)
+		return -EINVAL;
+
+	v = readl(priv->base + e->offset);
+	v &= ~(e->assert_mask | e->deassert_mask);
+	v |= assert ? e->assert_mask : e->deassert_mask;
+	writel(v, priv->base + e->offset);
+
+	return 0;
+}
+
+static int spacemit_reset_assert(struct reset_ctl *rst)
+{
+	return spacemit_reset_xfer(rst, true);
+}
+
+static int spacemit_reset_deassert(struct reset_ctl *rst)
+{
+	return spacemit_reset_xfer(rst, false);
+}
+
+static int spacemit_reset_request(struct reset_ctl *rst)
+{
+	struct spacemit_reset_priv *priv = dev_get_priv(rst->dev);
+
+	return rst->id < priv->table_size ? 0 : -EINVAL;
+}
+
+const struct reset_ops spacemit_reset_ops = {
+	.request	= spacemit_reset_request,
+	.rst_assert	= spacemit_reset_assert,
+	.rst_deassert	= spacemit_reset_deassert,
+};
+
+int spacemit_reset_probe(struct udevice *dev)
+{
+	struct spacemit_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = (void __iomem *)dev_remap_addr(dev);
+	if (!priv->base)
+		return -ENODEV;
+
+	return 0;
+}
+
+int spacemit_reset_bind(struct udevice *parent, const char *drv_name,
+			const struct spacemit_reset_data *table,
+			size_t table_size)
+{
+	struct spacemit_reset_priv *priv;
+	struct udevice *rst_dev;
+	int ret;
+
+	ret = device_bind_driver_to_node(parent, drv_name, "reset",
+					 dev_ofnode(parent), &rst_dev);
+	if (ret)
+		return ret;
+
+	priv = malloc(sizeof(*priv));
+	if (!priv) {
+		device_unbind(rst_dev);
+		return -ENOMEM;
+	}
+	priv->table = table;
+	priv->table_size = table_size;
+	dev_set_priv(rst_dev, priv);
+
+	return 0;
+}
diff --git a/drivers/reset/spacemit/reset-spacemit-common.h b/drivers/reset/spacemit/reset-spacemit-common.h
new file mode 100644
index 00000000000..cde52b3fc1d
--- /dev/null
+++ b/drivers/reset/spacemit/reset-spacemit-common.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * SpacemiT reset controller — common definitions (U-Boot)
+ */
+
+#ifndef _RESET_SPACEMIT_COMMON_H_
+#define _RESET_SPACEMIT_COMMON_H_
+
+#include <linux/types.h>
+
+struct udevice;
+struct reset_ops;
+
+struct spacemit_reset_data {
+	u32 offset;
+	u32 assert_mask;
+	u32 deassert_mask;
+};
+
+struct spacemit_reset_priv {
+	void *base;
+	const struct spacemit_reset_data *table;
+	size_t table_size;
+};
+
+#define RESET_DATA(_offset, _assert_mask, _deassert_mask)	\
+	{							\
+		.offset		= (_offset),			\
+		.assert_mask	= (_assert_mask),		\
+		.deassert_mask	= (_deassert_mask),		\
+	}
+
+extern const struct reset_ops spacemit_reset_ops;
+
+int spacemit_reset_probe(struct udevice *dev);
+int spacemit_reset_bind(struct udevice *parent, const char *drv_name,
+			const struct spacemit_reset_data *table,
+			size_t table_size);
+
+#endif /* _RESET_SPACEMIT_COMMON_H_ */
diff --git a/drivers/reset/spacemit/reset-spacemit-k1.c b/drivers/reset/spacemit/reset-spacemit-k1.c
index 129e1cc96f1..75000ff64e0 100644
--- a/drivers/reset/spacemit/reset-spacemit-k1.c
+++ b/drivers/reset/spacemit/reset-spacemit-k1.c
@@ -7,46 +7,19 @@
  * Copyright (C) 2026 RISCstar Ltd.
  */
 
-#include <asm/io.h>
 #include <dm.h>
-#include <dm/device-internal.h>
-#include <dm/lists.h>
 #include <dt-bindings/clock/spacemit,k1-syscon.h>
 #include <linux/bitops.h>
-#include <malloc.h>
-#include <reset-uclass.h>
 #include <soc/spacemit/k1-reset.h>
 #include <soc/spacemit/k1-syscon.h>
 
-/* ===================================================================
- * Per-syscon reset signal tables.
- *
- * Indexed by the kernel-side per-syscon-local IDs from
- * <dt-bindings/clock/spacemit,k1-syscon.h>. Each entry is
- * (offset, assert_mask, deassert_mask): bits in assert_mask are set
- * when the reset line is asserted; bits in deassert_mask are set when
- * deasserted; the union (assert_mask | deassert_mask) is the set of
- * bits the controller will overwrite on each transition.
- *
- * Layout mirrors the kernel-side K1 reset driver.
- * ===================================================================
- */
-
-struct spacemit_k1_reset_data {
-	u32 offset;
-	u32 assert_mask;
-	u32 deassert_mask;
-};
+#include "reset-spacemit-common.h"
 
-#define RESET_DATA(o, a, d) {					\
-	.offset = (o), .assert_mask = (a), .deassert_mask = (d)	\
-}
-
-static const struct spacemit_k1_reset_data k1_mpmu_resets[] = {
+static const struct spacemit_reset_data k1_mpmu_resets[] = {
 	[RESET_WDT]	= RESET_DATA(MPMU_WDTPCR,		BIT(2), 0),
 };
 
-static const struct spacemit_k1_reset_data k1_apbc_resets[] = {
+static const struct spacemit_reset_data k1_apbc_resets[] = {
 	[RESET_UART0]	= RESET_DATA(APBC_UART1_CLK_RST,	BIT(2), 0),
 	[RESET_UART2]	= RESET_DATA(APBC_UART2_CLK_RST,	BIT(2), 0),
 	[RESET_UART3]	= RESET_DATA(APBC_UART3_CLK_RST,	BIT(2), 0),
@@ -100,7 +73,7 @@ static const struct spacemit_k1_reset_data k1_apbc_resets[] = {
 	[RESET_CAN0]	= RESET_DATA(APBC_CAN0_CLK_RST,		BIT(2), 0),
 };
 
-static const struct spacemit_k1_reset_data k1_apmu_resets[] = {
+static const struct spacemit_reset_data k1_apmu_resets[] = {
 	[RESET_CCIC_4X]		= RESET_DATA(APMU_CCIC_CLK_RES_CTRL,	0, BIT(1)),
 	[RESET_CCIC1_PHY]	= RESET_DATA(APMU_CCIC_CLK_RES_CTRL,	0, BIT(2)),
 	[RESET_SDH_AXI]		= RESET_DATA(APMU_SDH0_CLK_RES_CTRL,	0, BIT(0)),
@@ -156,7 +129,7 @@ static const struct spacemit_k1_reset_data k1_apmu_resets[] = {
 	[RESET_MC]		= RESET_DATA(APMU_PMUA_MC_CTRL,		0, BIT(0)),
 };
 
-static const struct spacemit_k1_reset_data k1_apbc2_resets[] = {
+static const struct spacemit_reset_data k1_apbc2_resets[] = {
 	[RESET_APBC2_UART1]	= RESET_DATA(APBC2_UART1_CLK_RST,	BIT(2), 0),
 	[RESET_APBC2_SSP2]	= RESET_DATA(APBC2_SSP2_CLK_RST,	BIT(2), 0),
 	[RESET_APBC2_TWSI3]	= RESET_DATA(APBC2_TWSI3_CLK_RST,	BIT(2), 0),
@@ -166,89 +139,22 @@ static const struct spacemit_k1_reset_data k1_apbc2_resets[] = {
 	[RESET_APBC2_GPIO]	= RESET_DATA(APBC2_GPIO_CLK_RST,	BIT(2), 0),
 };
 
-/* ===================================================================
- * Driver
- * ===================================================================
- */
-
-struct spacemit_k1_reset_priv {
-	void __iomem *base;
-	const struct spacemit_k1_reset_data *table;
-	size_t table_size;
-};
-
-static int spacemit_k1_reset_xfer(struct reset_ctl *rst, bool assert)
-{
-	struct spacemit_k1_reset_priv *priv = dev_get_priv(rst->dev);
-	const struct spacemit_k1_reset_data *e;
-	u32 v;
-
-	if (rst->id >= priv->table_size)
-		return -EINVAL;
-
-	e = &priv->table[rst->id];
-	if (e->assert_mask == 0 && e->deassert_mask == 0)
-		return -EINVAL;	/* not owned by this syscon */
-
-	v = readl(priv->base + e->offset);
-	v &= ~(e->assert_mask | e->deassert_mask);
-	v |= assert ? e->assert_mask : e->deassert_mask;
-	writel(v, priv->base + e->offset);
-
-	return 0;
-}
-
-static int spacemit_k1_reset_assert(struct reset_ctl *rst)
-{
-	return spacemit_k1_reset_xfer(rst, true);
-}
-
-static int spacemit_k1_reset_deassert(struct reset_ctl *rst)
-{
-	return spacemit_k1_reset_xfer(rst, false);
-}
-
-static int spacemit_k1_reset_request(struct reset_ctl *rst)
-{
-	struct spacemit_k1_reset_priv *priv = dev_get_priv(rst->dev);
-
-	return rst->id < priv->table_size ? 0 : -EINVAL;
-}
-
-static const struct reset_ops spacemit_k1_reset_ops = {
-	.request	= spacemit_k1_reset_request,
-	.rst_assert	= spacemit_k1_reset_assert,
-	.rst_deassert	= spacemit_k1_reset_deassert,
-};
-
-static int spacemit_k1_reset_probe(struct udevice *dev)
-{
-	struct spacemit_k1_reset_priv *priv = dev_get_priv(dev);
 
-	priv->base = (void __iomem *)dev_remap_addr(dev);
-	if (!priv->base)
-		return -ENODEV;
-
-	return 0;
-}
 
 U_BOOT_DRIVER(spacemit_k1_reset) = {
 	.name		= "spacemit_k1_reset",
 	.id		= UCLASS_RESET,
-	.ops		= &spacemit_k1_reset_ops,
-	.probe		= spacemit_k1_reset_probe,
-	.priv_auto	= sizeof(struct spacemit_k1_reset_priv),
+	.ops		= &spacemit_reset_ops,
+	.probe		= spacemit_reset_probe,
+	.priv_auto	= sizeof(struct spacemit_reset_priv),
 	.flags		= DM_FLAG_PRE_RELOC,
 };
 
 int spacemit_k1_reset_bind(struct udevice *parent,
 			   enum spacemit_k1_reset_syscon syscon)
 {
-	struct spacemit_k1_reset_priv *priv;
-	struct udevice *rst_dev;
-	const struct spacemit_k1_reset_data *table;
+	const struct spacemit_reset_data *table;
 	size_t table_size;
-	int ret;
 
 	switch (syscon) {
 	case SPACEMIT_K1_RESET_MPMU:
@@ -271,19 +177,5 @@ int spacemit_k1_reset_bind(struct udevice *parent,
 		return -EINVAL;
 	}
 
-	ret = device_bind_driver_to_node(parent, "spacemit_k1_reset", "reset",
-					 dev_ofnode(parent), &rst_dev);
-	if (ret)
-		return ret;
-
-	priv = malloc(sizeof(*priv));
-	if (!priv) {
-		device_unbind(rst_dev);
-		return -ENOMEM;
-	}
-	priv->table = table;
-	priv->table_size = table_size;
-	dev_set_priv(rst_dev, priv);
-
-	return 0;
+	return spacemit_reset_bind(parent, "spacemit_k1_reset", table, table_size);
 }

-- 
2.55.0

[PATCH 8/8] reset: spacemit: Add SpacemiT K3 reset driver

[Yixun Lan]

Based on upstream Linux:
  938ce3b16582 ("reset: spacemit: Add SpacemiT K3 reset driver")

Add support for the SpacemiT K3 SoC reset controller. The K3 reset
driver reuses the common reset controller code and provides K3-specific
reset data for devices managed by the following units:

- MPMU (Main Power Management Unit)
- APBC (APB clock unit)
- APMU (Application Subsystem Power Management Unit)
- DCIU (DMA Control and Interface Unit)

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 drivers/clk/spacemit/Kconfig               |   1 +
 drivers/clk/spacemit/clk-k3.c              |  25 +++
 drivers/reset/spacemit/Kconfig             |   7 +
 drivers/reset/spacemit/Makefile            |   1 +
 drivers/reset/spacemit/reset-spacemit-k3.c | 244 +++++++++++++++++++++++++++++
 include/soc/spacemit/k3-reset.h            |  21 +++
 6 files changed, 299 insertions(+)

diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig
index c305f433871..a782426fe0f 100644
--- a/drivers/clk/spacemit/Kconfig
+++ b/drivers/clk/spacemit/Kconfig
@@ -24,6 +24,7 @@ config CLK_SPACEMIT_K1
 config CLK_SPACEMIT_K3
 	bool "SpacemiT K3 clock support"
 	select CLK_CCF
+	select RESET_SPACEMIT_K3
 	help
 	  This enables support clock driver for Spacemit K3 SoC.
 	  It's based on Common Clock Framework.
diff --git a/drivers/clk/spacemit/clk-k3.c b/drivers/clk/spacemit/clk-k3.c
index c4ac0b18442..519f2122c74 100644
--- a/drivers/clk/spacemit/clk-k3.c
+++ b/drivers/clk/spacemit/clk-k3.c
@@ -9,6 +9,7 @@
 #include <dm/device_compat.h>
 #include <regmap.h>
 #include <linux/clk-provider.h>
+#include <soc/spacemit/k3-reset.h>
 #include <soc/spacemit/k3-syscon.h>
 
 #include "clk_common.h"
@@ -1990,6 +1991,26 @@ U_BOOT_DRIVER(k3_pll_clk) = {
 	.flags		= DM_FLAG_PRE_RELOC,
 };
 
+static int k3_mpmu_clk_bind(struct udevice *dev)
+{
+	return spacemit_k3_reset_bind(dev, SPACEMIT_K3_RESET_MPMU);
+}
+
+static int k3_apbc_clk_bind(struct udevice *dev)
+{
+	return spacemit_k3_reset_bind(dev, SPACEMIT_K3_RESET_APBC);
+}
+
+static int k3_apmu_clk_bind(struct udevice *dev)
+{
+	return spacemit_k3_reset_bind(dev, SPACEMIT_K3_RESET_APMU);
+}
+
+static int k3_dciu_clk_bind(struct udevice *dev)
+{
+	return spacemit_k3_reset_bind(dev, SPACEMIT_K3_RESET_DCIU);
+}
+
 static const struct udevice_id k3_mpmu_clk_match[] = {
 	{ .compatible = "spacemit,k3-syscon-mpmu",
 	  .data = (ulong)&k3_ccu_mpmu_data },
@@ -2002,6 +2023,7 @@ U_BOOT_DRIVER(k3_mpmu_clk) = {
 	.name		= "k3_mpmu_clk",
 	.id		= UCLASS_CLK,
 	.of_match	= k3_mpmu_clk_match,
+	.bind		= k3_mpmu_clk_bind,
 	.probe		= k3_mpmu_clk_probe,
 	.ops		= &k3_mpmu_clk_ops,
 	.flags		= DM_FLAG_PRE_RELOC,
@@ -2019,6 +2041,7 @@ U_BOOT_DRIVER(k3_apbc_clk) = {
 	.name		= "k3_apbc_clk",
 	.id		= UCLASS_CLK,
 	.of_match	= k3_apbc_clk_match,
+	.bind		= k3_apbc_clk_bind,
 	.probe		= k3_apbc_clk_probe,
 	.ops		= &k3_apbc_clk_ops,
 	.flags		= DM_FLAG_PRE_RELOC,
@@ -2036,6 +2059,7 @@ U_BOOT_DRIVER(k3_apmu_clk) = {
 	.name		= "k3_apmu_clk",
 	.id		= UCLASS_CLK,
 	.of_match	= k3_apmu_clk_match,
+	.bind		= k3_apmu_clk_bind,
 	.probe		= k3_apmu_clk_probe,
 	.ops		= &k3_apmu_clk_ops,
 	.flags		= DM_FLAG_PRE_RELOC,
@@ -2053,6 +2077,7 @@ U_BOOT_DRIVER(k3_dciu_clk) = {
 	.name		= "k3_dciu_clk",
 	.id		= UCLASS_CLK,
 	.of_match	= k3_dciu_clk_match,
+	.bind		= k3_dciu_clk_bind,
 	.probe		= k3_dciu_clk_probe,
 	.ops		= &k3_dciu_clk_ops,
 	.flags		= DM_FLAG_PRE_RELOC,
diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig
index 20e4cc6e4d8..66ab5f85333 100644
--- a/drivers/reset/spacemit/Kconfig
+++ b/drivers/reset/spacemit/Kconfig
@@ -13,3 +13,10 @@ config RESET_SPACEMIT_K1
 	help
 	  Reset controller for SpacemiT K1 (MPMU/APBC/APMU/APBC2).
 	  Bound from the K1 CCU/syscon devices.
+
+config RESET_SPACEMIT_K3
+	bool "SpacemiT K3 reset support"
+	select RESET_SPACEMIT_COMMON
+	help
+	  Reset controller for SpacemiT K3 (MPMU/APBC/APMU/DCIU).
+	  Bound from the K3 CCU/syscon devices.
diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile
index 56f9fd1ab20..f89d068e1ca 100644
--- a/drivers/reset/spacemit/Makefile
+++ b/drivers/reset/spacemit/Makefile
@@ -4,3 +4,4 @@
 
 obj-$(CONFIG_RESET_SPACEMIT_COMMON)	+= reset-spacemit-common.o
 obj-$(CONFIG_RESET_SPACEMIT_K1)		+= reset-spacemit-k1.o
+obj-$(CONFIG_RESET_SPACEMIT_K3)		+= reset-spacemit-k3.o
diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c
new file mode 100644
index 00000000000..63e4bf66d1d
--- /dev/null
+++ b/drivers/reset/spacemit/reset-spacemit-k3.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SpacemiT K3 reset driver (syscon-bound).
+ *
+ * Port of Linux drivers/reset/spacemit/reset-spacemit-k3.c
+ *
+ * Copyright (C) 2025 SpacemiT Technology Co. Ltd
+ */
+
+#include <dm.h>
+#include <dt-bindings/reset/spacemit,k3-resets.h>
+#include <linux/bitops.h>
+#include <soc/spacemit/k3-reset.h>
+#include <soc/spacemit/k3-syscon.h>
+
+#include "reset-spacemit-common.h"
+
+static const struct spacemit_reset_data k3_mpmu_resets[] = {
+	[RESET_MPMU_WDT]	= RESET_DATA(MPMU_WDTPCR,	BIT(2), 0),
+	[RESET_MPMU_RIPC]	= RESET_DATA(MPMU_RIPCCR,	BIT(2), 0),
+};
+
+static const struct spacemit_reset_data k3_apbc_resets[] = {
+	[RESET_APBC_UART0]	= RESET_DATA(APBC_UART0_CLK_RST,	BIT(2),	0),
+	[RESET_APBC_UART2]	= RESET_DATA(APBC_UART2_CLK_RST,	BIT(2),	0),
+	[RESET_APBC_UART3]	= RESET_DATA(APBC_UART3_CLK_RST,	BIT(2),	0),
+	[RESET_APBC_UART4]	= RESET_DATA(APBC_UART4_CLK_RST,	BIT(2),	0),
+	[RESET_APBC_UART5]	= RESET_DATA(APBC_UART5_CLK_RST,	BIT(2),	0),
+	[RESET_APBC_UART6]	= RESET_DATA(APBC_UART6_CLK_RST,	BIT(2),	0),
+	[RESET_APBC_UART7]	= RESET_DATA(APBC_UART7_CLK_RST,	BIT(2),	0),
+	[RESET_APBC_UART8]	= RESET_DATA(APBC_UART8_CLK_RST,	BIT(2),	0),
+	[RESET_APBC_UART9]	= RESET_DATA(APBC_UART9_CLK_RST,	BIT(2),	0),
+	[RESET_APBC_UART10]	= RESET_DATA(APBC_UART10_CLK_RST,	BIT(2),	0),
+	[RESET_APBC_GPIO]	= RESET_DATA(APBC_GPIO_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM0]	= RESET_DATA(APBC_PWM0_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM1]	= RESET_DATA(APBC_PWM1_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM2]	= RESET_DATA(APBC_PWM2_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM3]	= RESET_DATA(APBC_PWM3_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM4]	= RESET_DATA(APBC_PWM4_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM5]	= RESET_DATA(APBC_PWM5_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM6]	= RESET_DATA(APBC_PWM6_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM7]	= RESET_DATA(APBC_PWM7_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM8]	= RESET_DATA(APBC_PWM8_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM9]	= RESET_DATA(APBC_PWM9_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_PWM10]	= RESET_DATA(APBC_PWM10_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_PWM11]	= RESET_DATA(APBC_PWM11_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_PWM12]	= RESET_DATA(APBC_PWM12_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_PWM13]	= RESET_DATA(APBC_PWM13_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_PWM14]	= RESET_DATA(APBC_PWM14_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_PWM15]	= RESET_DATA(APBC_PWM15_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_PWM16]	= RESET_DATA(APBC_PWM16_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_PWM17]	= RESET_DATA(APBC_PWM17_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_PWM18]	= RESET_DATA(APBC_PWM18_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_PWM19]	= RESET_DATA(APBC_PWM19_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_SPI0]	= RESET_DATA(APBC_SSP0_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_SPI1]	= RESET_DATA(APBC_SSP1_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_SPI3]	= RESET_DATA(APBC_SSP3_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_RTC]	= RESET_DATA(APBC_RTC_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_TWSI0]	= RESET_DATA(APBC_TWSI0_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TWSI1]	= RESET_DATA(APBC_TWSI1_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TWSI2]	= RESET_DATA(APBC_TWSI2_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TWSI4]	= RESET_DATA(APBC_TWSI4_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TWSI5]	= RESET_DATA(APBC_TWSI5_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TWSI6]	= RESET_DATA(APBC_TWSI6_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TWSI8]	= RESET_DATA(APBC_TWSI8_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TIMERS0]	= RESET_DATA(APBC_TIMERS0_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TIMERS1]	= RESET_DATA(APBC_TIMERS1_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TIMERS2]	= RESET_DATA(APBC_TIMERS2_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TIMERS3]	= RESET_DATA(APBC_TIMERS3_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TIMERS4]	= RESET_DATA(APBC_TIMERS4_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TIMERS5]	= RESET_DATA(APBC_TIMERS5_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TIMERS6]	= RESET_DATA(APBC_TIMERS6_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_TIMERS7]	= RESET_DATA(APBC_TIMERS7_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_AIB]	= RESET_DATA(APBC_AIB_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_ONEWIRE]	= RESET_DATA(APBC_ONEWIRE_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_I2S0]	= RESET_DATA(APBC_SSPA0_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_I2S1]	= RESET_DATA(APBC_SSPA1_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_I2S2]	= RESET_DATA(APBC_SSPA2_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_I2S3]	= RESET_DATA(APBC_SSPA3_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_I2S4]	= RESET_DATA(APBC_SSPA4_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_I2S5]	= RESET_DATA(APBC_SSPA5_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_DRO]	= RESET_DATA(APBC_DRO_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_IR0]	= RESET_DATA(APBC_IR0_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_IR1]	= RESET_DATA(APBC_IR1_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_TSEN]	= RESET_DATA(APBC_TSEN_CLK_RST,		BIT(2), 0),
+	[RESET_IPC_AP2AUD]	= RESET_DATA(APBC_IPC_AP2AUD_CLK_RST,	BIT(2), 0),
+	[RESET_APBC_CAN0]	= RESET_DATA(APBC_CAN0_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_CAN1]	= RESET_DATA(APBC_CAN1_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_CAN2]	= RESET_DATA(APBC_CAN2_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_CAN3]	= RESET_DATA(APBC_CAN3_CLK_RST,		BIT(2), 0),
+	[RESET_APBC_CAN4]	= RESET_DATA(APBC_CAN4_CLK_RST,		BIT(2), 0),
+};
+
+static const struct spacemit_reset_data k3_apmu_resets[] = {
+	[RESET_APMU_CSI]                = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0,       BIT(1)),
+	[RESET_APMU_CCIC2PHY]           = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0,       BIT(2)),
+	[RESET_APMU_CCIC3PHY]           = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0,       BIT(29)),
+	[RESET_APMU_ISP_CIBUS]          = RESET_DATA(APMU_ISP_CLK_RES_CTRL,       0,       BIT(16)),
+	[RESET_APMU_DSI_ESC]            = RESET_DATA(APMU_LCD_CLK_RES_CTRL1,      0,       BIT(3)),
+	[RESET_APMU_LCD]                = RESET_DATA(APMU_LCD_CLK_RES_CTRL1,      0,       BIT(4)),
+	[RESET_APMU_V2D]                = RESET_DATA(APMU_LCD_CLK_RES_CTRL1,      0,       BIT(27)),
+	[RESET_APMU_LCD_MCLK]           = RESET_DATA(APMU_LCD_CLK_RES_CTRL2,      0,       BIT(9)),
+	[RESET_APMU_LCD_DSCCLK]         = RESET_DATA(APMU_LCD_CLK_RES_CTRL2,      0,       BIT(15)),
+	[RESET_APMU_SC2_HCLK]           = RESET_DATA(APMU_CCIC_CLK_RES_CTRL,      0,       BIT(0)),
+	[RESET_APMU_CCIC_4X]            = RESET_DATA(APMU_CCIC_CLK_RES_CTRL,      0,       BIT(1)),
+	[RESET_APMU_CCIC1_PHY]          = RESET_DATA(APMU_CCIC_CLK_RES_CTRL,      0,       BIT(2)),
+	[RESET_APMU_SDH_AXI]            = RESET_DATA(APMU_SDH0_CLK_RES_CTRL,      0,       BIT(0)),
+	[RESET_APMU_SDH0]               = RESET_DATA(APMU_SDH0_CLK_RES_CTRL,      0,       BIT(1)),
+	[RESET_APMU_SDH1]               = RESET_DATA(APMU_SDH1_CLK_RES_CTRL,      0,       BIT(1)),
+	[RESET_APMU_SDH2]               = RESET_DATA(APMU_SDH2_CLK_RES_CTRL,      0,       BIT(1)),
+	[RESET_APMU_USB2_AHB]           = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(0)),
+	[RESET_APMU_USB2_VCC]           = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(2)),
+	[RESET_APMU_USB2_PHY]           = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(3)),
+	[RESET_APMU_USB3_A_AHB]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(5)),
+	[RESET_APMU_USB3_A_VCC]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(6)),
+	[RESET_APMU_USB3_A_PHY]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(7)),
+	[RESET_APMU_USB3_B_AHB]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(9)),
+	[RESET_APMU_USB3_B_VCC]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(10)),
+	[RESET_APMU_USB3_B_PHY]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(11)),
+	[RESET_APMU_USB3_C_AHB]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(13)),
+	[RESET_APMU_USB3_C_VCC]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(14)),
+	[RESET_APMU_USB3_C_PHY]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(15)),
+	[RESET_APMU_USB3_D_AHB]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(17)),
+	[RESET_APMU_USB3_D_VCC]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(18)),
+	[RESET_APMU_USB3_D_PHY]         = RESET_DATA(APMU_USB_CLK_RES_CTRL,       0,       BIT(19)),
+	[RESET_APMU_QSPI]               = RESET_DATA(APMU_QSPI_CLK_RES_CTRL,      0,       BIT(1)),
+	[RESET_APMU_QSPI_BUS]           = RESET_DATA(APMU_QSPI_CLK_RES_CTRL,      0,       BIT(0)),
+	[RESET_APMU_DMA]                = RESET_DATA(APMU_DMA_CLK_RES_CTRL,       0,       BIT(0)),
+	[RESET_APMU_AES_WTM]            = RESET_DATA(APMU_AES_CLK_RES_CTRL,       0,       BIT(4)),
+	[RESET_APMU_MCB_DCLK]           = RESET_DATA(APMU_MCB_CLK_RES_CTRL,       0,       BIT(0)),
+	[RESET_APMU_MCB_ACLK]           = RESET_DATA(APMU_MCB_CLK_RES_CTRL,       0,       BIT(1)),
+	[RESET_APMU_VPU]                = RESET_DATA(APMU_VPU_CLK_RES_CTRL,       0,       BIT(0)),
+	[RESET_APMU_DTC]                = RESET_DATA(APMU_DTC_CLK_RES_CTRL,       0,       BIT(0)),
+	[RESET_APMU_GPU]                = RESET_DATA(APMU_GPU_CLK_RES_CTRL,       0,       BIT(1)),
+	[RESET_APMU_MC]                 = RESET_DATA(APMU_PMUA_MC_CTRL,           0,       BIT(0)),
+	[RESET_APMU_CPU0_POP]           = RESET_DATA(APMU_PMU_CC2_AP,             BIT(0),  0),
+	[RESET_APMU_CPU0_SW]            = RESET_DATA(APMU_PMU_CC2_AP,             BIT(1),  0),
+	[RESET_APMU_CPU1_POP]           = RESET_DATA(APMU_PMU_CC2_AP,             BIT(3),  0),
+	[RESET_APMU_CPU1_SW]            = RESET_DATA(APMU_PMU_CC2_AP,             BIT(4),  0),
+	[RESET_APMU_CPU2_POP]           = RESET_DATA(APMU_PMU_CC2_AP,             BIT(6),  0),
+	[RESET_APMU_CPU2_SW]            = RESET_DATA(APMU_PMU_CC2_AP,             BIT(7),  0),
+	[RESET_APMU_CPU3_POP]           = RESET_DATA(APMU_PMU_CC2_AP,             BIT(9),  0),
+	[RESET_APMU_CPU3_SW]            = RESET_DATA(APMU_PMU_CC2_AP,             BIT(10), 0),
+	[RESET_APMU_C0_MPSUB_SW]        = RESET_DATA(APMU_PMU_CC2_AP,             BIT(12), 0),
+	[RESET_APMU_CPU4_POP]           = RESET_DATA(APMU_PMU_CC2_AP,             BIT(16), 0),
+	[RESET_APMU_CPU4_SW]            = RESET_DATA(APMU_PMU_CC2_AP,             BIT(17), 0),
+	[RESET_APMU_CPU5_POP]           = RESET_DATA(APMU_PMU_CC2_AP,             BIT(19), 0),
+	[RESET_APMU_CPU5_SW]            = RESET_DATA(APMU_PMU_CC2_AP,             BIT(20), 0),
+	[RESET_APMU_CPU6_POP]           = RESET_DATA(APMU_PMU_CC2_AP,             BIT(22), 0),
+	[RESET_APMU_CPU6_SW]            = RESET_DATA(APMU_PMU_CC2_AP,             BIT(23), 0),
+	[RESET_APMU_CPU7_POP]           = RESET_DATA(APMU_PMU_CC2_AP,             BIT(25), 0),
+	[RESET_APMU_CPU7_SW]            = RESET_DATA(APMU_PMU_CC2_AP,             BIT(26), 0),
+	[RESET_APMU_C1_MPSUB_SW]        = RESET_DATA(APMU_PMU_CC2_AP,             BIT(28), 0),
+	[RESET_APMU_MPSUB_DBG]          = RESET_DATA(APMU_PMU_CC2_AP,             BIT(29), 0),
+	[RESET_APMU_UCIE_IP]            = RESET_DATA(APMU_UCIE_CTRL,              BIT(1),  0),
+	[RESET_APMU_UCIE_HOT]           = RESET_DATA(APMU_UCIE_CTRL,              BIT(2),  0),
+	[RESET_APMU_UCIE_MON]           = RESET_DATA(APMU_UCIE_CTRL,              BIT(3),  0),
+	[RESET_APMU_RCPU_AUDIO_SYS]     = RESET_DATA(APMU_RCPU_CLK_RES_CTRL,      0,       BIT(0)),
+	[RESET_APMU_RCPU_MCU_CORE]      = RESET_DATA(APMU_RCPU_CLK_RES_CTRL,      0,       BIT(2)),
+	[RESET_APMU_RCPU_AUDIO_APMU]    = RESET_DATA(APMU_RCPU_CLK_RES_CTRL,      0,       BIT(3)),
+	[RESET_APMU_DSI4LN2_ESCCLK]     = RESET_DATA(APMU_LCD_CLK_RES_CTRL3,      0,       BIT(3)),
+	[RESET_APMU_DSI4LN2_LCD_SW]     = RESET_DATA(APMU_LCD_CLK_RES_CTRL3,      0,       BIT(4)),
+	[RESET_APMU_DSI4LN2_LCD_MCLK]   = RESET_DATA(APMU_LCD_CLK_RES_CTRL4,      0,       BIT(9)),
+	[RESET_APMU_DSI4LN2_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4,      0,       BIT(15)),
+	[RESET_APMU_DSI4LN2_DPU_ACLK]   = RESET_DATA(APMU_LCD_CLK_RES_CTRL5,      0,       BIT(0)),
+	[RESET_APMU_DPU_ACLK]           = RESET_DATA(APMU_LCD_CLK_RES_CTRL5,      0,       BIT(15)),
+	[RESET_APMU_UFS_ACLK]           = RESET_DATA(APMU_UFS_CLK_RES_CTRL,       0,       BIT(0)),
+	[RESET_APMU_EDP0]               = RESET_DATA(APMU_LCD_EDP_CTRL,           0,       BIT(0)),
+	[RESET_APMU_EDP1]               = RESET_DATA(APMU_LCD_EDP_CTRL,           0,       BIT(16)),
+	[RESET_APMU_PCIE_A_DBI]         = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,    0,       BIT(3)),
+	[RESET_APMU_PCIE_A_SLAVE]       = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,    0,       BIT(4)),
+	[RESET_APMU_PCIE_A_MASTER]      = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,    0,       BIT(5)),
+	[RESET_APMU_PCIE_B_DBI]         = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,    0,       BIT(3)),
+	[RESET_APMU_PCIE_B_SLAVE]       = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,    0,       BIT(4)),
+	[RESET_APMU_PCIE_B_MASTER]      = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,    0,       BIT(5)),
+	[RESET_APMU_PCIE_C_DBI]         = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,    0,       BIT(3)),
+	[RESET_APMU_PCIE_C_SLAVE]       = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,    0,       BIT(4)),
+	[RESET_APMU_PCIE_C_MASTER]      = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,    0,       BIT(5)),
+	[RESET_APMU_PCIE_D_DBI]         = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,    0,       BIT(3)),
+	[RESET_APMU_PCIE_D_SLAVE]       = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,    0,       BIT(4)),
+	[RESET_APMU_PCIE_D_MASTER]      = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,    0,       BIT(5)),
+	[RESET_APMU_PCIE_E_DBI]         = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,    0,       BIT(3)),
+	[RESET_APMU_PCIE_E_SLAVE]       = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,    0,       BIT(4)),
+	[RESET_APMU_PCIE_E_MASTER]      = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,    0,       BIT(5)),
+	[RESET_APMU_EMAC0]              = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL,     0,       BIT(1)),
+	[RESET_APMU_EMAC1]              = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL,     0,       BIT(1)),
+	[RESET_APMU_EMAC2]              = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL,     0,       BIT(1)),
+	[RESET_APMU_ESPI_MCLK]          = RESET_DATA(APMU_ESPI_CLK_RES_CTRL,      0,       BIT(0)),
+	[RESET_APMU_ESPI_SCLK]          = RESET_DATA(APMU_ESPI_CLK_RES_CTRL,      0,       BIT(2)),
+};
+
+static const struct spacemit_reset_data k3_dciu_resets[] = {
+	[RESET_DCIU_HDMA]	= RESET_DATA(DCIU_DMASYS_RSTN,		0, BIT(0)),
+	[RESET_DCIU_DMA350]	= RESET_DATA(DCIU_DMASYS_SDMA_RSTN,	0, BIT(0)),
+	[RESET_DCIU_DMA350_0]	= RESET_DATA(DCIU_DMASYS_S0_RSTN,	0, BIT(0)),
+	[RESET_DCIU_DMA350_1]	= RESET_DATA(DCIU_DMASYS_S1_RSTN,	0, BIT(0)),
+	[RESET_DCIU_AXIDMA0]	= RESET_DATA(DCIU_DMASYS_A0_RSTN,	0, BIT(0)),
+	[RESET_DCIU_AXIDMA1]	= RESET_DATA(DCIU_DMASYS_A1_RSTN,	0, BIT(0)),
+	[RESET_DCIU_AXIDMA2]	= RESET_DATA(DCIU_DMASYS_A2_RSTN,	0, BIT(0)),
+	[RESET_DCIU_AXIDMA3]	= RESET_DATA(DCIU_DMASYS_A3_RSTN,	0, BIT(0)),
+	[RESET_DCIU_AXIDMA4]	= RESET_DATA(DCIU_DMASYS_A4_RSTN,	0, BIT(0)),
+	[RESET_DCIU_AXIDMA5]	= RESET_DATA(DCIU_DMASYS_A5_RSTN,	0, BIT(0)),
+	[RESET_DCIU_AXIDMA6]	= RESET_DATA(DCIU_DMASYS_A6_RSTN,	0, BIT(0)),
+	[RESET_DCIU_AXIDMA7]	= RESET_DATA(DCIU_DMASYS_A7_RSTN,	0, BIT(0)),
+};
+
+U_BOOT_DRIVER(spacemit_k3_reset) = {
+	.name		= "spacemit_k3_reset",
+	.id		= UCLASS_RESET,
+	.ops		= &spacemit_reset_ops,
+	.probe		= spacemit_reset_probe,
+	.priv_auto	= sizeof(struct spacemit_reset_priv),
+	.flags		= DM_FLAG_PRE_RELOC,
+};
+
+int spacemit_k3_reset_bind(struct udevice *parent,
+			   enum spacemit_k3_reset_syscon syscon)
+{
+	const struct spacemit_reset_data *table;
+	size_t table_size;
+
+	switch (syscon) {
+	case SPACEMIT_K3_RESET_MPMU:
+		table = k3_mpmu_resets;
+		table_size = ARRAY_SIZE(k3_mpmu_resets);
+		break;
+	case SPACEMIT_K3_RESET_APBC:
+		table = k3_apbc_resets;
+		table_size = ARRAY_SIZE(k3_apbc_resets);
+		break;
+	case SPACEMIT_K3_RESET_APMU:
+		table = k3_apmu_resets;
+		table_size = ARRAY_SIZE(k3_apmu_resets);
+		break;
+	case SPACEMIT_K3_RESET_DCIU:
+		table = k3_dciu_resets;
+		table_size = ARRAY_SIZE(k3_dciu_resets);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return spacemit_reset_bind(parent, "spacemit_k3_reset", table, table_size);
+}
diff --git a/include/soc/spacemit/k3-reset.h b/include/soc/spacemit/k3-reset.h
new file mode 100644
index 00000000000..e2ae12e2edc
--- /dev/null
+++ b/include/soc/spacemit/k3-reset.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * SpacemiT K3 reset driver — header interface.
+ */
+
+#ifndef _SOC_SPACEMIT_K3_RESET_H
+#define _SOC_SPACEMIT_K3_RESET_H
+
+struct udevice;
+
+enum spacemit_k3_reset_syscon {
+	SPACEMIT_K3_RESET_MPMU,
+	SPACEMIT_K3_RESET_APBC,
+	SPACEMIT_K3_RESET_APMU,
+	SPACEMIT_K3_RESET_DCIU,
+};
+
+int spacemit_k3_reset_bind(struct udevice *parent,
+			   enum spacemit_k3_reset_syscon syscon);
+
+#endif /* _SOC_SPACEMIT_K3_RESET_H */

-- 
2.55.0